MC10E446 D

MC10E446 D
MC10E446, MC100E446
5VECL 4-Bit Parallel/Serial
Converter
Description
The MC10E/100E446 is an integrated 4-bit parallel to serial data
converter. The device is designed to operate for NRZ data rates of up to
1.3 Gb/s. The chip generates a divide by 4 and a divide by 8 clock for
both 4-bit conversion and a two chip 8-bit conversion function. The
conversion sequence was chosen to convert the parallel data into a serial
stream from bit D0 to D3. A serial input is provided to cascade two
E446 devices for 8 bit conversion applications. Note that the serial
output data clocks off of the negative input clock transition.
The SYNC input will asynchronously reset the internal clock
circuitry. This pin allows the user to reset the internal clock conversion
unit and thus select the start of the conversion process.
The MODE input is used to select the conversion mode of the device.
With the MODE input LOW, or open, the device will function as a 4-bit
converter. When the mode input is driven HIGH the internal load clock
will change on every eighth clock cycle thus allowing for an 8-bit
conversion scheme using two E446’s. When cascaded in an 8-bit
conversion scheme the devices will not operate at the 1.3 Gb/s data rate
of a single device. Refer to the applications section of this data sheet for
more information on cascading the E446.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB and
VCC via a 0.01 mF capacitor and limit current sourcing or sinking to
0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
Features
•
•
•
•
•
•
•
•
•
•
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PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1 28
MCxxxE446FNG
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
On Chip Clock ÷4 and ÷8
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
1.5 Gb/s Typical Data Rate Capability
Differential Clock and Serial Inputs
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC
VBB Output for Single-ended Input Applications
Asynchronous Data Synchronization
Mode Select to Expand to 8 Bits
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
Internal Input 50 kW Pulldown Resistors
ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 100 V
•
•
•
•
Latchup Test
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 525 devices
Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
For Additional Information, see Application Note
AND8003/D
Pb−Free Packages are Available*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 8
1
Publication Order Number:
MC10E446/D
MC10E446, MC100E446
D0
D1
D2
D3 MODE NC
NC
25
24
23
22
19
18
NC
21
20
Table 1. PIN DESCRIPTION
CLK
26
CLK
27
17
NC
VBB
28
16
VCC
VEE
1
15
SOUT
SIN
2
14
SOUT
SIN
3
13
VCCO
SYNC
4
12
NC
MC10E446/MC100E446
5
6
7
8
9
10
PIN
SIN
D0 − D3
SOUT, SOUT
CLK, CLK
CL/4, CL/4
CL/8, CL/8
MODE
SYNC
VBB
VCC, VCCO
VEE
NC
11
VCCO CL/8 CL/8 VCCO CL/4 CL/4 VCCO
* All VCC and VCCO pins are tied together on the die.
Warning: All VCC, VCCO, and VEE pins must be externally
connected to Power Supply to guarantee proper operation.
Figure 1. Pinout: PLCC−28 (Top View)
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2
FUNCTION
ECL Differential Serial Data Input
ECL Parallel Data Inputs
ECL Differential Serial Data Output
ECL Differential Clock Inputs
ECL Differential ÷4 Clock Output
ECL Differential ÷8 Clock Output
Conversion Mode 4-Bit/8-Bit
ECL Conversion Synchronizing Input
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
MC10E446, MC100E446
SIN
0
SIN
D
Q
1
D3
CLK
VEE
0
D
Q
1
D2
CLK
VEE
0
D
Q
1
D1
CLK
VEE
0
D
SOUT
Q
SOUT
1
D0
CLK
VEE
LOAD
PULSE
GENERATOR
Mode
VEE
0
CL/8
1
CL/8
CLK
CLK
Delay
P4
P8
R
R
CL/4
SYNC
VEE
CL/4
Figure 2. Logic Diagram
Table 2. FUNCTION TABLES
Mode
Conversion
L
H
4-Bit
8-Bit
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3
MC10E446, MC100E446
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
VCC
PECL Mode Power Supply
VEE = 0 V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
Iout
Output Current
Continuous
Surge
IBB
VBB Sink/Source
TA
Operating Temperature Range
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
Tsol
Wave Solder
Pb
Pb−Free
Condition 2
VI v VCC
VI w VEE
Rating
Unit
8
V
6
−6
V
V
50
100
mA
mA
± 0.5
mA
0 to +85
°C
−65 to +150
°C
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
PLCC−28
22 to 26
°C/W
265
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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4
MC10E446, MC100E446
Table 4. 10E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 1)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
126
151
4070
4160
4020
4210
4020
85°C
Typ
Max
Min
126
151
4105
4190
4090
4240
4090
Typ
Max
Unit
126
151
mA
4185
4280
mV
4330
mV
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
3980
VOHSOUT
Output HIGH Voltage
3980
VOL
Output LOW Voltage (Note 2)
3050
3210
3370
3050
3210
3370
3050
3227
3405
mV
VIH
Input HIGH Voltage
3830
3995
4160
3870
4030
4190
3940
4110
4280
mV
VIL
Input LOW Voltage
3050
3285
3520
3050
3285
3520
3050
3302
3555
mV
VBB
Output Voltage Reference
3.62
3.74
3.65
3.75
3.69
3.81
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
SOUT/SOUT
150
0.5
0.3
150
0.5
0.25
0.3
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 5. 10E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 3)
0°C
Typ
Max
126
151
−930
−840
−980
−790
−980
−1790
−1630
−1950
−1170
−1005
−840
Input LOW Voltage
−1950
−1715
VBB
Output Voltage Reference
−1.38
IIH
Input HIGH Current
IIL
Input LOW Current
Symbol
Characteristic
Min
25°C
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
−1020
VOHSOUT
Output HIGH Voltage
−1020
VOL
Output LOW Voltage (Note 4)
−1950
VIH
Input HIGH Voltage
VIL
SOUT/SOUT
Min
Typ
Max
126
151
−895
−810
−910
−760
−910
−1790
−1630
−1950
−1130
−970
−810
−1480
−1950
−1715
−1.27
−1.35
150
0.5
85°C
0.3
Min
Typ
Max
Unit
126
151
mA
−815
−720
mV
−670
mV
−1773
−1595
mV
−1060
−890
−720
mV
−1480
−1950
−1698
−1445
mV
−1.25
−1.31
150
0.5
0.065
0.3
0.2
−1.19
V
150
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.06 V.
4. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
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MC10E446, MC100E446
Table 6. 100E SERIES PECL DC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V (Note 5)
0°C
Symbol
Characteristic
Min
25°C
Typ
Max
Min
126
151
4050
4120
3975
4170
3975
85°C
Typ
Max
Min
126
151
4050
4120
3975
4170
3975
Typ
Max
Unit
145
174
mA
4050
4120
mV
4170
mV
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 6)
3975
VOHSOUT
Output HIGH Voltage
3975
VOL
Output LOW Voltage (Note 6)
3190
3295
3380
3190
3255
3380
3190
3260
3380
mV
VIH
Input HIGH Voltage
3835
3975
4120
3835
3975
4120
3835
3975
4120
mV
VIL
Input LOW Voltage
3190
3355
3525
3190
3355
3525
3190
3355
3525
mV
VBB
Output Voltage Reference
3.62
3.73
3.62
3.74
3.62
3.74
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
SOUT/SOUT
150
0.5
0.3
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
6. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 7. 100E SERIES NECL DC CHARACTERISTICS VCCx = 0.0 V; VEE = −5.0 V (Note 7)
0°C
Symbol
Characteristic
Min
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 8)
−1025
VOHSOUT
Output HIGH Voltage
−1025
VOL
Output LOW Voltage (Note 8)
VIH
VIL
SOUT/SOUT
25°C
Typ
Max
Min
126
151
−950
−880
−1025
−830
−1025
−1620
−1810
−1745
85°C
Typ
Max
Min
Typ
Max
Unit
126
151
145
174
mA
−950
−880
−1025
−950
−880
mV
−830
−1025
−830
mV
−1620
−1810
−1740
−1620
mV
−1810
−1705
Input HIGH Voltage
−1165
−1025
−880
−1165
−1025
−880
−1165
−1025
−880
mV
Input LOW Voltage
−1810
−1645
−1475
−1810
−1645
−1475
−1810
−1645
−1475
mV
VBB
Output Voltage Reference
−1.38
−1.27
−1.38
−1.26
−1.38
−1.26
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
0.3
150
0.5
0.25
0.5
0.2
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V.
8. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
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6
MC10E446, MC100E446
Table 8. AC CHARACTERISTICS VCCx = 5.0 V; VEE = 0.0 V or VCCx = 0.0 V; VEE = −5.0 V (Note 9)
0°C
Symbol
Characteristic
Min
Typ
1.3
1.6
25°C
Max
Min
Typ
1.3
1.6
1020
650
800
650
1200
850
1050
850
85°C
Max
Min
Typ
1.3
1.6
1020
650
800
650
1200
850
1050
850
Max
Unit
FMAX
Max Conversion Frequency
tPLH
tPHL
Propagation Delay to Output
CLK to SOUT (Note 10)
CLK to CL/4
CLK to CL/8
SYNC to CL/4, CL/8
1020
650
800
650
1200
850
1050
850
ts
Setup Time (Note 11)
SIN, Dn
-200
-450
-200
−450
−200
−450
ps
th
Hold Time (Note 11)
SIN, Dn
900
650
900
650
900
650
ps
tRR
Reset Recovery Time
SYNC
500
300
500
300
500
300
ps
tPW
Min Pulse Width
CLK, MR
300
tJITTER
Random Clock Jitter (RMS)
VPP
Input Voltage Swing (Differential Configuration)
150
tr
tf
Rise/Fall Times (20% - 80%)
Other
100
200
1480
1050
1300
1100
300
<1
SOUT
1480
1050
1300
1100
150
350
650
100
200
225
425
1480
1050
1300
1100
300
<1
1000
Gb/s
NRZ
225
425
ps
<1
1000
150
350
650
100
200
ps
225
425
ps
1000
mV
350
650
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. 10 Series: VEE can vary −0.46 V / +0.06 V.
100 Series: VEE can vary −0.46 V / +0.8 V.
10. Propagation delays measured from negative going clock edge.
11. Relative to negative clock edge.
CLK
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
D
Setup
Valid Data
ts
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
Hold
SYNC
t rr
th
CLK
Figure 3.
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MC10E446, MC100E446
CLK
RESET
D0
D0−1
D0−2
D1
D1−1
D1−2
D2
D2−1
D2−2
D3
D3−1
D3−2
SOUT
D0−1
D1−1
D2−1
D3−1
D0−2
D1−2
D2−2
D3−2
D5−1
D6−1
D7−1
CL/4
CL/8
Timing Diagram A. 4:1 Parallel to Serial Conversion
CLK
RESET
D0
D0−1
D0−2
D1
D1−1
D1−2
D2
D2−1
D2−2
D3
D3−1
D3−2
D4 (D0B)
D4−1
D4−2
D5 (D1B)
D5−1
D5−2
D6 (D2B)
D6−1
D6−2
D7 (D3B)
D7−1
D7−2
SOUT
D0−1
D1−1
D2−1
D3−1
D4−1
CL/4
CL/8
Timing Diagram B. 8:1 Parallel to Serial Conversion
Figure 4. Timing Diagrams
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D0−2
MC10E446, MC100E446
Applications Information
delaying the clock feeding E446A relative to the clock of
E446B the frequency of operation can be increased.
The MC10E/100E446 is an integrated 4:1 parallel to serial
converter. The chip is designed to work with the E445 device
to provide both transmission and receiving of a high speed
serial data path. The E446 can convert 4 bits of data into a
1.3 Gb/s NRZ data stream. The device features a SYNC
input which allows the user to reset the internal clock
circuitry and restart the conversion sequence
(see timing diagram A).
The E446 features a differential serial input and internal
divide by 8 circuitry to facilitate the cascading of two
devices to build a 8:1 multiplexer. Figure 1 illustrates the
architecture for a 8:1 multiplexer using two E446’s; the
timing diagram for this configuration can be found on the
following page. Notice the serial outputs (SOUT) of the
higher order converter feed the serial inputs of the the lower
order device. This feed through of the serial inputs bounds
the upper end of the frequency of operation. The clock to
serial output propagation delay plus the setup time of the
serial input pins must fit into a single clock period for the
cascade architecture to function properly. Using the worst
case values for these two parameters from the data sheet,
TPD CLK to SOUT = 1480 ps and tS for SIN = −200 ps,
yields a minimum period of 1280 ps or a clock frequency of
780 MHz.
The clock frequency is somewhat lower than that of a
single converter, to increase this frequency some games can
be played with the clock input of the higher order E446. By
CLK
CLK
E446B
E446A
SOUT
SOUT
MSB
SIN
SIN
Serial
Data
SOUT
SOUT
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0
Q7 Q6 Q5 Q4
Q3 Q2 Q1 Q0
LSB
Parallel Data
1000ps
600ps
CLOCK
Tpd CLK
to SOUT
1000ps
1600ps
Figure 5. Cascaded 8:1 Converter Architecture
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9
MC10E446, MC100E446
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
Package
Shipping †
MC10E446FN
PLCC−28
37 Units / Rail
MC10E446FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC10E446FNR2
PLCC−28
500 / Tape & Reel
MC10E446FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
MC100E446FN
PLCC−28
37 Units / Rail
MC100E446FNG
PLCC−28
(Pb−Free)
37 Units / Rail
MC100E446FNR2
PLCC−28
500 / Tape & Reel
MC100E446FNR2G
PLCC−28
(Pb−Free)
500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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MC10E446, MC100E446
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
B
Y BRK
−N−
0.007 (0.180)
U
T L−M
M
0.007 (0.180)
M
N
S
T L−M
S
S
N
S
D
Z
−M−
−L−
W
28
D
X
V
1
G1
A
0.007 (0.180)
R
0.007 (0.180)
C
M
M
T L−M
T L−M
S
S
N
S
N
S
H
0.007 (0.180)
N
S
S
G
J
0.004 (0.100)
−T− SEATING
T L−M
S
N
T L−M
S
N
S
K
PLANE
F
VIEW S
G1
M
K1
E
S
T L−M
S
VIEW D−D
Z
0.010 (0.250)
0.010 (0.250)
VIEW S
S
NOTES:
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
INCHES
MIN
MAX
0.485
0.495
0.485
0.495
0.165
0.180
0.090
0.110
0.013
0.019
0.050 BSC
0.026
0.032
0.020
−−−
0.025
−−−
0.450
0.456
0.450
0.456
0.042
0.048
0.042
0.048
0.042
0.056
−−− 0.020
2_
10_
0.410
0.430
0.040
−−−
http://onsemi.com
11
MILLIMETERS
MIN
MAX
12.32
12.57
12.32
12.57
4.20
4.57
2.29
2.79
0.33
0.48
1.27 BSC
0.66
0.81
0.51
−−−
0.64
−−−
11.43
11.58
11.43
11.58
1.07
1.21
1.07
1.21
1.07
1.42
−−−
0.50
2_
10_
10.42
10.92
1.02
−−−
0.007 (0.180)
M
T L−M
S
N
S
MC10E446, MC100E446
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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ON Semiconductor Website: www.onsemi.com
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For additional information, please contact your local
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MC10E446/D
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