Two-Wire Serial EEPROM 512K (8-bit wide) FEATURES

Two-Wire Serial EEPROM  512K (8-bit wide) FEATURES
Fremont Micro Devices
FT24C512A
Two-Wire Serial EEPROM
512K (8-bit wide)
FEATURES
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Low voltage and low power operations:
 FT24C512A:
VCC = 1.8V to 5.5V
Maximum Standby current < 1µA (typically 0.02µA and 0.06µA @ 1.8V and 5.5V respectively).
128 bytes page write mode.
Partial page write operation allowed.
Internally organized: 65,536×8 (512K).
Standard 2-wire bi-directional serial interface.
Schmitt trigger, filtered inputs for noise protection.
Self-timed write cycle (5ms maximum).
1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) compatibility.
Automatic erase before write operation.
Write protect pin for hardware data protection.
High reliability: typically 1,000,000 cycles endurance.
100 years data retention.
Industrial temperature range (-40o C to 85o C).
Standard 8-pin DIP/SOP/WSOP/MSOP/TSSOP Pb-free packages.
DESCRIPTION
The FT24C512A series are 524,288 bits of serial Electrical Erasable and Programmable Read Only
Memory, commonly known as EEPROM. They are organized as 65,536 words of 8 bits (one byte) each.
The devices are fabricated with proprietary advanced CMOS process for low power and low voltage
applications. These devices are available in standard 8-lead DIP, 8-lead SOP/WSOP/MSOP and 8-lead
TSSOP packages. A standard 2-wire serial interface is used to address all read and write functions. Our
extended VCC range (1.8V to 5.5V) devices enables wide spectrum of applications.
PIN CONFIGURATION
Pin Name
Pin Function
A2, A1, A0
Device Address Inputs
SDA
Serial Data Input / Open Drain Output
SCL
Serial Clock Input
WP
Write Protect
NC
No-Connect
Table 1
© 2009 Fremont Micro Devices Inc.
DS3009E-page1
FT24C512A
All three packaging types come in Pb-free certified.
FT24C512A
A0
A1
A2
1
8
2
7
3
6
GND
4
5
8L
8L
8L
8L
8L
VCC
WP
SCL
SDA
DIP
SOP
WSOP
MSOP
TSSOP
Figure 1: Package Type
ABSOLUTE MAXIMUM RATINGS
Industrial operating temperature:
Storage temperature:
Input voltage on any pin relative to ground:
Maximum voltage:
ESD Protection on all pins:
-40oC to 85oC
-50oC to 125oC
-0.3V to VCC + 0.3V
8V
>2000V
* Stresses exceed those listed under “Absolute Maximum Rating” may cause permanent damage to the device.
Functional operation of the device at conditions beyond those listed in the specification is not guaranteed.
Prolonged exposure to extreme conditions may affect device reliability or functionality.
Figure 2: Block Diagram
DS3009E-page2
© 2009 Fremont Micro Devices Inc.
FT24C512A
PIN DESCRIPTIONS
(A) SERIAL CLOCK (SCL)
The rising edge of this SCL input is to latch data into the EEPROM device while the falling edge of
this clock is to clock data out of the EEPROM device.
(B) DEVICE / CHIP SELECT ADDRESSES (A2, A1, A0)
These are the chip select input signals for the serial EEPROM devices. Typically, these signals are
hardwired to either VIH or VIL. If left unconnected, they are internally recognized as VIL.
(C) SERIAL DATA LINE (SDA)
SDA data line is a bi-directional signal for the serial devices. It is an open drain output signal and can
be wired-OR with other open-drain output devices.
(D) WRITE PROTECT (WP)
The FT24C512A device has a WP pin to protect the whole EEPROM array from programming.
Programming operations are allowed if WP pin is left un-connected or input to VIL. Conversely all
programming functions are disabled if WP pin is connected to VIH or VCC. Read operations is not
affected by the WP pin’s input level.
MEMORY ORGANIZATION
The FT24C512A devices have 512 pages respectively. Since each page has 128 bytes, random word
addressing to FT24C512A will require 16 bits data word addresses.
DEVICE OPERATION
(A) SERIAL CLOCK AND DATA TRANSITIONS
The SDA pin is typically pulled to high by an external resistor. Data is allowed to change only when
Serial clock SCL is at VIL. Any SDA signal transition may interpret as either a START or STOP
condition as described below.
(B) START CONDITION
With SCL ≥VIH, a SDA transition from high to low is interpreted as a START condition. All valid
commands must begin with a START condition.
(C) STOP CONDITION
With SCL ≥ VIH, a SDA transition from low to high is interpreted as a STOP condition. All valid read
or write commands end with a STOP condition. The device goes into the STANDBY mode if it is after
a read command. A STOP condition after page or byte write command will trigger the chip into the
STANDBY mode after the self-timed internal programming finish (see Figure 3).
© 2009 Fremont Micro Devices Inc.
DS3009E-page3
FT24C512/A
(D) ACKNOWLEDGE
The 2-wire protocol transmits address and data to and from the EEPROM in 8 bit words. The
EEPROM acknowledges the data or address by outputting a "0" after receiving each word. The
ACKNOWLEDGE signal occurs on the 9th serial clock after each word.
(E) STANDBY MODE
The EEPROM goes into low power STANDBY mode after a fresh power up, after receiving a STOP
bit in read mode, or after completing a self-time internal programming operation.
SCL
SDA
START
Condition
Data
Valid
STOP
Condition
Data
Transition
Figure 3: Timing diagram for START and STOP conditions
START Condition
SCL
Data in
Data out
ACK
Figure 4: Timing diagram for output ACKNOWLEDGE
DS3009E-page4
© 2009 Fremont Micro Devices Inc.
FT24C512A
DEVICE ADDRESSING
The 2-wire serial bus protocol mandates an 8 bits device address word after a START bit condition to
invoke a valid read or write command. The first four most significant bits of the device address must be
1010, which is common to all serial EEPROM devices. The next three bits are device address bits. These
three device address bits (5th, 6th and 7th) are to match with the external chip select/address pin states. If a
match is made, the EEPROM device outputs an ACKNOWLEDGE signal after the 8th read/write bit,
otherwise the chip will go into STANDBY mode. However, matching may not be needed for some or all
device address bits (5th, 6th and 7th) as noted below. The last or 8th bit is a read/write command bit. If the
8th bit is at VIH then the chip goes into read mode. If a “0” is detected, the device enters programming
mode.
WRITE OPERATION
(A)
BYTE WRITE
A write operation requires two 8-bit data word address following the device address word and
ACKNOWLEDGE signal. Upon receipt of this address, the EEPROM will respond with a “0” and then
clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will again
output a “0”. The addressing device, such as a microcontroller, must terminate the write sequence
with a STOP condition. At this time the EEPROM enters into an internally-timed write cycle state. All
inputs are disabled during this write cycle and the EEPROM will not respond until the writing is
completed (figure 5).
(B)
PAGE WRITE
The 512K EEPROM are capable of 128-byte page write.
A page write is initiated the same way as a byte write, but the microcontroller does not send a STOP
condition after the first data word is clocked in. The microcontroller can transmit up to 127 more data
words after the EEPROM acknowledges receipt of the first data word. The EEPROM will respond
with a “0” after each data word is received. The microcontroller must terminate the page write
sequence with a STOP condition (see Figure 6).
The lower 7 bits of the data word address are internally incremented following the receipt of each data
word. The higher data word address bits are not incremented, retaining the memory page row
location. If more than 128 data words are transmitted to the EEPROM, the data word address will
“roll over” and the previous data will be overwritten.
(C)
ACKNOWLEDGE POLLING
ACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal
programming. By issuing a valid read or write address command, the EEPROM will not acknowledge
at the 9th clock cycle if the device is still in the self-timed programming mode. However, if the
programming completes and the chip has returned to the STANDBY mode, the device will return a
valid ACKNOWLEDGE signal at the 9th clock cycle.
© 2009 Fremont Micro Devices Inc.
DS3009E-page5
FT24C512/A
READ OPERATIONS
The read command is similar to the write command except the 8th read/write bit in address word is set to
“1”. The three read operation modes are described as follows:
(A)
CURRENT ADDRESS READ
The EEPROM internal address word counter maintains the last read or write address plus one if the
power supply to the device has not been cut off. To initiate a current address read operation, the
micro-controller issues a START bit and a valid device address word with the read/write bit (8th) set to
“1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8bit data word will then be serially clocked out. The internal address word counter will then
automatically increase by one. For current address read the micro-controller will not issue an
ACKNOWLEDGE signal on the 18th clock cycle. The micro-controller issues a valid STOP bit after
the 18th clock cycle to terminate the read operation. The device then returns to STANDBY mode (see
Figure 7).
(B)
SEQUENTIAL READ
The sequential read is very similar to current address read. The micro-controller issues a START bit
and a valid device address word with read/write bit (8th) set to “1”. The EEPROM will response with
an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially
clocked out. Meanwhile the internally address word counter will then automatically increase by one.
Unlike current address read, the micro-controller sends an ACKNOWLEDGE signal on the 18th clock
cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the
ACKNOWLEDGE signal, the EEPROM will serially clocked out an 8-bit data word based on the
incremented internal address counter. If the micro-controller needs another data, it sends out an
ACKNOWLEDGE signal on the 27th clock cycle. Another 8-bit data word will then be serially clocked
out. This sequential read continues as long as the micro-controller sends an ACKNOWLEDGE signal
after receiving a new data word. When the internal address counter reaches its maximum valid
address, it rolls over to the beginning of the memory array address. Similar to current address read,
the micro-controller can terminate the sequential read by not acknowledging the last data word
received, but sending a STOP bit afterwards instead (figure 8).
(C)
RANDOM READ
Random read is a two-steps process. The first step is to initialize the internal address counter with a
target read address using a “dummy write” instruction. The second step is a current address read.
To initialize the internal address counter with a target read address, the micro-controller issues a
START bit first, follows by a valid device address with the read/write bit (8th) set to “0”. The EEPROM
will then acknowledge. The micro-controller will then send two address words. Again the EEPROM
will acknowledge. Instead of sending a valid written data to the EEPROM, the micro-controller
performs a current address read instruction to read the data. Note that once a START bit is issued,
the EEPROM will reset the internal programming process and continue to execute the new instruction
- which is to read the current address (figure 9).
DS3009E-page6
© 2009 Fremont Micro Devices Inc.
FT24C512A
S
T
A
R
T
W
R
I
T
E
DEVICE
ADDRESS
FIRST WORD
ADDRESS
SECOND WORD
ADDRESS
S
T
O
P
DATA
SDA LINE
LRA
S / C
B WK
M
S
B
M
S
B
A
C
K
LA
SC
BK
A
C
K
Figure 5: Byte Write
S
T
A
R
T
W
R
I
T
E
DEVICE
ADDRESS
SECOND WORD
ADDRESS(N)
FIRST WORD
ADDRESS(N)
S
T
O
DATA(N+X) P
DATA(N)
...
SDA LINE
M
S
B
LRA
S / C
B WK
M
S
B
LA
SC
BK
A
C
K
A
C
K
A
C
K
Figure 6: Page Write
S
T
A
R
T
R
E
A
D
DEVICE
ADDRESS
S
T
O
P
DATA
SDA LINE
M
S
B
N
O
LRA
S / C
B WK
A
C
K
Figure 7: Current Address Read
DEVICE
ADDRESS
R
E
A
D
DATA (N+1)
DATA (N)
DATA (N+2)
S
T
O
P
DATA (N+3)
SDA LINE
RA
/ C
WK
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Figure 8: Sequential Read
© 2009 Fremont Micro Devices Inc.
DS3009E-page7
FT24C512/A
S
T
A
R
T
W
R
I
T
E
DEVICE
ADDRESS
FIRST WORD
ADDRESS(N)
SECOND WORD
ADDRESS(N)
S
T
A
R
T
DEVICE
ADDRESS
R
E
A
D
S
T
O
P
DATA (N)
SDA LINE
M
S
B
LRA
S / C
B WK
M
S
B
A
C
K
L A
S C
B K
M
S
B
N
O
LRA
S / C
B WK
A
C
K
Figure 9: Random Read
tF
t HIGH
tLOW
SCL
t SU,STA
t HD.STA
tR
tLOW
t HD.DAT
t SU.DAT
t SU.STO
SDA IN
t AA
t DH
t BUF
SDA OUT
Figure 10: SCL and SDA Bus Timing
DS3009E-page8
© 2009 Fremont Micro Devices Inc.
FT24C512A
AC CHARACTERISTICS
Symbol
1.8V
Parameter
Min
fSCL
tLOW
tHIGH
tI
tAA
Clock frequency, SCL
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
tF
tSU.STO
tDH
tWR
Clock pulse width high
0.6
0.05
START set-up time
Input rise time
Input fall time
Min
Unit
Max
1000
0.4
0.9
0.05
kHz
µs
0.4
180
Clock low to data out valid
Time the bus must be free
before a new transmission
can start(1)
START hold time
Data in set-up time
120
µs
ns
0.55
µs
1.3
0.5
µs
0.6
0.25
µs
0.6
0.25
µs
0
0
µs
100
100
ns
(1)
0.3
(1)
0.3
300
100
µs
ns
STOP set-up time
0.6
0.25
µs
Date out hold time
50
50
ns
Write cycle time
Endurance(1)
Notes:
1.3
Data in hold time
Max
400
Clock pulse width low
Noise suppression time(1)
tBUF
2.5-5.0 V
25oC, Page Mode, 3.3V
5
5
1,000,000
ms
Write
Cycles
1. This Parameter is expected by characterization but are not fully screened by test.
2. AC Measurement conditions:
RL (Connects to Vcc): 1.3KΩ
Input Pulse Voltages: 0.3Vcc to 0.7Vcc
Input and output timing reference Voltages: 0.5Vcc
© 2009 Fremont Micro Devices Inc.
DS3009E-page9
FT24C512/A
DC CHARACTERISTICS
Symbol
Parameter
Test Conditions
Min
Typical
Max
Units
5.5
V
0.4
1.0
mA
1.8
VCC1
24C××A supply VCC
ICC
Supply read current
VCC @ 5.0V SCL = 100 kHz
ICC
Supply write current
VCC @ 5.0V SCL = 100 kHz
2.0
3.0
mA
ISB1
Supply current
VCC @ 1.8V, VIN = VCC or VSS
0.02
1.0
µA
ISB2
Supply current
VCC @ 2.5V, VIN = VCC or VSS
1.0
µA
ISB3
Supply current
VCC @ 5.0V, VIN = VCC or VSS
1.0
µA
IIL
Input leakage current
Output leakage
current
Input low level
VIN = VCC or VSS
3.0
µA
VIN = VCC or VSS
3.0
µA
VCC×0.3
V
ILO
VIL
0.07
-0.6
VIH
Input high level
VCC +0.5
V
VOL2
Output low level
VCC @ 3.0V, IOL = 2.1 mA
0.4
V
VOL1
Output low level
VCC @ 1.8V, IOL = 0.15 mA
0.4
V
VCC×0.7
ORDER CODE:
FT24CXXA – XXX - X
Packaging
B: Tube
T: Tape and Reel
Temperature Range
U: -40 to 85?
Package
D: DIP
S: SOP
W: WSOP
M: MSOP
T: TSSOP
DS3009E-page10
Option
G: Green Package RoHS Compliant
R: RoHS Compliant
© 2009 Fremont Micro Devices Inc.
FT24C512A
ORDER INFORMATION
Order code
FT24C512A-UDR-B
FT24C512A-UDG-B
FT24C512A-USR-B
FT24C512A-USR-T
FT24C512A-USG-B
FT24C512A-USG-T
FT24C512A-UWR-B
FT24C512A-UWR-T
FT24C512A-UWG-B
FT24C512A-UWG-T
FT24C512A-UMR-B
FT24C512A-UMR-T
FT24C512A-UMG-B
FT24C512A-UMG-T
FT24C512A-UTR-B
FT24C512A-UTR-T
FT24C512A-UTG-B
FT24C512A-UTG-T
Vcc
Temperature Range
Package
DIP8
SOP8
WSOP8
1.8-5.5V
© 2009 Fremont Micro Devices Inc.
-40-85℃
MSOP8
TSSOP8
Option
RoHS
Green Package
RoHS
RoHS
Green Package
Green Package
RoHS
RoHS
Green Package
Green Package
RoHS
RoHS
Green Package
Green Package
RoHS
RoHS
Green Package
Green Package
Packaging
Tube
Tube
Tube
T/R
Tube
T/R
Tube
T/R
Tube
T/R
Tube
T/R
Tube
T/R
Tube
T/R
Tube
T/R
DS3009E-page11
FT24C512/A
DIP8 PACKAGE OUTLINE DIMENSIONS
Symbol
A
A1
A2
B
B1
C
D
E
E1
e
L
E2
DS3009E-page12
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
3.710
0.510
3.200
0.380
4.310
0.146
0.020
0.126
0.015
0.170
3.600
0.570
1.524(BSC)
0.204
0.360
9.000
9.400
6.200
6.600
7.320
7.920
2.540 (BSC)
3.000
3.600
8.400
9.000
0.142
0.022
0.060(BSC)
0.008
0.014
0.354
0.370
0.244
0.260
0.288
0.312
0.100(BSC)
0.118
0.142
0.331
0.354
© 2009 Fremont Micro Devices Inc.
FT24C512A
SOP8 PACKAGE OUTLINE DIMENSIONS (150mil)
Symbol
A
A1
A2
b
c
D
E
E1
e
L
θ
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
1.350
0.100
1.350
0.330
0.170
4.700
3.800
5.800
1.750
0.250
1.550
0.510
0.250
5.100
4.000
6.200
0.053
0.004
0.053
0.013
0.006
0.185
0.150
0.228
0.069
0.010
0.061
0.020
0.010
0.200
0.157
0.244
1.270
8°
0.050(BSC)
0.016
0.050
0°
8°
1.270 (BSC)
0.400
0°
© 2009 Fremont Micro Devices Inc.
DS3009E-page13
FT24C512/A
WSOP8 PACKAGE OUTLINE DIMENSIONS (208 mil)
Symbol
A
A1
A2
b
c
D
E
E1
e
L
θ
DS3009E-page14
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
1.750
0.050
1.700
0.355
0.190
5.130
5.130
7.750
2.160
0.250
1.900
0.480
0.240
5.330
5.330
8.080
0.069
0.002
0.067
0.014
0.0075
0.202
0.202
0.305
0.085
.0098
0.075
0.019
0.0095
0.210
0.210
0.318
1.270 (BSC)
0.510
0°
0.760
8°
0.050(BSC)
0.02
0.03
0°
8°
© 2009 Fremont Micro Devices Inc.
FT24C512A
TSSOP8 PACKAGE OUTLINE DIMENSIONS
Symbol
D
E
b
c
E1
A
A2
A1
e
L
H
θ
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
2.900
4.300
0.190
0.090
6.250
3.100
4.500
0.300
0.200
6.550
1.100
1.000
0.150
0.114
0.169
0.007
0.004
0.246
0.122
0.177
0.012
0.008
0.258
0.043
0.039
0.006
0.800
0.020
0.031
0.001
0.65 (BSC)
0.500
0.026 (BSC)
0.700
0.020
0.25 (TYP)
1°
© 2009 Fremont Micro Devices Inc.
0.028
0.01 (TYP)
7°
1°
7°
DS3009E-page15
FT24C512/A
MSOP8 PACKAGE OUTLINE DIMENSIONS
Symbol
A
A1
A2
b
c
D
e
E
E1
L
DS3009E-page16
Dimensions In Millimeters
Dimensions In Inches
Min
Max
Min
Max
0.820
0.020
0.750
0.250
0.090
2.900
1.100
0.150
0.950
0.380
0.230
3.100
0.320
0.001
0.030
0.010
0.004
0.114
0.043
0.006
0.037
0.015
0.009
0.122
0.65 (BSC)
2.900
4.750
0.400
0.026 (BSC)
3.100
5.050
0.800
0.114
0.187
0.016
0.122
0.199
0.031
© 2009 Fremont Micro Devices Inc.
FT24C512A
APPENDIX A:REVISION HISTORY
Version A: Original data sheet for FT24C512/A.
* Information furnished is believed to be accurate and reliable. However, Fremont Micro Devices, Incorporated (BVI)
assumes no responsibility for the consequences of use of such information or for any infringement of patents of
other rights of third parties which may result from its use. No license is granted by implication or otherwise under
any patent rights of Fremont Micro Devices, Incorporated (BVI). Specifications mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied.
Fremont Micro Devices, Incorporated (BVI) products are not authorized for use as critical components in life support
devices or systems without express written approval of Fremont Micro Devices, Incorporated (BVI). The FMD logo is
a registered trademark of Fremont Micro Devices, Incorporated (BVI). All other names are the property of their
respective owners.
© 2009 Fremont Micro Devices Inc.
DS3009E-page17
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