csd97376q4m
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CSD97376Q4M
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SLPS422A – MARCH 2013 – REVISED JUNE 2013
Synchronous Buck NexFET™ Power Stage
FEATURES
APPLICATIONS
•
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•
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•
•
•
•
•
•
•
•
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1
23
90% System Efficiency at 15A
Max Rated Continuous Current 20A, Peak 45A
High Frequency Operation (up to 2 MHz)
High Density - SON 3.5x4.5-mm Footprint
Ultra Low Inductance Package
System Optimized PCB Footprint
Ultra Low Quiescent (ULQ) Current Mode
3.3V and 5V PWM Signal Compatible
Diode Emulation Mode with FCCM
Input Voltages up to 24V
Three-State PWM Input
Integrated Bootsrap Diode
Shoot Through Protection
RoHS Compliant – Lead Free Terminal Plating
Halogen Free
Ultrabook/Notebook DC/DC Converters
Multiphase Vcore and DDR Solutions
Point-of-Load Synchronous Buck in
Networking, Telecom, and Computing Systems
ORDERING INFORMATION
Device
Package
Media
CSD97376Q4M
SON 3.5 × 4.5-mm
Plastic Package
13-Inch
Reel
Qty
Ship
2500
Tape and
Reel
DESCRIPTION
VIN
VOUT
VCC
VCC
VOUT
PWM1
+Is1
-Is2
+NTC
-NTC
+Is2
-Is2
PWM2
VOUT
SS
RT
Efficiency (%)
CSD97376
100
12
90
10
80
8
VDD = 5V
VIN = 12V
VOUT = 1.8V
LOUT = .29µH
fSW = 500kHz
TA = 25ºC
70
60
6
4
50
40
2
0
4
8
12
Output Current (A)
16
20
PGND
Multi-Phase
Controller
Power Loss (W)
The CSD97376Q4M NexFET™ Power Stage is a highly optimized design for use in a high power, high density
Synchronous Buck converter. This product integrates the driver IC and NexFET technology to complete the
power stage switching function. The driver IC has a built-in selectable diode emulation function that enables
DCM operation to improve light load efficiency. In addition, the driver IC supports ULQ mode that enables
Connected Standby for Windows™ 8. With the PWM input in tri-state, quiescent current is reduced to 130 µA,
with immediate response. When SKIP# is held at tri-state, the current is reduced to 8 µA (typically 20 µs is
required to resume switching). This combination produces a high current, high efficiency, and high speed
switching device in a small 3.5 × 4.5-mm outline package. In addition, the PCB footprint has been optimized to
help reduce design time and simplify the completion of the overall system design.
0
G001
CSD97376
Figure 1. Application Diagram
Figure 2. Efficiency and Power Loss
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
Not Recommended For New Designs
CSD97376Q4M
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS (1)
TA = 25°C (unless otherwise noted)
VALUE
MIN
UNIT
MAX
VIN to PGND
-0.3
30
V
VSW to PGND , VIN to VSW
-0.3
30
V
VSW to PGND, VIN to VSW (<10ns)
-7
33
V
VDD to PGND
–0.3
6
V
PWM, SKIP# to PGND
–0.3
6
V
BOOT to PGND
–0.3
35
V
-2
38
V
–0.3
6
V
Human Body Model (HBM)
2000
V
Charged Device Model (CDM)
500
V
8
W
BOOT to PGND (<10ns)
BOOT to BOOT_R
ESD Rating
Power Dissipation, PD
Operating Temperature Range, TJ
-40
150
°C
Storage Temperature Range, TSTG
–55
150
°C
(1)
Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating
Conditions" is not implied. Exposure to Absolute Maximum rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
TA = 25° (unless otherwise noted)
Parameter
Conditions
Gate Drive Voltage, VDD
MIN
MAX
4.5
5.5
V
24
V
20
A
45
A
Input Supply Voltage, VIN
Continuous Output Current, IOUT
Peak Output Current, IOUT-PK (2)
Switching Frequency, fSW
VIN = 12V, VDD = 5V, VOUT = 1.8V,
fSW = 500kHz, LOUT = 0.29µH (1)
CBST = 0.1µF (min)
2000
On Time Duty Cycle
85
Minimum PWM On Time
40
Operating Temperature
–40
(1)
(2)
UNIT
kHz
%
ns
125
°C
Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
System conditions as defined in Note 1. Peak Output Current is applied for tp = 10ms, duty cycle ≤ 1%
THERMAL INFORMATION
TA = 25°C (unless otherwise noted)
PARAMETER
RθJC
Thermal Resistance, Junction-to-Case (Top of package) (1)
RθJB
Thermal Resistance, Junction-to-Board (2)
(1)
(2)
2
MIN
TYP
MAX
UNIT
22.8
°C/W
2.5
°C/W
RθJC is determined with the device mounted on a 1-inch² (6.45 -cm²), 2-oz (.071-mm thick) Cu pad on a 1.5-inch x 1.5-inch, 0.06-inch
(1.52-mm) thick FR4 board.
RθJB value based on hottest board temperature within 1mm of the package.
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ELECTRICAL CHARACTERISTICS
TA = 25°C, VDD = POR to 5.5V (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
PLOSS
Power Loss (1)
VIN = 12V, VDD = 5V, VOUT = 1.8V, IOUT = 12A,
fSW = 500kHz, LOUT = 0.29µH , TJ = 25°C
2.2
W
Power Loss (2)
VIN = 19V, VDD = 5V, VOUT = 1.8V, IOUT = 12A,
fSW = 500kHz, LOUT = 0.29µH , TJ = 25°C
2.4
W
Power Loss (2)
VIN = 19V, VDD = 5V, VOUT = 1.8V, IOUT = 12A,
fSW = 500kHz, LOUT = 0.29µH , TJ = 125°C
3.0
W
VIN
VIN Quiescent Current, IQ
PWM=Floating, VDD = 5V, VIN= 24V
1
µA
VDD
Standby Supply Current, IDD
Operating Supply Current, IDD
PWM = Float, SKIP# = VDD or 0V
130
SKIP# = Float
PWM = 50% Duty cycle, fSW = 500kHz
µA
8
µA
5.3
mA
POWER-ON RESET AND UNDER VOLTAGE LOCKOUT
Power-On Reset, VDD Rising
4.15
UVLO, VDD Falling
3.7
Hysteresis
V
V
0.2
mV
PWM and SKIP# I/O Specifications
Input Impedance, RI
Pull Up to VDD
1700
Pull Down (to GND)
Logic Level High, VIH
kΩ
800
2.65
Logic Level Low, VIL
0.6
Hysteresis, VIH
0.2
Tri-State Voltage, VTS
1.3
V
2
Tri-state Activation Time (falling) PWM,
tTHOLD(off1)
60
Tri-state Activation Time (rising) PWM, tTHOLD(off2)
60
Tri-state Activation Time (falling) SKIP#, tTSKF
1
Tri-state Activation Time (rising) SKIP#, tTSKR
1
Tri-state Exit Time PWM, t3RD(PWM) (2)
Tri-state Exit Time SKIP#, t3RD(SKIP#) (2)
ns
µs
100
ns
50
µs
240
mV
2
µA
BOOTSTRAP SWITCH
Forward Voltage, VFBST
IF = 10mA
Reverse Leakage, IRLEAK (2)
VBST – VDD = 25V
(1)
(2)
120
Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
Specified by design
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TYPICAL CHARACTERISTICS
TJ = 125°C, unless stated otherwise.
9
1.1
VIN = 12V
VDD = 5V
VOUT = 1.8V
fSW = 500kHz
LOUT = 0.29µH
6
5
4
3
2
0
2
4
6
8
10
12
14
Output Current (A)
16
18
0.8
0.7
0.6
Typ
Max
1
0.9
0.5
−50
20
24
24
20
20
16
12
400LFM
200LFM
100LFM
Nat Conv
4
0
0
10
20
VIN = 12V
VDD = 5V
VOUT = 1.8V
fSW = 500kHz
LOUT = 0.29µH
30
40
50
60
70
Ambient Temperature (ºC)
80
0
400LFM
200LFM
100LFM
Nat Conv
0
10
20
30
40
50
60
70
Ambient Temperature (ºC)
12
VIN = 12V
VDD = 5V
VOUT = 1.8V
fSW = 500kHz
LOUT = 0.29µH
0
20
40
60
80
100
Board Temperature (ºC)
Figure 7. Typical Safe Operating Area (1)
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1.2
1.15
G001
4.8
3.6
1.1
2.4
1.05
1.2
1
0.0
0.9
140
90
6.0
0.95
120
80
7.2
VIN = 12V
VDD = 5V
VOUT = 1.8V
LOUT = 0.29µH
IOUT = 20A
1.25
16
4
G001
VIN = 12V
VDD = 5V
VOUT = 1.8V
fSW = 500kHz
LOUT = 0.29µH
1.3
Typ
Max
8
150
Figure 6. Safe Operating Area – PCB Vertical Mount (1)
Power Loss, Normalized
Output Current (A)
8
G001
20
125
12
90
24
4
25
50
75
100
Junction Temperature (ºC)
16
4
Figure 5. Safe Operating Area – PCB Horizontal Mount (1)
0
0
Figure 4. Power Loss vs Temperature
Output Current (A)
Output Current (A)
Figure 3. Power Loss vs Output Current
8
−25
G001
SOA Temperature Adj (ºC)
Power Loss (W)
7
VIN = 12V
VDD = 5V
VOUT = 1.8V
fSW = 500kHz
LOUT = 0.29µH
1
Power Loss, Normalized
8
−1.2
0
400
800
1200
1600
Switching Frequency (kHz)
2000
−2.4
2400
G001
G001
Figure 8. Normalized Power Loss vs Frequency
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TYPICAL CHARACTERISTICS (continued)
TJ = 125°C, unless stated otherwise.
1.2
1.15
6.0
4.8
3.6
1.1
2.4
1.05
1.2
1
0.0
0.95
0.9
2
4
6
8
10 12 14 16
Input Voltage (V)
18
20
22
24
2.4
1
0
−2.4
−1.2
0.8
−4.9
−2.4
0.7
0
0.6
1.2
1.8
2.4
Output Voltage (V)
7.2
1.2
1.15
4.8
3.6
1.1
2.4
1.05
1.2
1
0
0.95
−1.2
0.9
−2.4
0.85
−3.6
100 200 300 400 500 600 700 800 900 1000 1100
Output Inductance (nH)
−7.3
3.6
G001
35
6
VIN = 12V
VDD = 5V
VOUT = 1.8V
LOUT = 0.29µH
IOUT = 20A
30
Driver Current (mA)
VIN = 12V
VDD = 5V
VOUT = 1.8V
fSW = 500kHz
IOUT = 20A
3
Figure 10. Normalized Power Loss vs Output Voltage
SOA Temperature Adj (ºC)
1.3
4.9
1.1
G001
1.25
Power Loss, Normalized
1.2
7.3
0.9
Figure 9. Normalized Power Loss vs Input Voltage
0
VIN = 12V
VDD = 5V
fSW = 500kHz
LOUT = 0.29µH
IOUT = 20A
1.3
Power Loss, Normalized
Power Loss, Normalized
1.25
9.7
1.4
SOA Temperature Adj (ºC)
7.2
VDD = 5V
VOUT = 1.8V
LOUT = 0.29µH
fSW = 500kHz
IOUT = 20A
SOA Temperature Adj (ºC)
1.3
25
20
15
10
5
0
G001
Figure 11. Normalized Power Loss vs Output Inductance
400
0
800
1200
1600
Switching Frequency (kHz)
2000
2400
G000
Figure 12. Driver Current vs Frequency
8.5
Driver Current (mA)
8.2
7.9
7.6
VIN = 12V
VDD = 5V
VOUT = 1.8V
LOUT = 0.29µH
IOUT = 20A
7.3
7
−50
−25
0
25
50
75
100
Junction Temperature (°C)
125
150
G000
Figure 13. Driver Current vs Temperature
1. The Typical CSD97376Q4M System Characteristic curves are based on measurements made on a PCB design with
dimensions of 4.0" (W) x 3.5" (L) x 0.062" (T) and 6 copper layers of 1 oz. copper thickness. See the Application
Information section for detailed explanation.
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PIN CONFIGURATION
SKIP#
1
8
PWM
VDD
2
7
BOOT
PGND
3
6
BOOT_R
9
PGND
VSW
4
5
VIN
Figure 14. Top View
PIN DESCRIPTION
PIN
NO.
6
DESCRIPTION
NAME
1
SKIP#
This pin enables the Diode Emulation function. When this pin is held Low, Diode Emulation Mode is enabled for the
Sync FET. When SKIP# is High, the CSD97376Q4M operates in Forced Continuous Conduction Mode. A tri-state
voltage on SKIP# puts the driver into a very low power state.
2
VDD
Supply Voltage to Gate Drivers and internal circuitry.
3
PGND
Power Ground, Needs to be connected to Pin 9 and PCB
4
VSW
Voltage Switching Node – pin connection to the output inductor.
5
VIN
Input Voltage Pin. Connect input capacitors close to this pin.
6
BOOT_R
7
BOOT
Bootstrap capacitor connection. Connect a minimum 0.1µF 16V X5R, ceramic cap from BOOT to BOOT_R pins. The
bootstrap capacitor provides the charge to turn on the Control FET. The bootstrap diode is integrated.
8
PWM
Pulse Width modulated 3-state input from external controller. Logic Low sets Control FET gate low and Sync FET gate
high. Logic High sets Control FET gate high and Sync FET gate Low. Open or High Z sets both MOSFET gates low if
greater than the 3-State Shutdown Hold-off Time (t3HT)
9
PGND
Power Ground
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VDD
+
DRVL
DRVH
Level Shift
+
VDD
+
BOOT
5
VIN
Control
FET
6 BOOT_R
+
VUVLO
7
1V
1.7Meg
+
SKIP#
4
VSW
2
VDD
9
PGND
3-State
Logic
1
+
800k
VDD
+
1V
1.7Meg
PWM
3-State
Logic
8
Sync
FET
DRVL
800k
PGND 3
Figure 15. Functional Block Diagram
FUNCTIONAL DESCRIPTION
POWERING CSD97376Q4M AND GATE DRIVERS
An external VDD voltage is required to supply the integrated gate driver IC and provide the necessary gate drive
power for the MOSFETS. A 1µF 10V X5R or higher ceramic capacitor is recommended to bypass VDD pin to
PGND. A bootstrap circuit to provide gate drive power for the Control FET is also included. The bootstrap supply
to drive the Control FET is generated by connecting a 100nF 16V X5R ceramic capacitor between BOOT and
BOOT_R pins. An optional RBOOT resistor can be used to slow down the turn on speed of the Control FET and
reduce voltage spikes on the VSW node. A typical 1Ω to 4.7Ω value is a compromise between switching loss and
VSW spike amplitude.
Undervoltage Lockout Protection (UVLO)
The undervoltage lockout (UVLO) comparator evaluates the VDD voltage level. As VVDD rises, both the Control
FET and Sync FET gates hold actively low at all times until VVDD reaches the higher UVLO threshold (VUVLO_H).,
Then the driver becomes operational and responds to PWM and SKIP# commands. If VDD falls below the lower
UVLO threshold (VUVLO_L = VUVLO_H – Hysteresis), the device disables the driver and drives the outputs of the
Control FET and Sync FET gates actively low. Figure 16 shows this function.
CAUTION
Do not start the driver in the very low power mode (SKIP# = Tri-state).
VUVLO_H
VUVLO_L
VVDD
Driver On
UDG-12218
Figure 16. UVLO Operation
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PWM Pin
The PWM pin incorporates an input tri-state function. The device forces the gate driver outputs to low when
PWM is driven into the tri-state window and the driver enters a low power state with zero exit latency. The pin
incorporates a weak pull-up to maintain the voltage within the tri-state window during low-power modes.
Operation into and out of tri-state mode follows the timing diagram outlined in Figure 17.
When VDD reaches the UVLO_H level, a tri-state voltage range (window) is set for the PWM input voltage. The
window is defined the PWM voltage range between PWM logic high (VIH) and logic low (VIL) thresholds. The
device sets high-level input voltage and low-level input voltage threshold levels to accommodate both 3.3 V
(typical) and 5 V (typical) PWM drive signals.
When the PWM exits tri-state, the driver enters CCM for a period of 4 µs, regardless of the state of the SKIP#
pin. Normal operation requires this time period in order for the auto-zero comparator to resume.
VIH
High-Z Window
High-Z Window
VIL
VSW
VOUT
t3RD1
tHOLD_OFF1
tpdLH
High-Z
High-Z
PWM
tHOLD_OFF2
tpdHL
t3RD2
Time
Figure 17. PWM Tri-State Timing Diagram
SKIP# Pin
The SKIP# pin incorporates the input tri-state buffer as PWM. The function is somewhat different. When SKIP# is
low, the zero crossing (ZX) detection comparator is enabled, and DCM mode operation occurs if the load current
is less than the critical current. When SKIP# is high, the ZX comparator disables, and the converter enters FCCM
mode. When both SKIP# and PWM are tri-stated, normal operation forces the gate driver outputs low and the
driver enters a low-power state. In the low-power state, the UVLO comparator remains off to reduce quiescent
current. When SKIP# is pulled low, the driver wakes up and is able to accept PWM pulses in less than 50 µs.
Table 1 shows the logic functions of UVLO, PWM, SKIP#, the Control FET Gate and the Sync FET Gate.
Table 1. Logic Functions of the Driver IC
(1)
8
UVLO
PWM
SKIP#
Sync FET Gate
Control FET Gate
MODE
Active
—
—
Low
Low
Disabled
Inactive
Low
Low
High (1)
Low
DCM (1)
Inactive
Low
High
High
Low
FCCM
Inactive
High
H or L
Low
High
Inactive
Tri-state
H or L
Low
Low
LQ
Inactive
—
Tri-state
Low
Low
ULQ
Until zero crossing protection occurs.
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Zero Crossing (ZX) Operation
The zero crossing comparator is adaptive for improved accuracy. As the output current decreases from a heavy
load condition, the inductor current also reduces and eventually arrives at a valley, where it touches zero current,
which is the boundary between continuous conduction and discontinuous conduction modes. The SW pin detects
the zero-current condition. When this zero inductor current condition occurs, the ZX comparator turns off the
rectifying MOSFET.
Integrated Boost-Switch
To maintain a BST-SW voltage close to VDD (to get lower conduction losses on the high-side FET), the
conventional diode between the VDD pin and the BST pin is replaced by a FET which is gated by the DRVL
signal.
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APPLICATION INFORMATION
The Power Stage CSD97376Q4M is a highly optimized design for synchronous buck applications using NexFET
devices with a 5V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest
power loss and highest system efficiency. As a result, a rating method is used that is tailored towards a more
systems centric environment. The high-performance gate driver IC integrated in the package helps minimize the
parasitics and results in extremely fast switching of the power MOSFETs. System level performance curves such
as Power Loss, Safe Operating Area and normalized graphs allow engineers to predict the product performance
in the actual application.
Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are primarily needed by engineers to estimate the loss
generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has
provided measured power loss performance curves. Figure 3 plots the power loss of the CSD97376Q4M as a
function of load current. This curve is measured by configuring and running the CSD97376Q4M as it would be in
the final application (see Figure 18). The measured power loss is the CSD97376Q4M device power loss which
consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve.
Power Loss = (VIN x IIN) + (VDD x IDD) – (VSW_AVG x IOUT)
(1)
The power loss curve in Figure 3 is measured at the maximum recommended junction temperature of
TJ = 125°C under isothermal test conditions.
Safe Operating Curves (SOA)
The SOA curves in the CSD97376Q4M datasheet give engineers guidance on the temperature boundaries within
an operating system by incorporating the thermal resistance and system power loss. Figure 5 and Figure 7
outline the temperature and airflow conditions required for a given load current. The area under the curve
dictates the safe operating area. All the curves are based on measurements made on a PCB design with
dimensions of 4.0" (W) x 3.5" (L) x 0.062" (T) and 6 copper layers of 1 oz. copper thickness.
Normalized Curves
The normalized curves in the CSD97376Q4M data sheet give engineers guidance on the Power Loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in
power loss and the secondary Y-axis is the change is system temperature required in order to comply with the
SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is
subtracted from the SOA curve.
CSD97376Q4M
Vin
VDD
Gate Drive
Voltage (VDD)
A
VIN
VDD
A
Input Current (IIN)
Boot
Gate Drive
Current (IDD)
BST
HSgate
V
DRVH
CBoot
Control
FET
Cin
V
Input Voltage
(VIN)
Boot_R
Vsw
SKIP#
LL
VSW
LO
VO
A
SKIP#
PWM
LSgate
PWM
DRVL
Sync
FET
Co
Output Current
(IOUT)
GND
PGND
Averaging
Circuit
V
Averaged Switched
Node Voltage
(VSW_AVG)
Figure 18. Power Loss Test Circuit
10
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Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see the Design Example).
Though the Power Loss and SOA curves in this datasheet are taken for a specific set of test conditions, the
following procedure will outline the steps engineers should take to predict product performance for any set of
system conditions.
Design Example
Operating Conditions: Output Current (lOUT) = 10A, Input Voltage (VIN ) = 7V, Output Voltage (VOUT) = 1.5V,
Switching Frequency (fSW) = 800kHz, Output Inductor (LOUT) = 0.2µH
Calculating Power Loss
•
•
•
•
•
•
Typical Power Loss at 10A = 2.1W (Figure 3)
Normalized Power Loss for switching frequency ≈ 0.99 (Figure 8)
Normalized Power Loss for input voltage ≈ 1.10 (Figure 9)
Normalized Power Loss for output voltage ≈ 0.93(Figure 10)
Normalized Power Loss for output inductor ≈ 1.10 (Figure 11)
Final calculated Power Loss = 2.1W × 0.99 × 1.10 × 0.93 × 1.10 ≈ 2.3W
Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for switching frequency ≈ -0.2°C (Figure 8)
SOA adjustment for input voltage ≈ 2.5°C (Figure 9)
SOA adjustment for output voltage ≈ 1.0°C (Figure 10)
SOA adjustment for output inductor ≈ 2.3°C (Figure 11)
Final calculated SOA adjustment = -0.2 + 2.5 + (-1.5) + 2.3 ≈ 3.1°C
Figure 19. Power Stage CSD97376Q4M SOA
In the design example above, the estimated power loss of the CSD97376Q4M would increase to 2.3W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 3.1°C. Figure 19
graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 3.1°C. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
Copyright © 2013, Texas Instruments Incorporated
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Not Recommended For New Designs
CSD97376Q4M
SLPS422A – MARCH 2013 – REVISED JUNE 2013
www.ti.com
RECOMMENDED PCB DESIGN OVERVIEW
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. Below
is a brief description on how to address each parameter.
Electrical Performance
The CSD97376Q4M has the ability to switch at voltage rates greater than 10kV/µs. Special care must be then
taken with the PCB layout design and placement of the input capacitors, inductor and output capacitors.
• The placement of the input capacitors relative to VIN and PGND pins of CSD97376Q4M device should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 20).
The example in Figure 20 uses 1 x 1nF 0402 25V and 3 x 10µF 1206 25V ceramic capacitors (TDK Part #
C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an
appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power
Stage C5, C8 and C6, C19 should follow in order.
• The bootstrap cap CBOOT 0.1µF 0603 16V ceramic capacitor should be closely connected between BOOT and
BOOT_R pins
• The switching node of the output inductor should be placed relatively close to the Power Stage
CSD97376Q4M VSW pins. Minimizing the VSW node length between these two components will reduce the
PCB conduction losses and actually reduce the switching noise level. (2)
Thermal Performance
The CSD97376Q4M has the ability to use the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed in your design. The example in Figure 20 uses vias with a 10 mil drill hole
and a 16 mil capture pad.
• Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
Figure 20. Recommended PCB Layout (Top Down View)
(2)
12
Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Not Recommended For New Designs
CSD97376Q4M
www.ti.com
SLPS422A – MARCH 2013 – REVISED JUNE 2013
MECHANICAL DATA
Ө°
c1
a1
D2
4
1
0.300
(x45°)
8
DIM
5
MILLIMETERS
INCHES
Min
Nom
Max
Min
Nom
Max
A
0.800
0.900
1.000
0.031
0.035
0.039
a1
0.000
0.000
0.080
0.000
0.000
0.003
b
0.150
0.200
0.250
0.006
0.008
0.010
b1
2.000
2.200
2.400
0.079
0.087
0.095
b2
0.150
0.200
0.250
0.006
0.008
0.010
c1
0.150
0.200
0.250
0.006
0.008
0.010
D2
3.850
3.950
4.050
0.152
0.156
0.160
E
4.400
4.500
4.600
0.173
0.177
0.181
E1
3.400
3.500
3.600
0.134
0.138
0.142
E2
2.000
2.100
2.200
0.079
0.083
0.087
e
0.400 TYP
0.016 TYP
K
0.300 TYP
0.012 TYP
L
0.300
0.400
0.500
0.012
0.016
0.020
L1
0.180
0.230
0.280
0.007
0.009
0.011
θ
0.00
—
—
0.00
—
—
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Not Recommended For New Designs
CSD97376Q4M
SLPS422A – MARCH 2013 – REVISED JUNE 2013
www.ti.com
Recommended PCB Land Pattern
(0.010)
0.250
(x18)
(0.006)
0.150
(0.006)
0.150
(0.016)
0.400
(0.024)
0.600 (x 2)
(0.008)
0.200
(x2)
(0.087)
2.200
R0.100
R0.100
0.225 ( x 2)
(0.009)
0.440 (0.017)
(0.088)
2.250
(0.012)
0.300
(0.159)
4.050
RECOMMENDED PCB PATTERN
Recommended Stencil Opening
(0.024)
0.600 (x 2)
(0.008)
0.200
(0.008)
0.200
(0.029)
0.738 (x 8)
(0.016)
0.400
(0.015)
0.390
(0.014)
0.350
0.300
(0.012)
R0.100
0.850 (x8)
(0.033)
(0.012)
0.300
(0.087)
2.200
R0.100
0.225 ( x 2)
(0.009)
(0.004)
0.115
0.440 (0.017)
(0.009)
0.225
(0.008)
0.200
(0.087)
2.200
0.200
(0.008)
NOTE: Dimensions are in mm (inches).
14
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Copyright © 2013, Texas Instruments Incorporated
Not Recommended For New Designs
CSD97376Q4M
www.ti.com
SLPS422A – MARCH 2013 – REVISED JUNE 2013
REVISION HISTORY
Changes from Original (March 2013) to Revision A
Page
•
Changed Feature From: Over 90% System Efficiency at 15A To: 90% System Efficiency at 15A ...................................... 1
•
Changed the Mechanical Drawing image ........................................................................................................................... 13
•
Added dimension row b2 to the MECHANICAL DATA table .............................................................................................. 13
•
Changed the Recommended PCB Land Pattern image ..................................................................................................... 14
•
Changed the Recommended Stencil Opening image ........................................................................................................ 14
Copyright © 2013, Texas Instruments Incorporated
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15
PACKAGE OPTION ADDENDUM
www.ti.com
2-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
CSD97376Q4M
NRND
Package Type Package Pins Package
Drawing
Qty
VSON-CLIP
DPC
8
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Pb-Free (RoHS
Exempt)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 150
97376M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-Apr-2015
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CSD97376Q4M
Package Package Pins
Type Drawing
VSONCLIP
DPC
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
3.71
B0
(mm)
K0
(mm)
P1
(mm)
4.71
1.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Dec-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD97376Q4M
VSON-CLIP
DPC
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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