4570 Group DATASHEET

4570 Group DATASHEET
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April 1st, 2010
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MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DESCRIPTION
● System clock switch function
............................................................. f(XIN)/4 or not divided
● Timers
Timer 1... 10-bit timer with a reload register and carrier wave
output auto-control function
Timer 2 ................................ 8-bit timer with a reload register
Timer 3... 8-bit timer with two reload registers and carrier wave
generation function
● Interrupt ................................................................... 4 sources
● Power-on reset circuit
● Watchdog timer ............................................................ 16 bits
● Key-on wakeup function (Ports P0, P1, and P4, ON/OFF of
port P4 can be switched)
●Pull-up transistor .............. (Ports P0, P1, and P4, ON/OFF of
port P4 can be switched)
● Voltage drop detection circuit
● Clock generating circuit (ceramic resonance)
The 4570 Group is a 4-bit single-chip microcomputer designed
with CMOS technology. Its CPU is that of the 4500 series using
a simple, high-speed instruction set. The computer is equipped
with a carrier wave output circuit for remote control, an 8-bit timer
with a reload register, a 10-bit timer with a reload register, and
an 8-bit timer with two reload registers.
The various microcomputers in the 4570 Group include variations
of the built-in memory size. The mask ROM version and One
Time PROM version of 4570 Group are produced as shown in
the table below.
FEATURES
● Minimum instruction execution time
When f(XIN) is selected for system clock ....................... 1.5µs
(f(XIN)=2.0 MHz, VDD=4.5 V to 5.5 V)
When f(XIN)/4 is selected for system clock ................. 2.86µs
(f(XIN)=4.2 MHz, VDD=2.0 V to 5.5 V)
● Supply voltage
............................. 2.5 V to 5.5 V (One Time PROM version)
....................................... 2.0 V to 5.5 V (Mask ROM version)
ROM (PROM) size
Product
(✕ 10 bits)
M34570M4-XXXFP
4096 words
8192 words
M34570M8-XXXFP
M34570MD-XXXFP
16384 words
8192 words
M34570E8FP
16384 words
M34570EDFP *
*: Under development (Jan. 1999)
APPLICATION
Remote control transmitter
RAM size
(✕ 4 bits)
128 words
128 words
128 words
128 words
128 words
Package
ROM type
36P2R-A
36P2R-A
Mask ROM
Mask ROM
36P2R-A
Mask ROM
36P2R-A
36P2R-A
One Time PROM
One Time PROM
PIN CONFIGURATION (TOP VIEW)
M34570Mx-XXXFP
1
36
D1
D3
2
35
D4
D5
D6
3
34
33
32
D8
4
5
6
7
D0
P13
P12
D9/TOUT
8
D7
P20
9
P21/INT
10
11
RESET
CNV SS
28
27
26
25
P11
P10
P03
P02
P01
P00
P43
P42
P41
23
P40
17
22
21
20
P33
P32
P31
18
19
P30
13
XIN
14
15
VDCE
VDD
CARR
31
30
29
24
12
XOUT
VSS
M34570Mx-XXXFP
D2
16
Outline 36P2R-A
2
Port P0
Port P1
4
Port P2
2
Watchdog timer (16 bits)
128 words ✕ 4 bits
RAM
4096 to 16384 words ✕ 10 bits
ROM (Note)
Note: PROM 16384 words ✕ 10 bits for the built-in PROM version.
Register B (4 bits)
Register A (4 bits)
Register E (8 bits)
Register D (3 bits)
Stack registers SKs (8 levels)
Interrupt stack register SDP(1 level)
ALU(4 bits)
4500 Series
CPU core
Reset (Voltage drop detection circuit)
Timer 3 (8 bits)
(Carrier wave generation)
Memory
XIN –XOUT
Port D
10
Timer 1 (10 bits)
Timer 2 (8 bits)
Port P4
4
Clock generating circuit
Port P3
4
Timers/Carrier wave generation
Internal peripheral functions
I/O port
4
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
BLOCK DIAGRAM
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PERFORMANCE OVERVIEW
Parameter
Function
Number of basic instructions
99
Minimum instruction execution time 1.5 µs (f(XIN) = 2.0 MHz:system clock = f(XIN): VDD = 5.0 V)
2.86 µs (f(XIN) = 4.2 MHz:system clock = f(XIN)/4: VDD = 5.0 V)
Memory sizes ROM
RAM
M34570M4 4096 words ✕ 10 bits
M34570M8 8192 words ✕ 10 bits
M34570MD 16384 words ✕ 10 bits
M34570E8 8192 words ✕ 10 bits
M34570ED 16384 words ✕ 10 bits
128 words ✕ 4 bits
Input/Output
D0–D9
ports
P00–P03
P10–P13 I/O
P20, P21 Input
P30–P33 I/O
Output
I/O
P40–P43 Input
Output
CARR
Output
TOUT
INT
Timers
Input
Ten independent output ports; port D9 is also used as the TOUT output pin.
4-bit I/O port; every pin of the ports has a key-on wakeup function and a pull-up function.
4-bit I/O port; every pin of the ports has a key-on wakeup function and a pull-up function.
2-bit input port, port P21 is also used as INT input pin.
4-bit I/O port
4-bit input port; both pull-up function and key-on wakeup function can be switched by software.
1-bit output port (CMOS output)
1-bit output pin; TOUT output pin is also used as port D9.
1-bit input pin with a key-on wakeup function. INT input pin is also used as port P21.
Timer 1
10-bit timer with a reload register and carrier wave output auto-control function
Timer 2
Timer 3
8-bit timer with a reload register
8-bit timer with two reload registers and carrier wave generation function
Interrupt
Sources
Nesting
Subroutine nesting
4 (one for external and three for timer)
1 level
8 levels (however, only 7 levels can be used when an interrupt is used or the TABP p instruction
Device structure
is executed)
CMOS silicon gate
Package
36-pin plastic molded SSOP
Operating temperature range
Supply voltage
–20 °C to 70 °C
2.0 V to 5.5 V for mask ROM version (2.5 V to 5.5 V for One Time PROM version)
Power
1.3 mA (f(XIN) = 4.2 MHz: system clock = f(XIN)/4, VDD=5.0 V)
at active
dissipation
(typical value) at RAM back-up
0.5 mA (f(XIN) = 1.0 MHz: system clock = f(XIN), VDD=3.0 V)
0.1 µA (Ta=25 °C, VDD=5V, typical value)
DEFINITION OF CLOCK AND CYCLE
● System clock
The system clock is the basic clock for controlling this product.
The system clock can be selected by bit 3 of the clock control
register MR as shown in the table below.
Table Selection of system clock
System clock
MR3
f(XIN)
0
f(XIN)/4
1
Note: f(XIN)/4 is selected immediately after system is released
from reset.
● Instruction clock
The instruction clock is the standard clock for controlling CPU.
The instruction clock is a signal derived from dividing the
system clock by 3. The one cycle of the instruction clock is
equivalent to the one machine cycle.
● Machine cycle
The machine cycle is the standard cycle required to execute
the instruction.
3
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PIN DESCRIPTION
VDD
Pin
Name
Power supply
VSS
Ground
CNVSS
CNVSS
Reset input
RESET
Input/Output
Function
—
Connected to a plus power supply.
—
Connected to a 0 V power supply.
Input
I/O
Connect CNVSS to VSS and apply “L” (0V) to CNVSS certainly.
An N-channel open-drain I/O pin for a system reset. A pull-up transistor and a
capacitor are built-in this pin. When the watchdog timer causes the system to be
reset or the low-supply voltage is detected, the RESET pin outputs “L” level.
XIN
Clock input
Input
I/O pins of the clock generating circuit. Connect a ceramic resonator between XIN
XOUT
Clock output
Output
D0–D9
Output port D
Output
pin and XOUT pin. A feedback resistor is built-in between them.
Each pin of port D has an independent 1-bit wide output function. Port D9 is also
P00–P03
I/O port P0
I/O
P10–P13
I/O port P1
I/O
P20, P21
Input port P2
I/O
P30–P33
I/O port P3
I/O
P40–P43
Input port P4
CARR
Carrier wave output
used as TOUT output pin. The output structure is N-channel open-drain.
4-bit I/O port. It can be used as an input port when the output latch is set to “1.”
The output structure is N-channel open-drain. Every pin of the ports has a key-on
wakeup function and a pull-up function.
4-bit I/O port. It can be used as an input port when the output latch is set to “1.”
The output structure is N-channel open-drain. Every pin of the ports has a key-on
wakeup function and a pull-up function.
2-bit input port. Port P21 is also used as the INT input pin.
4-bit I/O port. It can be used as an input port when the output latch is set to “1.”
The output structure is N-channel open-drain.
Input
4-bit input port. Every pin of the ports has a key-on wakeup function and a pull-up
function. Both functions can be switched by software.
Output
Carrier wave output pin for remote control transmit. The output structure is the
CMOS circuit.
for remote control
INT
Interrupt input
Input
INT input pin accepts an external interrupt and has a key-on wakeup function. INT
TOUT
Timer output
Output
input pin is also used as port P21.
TOUT output pin has the function to output the timer 2 underflow signal divided by
VDCE
Voltage drop
Input
2. TOUT output pin is also used as port D9.
4
detection circuit
VDCE pin is used to control the operation/stop of the voltage drop detection circuit.
The circuit is operating when “H” level is input to the VDCE pin. It is stopped when
enable
“L” level is input to this pin.
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MULTIFUNCTION
Pin
Multifunction
D9
TOUT
Pin
TOUT
Multifunction
D9
P21
INT
INT
Notes 1: Pins except above have just single function.
2: The port D9 is the output port and port P21 is the input port.
P21
CONNECTIONS OF UNUSED PINS
Connection
Pin
D0–D8
D9/TOUT
P00–P03
P10–P13
Connection
Pin
Connect to VSS, or set the output latch to P30–P33
“0” and open.
Set the output latch to “1” and open.
P40–P43
Connect to VSS, or set the output latch to
“0” and open.
Connect to VSS (Note 2) or open (Note 3).
Open.
CARR
P20, P21/INT
Connect to VSS (Note 1).
Notes 1: When the P21/INT pin is connected to VSS pin, set the return level to “H” level by software (interrupt control register I12=“1”).
When the P21/INT pin is connected to VSS pin while the return level is set to “L” level, system returns from RAM back-up
state immediately after system enters the RAM back-up state.
2: In order to connect ports P40–P43 to VSS, turn off their pull-up transistors (pull-up control register PU0i=“0”) by software and
also invalidate the key-on wakeup functions (key-on wakeup control register K0i=“0”). When these pins are connected to
VSS while the key-on wakeup functions are left valid, the system fails to return from RAM back-up state. In order to make
these pins open, turn on their pull-up transistors (register PU0i=“1”) by software (i = 0, 1, 2, 3).
Be sure to select the key-on wakeup function and the pull-up function with every one port.
3: In order to make ports P40–P43 open, turn on their pull-up transistors (register PU0i = “1”) by software (i = 0, 1, 2, 3).
(Note in order to set the output latch to “0” or “1” or make pins open)
• After system is released from reset, a port is in a high-impedance state until the output latch of the port is set to “0” by software.
Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur.
• To set the output latch periodically is recommended because the value of output latch may change by noise or a program run away
(caused by noise).
(Note in order to connect unused pins to VSS)
• To avoid noise, connect the unused pins to VSS at the shortest distance using a thick wire.
PORT FUNCTION
Port
Port D
Pin
D0–D8, D9/TOUT
Input/
Output
Output structure
Output
N-channel open-drain
Control
Control
Control
bits
instructions
registers
1
(10)
SD
RD
W22
Remark
W22 controls the switch of D9/
TOUT pin
CLD
Port P0
Port P1
P00–P03
I/O
N-channel open-drain
4
OP0A
IAP0
P10–P13
(4)
I/O
N-channel open-drain
4
OP1A
2
IAP1
IAP2
(4)
Port P2
P20
Port P3
P21/INT
P30–P33
Input
(2)
I/O
Pull-up functions
Key-on wakeup functions
Pull-up functions
Key-on wakeup functions
SNZI0
N-channel open-drain
4
Key-on wakeup function
(Note)
OP3A
IAP3
Port P4
P40–P43
Input
4
IAP4
(4)
PU0
K0
Pull-up functions
(programmable)
Key-on wakeup functions
(programmable)
Note: Level of the P21/INT pin can be examined with the SNZI0 instruction.
5
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PORT BLOCK DIAGRAMS
Pull-up
transistor
Key-on wakeup
input
(Note 1)
IAP0 instruction
P00–P0 3
Register A
IAP2 instruction
(Note 2)
Ai
D Q
OP0A instruction
Register A
T
P20
Key-on wakeup
input
External interrupt circuit
Pull-up
transistor
Key-on wakeup
input
(Note 1)
IAP2 instruction
(Note 1)
Register A
P21/INT
IAP1 instruction
P10–P1 3
Register A
(Note 2)
(Note 1)
Ai
D Q
OP1A instruction
T
IAP3 instruction
K00
Key-on wakeup
input
Pull-up
transistor
P30–P3 3
Register A
(Note 1)
(Note 2)
PU00
Ai
D Q
OP3A
instruction
IAP4 instruction
Register A
T
(Note 1)
P40
Decoder
Register Y
K01
Key-on wakeup
input
CLD
instruction
Pull-up
transistor (Note 1)
S
D0–D8
SD instruction
PU01
R Q
RD instruction
IAP4 instruction
Register A
P41
(Note 1)
Register Y
Decoder
CLD
instruction
K02
Key-on wakeup
input
Pull-up
transistor (Note 1)
PU02
Register A
Timer 2 underflow signal output
1/2
Key-on wakeup
input
Pull-up
transistor
(Note 1)
D9/TOUT
0
1
(Note 1)
P42
K03
Notes 1.
This symbol represents a parasitic diode.
Applied potential to ports P2 0 and P2 1 must be V DD or less.
PU03
2. i represents 0, 1, 2 or 3.
IAP4 instruction
6
W22
R Q
RD instruction
IAP4 instruction
Register A
S
SD instruction
P43
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PORT BLOCK DIAGRAMS (continued)
Register B
Register A
To timer 1
(T3HAB)
CARRY
Reload register R3H (8)
C21
W3 1,W3 0
Timer 2 underflow
signal
ORCLK
MR3
XIN
1/2
00
W33
01
0
10
1
0
11
1
Not available
(Note)
Reload control circuit
Port CARR
Q
T
Timer 3(8)
R
W33
(T3AB)
Reload register R3L (8)
(T3AB)
(TAB3)
Register B
Register A
T3F
(TAB3)
Timer 1 underflow
signal
Timer 3
interrupt
Q
T
R
C20
W10
Note :
This symbol represents a parasitic diode.
7
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
FUNCTION BLOCK OPERATIONS
CPU
<Carry>
(CY)
(1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such
as 4-bit data addition, comparison, AND operation, OR
operation, and bit manipulation.
(2) Register A and carry flag (CY)
Register A is a 4-bit register used for arithmetic, transfer,
exchange, and I/O operation.
Carry flag CY is a 1-bit flag that is set to “1” when there is a
carry with the AMC instruction (Figure 1).
It is unchanged with both A n instruction and AM instruction.
The value of A0 is stored in carry flag CY with the RAR
instruction (Figure 2).
Carry flag CY can be set to “1” with the SC instruction and
cleared to “0” with the RC instruction.
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4bit data, and for 8-bit data transfer together with register A.
Register E is an 8-bit register. It can be used for 8-bit data
transfer with register B used as the high-order 4 bits and
register A as the low-order 4 bits (Figure 3).
(M(DP))
Addition
ALU
(A)
<Result>
Fig. 1 AMC instruction execution example
<Set>
SC instruction
<Clear>
RC instruction
CY
A3 A2 A1 A0
<Rotation>
RAR instruction
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
(4) Register D
Register D is a 3-bit register.
It is used to store a 7-bit ROM address together with register
A and is used as a pointer within the specified page when the
TABP p, BLA p, or BMLA p instruction is executed (Figure 4).
Register B TAB instruction Register A
B3 B2 B1 B0
A3 A2 A1 A0
TEAB instruction
Register E E7 E6 E5 E4 E3 E2 E1 E0
TABE instruction
B3 B2 B1 B0
Register B
A3 A2 A1 A0
Register A
TBA instruction
Fig. 3 Registers A, B and register E
ROM
TABP p instruction
Specifying address
p6 p5
PCH
p4 p3 p2 p1 p0
PCL
DR2 DR1 DR0 A3 A2 A1 A0
8
4
0
Low-order 4 bits
Register A (4)
Middle-order 4 bits
Register B (4)
Immediate field
value p
The contents of The contents of
register D
register A
High-order 2 bits
Register W5 (2)
Fig. 4 TABP p instruction execution example
8
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an
interrupt occurs, this register (SDP) is used to temporarily
store the contents of data pointer, carry flag, skip flag, register
A, and register B just before an interrupt until returning to the
original routine.
Unlike the stack registers (SKs), this register (SDP) is not
used when executing the subroutine call instruction and the
table reference instruction.
Program counter (PC)
Executing the subroutine
Executing the return or
call or table reference
table reference instruction
instruction
SK0
(SP) = 0
SK1
(SP) = 1
SK2
(SP) = 2
SK3
(SP) = 3
SK4
(SP) = 4
SK5
(SP) = 5
SK6
(SP) = 6
SK7
(SP) = 7
Stack pointer (SP) points “7” at reset or
returning from RAM back-up mode. It points “0”
by executing the first BM instruction, and the
contents of program counter is stored in SK0.
When the BM instruction is executed after eight
stack registers are used ((SP) = 7), (SP) = 0
and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(SP)
(SK0)
(PC)
➝
➝
➝
(5) Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the
contents of program counter (PC) just before branching until
returning to the original routine when;
• branching to an interrupt service routine (referred to as
an interrupt service routine),
• performing a subroutine call, or
• executing the table reference instruction (TABP p).
Stack registers (SKs) are eight identical registers, so that
subroutines can be nested up to 8 levels. However, one of
stack registers is used when using an interrupt service routine
or when executing a table reference instruction. Accordingly,
be careful not to stack over when performing these operations
together. The contents of registers SKs are destroyed when
8 levels are exceeded.
The register SK nesting level is pointed automatically by 3bit stack pointer (SP). The contents of the stack pointer (SP)
can be transferred to register A with the TASP instruction.
Figure 5 shows the stack registers (SKs) structure.
Figure 6 shows the example of operation at subroutine call.
0
000116
SUB1
Main program
Subroutine
Address
SUB1 :
0000 16 NOP
NOP
·
·
·
RT
0001 16 BM SUB1
0002 16 NOP
(PC)
(SP)
➝
➝
(7) Skip flag
Skip flag controls skip decision for the conditional skip
instructions and continuous described skip instructions. When
an interrupt occurs, the contents of skip flag is stored
automatically in the interrupt stack register (SDP) and the
skip condition is retained.
(SK 0)
7
Note: Returning to the BM instruction execution
address with the RT instruction, and the BM
instruction is equivalent to the NOP instruction.
Fig. 6 Example of operation at subroutine call
9
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page
and address). It determines a sequence in which instructions
stored in ROM are read. It is a binary counter that increments
the number of instruction bytes each time an instruction is
executed. However, the value changes to a specified address
when branch instructions, subroutine call instructions, return
instructions, or the table reference instruction (TABP p) is
executed.
Program counter consists of PCH (most significant bit to bit
7) which specifies to a ROM page and PCL (bits 6 to 0) which
specifies an address within a page. After it reaches the last
address (address 127) of a page, it specifies address 0 of the
next page (Figure 7).
Make sure that the PCH does not specify after the last page
of the built-in ROM.
Program counter (PC)
p6 p5 p4 p 3 p 2 p1 p0
a6 a5 a4 a3 a2 a1 a0
PCH
Specifying page
PCL
Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP)
Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and
consists of registers Z, X, and Y. Register Z specifies a RAM
file group, register X specifies a file, and register Y specifies
a RAM digit (Figure 8).
Register Y is also used to specify the port D bit position.
When using port D, set the port D bit position to register Y
certainly and execute the SD or RD instruction (Figure 9).
Specifying
RAM digit
Register Y (4)
Register X (4)
Register Z (2)
Specifying RAM file
Specifying RAM file group
Fig. 8 Data pointer (DP) structure
Specifying bit position
Set
D9
0
1
0
D6
1
Register Y (4)
D4
1
Port D output latch
Fig. 9 SD instruction execution example
10
D5
D0
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PROGRAM MEMORY (ROM)
1 word of ROM is composed of 10 bits. ROM is separated every
128 words by the unit of page (addresses 0 to 127). Table 1
shows the ROM size and pages. Figure 10 shows the ROM map
of M34570M8.
Table 1 ROM size and pages
Product
M34570M4
M34570M8
M34570E8
M34570MD
ROM size
(✕ 10 bits)
4096 words
8192 words
8192 words
16384 words
Pages
9 8
0000 16
007F16
0080 16
00FF16
0100 16
017F16
0180 16
7
6
5
4
3
2
1 0
Page 0
Interrupt address page
Page 1
Subroutine special page
Page 2
Page 3
32 (0 to 31)
64 (0 to 63)
64 (0 to 63)
0FFF16
Page 31
1FFF16
Page 127
128 (0 to 127)
16384 words
M34570ED
128 (0 to 127)
Note: When the TABP instruction is executed after executing
the SBK instruction, data in pages 64 to 127 can be
referred. When the TABP instruction is executed after
executing the RBK instruction, data in pages 0 to 63 can
be referred.
A top part of page 1 (addresses 008016 to 00FF16) is reserved
for interrupt addresses (Figure 11). When an interrupt occurs,
the address (interrupt address) corresponding to each interrupt
is set in the program counter, and the instruction at the interrupt
address is executed. When using an interrupt service routine,
write the instruction generating the branch to that routine at an
interrupt address.
Page 2 (addresses 010016 to 017F 16) is the special page for
subroutine calls. Subroutines written in this page can be called
from any page with the 1-word instruction (BM). Subroutines
extending from page 2 to another page can also be called with
the BM instruction when it starts on page 2.
ROM pattern (bits 9 to 0) of all addresses can be used as data
areas with the TABP p instruction.
Fig. 10 ROM map of M34570Mx
9 8
7
6
5
4
3
2
1 0
0080 16
External 0 interrupt address
0084 16
Timer 1 interrupt address
008616
Timer 2 interrupt address
008816
Timer 3 interrupt address
00FF16
Fig. 11 Interrupt address page (addresses 008016 to 00FF16) structure
11
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
DATA MEMORY (RAM)
1 word of RAM is composed of 4 bits, but 1-bit manipulation
(with the SB j, RB j, and SZB j instructions) is enabled for the
entire memory area. A RAM address is specified by a data
pointer. The data pointer consists of registers Z, X, and Y. Set a
value to the data pointer certainly when executing an instruction
to access RAM.
Table 2 shows the RAM size. Figure 12 shows the RAM map.
Table 2 RAM size
Product
M34570Mx
M34570Ex
RAM size
128 words ✕ 4 bits (512 bits)
RAM 128 words ✕ 4 bits (512 bits)
0
Register Z
Register X
0 1
2
3
... 6
7
0
Register Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
128 words
Fig. 12 RAM map
12
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual
address (interrupt address) according to each interrupt source.
An interrupt occurs when the following 3 conditions are satisfied.
• Interrupt enable flag (INTE) = “1” (Interrupt enabled)
• Interrupt enable bit = “1” (Interrupt request occurrence enabled)
• An interrupt activated condition is satisfied
(request flag = “1”)
Table 3 shows interrupt sources. (Refer to each interrupt request
flag for details of activated conditions.)
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every
interrupt enable/disable. Interrupts are enabled when INTE
flag is set to “1” with the EI instruction and disabled when
INTE flag is cleared to “0” with the DI instruction. When any
interrupt occurs, the INTE flag is automatically cleared to “0,”
so that other interrupts are disabled until the EI instruction is
executed.
(2) Interrupt enable bits (V10–V13, V20–V23)
Use an interrupt enable bit of interrupt control registers V1
and V2 to select the corresponding interrupt request or skip
instruction.
Table 4 shows the interrupt request flag, interrupt enable bit
and skip instruction.
Table 5 shows the interrupt enable bit function.
Table 3 Interrupt sources
Interrupt
Priority
Activated condition
Interrupt name
address
level
Address 0
1
External 0 interrupt Level change of
in page 1
INT pin
2
Timer 1 underflow Address 4
Timer 1 interrupt
in page 1
3
Timer 2 interrupt
Timer 2 underflow
Address 6
in page 1
4
Timer 3 interrupt
Timer 3 underflow
Address 8
in page 1
Table 4 Interrupt request flag, interrupt enable bit and skip
instruction
Request flag Enable bit Skip instruction
Interrupt name
EXF0
SNZ0
V10
External 0 interrupt
Timer 1 interrupt
T1F
V12
SNZT1
Timer 2 interrupt
T2F
T3F
V13
V20
SNZT2
SNZT3
Timer 3 interrupt
Table 5 Interrupt enable bit function
Interrupt enable bit
1
0
Occurrence of
interrupt request
Enabled
Disabled
Skip instruction
Invalid
Valid
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied,
the corresponding interrupt request flag is set to “1.” Each
interrupt request flag is cleared to “0” when either;
• an interrupt occurs, or
• the next instruction is skipped with a skip instruction.
Each interrupt request flag is set when the activated condition
is satisfied even if the interrupt is disabled by the INTE flag or
its interrupt enable bit. Once set, the interrupt request flag
retains set until a clear condition is satisfied.
Accordingly, an interrupt occurs when the interrupt disable
state is released while the interrupt request flag is set.
If more than one interrupt request flag is set when the interrupt
disable state is released, the interrupt priority level is as follows
shown in Table 3.
13
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is
as follows (Figure 14).
• Program counter (PC)
An interrupt address is set in program counter. The
address to be executed when returning to the main routine
is automatically stored in the stack register (SK).
• Interrupt enable flag (INTE)
INTE flag is cleared to “0” so that interrupts are disabled.
• Interrupt request flag
Only the request flag for the current interrupt source is
cleared to “0.”
• Data pointer, carry flag, skip flag, registers A and B
The contents of these registers and flags are stored
automatically in the interrupt stack register (SDP).
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address
is executed after a branch to a sequence for storing data into
stack register is performed. Write the branch instruction to
an interrupt service routine at an interrupt address.
Use the RTI instruction to return to main routine.
Interrupt enabled by executing the EI instruction is performed
after executing 1 instruction (just after the next instruction is
executed). Accordingly, when the EI instruction is executed
just before the RTI instruction, interrupts are enabled after
returning to the main routine. (Refer to Figure 13)
Main
routine
Interrupt
occurs
•Interrupt enable flag (INTE)
........................................................ 0 (Interrupt disabled)
•Interrupt request flag (only the flag for the current interrupt source)
........................................................................................ 0
•Data pointer, carry flag, registers A and B, skip flag
............... Stored in the interrupt stack register (SDP) automatically
Fig. 14 Internal state when interrupt occurs
INT pin
EXF0
V10
Address 0 in
page 1
Timer 1
underflow
T1F
V12
Address 4 in
page 1
Timer 2
underflow
T2F
V13
Address 6 in
page 1
(L → H or
H → L input)
Activated
condition
T3F
V20
INTE
Request
flag
(state retained)
Enable
bit
Enable
flag
Fig. 15 Interrupt system diagram
EI
RTI
: Interrupt enabled state
: Interrupt disabled state
Fig. 13 Program example of interrupt processing
14
•Stack register (SK)
........... The address of main routine to be executed when returning
Timer 3
underflow
Interrupt
service routine
Interrupt
is enabled
•Program counter (PC)
..................................................... Each interrupt address
Address 8 in
page 1
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(6) Interrupt control register
● Interrupt control register V1
Interrupt enable bits of external 0, timer 1 and timer 2 are
assigned to register V1. Set the contents of this register
through register A with the TV1A instruction. The TAV1
instruction can be used to transfer the contents of register
V1 to register A.
● Interrupt control register V2
Interrupt enable bit of timer 3 is assigned to register V2.
Set the contents of this register through register A with the
TV2A instruction. The TAV2 instruction can be used to
transfer the contents of register V2 to register A.
Table 6 Interrupt control register
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
Not used
V10
External 0 interrupt enable bit
at reset : 00002
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid)
0
1
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
0
1
0
1
Interrupt control register V2
V23
Not used
V22
Not used
V21
Not used
RAM back-up : 00002
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
at reset : 00002
0
1
0
1
0
1
0
R/W
at RAM back-up : 00002
R/W
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZT3 instruction is valid)
1
Interrupt enabled (SNZT3 instruction is invalid)
Note: “R” represents read enabled, and “W” represents write enabled.
V20
Timer 3 interrupt enable bit
15
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
conditions are satisfied. The interrupt occurs after 3 machine
cycles only when the three interrupt conditions are satisfied
on execution of instructions other than one-cycle instructions
(Refer to Figure 16).
(7) Interrupt sequence
Interrupts occur only when the respective INTE flag, interrupt
enable bits (V10–V13 and V20–V23), and interrupt request
flags (EXF0, T1F, T2F, T3F) are “1.” The interrupt actually
occurs 2 to 3 machine cycles after the cycle in which all three
● When an interrupt request flag is set after its interrupt is enabled (Note 1)
1 machine cycle
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
T3
f(XIN)
System clock=f(X IN)/4 selected
f(XIN)
System clock=f(X IN) selected
Interrupt enable
flag (INTE)
EI instruction
execution cycle
Interrupt disabled state
Interrupt enabled state
INT pin
Retaining level for 4 cycles or
more of f(X IN) is necessary.
External
interrupt
Flag
EXF0
Interrupt activated
condition satisfied
Timer 1,
timer 2,
timer 3
interrupts
Flag
T1F, T2F
T3F
Flag cleared
2 to 3 machine cycles
(Notes 2, 3)
Notes 1: The system clock = f(X IN)/4 is selected just after system is released from reset.
2: The address is stacked to the last cycle.
3: This interval of cycles depends on the instruction executed at the time when each
interrupt activated condition is satisfied.
Fig. 16 Interrupt sequence
16
Software starts
from interrupt address.
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
EXTERNAL INTERRUPTS
An external interrupt request occurs when a valid waveform (=
waveform causing the external 0 interrupt) is input to an interrupt
input pin (edge detection).
The external 0 interrupt can be controlled with the interrupt control
register I1.
Table 7 External interrupt activated condition
Name
Input pin
External 0 interrupt
P21/INT
Valid waveform
Valid waveform
selection bit (I12)
0
1
Falling waveform (“H”→“L”)
Rising waveform (“L”→“H”)
I12
Falling
0
One-sided edge
detection circuit
P21/INT
EXF0
External 0
interrupt
1
Rising
SNZI0
instruction
Skip
Fig. 17 External interrupt circuit structure
17
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(1) External 0 interrupt request flag (EXF0)
External 0 interrupt request flag (EXF0) is set to “1” when a
valid waveform is input to P21/INT pin.
The valid waveforms causing the interrupt must be retained
at their level for 4 cycles or more of the system clock (Refer
to Figure 16).
The state of EXF0 flag can be examined with the skip
instruction (SNZ0). Use the interrupt control register V1 to
select the interrupt or the skip instruction. The EXF0 flag is
cleared to “0” when an interrupt occurs or when the next
instruction is skipped with the skip instruction.
The P21/INT pin need not be selected the external interrupt
input INT function or the normal input port P21 function.
However, the EXF0 flag is set to “1” when a valid waveform
is input to P21/INT pin even if it is used as an input port P21.
(2) External interrupt control register
● Interrupt control register I1
Register I1 controls the valid waveform for the external 0
interrupt, the return level (valid level of wakeup signal) from
the RAM back-up and P21/INT pin function. Set the contents
of this register through register A with the TI1A instruction.
The TAI1 instruction can be used to transfer the contents of
register I1 to register A.
● External 0 interrupt activated condition
External 0 interrupt activated condition is satisfied when a
valid waveform is input to P21/INT pin.
The valid waveform can be selected from rising waveform or
falling waveform. An example of how to use the external 0
interrupt is as follows.
➀ Select the valid waveform with the bit 2 of register I1.
➁ Clear the EXF0 flag to “0” with the SNZ0 instruction.
➂ Set the NOP instruction for the case when a skip is performed
with the SNZ0 instruction.
➃ Set both the external 0 interrupt enable bit (V10 ) and the
INTE flag to “1.”
The external 0 interrupt is now enabled. Now when a valid
waveform is input to the P21/INT pin, the EXF0 flag is set to
“1” and the external 0 interrupt occurs.
Table 8 External interrupt control register
Interrupt control register I1
I13
Not used
I12
Interrupt valid waveform for INT pin/return
level selection bit (Note 2)
at reset : 00002
0
1
at RAM back-up : state retained
R/W
This bit has no function, but read/write is enabled.
0
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)/“L” level
1
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)/“H” level
I11
Not used
I10
Not used
0
1
0
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Depending on the input state of P21/INT pin, the external interrupt request flag EXF0 may be set to “1” when the contents
of I12 is changed. Accordingly, set a value to bit 2 of register I1 and execute the SNZ0 instruction to clear the EXF0 flag after
executing at least one instruction.
18
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
TIMERS
The 4570 Group has the programmable timers and a fixed
dividing frequency timer.
● Programmable timer
The programmable timer has a reload register and enables
the frequency dividing ratio to be set. It is decremented from a
set value n. When it underflows (count to n + 1), a timer interrupt
request flag is set to “1,” new data is loaded from the reload
register, and count continues (auto-reload function).
● Fixed dividing frequency timer
The fixed dividing frequency timer has the fixed frequency
dividing ratio (n). An interrupt request flag is set to “1” every n
count of a count pulse.
FF16
n : Counter initial value
Count starts
Reload
Reload
The contents of counter
n
1st underflow
2nd underflow
0016
Time
n+1 count
n+1 count
Timer 1 interrupt “1”
request flag
“0”
An interrupt occurs or
a skip instruction is executed.
Fig. 18 Auto-reload function
19
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
The 4570 Group timer consists of the following circuits.
• Prescaler : frequency divider
• Timer 1 : 10-bit programmable timer with the interrupt function
and the carrier wave output auto-control function
• Timer 2 : 8-bit programmable timer with the interrupt function
• Timer 3 : 8-bit programmable timer with the interrupt function
and the carrier wave generation function
• 16-bit timer
Prescaler, timer 1, timer 2 and timer 3 can be controlled with the
timer control registers W1, W2 and W3.
16-bit timer is the free-run counter without the control register.
Each function is described below.
Table 9 Function related timers
Circuit
Prescaler
Timer 1
Timer 2
Timer 3
16-bit timer
Structure
Count source
• Instruction clock
Frequency divider
10-bit programmable • Prescaler output (ORCLK)
Frequency
dividing ratio
4, 8
Use of output signal
1 to 1024
• Timer 1, 2 and 3 count sources
• Timer 1 interrupt
1 to 256
binary down counter
• Carrier wave generating circuit
• Carrier wave output auto-control
8-bit programmable
output (CARRY)
• Prescaler output (ORCLK)
• Timer 2 count source
• Timer 2 interrupt
binary down counter
• Timer 1 underflow
• Timer 3 count source
• Instruction clock
• 16-bit timer underflow
• TOUT output
8-bit programmable • Prescaler output (ORCLK)
binary down counter
• Timer 2 underflow
• f(XIN) or f(XIN)/2
16-bit fixed
• Instruction clock
dividing frequency
1 to 256
• Timer 3 interrupt
• Timer 1 count source
• Carrier wave
65536
• Watchdog timer
(15-th bit output is counted
twice.)
• Timer 2 count source
(16-bit timer underflow)
20
Control
register
W1
W1
(W5)
W2
W3
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Instruction clock
System clock
Prescaler
W13 (Note 1)
MR3
0
XIN
Frequency
dividing circuit
(divided by 4)
Internal clock generating
circuit (divided by 3)
1
0
1/4
0
1
1/8
1
ORCLK
W10(Note 1)
W11
0
0
W12
Timer 1(10)
1
T1F
Timer 1
interrupt
1
CARRY
Reload register R1 (10)
(T1AB)
(TAB1)
(Note 2)
(TAB1)
Register W5 Register B Register A
Timer 1 underflow signal
W21,W20
W23(Note 1)
00
01
0
10
1
Timer 2 (8)
11
T2F
Timer 2
interrupt
Reload register R2 (8)
(TR2AB)
T
2
A
B
(TAB2)
Register B
T
2
A
B
(TAB2)
Register A
Timer 2 underflow signal
Register B
Register A
(T3HAB)
Reload register R3H (8)
W31,W30
MR3
1/2
Reload control circuit
W33(Note1)
00
01
0
10
1
0
11
1
Not available
Timer 3(8)
T
CARRY
Q
(to timer 1/port CARR)
R
(T3AB)
W33
Reload register R3L (8)
(T3AB)
(TAB3)
Register B
T3F
(TAB3)
Timer 3
interrupt
Register A
16-bit timer underflow signal
16-bit timer (WDT)
Instruction clock
1
15 16
System reset
WRST instruction
S
Reset signal
R
WEF
WDF1 WDF2
Q
W22
D9/TOUT
0
1
D9 output
Timer 2 underflow signal
1/2
Notes 1: Count source is stopped by setting to “0.”
2: When the T1AB instruction is executed after
setting W10 to “1,” data is only written to reload
register R1.
Fig. 19 Timers structure
21
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Table 10 Timer control registers
at reset : 00002
Timer control register W1
W13
Prescaler control bit
W12
Prescaler dividing ratio selection bit
W11
Timer 1 count source selection bit
W10
Timer 1 control bit
0
1
Stop (prescaler state initialized)
Operating
0
Instruction clock divided by 4
1
0
Instruction clock divided by 8
Prescaler output (ORCLK)
1
Carrier output (CARRY)
0
1
Stop (state retained)
Operating
at reset : 00002
Timer control register W2
W23
Timer 2 control bit
W22
Port D9/TOUT pin function selection bit
at RAM back-up : 00002
0
Stop (state retained)
1
Operating
0
1
Port D9
TOUT pin
at RAM back-up : state retained
Timer 2 count source selection bits
W20
0
0
Prescaler output (ORCLK)
0
1
1
Timer 1 underflow signal
Instruction clock
0
1
1
W33
W32
16-bit timer underflow signal
at reset : 00002
Timer control register W3
Timer 3 control bit
Not used
at RAM back-up : state retained
0
Stop (state retained)
1
Operating
0
1
This bit has no function, but read/write is enabled.
Timer 3 count source selection bits
W30
Timer count value store register W5
R/W
Count source
W31 W30
W31
R/W
Count source
W21 W20
W21
R/W
0
0
Timer 2 underflow signal
0
1
1
0
Prescaler output (ORCLK)
1
1
f(XIN) or f(XIN)/2
Not available
at reset : 002
at RAM back-up : state retained
R/W
2-bit register. The contents of the high-order 2 bits (bits 9 and 8) of the 10-bit ROM pattern at address (D 2D1D0A3A2A1A0) in page
p specified by registers D and A is stored in this register W5 with the TABP p instruction.
In addition, data can be transferred between the low-order 2 bits of register A and this register W5 with the TW5A or TAW5
instruction. Data can be read/written to/from the high-order 2 bits of timer 1 with the T1AB or TAB1 instruction.
Note: “R” represents read enabled, and “W” represents write enabled.
22
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(1) Timer control registers
● Timer control register W1
Register W1 controls the count source and count operation
of timer 1, the frequency dividing ratio and count operation
of prescaler. Set the contents of this register through
register A with the TW1A instruction. The TAW1 instruction
can be used to transfer the contents of register W1 to
register A.
● Timer control register W2
Register W2 controls the count operation and count source
of timer 2 and D9/TOUT pin function. Set the contents of
this register through register A with the TW2A instruction.
The TAW2 instruction can be used to transfer the contents
of register W2 to register A.
● Timer control register W3
Register W3 controls the count operation and count source
of timer 3. Set the contents of this register through register
A with the TW3A instruction. The TAW3 instruction can
be used to transfer the contents of register W3 to register
A.
● Timer count value store register W5
2-bit register. The contents of the high-order 2 bits (bits 9
and 8) of the 10-bit ROM pattern at address in page p
specified by registers D and A is stored in this register
W5 with the TABP p instruction.
In addition, data can be transferred between the low-order
2 bits of register A and this register W5 with the TW5A or
TAW5 instruction. Data can be read/written to/from the
high-order 2 bits of timer 1 with the T1AB or TAB1
instruction.
(2) Precautions
Note the following for the use of timers.
● Prescaler
Stop the prescaler operation to change its frequency
dividing ratio.
● Count source
Stop timer 1, 2 or 3 counting to change its count source.
● Reading the timer count value
Stop each of the timers and then execute the TAB1, TAB2
or TAB3 instruction to read timer 1, 2 or 3 data.
● Writing to reload register R1
When writing data to reload register R1 while timer 1 is
operating, avoid a timing when timer 1 underflows.
● Writing to reload register R3H
When writing data to reload register R3H while timer 3 is
operating, avoid a timing when timer 3 underflows.
(3) Prescaler
Prescaler is a frequency divider. Its frequency dividing ratio
can be selected. The count source of prescaler is the
instruction clock.
Use the bit 2 of register W1 to select the prescaler dividing
ratio and the bit 3 to start and stop its operation. When the bit
3 of register W1 is cleared to “0,” prescaler is initialized, and
the output signal (ORCLK) stops.
(4) Timer 1 (interrupt function)
Timer 1 is a 10-bit binary down counter with the timer 1 reload
register (R1). The 10-bit data can be set in timer 1 through
registers A, B and W5. Set bits 0 to 3 to register A, bits 4 to
7 to regiser B and bits 8 to 9 to register W5 to set data to
timer 1. Also, ROM pattern (bits 0 to 9) can be set to registers
A, B and W5 with the TABP p instruction. Execute the T1AB
instruction to set data in timer 1.
When timer 1 stops, 10-bit data can be set simultaneously in
timer 1 and the reload register (R1) with the T1AB instruction.
When timer 1 is operating, data can be set only in the reload
register (R1) with the T1AB instruction.
When setting the next count data to reload register R1 while
timer 1 is operating, be sure to set data before timer 1
underflows.
Timer 1 starts counting after the following process;
➀ set data in timer 1,
➁ select the count source with bit 1 of register W1,
➂ set the bit 0 of register W1 to “1.”
Once count is started, when timer 1 underflows (the next
count pulse is input after the contents of timer 1 becomes
“0”), the timer 1 interrupt request flag (T1F) is set to “1,” new
data is loaded from reload register R1, and count continues
(auto-reload function).
When a value set in reload register R1 is n, timer 1 divides
the count source signal by n + 1 (n = 0 to 1023).
Data can be read from timer 1 to registers A, B and W5.
Stop counting and then execute the TAB1 instruction to read
its data.
(5) Timer 2 (interrupt function)
Timer 2 is an 8-bit binary counter with the timer 2 reload
register (R2). Data can be set simultaneously in timer 2 and
the reload register (R2) with the TAB2 instrucion. Also, data
can be set only in the reload register (R2) with the TR2AB
instruction.
Timer 2 starts counting after following process;
➀ set data in timer 2,
➁ select the count source with bits 0 and 1 of register W2,
➂ set the bit 3 of register W2 to “1.”
Once count is started, when timer 2 underflows (the next
count pulse is input after the contents of timer 2 becomes
“0”), the timer 2 interrupt request flag (T2F) is set to “1,” new
data is loaded from reload register R2, and count continues
(auto-reload function).
When a value set in reload register R2 is n, timer 2 divides
the count source signal by n+1 (n = 0 to 255).
Data can be read from timer 2 to registers A and B with the
TAB2 instruction. Stop counting and then execute the TAB2
instruction to read its data.
23
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(6) Timer 3
Timer 3 is an 8-bit binary down counter with the timer 3 reload
registers (R3H, R3L). Data can be set simultaneously in timer
3 and the reload register (R3L) with the T3AB instruction.
Data can be set in reload register R3H with the T3HAB
instruction.
Timer 3 starts counting after the following process;
➀ set data in timer 3,
➁ select the count source with the bits 1 and 0 of register
W3,
➂ set the bit 3 of register W3 to “1.”
The f(XIN) or f(XIN)/2 is selected as the count source by setting
W31 to “1” and W30 to “0.”
When the f(XIN) is selected as the system clock (bit 3 of clock
control register MR= “0”), f(X IN) is selected as the count
source.
When the f(XIN)/4 is selected as the system clock (bit 3 of
clock control register MR= “1”), f(XIN)/2 is selected as the
count source.
Once count is started, when timer 3 underflows (the next count
pulse is input after the contents of timer 3 become “0”), the
timer 3 interrupt request flag (T3F) is set to “1,” new data is
loaded from reload register R3H, and count coutinues (autoreload function).
When the timer 3 underflows again after auto-reload is
performed, the timer 3 interrupt request flag (T3F) is set to
“1” and new data is reloaded from the reload register R3L
and count continues. Timer 3 reloads data from reload register
R3H or R3L alternately every underflow.
When the T3AB instruction is executed while timer 3 is
operating, new data is set in timer 3 and reload register R3L,
count is started again at the next machine cycle. At the next
underflow, data is reloaded from R3H and count continues
regardless that auto-reload is performed from reload register
R3H or R3L at the previous underflow.
Data can be read from timer 3 through registers A and B.
Stop counting and then execute the TAB3 instruction to read
its data. Timer 3 can be also used as the carrier wave
generating circuit.
(7) Timer output pin (D9/TOUT)
Timer output pin (D 9/T OUT) is used to output the timer 2
underflow signal.
The D9/TOUT pin function can be selected by the bit 2 of register
W2.
(8) Timer interrupt request flags (T1F, T2F, T3F)
Each timer interrupt request flag is set to “1” when each timer
underflows. The state of these flags can be examined with
the skip instructions (SNZT1, SNZT2, SNZT3).
Use the interrupt control registers V1 and V2 to select an
interrupt or a skip instruction.
An interrupt request flag is cleared to “0” when an interrupt
occurs or when the next instruction is skipped with a skip
instruction.
24
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a
program runs wild. Watchdog timer consists of 16-bit timer (WDT),
watchdog timer enable flag (WEF), and watchdog timer flags
(WDF1, WDF2).
Timer WDT starts downcounting the instruction clocks as the
count source immediately after system is released from reset.
The underflow signal is generated when the count value reaches
“000016.” This underflow signal can be used as the timer 2 count
source.
When the WRST instruction is executed after system is released
from reset, the WEF flag is set to “1.” At this time, the watchdog
timer starts operating.
When the count value of timer WDT reaches “BFFF 16 ” or
“3FFF16,” WDF1 flag is set to “1.” Then, if the WRST instruction
is not executed while the______
timer WDT counts 32767, the WDF2
flag is set to “1” and the RESET pin outputs “L” level to reset the
microcomputer. In software using the watchdog timer, make sure
that the WRST instruction is executed in 32766 machine cycles
or less in order to keep the microcomputer operating normally.
To prevent the watchdog timer from stopping in the event of
misoperation, the WEF flag is designed not to be initialized once
the WRST instruction has been executed. Note also that, if the
WRST instruction is never executed, the watchdog timer does
not start.
FFFF16
BFFF16
3FFF16
Value of timer WDT
0000 16
Flag WEF
Flag WDF1
Flag WDF2
RESET pin output
WRST instruction WRST instruction
System reset
execution
execution
Fig. 20 Watchdog timer function
The contents of the WEF flag, the WDF1 and WDF2 flags and
the timer WDT are initialized at the RAM back-up mode.
However, if the WDF2 flag is set to “1” at the same time that the
microcomputer enters the RAM back-up mode, system reset may
be performed.
When using the watchdog timer and the RAM back-up mode,
initialize the WDF1 flag with the WRST instruction just before
the microcomputer enters the RAM back-up mode (refer to Figure
21).
•
••
•
•
•
WRST
; Clear WDF1 flag
EPOF
; POF instruction execution enabled
POF
Oscillation stop (RAM back-up mode)
Fig. 21 Program example to enter the RAM back-up mode
when using the watchdog timer
25
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
CARRIER WAVE GENERATING CIRCUIT
The 4570 Group has a carrier wave generating circuit that
generates the transfer waveform for various remote control carrier
wave.
The carrier wave generating circuit outputs the signal inverted
every timer 3 underflow (CARRY) from port CARR.
When using the carrier wave generating circuit, select the f(XIN)
or f(XIN)/2 for the timer 3 count source (W31=“1”, W30=“0”).
When the bit 3 of the clock control register MR is “0” (system
clock=f(XIN)), f(XIN) is selected as the count source.
When the bit 3 of the clock control register MR is “1” (system
clock=f(XIN)/4), f(XIN)/2 is selected as the count source.
Set the count value corresponding to “L” interval of carrier wave
output to timer 3 reload register R3L.
Set the count value corresponding to “H” interval of carrier wave
output to timer 3 reload register R3H.
Also, timer 1 can auto-control the carrier wave output of port
CARR by setting the carrier wave output control register (C2).
When timer 3 is stopped, the output level of port CARR is
initialized. (“L” level)
(1) Carrier wave output control register (C2)
Timer 1 can auto-control the output enable interval and the
output disable interval of the carrier wave output from port
CARR by setting the bit 0 of register C2 to “1.” Set the
contents of this register through register A with the TC2A
instruction.
The setting of the output enable/disable interval is described
below.
➀ Validate the carrier wave output auto-control function
(C20=“1”).
➁ Set the count value (“L” interval of carrier wave output) to
timer 3 and reload register R3L.
➂ Set the count value (“H” interval of carrier wave output) to
timer 3 reload register R3H.
➃ Set the count value (the output enable interval of carrier
wave from port CARR) to timer 1.
➄ Select the carrier wave (W11 = “1”) as the timer 1 count
source.
➅ Operate timer 1 (W10=“1”).
➆ Operate timer 3 (W33=“1”).
➇ Set the next count value (the output disable interval of
carrier wave from port CARR) to reload register R1 before
timer 1 underflow occurs.
The carrier wave is output from port CARR until the first timer
3 underflow occurs. The output of the carrier wave from port
CARR is disabled and the next count value is loaded from
reload register R1 to timer 1 by the first timer 1 underflow.
Then, the output of carrier wave is disabled until the second
timer 1 underflow occurs. Also, the next enable interval of
the carrier wave output can be set by setting the third count
value to timer 1 reload register R1 before the second timer 1
underflow occurs.
If the carrier wave output auto-control function is invalidated
(C20=“0”) while the carrier wave output is auto-controlled, the
output of port CARR retains the state when the auto-control
is invalidated regardless of timer 1 underflow. This state can
be terminated by timer 1 stop (W10=“0”).
When the carrier wave output auto-control function is validated
(C20=“1”) again after it is invalidated (C20=“0”), the autocontrol of carrier wave output is started again when the next
timer 1 underflow occurs.
Stop the timer 3 and invalidate the auto-control function by
timer 1 to use the port CARR output contorl bit (C21).
(2) Notes when using the carrier wave output auto-control function
● Set the timer 1 and register C2 before timer 3 is started to
operate (W33=“1”).
● Stop the timer 1 (W1 0 =“0”) after stopping the timer 3
(W33=“0”) while the carrier wave output is disabled in order
to stop the carrier wave output auto-control operation.
● If the carrier wave output auto-control function is invalidated
(C20=“0”) while the carrier wave output is auto-controlled,
the output of port CARR retains the state when the autocontrol is invalidated regardless of timer 1 underflow.
When the carrier wave output auto-control function is
validated (C20 =“1”) again after it is invalidated (C20 =“0”),
the auto-control by timer 1 is validated again when the next
timer 1 underflow occurs.
However, when the carrier wave output auto-control bit (C20)
is changed during timer 1 underflow, the error-operation may
occur.
● When the carrier wave output auto-control function is
selected, use the carrier wave CARRY as the timer 1 count
source.
If the ORCLK is used as the count source, a short pulse
may occur in port CARR output because ORCLK is not
synchronized with the carrier wave.
● When the carrier wave output auto-control function is
selected and data is set to reload register R1 while timer 1
is operating, avoid the timing that the contents of timer 1
becomes “0” to execute the T1AB instruction.
Table 11 Carrier wave output control register
Carrier wave output control register C2
C21
Port CARR output control bit
C20
Carrier wave output auto-control bit
Note: “W” represents write enabled.
26
at reset : 002
at RAM back-up : 002
0
Port CARR “L” level output
1
Port CARR “H” level output
0
Auto-control output by timer 1 is invalid
Auto-control output by timer 1 is valid
1
W
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
TW3A
instruction
Machine cycle
Timer 3 start
▼
f(XIN) (divided by 3)
“H”
“L”
2
Timer 3
1 0 3 2 1 0 2 1 0 3 2 1 0 2 1 0
R3H
Timer 3 underflow
CARRY
“H”
“L”
“H” interval
“L” interval
set by R3H set by
R3L
“a”
➝
1
▼
Interval “a” is set
by timer 1
▼
(C20)
“1”
“0”
“c”
“b”
“d”
Timer 1 start
▼
▼
Timer 1 underflow
“H” interval
set by R3H
▼
Port CARR output
0216
R3L
“H”
“L”
set by
R3L
“H”
“L”
0316
Timer 3 reload register R3L
“1”
“0”
“L” interval
CARRY
R3H
R3L
Timer 3 reload register R3H
Interval “b” is set by
reload register R1
Interval “c” is set by
reload register R1
Interval “d” is set by
reload register R1
Carrier wave output start
“1”
“0”
Register C2 0
“1”
“0”
▼
➝
(C20)
▼
Carrier wave output start
0
(C20)
➝
Timer 1 underflow
▼
“H”
“L”
1 (C20)
➝
Port CARR output
▼
“H”
“L”
0 (C20)
➝
CARRY
1
Fig. 22 Carrier wave output auto-control by timer 1
27
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
RESET FUNCTION
____________
System reset is performed by applying “L” level to RESET pin
for 1 machine cycle or more when the following condition is
satisfied;
• the value of supply voltage is the minimum value or more of
the recommended operating conditions.
____________
Then when “H” level is applied to RESET pin, software starts
from address 0 in page 0.
f(XIN)
RESET
“H”
“L”
(Note)
f(XIN) is counted
10757 to 10786 times
Software start
(Address 0 in page 0)
Note: The number of clock cycles depends on the internal state of
the microcomputer when reset is performed.
Fig. 23 Reset release timing
Reset input
=
1machine cycle or more
f(XIN) is counted
10757 to 10786 times
0.85VDD
Software start
(Address 0 in page 0)
RESET
0.3VDD
Note: Keep the value of supply voltage the minimum value or more
of the recommended operating conditions.
(Note)
Fig. 24 RESET pin input waveform and reset operation
(1) Power-on reset
Reset can be automatically performed at power on (poweron reset) by the built-in power-on reset circuit. When the builtin power-on reset circuit is used, the time for the supply voltage
to reach the minimum operating voltage must be set to 100
µ s or less. If the rising time exceeds 100 µs, connect a
capacitor between the RESET pin and VSS at the shortest
distance, and input “L” level to RESET pin until the value of
supply voltage reaches the minimum operating voltage.
VDD
Pull-up
transistor
RESET
pin
Internal reset
signal
Power-on
reset circuit
Voltage drop detection circuit
(Note)
This symbol represents a parasitic
diode.
Applied potential to RESET pin must
Power-on
be VDD or less.
Fig. 25 Power-on reset circuit example
28
Reset state
Watchdog timer
output
WEF
Note:
Power-on reset circuit
output voltage
Internal reset signal
Reset released
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(2) Internal state at reset
Table 12 shows port state at reset, and Figure 26 shows
internal state at reset (they are retained after system is
released from reset).
The contents of timers, registers, flags and RAM except those
shown in Figure 26 are undefined, so set the initial values to
them.
Table 12 Port state at reset
Name
D0–D8, D9/TOUT
P00–P03
P10–P13
P20, P21/INT
P30–P33
Function
D0–D8, D9
P00–P03
P10–P13
P20, P21
P30–P33
P40–P43
P40–P43
CARR
CARR
Notes 1: Output latch is set to “1.”
2: The pull-up transistor is turned off.
State
High impedance (Note 1)
“H” (VDD) level (Note 1)
High impedance
High impedance (Note 1)
High impedance (Note 2)
“L” (VSS) level
• Program counter (PC) ............................................................................................
0 0 0 0 0 0
0
0
0
0
0
0
0
0
Address 0 in page 0 is set to program counter.
• Interrupt enable flag (INTE) ................................................................................... 0
• Power down flag (P) ...............................................................................................0
(Interrupt disabled)
• External 0 interrupt request flag (EXF0) ................................................................0
• Interrupt control register V1 ...................................................................................
0 0 0 0
• Interrupt control register V2 ...................................................................................
0 0 0 0
(Interrupt disabled)
(Interrupt disabled)
• Interrupt control register I1 ....................................................................................
0 0 0 0
• Timer 1 interrupt request flag (T1F) ...................................................................... 0
• Timer 2 interrupt request flag (T2F) ...................................................................... 0
• Timer 3 interrupt request flag (T3F) ...................................................................... 0
• Watchdog timer flags (WDF1, WDF2) ................................................................... 0
• Watchdog timer enable flag (WEF) ....................................................................... 0
• Timer control register W1 ......................................................................................
0 0 0 0
• Timer control register W2 ......................................................................................
0 0 0 0
• Timer control register W3 ......................................................................................
0 0 0 0
(Prescaler and timer 1 stopped)
(Timer 2 stopped)
(Timer 3 stopped)
• Timer count value store register W5 .....................................................................
0 0
• Clock control register MR ......................................................................................
1 0 0 0
• 8-bit general-purpose register SI ...........................................................................
0 0 0 0 0 0 0 0
• Carrier wave output control register C2 .................................................................
0 0
• Key-on wakeup control register K0 .......................................................................
0 0 0 0
• Pull-up control register PU0 ...................................................................................
0 0 0 0
• Carry flag (CY) ....................................................................................................... 0
• Register A ..............................................................................................................
0 0 0 0
• Register B ..............................................................................................................
0 0 0 0
• Register D ..............................................................................................................
✕ ✕ ✕
• Register E ..............................................................................................................
✕ ✕ ✕ ✕ ✕ ✕ ✕ ✕
• Register X ..............................................................................................................
0 0 0 0
• Register Y ..............................................................................................................
0 0 0 0
• Register Z ...............................................................................................................
✕ ✕
• Stack pointer (SP) ..................................................................................................
1 1 1
“✕” represents undefined.
Fig. 26 Internal state at reset
29
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
VOLTAGE DROP DETECTION CIRCUIT
The built-in voltage drop detection circuit is designed to detect a
drop in voltage and to reset the microcomputer if the supply
voltage drops below a set value.
The voltage drop detection circuit is not operated at the RAM
back-up mode.
Pull-up transistor
Internal reset signal
RESET pin
Power-on
reset circuit
Voltage drop detection circuit
Watchdog timer output
WEF
Fig. 27 Voltage drop detection reset circuit
VDD
Reset voltage
The microcomputer starts operation
after the f(XIN) is counted 10757 to
10786 times.
Internal reset
signal
Note: Set the VDCE pin to “H” level to operate the
voltage drop detection circuit.
Fig. 28 Voltage drop detection circuit operation waveform
30
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
RAM BACK-UP MODE
Table 13 Functions and states retained at RAM back-up
The 4570 Group has the RAM back-up mode.
When the EPOF and POF instructions are executed continuously,
system enters the RAM back-up state.
The POF instruction is equivalent to the NOP instruction when
the EPOF instruction is not executed before the POF instruction.
As oscillation is stopped retaining RAM, the function of reset
circuit and states at RAM back-up mode, power dissipation can
be reduced without losing the contents of RAM.
Table 13 shows the function and states retained at RAM backup. Figure 29 shows the state transition.
Function
Program counter (PC), registers A, B,
(1) Identification of the start condition
Warm start (return from the RAM back-up mode) or cold start
(return from the normal reset state) can be identified by
examining the state of the power down flag (P) with the SNZP
instruction.
Interrupt control registers V1, V2
Interrupt control register I1
(2) Warm start condition
When the external wakeup signal is input after the system
enters the RAM back-up mode by executing the EPOF and
POF instructions continuously, the CPU starts executing the
software from address 0 in page 0. In this case, the P flag is
“1.”
(3) Cold start condition
The CPU starts executing the software from address 0 in
page 0 when;
• reset pulse is input to RESET pin, or
• reset by watchdog timer is performed, or
• voltage drop detection circuit detects the voltage drop.
In this case, the P flag is “0.”
carry flag (CY), stack pointer (SP) (Note 2)
Contents of RAM
Port level
Clock control register MR
Timer control register W1
Timer control registers W2, W3
Timer count value store register W5
Carrier wave output control register C2
8-bit general-purpose register SI
Timer 1 function
Timer 2 function
Timer 3 function
Pull-up control register PU0
Key-on wakeup control register K0
External 0 interrupt request flag (EXF0)
Timer 1 interrupt request flag (T1F)
Timer 2 interrupt request flag (T2F)
Timer 3 interrupt request flag (T3F)
Watchdog timer flag 1 (WDF1)
Watchdog timer flag 2 (WDF2)
Watchdog timer enable flag (WEF)
16-bit timer (WDT)
Interrupt enable flag (INTE)
RAM back-up
✕
O
O
O
✕
O
O
✕
O
✕
O
✕
(Note 3)
(Note 3)
O
O
✕
✕
(Note 3)
(Note 3)
✕ (Note 4)
✕ (Note 4)
✕ (Note 4)
✕ (Note 4)
✕
Notes 1: “O” represents that the function can be retained, and
“✕” represents that the function is initialized.
Registers and flags other than the above are undefined
at RAM back-up, and set an initial value after returning.
2: The stack pointer (SP) points the level of the stack
register and is initialized to “1112” at RAM back-up.
3: The state of the timer is undefined.
4: Initialize the watchdog timer with the WRST instruction,
and then execute the EPOF and POF instructions.
31
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(4) Return signal
An external wakeup signal is used to return from the RAM
back-up mode because the oscillation is stopped. Table 14
shows the return condition for each return source.
(5) Port P4 control registers
• Key-on wakeup control register K0
Register K0 controls the port P4 key-on wakeup function.
Set the contents of this register through register A with
the TK0A instruction. In addition, the TAK0 instruction can
be used to transfer the contents of register K0 to register
A.
• Pull-up control register PU0
Register PU0 controls the ON/OFF of the port P4 pull-up
transistor. Set the contents of this register through register
A with the TPU0A instruction. In addition, the TAPU0
instruction can be used to transfer the contents of register
PU0 to register A.
Table 14 Return source and return condition
External wakeup signal
Return source
32
Ports P0, P1
and P4
Return condition
Remarks
Return by an external falling edge Port P0 shares the falling edge detection circuit with ports P1 and P4.
input (“H”→“L”).
Key-on wakeup functions of ports P0 and P1 are always valid. The keyon wakeup function valid/invalid of port P4 can be controlled with register
K0. Set the port using the key-on wakeup function selected to “H” level
P21/INT pin
before going into the RAM back-up mode.
Return by an external “H” level or Select the return level (“L” level or “H” level) with the bit 2 of register I1
“L” level input.
The EXF0 flag is not set.
according to the external state before going into the RAM back-up mode.
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
POF instruction
is executed
A
B
f(XIN) stop
(Stabilizing time a )
Reset
f(XIN) oscillation
Return input
(Stabilizing time a )
(RAM back-up
mode)
Stabilizing time a : The time required to stabilize f(XIN) oscillation is automatically
generated by hardware.
Fig. 29 State transition
Power down flag P
POF instruction
S
Reset input or voltage
drop detection circuit
output
R
Software start
Q
P = “1”
?
Yes
No
● Set source
● Clear source
Cold start
POF instruction is executed
Reset input
Fig. 30 Set source and clear source of the P flag
Warm start
Fig. 31 Start condition identified example using the SNZP
instruction
Table 15 Key-on wakeup control register and pull-up control register
Key-on wakeup control register K0
K03
K02
K01
K00
at reset : 00002
Port P43 key-on wakeup
0
control bit
Port P42 key-on wakeup
1
0
control bit
1
Port P41 key-on wakeup
control bit
0
1
Port P40 key-on wakeup
0
control bit
1
Pull-up control register PU0
PU03
PU02
PU01
Port P43 pull-up transistor
control bit
Port P42 pull-up transistor
control bit
Port P41 pull-up transistor
control bit
at RAM back-up : state retained
R/W
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
at reset : 00002
at RAM back-up : state retained
0
1
Pull-up transistor OFF
Pull-up transistor ON
0
Pull-up transistor OFF
1
0
Pull-up transistor ON
Pull-up transistor OFF
1
Pull-up transistor ON
R/W
Port P40 and P01 pull-up transistor
Pull-up transistor OFF
0
PU00
Pull-up transistor ON
control bit
1
Note: “R” represents read enabled, and “W” represents write enabled.
33
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
CLOCK CONTROL
The clock control circuit consists of the following circuits.
● Clock generating circuit
● Control circuit to stop the clock oscillation
● System clock selection circuit
● Instruction clock generating circuit
● Control circuit to return from the RAM back-up mode
System clock
Frequency dividing
circuit
(divided by 4)
XIN
XOUT
Oscillation
circuit
MR 3
1
0
Internal clock
generating circuit
(devided by 3)
Insturuction clock
Counter
Wait time control
circuit (Note)
POF instruction
R
S
Q
Software
start signal
RESET
Key-on wakeup control register
K00,K0 1,K02,K0 3
Port P4 0
MultiPort P4 1
Falling detected
plexer
Port P4 2
Port P4 3
I12
“L” level
Ports P0, P1
0
P21/INT
1
“H” level
Note: The wait time control circuit is automatically used to generate the time required to stabilize the
f(XIN) oscillation.
Fig. 32 Clock control circuit structure
Clock signal f(XIN) is obtained by externally connecting a ceramic
resonator. Connect this external circuit to pins XIN and XOUT at
the shortest distance. A feedback resistor is built-in between pins
XIN and XOUT.
M34570
XIN
ROM ORDERING METHOD
Please submit the information described below when ordering
Mask ROM.
(1) M34570M4-XXXFP Mask ROM Order Confirmation Form,
M34570M8-XXXFP Mask ROM Order Confirmation Form, or
M34570MD-XXXFP Mask ROM Order Confirmation Form
.............................................................................................. 1
(2) Data to be written into mask ROM .......................... EPROM
(three sets containing the identical data)
(3) Mark Specification Form .................................................... 1
34
CIN
Note: Externally connect a
damping resistor Rd
depending on the
XOUT
oscillation frequency.
(A feedback resistor is
built-in.)
Rd
Use the resonator
manufacturer’s
recommended value
COUT
because constants such
as capacitance depend
on the resonator.
Fig. 33 Ceramic resonator external circuit
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
LIST OF PRECAUTIONS
➀ Noise and latch-up prevention
Connect a capacitor on the following condition to prevent noise
and latch-up;
• connect a capacitor (approx. 0.1 µF) between pins VDD and
VSS at the shortest distance,
• equalize its wiring in width and length, and
• use the thickest wire.
In the One Time PROM version, CNVSS pin is also used as
VPP pin. Accordingly, when using this pin, connect this pin to
V SS through a resistor about 5 kΩ (connect this resistor to
CNVSS/VPP pin as close as possible).
➉ Notes on timer 1 count source
When the carrier wave output auto-control function is selected,
use the carrier wave CARRY as the timer 1 count source.
If the ORCLK is used as the count source, a short pulse may
occur in port CARR output because ORCLK is not
synchronized with the carrier wave.
11
Notes on writing to reload register R1 when carrier wave output
auto-control operation
When the carrier wave output auto-control function is selected
and data is set to reload register R1 while timer 1 is operating,
avoid the timing that the contents of timer 1 becomes “0” to
execute the T1AB instruction.
12
One Time PROM version
The operating power voltage of the One Time PROM version
is within the range of 2.5 V to 5.5 V.
13
Multifunction
Note that the port D9 output function and P21 input function
can be used even when TOUT and INT pin function is selected.
14
POF instruction
Note that system cannot enter the RAM back-up state when
executing only the POF instruction.
Execute the POF instruction immediately after executing the
EPOF instruction to enter the RAM back-up.
Be sure to disable interrupts by executing the DI instruction
before executing the EPOF instruction.
15
Program counter
Make sure that the PCH does not specify after the last page of
the built-in ROM.
16
P21/INT pin
When the interrupt valid waveform of P21/INT pin is changed
with the bit 2 of register I1 in software, be careful about the
following notes.
• Clear the bit 0 of register V1 to “0” and then change the
interrupt valid waveform of P21 /INT pin with the bit 2 of
register I1 (refer to Figure 34➀).
• Clear the bit 2 of register I1 to “0” and execute the SNZ0
instruction to clear the EXF0 flag after executing at least
one instruction (refer to Figure 34➁). Depending on the input
state of the P21/INT pin, the external 0 interrupt request flag
(EXF0) may be set to “1” when the interrupt valid waveform
is changed.
➁ Prescaler
Stop the prescaler operation to change its frequency dividing
ratio.
➂ Count source
Stop timer 1, timer 2 or timer 3 counting to change its count
source.
➃ Reading the timer count value
Stop each of the timers and then execute the TAB1, TAB2 or
TAB3 instruction to read timer 1, 2 or 3 data.
➄ Writing to reload register R1
When writing the data to reload register R1 while timer 1 is
operating, avoid a timing when timer 1 underflows.
➅ Writing to reload register R3H
When writing the data to reload register R3H while timer 3 is
operating, avoid a timing when timer 3 underflows.
➆ Notes on timer 3 operation start
Set the timer 1 and register C2 before timer 3 is started to
operate (W33=“1”).
➇ Notes on carrier wave output auto-control operation stop
Stop the timer 1 (W10=“0”) after stopping the timer 3 (W33=“0”)
while the carrier wave output is disabled in order to stop the
carrier wave output auto-control operation.
➈ Notes on setting carrier wave output control regiter C2
If the carrier wave output auto-control function is invalidated
(C20=“0”) while the carrier wave output is auto-controlled, the
output of port CARR retains the state when the auto-control is
invalidated regardless of timer 1 underflow.
When the carrier wave output auto-control function is validated
(C20=“1”) again after it is invalidated (C20=“0”), the auto-control
by timer 1 is validated again when the next timer 1 underflow
occurs.
However, when the carrier wave output auto-control bit (C20)
is changed during timer 1 underflow, the error-operation may
occur.
...
LA
4
TV1A
LA
TI1A
; (✕✕✕02)
; The SNZ0 instruction is valid
; Change of the interrupt valid waveform
➁
NOP
SNZ0
NOP
...
➀
4
;The SNZ0 instruction is executed
✕ : this bit is not related to the setting of INT.
Fig. 34 External 0 interrupt program example
35
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
SYMBOL
The symbols shown below are used in the following list of instruction function and machine instructions.
Contents
Symbol
A
B
Register A (4 bits)
DR
Register D (3 bits)
Register E (8 bits)
E
C2
SI
V1
V2
I1
W1
W2
W3
W5
K0
PU0
MR
X
Y
Z
DP
PC
PCH
PCL
SK
SP
CY
R1
R2
R3H
R3L
T1
T2
T3
T1F
Register B (4 bits)
Carrier wave output control register C2 (2 bits)
Symbol
WDF1
WDF2
WEF
INTE
EXF0
Contents
Watchdog timer flag 1
Watchdog timer flag 2
Watchdog timer enable flag
Interrupt enable flag
External 0 interrupt request flag
8-bit general-purpose register SI (8 bits)
Interrupt control register V1 (4 bits)
P
Power down flag
Interrupt control register V2 (4 bits)
D
Port D (10 bits)
Interrupt control register I1 (4 bits)
Timer control register W1 (4 bits)
P0
Port P0 (4 bits)
Port P1 (4 bits)
Timer control register W2 (4 bits)
Timer control register W3 (4 bits)
Timer count value store register W5 (2 bits)
Key-on wakeup control register K0 (4 bits)
Pull-up control register PU0 (4 bits)
Clock control register MR (4 bits)
Register X (4 bits)
P1
P2
P3
P4
x
y
z
p
Port P2 (2 bits)
Port P3 (4 bits)
Port P4 (4 bits)
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Hexadecimal variable
Register Y (4 bits)
Register Z (2 bits)
n
Hexadecimal constant which represents the
immediate value
Data pointer (10 bits)
i
Hexadecimal constant which represents the
(It consists of registers X, Y, and Z)
Program counter (14 bits)
j
immediate value
Hexadecimal constant which represents the
A3A2A1A0
immediate value
Binary notation of hexadecimal variable A
High-order 7 bits of program counter
Low-order 7 bits of program counter
Stack register (14 bits ✕ 8)
Stack pointer (3 bits)
Carry flag
Timer 1 reload register
Timer 2 reload register
Timer 3 reload register
(same for others)
←
Direction of data movement
↔
?
Data exchange between a register and memory
( )
Decision of state shown before “?”
Contents of registers and memories
Timer 3 reload register
—
Negate, Flag unchanged after executing
Timer 1
Timer 2
M(DP)
instruction
RAM address pointed by the data pointer
Timer 3
T2F
Timer 1 interrupt request flag
Timer 2 interrupt request flag
T3F
Timer 3 interrupt request flag
a
p, a
Label indicating address a6 a5 a4 a3 a2 a1 a0
C
+
Hex. C + Hex. number x (also same for others)
Label indicating address a6 a5 a4 a3 a2 a1 a0
in page p5 p4 p3 p2 p1 p0
x
Note : The 4570 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not
increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count
becomes “1” if the TABP p, RT, or RTS instruction is skipped.
36
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
LIST OF INSTRUCTION FUNCTION
(A) ← (B)
TBA
(B) ← (A)
TYA
TEAB
(A) ← (Y)
(Y) ← (A)
Grouping
Function
Mnemonic
(A) ← → (M(DP))
XAMI j
(X) ← (X)EXOR(j)
j = 0 to 15
(Y) ← (Y) + 1
TMA j
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
LA n
(A) ← n
(B) ← (E7–E4)
(A) ← (E3–E0)
TABP p
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(DR2–DR0) ← (A2–A0)
j = 0 to 3
RB j
(Mj(DP)) ← 0
j = 0 to 3
SZB j
(Mj(DP)) = 0 ?
j = 0 to 3
A3–A0)
(W5) ← (ROM(PC))9 to 8
TAZ
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
TAX
(A) ← (X)
(A) ← (ROM(PC))3 to 0
(PC) ← (SK(SP))
LXY x, y
(A2–A0) ← (SP2–SP0)
(A3) ← 0
(X) ← x, x = 0 to 15
(Y) ← y, y = 0 to 15
LZ z
(Z) ← z, z = 0 to 3
INY
(Y) ← (Y) + 1
Arithmetic operation
TASP
AM
(A) ← (A) + (M(DP))
AMC
(A) ← (A) + (M(DP))
Branch operation
(A2–A0) ← (DR2–DR0)
(A3) ← 0
SEAM
(A) = (M(DP)) ?
SEA n
(A) = n ?
n = 0 to 15
Ba
(PCL) ← a6–a0
BL p, a
(PCH) ← p
(PCL) ← a6–a0
BLA p
(PCH) ← p
(PC L ) ← (DR 2 –DR 0 ,
A3–A0)
BM a
(PCH) ← 2
(PCL) ← a6–a0
+ (CY)
(CY) ← Carry
An
(A) ← (A) + n
n = 0 to 15
AND
(A) ← (A)AND(M(DP))
DEY
(Y) ← (Y) – 1
OR
(A) ← (A)OR(M(DP))
TAM j
(A) ← (M(DP))
(X) ← (X)EXOR(j)
SC
(CY) ← 1
j = 0 to 15
RC
(CY) ← 0
(A) ← → (M(DP))
SZC
(CY) = 0 ?
CMA
(A) ← (A)
BML p, a (SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← a6–a0
BMLA p
(PCL) ← (DR2–DR0,
A3–A0)
XAMD j
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
j = 0 to 15
RAR
→ CY → A3A2A1A0
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Return operation
(X) ← (X)EXOR(j)
j = 0 to 15
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
RTI
XAM j
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
Subroutine operation
TAD
(SP) ← (SP) – 1
RAM addresses
(Mj(DP)) ← 1
(PC L ) ← (DR 2 –DR 0 ,
(B) ← (ROM(PC))7 to 4
RAM to register transfer
SB j
j = 0 to 15
n = 0 to 15
TDA
Function
Mnemonic
(E7–E4) ← (B)
(E3–E0) ← (A)
TABE
Grouping
Bit operation
TAB
TAY
Register to register transfer
Function
Comparison
operation
Mnemonic
RAM to register transfer
Grouping
RT
(PC) ← (SK(SP))
(SP) ← (SP) – 1
RTS
(PC) ← (SK(SP))
(SP) ← (SP) – 1
(Y) ← (Y) – 1
37
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
LIST OF INSTRUCTION FUNCTION (CONTINUED)
Grouping
Mnemonic
Function
Grouping
Mnemonic
Function
Grouping Mnemonic
Function
(B) ← (T37–T34)
DI
(INTE) ← 0
TAW1
(A) ← (W1)
EI
(INTE) ← 1
TW1A
(W1) ← (A)
SNZ0
(EXF0) = 1 ?
TAW2
(A) ← (W2)
(T37–T34) ← (B)
TW2A
(W2) ← (A)
(R3L3–R3L0) ← (A)
(T33–T30) ← (A)
TAB3
(A) ← (T33–T30)
T3AB
Interrupt operation
instruction,
(EXF0) ← 0
TAW3
(A) ← (W3)
I12 = 1 : (INT0) = “H” ?
I12 = 0 : (INT0) = “L” ?
TW3A
(W3) ← (A)
TAV1
(A) ← (V1)
TAW5
(A) ← (0, 0, W51, W50)
TV1A
(V1) ← (A)
TW5A
(W51, W50) ← (A1, A0)
TAV2
(A) ← (V2)
TAB1
(W5) ← (T19–T18)
SNZI0
Timer operation
After skipping the next
T3HAB
(R3H7–R3H4) ← (B)
(R3H3–R3H0) ← (A)
SNZT1
(T1F) = 1 ?
After skipping the next
instruction,
(T1F) ← 0
SNZT2
(B) ← (T17–T14)
TV2A
(V2) ← (A)
TAI1
(A) ← (I1)
TI1A
(I1) ← (A)
(R3L7–R3L4) ← (B)
(T2F) = 1 ?
After skipping the next
instruction,
(A) ← (T13–T10)
(T2F) ← 0
T1AB
at timer 1 stop (W10=0)
Timer operation
(R19–R18) ← (W5)
(T19–T18) ← (W5)
(R17–R14) ← (B)
(T17–T14) ← (B)
(R13–R10) ← (A)
(T13–T10) ← (A)
At timer 1 operating
(W10=1),
(R19–R18) ← (W5)
(R17–R14) ← (B)
(R13–R10) ← (A)
TAB2
(B) ← (T27–T24)
(A) ← (T23–T20)
T2AB
(R27–R24) ← (B)
(T27–T24) ← (B)
(R23–R20) ← (A)
(T23–T20) ← (A)
TR2AB
(R27–R24) ← (B)
(R23–R20) ← (A)
38
SNZT3
(T3F) = 1 ?
After skipping the next
instruction,
(T3F) ← 0
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
LIST OF INSTRUCTION FUNCTION (CONTINUED)
Mnemonic
Function
Function
NOP
(PC) ← (PC) + 1
OP0A
(P0) ← (A)
POF
RAM back-up mode
IAP1
(A) ← (P1)
EPOF
POF instruction valid
OP1A
(P1) ← (A)
SNZP
(P) = 1 ?
IAP2
(A1, A0) ← (P21, P20)
WRST
(WDF1) ← 0, (WEF) ←1
TAMR
(A) ← (MR3–MR0)
TMRA
(MR3–MR0) ← (A)
TABSI
(B) ← (SI7–SI4)
IAP3
Input/Output operation
Mnemonic
(A) ← (P0)
(A3, A2) ← (0)
(A) ← (P3)
OP3A
(P3) ← (A)
IAP4
(A) ← (P4)
CLD
(D) ← 1
RD
(D(Y)) ← 0
(Y) = 0 to 9
SD
(A) ← (SI3–SI0)
TSIAB
(SI7–SI4) ← (B)
(SI3–SI0) ← (A)
SBK
When executing the
TABP p instruction,
p6 ← 1
(D(Y)) ← 1
(Y) = 0 to 9
Carrier wave generating operation
Grouping
IAP0
Other operation
Grouping
TK0A
(K0) ← (A)
TAK0
(A) ← (K0)
TPU0A
(PU0) ← (A)
TAPU0
(A) ← (PU0)
TC2A
(C21, C20) ← (A1, A0)
RBK
When executing the
TABP p instruction,
p6 ← 0
39
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
INSTRUCTION CODE TABLE
—
010000 011000
—
D9—D4 000000 000001000010 000011000100 000101000110 000111001000 001001001010 001011001100 001101001110 001111
010111 011111
D3— Hex.
notation
D0
00
01
03
02
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10—17 18—1F
0000
0
NOP
BLA
SZB
BMLA RBK TASP
0
A
0
LA
0
TABP TABP TABP TABP
0*
16* 32** 48** BML BML
BL
BL
BM
B
0001
1
—
CLD
SZB
1
—
SBK
TAD
A
1
LA
1
TABP TABP TABP TABP
BML
1*
17* 33** 49** BML
BL
BL
BM
B
0010
2
POF
—
SZB
2
—
—
TAX
A
2
LA
2
TABP TABP TABP TABP
2*
18* 34** 50** BML BML
BL
BL
BM
B
0011
3
SZB
3
—
—
TAZ
A
3
LA
3
TABP TABP TABP TABP
BML BML
3*
19* 35** 51**
BL
BL
BM
B
0100
4
DI
RD
—
—
RT
TAV1
A
4
LA
4
TABP TABP TABP TABP
4*
20* 36** 52** BML BML
BL
BL
BM
B
0101
5
EI
SD
SEAn —
RTS TAV2
A
5
LA
5
TABP TABP TABP TABP
5*
21* 37** 53** BML BML
BL
BL
BM
B
0110
6
RC
—
SEAM —
RTI
—
A
6
LA
6
TABP TABP TABP TABP
BML
6*
22* 38** 54** BML
BL
BL
BM
B
0111
7
SC
DEY
—
—
—
A
7
LA
7
TABP TABP TABP TABP
7*
23* 39** 55** BML BML
BL
BL
BM
B
1000
8
—
AND
—
LZ
0
—
A
8
LA
8
TABP TABP TABP TABP
8*
24* 40** 56** BML BML
BL
BL
BM
B
1001
9
—
OR
LZ
1
—
A
9
LA
9
TABP TABP TABP TABP
9*
25* 41** 57** BML BML
BL
BL
BM
B
1010
A
AM TEAB TABE SNZI0
LZ
2
—
A
10
LA
10
TABP TABP TABP TABP
10*
26* 42** 58** BML BML
BL
BL
BM
B
1011
B
AMC
1100
C
1101
D
1110
1111
SNZP INY
—
SNZ0
TDA
—
—
—
LZ
3
EPOF
A
11
LA
11
TABP TABP TABP TABP
11*
27* 43** 59** BML BML
BL
BL
BM
B
TYA CMA
—
—
RB
0
SB
0
A
12
LA
12
TABP TABP TABP TABP
12*
28* 44** 60** BML BML
BL
BL
BM
B
—
RAR
—
—
RB
1
SB
1
A
13
LA
13
TABP TABP TABP TABP
13*
29* 45** 61** BML BML
BL
BL
BM
B
E
TBA
TAB
—
TV2A
RB
2
SB
2
A
14
LA
14
TABP TABP TABP TABP
BML BML
14*
30* 46** 62**
BL
BL
BM
B
F
—
TAY
SZC TV1A
RB
3
SB
3
A
15
LA
15
TABP TABP TABP TABP
15*
31* 47** 63** BML BML
BL
BL
BM
B
—
The above table shows the relationship between machine language codes and machine language instructions. D 3—D 0 show the loworder 4 bits of the machine language code, and D 9—D 4 show the high-order 6 bits of the machine language code. The hexadecimal
representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each
instruction is shown. Do not use code marked "—."
** cannot be used at M34570M4.
For M34570M4/M8/E8, the SBK and RBK instructions cannot be used.
For M34570MD/ED, the pages which is referred with the TABP instruction (*, **) can be switched with the SBK and RBK instructions.
After executing the SBK instruction, the pages which can be referred with the TABP instruction are 64 to 127. (ex. TABP 0 →TABP 64)
After executing the RBK instruction, the pages which can be referred with the TABP instruction are 0 to 63.
If the SBK instruction is not executed, the pages which can be referred with the TABP instruction are always 0 to 63.
The codes for the second word of a two-word instruction are described below.
The second word
40
BL
1p
paaa
aaaa
BML
BLA
1p
paaa
aaaa
1p
pp00
pppp
BMLA
1p
pp00
pppp
SEA
00
0111
nnnn
SZD
00
0010
1011
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
INSTRUCTION CODE TABLE (CONTINUED)
D3— Hex.
20
D0
notation
21
23
22
24
25
—
—
WRST
TMA TAM XAM XAMI XAMD
LXY
0
0
0
0
0
—
—
IAP1 TAB2 SNZT2
—
—
TMA TAM XAM XAMI XAMD
LXY
1
1
1
1
1
TAMR IAP2 TAB3 SNZT3
—
—
TMA TAM XAM XAMI XAMD
LXY
2
2
2
2
2
1
—
—
0010
2
—
TW5A
—
T3AB
—
0011
3
—
—
OP3A
—
—
0100
4
—
—
—
—
—
—
0101
5
—
—
—
—
—
0110
6
—
TMRA
—
—
0111
7
—
TI1A
—
1000
8
—
—
1001
9
—
1010
A
1011
OP1A T2AB
2F 30—3F
—
0001
TW3A OP0A T1AB
2E
IAP0 TAB1 SNZT1
—
28
2D
2A
0
27
111111
29
0000
26
110000
—
D9—D4 100000 100001100010 100011100100 100101100110 100111101000 101001101010 101011101100 101101101110 101111
2B
2C
—
—
—
—
TMA TAM XAM XAMI XAMD
LXY
3
3
3
3
3
IAP4
—
—
—
—
TMA TAM XAM XAMI XAMD
LXY
4
4
4
4
4
—
—
—
—
—
—
TMA TAM XAM XAMI XAMD
LXY
5
5
5
5
5
—
TAK0
—
—
—
—
—
TMA TAM XAM XAMI XAMD
LXY
6
6
6
6
6
—
—
TAPU0
—
—
—
—
—
TMA TAM XAM XAMI XAMD
LXY
7
7
7
7
7
—
TSIAB
—
—
—
TABSI
—
—
—
TMA TAM XAM XAMI XAMD
LXY
8
8
8
8
8
—
—
—
—
—
—
—
—
—
TC2A
TMA TAM XAM XAMI XAMD
LXY
9
9
9
9
9
—
—
—
TR2AB
—
—
—
—
—
—
—
TMA TAM XAM XAMI XAMD
LXY
10
10
10
10
10
B
—
TK0A
—
—
TAW1
—
—
—
—
—
—
TMA TAM XAM XAMI XAMD
LXY
11
11
11
11
11
1100
C
—
—
—
—
TAW2
—
—
—
—
—
—
TMA TAM XAM XAMI XAMD
LXY
12
12
12
12
12
1101
D
—
—
TPU0A T3HAB TAW3
—
—
—
—
—
—
TMA TAM XAM XAMI XAMD
LXY
13
13
13
13
13
1110
E
TW1A
—
—
—
—
—
—
—
—
—
—
TMA TAM XAM XAMI XAMD
LXY
14
14
14
14
14
1111
F
TW2A
—
—
—
TAW5
—
—
—
—
—
—
TMA TAM XAM XAMI XAMD
LXY
15
15
15
15
15
TAI1 IAP3
The above table shows the relationship between machine language codes and machine language instructions. D 3–D0 show the
low-order 4 bits of the machine language code, and D 9–D4 show the high-order 6 bits of the machine language code. The
hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the
first word of each instruction is shown. Do not use code marked “–.”
The codes for the second word of a two-word instruction are described below.
The second word
BL
1p
paaa
aaaa
BML
1p
paaa
aaaa
BLA
1p
pp00
pppp
BMLA
1p
pp00
pppp
SEA
00
0111
nnnn
SZD
00
0010
1011
41
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Register to register transfer
instructions
Hexadecimal
notation
Function
Skip condition
Carry flag CY
Instruction code
Parameter
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS
Detailed description
TAB
0
0
0
0
0
1
1
1
1
0
0
1
E
1
1
(A) ← (B)
–
–
Transfers the contents of register B to register A.
TBA
0
0
0
0
0
0
1
1
1
0
0
0
E
1
1
(B) ← (A)
–
–
Transfers the contents of register A to register B.
TAY
0
0
0
0
0
1
1
1
1
1
0
1
F
1
1
(A) ← (Y)
–
–
Transfers the contents of register Y to register A.
TYA
0
0
0
0
0
0
1
1
0
0
0
0
C
1
1
(Y) ← (A)
–
–
Transfers the contents of register A to register Y.
TEAB
0
0
0
0
0
1
1
0
1
0
0
1
A
1
1
(E7–E4) ← (B)
–
–
Transfers the contents of registers A and B to register E.
–
–
Transfers the contents of register E to registers A and B.
(E3–E0) ← (A)
TABE
0
0
0
0
1
0
1
0
1
0
0
2
A
1
1
(B) ← (E7–E4)
(A) ← (E3–E0)
TDA
0
0
0
0
1
0
1
0
0
1
0
2
9
1
1
(DR2–DR0) ← (A2–A0)
–
–
Transfers the contents of register A to register D.
TAD
0
0
0
1
0
1
0
0
0
1
0
5
1
1
1
(A2–A0) ← (DR2–DR0)
–
–
Transfers the contents of register D to register A.
–
–
Transfers the contents of register Z to register A.
(A3) ← 0
TAZ
0
0
0
1
0
1
0
0
1
1
0
5
3
1
1
(A1, A0) ← (Z1, Z0)
(A3, A2) ← 0
TAX
0
0
0
1
0
1
0
0
1
0
0
5
2
1
1
(A) ← (X)
–
–
Transfers the contents of register X to register A.
TASP
0
0
0
1
0
1
0
0
0
0
0
5
0
1
1
(A2–A0) ← (SP2–SP0)
(A3) ← 0
–
–
Transfers the contents of stack pointer (SP) to register A.
LXY x, y
1
1
x3 x2 x1 x0 y3 y2 y1 y0
3
x
y
1
1
(X) ← x, x = 0 to 15
(Y) ← y, y = 0 to 15
Continuous
description
–
Loads the value x in the immediate field to register X, and the value y in the immediate field to register
Y.
When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed
RAM addresses
and other LXY instructions coded continuously are skipped.
LZ z
0
0
0
1
0
0
1
0
z1 z0
0
4
8
1
1
(Z) ← z, z = 0 to 3
1
1
(Y) ← (Y) + 1
–
–
Loads the value z in the immediate field to register Z.
(Y) = 0
–
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the
+z
INY
0
0
0
0
0
1
0
0
1
1
0
1
3
next instruction is skipped.
DEY
0
0
0
0
0
1
0
1
1
1
0
1
7
1
1
(Y) ← (Y) – 1
(Y) = 15
–
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y
is 15, the next instruction is skipped.
42
43
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
TAM j
1
0
1
1
0
0
j
j
j
j
Hexadecimal
notation
2 C
j
1
1
Function
(A) ← (M(DP))
(X) ← (X)EXOR(j)
Skip condition
Carry flag CY
Instruction code
Parameter
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
–
–
After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between
register X and the value j in the immediate field, and stores the result in register X.
–
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
Detailed description
j = 0 to 15
XAM j
1
0
1
1
0
1
j
j
j
j
2 D
j
1
1
(A) ← → (M(DP))
(X) ← (X)EXOR(j)
performed between register X and the value j in the immediate field, and stores the result in register X.
RAM to register transfer
j = 0 to 15
XAMD j
XAMI j
TMA j
1
1
1
0
0
0
1
1
1
1
1
0
1
1
1
1
0
1
j
j
j
j
j
j
j
j
j
j
j
j
2 F
2 E
2 B
j
j
j
1
1
1
1
1
1
(A) ← → (M(DP))
(Y) = 15
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
(X) ← (X)EXOR(j)
j = 0 to 15
performed between register X and the value j in the immediate field, and stores the result in register X.
Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y
(Y) ← (Y) – 1
is 15, the next instruction is skipped.
(A) ← → (M(DP))
(Y) = 0
–
After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is
(X) ← (X)EXOR(j)
performed between register X and the value j in the immediate field, and stores the result in register X.
j = 0 to 15
(Y) ← (Y) + 1
Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the
next instruction is skipped.
(M(DP)) ← (A)
(X) ← (X)EXOR(j)
–
–
After transferring the contents of register A to M(DP), an exclusive OR operation is performed between
register X and the value j in the immediate field, and stores the result in register X.
(A) ← n
Continuous
–
Loads the value n in the immediate field to register A.
n = 0 to 15
description
j = 0 to 15
LA n
0
0
0
1
1
1
n
n
n
n
0 7
n
1
1
When the LA instructions are continuously coded and executed, only the first LA instruction is executed
Arithmetic operation
and other LA instructions coded continuously are skipped.
TABP p
0
0
1
0
p5 p4 p3 p2 p1 p0
0 8
+p
p
1
3
(SP) ← (SP) + 1
–
–
Transfers bits 9 and 8 to register W5, bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 9
(SK(SP)) ← (PC)
(PCH) ← p
to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in
page p.
(PCL) ← (DR2–DR0, A3–A0)
When this instruction is executed, 1 stage of stack register is used.
(W5) ← (ROM(PC))9 to 8
(B) ← (ROM(PC))7 to 4
When this instruction is executed after executing the SBK instruction, pages 64 to 127 are specified.
When this instruction is executed after executing the RBK instruction, pages 0 to 63 are specified.
(A) ← (ROM(PC))3 to 0
When this instruction is executed after system is released from reset or returned from RAM back-up,
(PC) ← (SK(SP))
(SP) ← (SP) – 1
pages 0 to 63 are specified.
(Note)
Note: p is 0 to 31 for M34570M4 and p is 0 to 63 for M34570E8 and M34570M8.
p is 0 to 127 for M34570ED and M34570MD, and p6 is specified with the SBK and RBK instructions.
44
45
MITSUBISHI MICROCOMPUTERS
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4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
Hexadecimal
notation
Function
Skip condition
Carry flag CY
Instruction code
Parameter
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
–
AM
0
0
0
0
0
0
1
0
1
0
0 0 A
1
1
(A) ← (A) + (M(DP))
–
AMC
0
0
0
0
0
0
1
0
1
1
0 0 B
1
1
(A) ← (A) + (M(DP))+ (CY)
(CY) ← Carry
–
An
0
0
0
1
1
0
n
n
n
n
0 6 n
1
1
(A) ← (A) + n
Overflow = 0
Arithmetic operation
Bit operation
Comparison
operation
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY
remains unchanged.
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag
CY.
–
n = 0 to 15
46
Detailed description
Adds the value n in the immediate field to register A.
The contents of carry flag CY remains unchanged.
Skips the next instruction when there is no overflow as the result of operation.
AND
0
0
0
0
0
1
1
0
0
0
0 1 8
1
1
(A) ← (A)AND(M(DP))
–
–
Performs the AND operation between the contents of register A and the contents of M(DP), and stores
the result in register A.
OR
0
0
0
0
0
1
1
0
0
1
0 1 9
1
1
(A) ← (A)OR(M(DP))
–
–
Performs the OR operation between the contents of register A and the contents of M(DP), and stores
the result in register A.
SC
0
0
0
0
0
0
0
1
1
1
0 0 7
1
1
(CY) ← 1
–
1
Sets carry flag CY to “1.”
RC
0
0
0
0
0
0
0
1
1
0
0 0 6
1
1
(CY) ← 0
–
0
Clears carry flag CY to “0.”
SZC
0
0
0
0
1
0
1
1
1
1
0 2 F
1
1
(CY) = 0 ?
(CY) = 0
–
Skips the next instruction when the contents of carry flag CY is “0.”
CMA
0
0
0
0
0
1
1
1
0
0
0 1 C
1
1
(A) ← (A)
–
–
Stores the one’s complement for register A’s contents in register A.
RAR
0
0
0
0
0
1
1
1
0
1
0 1 D
1
1
→ CY → A3A2A1A0
–
SB j
0
0
0
1
0
1
1
1
j
j
0 5
C
+j
1
1
(Mj(DP)) ← 1
j = 0 to 3
–
–
Sets the contents of bit j (bit specified by the value j in the immediate field) of M(DP) to “1.”
RB j
0
0
0
1
0
0
1
1
j
j
0 4
C
+j
1
1
(Mj(DP)) ← 0
j = 0 to 3
–
–
Clears the contents of bit j (bit specified by the value j in the immediate field) of M(DP) to “0.”
SZB j
0
0
0
0
1
0
0
0
j
j
0 2
j
1
1
(Mj(DP)) = 0 ?
j = 0 to 3
(Mj(DP)) = 0
j = 0 to 3
–
Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field)
of M(DP) is “0.”
SEAM
0
0
0
0
1
0
0
1
1
0
0 2
6
1
1
(A) = (M(DP)) ?
(A) = (M(DP))
–
Skips the next instruction when the contents of register A is equal to the contents of M(DP).
SEA n
0
0
0
0
1
0
0
1
0
1
0 2
5
2
2
(A) = n ?
n = 0 to 15
(A) = n
–
Skips the next instruction when the contents of register A is equal to the value n in the immediate field.
0
0
0
1
1
1
n
n
n
n
0 7
n
0/1 Rotates the contents of register A including the contents of carry flag CY to the right by 1 bit.
47
MITSUBISHI MICROCOMPUTERS
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SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Branch operation
instructions
Hexadecimal
notation
Function
Skip condition
Carry flag CY
Instruction code
Parameter
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
Detailed description
Ba
0
1
1
a6 a5 a4 a3 a2 a1 a0
1 8 a
+a
1
1
(PCL) ← a6–a0
–
–
Branch within a page : Branches to address a in the identical page.
BL p, a
0
0
1
1
p4 p3 p2 p1 p0
0 E p
+p
2
2
(PCH) ← p
(PCL) ← a6–a0
–
–
Branch out of a page : Branches to address a in page p.
1
0
p5 a6 a5 a4 a3 a2 a1 a0
2 p a
+a
0
0
0
0
1
0
0 1
0
–
–
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and
A in page p.
1
0
p5 p4 0
0
p3 p2 p1 p0
2 p
p
0
1
0
a6 a5 a4 a3 a2 a1 a0
1 a
a
–
–
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
–
–
Call the subroutine : Calls the subroutine at address a in page p.
–
–
Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers
D and A in page p.
–
–
Returns from interrupt service routine to main routine.
Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous
1
(Note)
BLA p
BM a
0
0
0
0
2
2
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(Note)
1
1
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
Subroutine operation
(PCH) ← 2
(PCL) ← a6–a0
BML p, a
0
0
1
1
0
p4 p3 p2 p1 p0
1
0
p5 a6 a5 a4 a3 a2 a1 a0
2 p a
+a
0
0
0
1
1
0
0 3
0
1
0
p5 p4 0
0
p3 p2 p1 p0
2 p
p
0 C p
+p
2
2
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
BMLA p
0
0
0
0
(PCL) ← a6–a0
(Note)
2
2
(SP) ← (SP) + 1
(SK(SP)) ← (PC)
(PCH) ← p
(PCL) ← (DR2–DR0, A3–A0)
(Note)
Return operation
RTI
0
0
0
1
0
0
0
1
1
0
0 4
6
1
1
(PC) ← (SK(SP))
(SP) ← (SP) – 1
description of the LA/LXY instruction, register A and register B to the states just before interrupt.
RT
0
0
0
1
0
0
0
1
0
0
0 4
4
1
2
(PC) ← (SK(SP))
–
–
Returns from subroutine to the routine called the subroutine.
Skip unconditionally
–
Returns from subroutine to the routine called the subroutine, and skips the next instruction unconditionally.
(SP) ← (SP) – 1
RTS
0
0
0
1
0
0
0
1
0
1
0 4
5
1
2
(PC) ← (SK(SP))
(SP) ← (SP) – 1
Note: p is 0 to 31 for M34570M4 and p is 0 to 63 for M34570E8 and M34570M8.
p is 0 to 127 for M34570ED and M34570MD, and p6 is specified with the SBK and RBK instructions.
48
49
MITSUBISHI MICROCOMPUTERS
MITSUBISHI MICROCOMPUTERS
4570 Group
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
Hexadecimal
notation
Function
Skip condition
Carry flag CY
Instruction code
Parameter
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
Detailed description
DI
0
0
0
0
0
0
0
1
0
0
0 0
4
1
1
(INTE) ← 0
–
–
Clears the interrupt enable flag INTE to “0,” and disables the interrupt.
EI
0
0
0
0
0
0
0
1
0
1
0 0
5
1
1
(INTE) ← 1
–
–
Sets the interrupt enable flag INTE to “1,” and enables the interrupt.
SNZ0
0
0
0
0
1
1
1
0
0
0
0 3
8
1
1
(EXF0) = 1 ?
After skipping the next instruction,
(EXF0) = 1
–
Skips the next instruction when the contents of EXF0 flag is “1.”
After skipping, clears the EXF0 flag to “0.”
(INT) = “H”
–
When bit 2 (I12) of register I1 is “1” : Skips the next instruction when the level of INT pin is “H.”
–
When bit 2 (I12) of register I1 is “0” : Skips the next instruction when the level of INT pin is “L.”
Timer operation
Interrupt operation
(EXF0) ← 0
SNZI0
0
0
0
0
1
1
1
0
1
0
0 3
A
1
1
I12 = 1 : (INT) = “H” ?
However, I12 = 1
I12 = 0 : (INT) = “L” ?
(INT) = “L”
However, I12 = 0
TAV1
0
0
0
1
0
1
0
1
0
0
0 5 4
1
1
(A) ← (V1)
–
–
Transfers the contents of interrupt control register V1 to register A.
TV1A
0
0
0
0
1
1
1
1
1
1
0 3 F
1
1
(V1) ← (A)
–
–
Transfers the contents of register A to interrupt control register V1.
TAV2
0
0
0
1
0
1
0
1
0
1
0 5 5
1
1
(A) ← (V2)
–
–
Transfers the contents of interrupt control register V2 to register A.
TV2A
0
0
0
0
1
1
1
1
1
0
0 3 E
1
1
(V2) ← (A)
–
–
Transfers the contents of register A to interrupt control register V2.
TAI1
1
0
0
1
0
1
0
0
1
1
2 5 3
1
1
(A) ← (I1)
–
–
Transfers the contents of interrupt control register I1 to register A.
TI1A
1
0
0
0
0
1
0
1
1
1
2 1 7
1
1
(I1) ← (A)
–
–
Transfers the contents of register A to interrupt control register I1.
TAW1
1
0
0
1
0
0
1
0
1
1
2 4 B
1
1
(A) ← (W1)
–
–
Transfers the contents of timer control register W1 to register A.
TW1A
1
0
0
0
0
0
1
1
1
0
2 0 E
1
1
(W1) ← (A)
–
–
Transfers the contents of register A to timer control register W1.
TAW2
1
0
0
1
0
0
1
1
0
0
2 4 C
1
1
(A) ← (W2)
–
–
Transfers the contents of timer control register W2 to register A.
TW2A
1
0
0
0
0
0
1
1
1
1
2 0 F
1
1
(W2) ← (A)
–
–
Transfers the contents of register A to timer control register W2.
TAW3
1
0
0
1
0
0
1
1
0
1
2 4 D
1
1
(A) ← (W3)
–
–
Transfers the contents of timer control register W3 to register A.
TW3A
1
0
0
0
0
1
0
0
0
0
2 1 0
1
1
(W3) ← (A)
–
–
Transfers the contents of register A to timer control register W3.
TAW5
1
0
0
1
0
0
1
1
1
1
2 4 F
1
1
(A) ← (0, 0, W51, W50)
–
–
Transfers the contents of timer count value store register W5 to the low-order 2 bits of register A. The
contents of the high-order 2 bits of register A is set to “0.”
TW5A
1
0
0
0
0
1
0
0
1
0
2 1 2
1
1
(W51, W50) ← (A1, A0)
–
50
–
Transfers the contents of the low-order 2 bits of register A to timer count value store register W5.
51
MITSUBISHI MICROCOMPUTERS
MITSUBISHI MICROCOMPUTERS
4570 Group
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
TAB1
1
0
0
1
1
1
0
0
0
0
Hexadecimal
notation
2 7 0
1
1
Function
(W5) ← (T19, T18)
Skip condition
Carry flag CY
Instruction code
Parameter
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
Detailed description
–
–
Transfers the contents of the high-order 2 bits of timer 1 to register W5, and transfers the contents of
(B) ← (T17–T14)
(A) ← (T13–T10)
T1AB
1
0
0
0
1
1
0
0
0
0
2 3 0
1
1
At timer 1 stop (W10=0),
(R19, R18) ← (W5)
the low-order 8 bits of timer 1 to registers A and B.
–
–
When stopping (W10=0), transfers the contents of register W5 to the contents of the high-order 2 bits of
timer 1 and of the timer 1 reload register, and transfers the contents of registers A and B to the contents
(T19, T18) ← (W5)
of the low-order 8 bits of timer 1 and of the timer 1 reload register.
(R17–R14) ← (B)
(T17–T14) ← (B)
When operating (W10=1), transfers the contents of register W5 to the contents of the high-order 2 bits
of the timer 1 reload register, and transfers the contents of registers A and B to the contents of the low-
(R13–R10) ← (A)
order 8 bits of the timer 1 reload register.
(T13–T10) ← (A)
At timer 1 operating (W10=1),
(R19, R18) ← (W5)
Timer operation
(R17–R14) ← (B)
(R13–R10) ← (A)
TAB2
1
0
0
1
1
1
0
0
0
1
2 7 1
1
1
(B) ← (T27–T24)
(A) ← (T23–T20)
–
–
Transfers the contents of timer 2 to registers A and B.
T2AB
1
0
0
0
1
1
0
0
0
1
2 3 1
1
1
(R27–R24) ← (B)
(T27–T24) ← (B)
–
–
Transfers the contents of registers A and B to timer 2 and timer 2 reload register.
–
–
Transfers the contents of registers A and B to timer 2 reload register.
–
–
Transfers the contents of timer 3 to registers A and B.
–
–
Transfers the contents of registers A and B to timer 3 and timer 3 reload register R3L.
–
–
Transfers the contents of registers A and B to timer 3 reload register R3H.
(R23–R20) ← (A)
(T23–T20) ← (A)
TR2AB
1
0
0
0
1
1
1
0
1
0
2 3 A
1
1
(R27–R24) ← (B)
(R23–R20) ← (A)
TAB3
1
0
0
1
1
1
0
0
1
0
2 7 2
1
1
(B) ← (T37–T34)
(A) ← (T33–T30)
T3AB
1
0
0
0
1
1
0
0
1
0
2 3 2
1
1
(R3L7–R3L4) ← (B)
(T37–T34) ← (B)
(R3L3–R3L0) ← (A)
(T33–T30) ← (A)
T3HAB
1
0
0
0
1
1
1
1
0
1
2 3 D
1
1
(R3H7–R3H4) ← (B)
(R3H3–R3H0) ← (A)
52
53
MITSUBISHI MICROCOMPUTERS
MITSUBISHI MICROCOMPUTERS
4570 Group
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Type of
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
instructions
SNZT1
1
0
1
0
0
0
0
0
0
0
Hexadecimal
notation
2 8 0
1
1
Function
(T1F) = 1 ?
Skip condition
Carry flag CY
Instruction code
Parameter
Number of
words
Number of
cycles
MACHINE INSTRUCTIONS (CONTINUED)
(T1F) = 1
–
Timer operation
1
0
1
0
0
0
0
0
0
1
2 8 1
1
1
(T2F) = 1 ?
After skipping the next instruction
Skips the next instruction when the contents of T1F flag is “1.”
After skipping, clears T1F flag.
After skipping the next instruction
(T1F) ← 0
SNZT2
Detailed description
(T2F) = 1
–
Skips the next instruction when the contents of T2F flag is “1.”
After skipping, clears T2F flag.
(T3F) = 1
–
Skips the next instruction when the contents of T3F flag is “1.”
(T2F) ← 0
SNZT3
1
0
1
0
0
0
0
0
1
0
2 8 2
1
1
(T3F) = 1 ?
After skipping, clears T3F flag.
After skipping the next instruction
(T3F) ← 0
IAP0
1
0
0
1
1
0
0
0
0
0
2 6 0
1
1
(A) ← (P0)
–
–
Transfers the input of port P0 to register A.
OP0A
1
0
0
0
1
0
0
0
0
0
2 2 0
1
1
(P0) ← (A)
–
–
Outputs the contents of register A to port P0.
IAP1
1
0
0
1
1
0
0
0
0
1
2 6 1
1
1
(A) ← (P1)
–
–
Transfers the input of port P1 to register A.
OP1A
1
0
0
0
1
0
0
0
0
1
2 2 1
1
1
(P1) ← (A)
–
–
Outputs the contents of register A to port P1.
IAP2
1
0
0
1
1
0
0
0
1
0
2 6 2
1
1
(A1, A0) ← (P21, P20)
–
–
Transfers the input of port P2 to register A.
Input/Output operation
(A3, A2) ← 0
54
IAP3
1
0
0
1
1
0
0
0
1
1
2 6 3
1
1
(A) ← (P3)
–
–
Transfers the input of port P3 to register A.
OP3A
1
0
0
0
1
0
0
0
1
1
2 2 3
1
1
(P3) ← (A)
–
–
Outputs the contents of register A to port P3.
IAP4
1
0
0
1
1
0
0
1
0
0
2 6 4
1
1
(A) ← (P4)
–
–
Transfers the input of port P4 to register A.
CLD
0
0
0
0
0
1
0
0
0
1
0 1 1
1
1
(D) ← 1
–
–
Sets port D to “1.”
RD
0
0
0
0
0
1
0
1
0
0
0 1 4
1
1
(D(Y)) ← 0
(Y) = 0 to 9
–
–
Clears a bit of port D specified by register Y to “0.”
SD
0
0
0
0
0
1
0
1
0
1
0 1 5
1
1
(D(Y)) ← 1
(Y) = 0 to 9
–
–
Sets a bit of port D specified by register Y to “1.”
TK0A
1
0
0
0
0
1
1
0
1
1
2 1 B
1
1
(K0) ← (A)
–
–
Transfers the contents of register A to key-on wakeup control register K0.
TAK0
1
0
0
1
0
1
0
1
1
0
2 5 6
1
1
(A) ← (K0)
–
–
Transfers the contents of key-on wakeup control register K0 to register A.
TPU0A
1
0
0
0
1
0
1
1
0
1
2 2 D
1
1
(PU0) ← (A)
–
–
Transfers the contents of register A to pull-up control register PU0.
TAPU0
1
0
0
1
0
1
0
1
1
1
2 5 7
1
1
(A) ← (PU0)
–
–
Transfers the contents of pull-up control register PU0 to register A.
55
Mnemonic
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Carrier generating circuit
operation
instructions
Hexadecimal
notation
4570 Group
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Function
Skip condition
Carry flag CY
Type of
MITSUBISHI MICROCOMPUTERS
Number of
words
Number of
cycles
Instruction code
Parameter
MITSUBISHI MICROCOMPUTERS
Detailed description
TC2A
1
0
1
0
1
0
1
0
0
1
2 A 9
1
1
(C21, C20) ← (A1, A0)
–
–
Transfers the contents of register A to carrier wave output control register C2.
NOP
0
0
0
0
0
0
0
0
0
0
0 0 0
1
1
(PC) ← (PC) + 1
–
–
No operation
POF
0
0
0
0
0
0
0
0
1
0
0 0 2
1
1
Transition to RAM back-up mode
–
–
Puts the system in RAM back-up mode state by executing the POF instruction after executing the
EPOF instruction.
Other operation
EPOF
0
0
0
1
0
1
1
0
1
1
0 5 B
1
1
POF instruction valid
–
–
Validates the POF instruction which is executed after the EPOF instruction by executing the EPOF
instruction.
(P) = 1
–
Skips the next instruction when P flag is “1.”
After skipping, P flag remains unchanged.
SNZP
0
0
0
0
0
0
0
0
1
1
0 0 3
1
1
(P) = 1 ?
WRST
1
0
1
0
1
0
0
0
0
0
2 A 0
1
1
(WDF1) ← 0, (WEF) ← 1
–
–
Operates the watchdog timer and initializes the watchdog timer flag (WDF1).
TABSI
1
0
0
1
1
1
1
0
0
0
2 7 8
1
1
(B) ← (SI7–SI4)
(A) ← (SI3–SI0)
–
–
Transfers the contents of general-purpose register SI to registers A and B.
TSIAB
1
0
0
0
1
1
1
0
0
0
2 3 8
1
1
(SI7–SI4) ← (B)
(SI3–SI0) ← (A)
–
–
Transfers the contents of registers A and B to general-purpose register SI.
TAMR
1
0
0
1
0
1
0
0
1
0
2 5 2
1
1
(A) ← (MR3–MR0)
–
–
Transfers the contents of clock control register MR to register A.
TMRA
1
0
0
0
0
1
0
1
1
0
2 1 6
1
1
(MR3–MR0) ← (A)
–
–
Transfers the contents of register A to clock control register MR.
SBK
0
0
0
1
0
0
0
0
0
1
0 4 1
1
1
When executing the TABP p instruction,
–
–
Data area which is referred when executing the TABP p instruction is set to pages 64 to 127.
This setting is valid only for the TABP p instruction.
–
–
Data area which is referred when executing the TABP p instruction is set to pages 0 to 63.
This setting is valid only for the TABP p instruction.
p6 ← 1
RBK
0
0
0
1
0
0
0
0
0
0
0 4 0
1
1
When executing the TABP p instruction,
p6 ← 0
If the SBK instruction is not executed, p6 when executing the TABP p instruction is “0.”
56
57
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
CONTROL REGISTERS
Interrupt control register V1
V13
Timer 2 interrupt enable bit
V12
Timer 1 interrupt enable bit
V11
Not used
V10
External 0 interrupt enable bit
at reset : 00002
0
Interrupt disabled (SNZT2 instruction is valid)
1
Interrupt enabled (SNZT2 instruction is invalid)
0
1
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
0
1
0
1
Interrupt control register V2
V23
Not used
V22
Not used
V21
Not used
V20
Timer 3 interrupt enable bit
0
1
0
1
0
1
0
1
Not used
I12
Interrupt valid waveform for INT pin /return
level selection bit (Note 2)
I11
Not used
I10
Not used
R/W
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
at reset : 00002
Interrupt control register I1
I13
RAM back-up : 00002
at RAM back-up : 00002
R/W
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
at reset : 00002
at RAM back-up : state retained
R/W
0
1
This bit has no function, but read/write is enabled.
0
Falling waveform (“L” level of INT pin is recognized with the SNZI0
instruction)/“L” level
1
0
1
0
Rising waveform (“H” level of INT pin is recognized with the SNZI0
instruction)/“H” level
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
1
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: Depending on the input state of P21/INT pin, the external interrupt request flag EXF0 may be set to “1” when the contents
of I12 is changed. Accordingly, set a value to bit 2 of register I1 and execute the SNZ0 instruction to clear the EXF0 flag after
executing at least one instruction.
58
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
CONTROL REGISTERS (CONTINUED)
at reset : 00002
Timer control register W1
W13
Prescaler control bit
W12
Prescaler dividing ratio selection bit
W11
Timer 1 count source selection bit
W10
Timer 1 control bit
0
Stop (prescaler state initialized)
1
0
Operating
Instruction clock divided by 4
1
Instruction clock divided by 8
0
1
Prescaler output (ORCLK)
Carrier output (CARRY)
0
Stop (state retained)
1
Operating
at reset : 00002
Timer control register W2
W23
Timer 2 control bit
W22
Port D9/TOUT pin function selection bit
0
Stop (state retained)
1
0
Operating
Port D9
1
TOUT pin
W21 W20
W21
Timer 2 count source selection bits
W20
0
0
0
1
1
0
1
1
Timer 3 control bit
W32
Not used
Timer 3 count source selection bits
W30
Timer count value store register W5
R/W
Timer 1 underflow signal
Instruction clock
16-bit timer underflow signal
0
Stop (state retained)
1
0
Operating
at RAM back-up : state retained
R/W
This bit has no function, but read/write is enabled.
1
Count source
W31 W30
W31
at RAM back-up : state retained
R/W
Count source
Prescaler output (ORCLK)
at reset : 00002
Timer control register W3
W33
at RAM back-up : 00002
0
0
0
1
Timer 2 underflow signal
Prescaler output (ORCLK)
1
0
f(XIN) or f(XIN)/2
1
1
Not available
at reset : 002
at RAM back-up : state retained
R/W
2-bit register. The contents of the high-order 2 bits (bits 9 and 8) of the 10-bit ROM pattern at address (D 2D1D0A3A2A1A0) in page
p specified by registers D and A is stored in this register W5 with the TABP p instruction.
In addition, data can be transferred between the low-order 2 bits of register A and this register W5 with the TW5A or TAW5
instruction. Data can be read/written to/from the high-order 2 bits of timer 1 with the T1AB or TAB1 instruction.
Note: “R” represents read enabled, and “W” represents write enabled.
59
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
CONTROL REGISTERS (CONTINUED)
Carrier wave output control register C2
C21
C20
Port CARR output control bit
Carrier wave output auto-control bit
at reset : 002
0
K02
K01
K00
Port P43 key-on wakeup
control bit
Port P42 key-on wakeup
control bit
Port CARR “H” level output
0
Auto-control output by timer 1 is invalid
1
Auto-control output by timer 1 is valid
Port P41 key-on wakeup
control bit
Port P40 key-on wakeup
control bit
at reset : 00002
Key-on wakeup not used
0
Key-on wakeup not used
Key-on wakeup used
1
0
1
Pull-up control register PU0
PU03
PU02
PU01
PU00
Key-on wakeup not used
Key-on wakeup used
Key-on wakeup not used
Key-on wakeup used
at RAM back-up : state retained
Port P43 pull-up transistor
control bit
0
1
Pull-up transistor OFF
Port P42 pull-up transistor
0
1
Pull-up transistor OFF
Pull-up transistor ON
0
Pull-up transistor OFF
1
0
Pull-up transistor ON
Pull-up transistor OFF
1
Pull-up transistor ON
control bit
Port P41 pull-up transistor
control bit
Port P40 and P01 pull-up transistor
control bit
System clock selection bit
MR2
Not used
MR1
Not used
MR0
Not used
8-bit general purpose register PU0
at RAM back-up : state retained
0
f(XIN)
1
f(XIN)/4
0
1
This bit has no function, but read/write is enabled.
1
0
1
R/W
Pull-up transistor ON
at reset : 10002
0
R/W
Key-on wakeup used
at reset : 00002
Clock control register MR
MR3
at RAM back-up : state retained
0
1
1
0
W
Port CARR “L” level output
1
Key-on wakeup control register K0
K03
at RAM back-up : 002
R/W
This bit has no function, but read/write is enabled.
This bit has no function, but read/write is enabled.
at reset : 0016
at RAM back-up : state retained
R/W
8-bit general purpose register.
8-bit data can be transferred between this register PU0 and registers A and B with the TSIAB instruction and TABSI instruction.
Note: “R” represents read enabled, and “W” represents write enabled.
60
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
ABSOLUTE MAXIMUM RATINGS
Symbol
Conditions
Parameter
VDD
Supply voltage
VI
Input voltage
P0, P1, P2, P3, P4, RESET, XIN, VDCE
VO
VO
Pd
Topr
Tstg
Output voltage P0, P1, P3, D
Output transistors in cut-off state
Output voltage CARR, XOUT
Power dissipation
Operating temperature range
Storage temperature range
Ratings
Unit
–0.3 to 7.0
V
–0.3 to VDD+0.3
V
–0.3 to VDD+0.3
–0.3 to VDD+0.3
V
V
300
mW
–20 to 70
–40 to 125
°C
°C
RECOMMENDED OPERATING CONDITIONS1
(Mask ROM version:Ta = –20 °C to 70 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted)
(One Time PROM version:Ta = –20 °C to 70 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted)
Symbol
Parameter
Mask ROM version
System clock
Conditions
f(XIN) ≤ 4.2 MHz
Ceramic resonator
Limits
Min.
Typ.
Max.
2.0
5.5
4.5
5.5
2.0
5.5
2.5
5.5
4.5
5.5
2.5
5.5
1.8
5.5
2.0
5.5
Unit
=f(XIN)/4
Mask ROM version
System clock
VDD
Supply voltage =f(XIN)
f(XIN) ≤ 2.0 MHz
Ceramic resonator
f(XIN) ≤ 1.0 MHz
Ceramic resonator
V
One Time PROM version
System clock
=f(XIN)/4
VRAM
VSS
f(XIN) ≤ 4.2 MHz
Ceramic resonator
One Time PROM version f(XIN) ≤ 2.0 MHz
Ceramic resonator
System clock
f(XIN) ≤ 1.0 MHz
=f(XIN)
Ceramic resonator
RAM back-up Mask ROM version
RAM back-up
voltage
One Time PROM version
Supply voltage
V
V
V
0
Mask ROM version
VDD=2.0 V to 5.5V
4.2
VDD=4.5 V to 5.5V
2.0
VDD=2.0 V to 5.5V
1.0
( a t c e r a m i c One Time PROM version
resonance)
VDD=2.5 V to 5.5V
System clock
4.2
System clock
=f(XIN)/4
Mask ROM version
f(XIN)
O s c i l l a t i o n System clock
=f(XIN)
frequency
MHz
=f(XIN)/4
One Time PROM version VDD=4.5 V to 5.5V
System clock
VDD=2.5 V to 5.5V
=f(XIN)
2.0
1.0
61
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
RECOMMENDED OPERATING CONDITIONS 2
(Mask ROM version:Ta = –20 °C to 70 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted)
(One Time PROM version:Ta = –20 °C to 70 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted)
Symbol
VIH
“H” level input voltage P0, P1, P2,
VIH
P3, P4, VDCE
“H” level input voltage XIN
VIH
“H” level input voltage RESET
VIH
VIL
“H” level input voltage INT
“L” level input voltage P0, P1, P2, P3,
Min.
0.7VDD
VDD
0.85VDD
0.8VDD
VDD
V
V
VDD
V
P4, VDCE
0
0.3VDD
V
“L” level input voltage XIN
______
“L” level input voltage RESET
0
0.3VDD
0
0
0.3VDD
V
V
0.2VDD
V
VDD=5.0 V
10
VDD=3.0 V
4
VDD=5.0 V
VDD=3.0 V
30
24
VDD=5.0 V
5
VDD=3.0 V
“L” level average output current P3 VDD=5.0 V
(Note)
VDD=3.0 V
2
15
“L” level average output current
P0, P1, D0–D9, CARR (Note)
IOH(peak) “H” level peak output current
CARR
IOH(avg) “H” level average output current
CARR (Note)
12
mA
mA
mA
mA
VDD=5.0 V
VDD=3.0 V
–30
–15
mA
VDD=5.0 V
–15
–7
mA
30
mA
20
mA
100
µs
VDD=3.0 V
Σ IOL
Σ IOL
“L” total current P0, P1, P3
“L” total current D
TPON
Power reset circuit valid power rising Mask ROM version
time
VDD = 0 to 2.0 V
One Time PROM version
VDD = 0 to 2.5 V
Note: The average output current is the average current value at the 100 ms interval.
62
Unit
V
“L” level input voltage INT
IOL(peak) “L” level peak output current
P0, P1, D0–D9, CARR
IOL(peak) “L” level peak output current P3
IOL(avg)
Max.
VDD
VIL
IOL(avg)
Typ.
0.8VDD
______
VIL
VIL
Limits
Conditions
Parameter
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
ELECTRICAL CHARACTERISTICS
(Mask ROM version:Ta = –20 °C to 70 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted)
(One Time PROM version:Ta = –20 °C to 70 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted)
Symbol
Parameter
Test conditions
Limits
Min.
Typ.
Max.
“L” level output voltage
IOL = 5 mA
VDD = 5.0 V
0.9
P0, P1, D0–D9, CARR, RESET
IOL = 2 mA
VDD = 3.0 V
VOL
“L” level output voltage P3
IOL = 15 mA
IOL = 12 mA
VDD = 5.0 V
VDD = 3.0 V
0.9
1.5
VOH
“H” level output voltage CARR
IOH = 15 mA
VDD = 5.0 V
2.4
IOH = –7 mA
VDD = 3.0 V
1.0
VOL
IIH
IIL
IOZ
IDD
“H” level input current P0, P1, P2, P3, P4,
RESET, VDCE
1
Output current at off-state D0–D9
Supply current
at CPU operating mode
VO = VDD
1
VDD = 5.0 V, f(XIN) = 4.2 MHz
System clock = f(XIN)/4
1.3
2.6
VDD = 5.0 V
f(XIN) = 2 MHz
1.9
3.8
System clock = f(XIN)
f(XIN) = 1 MHz
VDD = 3.0 V, f(XIN) = 4.2 MHz
1.3
2.6
0.6
1.2
0.5
1.0
0.4
0.1
50
0.8
10
125
250
System clock = f(XIN)/4
VDD = 3.0 V
System clock = f(XIN)
at RAM back-up mode
Pull-up resistor
RPH
value
P0, P1, P4
RESET
INT
VT+ – VT– Hysteresis
f(XIN) = 1 MHz
f(XIN) = 500 kHz
f(XIN) = stop, typical value at Ta = 25 °C
VDD = 5.0 V, VI = 0 V
VDD = 3.0 V, VI = 0 V
20
40
VDD = 5.0 V, VI = 0 V
12
VDD = 3.0 V, VI = 0 V
VDD = 5.0 V
25
VDD = 3.0 V
VDD = 5.0 V
VDD = 3.0 V
Note: In this case, the pull-up transistor of port P4 is turned off by software.
RESET
V
µA
µA
–1
VI = 0 V (Note)
V
V
VI = VDD (Note)
“L” level input current P2, P3, P4, RESET ,
VDCE
1.5
Unit
100
30
60
0.5
0.4
1.5
0.6
70
130
µA
mA
µA
kΩ
kΩ
V
V
63
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
BASIC TIMING DIAGRAM
Machine cycle
Parameter
Clock
Pin name
State
XIN
(System clock=f(X IN))
XIN
(System clock=f(X IN)/4)
Port D output
D0–D9
Port P0, P1, P3 output P00–P03
P10–P13
P30–P33
Port P0, P1, P2,
P3, P4 input
P00–P03
P10–P1 3
P20, P21
P30–P33
P40–P43
Interrupt input
INT
64
Mi
Mi+1
T3
T1
T2
T3
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
BUILT-IN PROM VERSION
In addition to the mask ROM version, the 4570 Group has the
programmable ROM version software compatible with mask
ROM. The One Time PROM version has PROM which can only
be written to and not be erased.
The built-in PROM version has functions similar to those of the
mask ROM version, but it has a PROM mode that enables writing
to built-in PROM.
Table 16 shows the product of built-in PROM version. Figure 35
shows the pin configurations of built-in PROM version. The One
Time PROM version has pin-compatibility with the mask ROM
version.
Table 16 Product of built-in PROM version
PROM size
RAM size
M34570E8FP
(✕ 10 bits)
8192 words
(✕ 4 bits)
128 words
36P2R-A
M34570EDFP
16384 words
128 words
36P2R-A
Product
ROM type
Package
One Time PROM
PIN CONFIGURATION (TOP VIEW)
D2
1
36
D1
D3
2
D4
D5
D6
3
35
34
D0
P13
P12
D7
5
6
D9/TOUT
7
8
P20
9
P21/INT
RESET
CNV SS
10
11
12
M34570ExFP
D8
4
33
32
31
30
29
28
27
26
25
XOUT
13
24
XIN
14
VSS
15
VDCE
VDD
16
23
22
21
CARR
18
20
19
17
P11
P10
P03
P02
P01
P00
P43
P42
P41
P40
P33
P32
P31
P30
Outline 36P2R-A
Fig. 35 Pin configuration of built-in PROM version
65
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
(1) PROM mode
The built-in PROM version has a PROM mode in addition to
a normal operation mode. The PROM mode is used to write
to and read from the built-in PROM.
In the PROM mode, the programming adapter can be used
with a general-purpose PROM programmer to write to or read
from the built-in PROM as if it were M5M27C256K.
Programming adapter is listed in Table 17. Contact addresses
at the end of this book for the appropriate PROM programmer.
• Writing and reading of built-in PROM
Programming voltage is 12.5 V. Write the program in the
PROM of the built-in PROM version as shown in Figure
36.
(2) Notes on handling
➀ A high-voltage is used for writing. Take care that
overvoltage is not applied. Take care especially at turning
on the power.
➁ For the One Time PROM version Mitsubishi Electric corp.
does not perform PROM writing test and screening in the
assembly process and following processes. In order to
improve reliability after writing, performing writing and test
according to the flow shown in Figure 37 before using is
recommended.
Table 17 Programming adapter
Microcomputer
Programming adapter
PCA7425
M34570E8FP, M34570EDFP
Address
0000 16
1
1
1
D4 D 3
D1
D0
Low-order 5 bits
1FFF 16
4000 16
D2
1
1
1
D4 D 3
D2
D1
D0
High-order 5 bits
5FFF 16
7FFF 16
The shaded area can be used only for M34570ED.
Set “FF 16” to the shaded area.
Fig. 36 PROM memory map
Writing with PROM programmer
Screening (Leave at 150 °C for 40 hours) (Note)
Verify test with PROM programmer
Function test in target device
Note: Since the screening temperature is higher
than storage temperature, never expose the
microcomputer to 150 °C exceeding 100
hours.
Fig. 37 Flow of writing and test of the product shipped in
blank
66
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
GZZ-SH55-08B <91A0>
Mask ROM number
4500 SERIES MASK ROM ORDER CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M34570M4-XXXFP
MITSUBISHI ELECTRIC
Receipt
Date:
Please fill in all items marked ✻.
✻ Customer
TEL (
Date
issued
)
Date:
Issuance
signature
Company
name
Section head S u p e r v i s o r
signature
signature
Responsible
Supervisor
officer
✻ 1. Confirmation
Three sets of EPROMs are required for each pattern if this order is performed by EPROMs.
One floppy disk is required for each pattern if this order is performed by floppy disk.
Ordering by the EPROMs
Specify the type of EPROMs submitted (check in the approximate box).
If at least two of the three sets of EPROMs submitted contain the identical data, we will produce
masks based on this data. We shall assume the responsibility for errors only if the mask ROM data
on the products we produce differ from this data. Thus, the customer must be especially careful in
verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM area
(hexadecimal notation)
EPROM Type:
27C512
27C256
Low-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
High-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
000016
4.00K
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
0FFF16
400016
4.00K
4FFF16
7FFF16
Low-order
5-bit data
High-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
000016
4.00K
0FFF16
400016
4.00K
4FFF16
FFFF16
Set “FF 16 ” in the shaded area.
Set “111 2 ” in the area
of low-order and high-order 5-bit data.
67
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
GZZ-SH55-08B <91A0>
Mask ROM number
4500 SERIES MASK ROM ORDER CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M34570M4-XXXFP
MITSUBISHI ELECTRIC
Ordering by floppy disk
We will produce masks based on the mask files generated by the mask file generating utility. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this
mask file. Thus, extreme care must be taken to verify the mask file in the submitted floppy disk.
The submitted floppy disk must be-3.5 inch 2HD type and DOS/V format. And the number of the mask
files must be 1 in one floppy disk.
File code
(hexadecimal notation)
Mask file name
.MSK (equal or less than eight characters)
✻ 2. Mark Specification
Mark specification must be submitted using the correct form for the type of package being ordered.
Fill out the approximate Mark Specification Form (36P2R-A for M34570M4-XXXFP) and attach to
the Mask ROM Order Confirmation Form.
✻ 3. Comments
68
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
GZZ-SH55-09B <91A0>
Mask ROM number
4500 SERIES MASK ROM ORDER CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M34570M8-XXXFP
MITSUBISHI ELECTRIC
Receipt
Date:
Please fill in all items marked ✻.
✻ Customer
TEL (
Date
issued
)
Date:
Issuance
signature
Company
name
Section head S u p e r v i s o r
signature
signature
Responsible
Supervisor
officer
✻ 1. Confirmation
Three sets of EPROMs are required for each pattern if this order is performed by EPROMs.
One floppy disk is required for each pattern if this order is performed by floppy disk.
Ordering by the EPROMs
Specify the type of EPROMs submitted (check in the approximate box).
If at least two of the three sets of EPROMs submitted contain the identical data, we will produce
masks based on this data. We shall assume the responsibility for errors only if the mask ROM data
on the products we produce differ from this data. Thus, the customer must be especially careful in
verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM area
(hexadecimal notation)
EPROM Type:
27C512
27C256
Low-order
5-bit data
000016
8.00K
1234567890123456789012345
1FFF16
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
High-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
400016
5FFF16
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345
1234567890123456789012345 7FFF16
Low-order
5-bit data
8.00K
High-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
000016
8.00K
1FFF16
400016
8.00K
5FFF16
FFFF16
Set “FF 16 ” in the shaded area.
Set “111 2 ” in the area
of low-order and high-order 5-bit data.
69
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
GZZ-SH55-09B <91A0>
Mask ROM number
4500 SERIES MASK ROM ORDER CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M34570M8-XXXFP
MITSUBISHI ELECTRIC
Ordering by floppy disk
We will produce masks based on the mask files generated by the mask file generating utility. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this
mask file. Thus, extreme care must be taken to verify the mask file in the submitted floppy disk.
The submitted floppy disk must be-3.5 inch 2HD type and DOS/V format. And the number of the mask
files must be 1 in one floppy disk.
File code
(hexadecimal notation)
Mask file name
.MSK (equal or less than eight characters)
✻ 2. Mark Specification
Mark specification must be submitted using the correct form for the type of package being ordered.
Fill out the approximate Mark Specification Form (36P2R-A for M34570M8-XXXFP) and attach to
the Mask ROM Order Confirmation Form.
✻ 3. Comments
70
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
GZZ-SH55-10B <91A0>
Mask ROM number
4500 SERIES MASK ROM ORDER CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M34570MD-XXXFP
MITSUBISHI ELECTRIC
Receipt
Date:
Please fill in all items marked ✻.
✻ Customer
TEL (
Date
issued
)
Date:
Issuance
signature
Company
name
Section head S u p e r v i s o r
signature
signature
Responsible
Supervisor
officer
✻ 1. Confirmation
Three sets of EPROMs are required for each pattern if this order is performed by EPROMs.
One floppy disk is required for each pattern if this order is performed by floppy disk.
Ordering by the EPROMs
Specify the type of EPROMs submitted (check in the approximate box).
If at least two of the three sets of EPROMs submitted contain the identical data, we will produce
masks based on this data. We shall assume the responsibility for errors only if the mask ROM data
on the products we produce differ from this data. Thus, the customer must be especially careful in
verifying the data contained in the EPROMs submitted.
Checksum code for entire EPROM area
(hexadecimal notation)
EPROM Type:
27C512
27C256
0000 16
0000 16
16.00K
Low-order
5-bit data
3FFF16
4000 16
High-order
5-bit data
16.00K
3FFF16
4000 16
High-order
5-bit data
16.00K
7FFF16
Low-order
5-bit data
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
123456789012345678901234
16.00K
7FFF16
FFFF 16
Set “FF 16 ” in the shaded area.
Set “111 2 ” in the area
of low-order and high-order 5-bit data.
71
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
GZZ-SH55-10B <91A0>
Mask ROM number
4500 SERIES MASK ROM ORDER CONFIRMATION FORM
SINGLE-CHIP MICROCOMPUTER M34570MD-XXXFP
MITSUBISHI ELECTRIC
Ordering by floppy disk
We will produce masks based on the mask files generated by the mask file generating utility. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this
mask file. Thus, extreme care must be taken to verify the mask file in the submitted floppy disk.
The submitted floppy disk must be-3.5 inch 2HD type and DOS/V format. And the number of the mask
files must be 1 in one floppy disk.
File code
(hexadecimal notation)
Mask file name
.MSK (equal or less than eight characters)
✻ 2. Mark Specification
Mark specification must be submitted using the correct form for the type of package being ordered.
Fill out the approximate Mark Specification Form (36P2R-A for M34570MD-XXXFP) and attach to
the Mask ROM Order Confirmation Form.
✻ 3. Comments
72
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
MARK SPECIFICATION FORM
36P2R-A (36-PIN SHRINK SOP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name
Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed).
A. Standard Mitsubishi Mark
36
19
Mitsubishi IC catalog name
Mitsubishi lot number
(6-digit or 7-digit)
18
1
B. Customer’s Parts Number + Mitsubishi catalog name
36
19
Mitsubishi lot number
(6-digit or 7-digit)
1
18
Customer’s Parts Number
Note : The fonts and size of characters are standard Mitsubishi type.
Mitsubishi IC catalog name
Note1 : The mark field should be written right aligned.
2 : The fonts and size of characters are standard Mitsubishi type.
3 : Customer’s Parts Number can be up to 11 characters : Only 0 ~
9, A ~ Z, +, –, /, (, ), &, , (periods), (commas) are usable.
.
,
C. Special Mark Required
36
19
1
18
Note1 : If the Special Mark is to be Printed, indicate the desired
layout of the mark in the left figure. The layout will be
duplicated as close as possible.
Mitsubishi lot number (6-digit or 7-digit) and Mask ROM
number (3-digit) are always marked.
2 : If the customer’s trade mark logo must be used in the
Special Mark, check the box below.
Please submit a clean original of the logo.
For the new special character fonts a clean font original
(ideally logo drawing) must be submitted.
Special logo required
3 : The standard Mitsubishi font is used for all characters
except for a logo.
73
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
PACKAGE OUTLINE
36P2R-A
Plastic 36pin 450mil SSOP
EIAJ Package Code
SSOP36-P-450-0.80
JEDEC Code
–
Weight(g)
0.53
Lead Material
Alloy 42
e
36
b2
E
HE
e1
I2
19
F
Recommended Mount Pad
Symbol
1
18
A
A2
y
b
L
e
A1
L1
D
A
A1
A2
b
c
D
E
e
HE
L
L1
y
c
Detail F
74
b2
e1
I2
Dimension in Millimeters
Min
Nom
Max
2.4
–
–
–
–
0.05
–
2.0
–
0.5
0.4
0.35
0.2
0.15
0.13
15.2
15.0
14.8
8.6
8.4
8.2
–
0.8
–
12.23
11.93
11.63
0.7
0.5
0.3
–
1.765
–
0.15
–
–
0°
–
10°
–
0.5
–
–
11.43
–
–
1.27
–
MITSUBISHI MICROCOMPUTERS
4570 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
Keep safety first in your circuit designs!
•
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of
substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap.
•
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any
intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor
product distributor for the latest product information before purchasing a product listed herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact
Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for
transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Notes regarding these materials
•
•
•
•
•
•
© 1999 MITSUBISHI ELECTRIC CORP.
New publication, effective April. 1999.
Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev.
No.
4570 GROUP DATA SHEET
Revision Description
Rev.
date
1.0
First Edition
971022
2.0
Main revision points are described below.
990331
•M34570MD-XXXFP and M34570EDFP (ROM expansion products [size: 16K 5 10 bits] ) added.
• SBK and RBK instructions added and TABP p instruction function is expanded.
(TABP p instruction: When this instruction is executed after executing the SBK instruction,
pages 64 to 127 are specified. When this instruction is executed after executing the RBK instruction, pages 0 to 63 are specified. When this instruction is executed after system is released from reset and returned from the RAM back-up mode, pages 0 to 63 are specified.)
• BL, BML, BLA and BMLA instructions revised. Referred pages are expanded to pages 0 to 127
(p6 can be used for page specification.)
(1/1)
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