phyCORE-i.MX27 H M

phyCORE-i.MX27 H M
phyCORE-i.MX27
HARDWARE MANUAL
EDITION JUNE 2009
A product of a PHYTEC Technology Holding company
phyCOREi.MX27
In this manual are descriptions for copyrighted products that are not explicitly indicated
as such. The absence of the trademark (™) and copyright (©) symbols does not imply
that a product is not protected. Additionally, registered patents and trademarks are
similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be
entirely reliable. However, PHYTEC Messtechnik GmbH assumes no responsibility for
any inaccuracies. PHYTEC Messtechnik GmbH neither gives any guarantee nor accepts
any liability whatsoever for consequential damages resulting from the use of this manual
or its associated product. PHYTEC Messtechnik GmbH reserves the right to alter the
information contained herein without prior notification and accepts no responsibility for
any damages which might result.
Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any liability
for damages arising from the improper usage or improper installation of the hardware or
software. PHYTEC Messtechnik GmbH further reserves the right to alter the layout
and/or design of the hardware without prior notification and accepts no liability for doing
so.
© Copyright 2009 PHYTEC Messtechnik GmbH, D-55129 Mainz.
Rights - including those of translation, reprint, broadcast, photomechanical or similar
reproduction and storage or processing in computer systems, in whole or in part - are
reserved. No reproduction may occur without the express written consent from PHYTEC
Messtechnik GmbH.
EUROPE
NORTH AMERICA
Address:
PHYTEC Technologie Holding AG
Robert-Koch-Str. 39
D-55129 Mainz
GERMANY
PHYTEC America LLC
203 Parfitt Way SW, Suite G100
Bainbridge Island, WA 98110
USA
Ordering
Information:
+49 (800) 0749832
[email protected]
1 (800) 278-9913
[email protected]
Technical
Support:
+49 (6131) 9221-31
[email protected]
1 (800) 278-9913
[email protected]
Fax:
+49 (6131) 9221-33
1 (206) 780-9135
Web Site:
http://www.phytec.de
http://www.phytec.com
Edition June 2009
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Contents
1
Preface.................................................................................................1
1.1 Introduction...................................................................................2
1.2 Block Diagram ..............................................................................4
1.3 View of the phyCORE-i.MX27 ......................................................5
2
Pin Description ...................................................................................7
3
Jumpers.............................................................................................23
4
Power Requirements........................................................................29
5
Real Time Clock U11 / SRAM U19 Backup-Voltage ......................31
6
System Configuration ......................................................................33
6.1 System Startup Configuration ....................................................33
6.1.1 Power-Up-Mode-Select (PUMS) ....................................33
6.1.2 Boot Mode Select ...........................................................34
7
System Memory ................................................................................35
7.1
7.2
7.3
7.4
Memory Model............................................................................36
LP-DDR-SDRAM (U3-U4) ..........................................................37
NOR-Flash (U17)........................................................................38
NAND Flash Memory (U16) .......................................................39
7.4.1 8/16-Bit NAND Flash Usage (JN1,JN2,RN31,RN32) .....40
7.5 I²C EEPROM (U12) ....................................................................41
7.5.1 Setting the EEPROM Lower Address Bits
(J13, J15, J16) ................................................................42
7.5.2 EEPROM Write Protection Control (J1)..........................43
8
Serial Interface..................................................................................45
8.1 RS-232 Transceiver (U18) .........................................................45
8.1.1 UART1 Routing (RN30) ..................................................46
9
USB-OTG Transceiver (U20)............................................................47
10
Ethernet Controller / Ethernet-Phy (U9) .........................................48
11
JTAG Interface (U15)........................................................................49
12
Technical Specifications .................................................................53
13
Hints for Handling the phyCORE-i.MX27 .......................................55
© PHYTEC Messtechnik GmbH 2009
L-710e_4
phyCOREi.MX27
14
The phyCORE i.MX27 on the i.MX Carrier Board ..........................57
14.1 Concept of the phyCORE-i.MX Development Kits .....................58
14.2 phyMAP-i.MX27..........................................................................59
14.2.1 phyMAP-i.MX27 Jumper Settings...................................61
14.2.2 phyMAP-i.MX27 Signal Mapping....................................63
14.2.3 phyMAP-i.MX27 Mapper Physical Dimensions ..............71
14.3 Cooperation of phyCORE-i.MX27 and phyCORE-i.MX
Carrier Board ..............................................................................72
14.3.1 Power Supply..................................................................73
14.3.2 CAN Interface .................................................................77
14.3.3 Push Buttons and LEDs .................................................79
14.3.4 Compact Flash Card.......................................................81
14.3.5 Security Digital Card/ MultiMedia Card...........................83
14.3.6 Audio and Touchscreen..................................................85
14.3.7 USB Host ........................................................................87
14.3.8 LCD Connectors .............................................................89
14.3.9 Camera Interface ............................................................91
14.3.10 JTAG Interface..............................................................94
14.3.11 Complete jumper setting list for phyCORE-i.MX27
on the i.MX Carrier Board .............................................96
15
Revision History ...............................................................................99
16
Component Placement Diagram ...................................................101
Index ........................................................................................................103
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Contents
Index of Figures
Figure 1: Block Diagram of the phyCore-i.MX27 .............................4
Figure 2: Top view of the phyCORE-i.MX27 (controller side)..........5
Figure 3: Bottom view of the phyCORE-i.MX27 (connector side) ...6
Figure 4: Pin-out of the phyCORE-Connector
(top view, with cross section insert)..................................8
Figure 5: Typical jumper pad numbering scheme .........................23
Figure 6: Jumper locations (top view)............................................24
Figure 7: Jumper locations (bottom side in top view) ....................25
Figure 8: minimum circuit...............................................................29
Figure 9: JTAG interface at U15 (top view) ...................................49
Figure 10: JTAG interface at U15 (bottom view) .............................50
Figure 11: Physical dimensions .......................................................53
Figure 12: phyCORE-i.MX27 Carrier Board connection using the
phyMAP-i.MX27..............................................................58
Figure 13: Modular development and Expansion Board concept
with phyCORE-i.MX27....................................................58
Figure 14: phyMAP-i.MX27 top view ...............................................59
Figure 15: phyMAP-i.MX27 bottom view .........................................60
Figure 16: Jumper location on PMA-005 .........................................61
Figure 17: Physical dimensions of phyMAP-i.MX27 mapper...........71
Figure 18: pyhCORE-i.MX Carrier Board and phyCORE-i.MX27
Power Supply .................................................................73
Figure 19: phyCORE-i.MX Carrier Board CAN Interface.................77
Figure 20: phyCORE-i.MX Carrier Board Buttons and LEDs ..........79
Figure 21: Compact Flash Card Interface .......................................81
Figure 22: SD Card interface ...........................................................83
Figure 23: phyCORE-i.MX Carrier Board Audio/Touch Interface ....85
Figure 24: phyCORE-iMX Carrier Board USB-Host Interface .........87
Figure 25: phyCORE-i.MX Carrier Board LCD Interfaces ...............89
© PHYTEC Messtechnik GmbH 2009
L-710e_4
phyCOREi.MX27
Figure 26: phyCORE-i.MX Carrier Board Camera Interface ...........91
Figure 27: phyCORE-iMX Carrier Board JTAG Interface ................94
Figure 28: phyCORE-i.MX27 component placement (top view) ....101
Figure 29: phyCORE-i.MX27 component placement
(bottom view) ................................................................102
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Contents
Index of Tables
Table 1:
Pin-out of the phyCORE-Connector X1............................9
Table 2:
Jumper settings ..............................................................26
Table 3:
Power supply for the minimum circuit.............................30
Table 4:
i.MX27 default power input voltages ..............................30
Table 5:
VBKUP2 Voltage Settings ..............................................31
Table 6:
Default PUMS for i.MX27 module...................................33
Table 7:
Boot Modes of i.MX27 module .......................................34
Table 8:
i.MX27 memory map ......................................................36
Table 9:
Compatible NOR Flash devices .....................................38
Table 10: Compatible NAND Flash devices ...................................39
Table 11: JN1/2,RN31/32 NAND Flash bit width selection ............40
Table 12: U12 EEPROM I²C address via J13, J15, and J16 .........42
Table 13: EEPROM write protection states via J1 .........................43
Table 14: RN30 UART1 signal routing ...........................................46
Table 15: Fast Ethernet controller memory map ............................48
Table 16: JTAG connector U15 signal assignment ........................51
Table 17: Jumper settings of PMA-002 ..........................................62
Table 18: PMA-002 mapping list ....................................................63
Table 19: Jumper settings for i.MX27 power supply via
power plug ......................................................................74
Table 20: Jumper settings for i.MX27 power supply via POE ........75
Table 21: Jumper settings for i.MX27 power supply via battery.....76
Table 22: CAN interface jumper settings........................................78
Table 23: x_BOOT_MODE0 selection ...........................................80
Table 24: x_BOOT_MODE1 selection ...........................................80
Table 25: x_switch ..........................................................................80
Table 26: CF interface jumper settings...........................................82
Table 27: SD/MMC interface jumper settings for i.MX27 module ..84
© PHYTEC Messtechnik GmbH 2009
L-710e_4
phyCOREi.MX27
Table 28: Audio/Touchscreen interface jumper settings ................86
Table 29: UBS Host interface jumper settings for i.MX27 module .88
Table 30: Camera interface jumper settings for i.MX27 module ....92
Table 31: JTAG jumper settings for phyCORE-i.MX27 module .....95
Table 32: Jumper settings for i.MX27 module on
i.MX Carrier Board ..........................................................96
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Preface
1 Preface
This hardware manual describes the phyCORE-i.MX27 Single Board Computer’s design and function.
Precise specifications for the Freescale i.MX27 microcontrollers can be found in the enclosed
microcontroller Data Sheet/User's Manual.
In this hardware manual and in the attached schematics, active low signals are denoted by a "/" or “#”
preceding the signal name (e.g.: /RD or #RD). A "0" indicates a logic zero or low-level signal, while a
"1" represents a logic one or high-level signal.
Declaration of Electro Magnetic Conformity of the PHYTEC
phyCORE-I.MX27
PHYTEC Single Board Computers (henceforth products) are designed for installation
in electrical appliances or as dedicated Evaluation Boards (i.e.: for use as a test and prototype
platform for hardware/software development) in laboratory environments.
Caution!
PHYTEC products lacking protective enclosures are subject to damage by ESD and, hence, may only
be unpacked, handled or operated in environments in which sufficient precautionary measures have
been taken in respect to ESD-dangers. It is also necessary that only appropriately trained personnel
(such as electricians, technicians and engineers) handle and/or operate these products. Moreover,
PHYTEC products should not be operated without protection circuitry if connections to the product's
pin header rows are longer than 3 m.
PHYTEC products fulfill the norms of the European Union’s Directive for Electro Magnetic Conformity
only in accordance to the descriptions and rules of usage indicated in this hardware manual
(particularly in respect to the pin header row connectors, power connector and serial interface to a
host-PC).
Implementation of PHYTEC products into target devices, as well as user modifications and extensions
of PHYTEC products, is subject to renewed establishment of conformity to, and certification of,
Electro Magnetic Directives. Users should ensure conformance following any modifications to the
products as well as implementation of the products into target systems.
The phyCORE-i.MX27 is one of a series of PHYTEC Single Board Computers that can be populated
with different controllers and, hence, offers various functions and configurations. PHYTEC supports a
variety of 8-/16- and 32-bit controllers in two ways:
(1)
as the basis for Rapid Development Kits which serve as a reference and evaluation platform
(2)
as insert-ready, fully functional phyCORE OEM modules, which can be embedded directly
into the user’s peripheral hardware design.
PHYTEC's microcontroller modules allow engineers to shorten development horizons, reduce design
costs and speed project concepts from design to market. For more information go to:
http://www.phytec.com/services/phytec-advantage.html
© PHYTEC Messtechnik GmbH 2009
L-710e_4
1
phyCOREi.MX27
1.1 Introduction
The phyCORE-i.MX27 belongs to PHYTEC’s phyCORE Single Board Computer module family. The
phyCORE SBCs represent the continuous development of PHYTEC Single Board Computer
technology. Like its mini-, micro- and nanoMODUL predecessors, the phyCORE boards integrate all
core elements of a microcontroller system on a subminiature board and are designed in a manner
that ensures their easy expansion and embedding in peripheral hardware developments.
As independent research indicates that approximately 70 % of all EMI (Electro Magnetic Interference)
problems stem from insufficient supply voltage grounding of electronic components in high frequency
environments the phyCORE board design features an increased pin package. The increased pin
package allows dedication of approximately 20 % of all pin header connectors on the phyCORE
boards to ground. This improves EMI and EMC characteristics and makes it easier to design complex
applications meeting EMI and EMC guidelines using phyCORE boards even in high noise
environments.
phyCORE boards achieve their small size through modern SMD technology and multi-layer design. In
accordance with the complexity of the module, 0402-packaged SMD components and laser-drilled
microvias are used on the boards, providing phyCORE users with access to this cutting edge
miniaturization technology for integration into their own design.
The phyCORE-i.MX27 is a subminiature (84 x 60 mm) insert-ready Single Board Computer populated
with the Freescale i.MX27 microcontroller. Its universal design enables its insertion in a wide range of
embedded applications. All controller signals and ports extend from the controller to high-density pitch
(0.635 mm) connectors aligning two sides of the board, allowing it to be plugged like a "big chip" into
a target application.
Precise specifications for the controller populating the board can be found in the applicable controller
User’s Manual or datasheet. The descriptions in this manual are based on the Freescale i.MX27. No
description of compatible microcontroller derivative functions is included, as such functions are not
relevant for the basic functioning of the phyCORE-i.MX27.
2
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Introduction
The phyCORE-I.MX27 offers the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Subminiature Single Board Computer (84 x 60 mm) achieved through modern SMD technology
Populated with the Freescale i.MX27 microcontroller (BGA404 packaging)
Improved interference safety achieved through multi-layer PCB technology and dedicated ground
pins
Controller signals and ports extend to two 200-pin high-density (0.635 mm) Molex connectors
aligning two sides of the board, enabling it to be plugged like a "big chip" into target application
Max. 400 MHz core clock frequency
Boot from NOR or NAND Flash
32 MByte (up to 64MByte) Intel Strata NOR Flash
64 MByte (up to 1 GByte) on-board NAND Flash 1
128 MByte (up to 256 MByte) Mobile DDR SDRAM on-board
RS-232 transceiver supporting one UART at data rates of up to 460kbps
Full featured UART Interfaces without transceiver
32 KB I2C EEPROM
Separate I²C RTC with backup function
512 Kbyte (up to 2MByte SRAM) with backup function
Battery buffered controller based RTC with automatic battery switchover
High-Speed USB OTG transceiver
Auto FDX/MDX 100 MBit Ethernet Controller
All controller required supplies generated on board by PMIC
Synchronous 18Bit LCD-Interface
PCMCIA/CF card Interface
ATA-Interface DMA-Mode 3 (up to DMA-mode 5 without level-shifter) / CMOS Camera Interface
Support of standard 20 pin debug interface through JTAG connector
Keyboard support for up to 64 keys in a 8 * 8 matrix
Two I2C interfaces
SD/MMC card interface with DMA
Special Power-Management IC which includes:
o
o
o
o
o
o
o
o
1
Stereo line-in
Stereo line-out / pre-amplified mono-out
Stereo mic-in
4-Wire touch interface
RTC
LCD-Backlight control
Battery charger
6 AD-Inputs
Please contact PHYTEC for more information about additional module configurations.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
3
phyCOREi.MX27
1.2 Block Diagram
Figure 1:
4
Block Diagram of the phyCore-i.MX27
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Introduction
C140
C141
L5
TP6
TP5
C21
R78
C112
RN17
QO1
D6
TP7
C107
R81
D7
TP8
R19
C29
R21
R25
TP15 TP16
R17
R12 R6 R53
R55
R7 R54
R8
C111
XT2
TP17
C109
C163
RN19
RN18
C144
L4
C26
U18
C27
C135
C114
C152
R1
R4
R3
R14
RN16
U3
D5
C142
C145
C150
RN4
R13
L3
RN30
C167
U14
RN8
RN6
R66
RN2
RN7
C16
R65
R60
C24
C23
C151
RN1
RN5
J9
C110
RN29
C164
C171
C173
Q4
RN25
TP1
TP2
TP9
TP10
TP11
TP12
TP13
TP14
RN24
Q2
C99
R64 R63
R62 R61
C172
C134
C17
C149
RN26
1.3 View of the phyCORE-i.MX27
C28
C143
RN23
RN22
RN21
RN20
C105
XT3
C146
RN3
U4
C81
D2
J21
U5
R11
C10 C11 R10
R37
R90
C175
R89
C102
U24
U19
C118
C115
RN14
RN12
C174
R72
C117 C116
R24
C96
RN15
RN13
RN31
C20 R9
RN32
C91
C162
C161
R41
R35
C108
U16
C85
U17
J1
U12
C104
R71
R48
JN2
JN1
J13
J16
J15
RN28
Figure 2:
RN27
C97
C94
U15
Top view of the phyCORE-i.MX27 (controller side)
© PHYTEC Messtechnik GmbH 2009
L-710e_4
5
phyCOREi.MX27
C133
C157
D8
J12
L1
J18
J17
C25
R84
R83
C123 C125
R69
C127
C1
C31
R86
C121
C122
R68
C15
C130 C129
C124 C131
C159
J2
Q3
C153 C158
C156
C95
C126
R88
C89
C154
J5
J3
R39
C113
R58
Q5
X1
R44
C147
R40
C148
R45
Q1
J4 J7 J6
C128
D9
C155
C18
C160
R67
R70
C165
C168
C136
C169
C93
X1
J11
J8
J10
C166
R20
R82
C50
R22
U9
C3
C90
U22
C119
R38
C92
R85
C132
L2
U23
C2
C120
R15
C83
C42
C88
C48
U21
J22
R87
C49
C41
C43
C47
R23
R47
R80
C73
C75
C64
C68 C7
C72
C82
C65
C67
C9
C46
R27
C37
RN10
R56
C34
C40
C39
R57
C38
C98
RN11
C8
C22
C13
C51
C57
C45
R28
C84
C69
C52
C70
C55
R34
C5
C60
C78
C63
C54
C71
C44
R79
C87
R29
TP4
C14 C79
C59
C80
C76
C53
C66
C138 R32
R30
C56
C36
C12
R31
C61
R33
C58
R18
C137
RN9
R16
XT1
TP3
R5
C77
C33
U6
C74
D3
C35
U2
C139
U1
C170
R26
R43
U20
C106
R42
C32
C62
J20
C101
C4
C30
C19
R59
D4
D1
C6
U10
R46
C100
R49
U11
R36
R50
J14
C86
J19
C103
Figure 3:
6
Bottom view of the phyCORE-i.MX27 (connector side)
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Pin Description
2 Pin Description
Please note that all module connections are not to exceed their expressed maximum voltage or
current. Maximum signal input values are indicated in the corresponding controller manuals/data
sheets. As damage from improper connections varies according to use and application, it is the user's
responsibility to take appropriate safety measures to ensure that the module connections are
protected from overloading through connected peripherals.
As Figure 4 indicates, all controller signals extend to surface mount technology (SMT) connectors
(0.635 mm) lining two sides of the module (referred to as phyCORE-connector). This allows the
phyCORE-i.MX27 to be plugged into any target application like a "big chip".
A new numbering scheme for the pins on the phyCORE-connector has been introduced with the
phyCORE specifications. This enables quick and easy identification of desired pins and minimizes
errors when matching pins on the phyCORE-module with the phyCORE-connector on the appropriate
PHYTEC Development Board or in user target circuitry.
The numbering scheme for the phyCORE-connector is based on a two dimensional matrix in which
column positions are identified by a letter and row position by a number. Pin 1A, for example, is
always located in the upper left hand corner of the matrix. The pin numbering values increase moving
down on the board. Lettering of the pin connector rows progresses alphabetically from left to right
(refer to Figure 4).
The numbered matrix can be aligned with the phyCORE-i.MX27 (viewed from above;
phyCORE-connector pointing down) or with the socket of the corresponding phyCORE Development
Board/user target circuitry. The upper left-hand corner of the numbered matrix (pin 1A) is thus
covered with the corner of the phyCORE-i.MX27 marked with a triangle. The numbering scheme is
always in relation to the PCB as viewed from above, even if all connector contacts extend to the
bottom of the module.
The numbering scheme is thus consistent for both the module’s phyCORE-connector as well as
mating connectors on the phyCORE Development Board or target hardware, thereby considerably
reducing the risk of pin identification errors.
Since the pins are exactly defined according to the numbered matrix previously described, the
phyCORE-connector is usually assigned a single designator for its position (X1 for example). In this
manner the phyCORE-connector comprises a single, logical unit regardless of the fact that it could
consist of more than one physical socketed connector. The location of row 1 on the board is marked
by a triangle on the PCB to allow easy identification.
The following figure (Figure 4) illustrates the numbered matrix system. It shows a phyCORE-i.MX27
with SMT phyCORE-connectors on its underside (defined as dotted lines) mounted on a Development
Board. In order to facilitate understanding of the pin assignment scheme, the diagram presents a
cross-view of the phyCORE-module showing these phyCORE-connectors mounted on the underside
of the module’s PCB.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
7
phyCOREi.MX27
Figure 4:
Pin-out of the phyCORE-Connector (top view, with cross section
insert)
Table 1 provides an overview of the pin-out of the phyCORE-connector, as well as descriptions of
possible alternative functions. Table 1 also provides the appropriate signal level interface voltages
listed in the SL (Signal Level) column. The Freescale i.MX27 is a multi-voltage operated
microcontroller and as such special attention should be paid to the interface voltage levels to avoid
unintentional damage to the microcontroller and other on-board components. Please refer to the
Freescale i.MX27 User’s Manual/Data Sheet for details on the functions and features of controller
signals and port pins.
8
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Pin Description
Note:
SL is short for Signal Level (V) and is the applicable logic level to interface a given pin.
Those pins marked as “N/A” have a range of applicable values that constitute proper operation.
Table 1:
Pin-out of the phyCORE-Connector X1
PIN ROW X1A
PIN #
SIGNAL
I/O
SL
1A
2A
3A
4A
5A
6A
7A
8A
9A
10A
11A
12A
13A
14A
15A
16A
17A
18A
19A
20A
21A
22A
23A
24A
NVDD7_12_14
GND
not connected
not connected
X_VSYNC
X_OE_ACD
GND
X_REV
X_SPL_SPR
X_PS
Not connected
GND
X_LD0
X_LD2
X_LD3
X_LD5
GND
X_LD8
X_LD10
X_LD11
X_LD13
GND
X_LD17
X_#CS0
O
I/O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
25A
X_#CS1
O
26A
X_#CS4
O
27A
28A
GND
X_#PC_IORD/#EB
1
O
NVDD7_12_14
0
NVDD7_12_14
NVDD7_12_14
0
NVDD7_12_14
NVDD7_12_14
NVDD7_12_14
0
NVDD7_12_14
NVDD7_12_14
NVDD7_12_14
NVDD7_12_14
0
NVDD7_12_14
NVDD7_12_14
NVDD7_12_14
NVDD7_12_14
0
NVDD7_12_14
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
0
NVDD1_2_3_4_
5
29A
X_#PC_IOWR/#OE
O
© PHYTEC Messtechnik GmbH 2009
DESCRIPTION
LCD reference voltage (1.75 V - 2.8 V)
Ground 0 V
Pin left unconnected
Pin left unconnected
Display vertical synchronization pulse
Alternate crystal direction/output enable
Ground 0 V
REV signal for display
SPL/SPR signal for display
Control signal output for source driver
Pin left unconnected
Ground 0 V
Input/Output data to display
Input/Output data to display
Input/Output data to display
Input/Output data to display
Ground 0V
Input/Output data to display
Input/Output data to display
Input/Output data to display
Input/Output data to display
Ground 0 V
Input/Output data to display
Chip Select 0 output
Chip Select 1 output
Chip Select 4 output
Ground 0 V
Active low external enable byte signal that
controls
D [7:0]
NVDD1_2_3_4_ Memory Output Enable
5
L-710e_4
9
phyCOREi.MX27
10
30A
X_#LBA
O
31A
X_BCLK
O
32A
33A
GND
X_A2
O
34A
X_A4
O
35A
X_A5
O
36A
X_A7
O
37A
38A
GND
X_A10
O
39A
X_A12
O
40A
X_A13
O
41A
X_A15
O
42A
43A
GND
X_A18
O
44A
X_A20
O
45A
X_A21
O
46A
X_A23
O
47A
48A
GND
X_D0
I/O
49A
X_D2
I/O
50A
X_D3
I/O
51A
X_D5
I/O
52A
53A
GND
X_D8
I/O
54A
X_D10
I/O
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
0
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
0
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
0
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
0
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
0
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
Load Burst Address
Burst Clock
Ground 0 V
Address-Line A2
Address-Line A4
Address-Line A5
Address-Line A7
Ground 0 V
Address-Line A10
Address-Line A12
Address-Line A13
Address-Line A15
Ground 0 V
Address-Line A18
Address-Line A20
Address-Line A21
Address-Line A23
Ground 0 V
Data_Bus D0
Data_Bus D2
Data_Bus D3
Data_Bus D5
Ground 0 V
Data_Bus D8
Data_Bus D10
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Pin Description
55A
X_D11
I/O
56A
X_D13
I/O
57A
58A
GND
X_PC_BVD1
I
59A
X_PC_BVD2
I
60A
X_#PC_CD1
I
61A
X_PC_PWRON
I
62A
63A
GND
X_#PC_RW
O
64A
X_PC_VS1
I
65A
X_PC_VS2
I
66A
X_CE0
O
67A
68A
GND
X_IOIS16
I
69A
70A
71A
72A
73A
74A
75A
76A
77A
78A
79A
80A
81A
82A
83A
84A
85A
86A
X_FEC_TXD3
X_FEC_RX_ER
X_FEC_RXD2
GND
X_FEC_MDC
X_FEC_TX_CLK
X_FEC_RXD0
X_FEC_RX_CLK
GND
X_CSI_D0
X_CSI_D2
X_CSI_D3
X_CSI_D5
GND
NVDD11
X_CSI_MCLK
X_CSI_VSYNC
X_CSI_PIXCLK
O
I
I
O
O
I
I
I
I
I
I
O
O
I
I
© PHYTEC Messtechnik GmbH 2009
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
0
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
0
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
NVDD1_2_3_4_
5
0
NVDD1_2_3_4_
5
NVDD6_8_9_10
NVDD6_8_9_10
NVDD6_8_9_10
0
NVDD6_8_9_10
NVDD6_8_9_10
NVDD6_8_9_10
NVDD6_8_9_10
0
NVDD11
NVDD11
NVDD11
NVDD11
0
NVDD11
NVDD11
NVDD11
NVDD11
L-710e_4
Data_Bus D11
Data_Bus D13
Ground 0 V
PCMCIA Battery Voltage Detect Input 1
PCMCIA Battery Voltage Detect Input 2
PCMCIA Card Detect Input 1
PCMCIA Power is ON Signal
Ground 0 V
PCMCIA External Transceiver Direction Signal
PCMCIA Voltage sense Input 1
PCMCIA Voltage sense Input 2
PCMCIA Card Enable 0 Signal
Ground 0 V
PCMCIA I/O port is 16-bits
Fast Ethernet Transmit Data 3
Fast Ethernet Receive Data Error
Fast Ethernet Receive Data 2
Ground 0 V
Fast Ethernet Management Data Clock
Fast Ethernet Transmit Clock signal
Fast Ethernet Receive Data 0
Fast Ethernet Receive Clock signal
Ground 0 V
Camera Sensor D0
Camera Sensor D2
Camera Sensor D3
Camera Sensor D5
Ground 0 V
Camera reference voltage (2.8 V)
Camera Sensor Master Clock
Camera Sensor vertical sync
Camera Sensor data latch clock
11
phyCOREi.MX27
87A
88A
89A
90A
91A
92A
93A
94A
95A
96A
97A
98A
99A
100A
12
GND
X_KP_COL0
X_KP_COL1
X_KP_COL2
X_KP_ROW0
GND
X_KP_ROW3
X_KP_ROW5
X_PC28
not connected
GND
X_PC29
X_PC30
X_PC31
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
NVDD6_8_9_10
NVDD6_8_9_10
NVDD6_8_9_10
NVDD6_8_9_10
0
NVDD6_8_9_10
NVDD6_8_9_10
NVDD6_8_9_10
0
NVDD6_8_9_10
NVDD6_8_9_10
NVDD6_8_9_10
Ground 0 V
Keypad Port Column 0
Keypad Port Column 1
Keypad Port Column 2
Keypad Port Row 0
Ground 0 V
Keypad Port Row 3
Keypad Port Row 5
GPIO PC28
Pin left unconnected
Ground 0 V
GPIO PC29
GPIO PC30
GPIO PC31
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Pin Description
PIN ROW X1B
PIN #
SIGNAL
I/O
SL
DESCRIPTION
1B
X_WDI
I
LV
2B
X_VSTBY
I
LV
3B
4B
5B
6B
7B
8B
9B
10B
11B
12B
13B
14B
15B
16B
17B
18B
19B
20B
21B
22B
23B
24B
25B
26B
27B
X_PWGT1EN
GND
X_HSYNC
not connected
X_CONTRAST
X_CLS
GND
X_LSCLK
not connected
not connected
X_LD1
GND
X_LD4
X_LD6
X_LD7
X_LD9
GND
X_LD12
X_LD14
X_LD15
X_LD16
GND
X_#CSD1
X_#CS5
X_#PC_REG/#EB0
I
I/O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
LV
0
NVDD7_12_14
NVDD7_12_14
NVDD7_12_14
0
NVDD7_12_14
NVDD7_12_14
0
NVDD7_12_14
NVDD7_12_14
NVDD7_12_14
NVDD7_12_14
0
NVDD7_12_14
NVDD7_12_14
NVDD7_12_14
NVDD7_12_14
0
NVDD1_2_3_4_5
NVDD1_2_3_4_5
NVDD1_2_3_4_5
28B
X_#PC_WE/#RW
O
NVDD1_2_3_4_5
29B
30B
31B
32B
33B
34B
35B
GND
X_#ECB
X_A0
X_A1
X_A3
GND
X_A6
I
O
O
O
O
0
NVDD1_2_3_4_5
NVDD1_2_3_4_5
NVDD1_2_3_4_5
NVDD1_2_3_4_5
0
NVDD1_2_3_4_5
Watchdog input has to be kept high by the
processor to keep MC13783 active
Signal from primary processor to put
MC13783 in a low power mode
Power gate driver 1 enable
Ground 0 V
Display horizontal synchronization pulse
Pin left unconnected
Contrast control for display
CLS signal for display
Ground 0 V
Display Shift Clock
Pin left unconnected
Pin left unconnected
Input/Output data to display
Ground 0 V
Input/Output data to display
Input/Output data to display
Input/Output data to display
Input/Output data to display
Ground 0 V
Input/Output data to display
Input/Output data to display
Input/Output data to display
Input/Output data to display
Ground 0 V
Chip Select Output 1 for SDRAM
Chip Select Output 5
Active low external enable byte signal that
controls D [15:8]
#RW signal—Indicates whether external
access is a read (high) or write (low) cycle
Ground 0 V
Active low signal sent by flash device
Address-Line A0
Address-Line A1
Address-Line A3
Ground 0 V
Address-Line A6
© PHYTEC Messtechnik GmbH 2009
L-710e_4
13
phyCOREi.MX27
36B
37B
38B
39B
40B
41B
42B
43B
44B
45B
46B
47B
48B
49B
50B
51B
52B
53B
54B
55B
56B
57B
58B
59B
60B
61B
62B
63B
64B
65B
66B
67B
68B
69B
70B
71B
72B
73B
74B
75B
76B
14
X_A8
X_A9
X_A11
GND
X_A14
X_A16
X_A17
X_A19
GND
X_A22
X_A24
X_A25
X_D1
GND
X_D4
X_D6
X_D7
X_D9
GND
X_D12
X_D14
X_D15
X_#FL_WP
GND
X_#PC_CD2
X_PC_POE
X_PC_READY
X_PC_RST
GND
X_#PC_WAIT
X_CE1
NVDD1_2_3_4_5
X_FEC_TXD2
GND
X_FEC_RXD1
X_FEC_RXD3
X_FEC_MDIO
X_FEC_CRS
GND
X_FEC_RX_DV
X_FEC_COL
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
O
I
O
I
O
O
O
I
I
I/O
I
I
I
NVDD1_2_3_4_5
NVDD1_2_3_4_5
NVDD1_2_3_4_5
0
NVDD1_2_3_4_5
NVDD1_2_3_4_5
NVDD1_2_3_4_5
NVDD1_2_3_4_5
0
NVDD1_2_3_4_5
NVDD1_2_3_4_5
NVDD1_2_3_4_5
NVDD1_2_3_4_5
0
NVDD1_2_3_4_5
NVDD1_2_3_4_5
NVDD1_2_3_4_5
NVDD1_2_3_4_5
0
NVDD1_2_3_4_5
NVDD1_2_3_4_5
NVDD1_2_3_4_5
0
NVDD1_2_3_4_5
NVDD1_2_3_4_5
NVDD1_2_3_4_5
NVDD1_2_3_4_5
0
NVDD1_2_3_4_5
NVDD1_2_3_4_5
NVDD1_2_3_4_5
NVDD6_8_9_10
0
NVDD6_8_9_10
NVDD6_8_9_10
NVDD6_8_9_10
NVDD6_8_9_10
0
NVDD6_8_9_10
NVDD6_8_9_10
Address-Line A8
Address-Line A9
Address-Line A11
Ground 0 V
Address-Line A14
Address-Line A16
Address-Line A17
Address-Line A19
Ground 0 V
Address-Line A22
Address-Line A24
Address-Line A25
Data_Bus D1
Ground 0 V
Data_Bus D4
Data_Bus D6
Data_Bus D7
Data_Bus D9
Ground 0 V
Data_Bus D12
Data_Bus D14
Data_Bus D15
Flash Protection Signal
Ground 0 V
PCMCIA Card Detect Input 2
PCMCIA buffers output enable
PCMCIA Ready
PCMCIA Card Reset
Ground 0 V
PCMCIA Extend bus cycle Input
PCMCIA Card Enable 1 Signal
Fast Ethernet Transmit Data 2
Ground 0 V
Fast Ethernet Receive Data 1
Fast Ethernet Receive Data 3
Fast Ethernet Management Data Input/Output
Fast Ethernet Carrier Sense enable
Ground 0 V
Fast Ethernet Receive data Valid signal
Fast Ethernet Collision signal
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Pin Description
77B
78B
79B
80B
81B
82B
83B
84B
85B
86B
87B
88B
89B
90B
91B
92B
93B
94B
95B
96B
97B
98B
99B
100B
X_FEC_TX_ER
X_CSI_D1
GND
X_CSI_D4
X_CSI_D6
X_CSI_D7
X_FEC_TX_EN
GND
X_CSI_HSYNC
X_FEC_TXD0
X_FEC_TXD1
NVDD6_8_9_10
GND
X_KP_COL3
X_KP_ROW1
X_KP_ROW2
X_KP_ROW4
GND
X_KP_COL4
X_KP_COL5
not connected
not connected
GND
X_CLKO
O
I
I
I
I
O
I
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
O
© PHYTEC Messtechnik GmbH 2009
NVDD6_8_9_10
NVDD11
0
NVDD11
NVDD11
NVDD11
NVDD6_8_9_10
0
NVDD11
NVDD6_8_9_10
NVDD6_8_9_10
NVDD6_8_9_10
0
NVDD6_8_9_10
NVDD6_8_9_10
NVDD6_8_9_10
NVDD6_8_9_10
0
NVDD6_8_9_10
NVDD6_8_9_10
0
NVDD1_2_3_4_5
L-710e_4
Fast Ethernet Transmit Data Error
Camera Sensor D1
Ground 0 V
Camera Sensor D4
Camera Sensor D6
Camera Sensor D7
Fast Ethernet Transmit enable signal
Ground 0 V
Camera Sensor horizontal sync
Fast Ethernet Transmit Data 0
Fast Ethernet Transmit Data 1
Keypad reference voltage (2.775 V)
Ground 0 V
Keypad Port Column 3
Keypad Port Row 1
Keypad Port Row 2
Keypad Port Row 4
Ground 0V
Keypad Port Column 4
Keypad Port Column 5
Pin left unconnected
Pin left unconnected
Ground 0 V
Clock out signal selected from internal clock
signals
15
phyCOREi.MX27
PIN ROW X1C
PIN #
SIGNAL
I/O
SL
DESCRIPTION
1C
2C
3C
4C
5C
6C
7C
8C
9C
10C
11C
12C
13C
VIN
VIN
GND
VIN
VIN
Not connected
GND
VCC_3V3
VCC_3V3
VCC_3V3
VCC_3V3
GND
X_POWER_BATT
I
Power
Power
0
Power
Power
0
Power
Power
Power
Power
0
VATLAS
(2.50 V - 2.86 V)
14C
X_BATTISNS
I
VATLAS
Battery current sensing point 1
15C
16C
17C
18C
X_BATTFET
X_CHRGISNSP
GND
X_BKUP_SUPPLY
O
I
I
VATLAS
VATLAS
0
MV
Driver output for battery path FET
Charge current sensing point 1
Ground 0 V
1. Coincell supply input
2. Coincell charger output
19C
X_CHRGLED
O
EHV
20C
X_CHRGMOD0
I
VATLAS
Selection of the mode of charging
21C
X_CHRGMOD1
I
VATLAS
Selection of the mode of charging
22C
23C
GND
X_RXOUTL_LSPP
O
0
VAUDIO
Ground 0 V
24C
X_RXOUTR_LSPM
O
VAUDIO
J17=1+2
Loudspeaker minus terminal
J17=2+3
Low power receive output for accessories
right channel
25C
X_RXINL
I
VAUDIO
Receive input left channel
26C
27C
28C
X_RXINR
GND
X_MC1RIN
I
I
VAUDIO
0
VAUDIO
Receive input right channel
Ground 0 V
29C
X_MC1LIN
Ì
VAUDIO
Left microphone amplifier input
16
Main Power Input (3:3 V – 4.5 V)
Main Power Input (3.3 V – 4.65 V)
Ground 0 V
Main Power Input (3.3 V – 4.65 V)
Main Power Input (3.3 V – 4.65 V)
Pin left unconnected
Ground 0 V
Power for 3.3 V devices
Power for 3.3 V devices
Power for 3.3 V devices
Power for 3.3 V devices
Ground 0 V
1. Battery positive terminal
2. Battery current sensing point 2
3. Battery supply voltage sense
Trickle LED driver output
J18=1+2
Loudspeaker positive terminal
J18=2+3
Low power receive output for accessories left
channel
Right microphone amplifier input
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Pin Description
30C
X_#ON1
I
LV
31C
32C
33C
34C
35C
X_#ON2
GND
X_ETH_LINK
X_ETH_SPEED
X_ETH_RX-
I
O
O
I/O
LV
0
3.3V
3.3V
3.3V
36C
X_ETH_TX-
I/O
3.3V
37C
38C
39C
40C
41C
42C
43C
44C
45C
46C
47C
48C
GND
X_ETH_#PD
X_ETH_#INT
NVDD6_8_9_10
X_#TRST
GND
X_#BATTDET
X_ADIN5
X_ADIN6
X_ADIN7
GND
X_ADOUT
I
O
O
I
O
I
I
I
O
0
3.3V
3.3V
NVDD6_8_9_10
NVDD6_8_9_10
0
LV
LV
LV
LV
0
LV
49C
X_ADTRIG
I
LV
ADC trigger input
50C
51C
X_#LOWBAT
X_USEROFF
O
I
LV
LV
52C
53C
54C
55C
56C
GND
X_VBUS
X_UDM
X_UDP
X_UID
I/O
I/O
I/O
I/O
0
5V (SW3)
3.3V
3.3V
3.3V
Low battery detection signal
Signal from processor to confirm user off
mode after a power fail
Ground 0 V
USB VBUS Voltage
USB transceiver cable interface, DUSB transceiver cable interface, D+
57C
58C
59C
60C
61C
62C
63C
64C
65C
66C
67C
GND
X_PB24
X_PB23
X_USBH2_CLK
X_USBH2_DIR
GND
X_USBH2_DATA2
X_USBH2_DATA4
X_USBH2_DATA6
NVDD7_12_14
GND
I/O
I/O
I
I
I/O
I/O
I/O
O
-
0
NVDD7_12_14
NVDD7_12_14
NVDD7_12_14
NVDD7_12_14
0
NVDD7_12_14
NVDD7_12_14
NVDD7_12_14
NVDD7_12_14
0
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Power on/off button connection 1
Power on/off button connection 2
Ground 0 V
Ethernet Link & Activity Indicator (Open Drain)
Ethernet Speed Indicator (Open Drain)
Receive negative input (normal)
Transmit negative output (reversed)
Transmit negative output (normal)
Receive negative input (reversed)
Ground 0 V
Ethernet Chip power down input
Management Interface (MII) Interrupt Out
JTAG reference voltage (2.775 V)
JTAG reset
Ground 0 V
Battery thermistor presence detect output
Analog Input Channel 5
Analog Input Channel 6
Analog Input Channel 7
Ground 0 V
ADC trigger output
USB on the go transceiver cable ID resistor
connection
Ground 0 V
GPIO PB 24
GPIO PB 23
USB Host transceiver ULPI clock signal
USB Host transceiver ULPI clock signal
Ground 0 V
USB Host transceiver ULPI data signal D2
USB Host transceiver ULPI data signal D4
USB Host transceiver ULPI data signal D6
USB Host reference voltage (2.775 V)
Ground 0 V
17
phyCOREi.MX27
68C
X_SD2_D0
I/O
NVDD15
69C
X_SD2_D1
I/O
NVDD15
70C
X_SD2_D2
I/O
NVDD15
71C
X_SD2_D3
I/O
NVDD15
72C
73C
74C
75C
76C
77C
78C
79C
80C
81C
82C
83C
84C
85C
86C
87C
88C
89C
GND
X_UART2_RTS
X_UART2_CTS
not connected
not connected
GND
X_UART3_TXD
X_UART3_CTS
not connected
not connected
GND
X_I2C2_SCL
X_I2C2_SDA
X_I2C_DATA
X_CSPI1_SCLK
GND
X_CSPI1_SS1
X_CSPI3_MOSI
I
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
0
NVDD6_8_9_10
NVDD6_8_9_10
0
NVDD6_8_9_10
NVDD6_8_9_10
0
NVDD7_12_14
NVDD7_12_14
NVDD7_12_14
NVDD6_8_9_10
0
NVDD6_8_9_10
NVDD6_8_9_10
90C
91C
92C
93C
94C
95C
96C
97C
98C
99C
100C
X_#CSPI1_RDY
X_PE19
GND
X_GPT5_TOUT
X_GPT5_TIN
X_GPT4_TOUT
X_GPT4_TIN
GND
X_BOOT1
X_BOOT0
AVDD
I/O
I/O
O
I
O
I
I/O
I/O
O
NVDD6_8_9_10
NVDD6_8_9_10
0
NVDD6_8_9_10
NVDD6_8_9_10
NVDD6_8_9_10
NVDD6_8_9_10
0
AVDD
AVDD
AVDD
18
SD/MMC Data line both in 1-bit and 4-bit
mode
SD/MMC Data line or interrupt in 4-bit mode
Interrupt in 1-bit mode
SD/MMC Data line or interrupt in 4-bit mode
Interrupt in 1-bit mode
SD/MMC Card detect in power up, Data line in
4-bit mode, not used in 1-bit mode
Ground 0 V
Request to send UART 2
Clear to send UART 2
Pin left unconnected
Pin left unconnected
Ground 0 V
Serial transmit signal UART 3
Clear to send UART 3
Pin left unconnected
Pin left unconnected
Ground 0 V
I²C 2 Serial Clock
I²C 2 Serial Data
I²C 1 Serial Data
SPI 1 clock
Ground 0 V
SPI 1 Chip select 1
SPI 3 Master data out; slave data in
Used as GPIO PE22
SPI 1 SPI data ready in Master mode
GPIO PE19
Ground 0 V
General purpose timer 5 output
General purpose timer 5 input
General purpose timer 4 output
General purpose timer 4 input
Ground 0 V
Boot-Mode 1
Boot-Mode 0
BOOT (0-3) reference voltage (1.8 V)
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Pin Description
PIN ROW X1D
PIN #
SIGNAL
I/O
SL
DESCRIPTION
1D
2D
3D
4D
5D
6D
7D
VIN
VIN
GND
X_#RESET_OUT
X_#RESET
X_#RESET
X_IMX27_FUSE
O
O
O
I
Power
Power
0
NVDD1_2_3_4_5
NVDD1_2_3_4_5
NVDD1_2_3_4_5
3.0 V
8D
X_TOUT
O
3.3 V
9D
10D
I
I
0
EHV
(max. 20 V)
EHV
I
EHV
Charger Input
I
EHV
Charger Input
14D
15D
16D
GND
X_CHARGER_INPUT
_3-20V
X_CHARGER_INPUT
_3-20V
X_CHARGER_INPUT
_3-20V
X_CHARGER_INPUT
_3-20V
GND
X_CHRGISNSN
X_BFET
I
O
0
VATLAS
EHV
17D
X_CHRGCTL
O
EHV
18D
X_PWRRDY
O
LV
Power ready signal after DVS and power
gate transition
19D
20D
GND
X_GPO1
O
0
LV
Ground 0 V
21D
22D
X_GPO2
X_UART_RXD_RS232
O
O
23D
X_UART_TXD_RS232
O
24D
25D
GND
X_UART_RTS_RS232
O
26D
X_UART_CTS_RS232
O
27D
X_GPO3
O
LV
RS232/
NVDD6_8_9_10
RS232/
NVDD6_8_9_10
0
RS232/
NVDD6_8_9_10
RS232/
NVDD6_8_9_10
LV
11D
12D
13D
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Main Power Input (3.3 V – 4.65 V)
Main Power Input (3.3 V – 4.65 V)
Ground 0 V
Reset Output from the i.MX27
Reset Input/Output
Reset Input/Output
Fusebox write (program) Supply Voltage
(3.0 V)
Open-Drain Thermostat Output of U10
(DS75)
Ground 0 V
Charger Input
Charger Input
Ground 0 V
Charge current sensing point 2
1. Driver output for dual path regulated BP
FET
2. Driver output for separate USB charger
path FET
Driver output for charger path FET’s
General purpose output 1
General purpose output 2
Serial Data receive line UART X
Serial Data transmit line UART X
Ground 0 V
Request to send UART X
Clear to send UART X
General purpose output 3
19
phyCOREi.MX27
28D
29D
30D
X_GPO4
GND
X_TSX1
O
O
31D
X_TSX2
O
32D
X_TSY1
O
33D
X_TSY2
O
34D
35D
GND
X_ETH_RX+
I/O
36D
X_ETH_TX+
I/O
37D
38D
39D
40D
41D
42D
43D
44D
45D
46D
47D
48D
49D
50D
51D
52D
53D
54D
55D
56D
57D
58D
59D
60D
61D
62D
63D
X_#ON3
X_TCK
GND
X_TDI
X_TDO
X_TMS
X_JTAG_CTRL
GND
X_ADIN8
X_ADIN9
X_ADIN10
X_ADIN11
GND
X_USBH1_RXDM
X_USBH1_RXDP
X_USBH1_TXDM
X_USBH1_TXDP
GND
X_USBH1_RCV
X_USB_HS_/PSW
X_USB_HS_FAULT
X_USBH1_SUSP
GND
X_USBH2_STP
X_USBH2_NXT
X_USBH2_DATA0
X_USBH2_DATA1
I
I
I
O
I
I
I
I
I
I
I
I
O
O
O
O
I
I
O
I
I/O
I/O
20
LV
0
LV
General purpose output 4
Ground 0 V
ADC generic input channel 12 or
touchscreen input X1, group 2
LV
ADC generic input channel 13 or
touchscreen input X2, group 2
LV
ADC generic input channel 14 or
touchscreen input Y1, group 2
LV
ADC generic input channel 15 or
touchscreen input Y2, group 2
0
Ground 0 V
3.3 V
Receive positive input (normal)
Transmit positive output (reversed)
3.3 V
Transmit positive output (normal)
Receive positive input (reversed)
LV
Power on/off button connection 3
NVDD6_8_9_10 JTAG clock
0
Ground 0 V
NVDD6_8_9_10 JTAG Data In
NVDD6_8_9_10 JTAG Data Out
NVDD6_8_9_10 JTAG Mode select
NVDD1_2_3_4_5 JTAG Mode
0
Ground 0 V
LV
Analog Input Channel 8
LV
Analog Input Channel 9
LV
Analog Input Channel 10
LV
Analog Input Channel 11
0
Ground 0 V
NVDD7_12_14
USB Host1 Receive Data Minus signal
NVDD7_12_14
USB Host1 Receive Data Plus signal
NVDD7_12_14
USB Host1 Transmit Data Minus signal
NVDD7_12_14
USB Host1 Transmit Data Plus signal
0
Ground 0 V
NVDD7_12_14
USB Host1 RCV signal
5V
USB-OTG Power switch output open drain
5V
USB-OTG over current input signal
NVDD7_12_14
USB Host1 Suspend signal
0
Ground 0 V
NVDD7_12_14
USB Host transceiver ULPI stop signal
NVDD7_12_14
USB Host transceiver ULPI next signal
NVDD7_12_14
USB Host transceiver ULPI data signal D0
NVDD7_12_14
USB Host transceiver ULPI data signal D1
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Pin Description
64D
GND
-
0
65D
66D
X_USBH2_DATA3
I/O
NVDD7_12_14
USB Host transceiver ULPI data signal D3
X_USBH2_DATA5
I/O
NVDD7_12_14
USB Host transceiver ULPI data signal D5
67D
X_USBH2_DATA7
I/O
NVDD7_12_14
68D
X_SD2_CMD
I/O
NVDD15
69D
GND
-
0
70D
X_SD2_CLK
O
NVDD15
SD/MMC Clock for MMC/SD/SDIO
71D
NVDD15
O
NVDD15
SD2 reference voltage (2.775 V)
72D
X_UART2_TXD
O
NVDD6_8_9_10
73D
X_UART2_RXD
I
NVDD6_8_9_10
74D
GND
-
0
75D
X_#USBH1_OE
O
NVDD7_12_14
USB Host1 Output Enable signal
76D
X_USBH1_FS
O
NVDD7_12_14
USB Host1 Full Speed output signal
77D
X_UART3_RXD
I
NVDD6_8_9_10
Serial data receive signal UART 3
78D
X_UART3_RTS
I
NVDD6_8_9_10
79D
GND
-
0
Ground 0 V
80D
not connected
-
-
Pin left unconnected
81D
X_PRIINT
O
NVDD6_8_9_10
Primary Interrupt output of PMIC U14
82D
X_#IRQRTC
O
NVDD6_8_9_10
Interrupt Output from RTC U11
(RTC-8564JE)
83D
NVDD6_8_9_10
O
NVDD6_8_9_10
84D
GND
-
0
85D
X_I2C_CLK
I/O
NVDD6_8_9_10
I²C 1 Serial Clock
86D
X_CSPI1_MOSI
I/O
NVDD6_8_9_10
SPI 1 Master data out; slave data in
87D
X_CSPI1_MISO
I/O
NVDD6_8_9_10
SPI 1 Master data in; slave data out
88D
X_CSPI3_SCLK
NVDD6_8_9_10
SPI 3 clock
Used as GPIO PE23
89D
GND
90D
X_CSPI3_MISO
-
0
Ground 0 V
USB Host transceiver ULPI data signal D7
SD/MMC line connect to card
Ground 0 V
Serial data transmit signal UART 2
Serial data receive signal UART 2
Ground 0 V
Request to send UART 3
I2C reference voltage (2.775 V)
Ground 0 V
Ground 0 V
NVDD6_8_9_10
SPI 3 Master data in; slave data out
Used as GPIO PE18
91D
X_OWIRE
I/O
NVDD6_8_9_10
1-Wire bus
92D
NVDD6_8_9_10
O
NVDD6_8_9_10
1-Wire reference voltage (2.775 V)
93D
X_PE20
I/O
NVDD6_8_9_10
GPIO PE20
94D
GND
-
0
Ground 0 V
95D
X_CSPI3_SS
96D
X_TIN
97D
NVDD6_8_9_10
SPI 3 Chip select
Used as GPIO PE21
I
NVDD6_8_9_10
Timer Input Clock-The signal on this input is
applied to GPT 1–3 simultaneously
X_TOUT1
O
NVDD6_8_9_10
Timer Output signal from General Purpose
Timer1 (GPT1)
98D
X_BOOT2
I/O
AVDD
99D
GND
-
0
X_PWMO
O
NVDD6_8_9_10
100D
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Boot-Mode 2
Ground 0 V
Pulse Width Modulator Output
21
phyCOREi.MX27
22
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Jumpers
3 Jumpers
For configuration purposes, the phyCORE-i.MX27 has 24 solder jumpers, some of which have been
installed prior to delivery. Figure 5 illustrates the numbering of the solder jumper pads, while Figure 6
and Figure 7 indicate the location of the solder jumpers on the board. 8 solder jumpers are located on
the top side of the module (opposite side of connectors) and 16 solder jumpers are located on the
bottom side of the module (connector side). Table 2 below provides a functional summary of the
solder jumpers, their default positions, and possible alternative positions and functions. A detailed
description of each solder jumper can be found in the applicable section listed in the table.
Figure 5:
Typical jumper pad numbering scheme
© PHYTEC Messtechnik GmbH 2009
L-710e_4
23
phyCOREi.MX27
J9
J21
J1
J13
JN2
JN1
J16
J15
Figure 6:
24
Jumper locations (top view)
© PHYTEC Messtechnik GmbH 2009
L-710e_4
C108
Jumpers
J6 J7J4
J2
J3
J5
J17
J18
J11
J8
J10
J12
J22
J20
J14
J19
Figure 7:
Jumper locations (bottom side in top view)
© PHYTEC Messtechnik GmbH 2009
L-710e_4
25
phyCOREi.MX27
The jumpers (J = solder jumper) have the following functions:
Table 2:
Jumper settings
DEFAULT SETTING
J1
closed
J2
closed
J3
open
J4
open
ALTERNATIVE SETTING
EEPROM U12 is not write
open
protected
Power up Mode select
open
(PUMS1) is connected to GND
(low)
Power up Mode select
closed
(PUMS1) is floating
Power up Mode select
(PUMS1) is floating
closed
J5
closed
J6
open
J7
open
Power up Mode select
(PUMS3) is floating
closed
J9
closed
open
J10
closed
J12
closed
CHRGMOD1 is connected to
VATLAS (high)
Signal X_PWGT1EN is
connected to the MolexConnector (X1 – Pin 3B)
Signal X_PRIINT is connected
to X_PB23 (GPIO)
J13
2+3
1+2
J14
2+3
J15
2+3
J16
2+3
J17
2+3
J18
2+3
EEPROM A1 is connected to
NVDD7_12_14 (high)
DS75 A1 is connected to
NVDD7_12_14 (high)
EEPROM A2 is connected to
GND (low)
EEPROM A0 is connected to
GND (low)
RXOUTR is connected to
X_RXOUTR_LSPM
(X1 – Pin 24C)
RXOUTL is connected to
X_RXOUTL_LSPP
(X1 – Pin 23C)
26
Power up Mode select
open
(PUMS2) is connected to GND
(low)
Power up Mode select
closed
(PUMS3) is floating
open
open
1+2
1+2
1+2
1+2
1+2
EEPROM U12 is write
protected
Power up Mode select
(PUMS1) is floating
Power up Mode select
(PUMS1) is connected to
VATLAS (high)
Power up Mode select
(PUMS2) is connected to
VATLAS (high)
Power up Mode select
(PUMS2) is floating
Power up Mode select
(PUMS3) is connected to
VATLAS (high)
Power up Mode select
(PUMS3) is connected to
GND (low)
CHRGMOD1 is floating
(high-z)
Signal X_PWGT1EN is not
connected to the MolexConnector (X1 – Pin 3B)
Signal X_PRIINT is not
connected to X_PB23
(GPIO)
EEPROM A1 is connected to
GND (low)
DS75 A1 is connected to
GND (low)
EEPROM A2 is connected to
NVDD7_12_14 (high)
EEPROM A0 is connected to
NVDD7_12_14 (high)
LSPM is connected to
X_RXOUTR_LSPM
(X1 – Pin 24C)
LSPP is connected to
X_RXOUTL_LSPP
(X1 – Pin 23C)
© PHYTEC Messtechnik GmbH 2009
SEE
SECTION
7.5.2
0
7.5
7.5
7.5
L-710e_4
Jumpers
J19
2+3
J20
1+3
2+4
J21
2+3
J22
closed
JN1
2+3
JN2
2+3
DS75 A2 is connected to GND
(low)
#SRAM_BHE is connected to
X_#PC_IORD/#EB1
X_#PC_REG/#EB0 is
connected to #SRAM_BLE
If main clock is generated by
crystal
If Sofware-Reset (GPIO) is
used to reset ETH_PHY
If 8-bit mode is used for
NAND-Flash
If 8-bit mode is used for
NAND-Flash
© PHYTEC Messtechnik GmbH 2009
L-710e_4
1+2
1+2
3+4
1+2
open
1+2
1+2
DS75 A2 is connected to
NVDD7_12_14 (high)
#SRAM_BHE is connected
to X_#PC_REG/#EB0
X_#PC_IORD/#EB1 is
connected to #SRAM_BLE
If main clock is generated by
oscillator
If no Sofware-Reset (GPIO)
is used to reset ETH_PHY
If 16-bit mode is used for
NAND-Flash
If 16-bit mode is used for
NAND-Flash
7.4.1
7.4.1
27
phyCOREi.MX27
28
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Power Requirements
4 Power Requirements
The phyCORE-i.MX27 normally operates off two different voltage supplies denoted as VIN and
VCC_3V3. The MC13783 primary on-board voltage regulator operates off VIN and generates all
on-board supply voltages except 3.3 V. The VCC_3V3 input supplies this required voltage.
Because of its wide input voltage range VIN is ideally suited for a battery. VCC_3V3, however, has a
very narrow input voltage range and must not be connected to a battery. A well regulated supply
should be used for VCC_3V3.
The phyCORE-i.MX Carrier Board generates VCC_3V3 from VIN with a 3.3 V voltage regulator on the
Carrier Board. VIN is sourced from either the wall socket input, or a battery. The Carrier Board also
controls charging the battery when the wall socket is used. You should refer to this example circuitry
when designing your own Carrier Board.
If your system does not require a battery then you can connect VIN and VCC_3V3 together and
supply both inputs with a 3.3 V input voltage. This will simplify the design and reduce the component
count. In this case make sure that the X_CHARGER_INPUT_3-20V is connected to a power supply
>4.4V. You also have to design a 0.02R resistor between X_POWER_BATT and X_BATTISNS and a
22µF capacitor at X_POWER_BATT. Put both components as close as possible to the module
connector. (see Figure 8 and Table 3 )
Figure 8:
minimum circuit
© PHYTEC Messtechnik GmbH 2009
L-710e_4
29
phyCOREi.MX27
Table 3:
Power supply for the minimum circuit
power supply
5 V (x_Charger_Input)
3.3 V (VIN)
3.3 V (VCC_3V3)
min.
4.4 V
3.25 V
3.15 V
typ.
5V
3.3 V
3.3 V
max.
20 V
4.5 V
3.45 V
The input voltage range of VIN is from 3.1 V.. 4.65 V, with a nominal current allowance of at least 3 A.
VCC_3V3 should be in a range of 3.3 V ± 0.15 V (±0.05 V if VCC_3V3 is connected to VIN) with a
nominal current allowance of at least 1.5 A.
See Table 1 from section 2 above for applicable VIN / VCC_3V3 power pins on the
phyCORE-connector.
Caution!
Connect all VIN and VCC_3V3 input pins to your power supplies.
As a general design rule we recommend connecting all GND pins which are neighboring signals
being used in the application circuitry.
The i.MX27 CPU is supplied by a lot of different power domains. Some of them are connected
together. The startup voltage levels are selected by the Power up Mode selection inputs (PUMS1..3)
of the PMIC device MC13783. With the default settings of the input pins PUMS1..3 the voltages are
the following:
Table 4:
i.MX27 default power input voltages
MC13783 POWER OUTPUT
SW1
SW2
SW3
VAUDIO
VIOLO
VIOHI
VGEN
VCAM
VRF1
VRF2
VMMC1
POWER-DOMAIN
QVDD
NVDD1_2_3_4_5
SW3
internally used by MC13783
AVDD
OSC26VDD
PLL_VDD
NVDD11
NVDD7_12_14
NVDD6_8_9_10
NVDD15
STARTUP VOLTAGE-LEVEL
1.2 V
1.8 V
5V
2.775 V
1.8 V
2.775 V
1.5 V
2.8 V
2.775 V
2.775 V
2.775 V
In general you should not need to adjust the Power up Mode settings. The configuration has been
optimized for the phyCORE-i.MX27 together with the phyCORE-i.MX Carrier Board.
30
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Real Time Clock U11
5 Real Time Clock U11 / SRAM U19 BackupVoltage
In case of a power fail or a user off event the backup-voltage AVDD_BKUP provides power to the I²C
Real Time Clock U11 (RTC8564JE) and the low power SRAM U19. In this cases a backup coincell
will supply the memory and the RTC via AVDD_BKUP (VBKUP2 of MC13783).
To set the output voltage and the different modes of VBKUP2, U14 (MC13783) must be programmed
over SPI.
Table 5:
VBKUP2 Voltage Settings
VBKUP2[1:0]
00
output = 1.0 V
01
10
11
output = 1.2 V
output = 1.5 V
output = 1.8 V
There are three bits which must be set to low/high for the different modes of VBKUP2:
VBKUP2EN:
VBKUP2AUTOMH:
VBKUP2AUTOUO:
Enables VBKUP2 in startup modes, on and user off wait modes
Enables VBKUP2 in memory hold modes
Enables VBKUP2 in user off modes
For further information refer to the MC13783 manual chapter 5.2. Operating Modes.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
31
phyCOREi.MX27
32
© PHYTEC Messtechnik GmbH 2009
L-710e_4
System Configuration
6
System Configuration
Although most features of the Freescale phyCORE-i.MX27 microcontroller are configured and/or programmed during the initialization routine, other features, which impact program execution, must be
configured prior to initialization via pin termination.
6.1
System Startup Configuration
During the reset cycle the i.MX27 processor reads the state of selected controller signals to determine
the basic system configuration. The configuration circuitries (pull-up or pull-down resistors) are
located on the phyCORE module. They are already set, so no further settings are necessary.
6.1.1 Power-Up-Mode-Select (PUMS)
The Power-Management-IC (M13783) has three Power-Up-Mode-Selecets. PUMS1 and PUMS2
determine the initial setup for the voltage level of the switchers and regulators and if they get enabled
or not. With PUMS3 three different power up sequences are selectable.
The three states of the PUMS settings are:
-
Pull-up (connected to VATLAS)
Pull-down (connected to GND)
Open (no jumper populated/left open)
For detailed information about PUMS and the power up sequence, refer to the MC13783 IC User’s
Guide, chapter 5.3 Power up.
The i.MX27 module (PCM-038) comes with a standard Power-Up-Mode-Select (see table below).
Table 6:
Default PUMS for i.MX27 module
PUMS1
PUMS2
PUMS3
GND
GND
Open
Note:
The i.MX27 controller has a defined power up sequence. Refer to the i.MX27 Data Sheet, chapter 3.3
Power-Up sequence.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
33
phyCOREi.MX27
6.1.2 Boot Mode Select
The i.MX27 controller has different boot modes, which can be selected. The system boot mode of the
processor is determined by the configuration of the four external input pins, BOOT[3:0].
Table 7:
Boot Modes of i.MX27 module
Boot Mode Selection
0000
0001
0010
0011
0100
0101
0110
0111
1xxx
Boot Mode/Device
Bootstrap from UART/USB
Reserved
8-bit NAND Flash (2 Kbyte per page)
16-bit Nand Flash (2 Kbyte per page)
16-bit Nand Flash (512 bytes per page)
16-bit CS0 (NOR-Flash)
32-bit CS0
8-bit Nand Flash (512 bytes per page)
Reserved
The phyCORE-i.MX27 module comes with a standard boot configuration of ‘0101’, so the system will
boot from the 16-bit NOR-Flash at CS0.
34
© PHYTEC Messtechnik GmbH 2009
L-710e_4
System Memory
7 System Memory
The phyCORE-i.MX27 provides different types of on-board memory:
•
•
•
•
•
LP-DDR-SDRAM:
SRAM:
NAND Flash:
NOR Flash:
I²C-EEPROM:
128 MByte
512KByte
64 MByte
32MByte
32 KB
(up to 256 MByte)
(up to 2 MByte)
(up to 1 GByte)
(up to 64 MByte)
(up to 32 KByte)
It should be noted that the LP-DDR-SDRAM has a dedicated memory bus to the i.MX27
microcontroller. The LP-DDR-SDRAM bus is therefore not made available at the phyCORE-connector
X1.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
35
phyCOREi.MX27
7.1 Memory Model
The i.MX27 memory map is summarized in Table 8 below. For a detailed view of the memory map
please consult the Freescale i.MX27 User’s Manual.
Table 8:
i.MX27 memory map
ADDRESS
0xA000 0000 – 0xAFFF FFFF
0xB000 0000 – 0xBFFF FFFF
0xC000 0000 – 0xC7FF FFFF
0xC800 0000 – 0xCFFF FFFF
0xD400 0000 – 0xD5FF FFFF
0xD600 00000 – 0xD7FF
FFFF
36
CHIP-SELECT
FUNCTION
/CSD0 (/CS2)
LP-DDR-SDRAM Bank 0 (U3,
U4)
not used on phyCORE-i.MX27
NOR-Flash (U17)
SRAM (U19)
not used on phyCORE-i.MX27
not used on phyCORE-i.MX27
(SJA1000 on Carrier Board)
/CSD1 (/CS3)
/CS0
/CS1
/CS4
/CS5
© PHYTEC Messtechnik GmbH 2009
L-710e_4
System Memory
7.2 LP-DDR-SDRAM (U3-U4)
The phyCORE-i.MX27 has one bank of LP-DDR-SDRAMs on the i.MX27.
The RAM bank is comprised of two 16-bit wide DDR-SDRAM chips, configured for 32-bit access, and
operating at 133 MHz. In lower density configurations, U3 and U4 populate the module and are
accessed via SDRAM memory bank 0 using chip select signal /CSD0 starting at 0xA000 0000.
Actually the RAM bank 1 is not populated and the /CSD1 chip select line is freed and can be used as
/CS3.
Typically the LP-DDR-SDRAM initialization is performed by a boot loader or operating system
following a power-on reset and must not be changed at a later point by any application code. When
writing custom code independent of an operating system or boot loader, SDRAM must be initialized
by accessing the appropriate SDRAM configuration registers on the i.MX27 controller. Refer to the
i.MX27 User Manual for accessing and configuring these registers.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
37
phyCOREi.MX27
7.3 NOR-Flash (U17)
The phyCORE-i.MX27 can be populated with an Intel Strata Flash at U17. This NOR-Flash is
connected to /CS0 which is located at memory address 0xC000 0000. The entire Flash can be write
protected by pulling the x_/FL_WP signal, located at the phyCORE-connector X1 on pin 58B, low.
The following NOR-Flash devices can be used on the phyCORE-i.MX27:
Table 9:
Compatible NOR Flash devices
MANUFACTURER
Intel
Intel
Intel
38
NOR FLASH P/N
PC28F640P30
PC28F128P30
PC28F256P30
DENSITY (MBYTE)
8
16
32
© PHYTEC Messtechnik GmbH 2009
L-710e_4
System Memory
7.4 NAND Flash Memory (U16)
Use of Flash as non-volatile memory on the phyCORE-i.MX27 provides an easily reprogrammable
means of code storage. The following Flash devices can be used on the phyCORE-i.MX27:
Table 10:
Compatible NAND Flash devices
MANUFACTURER
ST Microelectronics
ST Microelectronics
NAND FLASH P/N
NAND256R3A2BZA6
NAND512R3A2BZA6
DENSITY (MBYTE)
32
64
Additionally, any parts that are footprint (VFBGA) and functionally compatible with the NAND Flash
devices listed above may also be used with the phyCORE-i.MX27.
These Flash devices are programmable with 1.8 V. No dedicated programming voltage is required.
As of the printing of this manual these NAND Flash devices generally have a life expectancy of at
least 100,000 erase/program cycles and a data retention rate of 10 years.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
39
phyCOREi.MX27
7.4.1 8/16-Bit NAND Flash Usage (JN1,JN2,RN31,RN32)
The i.MX27 is capable of using 8-Bit and 16-Bit NAND Flash devices. To select between 8- and 16-bit
NAND Flash, the jumpers/resistor networks must be populated as follows:
Table 11:
JN1/2,RN31/32 NAND Flash bit width selection 1
NAND-FLASH BIT WIDTH
8-bit
16-bit
1
40
JN1/2
RN31/32
2-3/5-6/8-9/11-12
1-2/4-5/7-8/10-11
not populated
populated
Default settings are in bold blue text
© PHYTEC Messtechnik GmbH 2009
L-710e_4
System Memory
7.5 I²C EEPROM (U12)
The phyCORE-i.MX27 is populated with a ST 24W32C 1 non-volatile 32 KByte EEPROM (U12) with
an I²C interface to store configuration data or other general purpose data. This device is accessed
through I²C port 2 on the i.MX27. The serial clock signal and serial data signal for I²C port 2 are made
available at the phyCORE-connector as x_I2C2_SDA on X1 pin 84C and x_I2C2_SCL on X1 pin 83C.
Three solder jumpers are provided to set the lower address bits: J13, J15, and J16. Refer to section
7.5.1 for details on setting these jumpers.
Write protection to the device is accomplished via jumper J1. By default this jumper is closed, allowing
write access to the EEPROM. Removing this jumper will cause the EEPROM to enter write protect
mode, thereby disabling write access to the device. Refer to section 7.5.2 for further details on setting
this jumper.
1:
See the manufacturer’s data sheet for interfacing and operation.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
41
phyCOREi.MX27
7.5.1 Setting the EEPROM Lower Address Bits
(J13, J15, J16)
The 32 KB I²C EEPROM populating U12 on the phyCORE-module has the capability of configuring
the lower address bits A0, A1, and A2. The four upper address bits of the device are fixed at ‘1010’
(see ST 24W32C data sheet). The remaining three lower address bits of the seven bit I²C device
address are configurable using jumpers J13, J15 and J16. J16 sets address bit A0, J13 address bit
A1, and J15 address bit A2.
Table 12 below shows the resulting seven bit I²C device address for the eight possible jumper
configurations.
Table 12:
1
42
U12 EEPROM I²C address via J13, J15, and J16 1
U12 I²C DEVICE ADDRESS
J15
J13
J16
1010 010
1010 011
1010 000
1010 001
1010 110
1010 111
1010 100
1010 101
2+3
2+3
2+3
2+3
1+2
1+2
1+2
1+2
2+3
2+3
1+2
1+2
2+3
2+3
1+2
1+2
2+3
1+2
2+3
1+2
2+3
1+2
2+3
1+2
Defaults are in bold blue text
© PHYTEC Messtechnik GmbH 2009
L-710e_4
System Memory
7.5.2 EEPROM Write Protection Control (J1)
Jumper J1 controls write access to the EEPROM (U12) device. Closing this jumper allows write
access to the device, while opening this jumper enables write protection.
The following configurations are possible:
Table 13:
EEPROM write protection states via J1 1
EEPROM WRITE PROTECTION STATE
Write access allowed
Write protected
1
J1
closed
open
Defaults are in bold blue text
© PHYTEC Messtechnik GmbH 2009
L-710e_4
43
phyCOREi.MX27
44
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Serial Interface
8
Serial Interface
8.1 RS-232 Transceiver (U18)
One high-speed RS-232 transceiver supporting 460kbps data rates populates the phyCORE-i.MX27
at U18. This device converts the signal levels for:
•
RXD1/TXD1/RTS1/CTS1 (UART1)
The RS-232 interface enables connection of the module to a COM port on a host-PC. In this instance
the RxD line of the transceiver is connected to the TxD line of the COM port; while the TxD line of the
transceiver is connected to the RxD line of the COM port. The ground potential of the phyCOREi.MX27 circuitry needs to be connected to the applicable ground pin on the COM port as well.
The phyCORE-i.MX27 does not convert the remaining two available UARTs (UART2, UART3)
provided by the i.MX27 MCU to RS-232 levels. The TTL level signals are made available at the
phyCORE-connector X1 (see Table 1). External RS-232 transceivers must be supplied by the user if
additional UART’s require RS-232 levels.
The maximum baud rate of UART1 is limited to 460,800 bps when used with the on-board MAX3380
RS-232 transceiver.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
45
phyCOREi.MX27
8.1.1 UART1 Routing (RN30)
RN30 is used to route the signals of UART1 serial interface through the RS-232 transceiver or around
the RS-232 transceiver when populated. When RN30 is not populated UART1_RXD, UART1_TXD,
UART1_RTS and UART1_CTS are routed through the RS-232 transceiver U18 and come out as
X_UART1_RXD_RS232,
X_UART1_TXD_RS232,
x_UART1_RTS_RS232
and
x_UART1_CTS_RS232 at the phyCORE-connector pins X1 pin 22D, X1 pin 23D, X1 pin 25D, X1 pin
26D. If U18 does not populate the module, RN30 is populated to route the TTL level signals to these
same pins.
The standard phyCORE-i.MX27 module will have U18 populated, thereby routing the RS-232 level
signals to the phyCORE-connector. Be sure the phyCORE-i.MX27 configuration you are working with
before interfacing these signals outside of the module as incorrect voltage levels will likely cause
damage to on-board and off-board components.
The following configurations are possible:
Table 14:
RN30 UART1 signal routing 1
SIGNAL CONFIGURATION
RN30
X_UART1_RXD_RS232, X_UART1_TXD_RS232, X_UART1_ not populated
RTS_RS232, X_ UART1_CTS_RS232 as RS-232 level
signals at X1 pin 22D, X1 pin 23D, X1 pin 25D and X1 pin
26D
X_UART1_RXD_RS232, X_UART1_TXD_RS232,
populated
X_UART1_ RTS_RS232, X_ UART1_CTS_RS232 as TTL
level signals at X1 pin 22D, X1 pin 23D, X1 pin 25D and X1
pin 26D
1
46
Defaults are in bold blue text
© PHYTEC Messtechnik GmbH 2009
L-710e_4
USB-OTG Transceiver
9 USB-OTG Transceiver (U20)
The phyCORE-i.MX27 comes populated with a NXP ISP1504 USB On-The-Go High-Speed
transceiver (U20) supporting high speed, full speed, and low speed data rates. The ISP1504 functions
as the transceiver between the i.MX27 Host Controller, Device Controller, and On-The-Go Controller.
An external USB Standard-A (for USB host), USB Standard-B (for USB device), or USB mini-AB (for
USB OTG) connector is all that is needed to interface the phyCORE-i.MX27 USB OTG functionality.
The applicable interface signals (D+/D-/VBUS/ID) can be found in the phyCORE-connector pin-out
Table 1.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
47
phyCOREi.MX27
10 Ethernet Controller / Ethernet-Phy (U9)
Connection of the phyCORE-i.MX27 to the world wide web (WWW) or a local area network (LAN) is
possible with the internal 10/100 Mbps Fast Ethernet controller. With this Ethernet controller an
external transceiver interface and transceiver function are required to complete the interface to the
media. Therefor the i.MX27 uses an Ethernet-Phy (U9).
The Ethernet-Phy provides MII/RMII/SMII interfaces to transmit and receive data. In addition the PHY
also supports HP Auto-MDIX technology, eliminating the need for the consideration of a direct
connect LAN cable, or a cross-over patch cable. It detects the TX and RX pins of the connected
device and automatically configures the PHY TX and RX pins accordingly. The Ethernet-Phy also
features LinkMD cable diagnostics, which allows detection of common cabling plant problems such as
open and short circuits.
The physical memory area for the Fast Ethernet controller is defined in Table 15.
Table 15:
Fast Ethernet controller memory map
ADDRESS
0x1002_B + 0x000-1FF
0x1002_B + 0x200-3FF
FUNCTION
Control/Status Registers
MIB Block Counters
Connection to an external Ethernet transformer should be done using very short signal traces. The
TPI+/TPI- and TPO+/TPO- signals should be routed as 100 Ohm differential pairs. The same applies
for the signal lines after the transformer circuit. The carrier board layout should avoid any other signal
lines crossing the Ethernet signals.
Caution!
Please note the datasheet of the Ethernet-Phy when creating the Ethernet transformer circuitry.
48
© PHYTEC Messtechnik GmbH 2009
L-710e_4
JTAG Interface (U15)
11 JTAG Interface (U15)
The phyCORE-i.MX27 is equipped with a JTAG interface for downloading program code into the
external flash, internal controller RAM or for debugging programs currently executing. The JTAG
interface extends out to a 2.0 mm pitch pin header at U15 on the edge of the module PCB. Figure 9
and Figure 10 show the position of the debug interface (JTAG connector U15) on the phyCOREmodule.
U15
2
Figure 9:
4
6
8
10
12
14
16
18
20
JTAG interface at U15 (top view)
© PHYTEC Messtechnik GmbH 2009
L-710e_4
49
phyCOREi.MX27
U15
Figure 10: JTAG interface at U15 (bottom view)
Pin 1 of the JTAG connector U15 is on the connector side of the module. Pin 2 of the JTAG connector
is on the controller side of the module.
Note:
The JTAG connector U15 only populates phyCORE-i.MX27 modules with order code PCM-038-D.
JTAG connector U15 is not populated on phyCORE modules with order code PCM-038. However, all
JTAG signals are also accessible at the phyCORE-connector X1 (Molex connectors). We recommend
integration of a standard (2.54 mm pitch) pin header connector in the user target circuitry to allow
easy program updates via the JTAG interface. See Table 16 for details on the JTAG signal pin
assignment.
50
© PHYTEC Messtechnik GmbH 2009
L-710e_4
JTAG Interface (U15)
Table 16:
JTAG connector U15 signal assignment
SIGNAL
VCC(NVDD6_8_9_10
)
GND
GND
GND
GND
GND
GND
GND
GND
GND
PIN
ROW*
A
B
2
1
4
6
8
10
12
14
16
18
20
3
5
7
9
11
13
15
17
19
SIGNAL
VTref (NVDD6_8_9_10 via 100
Ohm)
X_#TRST
X_TDI
X_TMS
X_TCK
RTCK (10k Ohm pulldown)
X_TDO
X_#RESET
Not connected
J_DBGACK (10k Ohm pulldown)
*Note:
Row A is on the controller side of the module and row B is connector side of the module
PHYTEC offers a JTAG-Emulator adapter (order code JA-002) for connecting the phyCORE-i.MX27
to a standard emulator. The JTAG-Emulator adapter extends the signals of the module's JTAG
connector to a standard ARM connector with 2.54 mm pin pitch. The JA-002 therefor functions as an
adapter for connecting the module's non-ARM-compatible JTAG connector U15 to standard Emulator
connectors.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
51
phyCOREi.MX27
52
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Technical Specifications
12 Technical Specifications
The physical dimensions of the phyCORE-i.MX27 are represented in Figure 11. The module's profile
is approximately 8.5 mm thick, with a maximum component height of 4.0 mm on the bottom
(connector) side of the PCB and approximately 3.1 mm on the top (microcontroller) side. The board
itself is approximately 1.4 mm thick.
3.6mm
3.7mm
3.28mm
6.88mm
6.25mm
4.75mm
0.635mm
75.1mm
77.15mm
77.47mm
84mm
10.58mm
8.93mm
60mm
55.35mm
53.85mm
2.35mm
Figure 11: Physical dimensions
© PHYTEC Messtechnik GmbH 2009
L-710e_4
53
phyCOREi.MX27
Additional specifications:
•
•
Dimensions:
60 mm x 84 mm
Weight:
•
•
Storage temperature:
approximately 35 g with all optional
components mounted on the circuit board
-20°C to +125°C
•
•
•
Humidity:
0°C to +70°C (standard)
-20°C to +85°C (optional)
95 % r.F. not condensed
Operating voltage:
VIN 3.1 V to 4.6 V
Power consumption:
VCC_3V3 / 43 mA typical
VIN / 100 mA typical
Conditions:
VCC_3V3 = 3.3 V, VIN = 4.25 V
256 kByte SRAM, 32 MByte Flash, 128 MB
LP-DDR-RAM, 64 MB NAND-Flash,
Ethernet, 400 MHz CPU frequency at 20°C
Operating temperature:
These specifications describe the standard configuration of the phyCORE-i.MX27 as of the printing of
this manual.
54
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Hints for Handling
13 Hints for Handling the phyCORE-i.MX27
Removal of various components, such as the microcontroller and the standard quartz, is not
advisable given the compact nature of the module. Should this nonetheless be necessary, please
ensure that the board as well as surrounding components and sockets remain undamaged while desoldering. Overheating the board can cause the solder pads to loosen, rendering the module
inoperable. Carefully heat neighboring connections in pairs. After a few alternations, components can
be removed with the solder-iron tip. Alternatively, a hot air gun can be used to heat and loosen the
bonds.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
55
phyCOREi.MX27
56
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
14 The phyCORE i.MX27 on the i.MX Carrier Board
In this chapter you will find the information about using the phyCORE-i.MX27 module with the
phyCORE i.MX Carrier Board.
You will get an overview of how the phyCORE-i.MX27 module works with the phyCORE-i.MX Carrier
Board, how both boards are connected together over the phyMAPPER and you will also find all
settings that have to be done for a speedy and secure start-up of your i.MX27 module.
In this chapter you will only find specialized information of how the phyCORE-i.MX27 module works
with the phyCORE-i.MX Carrier Board. For further information about the Carrier Board please refer to
the i.MX Carrier Board Hardware Manual.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
57
phyCOREi.MX27
14.1 Concept of the phyCORE-i.MX Development Kits
Phytec decided to use one i.MX Carrier Board for different i.MX modules. Because every i.MX module
has different features and therefore a different pinning it is necessary to map the signals of the
modules to the right place on the Carrier Board.
For this every i.MX module comes with a phyMAPPER that is mapping the signals of the i.MX module
to the i.MX Carrier Board.
An example of the concept is shown in Figure 12 below. For further information about the concept of
the i.MX Carrier Board refer to the i.MX Carrier Board Hardware Manual.
Figure 12: phyCORE-i.MX27 Carrier Board connection using the phyMAP-i.MX27
Figure 13 below illustrates the modular development platform concept:
Patch Field
LCD Adapter
Expansion
Board
i.MX 27 Module
i.MX 27 Mapper
i.MX Carrier Board
Expansion Bus
Connectors
Figure 13: Modular development and Expansion Board concept with
phyCORE-i.MX27
58
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
14.2 phyMAP-i.MX27
The phyMAP-i.MX27 is responsible for mapping the signals from the various phyCORE-i.MX modules
to the phyCORE-i.MX Carrier Board. Signal differences at the connectors on the phyCORE-i.MX
modules, along with signal differences between the phyCORE-i.MX module connectors and i.MX
Carrier Board connector do not allow for direct connection of the phyCORE-i.MX modules into a
single, standardized Carrier Board. To allow for the use of a single Carrier Board, despite the signal
differences, the phyMAP-i.MX27 board serves as the gateway to properly map signals from the i.MX
Carrier Board Molex connectors to the various phyCORE-i.MX module connectors.
X1
J2
J1
X1
Figure 14: phyMAP-i.MX27 top view
© PHYTEC Messtechnik GmbH 2009
L-710e_4
59
phyCOREi.MX27
X2
X2
X2
Figure 15: phyMAP-i.MX27 bottom view
60
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
14.2.1
phyMAP-i.MX27 Jumper Settings
X1
J2
J1
X1
Figure 16: Jumper location on PMA-005
There are 2 solder jumpers (0805) available on the phyMAP-i.MX27 Mapper. They are used to set
different functions partially in relation with the i.MX Carrier Board.
An individual description of the jumpers and a list of all jumper settings you will find subsequent.
J1
With this jumper you can select the backup power supply of the module. If it is set to 1+2 the
backup power supply device is the goldcap C161 of the Carrier Board. If J1 is set to 2+3 the
backup power is provided by a Li-Cell at connector X20 of the Carrier Board.
J2
Whether the Phytec provided Sharp-Display or the Hitachi-Display is used with the i.MX27
Development Kit this jumper has to be set to the right position. In position 1+2 the X_OE_ACD
signal for the Hitachi Display is connected to the display. When J2 is set to 2+3 the X_PS
signal for the Sharp-Display is connected to the display.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
61
phyCOREi.MX27
Table 17:
JUMPER
J1
J2
62
Jumper settings of PMA-002
SETTING
1+2
2+3
1+2
2+3
DESCRIPTION
x_BKUP_SUPPLY supplied by X_LICELL
x_BKUP_SUPPLY supplied by X_VBAT
Hitachi display is used
Sharp display is used
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
14.2.2
phyMAP-i.MX27 Signal Mapping
In the following table you will find all signals of the phyCORE-i.MX27 module (PCM-038) connected
through the phyMAP-i.MX27 mapper (PMA-002) to the phyCORE-i.MX Carrier Board (PCM-970).
Take care that there are some signals connected to jumpers on the phyMAP-i.MX27 mapper. With
this signals it depends on the individual jumper setting where this signals are connected to. This
signals are in bold text.
Table 18:
PMA-002 mapping list
SIGNAL NAME ON
PMA-002 MAPPER
X1 PIN #
X_#BATTDET
X_#CSD1
X_#CSPI1_RDY
X_#CS0
X_#CS1
X_#CS4
X_#CS5
X_#ECB
X_#FL_WP
X_#IRQRTC
X_#LBA
X_#LOWBAT
X_#ON1
X_#ON2
X_#ON3
X_#PC_CD1
X_#PC_CD2
X_#PC_IORD/#EB1
X_#PC_IOWR/#OE
X_#PC_REG/#EB0
X_#PC_RW
X_#PC_WAIT
X_#PC_WE/#RW
X_#RESET
X_#RESET_OUT
X_#RST_MCU
43C
25B
90C
24A
25A
26A
26B
30B
58B
82D
30A
50C
30C
31C
37D
60A
60B
28A
29A
27B
63A
65B
28B
5D
4D
6D
MAPPED
TO
© PHYTEC Messtechnik GmbH 2009
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
L-710e_4
X2 PIN # SIGNAL NAME ON I.MX
CARRIER BOARD
25E
2F
41F
1E
1F
58A, 3E
3F
4E
49E
45E
54A
31E
55D
56C
56D
66A
66B
56B
53A
55B
64A
61B
55A
68D
68C
4D, 5D,
44C
x_EXP038
x_EXP002
x_EXP065
x_EXP000
x_EXP001
x_/CS_CAN, x_EXP003
x_EXP004
x_EXP005
x_EXP077
x_EXP070
x_LBA
x_EXP048
x_/ON1
x_/ON2
x_/ON3
x_/PC_CD1
x_/PC_CD2
x_/EB1
x_/OE
x_/EB0
x_/PC_RW
x_/PC_WAIT
x_/WR
x_EXP081
x_EXP080
x_/RESET_3V3, x_/Reset_Btn,
x_JTAG_SRST
63
phyCOREi.MX27
X_#TRST
X_#USBH1_OE
X_ADIN5
X_ADIN6
X_ADIN7
X_ADIN8
X_ADIN9
X_ADIN10
X_ADIN11
X_ADOUT
X_ADTRIG
X_A0
X_A1
X_A2
X_A3
X_A4
X_A5
X_A6
X_A7
X_A8
X_A9
X_A10
X_A11
X_A12
X_A13
X_A14
X_A15
X_A16
X_A17
X_A18
X_A19
X_A20
X_A21
X_A22
X_A23
X_A24
X_A25
X_BATTFET
64
41C
75D
44C
45C
46C
45D
46D
47D
48D
48C
49C
31B
32B
33A
33B
34A
35A
35B
36A
36B
37B
38A
38B
39A
40A
40B
41A
41B
42B
43A
43B
44A
45A
45B
46A
46B
47B
15C
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
43D
35F
25F
26E
26F
27F
28E
28F
29E
30E
30F
27B
28A
28B
29A
30A
30B
31A
31B
32B
33A
33B
34A
35A
35B
36A
36B
37B
38A
38B
39A
40A
40B
41A
41B
42B
43A
15C
x_CPU_/TRST
x_EXP055
x_EXP039
x_EXP040
x_EXP041
x_EXP042
x_EXP043
x_EXP044
x_EXP045
x_EXP046
x_EXP047
x_A0
x_A1
x_A2
x_A3
x_A4
x_A5
x_A6
x_A7
x_A8
x_A9
x_A10
x_A11
x_A12
x_A13
x_A14
x_A15
x_A16
x_A17
x_A18
x_A19
x_A20
x_A21
x_A22
x_A23
x_A24
x_A25
x_BATTFET
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
X_BATTISNS
X_BCLK
X_BFET
X_BKUP_SUPPLY
X_BOOT0
X_BOOT1
X_BOOT2
X_CE0
X_CE1
X_CHARGER_INPUT_3
-20V
X_CHRGCTL
X_CHRGISNSN
X_CHRGISNSP
X_CHRGLED
X_CHRGMOD0
X_CLKO
X_CLS
X_CONTRAST
X_CSI_D0
X_CSI_D1
X_CSI_D2
X_CSI_D3
X_CSI_D4
X_CSI_D5
X_CSI_D6
X_CSI_D7
X_CSI_HSYNC
X_CSI_MCLK
X_CSI_PIXCLK
X_CSI_VSYNC
X_CSPI1_MISO
X_CSPI1_MOSI
X_CSPI1_SCLK
X_CSPI1_SS1
X_D0
X_D1
X_D2
14C
31A
16D
18C
<->
<->
<->
<->
14C
18E
17D
18C, (6C)
x_BATTISNS
x_EXP027
x_BFET
x_LICELL, (x_VBAT)
99C
98C
98D
66A
66B
10D, 11D,
12D, 13D
17D
15D
16C
19C
20C
100B
8B
7B
78A
78B
79A
80A
80B
81A
81B
82B
85B
84A
86A
85A
87D
86D
86C
88C
48A
48B
49A
<->
<->
<->
<->
<->
<->
100B
53C
53D
58B
57B
10D, 11D,
12D, 13D
18D
16D
16C
19C
20C
20F
8B
7B
75A
75B
76A
76B
77B
78A
78B
79A
73B
69A
71B
72B
96B
95B
97B
98B
43B
44A
45A
x_switch
x_BOOT_MODE0
x_BOOT_MODE1
x_/CE2
x_/CE1
Charger_Input ->
x_Charger_Input
x_CHRGCTL
x_CHRGISNSN
x_CHRGISNSP
x_CHRGLED
x_CHRGMOD0
x_EXP031
x_LC_D3_CLS
x_LC_CONTRAST
x_CSI_D2
x_CSI_D3
x_CSI_D4
x_CSI_D5
x_CSI_D6
x_CSI_D7
x_CSI_D8
x_CSI_D9
x_CSI_HSYNC
x_CSI_MCLK
x_CSI_PCLK
x_CSI_VSYNC
x_MISO
x_MOSI
x_SPICLK
X_CE
x_D0
x_D1
x_D2
© PHYTEC Messtechnik GmbH 2009
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
L-710e_4
65
phyCOREi.MX27
X_D3
X_D4
X_D5
X_D6
X_D7
X_D8
X_D9
X_D10
X_D11
X_D12
X_D13
X_D14
X_D15
X_ETH_#PD
X_ETH_LINK
X_ETH_RX+
X_ETH_RXX_ETH_SPEED
X_ETH_TX+
X_ETH_TXX_FEC_COL
X_FEC_CRS
X_FEC_MDC
X_FEC_MDIO
X_FEC_RXD0
X_FEC_RXD1
X_FEC_RXD2
X_FEC_RXD3
X_FEC_RX_CLK
X_FEC_RX_DV
X_FEC_RX_ER
X_FEC_TXD0
X_FEC_TXD1
X_FEC_TXD2
X_FEC_TXD3
X_FEC_TX_CLK
X_FEC_TX_EN
X_FEC_TX_ER
66
50A
50B
51A
51B
52B
53A
53B
54A
55A
55B
56A
56B
57B
38C
33C
35D
35C
34C
36D
36C
76B
73B
73A
72C
75A
70B
71A
71B
76A
75B
70A
86B
87B
68B
69A
74A
83B
77B
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
45B
46A
46B
47B
48A
48B
49A
50A
50B
51A
51B
52B
53B
5E
32D
30C
31C
33D
30D
31D
15E
11F
11E
10F
13E
8F
9E
10E
14E
13F
8E
16F
17F
6F
7F
12F
16E
15F
x_D3
x_D4
x_D5
x_D6
x_D7
x_D8
x_D9
x_D10
x_D11
x_D12
x_D13
x_D14
x_D15
x_EXP006
x_ETH_/LED1
x_ETH_TPI+
x_ETH_TPIx_ETH_/LED2
x_ETH_TPO+
x_ETH_TPOx_EXP022
x_EXP017
x_EXP016
x_EXP015
x_EXP019
x_EXP012
x_EXP013
x_EXP014
x_EXP021
x_EXP020
x_EXP011
x_EXP025
x_EXP026
x_EXP009
x_EXP010
x_EXP018
x_EXP024
x_EXP023
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
X_GPO1
X_GPO2
X_GPO3
X_GPO4
X_GPT4_TIN
X_GPT4_TOUT
X_GPT5_TIN
X_GPT5_TOUT
X_HSYNC
X_IMX27_FUSE
X_IOIS16
X_I2C_CLK
X_I2C_DATA
X_I2C2_SCL
X_I2C2_SDA
X_JTAG_CTRL
X_KP_COL0
X_KP_COL1
X_KP_COL2
X_KP_COL3
X_KP_COL4
X_KP_COL5
X_KP_ROW0
X_KP_ROW1
X_KP_ROW2
X_KP_ROW3
X_KP_ROW4
X_KP_ROW5
X_LD0
X_LD1
X_LD2
X_LD3
X_LD4
X_LD5
X_LD6
X_LD7
X_LD8
X_LD9
20D
21D
27D
28D
96C
95C
94C
93C
5B
7D
68A
85D
85C
83C
84C
43D
88A
89A
90A
90B
95B
96B
91A
91B
92B
93A
93B
94A
13A
13B
14A
15A
15B
16A
16B
17B
18A
18B
© PHYTEC Messtechnik GmbH 2009
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
L-710e_4
21F
22F
23E
23F
46E
46F
47F
48F
11A
6D
65A
99A
100A
39E
40E
43C
48D
49C
50C
50D
51C
51D
45C
45D
46C
46D
47D
48C
13A
13B
14A
15A
15B
16A
16B
17B
18A
18B
x_EXP033
x_EXP034
x_EXP035
x_EXP036
x_EXP072
x_EXP073
x_EXP074
x_EXP076
x_LC_FPLINE
x_iMX_FUSE
x_IOIS16
x_I2C_SCL
x_I2C_SDA
x_EXP061
x_EXP062
x_CPU_SJC_MOD
x_KEY_COL0
x_KEY_COL1
x_KEY_COL2
x_KEY_COL3
x_KEY_COL4
x_KEY_COL5
x_KEY_ROW0
x_KEY_ROW1
x_KEY_ROW2
x_KEY_ROW3
x_KEY_ROW4
x_KEY_ROW5
x_LC_D0
x_LC_D1
x_LC_D2
x_LC_D3
x_LC_D4
x_LC_D5
x_LC_D6
x_LC_D7
x_LC_D8
x_LC_D9
67
phyCOREi.MX27
X_LD10
X_LD11
X_LD12
X_LD13
X_LD14
X_LD15
X_LD16
X_LD17
X_LSCLK
X_MC1LIN
X_MC1RIN
X_OE_ACD
X_OWIRE
X_PB24
X_PC_BVD1
X_PC_BVD2
X_PC_POE
X_PC_PWRON
X_PC_READY
X_PC_RST
X_PC_VS1
X_PC_VS2
X_PC28
X_PC29
X_PC30
X_PC31
X_PE18
X_PE19
X_PE20
X_PE21
X_PE22
X_PE23
X_POWER_BATT
X_PRIINT
X_PS
X_PWMO
X_PWRRDY
68
19A
20A
20B
21A
21B
22B
23B
23A
10B
29C
28C
6A
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
19A
20A
20B
21A
21B
22B
23B
23A
10B
29C
28C
10A, 24E
x_LC_D10
x_LC_D11
x_LC_D12
x_LC_D13
x_LC_D14
x_LC_D15
x_LC_D16
x_LC_D17
x_LC_BCLK
x_MC1LIN
x_MC1RIN
x_LC_DRDY0, x_EXP037
91D
58C
58A
59A
61B
61A
62B
63B
64A
65A
95A
98A
99A
100A
90D
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
x_1Wire
x_CSI_ENABLE
x_PC_BVD1
x_PC_BVD2
x_PCOE
x_PC_PWRON
x_PC_READY
x_PC_RST
x_PC_VS1
x_PC_VS2
x_SD_W
x_SD_D
x_SNAPSHOT
x_TRIGGER
x_LED, x_EXP007, x_EXP066
91C
39C
3B
2B
1B
13C
81D
10A
<->
<->
<->
<->
<->
<->
<->
<->
58D
70B
60A
61A
62B
63A
63B
65B
67B
68B
95A
94A
71A
70A
58C, 5F,
42F
59A, 96A
70D
43E
41E
40F
15D
69C
10A
x_CAN_INT, x_/IRQ
x_EXP084
x_EXP067
x_EXP064
x_EXP063
x_Power_BATT
x_EXP082
x_LC_DRDY0
100D
18D
<->
<->
45F
6E
x_EXP071
x_EXP008
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
X_REV
X_RXINL
X_RXINR
X_RXOUTL_LSPP
X_RXOUTR_LSPM
X_SD2_CLK
X_SD2_CMD
X_SD2_D0
X_SD2_D1
X_SD2_D2
X_SD2_D3
X_SPL_SPR
X_TCK
X_TDI
X_TDO
X_TIN
X_TMS
X_TOUT
X_TOUT1
X_TSX1
X_TSX2
X_TSY1
X_TSY2
X_UART1_CTS_RS232
X_UART1_RTS_RS232
X_UART1_RXD_RS232
X_UART1_TXD_RS232
X_UART2_CTS
X_UART2_RTS
X_UART2_RXD
X_UART2_TXD
X_UART3_CTS
X_UART3_RTS
X_UART3_RXD
X_UART3_TXD
X_UDM
X_UDP
X_UID
8A
25C
26C
23C
24C
70D
68D
68C
69C
70C
71C
9A
38D
40D
41D
96D
42D
8D
97D
30D
31D
32D
33D
26D
25D
22D
23D
74C
73C
73D
72D
79C
78D
77D
78C
54C
55C
56C
© PHYTEC Messtechnik GmbH 2009
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
L-710e_4
8A
25C
26C
23C
24C
91A
90B
91B
92B
93A
93B
9A
40D
39C
40C
50F
41C
48E
50E
25D
26D
27D
28D
65C
66C
65D
66D
61D
60D
61C
60C
38E
38F
36F
37F
34C
35C
36C
x_LC_D3_REV
x_RXINL
x_RXINR
x_RXOUTL
x_RXOUTR
x_SD1_CLK
x_SD1_CMD
x_SD1_DATA0
x_SD1_DATA1
x_SD1_DATA2
x_SD1_DATA3
x_LC_D3_SPL
x_CPU_TCK
x_CPU_TDI
x_CPU_TDO
x_EXP079
x_CPU_TMS
x_EXP075
x_EXP078
x_TSX1
x_TSX2
x_TSY1
x_TSY2
x_CTS_RS232
x_RTS_RS232
x_RXD_RS232
x_TXD_RS232
x_CTS_DCE1_TTL
x_RTS_DCE1_TTL
x_RXD_DCE1_TTL
x_TXD_DCE1_TTL
x_EXP059
x_EXP060
x_EXP057
x_EXP058
x_UDM
x_UDP
x_UID
69
phyCOREi.MX27
X_USBH1_FS
X_USBH1_RCV
X_USBH1_RXDM
X_USBH1_RXDP
X_USBH1_SUSP
X_USBH1_TXDM
X_USBH1_TXDP
X_USBH2_CLK
X_USBH2_DATA0
X_USBH2_DATA1
X_USBH2_DATA2
X_USBH2_DATA3
X_USBH2_DATA4
X_USBH2_DATA5
X_USBH2_DATA6
X_USBH2_DATA7
X_USBH2_DIR
X_USBH2_NXT
X_USBH2_STP
X_USB_HS_/PSW
X_USB_HS_FAULT
X_USEROFF
X_VBUS
X_VSYNC
76D
55D
50D
51D
58D
52D
53D
60C
62D
63D
63C
65D
64C
66D
65C
67D
61C
61D
60D
56D
57D
51C
53C
5A
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
<->
36E
34E
31F
32F
35E
33E
33F
83A
85A
85B
86A
86B
87B
88A
88B
89A
84A
83B
82B
35D
36D
21E
33C
5B
x_EXP056
x_EXP053
x_EXP049
x_EXP050
x_EXP054
x_EXP051
x_EXP052
x_USBHOST2_CLK
x_USBHOST2_DA0
x_USBHOST2_DA1
x_USBHOST2_DA2
x_USBHOST2_DA3
x_USBHOST2_DA4
x_USBHOST2_DA5
x_USBHOST2_DA6
x_USBHOST2_DA7
x_USBHOST2_DIR
x_USBHOST2_NXT
x_USBHOST2_STP
x_USB_HS_/PSW
x_USB_HS_FAULT
x_EXP032
x_VBUS
x_LC_FPFRAME
Note:
Signals in bold text are connected to jumpers. The mapping of this signals could differ from the
mapping list. Please check the positions of the affected jumpers to find out how the signals are
mapped.
70
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
14.2.3
phyMAP-i.MX27 Mapper Physical Dimensions
1.64mm
102mm
7.84mm
3.6mm
19.4mm
70mm
50.6mm
47.6mm
2mm
1.65mm
1.65mm
3.65mm
11.56mm
2mm
2mm
66.17mm
70.17mm
77.37mm
80.5mm
Figure 17: Physical dimensions of phyMAP-i.MX27 mapper
© PHYTEC Messtechnik GmbH 2009
L-710e_4
71
phyCOREi.MX27
14.3 Cooperation of phyCORE-i.MX27 and
phyCORE-i.MX Carrier Board
In this chapter you will find specific information and settings to adapt the i.MX Carrier Board to the
i.MX27 module.
For information about the general functionality of the various interfaces of the phyCORE-i.MX Carrier
Board, please refer to the phyCORE-i.MX Carrier Board Hardware Manual.
72
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
Power Supply
Line I N
MI C
CAN
Line OUT
X27
USB
USB-OTG
P1
RS232 disable
RS232 aut oshut down
SERI AL 1+2
1-W
I RE
14.3.1
1
CAN- by
JP31
CAN-pwr
3V3
JP38
VI N
JP36
JP33
JP34
JP40
1
SJC-Mode
5V
Reset
Power On
GPI O
Suspend
Char ging
1
Boot Mode/ CLK-Sel.
PHYTEC
St andby
JP39
MATRI X KEYBOARD
JTAG
DMC
S/ N
PCM-970
COMPACT FLASH
X21
MAI N-LI -Cell
JP35
At t ent ion see manual
5V DC 3A
CHARGER
VCC CF
CAN-PLD
JP32
X26
PL 1280.4
1
BACKUP-LI - Cell
LCD-SW
CAMERA
DI SPLAY
MMC-SD
VCC LCD
1
C
A
D
B
1
Figure 18: pyhCORE-i.MX Carrier Board and phyCORE-i.MX27 Power Supply
Subsequent you will find the different jumper settings for the three power supply modes described in
the phyCORE-i.MX Carrier Board Hardware Manual.
Note:
With the phyCORE-i.MX27 module the Power Management IC MC13783 is provided so battery
charging is also provided with the i.MX27 module.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
73
phyCOREi.MX27
14.3.1.1
Power Supply via Power Plug
Table 19 below shows the jumper settings to supply the phyCORE-i.MX27 module and the
phyCORE-i.MX Carrier Board with a wall charger at X26 of the i.MX Carrier Board.
Table 19:
JUMPER
SETTING
JP31
1+3,2+4
3+5,4+6
Power source is Power Over Ethernet (POE)
Power source is 5 V adapter
JP32
1+3,2+4
3+5,4+6
No power switching, direct supply of VCC_3V3
Separate supply path
JP33
1+2,3+4
open,open
No power switching, direct supply from VCC_3V3
Separate supply path
JP34
1+2,3+4
open,open
No power switching, direct supply from VCC_3V3
Separate supply path
JP35
open
closed
VCC_5V Power Supply is enabled
VCC_5V Power Supply is disabled
JP36
open
closed
VCC_3V3 Power Supply is disabled
VCC_3V3 Power Supply is enabled
JP38
1+2,3+4
open,open
Power switching, supply from 5 V adapter or POE
No power switching, direct supply from VCC_3V3
JP39
1+2,3+4
open,open
open
closed
Power switching active, Battery charge path closed
No power switching, direct supply from VCC_3V3
No power switching active, minimum circuit
Power switching active
JP40
7
74
Jumper settings for i.MX27 power supply via power plug 7
DESCRIPTION
Settings for the phyCORE-i.MX27 power supply via power plug are in bold blue
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
14.3.1.2
Power Supply via Power over Ethernet
Table 20 below shows the jumper settings to supply the phyCORE-i.MX27 module and the
phyCORE-i.MX Carrier Board with Power over Ethernet at X27.
Table 20:
JUMPER
SETTING
JP31
1+3,2+4
3+5,4+6
Power source is Power Over Ethernet (POE)
Power source is 5V adapter
JP32
1+3,2+4
3+5,4+6
No power switching, direct supply of VCC_3V3
Separate supply path
JP33
1+2,3+4
open,open
No power switching, direct supply from VCC_3V3
Separate supply path
JP34
1+2,3+4
open,open
No power switching, direct supply from VCC_3V3
Separate supply path
JP35
open
closed
VCC_5V Power Supply is enabled
VCC_5V Power Supply is disabled
JP36
open
closed
VCC_3V3 Power Supply is disabled
VCC_3V3 Power Supply is enabled
JP38
1+2,3+4
open,open
Power switching, supply from 5 V adapter or POE
No power switching, direct supply from VCC_3V3
JP39
1+2,3+4
open,open
open
closed
Power switching active, Battery charge path closed
No power switching, direct supply from VCC_3V3
No power switching active, minimum circuit
Power switching active
JP40
8
Jumper settings for i.MX27 power supply via POE 8
DESCRIPTION
Settings for the phyCORE-i.MX27 power supply via Power over Ethernet are in bold blue
© PHYTEC Messtechnik GmbH 2009
L-710e_4
75
phyCOREi.MX27
14.3.1.3
Power Supply via Battery
Table 21 below shows the jumper settings to supply the phyCORE-i.MX27 module and the
phyCORE-i.MX Carrier Board with a battery at X21 of the i.MX Carrier Board.
Table 21:
JUMPER
SETTING
JP31
1+3,2+4
3+5,4+6
Power source for battery charging is Power Over Ethernet (POE)
Power source for battery charging is 5 V adapter
JP32
1+3,2+4
3+5,4+6
No power switching, direct supply of VCC_3V3
Separate supply path
JP33
1+2,3+4
open,open
No power switching, direct supply from VCC_3V3
Separate supply path
JP34
1+2,3+4
open,open
No power switching, direct supply from VCC_3V3
Separate supply path
JP35
open
closed
VCC_5V Power Supply is enabled
VCC_5V Power Supply is disabled
JP36
open
closed
VCC_3V3 Power Supply is disabled
VCC_3V3 Power Supply is enabled
JP38
1+2,3+4
open,open
Power switching, supply from 5 V adapter or POE
No power switching, direct supply from VCC_3V3
JP39
1+2,3+4
open,open
open
closed
Power switching active, Battery charge path closed
No power switching, direct supply from VCC_3V3
No power switching active, minimum circuit
Power switching active
JP40
9
76
Jumper settings for i.MX27 power supply via battery 9
DESCRIPTION
Settings for the phyCORE-i.MX27 power supply via battery are in bold blue
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
14.3.2
CAN Interface
P1
1-WIRE
MI C
RS232 disable
JP11 JP7
1
RS232 aut oshut down
SERI AL 1+2
Line I N
CAN
Line OUT
USB
USB-OTG
P2
JP10
CAN- by
JP9JP8
Power On
VI N
GPI O
Suspend
Char ging
MAI N-LI -Cell
VCC CF
1
1
MATRI X KEYBOARD
JTAG
Boot Mode/ CLK-Sel.
PHYTEC
St andby
DMC
S/ N
PCM-970
COMPACT FLASH
3V3
SJC-Mode
5V
Reset
5V DC 3A
CHARGER
At t ent ion see manual
CAN-PLD
CAN-pwr
PL 1280.4
1
BACKUP-LI - Cell
LCD-SW
CAMERA
DI SPLAY
MMC-SD
VCC LCD
1
C
A
D
B
1
Figure 19: phyCORE-i.MX Carrier Board CAN Interface
The phyCORE-i.MX27 does not provide a CAN controller. For CAN support there is a CAN controller
available on the Carrier Board that is connected to the data-/address bus of the phyCORE-i.MX27.
Please refer to Table 22 below for the jumper settings to use the CAN interface with the i.MX27
module.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
77
phyCOREi.MX27
Table 22:
CAN interface jumper settings 10
JUMPER
SETTING
DESCRIPTION
JP7
1+2
2+3
CANTxD signal is routed to the CAN transceiver
x_CAN_TxD signal is routed to the CAN transceiver
JP8
1+2
2+3
Digital Isolator is supplied by VCC_CAN
Digital Isolator supply is VCC_5V
JP9
1+2
2+3
CANV- is connected to GND of i.MX Carrier Board
CANV- is not connected to GND of i.MX Carrier Board
JP10
1+2
2+3
CANRxd signal is routed to the CAN transceiver
x_CAN_RxD signal is routed to the CAN transceiver
JP11
1+2
2+3
CANV+ is connected to VCC_5V of i.MX Carrier Board
CANV+ is connected to CAN_OUT (external supply)
10 Default settings for the phyCORE-i.MX27 CAN interface on the i.MX Carrier Board are in bold blue
78
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
Push Buttons and LEDs
Line I N
MI C
CAN
Line OUT
USB
USB-OTG
14.3.3
RS232 disable
D19
RS232 aut oshut down
SERI AL 1+2
1-W
I RE
P1
1
CAN- by
CAN-pwr
D42
3V3
VI N
S3
S4
GPI O
Suspend
MAI N-LI -Cell
St andby
Char ging
D21
D22
D23
D40
D41
VCC CF
1
S5
1
MATRI X KEYBOARD
JTAG
Boot Mode/ CLK-Sel.
PHYTEC
DMC
BACKUP-LI - Cell
D20
S/ N
PCM-970
COMPACT FLASH
5V
Reset
Power On
SJC-Mode
S1
S2
5V DC 3A
CHARGER
At t ent ion see manual
CAN-PLD
PL 1280.4
1
D50
LCD-SW
D24
CAMERA
DI SPLAY
MMC-SD
VCC LCD
1
C
A
D
B
1
Figure 20: phyCORE-i.MX Carrier Board Buttons and LEDs
The GPIO signal to drive the User-LED D40 high or low is the X_PE18 signal of the i.MX27 module.
Caution!
GPIO PE18 can also be used to manage the power supply of the CF interface on the i.MX Carrier Board.
If you only want to drive the User-LED D40 high or low make sure, that jumper JP604 is closed to force
the CF interface active.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
79
phyCOREi.MX27
14.3.3.1
Boot-Mode and Clock Selection
Note:
Clock selection is not available with the i.MX27 module.
The i.MX27 controller is able to boot from different devices as described in chapter 6.1.2. To have a
choice from which device the controller should boot the boot signals BOOT0 to BOOT2 are connected to
the dip-switch S5 on the i.MX Carrier Board.
With S5 on the i.MX Carrier Board it is possible to select the status of BOOT0, BOOT1 and BOOT2. For
detailed information see Table 23, Table 24 and Table 25 below.
Note:
A standard Boot Configuration is already set on the i.MX27 module. Here you can change the Boot Mode
to an alternatively mode. For standard Boot Configuration all dip switches have to be in OFF position.
Table 23:
x_BOOT_MODE0 selection
STATE OF SW NUMBER
3
STATE OF SW NUMBER
4
ON
OFF
OFF
ON
Table 24:
STATE OF SW NUMBER
6
ON
OFF
OFF
ON
STATE OF X_BOOT2
0
1
x_switch
STATE OF SW NUMBER
7
STATE OF SW NUMBER
8
ON
OFF
OFF
ON
80
0
1
x_BOOT_MODE1 selection
STATE OF SW NUMBER
5
Table 25:
STATE OF X_BOOT1
STATE OF X_BOOT0
0
1
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
Compact Flash Card
Line I N
MI C
CAN
Line OUT
USB
USB-OTG
14.3.4
RS232 disable
RS232 aut oshut down
SERI AL 1+2
1-W
I RE
P1
1
CAN- by
CAN-pwr
GPI O
Suspend
Char ging
MAI N-LI -Cell
1
MATRI X KEYBOARD
JTAG
Boot Mode/ CLK-Sel.
PHYTEC
St andby
DMC
S/ N
PCM-970
X10
PL 1280.4
COMPACT FLASH
VI N
JP604
1
SJC-Mode
3V3
Power On
At t ent ion see manual
5V
Reset
5V DC 3A
CHARGER
VCC CF
CAN-PLD
1
BACKUP-LI - Cell
LCD-SW
JP4
JP17
JP602
JP5
CAMERA
DI SPLAY
MMC-SD
VCC LCD
1
C
A
D
B
1
Figure 21: Compact Flash Card Interface
The GPIO signal of the i.MX27 module connected to signal x_EXP007 of the i.MX Carrier Board is
X_PE18. With GPIO PE18 the power supply of the CF interface can be managed.
Caution!
GPIO PE18 is also used with the User-LED D40 on the i.MX Carrier Board.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
81
phyCOREi.MX27
Table 26:
JUMPER
1
82
CF interface jumper settings 1
SETTING
DESCRIPTION
JP4
closed
open
/PC_RW signal can manage the data direction of U13
Data direction of U13 is from controller to CF
JP5
closed
open
Compact Flash is Master
Compact Flash is Slave
JP17
open
closed
Output 2 of U15 is active
Output 2 of U15 is disabled
JP602
closed
open
PC_RW non-inverted
PC_RW inverted
JP604
closed
open
Power supply of CF is forced active
Power supply of CF can be managed by GPIO signal x_EXP007
Default settings for the phyCORE-i.MX27 CF interface on the i.MX Carrier Board are in bold blue
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
Security Digital Card/ MultiMedia Card
Line I N
MI C
CAN
Line OUT
USB
USB-OTG
14.3.5
RS232 disable
RS232 aut oshut down
SERI AL 1+2
1-W
I RE
P1
1
CAN- by
CAN-pwr
VI N
GPI O
Suspend
Char ging
MAI N-LI -Cell
VCC CF
1
1
MATRI X KEYBOARD
JTAG
Boot Mode/ CLK-Sel.
PHYTEC
St andby
DMC
S/ N
PCM-970
COMPACT FLASH
3V3
Power On
SJC-Mode
5V
Reset
5V DC 3A
CHARGER
At t ent ion see manual
CAN-PLD
PL 1280.4
1
BACKUP-LI - Cell
LCD-SW
VCC LCD
MMC-SD
X15
JP50
CAMERA
DI SPLAY
JP18
1
C
A
D
B
1
Figure 22: SD Card interface
The MMC_DETECT signal is connected to GPIO signal X_PC29 of the i.MX27 module.
MMC_WP is connected to GPIO signal X_PC28.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
83
phyCOREi.MX27
Table 27:
JUMPER
1
84
SD/MMC interface jumper settings for i.MX27 module 1
SETTING
DESCRIPTION
JP50
2+3
1+2
MMC_WP signal of SD/MMC Interface is connected to GPIO
MMC_WP signal of SD/MMC Interface is not connected to GPIO
JP18
2+3
1+2
Level shifter U25 is enabled
Level shifter U25 is disabled
Default settings for the phyCORE-i.MX27 SD/MMC interface are in bold blue
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
14.3.6
Audio and Touchscreen
P1
RS232 disable
JP47
JP48
JP49
RS232 aut oshut down
SERI AL 1+2
JP28
JP25
JP27
JP26
1-W
I RE
MI C
CAN
Line I N
JP24
JP23
JP20
JP19
JP21
JP22
Line OUT
USB
USB-OTG
X13 X12 X11
1
CAN- by
CAN-pwr
VI N
GPI O
Suspend
Char ging
MAI N-LI -Cell
VCC CF
1
1
MATRI X KEYBOARD
JTAG
Boot Mode/ CLK-Sel.
PHYTEC
St andby
DMC
S/ N
PCM-970
COMPACT FLASH
3V3
Power On
SJC-Mode
Reset
5V DC 3A
CHARGER
At t ent ion see manual
CAN-PLD
5V
PL 1280.4
1
BACKUP-LI - Cell
LCD-SW
MMC-SD
VCC LCD
CAMERA
DI SPLAY
X23
1
C
A
D
B
1
Figure 23: phyCORE-i.MX Carrier Board Audio/Touch Interface
With the phyCORE-i.MX27 module the MC13783 Power Management IC is used that has audio and
touch functions integrated. So the i.MX27 module does not have to use the audio/touchscreen device
(U24) on the i.MX Carrier Board.
To select that the PMIC audio and touch should be used, there are a variety of jumpers which have to be
set.
A detailed list of all jumper settings you will find in Table 28 below.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
85
phyCOREi.MX27
Table 28:
JUMPER
Audio/Touchscreen interface jumper settings 1
SETTING
DESCRIPTION
JP21
2+3
1+2
x_MC1RIN is connected to X11
MIC1 is connected to X11
JP22
2+3
1+2
x_MC1LIN is connected to X11
MIC2 is connected to X11
JP19
2+3
1+2
x_RXOUTL is connected to X12
LINE_INR is connected to X12
JP20
2+3
1+2
x_RXOUTR is connected to X12
LINE_INL is connected to X12
JP23
2+3
1+2
x_RXINL is connected to X13
LINE_OUTR is connected to X13
JP24
2+3
1+2
x_RXINR is connected to X13
LINE_OUTL is connected to X13
JP25
2+3
1+2
x_TSY1 is connected to X23
TP_Y- is connected to X23
JP26
2+3
1+2
x_TSX2 is connected to X23
TP_X+ is connected to X23
JP27
2+3
1+2
x_TSY2 is connected to X23
TP_Y+ is connected to X23
JP28
2+3
1+2
X_TSX1 is connected to X23
TP_X- is connected to X23
JP47
open
closed
Reset is held high, no asserting by GPIO of i.MX module
Reset can be asserted by GPIO of i.MX module
JP48
open
closed
No access to IRQ via GPIO of i.MX module
Access to IRQ via GPIO of i.MX module
JP49
open
closed
No access to PENDOWN via GPIO of i.MX module
Access to PENDOWN via GPIO of i.MX module
Caution!
Jumper JP47 to JP49 always have to be opened with the phyCORE-i.MX27. Functions behind this
jumpers are not available for the i.MX27 module.
1
86
Settings for the phyCORE-i.MX27 audio/touchscreen interface are in bold blue
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
X17
Line I N
JP6
MI C
CAN
Line OUT
USB
USB Host
USB-OTG
14.3.7
1
GPI O
Suspend
Char ging
MAI N-LI -Cell
VCC CF
1
1
MATRI X KEYBOARD
JTAG
Boot Mode/ CLK-Sel.
PHYTEC
St andby
DMC
S/ N
PCM-970
COMPACT FLASH
VI N
SJC-Mode
3V3
At t ent ion see manual
5V
Reset
Power On
1-W
I RE
CAN- by
CAN-pwr
CAN-PLD
5V DC 3A
CHARGER
RS232 aut oshut down
SERI AL 1+2
J13
RS232 disable
JP43
JP46
JP42
JP45
JP44
P1
PL 1280.4
1
BACKUP-LI - Cell
LCD-SW
CAMERA
DI SPLAY
MMC-SD
VCC LCD
1
C
A
D
B
1
Figure 24: phyCORE-iMX Carrier Board USB-Host Interface
The i.MX27 controller supports control of input USB devices such as keyboard, mouse or USB key. To
realize a USB Host interface the i.MX27 USB Host Controller (USBH2) uses the USB Host Transceiver
(U26) of the i.MX Carrier Board.
For further details and jumper settings have a look at Table 29.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
87
phyCOREi.MX27
Table 29:
UBS Host interface jumper settings for i.MX27 module 1
JUMPER
SETTING
JP13
open
closed
USB Host transceiver U26 is disabled, USB Host is out of operation
USB Host transceiver U26 is active, USB Host is in operation
JP6
open
closed
Reset pin is held HIGH, no Reset asserted
Reset pin is connected to GPIO, Reset can be asserted
JP42
1+2
2+3
USB Host is managed on the i.MX baseboard
USB Host is managed on the i.MX module
JP43
1+2
2+3
open
closed
USB Host is managed on the i.MX baseboard
USB Host is managed on the i.MX module
USB Host is managed on the i.MX module
USB Host is managed on the i.MX baseboard
JP45
1+2
2+3
USB Host is managed on the i.MX baseboard
USB Host is managed on the i.MX module
JP46
1+2
2+3
USB Host is managed on the i.MX baseboard
USB Host is managed on the i.MX module
JP44
DESCRIPTION
Caution!
With the phyCORE-i.MX27 jumper JP6 and JP42 to JP46 always have to be set as described in the table
above. The alternative functions of this jumpers are not available for the i.MX27 module.
1
88
Settings for the phyCORE-i.MX27 USB-Host interface are in bold blue
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
LCD Connectors
Line I N
MI C
CAN
Line OUT
USB
USB-OTG
14.3.8
RS232 disable
RS232 aut oshut down
SERI AL 1+2
1-W
I RE
P1
1
CAN- by
CAN-pwr
VI N
GPI O
Suspend
Char ging
MAI N-LI -Cell
VCC CF
1
1
MATRI X KEYBOARD
JTAG
Boot Mode/ CLK-Sel.
PHYTEC
St andby
DMC
S/ N
PCM-970
COMPACT FLASH
3V3
Power On
SJC-Mode
5V
Reset
5V DC 3A
CHARGER
At t ent ion see manual
CAN-PLD
PL 1280.4
1
BACKUP-LI - Cell
LCD-SW
SW1
MMC-SD
VCC LCD
X23
CAMERA
DI SPLAY
X22
1
C
A
D
B
1
Figure 25: phyCORE-i.MX Carrier Board LCD Interfaces
The phyCORE-i.MX27 module comes with a 18-bit LCD interface. This 18-bit LCD interface is fully
connected to the molex connectors X1 of the i.MX27 module and can be used in the customers
application.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
89
phyCOREi.MX27
14.3.8.1
Serial LCD
Note:
Serial LCD is not supported by the phyCORE-i.MX27 module, because the i.MX27 microcontroller does
not provide Serial LCD.
90
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
Camera Interface
Line I N
MI C
CAN
Line OUT
USB
USB-OTG
14.3.9
RS232 disable
RS232 aut oshut down
SERI AL 1+2
1-W
I RE
P1
1
CAN- by
CAN-pwr
VI N
GPI O
Suspend
Char ging
MAI N-LI -Cell
VCC CF
1
1
MATRI X KEYBOARD
JTAG
Boot Mode/ CLK-Sel.
PHYTEC
St andby
DMC
S/ N
PCM-970
COMPACT FLASH
3V3
Power On
SJC-Mode
5V
Reset
5V DC 3A
CHARGER
At t ent ion see manual
CAN-PLD
PL 1280.4
1
BACKUP-LI - Cell
LCD-SW
MMC-SD
VCC LCD
DI SPLAY
JP16
JP15
CAMERA
JP3
1
C
A
D
B
1
X8
X7
Figure 26: phyCORE-i.MX Carrier Board Camera Interface
The camera interface can be managed by the signal x_CSI_ENABLE connected to X_PB24 of the i.MX27
module.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
91
phyCOREi.MX27
Table 30:
JUMPER
JP3
1
92
Camera interface jumper settings for i.MX27 module 1
SETTING
closed
open
DESCRIPTION
JP16
1+2
2+3
Outputs of level shifter U12 are enabled, CSI is active
Outputs of U12 are disabled or GPIO x_CSI_ENABLE (PB24 of i.MX27)
can be used to control U12
Jumper settings to chance camera sensor specific I²C address. For more
information refer to the manual of the used camera sensor.
JP15
1+2
2+3
Use of Camera Connector X7 with VCC_CAM supply (3.3V)
Use of Camera Connector X8 with external VCC_CAM_EXT supply
Default Settings for the phyCORE-i.MX35 Camera Interface are in bold blue
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
14.3.9.1
PHYTEC Camera Connector
Note:
i.MX27 only has an 8-bit camera interface so you need to have a Camera-Sensor with internal
multiplexer. When ordering a Phytec Camera-Sensor, please consider to order a sensor with ordering
option “MUX”.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
93
phyCOREi.MX27
JTAG Interface
Line I N
MI C
CAN
Line OUT
USB
USB-OTG
14.3.10
RS232 disable
RS232 aut oshut down
SERI AL 1+2
1-W
I RE
P1
1
CAN- by
CAN-pwr
VI N
JP12
GPI O
Suspend
Char ging
MAI N-LI -Cell
VCC CF
X6
1
1
MATRI X KEYBOARD
JTAG
Boot Mode/ CLK-Sel.
PHYTEC
St andby
DMC
S/ N
PCM-970
COMPACT FLASH
3V3
Power On
SJC-Mode
5V
Reset
5V DC 3A
CHARGER
At t ent ion see manual
CAN-PLD
PL 1280.4
1
BACKUP-LI - Cell
LCD-SW
CAMERA
DI SPLAY
MMC-SD
VCC LCD
1
C
A
D
B
1
Figure 27: phyCORE-iMX Carrier Board JTAG Interface
Two JTAG modes are provided by the phyCORE-i.MX27 module dependent on the status of the
JTAG_CTRL signal of the i.MX27 controller.
Jumper JP12 can be used to select the JTAG mode the controller should operate in.
94
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
Table 31:
JUMPER
JP12
1
JTAG jumper settings for phyCORE-i.MX27 module 1
SETTING
open
closed
DESCRIPTION
JTAG Controller is in ARM926 Platform mode
JTAG Controller is in i.MX27 JTAG Controller mode
Default Settings for the phyCORE-i.MX27 JTAG Interface are in bold blue
© PHYTEC Messtechnik GmbH 2009
L-710e_4
95
phyCOREi.MX27
14.3.11
Complete jumper setting list for phyCORE-i.MX27
on the i.MX Carrier Board
The following table contains all jumper settings that can be set on the phyCORE-i.MX Carrier Board. Also it
shows the default jumper settings for using the phyCORE-i.MX27 module with the i.MX Carrier Board. These
default jumper settings are normally done prior to delivery.
Table 32:
JUMPER
SETTING
JP1
open
closed
RS-232 transceivers are enabled
RS-232 transceivers are disabled
JP2
open
closed
RS-232 auto shutdown is disabled
RS-232 auto shutdown is enabled
JP3
open
closed
open
closed
open
closed
Camera interface is managed by x_CSI_ENABLE
Camera interface is always enabled
Compact Flash is in overwrite mode
Compact Flash is usable
Compact-Flash is Slave
Compact-Flash is Master
JP6
open
closed
USBH2 transceiver Reset is not controllable
USBH2 transceiver Reset is controllable via GPIO
JP7
1+2
2+3
1+2
2+3
CAN is managed on the Carrier Board
CAN is managed on the module
CAN signals is are on the level VCC_CAN (from mapper)
CAN signals is are on the level VCC_5V
JP9
1+2
2+3
CAN is supplied via on Board 5 V Power-Supply
CAN is supplied via an external Power-Supply
JP10
1+2
2+3
CAN is managed on the Carrier Board
CAN is managed on the module
JP11
1+2
2+3
CAN is supplied via on Board Power-Supply
CAN is supplied via an external Power-Supply
JP12
open
closed
open
closed
Only the System JTAG Controller
All core's TAPS in a single daisy chain
USB Host transceiver is disabled
USB Host transceiver is enabled
JP14
open
closed
VCC_FUSE = 2.775 V (no FUSE programming)
VCC_FUSE = 3,3V (use only for FUSE programming)
JP15
1+2
2+3
JP4
JP5
JP8
JP13
1
96
Jumper settings for i.MX27 module on i.MX Carrier Board 1
DESCRIPTION
Camera interface supplied via on-board 3.3 V supply
Camera interface is supplied via external supply
Default settings are in bold blue
© PHYTEC Messtechnik GmbH 2009
L-710e_4
The phyCORE-i.MX on the Carrier Board
JP16
1+2
2+3
JP17
open
closed
1+2
2+3
1+2
2+3
1+2
2+3
1+2
2+3
1+2
2+3
JP18
JP19
JP20
JP21
JP22
CMOS-Sensor I²C address is 0x55
CMOS-Sensor I²C Address is 0x33
Compact Flash expansion connector is enabled
Compact Flash expansion connector is disabled
MMC driver is disabled
MMC driver is enabled
Stereo output is managed on the baseboard
Stereo output is managed on the module
Stereo output is managed on the baseboard
Stereo output is managed on the module
Stereo MIC is managed on the baseboard
Stereo MIC is managed on the module
Stereo MIC is managed on the baseboard
Stereo MIC is managed on the module
JP23
1+2
2+3
Stereo LINE IN is managed on the baseboard
Stereo LINE IN is managed on the module
JP24
1+2
2+3
Stereo LINE IN is managed on the baseboard
Stereo LINE IN is managed on the module
JP25
1+2
2+3
Touch screen is managed on the baseboard
Touch screen is managed on the module
JP26
1+2
2+3
Touch screen is managed on the baseboard
Touch screen is managed on the module
JP27
1+2
2+3
Touch screen is managed on the baseboard
Touch screen is managed on the module
JP28
1+2
2+3
Touch screen is managed on the baseboard
Touch screen is managed on the module
JP29
1+2
2+3
1+2
3+4
5+6
1+3,2+4
3+5,4+6
Backup voltage is supplied by ext. LICELL
Backup voltage is supplied by onboard Goldcap
VCC_BOOT is deep-sleep test voltage
VCC_CLK is deep-sleep test voltage
VCC_JTAG is deep-sleep test voltage
Power source is Power Over Ethernet (POE)
Power source is 5 V adapter
JP32
1+3,2+4
3+5,4+6
No power switching, direct supply of VCC_3V3
Separate supply path
JP33
1+2,3+4
open,open
JP30
JP31
No power switching, direct supply from VCC_3V3
Separate supply path
© PHYTEC Messtechnik GmbH 2009
L-710e_4
97
phyCOREi.MX27
JP34
1+2,3+4
open,open
JP35
open
closed
VCC_5V Power Supply is enabled
VCC_5V Power Supply is disabled
JP36
open
closed
VCC_3V3 Power Supply is disabled
VCC_3V3 Power Supply is enabled
JP37
open
closed
Chargemode is Single Path
Chargemode is Dual Path
JP38
1+2,3+4
open,open
Power switching, supply from 5 V adapter or POE
No power switching, direct supply from VCC_3V3
JP39
1+2,3+4
open,open
open
closed
Power switching active, Battery charge path closed
No power switching, direct supply from VCC_3V3
No power switching active, minimum circuit
Power switching active
JP40
JP42
1+2
2+3
JP43
1+2
2+3
open
closed
JP44
USB VBUS power enable managed on baseboard
USB VBUS power enable managed on module
USB VBUS overcurrent managed on the baseboard
USB VBUS overcurrent managed on the module
USB Host is managed on the module
USB Host is managed on the baseboard
JP45
1+2
2+3
USB Host is managed on the baseboard
USB Host is managed on the module
JP46
1+2
2+3
USB Host is managed on the baseboard
USB Host is managed on the module
JP47
open
closed
Reset of audio/touch device is not controllable
Reset of audio/touch device is controllable via GPIO
JP48
open
closed
IRQ of audio/touch device is not controllable
IRQ of audio/touch device is controllable via GPIO
JP49
open
closed
open
closed
PENDOWN of audio/touch device is not controllable
PENDOWN of audio/touch device is controllable via GPIO
SD card write protect is not connected to the module
SD card write protect is connected to the module
JP602
open
closed
PC_RW inverted
PC_RW non-inverted
JP604
open
closed
CF power is manged by x_EXP007
Force enabling VCC_CFL
JP50
98
No power switching, direct supply from VCC_3V3
Separate supply path
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Revision History
15 Revision History
Date
Version numbers
Changes in this manual
30-June-2009
Manual L-710e_4
PCM-038
PCB# 1281.2
PCM-970
PCB# 1280.4
Preliminary documentation.
Describes the phyCORE-i.MX27 with
phyMAP-i.MX27 and i.MX Carrier Board.
© PHYTEC Messtechnik GmbH 2009
L-710e_4
99
phyCOREi.MX27
100
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Compoonent Placement Diagram
C140
C141
L5
TP6
TP5
C21
R78
RN17
QO1
D6
TP7
C107
R81
D7
TP8
R19
C29
R21
R25
TP15 TP16
R17
R12 R6 R53
R55
R7 R54
R8
C111
XT2
TP17
C109
C26
U18
C27
C135
C114
C112
C144
L4
C163
RN19
RN18
D5
C142
C152
R1
R4
R3
R14
RN16
U3
L3
RN30
C167
C145
C150
RN4
R13
R66
U14
RN8
RN6
R65
RN2
RN7
C16
R60
C24
C23
C151
RN1
RN5
J9
C110
RN29
C164
C171
C173
Q4
RN25
TP1
TP2
TP9
TP10
TP11
TP12
TP13
TP14
RN24
Q2
C99
R64 R63
R62 R61
C172
C134
C17
C149
RN26
16 Component Placement Diagram
C28
C143
RN23
RN22
RN21
RN20
C105
XT3
C146
RN3
U4
C81
D2
J21
U5
R11
C10 C11 R10
R37
R90
C175
R89
C102
U24
U19
C118
C115
RN14
RN12
C174
R72
C117 C116
R24
C96
RN15
RN13
RN31
C20 R9
RN32
C91
C162
C161
R41
R35
C108
U16
C85
U17
J1
U12
C104
R71
R48
JN2
RN28
Figure 28:
JN1
RN27
C97
C94
J13
J16
J15
U15
phyCORE-i.MX27 component placement (top view)
© PHYTEC Messtechnik GmbH 2009
L-710e_4
101
phyCOREi.MX27
C133
C157
C124 C131
C127
J12
L1
J18
J17
C123 C125
D8
R69
C25
R84
R83
R86
C121
C122
C1
C31
R88
R68
C15
C130 C129
C126
C159
J2
Q3
C153 C158
C156
C95
C89
C154
J5
J3
R39
C113
R58
Q5
X1
R44
C147
R40
C148
R45
Q1
J4 J7 J6
C128
D9
C155
C18
C160
R67
C166
R70
C165
C168
C136
C169
C93
X1
J11
J8
J10
C90
U22
C119
R20
R82
C50
R22
U9
C3
C92
R85
C132
L2
R38
U23
C2
C120
R15
C83
C42
C88
C48
U21
J22
R87
C49
C41
C43
C47
R23
R47
R80
C55
C73
C75
C64
C68 C7
C22
C13
C82
C65
C67
C9
C46
RN10
R56
R27
C37
C34
C40
C39
R57
C38
C98
RN11
C8
C72
C84
C69
C57
C45
R28
C5
C60
C52
C70
C63
C54
C78
C51
C14 C79
C59
C44
R79
C87
R29
TP4
C80
C76
C71
C66
C138 R32
R30
C56
C53
C36
C12
R34
R31
C61
R33
C58
R18
C137
RN9
R16
XT1
TP3
R5
C77
C33
U6
C74
D3
C35
U2
C139
U1
C170
R26
R43
U20
C106
R42
C32
C62
J20
C101
C4
C30
C19
R59
D4
D1
C6
U10
R46
C100
R49
U11
R36
R50
J14
C86
J19
C103
Figure 29: phyCORE-i.MX27 component placement (bottom view)
102
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Index
Index
1
N
10/100 Mbps Ethernet................. 46
NAND Flash...........................33, 37
B
O
Block Diagram ............................... 4
Operating Temperature ...............52
Operating Voltage........................52
C
COM Port .................................... 43
D
Debug Interface........................... 47
Dimensions.................................. 52
E
EEPROM............................... 33, 39
EEPROM Write Protection .......... 41
EMC .............................................. 1
Emulator ...................................... 49
F
Features ........................................ 3
H
Humidity ...................................... 52
I
I²C EEPROM ............................... 39
ISP1301....................................... 45
J
J603............................................. 41
JA-002 ......................................... 49
JTAG Interface ............................ 47
JTAG-Emulator Adapter.............. 49
© PHYTEC Messtechnik GmbH 2009
L-710e_4
P
phyCORE-connector .................7, 8
Physical Dimensions ...................51
Pin Description ..............................7
Pinout.............................................9
Power Consumption ....................52
R
RS-232 Interface .........................43
RS-232 Level...............................43
RS-232 Transceiver.....................43
RTC .............................................29
S
SDR SDRAM ...................33, 35, 36
SDRAM..................................35, 36
SMT Connector .............................7
Storage Temperature ..................52
System Configuration ..................31
System Memory...........................33
T
Technical Specifications ..............51
TTL Level.....................................43
U
U300 ............................................45
U301 ............................................43
U302 ............................................43
103
phyCOREi.MX27
U600............................................ 37
U601............................................ 39
U602...................................... 35, 36
U603...................................... 35, 36
UART3......................................... 43
UART5......................................... 43
USB Device ................................. 45
USB Host..................................... 45
USB On-The-Go.......................... 45
104
USB OTG ....................................45
USB Transceiver .........................45
W
Weight..........................................52
X
X201 ............................................47
© PHYTEC Messtechnik GmbH 2009
L-710e_4
Suggestions for Improvement
Document:
Document number:
phyCORE-i.MX27
L-710e_4, June 2009
How would you improve this manual?
Did you find any mistakes in this manual?
Submitted by:
Customer number:
Name:
Company:
Address:
Return to:
PHYTEC Technologie Holding AG
Postfach 100403
D-55135 Mainz, Germany
Fax : +49 (6131) 9221-33
© PHYTEC MesstechnikGmbH 2009
L-710e_4
page
Published by
© PHYTEC Messtechnik GmbH 2009
Ordering No. L-710e_4
Printed in Germany
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement