advertisement
MOTOROLA
M68000 FAMILY
Programmer’s Reference Manual
(Includes CPU32 Instructions)
MOTOROLA INC., 1992
TABLE OF CONTENTS
Paragraph
Number
Title
Page
Number
Section 1
Introduction
Integer Unit User Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Data Registers (D7 – D0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Address Registers (A7 – A0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Floating-Point Unit User Programming Model . . . . . . . . . . . . . . . . . . . . 1-4
Floating-Point Data Registers (FP7 – FP0) . . . . . . . . . . . . . . . . . . . . . 1-4
Floating-Point Control Register (FPCR) . . . . . . . . . . . . . . . . . . . . . . . 1-5
Exception Enable Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Mode Control Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Floating-Point Status Register (FPSR) . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Floating-Point Condition Code Byte. . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Quotient Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Exception Status Byte.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Accrued Exception Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Floating-Point Instruction Address Register (FPIAR) . . . . . . . . . . . . . 1-8
Supervisor Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Address Register 7 (A7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Vector Base Register (VBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Alternate Function Code Registers (SFC and DFC) . . . . . . . . . . . . . 1-11
Acu Status Register (MC68EC030 only) . . . . . . . . . . . . . . . . . . . . . . 1-11
Transparent Translation/access Control Registers . . . . . . . . . . . . . . 1-12
Transparent Translation/access Control Register Fields for the
Transparent Translation/access Control Register Fields for the
Floating-Point Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Packed Decimal Real Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Binary Floating-Point Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
Floating-Point Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Normalized Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Denormalized Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Not-A-Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Data Format and Type Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Organization of Data in Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
Organization of Integer Data Formats in Registers . . . . . . . . . . . . . . 1-25
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL iii
TABLE OF CONTENTS
(
Continued
)
Paragraph
Number
Title
Page
Number
Organization of Integer Data Formats in Memory . . . . . . . . . . . . . . . 1-27
Organization of Fpu Data Formats in Registers and Memory . . . . . . 1-30
Section 2
Addressing Capabilities
Effective Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Data Register Direct Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Address Register Direct Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Address Register Indirect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Address Register Indirect with Postincrement Mode. . . . . . . . . . . . . . 2-6
Address Register Indirect with Predecrement Mode . . . . . . . . . . . . . . 2-7
Address Register Indirect with Displacement Mode . . . . . . . . . . . . . . 2-8
Address Register Indirect with Index (8-Bit Displacement) Mode . . . . 2-9
Address Register Indirect with Index (Base Displacement) Mode. . . 2-10
Memory Indirect Postindexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Memory Indirect Preindexed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Program Counter Indirect with Displacement Mode . . . . . . . . . . . . . 2-13
Program Counter Indirect with Index (8-Bit Displacement) Mode . . . 2-14
Program Counter Indirect with Index (Base Displacement) Mode. . . 2-15
Program Counter Memory Indirect Postindexed Mode . . . . . . . . . . . 2-16
Program Counter Memory Indirect Preindexed Mode . . . . . . . . . . . . 2-17
Absolute Short Addressing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Absolute Long Addressing Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Effective Addressing Mode Summary . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Brief Extension Word Format Compatibility . . . . . . . . . . . . . . . . . . . . . 2-21
Full Extension Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
No Memory Indirect Action Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
Memory Indirect Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
Memory Indirect with Preindex. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25
Memory Indirect with Postindex. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
Memory Indirect with Index Suppressed.. . . . . . . . . . . . . . . . . . . . 2-27
Other Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
Section 3
Instruction Set Summary
Data Movement Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Integer Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
iv M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
TABLE OF CONTENTS
(
Continued
)
Paragraph
Number
Title
Page
Number
Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Binary-Coded Decimal Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Program Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
System Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Cache Control Instructions (MC68040) . . . . . . . . . . . . . . . . . . . . . . . 3-14
Multiprocessor Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
Memory Management Unit (MMU) Instructions. . . . . . . . . . . . . . . . . 3-15
Floating-Point Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Integer Unit Condition Code Computation . . . . . . . . . . . . . . . . . . . . . . 3-17
Using the Cas and Cas2 Instructions . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Using the Moves Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Nested Subroutine Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Pipeline Synchronization with the Nop Instruction. . . . . . . . . . . . . . . 3-21
Floating-Point Instruction Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Floating-Point Computational Accuracy . . . . . . . . . . . . . . . . . . . . . . . . 3-23
Intermediate Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
Rounding the Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
Floating-Point Postprocessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
Underflow, Round, Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
Conditional Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
Section 4
Integer Instructions
Section 5
Floating Point Instructions
Section 6
Supervisor (Privileged) Instructions
Section 7
CPU32 Instructions
Section 8
Instruction Format Summary
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL v
TABLE OF CONTENTS
(
Continued
)
Paragraph
Number
Title
Page
Number
Coprocessor ID Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Effective Address Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Register/Memory Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Source Specifier Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Destination Register Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Conditional Predicate Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Shift and Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Count Register Field. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2
Address/Data Field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Operation Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-4
Appendix A
Processor Instruction Summary
MC68000, MC68008, MC68010 Processors . . . . . . . . . . . . . . . . . . . . A-12
M68000, MC68008, and MC68010 Instruction Set . . . . . . . . . . . . . . A-12
MC68000, MC68008, and MC68010 Addressing Modes . . . . . . . . . A-16
MC68020 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
MC68020 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17
MC68020 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-20
MC68030 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21
MC68030 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21
MC68030 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-24
MC68040 Processors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25
MC68040 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-25
MC68040 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-29
MC68881/MC68882 Coprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . A-30
MC68881/MC68882 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . A-30
MC68881/MC68882 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . A-31
MC68851 Coprocessors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-31
MC68851 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-31
MC68851 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-31
Appendix B
Exception Processing Reference
Exception Vector Assignments for the M68000 Family . . . . . . . . . . . . . B-1
Exception Stack Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-3
Floating-Point Stack Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-10
vi M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
TABLE OF CONTENTS
(
Concluded
)
Paragraph
Number
Title
Page
Number
Appendix C
S-Record Output Format
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL vii
LIST OF FIGURES
Figure
Number
Title
Page
Number
1-1 M68000 Family User Programming Model....................................................... 1-2
1-2 M68000 Family Floating-Point Unit User Programming Model ........................ 1-4
1-9 MC68030 Transparent Translation/MC68EC030 Access
1-10 MC68040 and MC68LC040 Transparent Translation/MC68EC040
1-19 Organization of Integer Data Formats in Address Registers.......................... 1-26
1-18 Organization of Integer Data Formats in Data Registers ............................... 1-26
1-22 Organization of FPU Data Formats in Memory .............................................. 1-30
2-3 M68000 Family Brief Extension Word Formats.............................................. 2-21
B-1 MC68000 Group 1 and 2 Exception Stack Frame ...........................................B-3
B-2 MC68000 Bus or Address Error Exception Stack Frame.................................B-3
B-4 Throwaway Four-Word Stack Frame, Format $1.............................................B-3
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL ix
LIST OF FIGURES (Concluded)
Figure
Number
Title
Page
Number
B-6 MC68040 Floating-Point Post-Instruction Stack Frame, Format $3.................B-4
B-7 MC68EC040 and MC68LC040 Floating-Point Unimplemented
B-8 MC68040 Access Error Stack Frame, Format $7 ...........................................B-5
B-9 MC68010 Bus and Address Error Stack Frame, Format $8 ...........................B-6
B-10 MC68020 Bus and MC68030 Coprocessor Mid-Instruction
B-11 MC68020 and MC68030 Short Bus Cycle Stack Frame, Format $A ...............B-7
B-12 MC68020 and MC68030 Long Bus Cycle Stack Frame, Format $B...............B-8
B-13 CPU32 Bus Error for Prefetches and Operands Stack Frame, Format $C.....B-8
B-14 CPU32 Bus Error on MOVEM Operand Stack Frame, Format $C .................B-9
B-15 CPU32 Four- and Six-Word Bus Error Stack Frame, Format $C....................B-9
B-16 MC68881/MC68882 and MC68040 Null Stack Frame..................................B-10
B-22 MC68040 Unimplimented Instruction Stack Frame........................................B-12
x M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
LIST OF TABLES
Table
Number
Title
Page
Number
1-1 Supervisor Registers Not Related To Paged Memory Management .............. 1-9
1-2 Supervisor Registers Related To Paged Memory Management................... 1-10
1-4 Single-Precision Real Format Summary Data Format .................................. 1-21
1-5 Double-Precision Real Format Summary...................................................... 1-22
1-6 Extended-Precision Real Format Summary.................................................. 1-23
1-6 Extended-Precision Real Format Summary (Continued) .............................. 1-24
1-7 Packed Decimal Real Format Summary ....................................................... 1-24
1-8 MC68040 FPU Data Formats and Data Types ............................................. 1-30
2-4 Effective Addressing Modes and Categories ................................................ 2-20
3-8 Binary-Coded Decimal Operation Format ..................................................... 3-11
3-20 Operation Table Example (FADD Instruction)............................................... 3-22
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL xi
Table
Number
LIST OF TABLES (Continued)
Title
Page
Number
A-1 M68000 Family Instruction Set And Processor Cross-Reference................... A-1
A-3 MC68000 and MC68008 Instruction Set ....................................................... A-12
A-5 MC68000, MC68008, and MC68010 Data Addressing Modes ..................... A-16
B-1 Exception Vector Assignments for the M68000 Family................................... B-2
xii M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
SECTION 1
INTRODUCTION
This manual contains detailed information about software instructions used by the microprocessors and coprocessors in the M68000 family, including:
MC68000
MC68EC000
MC68HC000
MC68008
MC68010
MC68020
MC68EC020
MC68030
MC68EC030
MC68040
MC68LC040
MC68EC040
MC68330
MC68340
MC68851
— 16-/32-Bit Embedded Controller
— Low Power 16-/32-Bit Microprocessor
— 16-Bit Microprocessor with 8-Bit Data Bus
— 16-/32-Bit Virtual Memory Microprocessor
— 32-Bit Virtual Memory Microprocessor
— 32-Bit Embedded Controller
— Second-Generation 32-Bit Enhanced Microprocessor
— 32-Bit Embedded Controller
— Third-Generation 32-Bit Microprocessor
— Third-Generation 32-Bit Microprocessor
— 32-Bit Embedded Controller
— Integrated CPU32 Processor
—
—
Integrated Processor with DMA
Paged Memory Management Unit
MC68882 — Enhanced Floating-Point Coprocessor
NOTE
All references to the MC68000, MC68020, and MC68030 include the corresponding embedded controllers, MC68EC000,
MC68EC020, and MC68EC030. All references to the MC68040 include the MC68LC040 and MC68EC040. This referencing method applies throughout the manual unless otherwise specified.
The M68000 family programming model consists of two register groups: user and supervisor. User programs executing in the user mode only use the registers in the user group. System software executing in the supervisor mode can access all registers and uses the control registers in the supervisor group to perform supervisor functions. The following paragraphs provide a brief description of the registers in the user and supervisor models as well as the data organization in the registers.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-1
Introduction
1.1 INTEGER UNIT USER PROGRAMMING MODEL
Figure 1-1 illustrates the integer portion of the user programming model. It consists of the following registers:
• 16 General-Purpose 32-Bit Registers (D7 – D0, A7 – A0)
• 32-Bit Program Counter (PC)
• 8-Bit Condition Code Register (CCR)
.
31 15
31
31
31
15
15
15 7
0
0
0
A7
(USP)
0
PC
0
CCR
A0
A1
A2
A3
A4
A5
A6
D4
D5
D6
D7
D0
D1
D2
D3 DATA
REGISTERS
ADDRESS
REGISTERS
USER
STACK
POINTER
PROGRAM
COUNTER
CONDITION
CODE
REGISTER
Figure 1-1. M68000 Family User Programming Model
1.1.1 Data Registers (D7 – D0)
These registers are for bit and bit field (1 – 32 bits), byte (8 bits), word (16 bits), long-word
(32 bits), and quad-word (64 bits) operations. They also can be used as index registers.
1.1.2 Address Registers (A7 – A0)
These registers can be used as software stack pointers, index registers, or base address registers. The base address registers can be used for word and long-word operations.
Register A7 is used as a hardware stack pointer during stacking for subroutine calls and exception handling. In the user programming model, A7 refers to the user stack pointer
(USP).
1-2 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Introduction
1.1.3 Program Counter
The PC contains the address of the instruction currently executing. During instruction execution and exception processing, the processor automatically increments the contents or places a new value in the PC. For some addressing modes, the PC can be used as a pointer for PC relative addressing.
1.1.4 Condition Code Register
Consisting of five bits, the CCR, the status register’s lower byte, is the only portion of the status register (SR) available in the user mode. Many integer instructions affect the CCR, indicating the instruction’s result. Program and system control instructions also use certain combinations of these bits to control program and system flow. The condition codes meet two criteria: consistency across instructions, uses, and instances and meaningful results with no change unless it provides useful information.
Consistency across instructions means that all instructions that are special cases of more general instructions affect the condition codes in the same way. Consistency across uses means that conditional instructions test the condition codes similarly and provide the same results whether a compare, test, or move instruction sets the condition codes. Consistency across instances means that all instances of an instruction affect the condition codes in the same way.
The first four bits represent a condition of the result generated by an operation. The fifth bit or the extend bit (X-bit) is an operand for multiprecision computations. The carry bit (C-bit) and the X-bit are separate in the M68000 family to simplify programming techniques that use them (refer to Table 3-18 as an example). In the instruction set definitions, the CCR is illustrated as follows:
X N Z V C
X—Extend
Set to the value of the C-bit for arithmetic operations; otherwise not affected or set to a specified result.
N—Negative
Set if the most significant bit of the result is set; otherwise clear.
Z—Zero
Set if the result equals zero; otherwise clear.
V—Overflow
Set if an arithmetic overflow occurs implying that the result cannot be represented in the operand size; otherwise clear.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-3
Introduction
C—Carry
Set if a carry out of the most significant bit of the operand occurs for an addition, or if a borrow occurs in a subtraction; otherwise clear.
1.2 FLOATING-POINT UNIT USER PROGRAMMING MODEL
The following paragraphs describe the registers for the floating- point unit user programming model. Figure 1-2 illustrates the M68000 family user programming model’s floating-point portion for the MC68040 and the MC68881/MC68882 floating-point coprocessors. It contains the following registers:
• 8 Floating-Point Data Registers (FP7 – FP0)
• 16-Bit Floating-Point Control Register (FPCR)
• 32-Bit Floating-Point Status Register (FPSR)
• 32-Bit Floating-Point Instruction Address Register (FPIAR)
79 63 0
FP0
FP1
FP2
FP3
FP4
FP5
FP6
FP7
31
31
CONDITION
CODE
0
23
QUOTIENT
15
EXCEPTION
ENABLE
15
EXCEPTION
STATUS
7 0
MODE
CONTROL
7
ACCRUED
EXCEPTION
0
FPCR
FPSR
FPIAR
FLOATING-POINT
DATA REGISTERS
FLOATING-POINT
CONTROL
REGISTER
FLOATING-POINT
STATUS
REGISTER
FLOATING-POINT
INSTRUCTION
ADDRESS
REGISTER
Figure 1-2. M68000 Family Floating-Point Unit User Programming Model
1.2.1 Floating-Point Data Registers (FP7 – FP0)
These floating-point data registers are analogous to the integer data registers for the
M68000 family. They always contain extended- precision numbers. All external operands, despite the data format, are converted to extended-precision values before being used in any calculation or being stored in a floating-point data register. A reset or a null-restore operation sets FP7 – FP0 positive, nonsignaling not-a-numbers (NANs).
1-4 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Introduction
1.2.2 Floating-Point Control Register (FPCR)
The FPCR (see Figure 1-3) contains an exception enable (ENABLE) byte and a mode control (MODE) byte. The user can read or write to the FPCR. Motorola reserves bits 31 –
16 for future definition; these bits are always read as zero and are ignored during write operations. The reset function or a restore operation of the null state clears the FPCR. When cleared, this register provides the IEEE 754 Standard for Binary Floating-Point Arithmetic defaults.
1.2.2.1 EXCEPTION ENABLE BYTE. Each bit of the ENABLE byte (see Figure 1-3) corresponds to a floating-point exception class. The user can separately enable traps for each class of floating-point exceptions.
1.2.2.2 MODE CONTROL BYTE. MODE (see Figure 1-3) controls the user- selectable rounding modes and precisions. Zeros in this byte select the IEEE 754 standard defaults.
The rounding mode (RND) field specifies how inexact results are rounded, and the rounding precision (PREC) field selects the boundary for rounding the mantissa. Refer to Table 3-21 for encoding information. .
EXCEPTION ENABLE MODE CONTROL
15
BSUN
14 13 12 11
SNAN OPERR OVFL UNFL
10 9 8
DZ INEX2 INEX1
7
PREC
6 5
RND
4 3 2
0
1 0
Figure 1-3. Floating-Point Control Register
ROUNDING MODE
ROUNDING PRECISION
INEXACT DECIMAL INPUT
INEXACT OPERATION
DIVIDE BY ZERO
UNDERFLOW
OVERFLOW
OPERAND ERROR
SIGNALING NOT-A-NUMBER
BRANCH/SET ON UNORDERED
1.2.3 Floating-Point Status Register (FPSR)
The FPSR (see Figure 1-2) contains a floating-point condition code (FPCC) byte, a floatingpoint exception status (EXC) byte, a quotient byte, and a floating-point accrued exception
(AEXC) byte. The user can read or write to all the bits in the FPSR. Execution of most floating-point instructions modifies this register. The reset function or a restore operation of the null state clears the FPSR.
1.2.3.1 FLOATING-POINT CONDITION CODE BYTE. The FPCC byte, illustrated in
Figure 1-4, contains four condition code bits that set after completion of all arithmetic instructions involving the floating-point data registers. The move floating-point data register
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-5
Introduction to effective address, move multiple floating-point data register, and move system control register instructions do not affect the FPCC. .
31
0
28 27
N
26
Z
25
I
24
NAN
NOT-A-NUMBER OR UNORDERED
INFINITY
ZERO
NEGATIVE
Figure 1-4. FPSR Condition Code Byte
1.2.3.2 QUOTIENT BYTE. The quotient byte contains the seven least significant bits of the unsigned quotient as well as the sign of the entire quotient (see Figure 1-5). The quotient bits can be used in argument reduction for transcendentals and other functions. For example, seven bits are more than enough to figure out the quadrant of a circle in which an operand resides. The quotient bits remain set until the user clears them. .
23
S
22
QUOTIENT
16
SEVEN LEAST SIGNIFICANT
BITS OF QUOTIENT
SIGN OF QUOTIENT
Figure 1-5. FPSR Quotient Code Byte
1.2.3.3 EXCEPTION STATUS BYTE. The EXC byte, illustrated in Figure 1- 6, contains a bit for each floating-point exception that might have occurred during the most recent arithmetic instruction or move operation. This byte is cleared at the start of all operations that generate floating-point exceptions. Operations that do not generate floating-point exceptions do not clear this byte. An exception handler can use this byte to determine which floating-point exception(s) caused a trap. .
1-6
BRANCH/SET ON
UNORDERED
SIGNALING NOT-A-NUMBER
OPERAND ERROR
OVERFLOW
15
BSUN
14
SNAN
13
OPERR
12
OVFL
11
UNFL
10
DZ
9
INEX2
8
INEX1
Figure 1-6. FPSR Exception Status Byte
INEXACT DECIMAL
INPUT
INEXACT OPERATION
DIVIDE BY ZERO
UNDERFLOW
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Introduction
1.2.3.4 ACCRUED EXCEPTION BYTE. The AEXC byte contains five exception bits (see
Figure 1-7) required by the IEEE 754 standard for trap disabled operations. These exceptions are logical combinations of the bits in the EXC byte. The AEXC byte contains a history of all floating-point exceptions that have occurred since the user last cleared the
AEXC byte. In normal operations, only the user clears this byte by writing to the FPSR; however, a reset or a restore operation of the null state can also clear the AEXC byte.
Many users elect to disable traps for all or part of the floating- point exception classes. The
AEXC byte makes it unnecessary to poll the EXC byte after each floating-point instruction.
At the end of most operations (FMOVEM and FMOVE excluded), the bits in the EXC byte are logically combined to form an AEXC value that is logically ORed into the existing AEXC byte. This operation creates "sticky" floating- point exception bits in the AEXC byte that the user needs to poll only once—i.e., at the end of a series of floating-point operations.
.
7
IOP
6
OVFL
5
UNFL
4
DZ
3
INEX
2 1 0
INEXACT
DIVIDE BY ZERO
UNDERFLOW
OVERFLOW
INVALID OPERATION
Figure 1-7. FPSR Accrued Exception Byte
Setting or clearing the AEXC bits neither causes nor prevents an exception. The following equations show the comparative relationship between the EXC byte and AEXC byte.
Comparing the current value in the AEXC bit with a combination of bits in the EXC byte derives a new value in the corresponding AEXC bit. These equations apply to setting the
AEXC bits at the end of each operation affecting the AEXC byte:
IOP
New
AEXC Bit
OVFL
UNFL
DZ
INEX
= Old
AEXC Bit
= IOP
= OVFL
= UNFL
= DZ
= INEX
V
V
V
V
V
V
EXC Bits
(SNAN V OPERR)
(OVFL)
(UNFL L INEX2)
(DZ)
(INEX1 V INEX2 V OVFL)
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-7
Introduction
1.2.4 Floating-Point Instruction Address Register (FPIAR)
The integer unit can be executing instructions while the FPU is simultaneously executing a floating-point instruction. Additionally, the FPU can concurrently execute two floating-point instructions. Because of this nonsequential instruction execution, the PC value stacked by the FPU, in response to a floating-point exception trap, may not point to the offending instruction.
For the subset of the FPU instructions that generate exception traps, the 32-bit FPIAR is loaded with the logical address of the instruction before the processor executes it. The floating-point exception handler can use this address to locate the floating-point instruction that caused an exception. Since the FPU FMOVE to/from the FPCR, FPSR, or FPIAR and
FMOVEM instructions cannot generate floating- point exceptions, these instructions do not modify the FPIAR. A reset or a null-restore operation clears the FPIAR.
1.3 SUPERVISOR PROGRAMMING MODEL
System programers use the supervisor programming model to implement sensitive operating system functions—e.g., I/O control and memory management unit (MMU) subsystems. The following paragraphs briefly describe the registers in the supervisor programming model. They can only be accessed via privileged instructions. Table 1-1 lists the supervisor registers and the processors not related to paged memory management. For information concerning page memory management programming, refer to the devicespecific user’s manual. Table 1-2 lists the supervisor registers and the processors related to paged memory management.
1-8 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Introduction
Table 1-1. Supervisor Registers
Not Related To Paged Memory Management
Devices
Registers
AC1, AC0
ACUSR
CAAR
CACR
DACR1,
DACR0
DFC
DTT1, DTT0
IACR1,
IACR0
ITT1, ITT0
MSP
SFC
SR
SSP/ISP
TT1, TT0
VBR
68000
68008
68HC000
68HC001
68EC000 68010 x x x x x x x
68020
68EC020 CPU32 68030 68EC030 68040 68EC040 68LC040 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
AC1, AC0 = Access Control Registers
ACUSR = Access Control Unit Status Register
CAAR = Cache Address Register
CACR = Cache Control Register
DACR1, DACR0 = Data Access ControlRegisters
DFC = Destination Function Code Register
DTT1, DTT0 = Data Transparent Translation Registers
IACR1, IACR0 = Instruction Access Control Registers
ITT1, ITT0 = Instruction Transparent
Translation Registers
MSP = Master Stack Pointer Register
SFC = Source Function Code Register
SR = Status Register
SSP/ISP = Supervisor and Interrupt Stack Pointer
TT1, TT0 = Transparent Translation Registers
VBR = Vector Base Register
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-9
Introduction
Table 1-2. Supervisor Registers
Related To Paged Memory Management
Devices
68030 68040 68LC040 Registers
AC
CAL
CRP
DRP
PCSR
PMMUSR,
MMUSR
SCC
SRP
TC
URP
VAL
68851 x x x x x x x x x x x x x x x x x x x x x x
AC = Access Control Register
CAL = Current Access Level Register
CRP = CPU Root Pointer
DRP = DMA Root Pointer
PCSR = PMMU Control Register
PMMUSR = Paged Memory Management Unit Status Register
MMUSR = Memory Management Unit Status Register
SCC = Stack Change Control Register
SRP = Supervisor Root Pointer Register
TC = Translation Control Register
URP = User Root Pointer
VAL = Valid Access Level Register
1.3.1 Address Register 7 (A7)
In the supervisor programming model register, A7 refers to the interrupt stack pointer,
A7’(ISP) and the master stack pointer, A7" (MSP). The supervisor stack pointer is the active stack pointer (ISP or MSP). For processors that do not support ISP or MSP, the system stack is the system stack pointer (SSP). The ISP and MSP are general- purpose address registers for the supervisor mode. They can be used as software stack pointers, index registers, or base address registers. The ISP and MSP can be used for word and long-word operations.
1.3.2 Status Register
Figure 1-8 illustrates the SR, which stores the processor status and contains the condition codes that reflect the results of a previous operation. In the supervisor mode, software can access the full SR, including the interrupt priority mask and additional control bits. These bits indicate the following states for the processor: one of two trace modes (T1, T0), supervisor or user mode (S), and master or interrupt mode (M). For the MC68000, MC68EC000,
MC68008, MC68010, MC68HC000, MC68HC001, and CPU32, only one trace mode
1-10 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Introduction supported, where T0 is always zero, and only one system stack where the M-bit is always zero. I2, I1, and I0 define the interrupt mask level.
.
SYSTEM BYTE
USER BYTE
(CONDITION CODE REGISTER)
15 14 13 12 11 10
T1 T0 S M
9 8
0 I2 I1 I0
7
0
6 5
0 0 X
4 3 2 1
N Z V C
0
INTERRUPT
PRIORITY MASK
TRACE
ENABLE
SUPERVISOR/USER STATE
MASTER/INTERRUPT STATE
CARRY
OVERFLOW
ZERO
NEGATIVE
EXTEND
0
1
T1
0
1
T0
0
0
1
1
TRACE MODE
NO TRACE
TRACE ON ANY INSTRUCTION
TRACE ON CHANGE OF FLOW
UNDEFINED
S
0
1
1
Figure 1-8. Status Register
M x
0
1
ACTIVE STACK
USP
ISP
MSP
1.3.3 Vector Base Register (VBR)
The VBR contains the base address of the exception vector table in memory. The displacement of an exception vector adds to the value in this register, which accesses the vector table.
1.3.4 Alternate Function Code Registers (SFC and DFC)
The alternate function code registers contain 3-bit function codes. Function codes can be considered extensions of the 32-bit logical address that optionally provides as many as eight
4-Gbyte address spaces. The processor automatically generates function codes to select address spaces for data and programs at the user and supervisor modes. Certain instructions use SFC and DFC to specify the function codes for operations.
1.3.5 Acu Status Register (MC68EC030 only)
The access control unit status register (ACUSR) is a 16-bit register containing the status information returned by execution of the PTEST instruction. The PTEST instruction searches the access control (AC) registers to determine a match for a specified address. A match in either or both of the AC registers sets bit 6 in the ACUSR. All other bits in the
ACUSR are undefined and must not be used.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-11
Introduction
1.3.6 Transparent Translation/access Control Registers
Transparent translation is actually a misnomer since the whole address space transparently translates in an embedded control environment with no on-chip MMU present as well as in processors that have built-in MMUs. For processors that have built-in MMUs, such as the
MC68030, MC68040, and MC68LC040, the transparent translation (TT) registers define blocks of logical addresses that are transparently translated to corresponding physical addresses. These registers are independent of the on-chip MMU. For embedded controllers, such as the MC68EC030 and MC68EC040, the access control registers (AC) are similar in function to the TT registers but just named differently. The AC registers, main function are to define blocks of address space that control address space properties such as cachability. The following paragraphs describe these registers.
NOTE
For the paged MMU related supervisor registers, please refer to the appropriate user’s manual for specific programming detail.
1.3.6.1 TRANSPARENT TRANSLATION/ACCESS CONTROL REGISTER FIELDS FOR
THE M68030. Figure 1-9 illustrates the MC68030 transparent translation/MC68EC030 access control register format.
31 24 23 16
E
15
0
14
0
13
ADDRESS BASE
0 0
12 11
CI
10
R/W RWM
9 8
0
7 6
ADDRESS MASK
FC BASE 0
4 3 2
FC MASK
0
Figure 1-9. MC68030 Transparent Translation/MC68EC030 Access Control Register
Format
Address Base
This 8-bit field is compared with address bits A31 – A24. Addresses that match in this comparison (and are otherwise eligible) are transparently translated/access controlled.
Address Mask
This 8-bit field contains a mask for the address base field. Setting a bit in this field causes the corresponding bit of the address base field to be ignored. Blocks of memory larger than 16 Mbytes can be transparently translated/accessed controlled by setting some logical address mask bits to ones. The low-order bits of this field normally are set to define contiguous blocks larger than 16 Mbytes, although this is not required.
1-12 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Introduction
E—Enable
0 = Transparent translation/access control disabled
1 = Transparent translation/access control enabled
CI—Cache Inhibit
0 = Caching allowed
1 = Caching inhibited
R/W—Read/Write
0 = Only write accesses permitted
1 = Only read accesses permitted
R/WM—Read/Write Mask
0 = R/W field used
1 = R/W field ignored
FC BASE—Function Code Base
This 3-bit field defines the base function code for accesses to be transparently translated with this register. Addresses with function codes that match the FC BASE field (and are otherwise eligible) are transparently translated.
FC MASK—Function Code Mask
This 3-bit field contains a mask for the FC BASE field. Setting a bit in this field causes the corresponding bit of the FC BASE field to be ignored.
1.3.6.2 TRANSPARENT TRANSLATION/ACCESS CONTROL REGISTER FIELDS FOR
THE M68040. Figure 1-10 illustrates the MC68040 and MC68LC040 transparent translation/ MC68EC040 access control register format.
31 24 23 16
E
15
S FIELD
14 13
ADDRESS BASE
0 0
12 11
0
10
U1
9
U0
8
0
7 6
CM
5
ADDRESS MASK
0 0
4 3
W
2
0
1
0
0
Figure 1-10. MC68040 and MC68LC040 Transparent Translation/MC68EC040 Access
Control Register Format
Address Base
This 8-bit field is compared with address bits A31 – A24. Addresses that match in this comparison (and are otherwise eligible) are transparently translated/access controlled.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-13
Introduction
Address Mask
This 8-bit field contains a mask for the address base field. Setting a bit in this field causes the corresponding bit in the address base field to be ignored. Blocks of memory larger than 16 Mbytes can be transparently translated/access controlled by setting some logical address mask bits to ones. The low-order bits of this field normally are set to define contiguous blocks larger than 16 Mbytes, although this not required.
E—Enable
This bit enables and disables transparent translation/access control of the block defined by this register.
0 = Transparent translation/access control disabled
1 = Transparent translation/access control enabled
S—Supervisor/User Mode
This field specifies the use of the FC2 in matching an address.
00 = Match only if FC2 is 0 (user mode access)
01 = Match only if FC2 is 1 (supervisor mode access)
1X = Ignore FC2 when matching
U1, U2—User Page Attributes
The MC68040, MC68E040, MC68LC040 do not interpret these user-defined bits. If an external bus transfer results from the access, U0 and U1 are echoed to the UPA0 and
UPA1 signals, respectively.
CM—Cache Mode
This field selects the cache mode and access serialization for a page as follows:
00 = Cachable, Writethrough
01 = Cachable, Copyback
10 = Noncachable, Serialized
11 = Noncachable
W—Write Protect
This bit indicates if the block is write protected. If set, write and read-modify-write accesses are aborted as if the resident bit in a table descriptor were clear.
0 = Read and write accesses permitted
1 = Write accesses not permitted
1.4 INTEGER DATA FORMATS
The operand data formats supported by the integer unit, as listed in Table 1-3, include those supported by the MC68030 plus a new data format (16-byte block) for the MOVE16 instruction. Integer unit operands can reside in registers, memory, or instructions themselves. The operand size for each instruction is either explicitly encoded in the instruction or implicitly defined by the instruction operation.
1-14 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Introduction
Operand Data Format
Bit
Bit Field
Binary-Coded Decimal
(BCD)
Byte Integer
Word Integer
Long-Word Integer
Quad-Word Integer
16-Byte
Table 1-3. Integer Data Formats
Size Notes
1 Bit
1 – 32 Bits Field of Consecutive Bit
—
8 Bits Packed: 2 Digits/Byte; Unpacked: 1 Digit/Byte
8 Bits
16 Bits
—
—
32 Bits —
64 Bits Any Two Data Registers
128 Bits Memory Only, Aligned to 16- Byte Boundary
1.5 FLOATING-POINT DATA FORMATS
The following paragraphs describe the FPU’s operand data formats. The FPU supports seven data formats. There are three signed binary integer formats (byte, word, and long word) that are identical to those supported by the integer unit. The FPU supports the use of the packed decimal real format. The MC68881 and MC68882 support this format in hardware and the processors starting with the MC68040 support it in software.
The FPU also supports three binary floating- point formats (single, double, and extended precision) that fully comply with the IEEE 754 standard. All references in this manual to extendedprecision format imply the double-extended-precision format defined by the IEEE 754 standard.
1.5.1 Packed Decimal Real Format
Figure 1-11 illustrates the packed decimal real format which is three long words consisting of a 3-digit base 10 exponent and a 17-digit base 10 mantissa. The first two long words, digits 15 – 0, are 64 bits and map directly to bit positions 63 – 0 of the extended-precision real format. There are two separate sign bits, one for the exponent, the other for the mantissa. An extra exponent (EXP3) is defined for overflows that can occur when converting from the extended-precision real format to the packed decimal real format.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-15
Introduction
.
SIGN OF MANTISSA
SIGN OF EXPONENT
USED ONLY FOR ± INFINITY OR NANS
IMPLICIT DECIMAL POINT
96
SM SE Y Y
DIGIT 15
EXP 0
DIGIT 14
EXP 1 EXP 0
DIGIT 13 DIGIT 12
(EXP 3)
DIGIT 11
XXXX
DIGIT 10
XXXX
DIGIT 9
DIGIT 16
65
DIGIT 8
DIGIT 7
32
DIGIT 6 DIGIT 5 DIGIT 4 DIGIT 3 DIGIT 2 DIGIT 1 DIGIT 0
NOTE: XXXX indicates “don't care", which is zero when written and ignored when
read.
0
Figure 1-11. Packed Decimal Real Format
1.5.2 Binary Floating-Point Formats
Figure 1-12 illustrates the three binary floating-point data formats. The exponent in the three binary floating-point formats is an unsigned binary integer with an implied bias added to it.
When subtracting the bias from the exponent’s value, the result represents a signed twos complement power of two. This yields the magnitude of a normalized floating-point number when multiplied by the mantissa. A program can execute a CMP instruction that compares floating-point numbers in memory using biased exponents, despite the absolute magnitude of the exponents.
.
S
94
15-BIT
EXPONENT
80
ZERO
SIGN OF MANTISSA
63
S
62
11-BIT
EXPONENT
51
SIGN OF FRACTION
64-BIT
MANTISSA
EXPLICIT INTEGER PART BIT
S
30
8-BIT
EXPONENT
22
23-BIT
FRACTION
SIGN OF FRACTION
0
SINGLE REAL
0
52-BIT
FRACTION
DOUBLE REAL
0
EXTENDED REAL
Figure 1-12. Binary Floating-Point Data Formats
Data formats for single- and double-precision numbers differ slightly from those for extended-precision numbers in the representation of the mantissa. For all three precisions, a normalized mantissa is always in the range (1.0...2.0). The extended-precision data format represents the entire mantissa, including the explicit integer part bit. Single- and doubleprecision data formats represent only a fractional portion of the mantissa (the fraction) and always imply the integer part as one.
1-16 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Introduction
The IEEE 754 standard has created the term significand to bridge the difference between mantissa and fraction and to avoid the historical implications of the term mantissa. The IEEE
754 standard defines a significand as the component of a binary floating-point number that includes an explicit or implicit leading bit to the left of the implied binary point. However, this manual uses the term mantissa for extended-precision formats and fraction for single- and double- precision formats instead of the IEEE term significand.
NOTE
This section specifies ranges using traditional set notation with the format "bound...bound" specifying the boundaries of the range. The bracket types enclosing the range define whether the endpoint is inclusive or exclusive. A square bracket indicates inclusive, and a parenthesis indicates exclusive. For example, the range specification "[1.0...2.0]" defines the range of numbers greater than or equal to 1.0 and less than or equal to 2.0. The range specification "(0.0... + inf)" defines the range of numbers greater than 0.0 and less than positive infinity, but not equal to.
1.6 FLOATING-POINT DATA TYPES
Each floating-point data format supports five, unique, floating-point data types: 1) normalized numbers, 2) denormalized numbers, 3) zeros, 4) infinities, and 5) NANs.
Exponent values in each format represent these special data types. The normalized data type never uses the maximum or minimum exponent value for a given format, except the extended-precision format. The packed decimal real data format does not support denormalized numbers.
There is a subtle difference between the definition of an extended- precision number with an exponent equal to zero and a single- or double-precision number with an exponent equal to zero. The zero exponent of a single- or double-precision number denormalizes the number’s definition, and the implied integer bit is zero. An extended- precision number with an exponent of zero may have an explicit integer bit equal to one. This results in a normalized number, though the exponent is equal to the minimum value. For simplicity, the following discussion treats all three floating-point formats in the same manner, where an exponent value of zero identifies a denormalized number. However, remember the extended-precision format can deviate from this rule.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-17
Introduction
1.6.1 Normalized Numbers
Normalized numbers encompass all numbers with exponents laying between the maximum and minimum values. Normalized numbers can be positive or negative. For normalized numbers in single and double precision the implied integer bit is one. In extended precision, the mantissa’s MSB, the explicit integer bit, can only be a one (see Figure 1-13); and the exponent can be zero.
.
MIN < EXPONENT < MAX
SIGN OF MANTISSA, 0 OR 1
MANTISSA = ANY BIT PATTERN
Figure 1-13. Normalized Number Format
1.6.2 Denormalized Numbers
Denormalized numbers represent real values near the underflow threshold. The detection of the underflow for a given data format and operation occurs when the result’s exponent is less than or equal to the minimum exponent value. Denormalized numbers can be positive or negative. For denormalized numbers in single and double precision the implied integer bit is a zero. In extended precision, the mantissa’s MSB, the explicit integer bit, can only be a zero (see Figure 1-14).
.
EXPONENT = 0 MANTISSA = ANY NONZERO BIT PATTERN
SIGN OF MANTISSA, 0 OR 1
Figure 1-14. Denormalized Number Format
Traditionally, the detection of underflow causes floating-point number systems to perform a
"flush-to-zero". This leaves a large gap in the number line between the smallest magnitude normalized number and zero. The IEEE 754 standard implements gradual underflows: the result mantissa is shifted right (denormalized) while the result exponent is incremented until reaching the minimum value. If all the mantissa bits of the result are shifted off to the right during this denormalization, the result becomes zero. Usually a gradual underflow limits the potential underflow damage to no more than a round-off error. This underflow and denormalization description ignores the effects of rounding and the user-selectable rounding modes. Thus, the large gap in the number line created by "flush-to-zero" number systems is filled with representable (denormalized) numbers in the IEEE "gradual underflow" floating-point number system.
Since the extended-precision data format has an explicit integer bit, a number can be formatted with a nonzero exponent, less than the maximum value, and a zero integer bit.
The IEEE 754 standard does not define a zero integer bit. Such a number is an unnormalized number. Hardware does not directly support denormalized and unnormalized numbers, but implicitly supports them by trapping them as unimplemented data types, allowing efficient conversion in software.
1-18 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Introduction
1.6.3 Zeros
Zeros can be positive or negative and represent the real values + 0.0 and – 0.0 (see Figure
1-15).
.
EXPONENT = 0
SIGN OF MANTISSA, 0 OR 1
MANTISSA = 0
Figure 1-15. Zero Format
1.6.4 Infinities
Infinities can be positive or negative and represent real values that exceed the overflow threshold. A result’s exponent greater than or equal to the maximum exponent value indicates the overflow for a given data format and operation. This overflow description ignores the effects of rounding and the user-selectable rounding models. For single- and double-precision infinities the fraction is a zero. For extended-precision infinities, the mantissa’s MSB, the explicit integer bit, can be either one or zero (see Figure 1-16).
.
EXPONENT = MAXIMUM
SIGN OF MANTISSA, 0 OR 1
MANTISSA = 0
Figure 1-16. Infinity Format
1.6.5 Not-A-Numbers
When created by the FPU, NANs represent the results of operations having no mathematical interpretation, such as infinity divided by infinity. All operations involving a
NAN operand as an input return a NAN result. When created by the user, NANs can protect against unitialized variables and arrays or represent user-defined data types. For extendedprecision NANs, the mantissa’s MSB, the explicit integer bit, can be either one or zero (see
Figure 1-17).
.
EXPONENT = MAXIMUM
SIGN OF MANTISSA, 0 OR 1
MANTISSA = ANY NONZERO BIT PATTERN
Figure 1-17. Not-A-Number Format
The FPU implements two different types of NANs identified by the value of the MSB of the mantissa for single- and double-precision, and the MSB of the mantissa minus one for extended-precision. If the bit is set, it is a nonsignaling NAN, otherwise, it is an SNAN. An
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-19
Introduction
SNAN can be used as an escape mechanism for a user-defined, non-IEEE data type. The
FPU never creates an SNAN resulting from an operation.
The IEEE specification defines NAN processing used as an input to an operation. A nonsignaling NAN must be returned when using an SNAN as an input and there is a disabled SNAN trap. The FPU does this by using the source SNAN, setting the MSB of the mantissa, and storing the resulting nonsignaling NAN in the destination. Because of the
IEEE formats for NANs, the result of setting an SNAN MSB is always a nonsignaling NAN.
When the FPU creates a NAN, the NAN always contains the same bit pattern in the mantissa. All bits of the mantissa are ones for any precision. When the user creates a NAN, any nonzero bit pattern can be stored in the mantissa.
1.6.6 Data Format and Type Summary
Tables 1-4 through 1-6 summarize the data type specifications for single-, double-, and extended-precision data formats. Packed decimal real formats support all data types except denormalized numbers. Table 1-7 summarizes the data types for the packed decimal real format.
1-20 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Table 1-4. Single-Precision Real Format Summary Data Format
Data Format
31 30 s e
23 22 f
0
Field Size In Bits
Sign (s)
Biased Exponent (e)
Fraction (f)
Total
Interpretation of Sign
Positive Fraction
Negative Fraction
Normalized Numbers
Bias of Biased Exponent
Range of Biased Exponent
Range of Fraction
Fraction
Relation to Representation of Real Numbers
Denormalized Numbers
Biased Exponent Format Minimum
Bias of Biased Exponent
Range of Fraction
Fraction
Relation to Representation of Real Numbers
Signed Zeros
Biased Exponent Format Minimum
Fraction
Signed Infinities
Biased Exponent Format Maximum
Fraction
NANs
Sign
Biased Exponent Format Maximum
Fraction
Representation of Fraction
Nonsignaling
Signaling
Nonzero Bit Pattern Created by User
Fraction When Created by FPCP
Approximate Ranges
Maximum Positive Normalized
Minimum Positive Normalized
Minimum Positive Denormalized
1
8
23
32 s = 0 s = 1
+127 ($7F)
0 < e < 255 ($FF)
Zero or Nonzero
1.f
(–1) s ×
2 e–127 ×
1.f
0 ($00)
+126 ($7E)
Nonzero
0.f
(–1) s ×
2–
126 ×
0.f
0 ($00)
0.f = 0.0
255 ($FF)
0.f = 0.0
Don’t Care
255 ($FF)
Nonzero
0.1xxxx…xxxx
0.0xxxx…xxxx xxxxx…xxxx
11111…1111
3.4
×
10
38
1.2
×
10–
38
1.4
×
10–
45
Introduction
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-21
Introduction
Table 1-5. Double-Precision Real Format Summary
Data Format
63 62 s e
52 51 f
Field Size (in Bits)
Sign (s)
Biased Exponent (e)
Fraction (f)
Total
Interpretation of Sign
Positive Fraction
Negative Fraction
Normalized Numbers
Bias of Biased Exponent
Range of Biased Exponent
Range of Fraction
Fraction
Relation to Representation of Real Numbers
Denormalized Numbers
Biased Exponent Format Minimum
Bias of Biased Exponent
Range of Fraction
Fraction
Relation to Representation of Real Numbers
Signed Zeros
Biased Exponent Format Minimum
Fraction (Mantissa/Significand)
Signed Infinities
Biased Exponent Format Maximum
Fraction
NANs
Sign
Biased Exponent Format Maximum
Fraction
Representation of Fraction
Nonsignaling
Signaling
Nonzero Bit Pattern Created by User
Fraction When Created by FPCP
Approximate Ranges
Maximum Positive Normalized
Minimum Positive Normalized
Minimum Positive Denormalized
0
1
11
52
64 s = 0 s = 1
+1023 ($3FF)
0 < e < 2047 ($7FF)
Zero or Nonzero
1.f
(–1) s ×
2 e–1023 ×
1.f
0 ($000)
+1022 ($3FE)
Nonzero
0.f
(–1) s × 2–
1022 × 0.f
0 ($00)
0.f = 0.0
2047 ($7FF)
0.f = 0.0
0 or 1
255 ($7FF)
Nonzero
1xxxx…xxxx
0xxxx…xxxx xxxxx…xxxx
11111…1111
18 x 10
308
2.2 x 10–
308
4.9 x 10–
324
1-22 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Table 1-6. Extended-Precision Real Format Summary
Data Format
95 94 s e
80 79 z
64 63 62 i f
0
Field Size (in Bits)
Sign (s)
Biased Exponent (e)
Zero, Reserved (u)
Explicit Integer Bit (j)
Mantissa (f)
Total
1
63
96
1
15
16
Interpretation of Unused Bits
Input
Output
Interpretation of Sign
Positive Mantissa
Negative Mantissa
Normalized Numbers
Bias of Biased Exponent
Range of Biased Exponent
Explicit Integer Bit
Range of Mantissa
Mantissa (Explicit Integer Bit and Fraction )
Relation to Representation of Real Numbers
Don’t Care
All Zeros s = 0 s = 1
+16383 ($3FFF)
0 < = e < 32767 ($7FFF)
1
Zero or Nonzero
1.f
(–1) s × 2 e–16383 × 1.f
Denormalized Numbers
Biased Exponent Format Minimum
Bias of Biased Exponent
Explicit Integer Bit
0 ($0000)
+16383 ($3FFF)
0
Range of Mantissa
Mantissa (Explicit Integer Bit and Fraction )
Relation to Representation of Real Numbers
Nonzero
0.f
(–1) s ×
2–
16383 ×
0.f
Signed Zeros
Biased Exponent Format Minimum
Mantissa (Explicit Integer Bit and Fraction )
0 ($0000)
0.0
Signed Infinities
Biased Exponent Format Maximum
Explicit Integer Bit
Mantissa (Explicit Integer Bit and Fraction )
32767 ($7FFF)
Don’t Care x.000…0000
Introduction
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-23
Introduction
Table 1-6. Extended-Precision Real
Format Summary (Continued)
NANs
Explicit Integer Bit
Biased Exponent Format Maximum
Mantissa
Representation of Fraction
Nonsignaling
Signaling
Nonzero Bit Pattern Created by User
Fraction When Created by FPCP
Approximate Ranges
Maximum Positive Normalized
Minimum Positive Normalized
Minimum Positive Denormalized
Don’t Care
32767 ($7FFF)
Nonzero x.1xxxx…xxxx x.0xxxx…xxxx x.xxxxx…xxxx
1.11111…1111
1.2
×
10
4932
1.7
×
10
–4932
3.7
×
10
4951
Table 1-7. Packed Decimal Real Format Summary
Data Type SM SE Y
±
Infinity
±
NAN
±
SNAN
0/1
0/1
0/1
1
1
1
1
1
1
+Zero 0 0/1 X
–Zero
+In-Range
–In-Range
1
0
1
0/1
0/1
0/1
X
X
X
X
X
1
X
X
Y
1
1
3-Digit
Exponent
$FFF
$FFF
$FFF
$000–$999
$000–$999
$000–$999
$000–$999
1-Digit
Integer
$XXXX
$XXXX
$XXXX
$XXX0
$XXX0
$XXX0–$XXX9
$XXX0–$XXX9
16-Digit Fraction
$00…00
Nonzero
Nonzero
$00…00
$00…00
$00…01–$99…99
$00…01–$99…99
A packed decimal real data format with the SE and both Y bits set, an exponent of $FFF, and a nonzero 16-bit decimal fraction is a NAN. When the FPU uses this format, the fraction of the NAN is moved bit- by-bit into the extended-precision mantissa of a floating-point data register. The exponent of the register is set to signify a NAN, and no conversion occurs. The
MSB of the most significant digit in the decimal fraction (the MSB of digit 15) is a don’t care, as in extended-precision NANs, and the MSB of minus one of digit 15 is the SNAN bit. If the
NAN bit is a zero, then it is an SNAN.
If a non-decimal digit ($A – $F) appears in the exponent of a zero, the number is a true zero.
The FPU does not detect non-decimal digits in the exponent, integer, or fraction digits of an in-range packed decimal real data format. These non-decimal digits are converted to binary in the same manner as decimal digits; however, the result is probably useless although it is repeatable. Since an in-range number cannot overflow or underflow when converted to extended precision, conversion from the packed decimal real data format always produces normalized extended-precision numbers.
1-24 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Introduction
1.7 ORGANIZATION OF DATA IN REGISTERS
The following paragraphs describe data organization within the data, address, and control registers.
1.7.1 Organization of Integer Data Formats in Registers
Each integer data register is 32 bits wide. Byte and word operands occupy the lower 8- and
16-bit portions of integer data registers, respectively. Long- word operands occupy the entire
32 bits of integer data registers. A data register that is either a source or destination operand only uses or changes the appropriate lower 8 or 16 bits (in byte or word operations, respectively). The remaining high-order portion does not change and goes unused. The address of the least significant bit (LSB) of a long-word integer is zero, and the MSB is 31.
For bit fields, the address of the MSB is zero, and the LSB is the width of the register minus one (the offset). If the width of the register plus the offset is greater than 32, the bit field wraps around within the register. Figure 1-18 illustrates the organization of various data formats in the data registers.
An example of a quad word is the product of a 32-bit multiply or the quotient of a 32-bit divide operation (signed and unsigned). Quad words may be organized in any two integer data registers without restrictions on order or pairing. There are no explicit instructions for the management of this data format, although the MOVEM instruction can be used to move a quad word into or out of registers.
Binary-coded decimal (BCD) data represents decimal numbers in binary form. Although there are many BCD codes, the BCD instructions of the M68000 family support two formats, packed and unpacked. In these formats, the LSBs consist of a binary number having the numeric value of the corresponding decimal number. In the unpacked BCD format, a byte defines one decimal number that has four LSBs containing the binary value and four undefined MSBs. Each byte of the packed BCD format contains two decimal numbers; the least significant four bits contain the least significant decimal number and the most significant four bits contain the most significant decimal number.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-25
Introduction
.
31
MSB
31
31
31
MSB
63
MSB
31
31
31
31
30
OFFSET
NOT USED
NOT USED
15
MSB
LONG WORD
7
MSB
LOW-ORDER WORD
1 0
LSB
< 31,OFFSET OF 0 = MSB)
0
LSB BYTE
0
LSB 16-BIT WORD
0
LSB LONG WORD
32
ANY DX
ANY DY
WIDTH*
8 7 4
UNDEFINED
8 7
MOST SIGNIFICANT DIGIT
4
3
LEAST SIGNIFICANT DIGIT
0
3
LEAST SIGNIFICANT DIGIT
0
0
LSB
0
QUAD WORD
BIT FIELD (0 < OFFSET < 32,
0 < WIDTH 32)
UNPACKED BCD
PACKED BCD
* IF WIDTH + OFFSET > 32, BIT FIELD WRAPS AROUND WITHIN THE REGISTER.
Figure 1-18. Organization of Integer Data Formats in Data Registers
Because address registers and stack pointers are 32 bits wide, address registers cannot be used for byte-size operands. When an address register is a source operand, either the loworder word or the entire long-word operand is used, depending upon the operation size.
When an address register is the destination operand, the entire register becomes affected, despite the operation size. If the source operand is a word size, it is sign-extended to 32 bits and then used in the operation to an address register destination. Address registers are primarily for addresses and address computation support. The instruction set includes instructions that add to, compare, and move the contents of address registers. Figure 1-19 illustrates the organization of addresses in address registers.
31 16 15 0
SIGN-EXTENDED 16-BIT ADDRESS OPERAND
31
FULL 32-BIT ADDRESS OPERAND
Figure 1-19. Organization of Integer Data Formats in Address Registers
0
1-26 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Introduction
Control registers vary in size according to function. Some control registers have undefined bits reserved for future definition by Motorola. Those particular bits read as zeros and must be written as zeros for future compatibility.
All operations to the SR and CCR are word-size operations. For all CCR operations, the upper byte is read as all zeros and is ignored when written, despite privilege mode. The alternate function code registers, supervisor function code (SFC) and data function code
(DFC), are 32-bit registers with only bits 0P2 implemented. These bits contain the address space values for the read or write operands of MOVES, PFLUSH, and PTEST instructions.
Values transfer to and from the SFC and DFC by using the MOVEC instruction. These are long-word transfers; the upper 29 bits are read as zeros and are ignored when written.
1.7.2 Organization of Integer Data Formats in Memory
The byte-addressable organization of memory allows lower addresses to correspond to higher order bytes. The address N of a long-word data item corresponds to the address of the highest order wordUs MSB. The lower order word is located at address N + 2, leaving the LSB at address N + 3 (see Figure 1-20). Organization of data formats in memory is consistent with the M68000 family data organization. The lowest address (nearest
$00000000) is the location of the MSB, with each successive LSB located at the next address (N + 1, N + 2, etc.). The highest address (nearest $FFFFFFFF) is the location of the
LSB.
.
31 23 15
LONG WORD $00000000
7
WORD $00000000
BYTE $00000000
WORD $00000002
BYTE $00000001 BYTE $00000002
LONG WORD $00000004
BYTE $00000003
WORD $00000004
BYTE $00000004 BYTE $00000005
WORD $00000006
BYTE $00000006 BYTE $00000007
0
LONG WORD $FFFFFFFC
WORD $FFFFFFFC
BYTE $FFFFFFFC BYTE $FFFFFFFD
WORD $FFFFFFFE
BYTE $FFFFFFFE BYTE $FFFFFFFF
Figure 1-20. Memory Operand Addressing
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-27
Introduction
Figure 1-21 illustrates the organization of IU data formats in memory. A base address that selects one byte in memory, the base byte, specifies a bit number that selects one bit, the bit operand, in the base byte. The MSB of the byte is seven.
The following conditions specify a bit field operand:
1. A base address that selects one byte in memory.
2. A bit field offset that shows the leftmost (base) bit of the bit field in relation to the
MSB of the base byte.
3. A bit field width that determines how many bits to the right of the base bit are in the bit field.
The MSB of the base byte is bit field offset 0; the LSB of the base byte is bit field offset 7; and the LSB of the previous byte in memory is bit field offset – 1. Bit field offsets may have values between 2 – 31 to 231 – 1, and bit field widths may range from 1 to 32 bits.
A 16-byte block operand, supported by the MOVE16 instruction, has a block of 16 bytes, aligned to a 16-byte boundary. An address that can point to any byte in the block specifies this operand.
1-28 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Introduction
.
7
BYTE n – 1
0 7
7
BYTE n – 1
ADDRESS
0 7
7
BYTE n – 1
0 7
7
BYTE n – 1
0 7 0 7
7 6 5 4 3 2 1 0 BYTE n + 1
0 7
BYTE n + 2
0
BIT DATA
7
7
BYTE n – 1
ADDRESS BIT
NUMBER
0 7
BYTE n
0 7
OFFSET
. . . – 3 – 2 – 1 0 1 2 . . .
BASE ADDRESS
OFFSET
0 7 0 7
BYTE n – 1 MSB BYTE n LSB
BASE BIT
0 7
0 1 2 3 . . . .
w – 1
WIDTH
0
BIT FIELD
DATA
BYTE n + 1
0 7
BYTE n + 2
0
BYTE DATA
ADDRESS
0 7
WORD INTEGER
0 7
BYTE n + 2
0 7
BYTE n + 3
0
WORD DATA
ADDRESS
0 7 0 7
LONG-WORD INTEGER
0 7 0 7
BYTE n + 4
0
LONG-WORD
DATA
0 7 0 7
QUAD-WORD INTEGER
0 7 0 7
BYTE n + 8
0
QUAD-WORD
DATA
7
BYTE n – 1
0 7 0 7 0 7
16-BYTE BLOCK
(ALIGNED TO
16-BYTE
BOUNDARY)
0 7 0 7 0
16-BYTE BLOCK
BYTE n + 16
7
7
BYTE n – 1
0 7
MSD
4 3
LSD
0 7
BYTE n + 1
0 7
BYTE n + 2
0
PACKED
BCD
DATA
ADDRESS
BYTE n – 1
0 7
XX
4 3
MSD
0 7
XX
4 3
LSD
0 7
BYTE n + 2
0
UNPACKED
BCD
DATA
ADDRESS
Figure 1-21. Memory Organization for Integer Operands
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 1-29
Introduction
1.7.3 Organization of Fpu Data Formats in Registers and Memory
The eight, 80-bit floating-point data registers are analogous to the integer data registers and are completely general purpose (i.e., any instruction may use any register). The MC68040 supports only some data formats and types in hardware. Table 1-8 lists the data formats supported by the MC68040.
Number
Types
Normalized
Zero
Infinity
NAN
Denormalized
Unnormalized
Table 1-8. MC68040 FPU Data Formats and Data Types
Single-
Precision
Real
∗
∗
∗
∗
†
Double-
Precision
Real
∗
∗
∗
∗
†
Extended-
Precision
Real
∗
∗
∗
∗
†
†
Data Formats
Packed-
Decimal
Real
†
†
†
†
†
†
Byte
Integer
∗
∗
Word
Integer
∗
∗
Long-
Word
Integer
∗
∗
NOTES:
*
=
Data Format/Type Supported by On-Chip MC68040 FPU Hardware
† = Data Format/Type Supported by Software (MC68040FPSP)
Figure 1-22 illustrates the floating-point data format for the single- , double-, and extendedprecision binary real data organization in memory.
.
7
BYTEn -1
0 7 0 7 0 7
SINGLE-PRECISION REAL
0 7 0 7
BYTEn +4
0
7
BYTEn -1
ADDRESS
0 7 0 7 0 7
DOUBLE-PRECISION REAL
0 7 0 7 0
BYTEn +8
7
BYTEn -1
ADDRESS
0 7 0 7 0 7 0 7 0 7
EXTENDED-PRECISION REAL
BYTEn +12
Figure 1-22. Organization of FPU Data Formats in Memory
0
1-30 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
SECTION 2
ADDRESSING CAPABILITIES
Most operations take asource operand and destination operand, compute them, and store the result in the destination location. Single-operand operations take a destination operand, compute it, and store the result in the destination location. External microprocessor references to memory are either program references that refer to program space or data references that refer to data space. They access either instruction words or operands (data items) for an instruction. Program space is the section of memory that contains the program instructions and any immediate data operands residing in the instruction stream. Data space is the section of memory that contains the program data. Data items in the instruction stream can be accessed with the program counter relative addressing modes; these accesses classify as program references.
2.1 INSTRUCTION FORMAT
M68000 family instructions consist of at least one word; some have as many as 11 words.
Figure 2-1 illustrates the general composition of an instruction. The first word of the instruction, called the simple effective address operation word, specifies the length of the instruction, the effective addressing mode, and the operation to be performed. The remaining words, called brief and full extension words, further specify the instruction and operands. These words can be floating-point command words, conditional predicates, immediate operands, extensions to the effective addressing mode specified in the simple effective address operation word, branch displacements, bit number or bit field specifications, special register specifications, trap operands, pack/unpack constants, or argument counts.
15 0
SINGLE EFFECTIVE ADDRESS OPERATION WORD
(ONE WORD, SPECIFIES OPERATION AND MODES)
SPECIAL OPERAND SPECIFIERS
(IF ANY, ONE OR TWO WORDS)
IMMEDIATE OPERAND OR SOURCE EFFECTIVE ADDRESS EXTENSION
(IF ANY, ONE TO SIX WORDS)
DESTINATION EFFECTIVE ADDRESS EXTENSION
(IF ANY, ONE TO SIX WORDS)
Figure 2-1. Instruction Word General Format
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 2-1
Addressing Capabilities
An instruction specifies the function to be performed with an operation code and defines the location of every operand. Instructions specify an operand location by register specification, the instruction’s register field holds the register’s number; by effective address, the instruction’s effective address field contains addressing mode information; or by implicit reference, the definition of the instruction implies the use of specific registers.
The single effective address operation word format is the basic instruction word (see Figure
2-2). The encoding of the mode field selects the addressing mode. The register field contains the general register number or a value that selects the addressing mode when the mode field contains opcode 111. Some indexed or indirect addressing modes use a combination of the simple effective address operation word followed by a brief extension word. Other indexed or indirect addressing modes consist of the simple effective address operation word and a full extension word. The longest instruction is a MOVE instruction with a full extension word for both the source and destination effective addresses and eight other extension words. It also contains 32-bit base displacements and 32-bit outer displacements for both source and destination addresses. Figure 2-2 illustrates the three formats used in an instruction word; Table 2-1 lists the field definitions for these three formats.
SINGLE EFFECTIVE ADDRESS OPERATION WORD FORMAT
15
X
14
X
13
X
12
X
11
X
10
X
9
X
8
X
7
X
6
X
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
15
D/A
14 13
REGISTER
12 11
W/L
BRIEF EXTENSION WORD FORMAT
10
SCALE
9 8
0
7 6 5 4 3
DISPLACEMENT
2 1 0
15
D/A
14 13
REGISTER
12
FULL EXTENSION WORD FORMAT
11
W/L
10
SCALE
9 8
1
7
BS
6
IS
5 4
BD SIZE
BASE DISPLACEMENT (0, 1, OR 2 WORDS)
OUTER DISPLACEMENT (0, 1, OR 2 WORDS)
3
0
Figure 2-2. Instruction Word Specification Formats
2 1
I/IS
0
2-2 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Addressing Capabilities
Table 2-1. Instruction Word Format Field Definitions
Mode
Register
D/A
W/L
Scale
BS
IS
I/IS
Field
BD SIZE
Definition
Instruction
Addressing Mode
General Register Number
Extensions
Index Register Type
0 = Dn
1 = An
Word/Long-Word Index Size
0 = Sign-Extended Word
1 = Long Word
Scale Factor
00 = 1
01 = 2
10 = 4
11 = 8
Base Register Suppress
0 = Base Register Added
1 = Base Register Suppressed
Index Suppress
0 = Evaluate and Add Index Operand
1 = Suppress Index Operand
Base Displacement Size
00 = Reserved
01 = Null Displacement
10 = Word Displacement
11 = Long Displacement
Index/Indirect Selection
Indirect and Indexing Operand Determined in Conjunction with Bit 6, Index Suppress
For effective addresses that use a full extension word format, the index suppress (IS) bit and the index/indirect selection (I/IS) field determine the type of indexing and indirect action.
Table 2-2 lists the index and indirect operations corresponding to all combinations of IS and
I/IS values.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 2-3
Addressing Capabilities
IS
1
1
1
0
1
1
0
0
0
0
0
0
0
Table 2-2. IS-I/IS Memory Indirect Action Encodings
Index/Indirect
000
001
010
011
100
101
110
111
000
001
010
011
100–111
Operation
No Memory Indirect Action
Indirect Preindexed with Null Outer Displacement
Indirect Preindexed with Word Outer Displacement
Indirect Preindexed with Long Outer Displacement
Reserved
Indirect Postindexed with Null Outer Displacement
Indirect Postindexed with Word Outer Displacement
Indirect Postindexed with Long Outer Displacement
No Memory Indirect Action
Memory Indirect with Null Outer Displacement
Memory Indirect with Word Outer Displacement
Memory Indirect with Long Outer Displacement
Reserved
2.2 EFFECTIVE ADDRESSING MODES
Besides the operation code, which specifies the function to be performed, an instruction defines the location of every operand for the function. Instructions specify an operand location in one of three ways. A register field within an instruction can specify the register to be used; an instruction’s effective address field can contain addressing mode information; or the instruction’s definition can imply the use of a specific register. Other fields within the instruction specify whether the register selected is an address or data register and how the register is to be used. Section 1 Introduction contains detailed register descriptions.
An instruction’s addressing mode specifies the value of an operand, a register that contains the operand, or how to derive the effective address of an operand in memory. Each addressing mode has an assembler syntax. Some instructions imply the addressing mode for an operand. These instructions include the appropriate fields for operands that use only one addressing mode.
2-4 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Addressing Capabilities
2.2.1 Data Register Direct Mode
In the data register direct mode, the effective address field specifies the data register containing the operand.
.
GENERATION:
ASSEMBLER SYNTAX:
EA MODE FIELD:
EA REGISTER FIELD:
NUMBER OF EXTENSION WORDS:
EA = Dn
Dn
000
REG. NO.
0
DATA REGISTER OPERAND
2.2.2 Address Register Direct Mode
In the address register direct mode, the effective address field specifies the address register containing the operand.
.
GENERATION:
ASSEMBLER SYNTAX:
EA MODE FIELD:
EA REGISTER FIELD:
NUMBER OF EXTENSION WORDS:
EA = An
An
001
REG. NO.
0
ADDRESS REGISTER OPERAND
2.2.3 Address Register Indirect Mode
In the address register indirect mode, the operand is in memory. The effective address field specifies the address register containing the address of the operand in memory.
.
GENERATION:
ASSEMBLER SYNTAX:
EA MODE FIELD:
EA REGISTER FIELD:
NUMBER OF EXTENSION WORDS:
EA = (An)
(An)
010
REG. NO.
0
ADDRESS REGISTER
31 0
MEMORY
OPERAND POINTER
POINTS TO
OPERAND
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 2-5
Addressing Capabilities
2.2.4 Address Register Indirect with Postincrement Mode
In the address register indirect with postincrement mode, the operand is in memory. The effective address field specifies the address register containing the address of the operand in memory. After the operand address is used, it is incremented by one, two, or four depending on the size of the operand: byte, word, or long word, respectively. Coprocessors may support incrementing for any operand size, up to 255 bytes. If the address register is the stack pointer and the operand size is byte, the address is incremented by two to keep the stack pointer aligned to a word boundary.
.
GENERATION:
ASSEMBLER SYNTAX:
EA MODE FIELD:
EA REGISTER FIELD:
NUMBER OF EXTENSION WORDS:
EA = (An) + SIZE
(An) +
011
REG. NO.
0
ADDRESS REGISTER
OPERAND LENGTH ( 1, 2, OR 4)
OPERAND POINTER
MEMORY
31
31
SIZE
+
CONTENTS
CONTENTS
POINTS TO
OPERAND
0
0
2-6 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Addressing Capabilities
2.2.5 Address Register Indirect with Predecrement Mode
In the address register indirect with predecrement mode, the operand is in memory. The effective address field specifies the address register containing the address of the operand in memory. Before the operand address is used, it is decremented by one, two, or four depending on the operand size: byte, word, or long word, respectively. Coprocessors may support decrementing for any operand size up to 255 bytes. If the address register is the stack pointer and the operand size is byte, the address is decremented by two to keep the stack pointer aligned to a word boundary.
.
GENERATION:
ASSEMBLER SYNTAX:
EA MODE FIELD:
EA REGISTER FIELD:
NUMBER OF EXTENSION WORDS:
EA = (An)–SIZE
– (An)
100
REG. NO.
0
ADDRESS REGISTER
OPERAND LENGTH ( 1, 2, OR 4)
OPERAND POINTER
31
31
SIZE
CONTENTS
0
0
MEMORY
CONTENTS
POINTS TO
OPERAND
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 2-7
Addressing Capabilities
2.2.6 Address Register Indirect with Displacement Mode
In the address register indirect with displacement mode, the operand is in memory. The sum of the address in the address register, which the effective address specifies, plus the signextended 16-bit displacement integer in the extension word is the operand’s address in memory. Displacements are always sign-extended to 32 bits prior to being used in effective address calculations.
.
GENERATION:
ASSEMBLER SYNTAX:
EA MODE FIELD:
EA REGISTER FIELD:
NUMBER OF EXTENSION WORDS:
EA = (An) + d 16
(d An)
101
REG. NO.
1
ADDRESS REGISTER
DISPLACEMENT
31
SIGN EXTENDED
15
OPERAND POINTER
MEMORY
31
INTEGER
31
0
CONTENTS
+
CONTENTS
POINTS TO
OPERAND
0
0
2-8 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Addressing Capabilities
2.2.7 Address Register Indirect with Index (8-Bit Displacement) Mode
This addressing mode requires one extension word that contains an index register indicator and an 8-bit displacement. The index register indicator includes size and scale information.
In this mode, the operand is in memory. The operand’s address is the sum of the address register’s contents; the sign-extended displacement value in the extension word’s low-order eight bits; and the index register’s sign-extended contents (possibly scaled). The user must specify the address register, the displacement, and the index register in this mode.
.
GENERATION:
ASSEMBLER SYNTAX:
EA MODE FIELD:
EA REGISTER FIELD:
NUMBER OF EXTENSION WORDS:
EA = (An) + (Xn) + d
8
(d ,An, Xn.SIZE*SCALE)
110
REG. NO.
1
31
ADDRESS REGISTER
31 7
DISPLACEMENT SIGN EXTENDED
31
INDEX REGISTER SIGN-EXTENDED VALUE
INTEGER
0
0
CONTENTS
SCALE X SCALE VALUE
31
OPERAND POINTER
MEMORY
CONTENTS
POINTS TO
OPERAND
+
+
0
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 2-9
Addressing Capabilities
2.2.8 Address Register Indirect with Index (Base Displacement) Mode
This addressing mode requires an index register indicator and an optional 16- or 32-bit signextended base displacement. The index register indicator includes size and scaling information. The operand is in memory. The operand’s address is the sum of the contents of the address register, the base displacement, and the scaled contents of the sign-extended index register.
In this mode, the address register, the index register, and the displacement are all optional.
The effective address is zero if there is no specification. This mode provides a data register indirect address when there is no specific address register and the index register is a data register.
.
GENERATION:
ASSEMBLER SYNTAX:
EA MODE FIELD:
EA REGISTER FIELD:
NUMBER OF EXTENSION WORDS:
ADDRESS REGISTER
31
BASE DISPLACEMENT
31
INDEX REGISTER
EA = (An) + (Xn) + bd
(bd,An,Xn.SIZE*SCALE)
110
REG. NO.
1,2, OR 3
31
SIGN-EXTENDED VALUE
SIGN-EXTENDED VALUE
SCALE
OPERAND POINTER
SCALE VALUE
31
0
CONTENTS
0
X
MEMORY
CONTENTS
POINTS TO
OPERAND
+
+
0
0
2-10 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Addressing Capabilities
2.2.9 Memory Indirect Postindexed Mode
In this mode, both the operand and its address are in memory. The processor calculates an intermediate indirect memory address using a base address register and base displacement. The processor accesses a long word at this address and adds the index operand (Xn.SIZE*SCALE) and the outer displacement to yield the effective address. Both displacements and the index register contents are sign-extended to 32 bits.
In the syntax for this mode, brackets enclose the values used to calculate the intermediate memory address. All four user-specified values are optional. Both the base and outer displacements may be null, word, or long word. When omitting a displacement or suppressing an element, its value is zero in the effective address calculation.
.
GENERATION:
ASSEMBLER SYNTAX:
EA MODE FIELD:
EA REGISTER FIELD:
NUMBER OF EXTENSION WORDS:
ADDRESS REGISTER
BASE DISPLACEMENT
INTERMEDIATE
ADDRESS
MEMORY
INDEX REGISTER
31
31
EA = (An + bd) + Xn.SIZE*SCALE + od
([bd,An],Xn.SIZE*SCALE,od)
110
REG. NO.
1,2,3,4, OR 5
31
0
CONTENTS
SIGN-EXTENDED VALUE
31
+
CONTENTS
POINTS TO
31
SIGN-EXTENDED VALUE
VALUE AT INDIRECT MEMORY ADDRESS
0
0
0
0
SCALE
OUTER DISPLACEMENT
31
SCALE VALUE
0
X
+
+
SIGN-EXTENDED VALUE
31 0
OPERAND POINTER
MEMORY
CONTENTS
POINTS TO
OPERAND
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 2-11
Addressing Capabilities
2.2.10 Memory Indirect Preindexed Mode
In this mode, both the operand and its address are in memory. The processor calculates an intermediate indirect memory address using a base address register, a base displacement, and the index operand (Xn.SIZE*SCALE). The processor accesses a long word at this address and adds the outer displacement to yield the effective address. Both displacements and the index register contents are sign-extended to 32 bits.
In the syntax for this mode, brackets enclose the values used to calculate the intermediate memory address. All four user-specified values are optional. Both the base and outer displacements may be null, word, or long word. When omitting a displacement or suppressing an element, its value is zero in the effective address calculation.
.
GENERATION:
ASSEMBLER SYNTAX:
EA MODE FIELD:
EA REGISTER FIELD:
NUMBER OF EXTENSION WORDS:
EA = (bd + An) + Xn.SIZE*SCALE + od
([bd, An, Xn.SIZE*SCALE], od)
110
REG. NO.
1,2,3,4, OR 5
31
ADDRESS REGISTER
31
BASE DISPLACEMENT SIGN-EXTENDED VALUE
31
INDEX REGISTER SIGN-EXTENDED VALUE
SCALE
INTERMEDIATE ADDRESS
MEMORY
OUTER DISPLACEMENT
OPERAND POINTER
MEMORY
31
0
CONTENTS
0
+
X +
31
CONTENTS
POINTS TO
31
SIGN-EXTENDED VALUE
31
VALUE AT INDIRECT MEMORY ADDRESS
0
+
CONTENTS
POINTS TO
OPERAND
0
0
0
0
2-12 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Addressing Capabilities
2.2.11 Program Counter Indirect with Displacement Mode
In this mode, the operand is in memory. The address of the operand is the sum of the address in the program counter (PC) and the sign-extended 16-bit displacement integer in the extension word. The value in the PC is the address of the extension word. This is a program reference allowed only for reads.
.
GENERATION:
ASSEMBLER SYNTAX:
EA MODE FIELD:
EA REGISTER FIELD:
NUMBER OF EXTENSION WORDS:
PROGRAM COUNTER
DISPLACEMENT
EA = (PC) + d
111
010
1
31
SIGN EXTENDED
15
16
31
INTEGER
31
OPERAND POINTER
MEMORY
0
CONTENTS
+
CONTENTS
POINTS TO
OPERAND
0
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 2-13
Addressing Capabilities
2.2.12 Program Counter Indirect with Index (8-Bit Displacement) Mode
This mode is similar to the mode described in 2.2.7 Address Register Indirect with Index
(8-Bit Displacement) Mode , except the PC is the base register. The operand is in memory.
The operand’s address is the sum of the address in the PC, the sign-extended displacement integer in the extension word’s lower eight bits, and the sized, scaled, and sign-extended index operand. The value in the PC is the address of the extension word. This is a program reference allowed only for reads. The user must include the displacement, the PC, and the index register when specifying this addressing mode.
.
GENERATION:
ASSEMBLER SYNTAX:
EA MODE FIELD:
EA REGISTER FIELD:
NUMBER OF EXTENSION WORDS:
EA = (PC) + (Xn) + d
8
111
8
(d ,PC,Xn.SIZE*SCALE)
011
1
PROGRAM COUNTER
DISPLACEMENT
INDEX REGISTER
31
31
31
SIGN EXTENDED
7
INTEGER
0
0
SIGN-EXTENDED VALUE
CONTENTS
SCALE SCALE VALUE
31
X
OPERAND POINTER
MEMORY
CONTENTS
POINTS TO
OPERAND
+
+
0
0
2-14 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Addressing Capabilities
2.2.13 Program Counter Indirect with Index (Base Displacement) Mode
This mode is similar to the mode described in 2.2.8 Address Register Indirect with Index
, except the PC is the base register. It requires an index register indicator and an optional 16- or 32-bit sign-extended base displacement. The operand is in memory. The operand’s address is the sum of the contents of the PC, the base displacement, and the scaled contents of the sign-extended index register. The value of the
PC is the address of the first extension word. This is a program reference allowed only for reads.
In this mode, the PC, the displacement, and the index register are optional. The user must supply the assembler notation ZPC (a zero value PC) to show that the PC is not used. This allows the user to access the program space without using the PC in calculating the effective address. The user can access the program space with a data register indirect access by placing ZPC in the instruction and specifying a data register as the index register.
.
GENERATION:
ASSEMBLER SYNTAX:
EA MODE FIELD:
EA REGISTER FIELD:
NUMBER OF EXTENSION WORDS:
EA = (PC) + (Xn) + bd
(bd, PC, Xn. SIZE*SCALE)
111
011
1,2, OR 3
31
PROGRAM COUNTER
31
DISPLACEMENT SIGN-EXTENDED VALUE
31
INDEX REGISTER SIGN-EXTENDED VALUE
SCALE SCALE VALUE
31
OPERAND POINTER
0
0
MEMORY
CONTENTS
X
CONTENTS
POINTS TO
OPERAND
+
+
0
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 2-15
Addressing Capabilities
2.2.14 Program Counter Memory Indirect Postindexed Mode
This mode is similar to the mode described in
2.2.9 Memory Indirect Postindexed Mode ,
but the PC is the base register. Both the operand and operand address are in memory. The processor calculates an intermediate indirect memory address by adding a base displacement to the PC contents. The processor accesses a long word at that address and adds the scaled contents of the index register and the optional outer displacement to yield the effective address. The value of the PC used in the calculation is the address of the first extension word. This is a program reference allowed only for reads.
In the syntax for this mode, brackets enclose the values used to calculate the intermediate memory address. All four user-specified values are optional. The user must supply the assembler notation ZPC (a zero value PC) to show the PC is not used. This allows the user to access the program space without using the PC in calculating the effective address. Both the base and outer displacements may be null, word, or long word. When omitting a displacement or suppressing an element, its value is zero in the effective address calculation.
GENERATION:
ASSEMBLER SYNTAX:
EA MODE FIELD:
EA REGISTER FIELD:
NUMBER OF EXTENSION WORDS:
PROGRAM COUNTER
BASE DISPLACEMENT
INTERMEDIATE
ADDRESS
MEMORY
INDEX REGISTER
31
31
EA = (bd + PC) + Xn.SIZE*SCALE + od
([bd,PC],Xn.SIZE*SCALE,od)
111
011
1,2,3,4, or 5
31
CONTENTS
0
SIGN-EXTENDED VALUE
+
31 0
CONTENTS
POINTS TO
31
VALUE AT INDIRECT MEM. ADDRESS IN PROG. SPACE
0
0
SIGN-EXTENDED VALUE
0
SCALE SCALE VALUE X
+
31 0
OUTER DISPLACEMENT SIGN-EXTENDED VALUE
31
+
0
OPERAND POINTER
MEMORY
CONTENTS
POINTS TO
OPERAND
2-16 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Addressing Capabilities
2.2.15 Program Counter Memory Indirect Preindexed Mode
This mode is similar to the mode described in
2.2.10 Memory Indirect Preindexed Mode ,
but the PC is the base register. Both the operand and operand address are in memory. The processor calculates an intermediate indirect memory address by adding the PC contents, a base displacement, and the scaled contents of an index register. The processor accesses a long word at immediate indirect memory address and adds the optional outer displacement to yield the effective address. The value of the PC is the address of the first extension word. This is a program reference allowed only for reads.
In the syntax for this mode, brackets enclose the values used to calculate the intermediate memory address. All four user-specified values are optional. The user must supply the assembler notation ZPC showing that the PC is not used. This allows the user to access the program space without using the PC in calculating the effective address. Both the base and outer displacements may be null, word, or long word. When omitting a displacement or suppressing an element, its value is zero in the effective address calculation.
.
GENERATION:
ASSEMBLER SYNTAX:
EA MODE FIELD:
EA REGISTER FIELD:
NUMBER OF EXTENSION WORDS:
PROGRAM COUNTER
31
BASE DISPLACEMENT
31
INDEX REGISTER
EA = (bd + PC) + Xn.SIZE*SCALE + od
([bd,PC,Xn.SIZE*SCALE],od)
111
011
1,2,3,4, or 5
31
SIGN-EXTENDED VALUE
SIGN-EXTENDED VALUE
SCALE
INTERMEDIATE
ADDRESS
MEMORY
OUTER DISPLACEMENT
OPERAND POINTER
MEMORY
31
0
CONTENTS
0
+
SCALE VALUE X
+
31
INDIRECT MEMORY ADDRESS
POINTS TO
31 0
VALUE AT INDIRECT MEM. ADDRESS IN PROG. SPACE
0
0
SIGN-EXTENDED VALUE
31
+
0
CONTENTS
POINTS TO
OPERAND
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 2-17
Addressing Capabilities
2.2.16 Absolute Short Addressing Mode
In this addressing mode, the operand is in memory, and the address of the operand is in the extension word. The 16-bit address is sign-extended to 32 bits before it is used. .
GENERATION:
ASSEMBLER SYNTAX:
EA MODE FIELD:
EA REGISTER FIELD:
NUMBER OF EXTENSION WORDS:
EA GIVEN
(xxx).W
111
000
1
EXTENSION WORD
OPERAND POINTER
MEMORY
31
31
SIGN-EXTENDED
15
EXTENSION VALUE
0
0
CONTENTS
POINTS TO
OPERAND
2.2.17 Absolute Long Addressing Mode
In this addressing mode, the operand is in memory, and the operand’s address occupies the two extension words following the instruction word in memory. The first extension word contains the high-order part of the address; the second contains the low-order part of the address. .
GENERATION:
ASSEMBLER SYNTAX:
EA MODE FIELD:
EA REGISTER FIELD:
NUMBER OF EXTENSION WORDS:
EA GIVEN
(xxx).L
111
001
2
FIRST EXTENSION WORD
SECOND EXTENSION WORD
OPERAND POINTER
MEMORY
15
ADDRESS HIGH
0
15
31
CONTENTS
POINTS TO
ADDRESS LOW
0
0
OPERAND
2-18 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Addressing Capabilities
2.2.18 Immediate Data
In this addressing mode, the operand is in one or two extension words. Table 2-3 lists the location of the operand within the instruction word format. The immediate data format is as follows:
.
GENERATION:
ASSEMBLER SYNTAX:
EA MODE FIELD:
EA REGISTER FIELD:
NUMBER OF EXTENSION WORDS:
OPERAND GIVEN
#<xxx>
111
100
1,2,4, OR 6, EXCEPT FOR PACKED DECIMAL REAL OPERANDS
Table 2-3. Immediate Operand Location
Operation Length
Byte
Word
Location
Low-order byte of the extension word.
The entire extension word.
Long Word
Single-Precision
Double-Precision
High-order word of the operand is in the first extension word; the low-order word is in the second extension word.
In two extension words.
In four extension words.
Extended-Precision In six extension words.
Packed-Decimal Real In six extension words.
2.3 EFFECTIVE ADDRESSING MODE SUMMARY
Effective addressing modes are grouped according to the use of the mode. Data addressing modes refer to data operands. Memory addressing modes refer to memory operands.
Alterable addressing modes refer to alterable (writable) operands. Control addressing modes refer to memory operands without an associated size.
These categories sometimes combine to form new categories that are more restrictive. Two combined classifications are alterable memory (addressing modes that are both alterable and memory addresses) and data alterable (addressing modes that are both alterable and data). Table 2-4 lists a summary of effective addressing modes and their categories.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 2-19
Addressing Capabilities
Table 2-4. Effective Addressing Modes and Categories
Syntax
Mode
Field
Reg.
Field Data Memory Control Alterable Addressing Modes
Register Direct
Data
Address
Register Indirect
Address
Address with Postincrement
Address with Predecrement
Address with Displacement
Address Register Indirect with Index
8-Bit Displacement
Base Displacement
Memory Indirect
Postindexed
Preindexed
Program Counter Indirect with Displacement
Program Counter Indirect with Index
8-Bit Displacement
Base Displacement
Program Counter Memory Indirect
Postindexed
Preindexed
Absolute Data Addressing
Short
Long
Immediate
Dn
An
(An)
(An)+
–(An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An],Xn,od)
([bd,An,Xn],od)
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC],Xn,od)
([bd,PC,Xn],od)
(xxx).W
(xxx).L
#<xxx>
000
001
010
011
100
101
110
110
110
110
111
111
111
111
111
111
111
111 reg. no.
reg. no.
reg. no.
reg. no.
reg. no.
reg. no.
reg. no.
reg. no.
reg. no.
reg. no.
010
011
011
011
011
000
000
100
X
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
—
X
X
X
X
X
X
X
X
X
X
X
—
X
—
—
X
X
X
—
—
—
X
X
X
X
X
X
X
X
—
—
—
X
X
2-20 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Addressing Capabilities
2.4 BRIEF EXTENSION WORD FORMAT COMPATIBILITY
Programs can be easily transported from one member of the M68000 family to another in an upward-compatible fashion. The user object code of each early member of the family, which is upward compatible with newer members, can be executed on the newer microprocessor without change. Brief extension word formats are encoded with information that allows the CPU32, MC68020, MC68030, and MC68040 to distinguish the basic M68000 family architecture’s new address extensions. Figure 2-3 illustrates these brief extension word formats. The encoding for SCALE used by the CPU32, MC68020, MC68030, and
MC68040 is a compatible extension of the M68000 family architecture. A value of zero for
SCALE is the same encoding for both extension words. Software that uses this encoding is compatible with all processors in the M68000 family. Both brief extension word formats do not contain the other values of SCALE. Software can be easily migrated in an upwardcompatible direction, with downward support only for nonscaled addressing. If the MC68000 were to execute an instruction that encoded a scaling factor, the scaling factor would be ignored and would not access the desired memory address. The earlier microprocessors do not recognize the brief extension word formats implemented by newer processors. Although they can detect illegal instructions, they do not decode invalid encodings of the brief extension word formats as exceptions.
15
D/A
14 13
REGISTER
12 11
W/L
10
0
9
0
8
0
7 6 5 4 3 2
DISPLACEMENT INTEGER
15
D/A
14 13
REGISTER
12
(a) MC68000, MC68008, and MC68010
11
W/L
10
SCALE
9 8
0
7 6 5 4 3 2
DISPLACEMENT INTEGER
(b) CPU32, MC68020, MC68030, and MC68040
Figure 2-3. M68000 Family Brief Extension Word Formats
1
1
0
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 2-21
Addressing Capabilities
2.5 FULL EXTENSION ADDRESSING MODES
The full extension word format provides additional addressing modes for the MC68020,
MC68030, and MC68040. There are four elements common to these full extension addressing modes: a base register (BR), an index register (Xn), a base displacement (bd), and an outer displacement (od). Each of these four elements can be suppressed independently of each other. However, at least one element must be active and not suppressed. When an element is suppressed, it has an effective value of zero.
BR can be suppressed through the BS field of the full extension word format. The encoding of bits 0-5 in the single effective address word format (see Figure 2-2) selects BR as either the PC when using program relative addressing modes, or An when using non-program relative addressing modes. The value of the PC is the address of the extension word. For the non-program relative addressing modes, BR is the contents of a selected An.
SIZE and SCALE can be used to modify Xn. The W/L field in the full extension format selects the size of Xn as a word or long word. The SCALE field selects the scaling factor, shifts the value of the Xn left multiplying the value by 1, 2, 4, or 8, respectively, without actually changing the value. Scaling can be used to calculate the address of arrayed structures.
Figure 2-4 illustrates the scaling of an Xn.
The bd and od can be either word or long word. The size of od is selected through the encoding of the I/IS field in the full extension word format (refer to Table 2-2). There are two main modes of operation that use these four elements in different ways: no memory indirect action and memory indirect. The od is provided only for using memory indirect addressing modes of which there are three types: with preindex, with postindex, and with index suppressed.
2-22 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
A6 = 0
1
2
3
7
Addressing Capabilities
.
SYNTAX: MOVE.B (A5, A6.L*SCALE),(A7)
WHERE
A5 = ADDRESS OF ARRAY STRUCTURE
A6 = INDEX NUMBER OF ARRAY ITEM
A7 = STACK POINTER
SIMPLE ARRAY
(SCALE = 1)
0 7
A6 = 0
1
RECORD OF 2 BYTES
(SCALE = 2)
0
A6 = 0
7
RECORD OF 4 BYTES
(SCALE = 4)
0
A6 = 0
7
RECORD OF 8 BYTES
(SCALE = 8)
0
1
1
NOTE: Regardless of array structure, software increments
index by the appropriate amount to point to next
record.
Figure 2-4. Addressing Array Items
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 2-23
Addressing Capabilities
2.5.1 No Memory Indirect Action Mode
No memory indirect action mode uses BR, Xn with its modifiers, and bd to calculate the address of the required operand. Data register indirect (Dn) and absolute address with index
(bd,Xn.SIZE*SCALE) are examples of the no memory indirect action mode. Figure 2-5 illustrates the no memory indirect action mode.
BR Xn bd
S S S Not Applicable
A
S
S
A
A
S
S
A
S
A
A
An
An
An
PC
S
S
S
An
PC
PC
PC
Addressing Mode
A Absolute Addressing Mode
S Register Indirect
A Register Indirect with Constant Index
S Address Register Indirect
A Address Register Indirect with Constant Index
S Address Register Indirect with Variable Index
A Address Register Indirect with Constant and Variable Index
S PC Relative
A PC Relative with Constant Index
S PC Relative with Variable Index
A PC Relative with Constant and Variable Index
NOTE: S indicates suppressed and A indicates active.
.
An or PC bd.BD SIZE
Xn.SIZE*SCALE
OPERAND
Figure 2-5. No Memory Indirect Action
2-24 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Addressing Capabilities
2.5.2 Memory Indirect Modes
Memory indirect modes fetch two operands from memory. The BR and bd evaluate the address of the first operand, intermediate memory pointer (IMP). The value of IMP and the od evaluates the address of the second operand.
There are three types of memory indirect modes: pre-index, post-index, and index register suppressed. Xn and its modifiers can be allocated to determine either the address of the IMP
(pre-index) or to the address of the second operand (post-index).
2.5.2.1 MEMORY INDIRECT WITH PREINDEX. The Xn is allocated to determine the address of the IMP. Figure 2-6 illustrates the memory indirect with pre-indexing mode.
BR Xn bd od
S A S
IMP Addressing Mode
S Register Indirect
S
S
S
A
A
A
S
A
A
A
S
Register Indirect
Register Indirect with Constant Index
An
An
An
A
A
A
S
S
A
A Register Indirect with Constant Index
S
A
Address Register Indirect with
Variable Index
Address Register Indirect with
Variable Index
S
A
Address Register Indirect with
Constant and Variable Index
Address Register Indirect with
Constant and Variable Index
S PC Relative with Variable Index
An
PC
A
A
A
S
PC
PC
PC
A
A
A
S
A
A
A PC Relative with Variable Index
S
A
PC Relative with Constant and
Variable Index
PC Relative with Constant and
Variable Index
NOTE: S indicates suppressed and A indicates active.
Operand Addressing Mode
Memory Pointer Directly to Data Operand
Memory Pointer as Base with Displacement to Data Operand
Memory Pointer Directly to Data Operand
Memory Pointer as Base with Displacement to Data Operand
Memory Pointer Directly to Data Operand
Memory Pointer as Base with Displacement to Data Operand
Memory Pointer Directly to Data Operand
Memory Pointer as Base with Displacement to Data Operand
Memory Pointer Directly to Data Operand
Memory Pointer as Base with Displacement to Data Operand
Memory Pointer Directly to Data Operand
Memory Pointer as Base with Displacement to Data Operand
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 2-25
Addressing Capabilities
.
An or PC bd.BD SIZE od.OD SIZE
OPERAND
Xn.SIZE*SCALE
IMP
Figure 2-6. Memory Indirect with Preindex
2.5.2.2 MEMORY INDIRECT WITH POSTINDEX. The Xn is allocated to evaluate the address of the second operand. Figure 2-7 illustrates the memory indirect with post-indexing mode.
BR Xn bd od
S
S
A
A
S
S
S
A
S A A
IMP Addressing Mode
—
—
S Absolute Addressing Mode
S
An
An
An
A
A
A
A
A
S
S
A
A Absolute Addressing Mode
S Address Register Indirect
A Address Register Indirect
S
A
Address Register Indirect with
Constant Index
Address Register Indirect with
Constant Index
S PC Relative
An
PC
PC
PC
A
A
A
A
A
S
S
A
A
S
PC Relative
PC Relative with Constant Index
PC A A A PC Relative with Constant Index
NOTE: S indicates suppressed and A indicates active.
Operand Addressing Mode
—
—
Memory Pointer with Variable Index to
Data Operand
Memory Pointer with Constant and Variable
Index to Data Operand
Memory Pointer with Variable Index to
Data Operand
Memory Pointer with Constant and Variable
Index to Data Operand
Memory Pointer with Variable Index to
Data Operand
Memory Pointer with Constant and Variable
Index to Data Operand
Memory Pointer with Variable Index to
Data Operand
Memory Pointer with Constant and Variable
Index to Data Operand
Memory Pointer with Variable Index to
Data Operand
Memory Pointer with Constant and Variable
Index to Data Operand
2-26 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Addressing Capabilities
.
An or PC bd.BD SIZE od.OD SIZE
IMP od.OD SIZE
OPERAND
Figure 2-7. Memory Indirect with Postindex
2.5.2.3 MEMORY INDIRECT WITH INDEX SUPPRESSED. The Xn is suppressed. Figure
2-8 illustrates the memory indirect with index suppressed mode.
S
An
An
BR Xn bd od
S
S
S
S
S
S
S
A
S S A
IMP Addressing Mode
—
—
S Absolute Addressing Mode
An
An
PC
PC
PC
PC
S
S
S
S
S
S
S
S
S
S
A
A
A
S
A
S
S
A
A Absolute Addressing Mode
S Address Register Indirect
A Address Register Indirect
S
A
Address Register Indirect with
Constant Index
Address Register Indirect with
Constant Index
S PC Relative
A PC Relative
S PC Relative with Constant Index
A PC Relative with Constant Index
NOTE: S indicates suppressed and A indicates active.
.
Operand Addressing Mode
—
—
Memory Pointer Directly to Data Operand
Memory Pointer as Base with Displacement to Data Operand
Memory Pointer Directly to Data Operand
Memory Pointer as Base with Displacement to Data Operand
Memory Pointer Directly to Data Operand
Memory Pointer as Base with Displacement to Data Operand
Memory Pointer Directly to Data Operand
Memory Pointer as Base with Displacement to Data Operand
Memory Pointer Directly to Data Operand
Memory Pointer as Base with Displacement to Data Operand
An or PC bd.BD SIZE od.OD SIZE
IMP OPERAND
Figure 2-8. Memory Indirect with Index Suppress
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 2-27
Addressing Capabilities
2.6 OTHER DATA STRUCTURES
Stacks and queues are common data structures. The M68000 family implements a system stack and instructions that support user stacks and queues.
2.6.1 System Stack
Address register seven (A7) is the system stack pointer. Either the user stack pointer (USP), the interrupt stack pointer (ISP), or the master stack pointer (MSP) is active at any one time.
Refer to Section 1 Introduction for details on these stack pointers. To keep data on the system stack aligned for maximum efficiency, the active stack pointer is automatically decremented or incremented by two for all byte-size operands moved to or from the stack.
In long-word-organized memory, aligning the stack pointer on a long-word address significantly increases the efficiency of stacking exception frames, subroutine calls and returns, and other stacking operations.
The user can implement stacks with the address register indirect with postincrement and predecrement addressing modes. With an address register the user can implement a stack that fills either from high memory to low memory or from low memory to high memory.
Important consideration are:
• Use the predecrement mode to decrement the register before using its contents as the pointer to the stack.
• Use the postincrement mode to increment the register after using its contents as the pointer to the stack.
• Maintain the stack pointer correctly when byte, word, and long-word items mix in these stacks.
To implement stack growth from high memory to low memory, use -(An) to push data on the stack and (An) + to pull data from the stack. For this type of stack, after either a push or a pull operation, the address register points to the top item on the stack.
.
An
LOW MEMORY
(FREE)
TOP OF STACK
BOTTOM OF STACK
HIGH MEMORY
2-28 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Addressing Capabilities
To implement stack growth from low memory to high memory, use (An) + to push data on the stack and -(An) to pull data from the stack. After either a push or pull operation, the address register points to the next available space on the stack. .
LOW MEMORY
BOTTOM OF STACK
An
TOP OF STACK
(FREE)
HIGH MEMORY
2.6.2 Queues
The user can implement queues, groups of information waiting to be processed, with the address register indirect with postincrement or predecrement addressing modes. Using a pair of address registers, the user implements a queue that fills either from high memory to low memory or from low memory to high memory. Two registers are used because the queues get pushed from one end and pulled from the other. One address register contains the put pointer; the other register the get pointer. To implement growth of the queue from low memory to high memory, use the put address register to put data into the queue and the get address register to get data from the queue.
After a put operation, the put address register points to the next available space in the queue; the unchanged get address register points to the next item to be removed from the queue. After a get operation, the get address register points to the next item to be removed from the queue; the unchanged put address register points to the next available space in the queue. .
GET (Am) +
LOW MEMORY
LAST GET (FREE)
NEXT GET
PUT (An) +
LAST PUT
(FREE)
HIGH MEMORY
To implement the queue as a circular buffer, the relevant address register should be checked and adjusted. If necessary, do this before performing the put or get operation. Subtracting the buffer length (in bytes) from the register adjusts the address register. To implement growth of the queue from high memory to low memory, use the put address register indirect to put data into the queue and get address register indirect to get data from the queue.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 2-29
Addressing Capabilities
After a put operation, the put address register points to the last item placed in the queue; the unchanged get address register points to the last item removed from the queue. After a get operation, the get address register points to the last item placed in the queue.
.
PUT – (An)
LOW MEMORY
(FREE)
LAST PUT
GET – (Am)
NEXT GET
LAST GET (FREE)
HIGH MEMORY
To implement the queue as a circular buffer, the get or put operation should be performed first. Then the relevant address register should be checked and adjusted, if necessary.
Adding the buffer length (in bytes) to the address register contents adjusts the address register.
2-30 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
SECTION 3
INSTRUCTION SET SUMMARY
This section briefly describes the M68000 family instruction set, using Motorola,s assembly language syntax and notation. It includes instruction set details such as notation and format, selected instruction examples, and an integer condition code discussion. The section concludes with a discussion of floating-point details such as computational accuracy, conditional test definitions, an explanation of the operation table, and a discussion of not-anumbers (NANs) and postprocessing.
3.1 INSTRUCTION SUMMARY
Instructions form a set of tools that perform the following types of operations:
Data Movement
Integer Arithmetic
Logical Operations
Shift and Rotate Operations
Bit Manipulation
Bit Field Manipulation
Binary-Coded Decimal Arithmetic
Program Control
System Control
Cache Maintenance
Multiprocessor Communications
Memory Management
Floating-Point Arithmetic
The following paragraphs describe in detail the instruction for each type of operation. Table
3-1 lists the notations used throughout this manual. In the operand syntax statements of the instruction definitions, the operand on the right is the destination operand.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 3-1
Instruction Set Summary
Table 3-1. Notational Conventions
+
–
×
÷
~
Λ
V
⊕
→
←→
<op>
Arithmetic addition or postincrement indicator.
Arithmetic subtraction or predecrement indicator.
Arithmetic multiplication.
Arithmetic division or conjunction symbol.
Invert; operand is logically complemented.
Logical AND
Logical OR
Logical exclusive OR
Source operand is moved to destination operand.
Two operands are exchanged.
Any double-operand operation.
<operand>tested Operand is compared to zero and the condition codes are set appropriately.
sign-extended All bits of the upper portion are made equal to the high-order bit of the lower portion.
TRAP
STOP
Other Operations
Equivalent to Format
÷
Offset Word
→
→
(SSP); SSP – 2
→
SSP; (Vector)
(SSP); SSP – 2
→
PC
→
SSP; PC
→
(SSP); SSP – 4
→
SSP; SR
Enter the stopped state, waiting for interrupts.
<operand>
10
If <condition> then <operations> else <operations>
Single- And Double Operand Operations
The operand is BCD; operations are performed in decimal.
Test the condition. If true, the operations after “then”are performed. If the condition is false and the optional “else”clause is present, the operations after “else”are performed. If the condition is false and else is omitted, the instruction performs no operation. Refer to the Bcc instruction description as an example.
Register Specifications
An
Ax, Ay
Dc
Dh, Dl
Dn
Dr, Dq
Du
Dx, Dy
MRn
Rn
Rx, Ry
Xn
Any Address Register n (example: A3 is address register 3)
Source and destination address registers, respectively.
Data register D7–D0, used during compare.
Data register’s high- or low-order 32 bits of product.
Any Data Register n (example: D5 is data register 5)
Data register’s remainder or quotient of divide.
Data register D7–D0, used during update.
Source and destination data registers, respectively.
Any Memory Register n.
Any Address or Data Register
Any source and destination registers, respectively.
Index Register
3-2 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Set Summary
Table 3-1. Notational Conventions (Continued)
+ inf
<fmt>
[ ] bd ccc d n
LSB
LSW
MSB
MSW od
SCALE
SIZE
{offset:width}
Data Format And Type
Positive Infinity
Operand Data Format: Byte (B), Word (W), Long (L), Single (S), Double (D), Extended (X), or
Packed (P).
B, W, L
D k
P
S
X
– inf
Specifies a signed integer data type (twos complement) of byte, word, or long word.
Double-precision real data format (64 bits).
A twos complement signed integer (–64 to +17) specifying a number’s format to be stored in the packed decimal format.
Packed BCD real data format (96 bits, 12 bytes).
Single-precision real data format (32 bits).
Extended-precision real data format (96 bits, 16 bits unused).
Negative Infinity
Subfields and Qualifiers
#<xxx> or #<data> Immediate data following the instruction word(s).
( ) Identifies an indirect address in a register.
Identifies an indirect address in memory.
Base Displacement
Index into the MC68881/MC68882 Constant ROM
Displacement Value, n Bits Wide (example: d
16
is a 16-bit displacement).
Least Significant Bit
Least Significant Word
Most Significant Bit
Most Significant Word
Outer Displacement
A scale factor (1, 2, 4, or 8 for no-word, word, long-word, or quad-word scaling, respectively).
The index register’s size (W for word, L for long word).
CCR
DFC
FPcr
FPm, FPn
IC, DC, IC/DC
MMUSR
PC
Rc
SFC
SR
Bit field selection.
Register Names
Condition Code Register (lower byte of status register)
Destination Function Code Register
Any Floating-Point System Control Register (FPCR, FPSR, or FPIAR)
Any Floating-Point Data Register specified as the source or destination, respectively.
Instruction, Data, or Both Caches
MMU Status Register
Program Counter
Any Non Floating-Point Control Register
Source Function Code Register
Status Register
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 3-3
FC
N
U
V
*
C cc
X
Z
—
ISP
MSP
SP
SSP
USP
<ea>
<label>
<list>
LB m m–n
UB
Instruction Set Summary
Table 3-1. Notational Conventions (Concluded)
Register Codes
General Case
Carry Bit in CCR
Condition Codes from CCR
Function Code
Negative Bit in CCR
Undefined, Reserved for Motorola Use.
Overflow Bit in CCR
Extend Bit in CCR
Zero Bit in CCR
Not Affected or Applicable.
Stack Pointers
Supervisor/Interrupt Stack Pointer
Supervisor/Master Stack Pointer
Active Stack Pointer
Supervisor (Master or Interrupt) Stack Pointer
User Stack Pointer
Miscellaneous
Effective Address
Assemble Program Label
List of registers, for example D3–D0.
Lower Bound
Bit m of an Operand
Bits m through n of Operand
Upper Bound
3-4 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Set Summary
3.1.1 Data Movement Instructions
The MOVE and FMOVE instructions with their associated addressing modes are the basic means of transferring and storing addresses and data. MOVE instructions transfer byte, word, and long-word operands from memory to memory, memory to register, register to memory, and register to register. MOVE instructions transfer word and long-word operands and ensure that only valid address manipulations are executed. In addition to the general
MOVE instructions, there are several special data movement instructions: MOVE16,
MOVEM, MOVEP, MOVEQ, EXG, LEA, PEA, LINK, and UNLK. The MOVE16 instruction is an MC68040 extension to the M68000 instruction set.
The FMOVE instructions move operands into, out of, and between floating-point data registers. FMOVE also moves operands to and from the floating-point control register
(FPCR), floating-point status register (FPSR), and floating-point instruction address register
(FPIAR). For operands moved into a floating-point data register, FSMOVE and FDMOVE explicitly select single- and double-precision rounding of the result, respectively. FMOVEM moves any combination of either floating-point data registers or floating-point control registers. Table 3-2 lists the general format of these integer and floating-point data movement instructions.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 3-5
Instruction Set Summary
Table 3-2. Data Movement Operation Format
Instruction
EXG
FMOVE
FSMOVE,
FDMOVE
FMOVEM
Operand Syntax
Rn, Rn
FPm,FPn
<ea>,FPn
FPm,<ea>
<ea>,FPcr
FPcr,<ea>
FPm,FPn
<ea>,FPn
<ea>,<list>
1
<ea>,Dn
<list>
1
,<ea>
Dn,<ea>
<ea>,An
Operand Size
32 Rn
← →
Rn
Source
→
Destination
Operation
X
B, W, L, S, D, X, P
B, W, L, S, D, X, P
32
32
X
B, W, L, S, D, X
32, X
X
32, X
X
Source
→
Destination; round destination to single or double precision.
Listed Registers
→
Destination
Source
→
Listed Registers
LEA
LINK
MOVE
MOVE16
MOVEA
MOVEM
MOVEP
MOVEQ
PEA
UNLK
An,#<d>
<ea>,<ea>
<ea>,<ea>
<ea>,An list,<ea>
<ea>,list
Dn, (d
16
,An)
(d
16
,An),Dn
#<data>,Dn
<ea>
An
32
16, 32
8, 16, 32
16 bytes
16, 32 → 32
16, 32
16, 32 → 32
16, 32
8
→
32
32
32
<ea> → An
SP – 4
→
SP; An
→
(SP); SP
→
An, SP + D
→
SP
Source → Destination
Aligned 16-Byte Block
→
Destination
Listed Registers
→
Destination
Source → Listed Registers
Dn 31–24
→
(An + d n
); Dn 23–16
→
(An + d n
+ 2);
Dn 15–8
→
(An + d n
+ 4); Dn 7–0
→
(An + d n
+ 6)
(An + d n
)
(An + d n
→
Dn 31–24; (An + d n
+ 2)
→
Dn 23–16;
+ 4)
→
Dn 15–8; (An + d n
+ 6)
→
Dn 7–0
Immediate Data
→
Destination
SP – 4
→
SP; <ea>
→
(SP)
An
→
SP; (SP)
→
An; SP + 4
→
SP
NOTE: A register list includes any combination of the eight floating-point data registers or any combination of three control registers (FPCR, FPSR, and FPIAR). If a register list mask resides in a data register, only floating-point data registers may be specified.
3.1.2 Integer Arithmetic Instructions
The integer arithmetic operations include four basic operations: ADD, SUB, MUL, and DIV.
They also include CMP, CMPM, CMP2, CLR, and NEG. The instruction set includes ADD,
CMP, and SUB instructions for both address and data operations with all operand sizes valid for data operations. Address operands consist of 16 or 32 bits. The CLR and NEG instructions apply to all sizes of data operands. Signed and unsigned MUL and DIV instructions include:
• Word multiply to produce a long-word product.
• Long-word multiply to produce a long-word or quad-word product.
• Long word divided by a word divisor (word quotient and word remainder).
• Long word or quad word divided by a long-word divisor (long-word quotient and longword remainder).
3-6 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Set Summary
A set of extended instructions provides multiprecision and mixed-size arithmetic: ADDX,
SUBX, EXT, and NEGX. Refer to Table 3-3 for a summary of the integer arithmetic operations. In Table 3-3, X refers to the X-bit in the CCR.
Table 3-3. Integer Arithmetic Operation Format
Instruction Operand Syntax Operand Size
ADD
ADDA
Dn,<ea>
<ea>,Dn
<ea>,An
8, 16, 32
8, 16, 32
16, 32
ADDI
ADDQ
ADDX
CLR
CMP
CMPA
CMPI
CMPM
CMP2
DIVS/DIVU
DIVSL/DIVUL
EXT
EXTB
MULS/MULU
NEG
NEGX
SUB
SUBA
SUBI
SUBQ
SUBX
#<data>,<ea>
#<data>,<ea>
Dn,Dn
–(An), –(An)
<ea>
<ea>,Dn
<ea>,An
#<data>,<ea>
(An)+,(An)+
<ea>,Rn
<ea>,Dn
<ea>,Dr–Dq
<ea>,Dq
<ea>,Dr–Dq
Dn
Dn
Dn
<ea>,Dn
<ea>,Dl
<ea>,Dh–Dl
<ea>
<ea>
<ea>,Dn
Dn,<ea>
<ea>,An
#<data>,<ea>
#<data>,<ea>
Dn,Dn
–(An), –(An)
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
16, 32
8, 16, 32
8, 16, 32
8, 16, 32
32
÷
64
÷
16
32
32
÷
→
→
16,16
32,32
32
→
32
32
÷
32
→
32,32
8
16
→
→
16
32
8
→
32
16 x 16
→
32
32 x 32
→
32 x 32
→
32
64
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
Operation
Source + Destination
→
Destination
Immediate Data + Destination
→
Destination
Source + Destination + X
→
Destination
0
→
Destination
Destination – Source
Destination – Immediate Data
Destination – Source
Lower Bound
→
Rn
→
Upper Bound
Destination
÷
Source
→
Destination
(Signed or Unsigned Quotient, Remainder)
Sign-Extended Destination
→
Destination
Source x Destination
→
Destination
(Signed or Unsigned)
0 – Destination
→
Destination
0 – Destination – X
→
Destination
Destination = Source
→
Destination
Destination – Immediate Data
→
Destination
Destination – Source – X
→
Destination
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 3-7
Instruction Set Summary
3.1.3 Logical Instructions
The logical operation instructions (AND, OR, EOR, and NOT) perform logical operations with all sizes of integer data operands. A similar set of immediate instructions (ANDI, ORI, and EORI) provides these logical operations with all sizes of immediate data. Table 3-4 summarizes the logical operations.
Table 3-4. Logical Operation Format
Instruction Operand Syntax Operand Size
AND
ANDI
<ea>,Dn
Dn,<ea>
#<data>,<ea>
8, 16, 32
8, 16, 32
8, 16, 32
EOR
EORI
NOT
OR
ORI
Dn,<ea>
#<data>,<ea>
<ea>
<ea>,Dn
Dn,<ea>
#<data>,<ea>
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
8, 16, 32
Operation
Source
Λ
Destination
→
Destination
Immediate Data
Λ
Destination
→
Destination
Source
⊕
Destination
→
Destination
Immediate Data
⊕
Destination
→
Destination
~ Destination
→
Destination
Source V Destination
→
Destination
Immediate Data V Destination
→
Destination
3.1.4 Shift and Rotate Instructions
The ASR, ASL, LSR, and LSL instructions provide shift operations in both directions. The
ROR, ROL, ROXR, and ROXL instructions perform rotate (circular shift) operations, with and without the CCR extend bit (X-bit). All shift and rotate operations can be performed on either registers or memory.
Register shift and rotate operations shift all operand sizes. The shift count can be specified in the instruction operation word (to shift from 1 – 8 places) or in a register (modulo 64 shift count).
Memory shift and rotate operations shift word operands one bit position only. The SWAP instruction exchanges the 16-bit halves of a register. Fast byte swapping is possible by using the ROR and ROL instructions with a shift count of eight, enhancing the performance of the shift/rotate instructions. Table 3-5 is a summary of the shift and rotate operations. In Table
3-5, C and X refer to the C-bit and X- bit in the CCR.
3-8 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Set Summary
Table 3-5. Shift and Rotate Operation Format
Instruction
ASL
ASR
LSL
LSR
Operand Syntax
Dn, Dn
# data , Dn ea
Dn, Dn
# data , Dn ea
Dn, Dn
# data , Dn ea
Dn, Dn
# data , Dn ea
ROL
ROR
ROXL
ROXR
SWAP
Dn, Dn
# data , Dn ea
Dn, Dn
# data , Dn ea
Dn, Dn
# data , Dn ea
Dn, Dn
# data , Dn ea
Dn
8, 16, 32
8, 16, 32
16
8, 16, 32
8, 16, 32
16
8, 16, 32
8, 16, 32
16
8, 16, 32
8, 16, 32
16
32
Operand Size
8, 16, 32
8, 16, 32
16
8, 16, 32
8, 16, 32
16
8, 16, 32
8, 16, 32
16
8, 16, 32
8, 16, 32
16
C
0
X/C
X/C
X
C
Operation
MSW LSW
X/C
X/C
C
X
0
0
C
NOTE: X indicates the extend bit and C the carry bit in the CCR.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 3-9
Instruction Set Summary
3.1.5 Bit Manipulation Instructions
BTST, BSET, BCLR, and BCHG are bit manipulation instructions. All bit manipulation operations can be performed on either registers or memory. The bit number is specified either as immediate data or in the contents of a data register. Register operands are 32 bits long, and memory operands are 8 bits long. Table 3-6 summarizes bit manipulation operations; Z refers to the zero bit of the CCR.
Instruction
BCHG
BCLR
BSET
BTST
Table 3-6. Bit Manipulation Operation Format
Operand Syntax
Dn,<ea>
#<data>,<ea>
Dn,<ea>
#<data>,<ea>
Dn,<ea>
#<data>,<ea>
Dn,<ea>
#<data>,<ea>
Operand Size
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
8, 32
Operation
~ (<Bit Number> of Destination)
→
Z
→
Bit of Destination
~ (<Bit Number> of Destination)
→
Z;
0
→
Bit of Destination
~ (<Bit Number> of Destination)
→
Z;
1
→
Bit of Destination
~ (<Bit Number> of Destination)
→
Z
3.1.6 Bit Field Instructions
The M68000 family architecture supports variable-length bit field operations on fields of up to 32 bits. The BFINS instruction inserts a value into a bit field. BFEXTU and BFEXTS extract a value from the field. BFFFO finds the first set bit in a bit field. Also included are instructions analogous to the bit manipulation operations: BFTST, BFSET, BFCLR, and
BFCHG. Table 3-7 summarizes bit field operations.
Instruction
BFCHG
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
Table 3-7. Bit Field Operation Format
Operand Syntax
<ea> {offset:width}
<ea> {offset:width}
<ea> {offset:width}, Dn
<ea> {offset:width}, Dn
<ea> {offset:width}, Dn
Dn,<ea> {offset:width}
<ea> {offset:width}
<ea> {offset:width}
Operand Size
1–32
1–32
1–32
1–32
1–32
1–32
1–32
1–32
Operation
~ Field
→
Field
0's
→
Field
Field
→
Dn; Sign-Extended
Field
→
Dn; Zero-Extended
Scan for First Bit Set in Field; Offset
→
Dn.
Dn
→
Field
1's
→
Field
Field MSB
→
N; ~ (OR of All Bits in Field)
→
Z
NOTE: All bit field instructions set the CCR N and Z bits as shown for BFTST before performing the specified operation.
3-10 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Set Summary
3.1.7 Binary-Coded Decimal Instructions
Five instructions support operations on binary-coded decimal (BCD) numbers. The arithmetic operations on packed BCD numbers are ABCD, SBCD, and NBCD. PACK and
UNPK instructions aid in the conversion of byte-encoded numeric data, such as ASCII or
EBCDIC strings to BCD data and vice versa. Table 3-8 summarizes BCD operations. In
Table 3- 8 X refers to the X-bit in the CCR.
Table 3-8. Binary-Coded Decimal Operation Format
Instruction Operand Syntax Operand Size
ABCD
NBCD
PACK
SBCD
UNPK
Dn,Dn
–(An), –(An)
<ea>
–(An), –(An) #<data>
Dn,Dn,#<data>
Dn,Dn
–(An), –(An)
–(An),–(An) #<data>
Dn,Dn,#<data>
8
8
8
16
→
8
16
→
8
8
8
8
→
16
8
→
16
Operation
Source
10
+ Destination
10
+ X
→
Destination
0 – Destination
10
– X
→
Destination
Unpackaged Source + Immediate Data
→
Packed
Destination
Destination
10 –
Source
10 –
X
→
Destination
Packed Source
→
Unpacked Source
Unpacked Source + Immediate Data
→
Unpacked Destination
3.1.8 Program Control Instructions
A set of subroutine call and return instructions and conditional and unconditional branch instructions perform program control operations. Also included are test operand instructions
(TST and FTST), which set the integer or floating-point condition codes for use by other program and system control instructions. NOP forces synchronization of the internal pipelines. Table 3-9 summarizes these instructions.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 3-11
Instruction Set Summary
Table 3-9. Program Control Operation Format
Instruction Operand Syntax Operand Size
Bcc, FBcc
DBcc, FDBcc
Scc, FScc
BRA
BSR
JMP
JSR
NOP
FNOP
RTD
RTR
RTS
<label>
Dn,<label>
<ea>
<label>
<label>
<ea>
<ea> none none
#<data> none none
Operation
Integer and Floating-Point Conditional
8, 16, 32
16
8
If Condition True, Then PC + d n
→
PC
If Condition False, Then Dn – 1
→
Dn
If Dn
→
–1, Then PC + d n
→
PC
If Condition True, Then 1's
→
Destination;
Else 0's
→
Destination none none none none
Unconditional
8, 16, 32
8, 16, 32
PC + d n
→
PC
SP – 4
→
SP; PC
→
(SP); PC + d n
→
PC
Destination
→
PC
SP – 4
→
SP; PC
→
(SP); Destination
→
PC
PC + 2
→
PC (Integer Pipeline Synchronized)
PC + 4
→
PC (FPU Pipeline Synchronized)
16 none none
Returns
(SP)
→
PC; SP + 4 + d n
→
SP
(SP)
→
CCR; SP + 2
→
SP; (SP)
→
PC; SP + 4
→
SP
(SP)
→
PC; SP + 4
→
SP
Test Operand
TST
FTST
<ea>
<ea>
FPn
8, 16, 32
B, W, L, S, D, X, P
X
Set Integer Condition Codes
Set Floating-Point Condition Codes
Letters cc in the integer instruction mnemonics Bcc, DBcc, and Scc specify testing one of the following conditions:
CC—Carry clear GE—Greater than or equal
LS—Lower or same PL—Plus
CS—Carry set
LT—Less than
EQ—Equal
MI—Minus
F—Never true*
NE—Not equal
GT—Greater than
T—Always true*
HI—Higher
VC—Overflow clear
LE—Less than or equal
VS—Overflow set
*Not applicable to the Bcc instructions.
3.1.9 System Control Instructions
Privileged and trapping instructions as well as instructions that use or modify the CCR provide system control operations. FSAVE and FRESTORE save and restore the nonuser visible portion of the FPU during context switches in a virtual memory or multitasking system. The conditional trap instructions, which use the same conditional tests as their corresponding program control instructions, allow an optional 16- or 32-bit immediate operand to be included as part of the instruction for passing parameters to the operating system. These instructions cause the processor to flush the instruction pipe. Table 3-10 summarizes these instructions. See 3.2 Integer Unit Condition Code Computation for more details on condition codes.
3-12 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Set Summary
Instruction
ANDI to SR
EORI to SR
FRESTORE
FSAVE
MOVE to SR
MOVE from SR
MOVE USP
MOVEC
MOVES
ORI to SR
RESET
RTE
STOP
BKPT
CHK
CHK2
ILLEGAL
TRAP
TRAPcc
FTRAPcc
TRAPV
ANDI to SR
EORI to SR
MOVE to SR
MOVE from SR
ORI to SR
#<data>,SR
#<data>,SR
<ea>
<ea>
<ea>,SR
SR,<ea>
USP,An
An,USP
Rc,Rn
Rn,Rc
Rn,<ea>
<ea>,Rn
#<data>,SR none none
Table 3-10. System Control Operation Format
Operand
Syntax
Operand Size Operation
#<data>
#<data>
<ea>,Dn
<ea>,Rn none
#<data> none
#<data> none
#<data> none
#<data>,CCR
#<data>,CCR
<ea>,CCR
CCR,<ea>
#<data>,CCR
16
16 none none
16
16
32
32
32
32
8, 16, 32
16 none none
16
Privileged
Immediate Data
Λ
SR
→
SR
Immediate Data
⊕
SR
→
SR
State Frame
→
Internal Floating-Point Registers
Internal Floating-Point Registers
→
State Frame
Source
→
SR
SR
→
Destination
USP
→
An
An
→
USP
Rc
→
Rn
Rn
→
Rc
Rn
→
Destination Using DFC
Source Using SFC
→
Rn
Immediate Data V SR
→
SR
Assert Reset Output
(SP)
→
SR; SP + 2
→
SP; (SP)
→
PC; SP + 4
→
SP;
Restore Stack According to Format
Immediate Data
→
SR; STOP
Trap Generating none Run Breakpoint Cycle
16, 32
8, 16, 32 none none
If Dn < 0 or Dn > (<ea>), Then CHK Exception
If Rn< Lower Bound or Rn > Upper Bound,
Then CHK Exception
SSP – 2
→
SSP; Vector Offset
→
(SSP);
SSP – 4
→
SSP; PC
→
(SSP);
SSP – 2
→
SSP; SR
→
(SSP);
Illegal Instruction Vector Address
→
PC
SSP – 2
→
SSP; Format and Vector Offset
→
(SSP)
SSP – 4
→
SSP; PC
→
(SSP); SSP – 2
→
SSP;
SR
→
(SSP); Vector Address
→
PC
If cc True, Then Trap Exception none
16, 32 none
16, 32
If Floating-Point cc True, Then Trap Exception none If V, Then Take Overflow Trap Exception
Condition Code Register
8
8
16
16
8
Immediate Data
Λ
CCR
→
CCR
Immediate Data
⊕
CCR
→
CCR
Source
→
CCR
CCR
→
Destination
Immediate Data V CCR
→
CCR
Letters cc in the TRAPcc and FTRAPcc specify testing for a condition.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 3-13
Instruction Set Summary
3.1.10 Cache Control Instructions (MC68040)
The cache instructions provide maintenance functions for managing the instruction and data caches. CINV invalidates cache entries in both caches, and CPUSH pushes dirty data from the data cache to update memory. Both instructions can operate on either or both caches and can select a single cache line, all lines in a page, or the entire cache. Table 3-11 summarizes these instructions.
Instruction
CINVL
CINVP
CINVA
CPUSHL
CPUSHP
CPUSHA
Table 3-11. Cache Control Operation Format
Operand Syntax Operand Size caches,(An) none caches, (An) caches caches,(An) caches, (An) caches none none none none none
Operation
Invalidate cache line
Invalidate cache page
Invalidate entire cache
Push selected dirty data cache lines, then
invalidate selected cache lines
3.1.11 Multiprocessor Instructions
The TAS, CAS, and CAS2 instructions coordinate the operations of processors in multiprocessing systems. These instructions use read- modify-write bus cycles to ensure uninterrupted updating of memory. Coprocessor instructions control the coprocessor operations. Table 3- 12 summarizes these instructions.
Instruction
CAS
CAS2
TAS cpBcc cpDBcc cpGEN cpRESTORE cpSAVE cpScc cpTRAPcc
Table 3-12. Multiprocessor Operations
Operand Syntax
Dc,Du,<ea>
Operand Size Operation
Read-Write-Modify
8, 16, 32 Destination – Dc
→
CC
If Z, Then Du
→
Destination
Else Destination
→
Dc
16, 32 Dual Operand CAS Dc1–Dc2, Du1–Du2,
(Rn)–(Rn)
<ea> 8 Destination – 0; Set Condition Codes;
1
→
Destination [7]
<label>
<label>,Dn
User Defined
<ea>
<ea>
<ea> none
#<data>
Coprocessor
16, 32
16
User Defined none none
8 none
16, 32
If cpcc True, Then PC + d n
→
PC
If cpcc False, Then Dn – 1
→
Dn
If Dn
≠
–1, Then PC + d n
→
PC
Operand
→
Coprocessor
Restore Coprocessor State from <ea>
Save Coprocessor State at <ea>
If cpcc True, Then 1's
→
Destination;
Else 0's
→
Destination
If cpcc True, Then TRAPcc Exception
3-14 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Set Summary
3.1.12 Memory Management Unit (MMU) Instructions
The PFLUSH instructions flush the address translation caches (ATCs) and can optionally select only nonglobal entries for flushing. PTEST performs a search of the address translation tables, stores the results in the MMU status register, and loads the entry into the
ATC. Table 3-13 summarizes these instructions.
Table 3-13. MMU Operation Format
Instruction Processor
PBcc
PDBcc
MC68851
MC68851
Operand
Syntax
Operand
Size
<label>
Dn,<label> none none none none
Operation
Branch on PMMU Condition
Test, Decrement, and Branch
Invalidate All ATC Entries PFLUSHA
PFLUSH
PFLUSHN
MC68030
MC68040
MC68851
MC68040
MC68040
PFLUSHAN MC68040
PFLUSHS MC68851
PFLUSHR
PLOAD
MC68851
MC68030
MC68851
PMOVE MC68030
MC68851
PRESTORE MC68851
PSAVE
PScc
PTEST
PTRAPcc
MC68851
MC68851
MC68030
MC68040
MC68851
MC68851
(An)
(An) none none
<ea>
FC,<ea>
MRn,<ea>
<ea>,MRn
<ea>
<ea>
<ea>
(An)
8,16,32,64 Move to/from MMU Registers none none
8 none
PMMU Restore Function
PMMU Save Function
Set on PMMU Condition
Information About Logical Address
→
MMU Status Register
#<data> none none none none none none
16,32
Invalidate ATC Entries at Effective Address
Invalidate Nonglobal ATC Entries at Effective Address
Invalidate All Nonglobal ATC Entries
Invalidate All Shared/Global ATC Entries
Invalidate ATC and RPT Entries
Load an Entry into the ATC
Trap on PMMU Condition
3.1.13 Floating-Point Arithmetic Instructions
The following paragraphs describe the floating-point instructions, organized into two categories of operation: dyadic (requiring two operands) and monadic (requiring one operand).
The dyadic floating-point instructions provide several arithmetic functions that require two input operands, such as add and subtract. For these operations, the first operand can be located in memory, an integer data register, or a floating-point data register. The second operand is always located in a floating-point data register. The results of the operation store in the register specified as the second operand. All FPU operations support all data formats.
Results are rounded to either extended-, single-, or double-precision format. Table 3-14 gives the general format of dyadic instructions, and Table 3-15 lists the available operations.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 3-15
Instruction Set Summary
Instruction
F<dop>
Table 3-14. Dyadic Floating-Point Operation Format
Operand
Syntax
<ea>,FPn
FPm,FPn
Operand
Format
B, W, L, S, D, X, P
X
Operation
FPn <Function> Source
→
FPn
NOTE: < dop > is any one of the dyadic operation specifiers.
Table 3-15. Dyadic Floating-Point Operations
Instruction
FADD, FSADD, FDADD
FCMP
FDIV, FSDIV, FDDIV
FMOD
FMUL, FSMUL, FDMUL
FREM
FSCALE
FSUB, FSSUB, FDSUB
FSGLDIV, FSGLMUL
Operation
Add
Compare
Divide
Modulo Remainder
Multiply
IEEE Remainder
Scale Exponent
Subtract
Single-Precision Divide, Multiply
The monadic floating-point instructions provide several arithmetic functions requiring only one input operand. Unlike the integer counterparts to these functions (e.g., NEG < ea > ), a source and a destination can be specified. The operation is performed on the source operand and the result is stored in the destination, which is always a floating-point data register. When the source is not a floating-point data register, all data formats are supported.
The data format is always extended precision for register-to-register operations. Table 3-16 lists the general format of these instructions, and Table 3-17 lists the available operations.
Instruction
F<mop>
Table 3-16. Monadic Floating-Point Operation Format
Operand
Syntax
<ea>,FPn
FPm,FPn
FPn
Operand
Format
B, W, L, S, D, X, P
X
X
Operation
Source
→
Function
→
FPn
FPn
→
Function
→
FPn
NOTE: < mop > is any one of the monadic operation specifiers.
3-16 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Set Summary
Table 3-17. Monadic Floating-Point Operations
Instruction
FABS Absolute Value
Operation Instruction
FLOGN In(x)
Operation
FACOS
FASIN
FATAN
FCOS
Arc Cosine
Arc Sine
Hyperbolic Art Tangent
Cosine
FCOSH Hyperbolic Cosine
FETOX
FETOXM1 e x e x –
1
FGETEXP Extract Exponent
FGETMAN Extract Mantissa
FINT Extract Integer Part
FINTRZ Extract Integer Part, Rounded-to-Zero
FLOGNP1 In(x + 1)
FLOG10
FLOG2
FNEG
Log
10
(x)
Log
2
(x)
Negate
FSIN
FSINH
Sine
Hyperbolic Sine
FSQRT
FTAN
FTANH
FTENTOX
FTWOTOX
Square Root
Tangent
Hyperbolic Tangent
10 x
2 x
3.2 INTEGER UNIT CONDITION CODE COMPUTATION
Many integer instructions affect the CCR to indicate the instruction,s results. Program and system control instructions also use certain combinations of these bits to control program and system flow. The condition codes meet consistency criteria across instructions, uses, and instances. They also meet the criteria of meaningful results, where no change occurs unless it provides useful information. Refer to Section 1 Introduction for details concerning the CCR.
Table 3-18 lists the integer condition code computations for instructions and Table 3-19 lists the condition names, encodings, and tests for the conditional branch and set instructions.
The test associated with each condition is a logical formula using the current states of the condition codes. If this formula evaluates to one, the condition is true. If the formula evaluates to zero, the condition is false. For example, the T condition is always true, and the
EQ condition is true only if the Z-bit condition code is currently true.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 3-17
Instruction Set Summary
ABCD
ADD, ADDI, ADDQ
ADDX
Table 3-18. Integer Unit Condition Code Computations
Operations X N
* U
*
*
—
*
*
*
Z
?
*
?
*
V C
U
?
?
0
Special Definition
?
C = Decimal Carry
Z = Z
Λ
Rm
Λ
…
Λ
R0
?
V = Sm
Λ
Dm
Λ
Rm V Sm
Λ
Dm
Λ
Rm
C = Sm
Λ
Dm V Rm
Λ
Dm V Sm
Λ
Rm
?
V = Sm
Λ
Dm
Λ
Rm V Sm
Λ
Dm
Λ
Rm
C = Sm
Λ
Dm V Rm
Λ
Dm V Sm
Λ
Rm
Z = Z
Λ
Rm
Λ
…
Λ
R0
0 AND, ANDI, EOR, EORI,
MOVEQ, MOVE, OR, ORI,
CLR, EXT, EXTB, NOT, TAS, TST
CHK
CHK2, CMP2
—
—
*
U
U
?
U
U
SUB, SUBI, SUBQ
SUBX
CAS, CAS2, CMP, CMPA, CMPI,
CMPM
DIVS, DUVU
MULS, MULU
SBCD, NBCD
NEG
NEGX
*
*
—
—
—
*
*
*
BTST, BCHG, BSET, BCLR —
BFTST, BFCHG, BFSET, BFCLR —
BFEXTS, BFEXTU, BFFFO
BFINS
ASL
ASL (r = 0)
LSL, ROXL
—
—
*
—
*
*
*
*
*
*
U
*
*
—
?
?
?
*
*
*
*
?
*
*
*
?
*
?
?
?
?
?
*
*
*
?
?
?
?
?
U
?
?
—
0
0
0
?
0
0
U
?
Z = (R = LB) V (R = UB)
C = (LB
≤
UB)
Λ
(IR < LB) V (R > UB))
V (UB < LB)
Λ
(R > UB)
Λ
(R < LB)
?
V = Sm
Λ
Dm
Λ
Rm V Sm
Λ
Dm
Λ
Rm
C = Sm
Λ
Dm V Rm
Λ
Dm V Sm
Λ
Rm
?
V = Sm
Λ
Dm
Λ
Rm V Sm
Λ
Dm
Λ
Rm
C = Sm
Λ
Dm V Rm
Λ
Dm V Sm
Λ
Rm
Z = Z
Λ
Rm
Λ
…
Λ
R0
?
V = Sm
Λ
Dm
Λ
Rm V Sm
Λ
Dm
Λ
Rm
C = Sm
Λ
Dm V Rm
Λ
Dm V Sm
Λ
Rm
0 V = Division Overflow
0 V = Multiplication Overflow
?
C = Decimal Borrow
Z = Z Λ Rm
Λ
…
Λ
R0
?
V = Dm
Λ
Rm
C = Dm V Rm
?
V = Dm
Λ
Rm
C = Dm V Rm
Z = Z
Λ
Rm
Λ
…
Λ
R0
— Z = Dn
0 N = Dm
Z = Dn
Λ
Dm–1
Λ
…
Λ
D0
0 N = Sm
Z = Sm
Λ
Sm–1
Λ
…
Λ
S0
0 N = Dm
Z = Dm
Λ
Dm–1
Λ
…
Λ
D0
?
V = Dm
Λ
Dm–1 V … V Dm– r V Dm
Λ
(DM –1 V …+ Dm – r)
C = Dm– r+1
0
?
C = Dm – r + 1
3-18 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Set Summary
Table 3-18. Integer Unit Condition Code Computations (Continued)
Operations
LSR (r = 0)
ROXL (r = 0)
ROL
ROL (r = 0)
ASR, LSR, ROXR
ASR, LSR (r = 0)
ROXR (r = 0)
ROR
ROR (r = 0)
X N
— *
—
—
—
—
—
—
—
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Z
*
0
0
0
0
0
0
0
0
V C
0 0
?
X = C
?
C = Dm – r + 1
0
?
C = Dr – 1
0
?
X = C
?
C = Dr – 1
0
Special Definition
? = Other—See Special Definition
N = Result Operand (MSB)
Z = Rm
Λ
…
Λ
R0
Sm = Source Operand (MSB)
Dm = Destination Operand (MSB)
Rm = Result Operand (MSB)
Rm = Not Result Operand (MSB)
R = Register Tested r = Shift Count
Mnemonic
T *
F *
HI
LS
CC(HI)
CS(LO)
NE
EQ
VC
VS
PL
MI
GE
LT
GT
LE
Table 3-19. Conditional Tests
Condition
True
False
High
Low or Same
Carry Clear
Carry Set
Not Equal
Equal
Overflow Clear
Overflow Set
Plus
Minus
Greater or Equal
Less Than
Greater Than
Less or Equal
Encoding
0000
0001
1001
1010
1011
1100
1101
1110
1111
0010
0011
0100
0101
0110
0111
1000
Test
1
0
C
Λ
Z
C V Z
C
Z
V
C
Z
V
N
N
N Λ V V N
Λ
V
N
Λ
V V N
Λ
V
N
Λ
V
Λ
Z V N
Λ
V
Λ
Z
Z V N
Λ
V V N
Λ
V
NOTES:
N = Logical Not N
V = Logical Not V
Z = Logical Not Z
*Not available for the Bcc instruction.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 3-19
Instruction Set Summary
3.3 INSTRUCTION EXAMPLES
The following paragraphs provide examples of how to use selected instructions.
3.3.1 Using the Cas and Cas2 Instructions
The CAS instruction compares the value in a memory location with the value in a data register, and copies a second data register into the memory location if the compared values are equal. This provides a means of updating system counters, history information, and globally shared pointers. The instruction uses an indivisible read-modify- write cycle. After
CAS reads the memory location, no other instruction can change that location before CAS has written the new value. This provides security in single-processor systems, in multitasking environments, and in multiprocessor environments. In a single-processor system, the operation is protected from instructions of an interrupt routine. In a multitasking environment, no other task can interfere with writing the new value of a system variable. In a multiprocessor environment, the other processors must wait until the CAS instruction completes before accessing a global pointer.
3.3.2 Using the Moves Instruction
This instruction moves the byte, word, or long-word operand from the specified general register to a location within the address space specified by the destination function code
(DFC) register. It also moves the byte, word, or long-word operand from a location within the address space specified by the source function code (SFC) register to the specified general register.
3.3.3 Nested Subroutine Calls
The LINK instruction pushes an address onto the stack, saves the stack address at which the address is stored, and reserves an area of the stack. Using this instruction in a series of subroutine calls results in a linked list of stack frames.
The UNLK instruction removes a stack frame from the end of the list by loading an address into the stack pointer and pulling the value at that address from the stack. When the operand of the instruction is the address of the link address at the bottom of a stack frame, the effect is to remove the stack frame from the stack and from the linked list.
3.3.4 Bit Field Instructions
One of the data types provided by the MC68030 is the bit field, consisting of as many as 32 consecutive bits. An offset from an effective address and a width value defines a bit field.
The offset is a value in the range of – 231 through 231 – 1 from the most significant bit (bit
7) at the effective address. The width is a positive number, 1 through 32. The most significant bit of a bit field is bit 0. The bits number in a direction opposite to the bits of an integer.
The instruction set includes eight instructions that have bit field operands. The insert bit field
(BFINS) instruction inserts a bit field stored in a register into a bit field. The extract bit field signed (BFEXTS) instruction loads a bit field into the least significant bits of a register and
3-20 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Set Summary extends the sign to the left, filling the register. The extract bit field unsigned (BFEXTU) also loads a bit field, but zero fills the unused portion of the destination register.
The set bit field (BFSET) instruction sets all the bits of a field to ones. The clear bit field
(BFCLR) instruction clears a field. The change bit field (BFCHG) instruction complements all the bits in a bit field. These three instructions all test the previous value of the bit field, setting the condition codes accordingly. The test bit field (BFTST) instruction tests the value in the field, setting the condition codes appropriately without altering the bit field. The find first one in bit field (BFFFO) instruction scans a bit field from bit 0 to the right until it finds a bit set to one and loads the bit offset of the first set bit into the specified data register. If no bits in the field are set, the field offset and the field width is loaded into the register.
An important application of bit field instructions is the manipulation of the exponent field in a floating-point number. In the IEEE standard format, the most significant bit is the sign bit of the mantissa. The exponent value begins at the next most significant bit position; the exponent field does not begin on a byte boundary. The extract bit field (BFEXTU) instruction and the BFTST instruction are the most useful for this application, but other bit field instructions can also be used.
Programming of input and output operations to peripherals requires testing, setting, and inserting of bit fields in the control registers of the peripherals. This is another application for bit field instructions. However, control register locations are not memory locations; therefore, it is not always possible to insert or extract bit fields of a register without affecting other fields within the register.
Another widely used application for bit field instructions is bit- mapped graphics. Because byte boundaries are ignored in these areas of memory, the field definitions used with bit field instructions are very helpful.
3.3.5 Pipeline Synchronization with the Nop Instruction
Although the no operation (NOP) instruction performs no visible operation, it serves an important purpose. It forces synchronization of the integer unit pipeline by waiting for all pending bus cycles to complete. All previous integer instructions and floating-point external operand accesses complete execution before the NOP begins. The NOP instruction does not synchronize the FPU pipeline—floating- point instructions with floating-point register operand destinations can be executing when the NOP begins. NOP is considered a change of flow instruction and traps for trace on change of flow. A single- cycle nonsynchronizing operation can be affected with the TRAPF instruction.
3.4 FLOATING-POINT INSTRUCTION DETAILS
The following paragraphs describe the operation tables used in the instruction descriptions and the conditional tests that can be used to change program flow based on floating-point conditions. Details on NANs and floating-point condition codes are also discussed. The
IEEE 754 standard specifies that each data format must support add, subtract, multiply, divide, remainder, square root, integer part, and compare. In addition to these arithmetic
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 3-21
Instruction Set Summary functions, software supports remainder and integer part; the FPU also supports the nontranscendental operations of absolute value, negate, and test.
Most floating-point instruction descriptions include an operation table. This table lists the resulting data types for the instruction based on the operand,s input. Table 3-20 is an operation table example for the FADD instruction. The operation table lists the source operand type along the top, and the destination operand type along the side. In-range numbers are normalized, denormalized, unnormalized real numbers, or integers that are converted to normalized or denormalized extended-precision numbers upon entering the
FPU.
Table 3-20. Operation Table Example (FADD Instruction)
DESTINATION
In Range
+
+
ADD
–
Zero +
–
ADD
– –inf
In Range
SOURCE
1
– + Zero –
ADD
+ 0.0
0.0
2
+inf
–inf
+ Infinity –
+inf –inf
0.0
2 +inf –inf
–0.0
+inf NAN 3
NAN 3 –inf
NOTES:
1.If either operand is a NAN, refer to 1.6.5 NANs for more information.
2.Returns +0.0 in rounding modes RN, RZ, and RP; returns –0.0 in RM.
3.Sets the OPERR bit in the FPSR exception byte.
For example, Table 3-20 illustrates that if both the source and destination operand are positive zero, the result is also a positive zero. If the source operand is a positive zero and the destination operand is an in-range number, then the ADD algorithm is executed to obtain the result. If a label such as ADD appears in the table, it indicates that the FPU performs the indicated operation and returns the correct result. Since the result of such an operation is undefined, a NAN is returned as the result, and the OPERR bit is set in the FPSR EXC byte.
In addition to the data types covered in the operation tables for each floating-point instruction, NANs can also be used as inputs to an arithmetic operation. The operation tables do not contain a row and column for NANs because NANs are handled the same way for all operations. If either operand, but not both operands, of an operation is a nonsignaling
NAN, then that NAN is returned as the result. If both operands are nonsignaling NANs, then the destination operand nonsignaling NAN is returned as the result.
If either operand to an operation is a signaling NAN (SNAN), then the SNAN bit is set in the
FPSR EXC byte. If the SNAN exception enable bit is set in the FPCR ENABLE byte, then the exception is taken and the destination is not modified. If the SNAN exception enable bit is not set, setting the SNAN bit in the operand to a one converts the SNAN to a nonsignaling
NAN. The operation then continues as described in the preceding paragraph for nonsignaling NANs.
3-22 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Set Summary
3.5 FLOATING-POINT COMPUTATIONAL ACCURACY
Representing a real number in a binary format of finite precision is problematic. If the number cannot be represented exactly, a round-off error occurs. Furthermore, when two of these inexact numbers are used in a calculation, the result becomes even more inexact. The
IEEE 754 standard defines the error bounds for calculating binary floating-point values so that the result obtained by any conforming device can be predicted exactly for a particular precision and rounding mode. The error bound defined by the IEEE 754 standard is one-half unit in the last place of the destination data format in the RN mode, and one unit in last place in the other rounding modes. The operation’s data format must have the same input values, rounding mode, and precision. The standard also specifies the maximum allowable error that can be introduced during a calculation and the manner in which rounding of the result is performed.
The single- and double-precision formats provide emulation for devices that only support those precisions. The execution speed of all instructions is the same whether using singleor double-precision rounding. When using these two data formats, the FPU produces the same results as any other device that conforms to the IEEE standard but does not support extended precision. The results are the same when performing the same operation in extended precision and storing the results in single- or double-precision format.
The FPU performs all floating-point internal operations in extended-precision. It supports mixed-mode arithmetic by converting single- and double-precision operands to extendedprecision values before performing the specified operation. The FPU converts all memory data formats to the extended-precision data format and stores the value in a floating-point register or uses it as the source operand for an arithmetic operation. The FPU also converts extended-precision data formats in a floating-point data register to any data format and either stores it in a memory destination or in an integer data register.
Additionally if the external operand is a denormalized number, the number is normalized before an operation is performed. However, an external denormalized number moved into a floating-point data register is stored as a denormalized number. The number is first normalized and then denormalized before it is stored in the designated floating-point data register. This method simplifies the handling of all other data formats and types.
If an external operand is an unnormalized number, the number is normalized before it is used in an arithmetic operation. If the external operand is an unnormalized zero (i.e., with a mantissa of all zeros), the number is converted to a normalized zero before the specified operation is performed. The regular use of unnormalized inputs not only defeats the purpose of the IEEE 754 standard, but also can produce gross inaccuracies in the results.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 3-23
Instruction Set Summary
3.5.1 Intermediate Result
All FPU calculations use an intermediate result. When the FPU performs any operation, the calculation is carried out using extended-precision inputs, and the intermediate result is calculated as if to produce infinite precision. After the calculation is complete, the intermediate result is rounded to the selected precision and stored in the destination.
Figure 3-1 illustrates the intermediate result format. The intermediate result’s exponent for some dyadic operations (i.e., multiply and divide) can easily overflow or underflow the 15bit exponent of the designation floating-point register. To simplify the overflow and underflow detection, intermediate results in the FPU maintain a 16-bit (17 bits for the MC68881 and
MC68882), twos complement, integer exponent. Detection of an overflow or underflow intermediate result always converts the 16-bit exponent into a 15-bit biased exponent before being stored in a floating-point data register. The FPU internally maintains the 67-bit mantissa for rounding purposes. The mantissa is always rounded to 64 bits (or less, depending on the selected rounding precision) before it is stored in a floating-point data register.
.
16-BIT EXPONENT 63-BIT MANTISSA
INTEGER BIT
OVERFLOW BIT
LSB OF FRACTION
GUARD BIT
ROUND BIT
STICKY BIT
Figure 3-1. Intermediate Result Format
If the destination is a floating-point data register, the result is in the extended-precision format and is rounded to the precision specified by the FPSR PREC bits before being stored.
All mantissa bits beyond the selected precision are zero. If the single- or double-precision mode is selected, the exponent value is in the correct range even if it is stored in extendedprecision format. If the destination is a memory location, the FPSR PREC bits are ignored.
In this case, a number in the extended-precision format is taken from the source floatingpoint data register, rounded to the destination format precision, and then written to memory.
Depending on the selected rounding mode or destination data format in effect, the location of the least significant bit of the mantissa and the locations of the guard, round, and sticky bits in the 67-bit intermediate result mantissa varies. The guard and round bits are always calculated exactly. The sticky bit is used to create the illusion of an infinitely wide intermediate result. As the arrow illustrates in Figure 3-1, the sticky bit is the logical OR of all the bits in the infinitely precise result to the right of the round bit. During the calculation stage of an arithmetic operation, any non-zero bits generated that are to the right of the round bit set the sticky bit to one. Because of the sticky bit, the rounded intermediate result for all required IEEE arithmetic operations in the RN mode is in error by no more than one half unit in the last place.
3-24 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Set Summary
3.5.2 Rounding the Result
The FPU supports the four rounding modes specified by the IEEE 754 standard. These modes are round to nearest (RN), round toward zero (RZ), round toward plus infinity (RP), and round toward minus infinity (RM). The RM and RP rounding modes are often referred to as "directed rounding modes" and are useful in interval arithmetic. Rounding is accomplished through the intermediate result. Single-precision results are rounded to a 24bit boundary; double-precision results are rounded to a 53-bit boundary; and extendedprecision results are rounded to a 64-bit boundary. Table 3-21 lists the encodings for the
FPCR that denote the rounding and precision modes.
Table 3-21. FPCR Encodings
Rounding Mode
(RND Field)
To Nearest (RN)
To Zero (RZ)
To Minus Infinity (RM)
To Plus Infinity (RP)
Encoding
1
1
0
0
0
1
0
1
Rounding Precision
(PREC Field)
Extend (X)
Single (S)
Double (D)
Undefined
Rounding the intermediate result’s mantissa to the specified precision and checking the 16bit intermediate exponent to ensure that it is within the representable range of the selected rounding precision accomplishes range control. Range control is a method used to assure correct emulation of a device that only supports single- or double- precision arithmetic. If the intermediate result’s exponent exceeds the range of the selected precision, the exponent value appropriate for an underflow or overflow is stored as the result in the 16-bit extendedprecision format exponent. For example, if the data format and rounding mode is single precision RM and the result of an arithmetic operation overflows the magnitude of the singleprecision format, the largest normalized single-precision value is stored as an extendedprecision number in the destination floating-point data register (i.e., an unbiased 15-bit exponent of $00FF and a mantissa of $FFFFFF0000000000). If an infinity is the appropriate result for an underflow or overflow, the infinity value for the destination data format is stored as the result (i.e., an exponent with the maximum value and a mantissa of zero).
Figure 3-2 illustrates the algorithm that the FPU uses to round an intermediate result to the selected rounding precision and destination data format. If the destination is a floating-point register, either the selected rounding precision specified by the FPCR PREC status byte or by the instruction itself determines the rounding boundary. For example, FSADD and
FDADD specify single- and double-precision rounding regardless of the precision specified in the FPCR PREC status byte. If the destination is external memory or an integer data register, the destination data format determines the rounding boundary. If the rounded result of an operation is not exact, then the INEX2 bit is set in the FPSR EXC status byte.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 3-25
Instruction Set Summary
.
ENTRY
GUARD, ROUND,
AND STICKY BITS = 0
INEX2 ➧ 1
SELECT ROUNDING MODE
RN RM
POS
RP
NEG POS NEG
GUARD AND LSB = 1,
ROUND AND STICKY = 0
OR
GUARD = 1
ROUND OR STICKY = 1
INTERMEDIATE
RESULT
INTERMEDIATE
RESULT
ADD 1 TO
LSB
ADD 1 TO
LSB
RZ
GUARD, ROUND,
AND STICKY ARE
CHOPPED
EXACT RESULT
OVERFLOW = 1
SHIFT MANTISSA
RIGHT 1 BIT,
ADD 1 TO EXPONENT
GUARD ➧ 0
ROUND ➧ 0
STICKY ➧ 0
EXIT EXIT
Figure 3-2. Rounding Algorithm Flowchart
The three additional bits beyond the extended-precision format, the difference between the intermediate result’s 67-bit mantissa and the storing result’s 64-bit mantissa, allow the FPU to perform all calculations as though it were performing calculations using a float engine with infinite bit prec The result is always correct for the specified destination’s data format before performing rounding (unless an overflow or underflow error occurs). The specified rounding operation then produces a number that is as close as possible to the infinitely precise
3-26 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Set Summary intermediate value and still representable in the The following tie-case example shows how the 67-bit mantissa allows the FPU to meet the error bound of the IEEE specification:
Result
Intermediate
Rounded-to-Nearest
Integer x x
63-Bit Fraction xxx…x00 xxx…x00
Guard Round Sticky
1 0 0
0 0 0
The LSB of the rounded result does not increment though the guard bit is set in the intermediate result. The IEEE 754 standard specifies that tie cases should be handled in this manner. If the destination data format is extended and there is a difference between the infinitely precise intermediate result and the round-to-nearest result, the relative difference is 2 – 64 (the value of the guard bit). This error is equal to half of the least significant bit’s value and is the worst case error that can be introduced when using the RN mode. Thus, the term one-half unit in the last place correctly identifies the error bound for this operation. This error specification is the relative error present in the result; the absolute error bound is equal to 2exponent x 2 – 64. The following example shows the error bound for the other rounding modes:
Result
Intermediate
Rounded-to-Nearest
Integer x x
63-Bit Fraction xxx…x00 xxx…x00
Guard Round Sticky
1 1 1
0 0 0
The difference between the infinitely precise result and the rounded result is 2 – 64 + 2 – 65
+ 2 – 66, which is slightly less than 2 – 63 (the value of the LSB). Thus, the error bound for this operation is not more than one unit in the last place. For all arithmetic operations, the
FPU meets these error bounds, providing accurate and repeatable results.
3.6 FLOATING-POINT POSTPROCESSING
Most operations end with a postprocessing step. The FPU provides two steps in postprocessing. First, the condition code bits in the FPSR are set or cleared at the end of each arithmetic operation or move operation to a single floating-point data register. The condition code bits are consistently set based on the result of the operation. Second, the
FPU supports 32 conditional tests that allow floating-point conditional instructions to test floating-point conditions in exactly the same way as the integer conditional instructions test the integer condition code The combination of consistently set condition code bits and the simple programming of conditional instructions gives the processor a very flexible, highperformance method of altering program flow based on floating-point results. While reading the summary for each instruction, it should be assumed that an instruction performs postprocessing unless the summary specifically states that the instruction does not do so.
The following paragraphs describe postprocessing in detail.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 3-27
Instruction Set Summary
3.6.1 Underflow, Round, Overflow
During the calculation of an arithmetic result, the FPU arithmetic logic unit (ALU) has more precision and range than the 80-bit extended precision format. However, the final result of these operations is an extended-precision floating-point value. In some cases, an intermediate result becomes either smaller or larger than can be represented in extended precision. Also, the operation can generate a larger exponent or more bits of precision than can be represented in the chosen rounding precision. For these reasons, every arithmetic instruction ends by rounding the result and checking for overflow and underflow.
At the completion of an arithmetic operation, the intermediate result is checked to see if it is too small to be represented as a normalized number in the selected precision. If so, the underflow (UNFL) bit is set in the FPSR EXC byte. It is also denormalized unless denormalization provides a zero value. Denormalizing a number causes a loss of accuracy, but a zero is not returned unless absolutely necessary. If a number is grossly underflowed, the FPU returns a zero or the smallest denormalized number with the correct sign, depending on the rounding mode in effect.
If no underflow occurs, the intermediate result is rounded according to the user-selected rounding precision and rounding mode. After rounding, the inexact bit (INEX2) is set appropriately. Lastly, the magnitude of the result is checked to see if it is too large to be represented in the current rounding precision. If so, the overflow (OVFL) bit is set and a correctly signed infinity or correctly signed largest normalized number is returned, depending on the rounding mode in effect.
3.6.2 Conditional Testing
Unlike the integer arithmetic condition codes, an instruction either always sets the floatingpoint condition codes in the same way or it does not change them at all. Therefore, the instruction descriptions do not include floating-point condition code settings. The following paragraphs describe how floating-point condition codes are set for all instructions that modify condition codes.
The condition code bits differ slightly from the integer condition codes. Unlike the operation type dependent integer condition codes, examining the result at the end of the operation sets or clears the floating-point condition codes accordingly. The M68000 family integer condition codes bits N and Z have this characteristic, but the V and C bits are set differently for different instructions. The data type of the operation’s result determines how the four condition code bits are set. Table 3-22 lists the condition code bit setting for each data type.
Loading the FPCC with one of the other combinations and executing a conditional instruction can produce an unexpected branch condition.
3-28 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Set Summary
Table 3-22. FPCC Encodings
Data Type
+ Normalized or Denormalized
– Normalized or Denormalized
+ 0
– 0
+ Infinity
– Infinity
+ NAN
– NAN
1
0
1
1
0
1
0
N
0
0
0
0
1
0
0
1
Z
0
1
0
0
0
1
0
0
I
0
NAN
0
0
1
1
0
0
0
0
The inclusion of the NAN data type in the IEEE floating-point number system requires each conditional test to include the NAN condition code bit in its Boolean equation. Because a comparison of a NAN with any other data type is unordered (i.e., it is impossible to determine if a NAN is bigger or smaller than an in-range number), the compare instruction sets the
NAN condition code bit when an unordered compare is attempted. All arithmetic instructions also set the NAN bit if the result of an operation is a NAN. The conditional instructions interpret the NAN condition code bit equal to one as the unordered condition.
The IEEE 754 standard defines four conditions: equal to (EQ), greater than (GT), less than
(LT), and unordered (UN). In addition, the standard only requires the generation of the condition codes as a result of a floating-point compare operation. The FPU can test these conditions at the end of any operation affecting the condition codes. For purposes of the floating-point conditional branch, set byte on condition, decrement and branch on condition, and trap on condition instructions, the processor logically combines the four FPCC condition codes to form 32 conditional tests. There are three main categories of conditional tests:
IEEE nonaware tests, IEEE aware tests, and miscellaneous. The set of IEEE nonaware tests is best used:
• when porting a program from a system that does not support the IEEE standard to a conforming system, or
• when generating high-level language code that does not support IEEE floating-point concepts (i.e., the unordered condition).
The 32 conditional tests are separated into two groups; 16 that cause an exception if an unordered condition is present when the conditional test is attempted and 16 that do not cause an exception. An unordered condition occurs when one or both of the operands in a floating-point compare operation The inclusion of the unordered condition in floating-point branches destroys the familiar trichotomy relationship (greater than, equal, less than) that exists for integers. For example, the opposite of floating-point branch greater than (FBGT) is not floating-point branch less than or equal (FBLE). Rather, the opposite condition is floating-point branch not greater than (FBNGT). If the result of the previous instruction was unordered, FBNGT is true; whereas, both FBGT and FBLE would be false since unordered fails both of these tests (and sets BSUN). Compiler programmers should be particularly careful of the lack of trichotomy in the floating-point branches since it is common for compilers to invert the sense of conditions.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 3-29
Instruction Set Summary
When using the IEEE nonaware tests, the user receives a BSUN exception whenever a branch is attempted and the NAN condition code bit is set, unless the branch is an FBEQ or an FBNE. If the BSUN exception is enabled in the FPCR, the exception causes another exception. Therefore, the IEEE nonaware program is interrupted if an unexpected condition occurs. Compilers and programmers who are knowledgeable of the IEEE 754 standard should use the IEEE aware tests in programs that contain ordered and unordered conditions. Since the ordered or unordered attribute is explicitly included in the conditional test, the BSUN bit is not set in the FPSR EXC byte when the unordered condition occurs.
Table 3-23 summarizes the conditional mnemonics, definitions, equations, predicates, and whether the BSUN bit is set in the FPSR EXC byte for the 32 floating-point conditional tests.
The equation column lists the combination of FPCC bits for each test in the form of an equation. All condition codes with an overbar indicate cleared bits; all other bits are set.
3-30 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Set Summary
Table 3-23. Floating-Point Conditional Tests
Predicate
NLT
LE
NLE
GL
NGL
GLE
NGLE
EQ
NE
GT
NGT
GE
NGE
LT
UGE
OLE
UGT
OGL
UEQ
OR
UN
EQ
NE
OGT
ULE
OGE
ULT
OLT
Mnemonic
F
T
SF
ST
SEQ
SNE
Definition
Not Less Than
Less Than or Equal
Not Less Than or Equal
Greater or Less Than
Equation
IEEE Nonaware Tests
Z Equal
Not Equal
Greater Than
Not Greater Than
Greater Than or Equal
Not Greater Than or Equal
Less Than
Not Greater or Less Than
Greater, Less or Equal
Z
NAN V Z V N
NAN V Z V N
Z V (NAN V N)
NAN V (N
Λ
Z)
N
Λ
(NAN V Z)
NAN V (Z V N)
Z V (N
Λ
NAN)
NAN V (N V Z)
NAN V Z
NAN V Z
NAN
Not Greater, Less or Equal NAN
IEEE Aware Tests
Equal Z
Not Equal
Ordered Greater Than
Z
NAN V Z V N
Unordered or Less or Equal
Ordered Greater Than or Equal Z V (NAN V N)
Unordered or Less Than
Ordered Less Than
NAN V (N
Λ
Z)
N
Λ
(NAN V Z)
Unordered or Greater or Equal
Ordered Less Than or Equal
Unordered or Greater Than
NAN V Z V N
Z V (N
Λ
NAN)
NAN V (N V Z)
Ordered Greater or Less Than
Unordered or Equal
Ordered
NAN V Z V N
NAN V
NAN
Z
NAN V Z
Unordered NAN
Miscellaneous Tests
False False
True
Signaling False
Signaling True
Signaling Equal
Signaling Not Equal
True
False
True
Z
Z
000000
001111
010000
011111
010001
011110
000001
001110
010010
011101
010011
011100
010100
011011
010101
011010
010110
011001
010111
011000
000001
001110
000010
001101
000011
001100
000100
001011
000101
001010
000110
001001
000111
001000
BSUN Bit Set
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 3-31
Instruction Set Summary
3.7 INSTRUCTION DESCRIPTIONS
Section 4, 5, 6, and 7 contain detailed information about each instruction in the M68000 family instruction set. Each section arranges the instruction in alphabetical order by instruction mnemonic and includes descriptions of the instruction’s notation and format.
Figure 3-3 illustrates the format of the instruction descriptions. Note that the illustration is an amalgamation of the various parts that make up an instruction description. Instruction descriptions for the integer unit differ slightly from those for the floating-point unit; i.e. there are no operation tables included for integer unit instruction descriptions.
The size attribute line specifies the size of the operands of an instruction. When an instruction uses operands of more than one size, the mnemonic of the instruction includes a suffix such as:
.B—Byte Operands
.W—Word Operands
.L—Long-Word Operands
.S—Single-Precision Real Operands
.D—Double-Precision Real Operands
.X—Extended-Precision Real Operands
.P—Packed BCD Real Operands
The instruction format specifies the bit pattern and fields of the operation and command words, and any other words that are always part of the instruction. The effective address extensions are not explicitly illustrated. The extension words, if any, follow immediately after the illustrated portions of the instructions.
3-32 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Set Summary
INSTRUCTION NAME
APPLICABLE PROCESSORS
OPERATION DESCRIPTION
INSTRUCTION'S ASSEMBLER SYNTAX
SIZE ATRIBUTE
TEXT DESCRIPTION OF INSTRUCTION OPERATION
APPLICABLE RESULT OF FLOATING-POINT OPERATION
.
EFFECTS ON INTEGER CONDITION CODES
OR FLOATING-POINT STATUS REGISTER
INSTRUCTION FORMAT
DEFINITIONS AND ALLOWED VALUES FOR THE
INSTRUCTION FORMAT FIELDS
ABCD
Operation:
Assembler
System:
Add Decimal with Ex
(MC68020, MC68030,
Absolute value of s
FABSxfm tx <ee
FABSX FPm
FABSX FPn
Attributes:
Description:
Forms = (Byte, Word,
Converts the source o absolute value of that
Operation Table:
Destination Sourc
Result A
NOTE: If the source operation
Status Register:
Condition Codes:
Quotient Byte:
Exception Byte:
Affected by
Not Affected
BSUN
SNAN
OPERR
OVRL
Accrued Exception Byte:
Instruction Format:
15 14 13 12 11 10
0
1
1
0
1
0
1 1
SOURCE
SPECIFIER
Instruction Fields:
Effective Address Field - Determines
Figure 3-3. Instruction Description Format
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 3-33
SECTION 4
INTEGER INSTRUCTIONS
This section contains detailed information about the integer instructions for the M68000 family. A detailed discussion of each instruction description is arranged in alphabetical order by instruction mnemonic.
Each instruction description identifies the differences among the M68000 family for that instruction. Noted under the title of the instruction are all specific processors that apply to that instruction—for example:
Test Bit Field and Change
(MC68030, MC68040)
The MC68HC000 is identical to the MC68000 except for power dissipation; therefore, all instructions that apply to the MC68000 also apply to the MC68HC000. All references to the
MC68000, MC68020, and MC68030 include references to the corresponding embedded controllers, MC68EC000, MC68EC020, and MC68EC030. All references to the MC68040 include the MC68LC040 and MC68EC040. This referencing applies throughout this section unless otherwise specified.
Identified within the paragraphs are the specific processors that use different instruction fields, instruction formats, etc.—for example:
MC68020, MC68030, and MC68040 only
(bd,An,Xn) 110 reg. number:An
**Can be used with CPU32 processor
(bd,PC,Xn)** 111 011
Appendix A Processor Instruction Summary provides a listing of all processors and the instructions that apply to them for quick reference.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-1
Integer Instructions
ABCD
Operation:
Assembler
Syntax:
Attributes:
Add Decimal with Extend
(M68000 Family)
Source10 + Destination10 + X
→
Destination
ABCD Dy,Dx
ABCD – (Ay), – (Ax)
ABCD
Size = (Byte)
Description: Adds the source operand to the destination operand along with the extend bit, and stores the result in the destination location. The addition is performed using binarycoded decimal arithmetic. The operands, which are packed binary-coded decimal numbers, can be addressed in two different ways:
1. Data Register to Data Register: The operands are contained in the data registers specified in the instruction.
2. Memory to Memory: The operands are addressed with the predecrement addressing mode using the address registers specified in the instruction.
This operation is a byte operation only.
Condition Codes:
X
*
N
U
Z
*
V
U
C
*
X — Set the same as the carry bit.
N — Undefined.
Z — Cleared if the result is nonzero; unchanged otherwise.
V — Undefined.
C — Set if a decimal carry was generated; cleared otherwise.
NOTE
Normally, the Z condition code bit is set via programming before the start of an operation. This allows successful tests for zero results upon completion of multiple-precision operations.
4-2 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
ABCD
Add Decimal with Extend
(M68000 Family)
Instruction Format:
15
1
14
1
13
0
12
0
11 10
REGISTER Rx
9 8
1
7
0
6
0
5
0
Integer Instructions
ABCD
4
0
3
R/M
2 1
REGISTER Ry
0
Instruction Fields:
Register Rx field—Specifies the destination register.
If R/M = 0, specifies a data register.
If R/M = 1, specifies an address register for the predecrement addressing mode.
R/M field—Specifies the operand addressing mode.
0 — The operation is data register to data register.
1 — The operation is memory to memory.
Register Ry field—Specifies the source register.
If R/M = 0, specifies a data register.
If R/M = 1, specifies an address register for the predecrement addressing mode.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-3
Integer Instructions
ADD
Operation:
Assembler
Syntax:
Attributes:
Source + Destination
→
Destination
ADD < ea > ,Dn
ADD Dn, < ea >
Add
(M68000 Family)
ADD
Size = (Byte, Word, Long)
Description: Adds the source operand to the destination operand using binary addition and stores the result in the destination location. The size of the operation may be specified as byte, word, or long. The mode of the instruction indicates which operand is the source and which is the destination, as well as the operand size.
Condition Codes:
X
∗
N
∗
Z
∗
V
∗
C
∗
X — Set the same as the carry bit.
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if an overflow is generated; cleared otherwise.
C — Set if a carry is generated; cleared otherwise.
Instruction Format:
15
1
14
1
13
0
12
1
11 10
REGISTER
9 8 7
OPMODE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
4-4 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
ADD
Add
(M68000 Family)
Instruction Fields:
Register field—Specifies any of the eight data registers.
Opmode field
Integer Instructions
ADD
Byte
000
100
Word
001
101
Long
010
110
Operation
< ea > + Dn
→
Dn
Dn + < ea >
→
< ea >
Effective Address field—Determines addressing mode. a. If the location specified is a source operand, all addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An*
000
001
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
MC68020, MC68030, and MC68040 only
(bd,An,Xn)**
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Word and long only
**Can be used with CPU32.
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)†
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
Register
000
001
100
010
011
011
011
011
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-5
Integer Instructions
ADD
Add
(M68000 Family) b. If the location specified is a destination operand, only memory alterable addressing modes can be used as listed in the following tables:
ADD
Addressing Mode Mode
Dn
An
—
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register
—
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
NOTE
The Dn mode is used when the destination is a data register; the destination < ea > mode is invalid for a data register.
ADDA is used when the destination is an address register. ADDI and ADDQ are used when the source is immediate data. Most assemblers automatically make this distinction.
Register
000
001
—
—
—
—
—
—
4-6 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
ADDA
Add Address
(M68000 Family)
Source + Destination
→
Destination
ADDA
Operation:
Assembler
Syntax:
Attributes:
ADDA < ea > , An
Size = (Word, Long)
Description: Adds the source operand to the destination address register and stores the result in the address register. The size of the operation may be specified as word or long. The entire destination address register is used regardless of the operation size.
Condition Codes:
Not affected.
Instruction Format:
15
1
14
1
13
0
12
1
11 10
REGISTER
9 8 7
OPMODE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields:
Register field—Specifies any of the eight address registers. This is always the destination.
Opmode field—Specifies the size of the operation.
011— Word operation; the source operand is sign-extended to a long operand and the operation is performed on the address register using all 32 bits.
111— Long operation.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-7
Integer Instructions
ADDA
Add Address
(M68000 Family)
ADDA
Effective Address field—Specifies the source operand. All addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
001
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
100
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
011
011
011
4-8 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
ADDI
Add Immediate
(M68000 Family)
Immediate Data + Destination
→
Destination
ADDI
Operation:
Assembler
Syntax:
Attributes:
ADDI # < data > , < ea >
Size = (Byte, Word, Long)
Description: Adds the immediate data to the destination operand and stores the result in the destination location. The size of the operation may be specified as byte, word, or long. The size of the immediate data matches the operation size.
Condition Codes:
15
0
14
0
X
*
13
0
N
*
Z
*
V
*
C
*
X — Set the same as the carry bit.
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if an overflow is generated; cleared otherwise.
C — Set if a carry is generated; cleared otherwise.
Instruction Format:
12
0
11
0
10
1
16-BIT WORD DATA
9
1
8
0
7
SIZE
32-BIT LONG DATA
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
8-BIT BYTE DATA
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-9
Integer Instructions
ADDI
Add Immediate
(M68000 Family)
ADDI
Instruction Fields:
Size field—Specifies the size of the operation.
00 — Byte operation
01 — Word operation
10 — Long operation
Effective Address field—Specifies the destination operand. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
Immediate field—Data immediately following the instruction.
If size = 00, the data is the low-order byte of the immediate word.
If size = 01, the data is the entire immediate word.
If size = 10, the data is the next two immediate words.
—
—
—
—
—
—
4-10 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
ADDQ
Add Quick
(M68000 Family)
Immediate Data + Destination
→
Destination
ADDQ
Operation:
Assembler
Syntax:
Attributes:
ADDQ # < data > , < ea >
Size = (Byte, Word, Long)
Description: Adds an immediate value of one to eight to the operand at the destination location. The size of the operation may be specified as byte, word, or long. Word and long operations are also allowed on the address registers. When adding to address registers, the condition codes are not altered, and the entire destination address register is used regardless of the operation size.
Condition Codes:
X — Set the same as the carry bit.
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if an overflow occurs; cleared otherwise.
C — Set if a carry occurs; cleared otherwise.
The condition codes are not affected when the destination is an address register.
Instruction Format:
15
0
14
1
X
*
13
0
N
*
12
1
Z
*
V
*
C
*
11 10
DATA
9 8
0
7
SIZE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-11
Integer Instructions
ADDQ
Add Quick
(M68000 Family)
ADDQ
Instruction Fields:
Data field—Three bits of immediate data representing eight values (0 – 7), with the immediate value zero representing a value of eight.
Size field—Specifies the size of the operation.
00— Byte operation
01— Word operation
10— Long operation
Effective Address field—Specifies the destination location. Only alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
001
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn**
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Word and long only.
**Can be used with CPU32.
(bd,PC,Xn)†
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
4-12 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
ADDX
Operation:
Assembler
Syntax:
Attributes:
Add Extended
(M68000 Family)
Source + Destination + X
→
Destination
ADDX Dy,Dx
ADDX – (Ay), – (Ax)
ADDX
Size = (Byte, Word, Long)
Description: Adds the source operand and the extend bit to the destination operand and stores the result in the destination location. The operands can be addressed in two different ways:
1. Data register to data register—The data registers specified in the instruction contain the operands.
2. Memory to memory—The address registers specified in the instruction address the operands using the predecrement addressing mode.
The size of the operation can be specified as byte, word, or long.
Condition Codes:
X
*
N
*
Z
*
V
*
C
*
X — Set the same as the carry bit.
N — Set if the result is negative; cleared otherwise.
Z — Cleared if the result is nonzero; unchanged otherwise.
V — Set if an overflow occurs; cleared otherwise.
C — Set if a carry is generated; cleared otherwise.
NOTE
Normally, the Z condition code bit is set via programming before the start of an operation. This allows successful tests for zero results upon completion of multiple-precision operations.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-13
Integer Instructions
ADDX
Add Extended
(M68000 Family)
ADDX
Instruction Format:
15
1
14
1
13
0
12
1
11 10
REGISTER Rx
9 8
1
7
SIZE
6 5
0
4
0
3
R/M
2 1
REGISTER Ry
0
Instruction Fields:
Register Rx field—Specifies the destination register.
If R/M = 0, specifies a data register.
If R/M = 1, specifies an address register for the predecrement addressing mode.
Size field—Specifies the size of the operation.
00 — Byte operation
01 — Word operation
10 — Long operation
R/M field—Specifies the operand address mode.
0 — The operation is data register to data register.
1 — The operation is memory to memory.
Register Ry field—Specifies the source register.
If R/M = 0, specifies a data register.
If R/M = 1, specifies an address register for the predecrement addressing mode.
4-14 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
AND
Operation:
Assembler
Syntax:
Attributes:
Source L Destination
→
Destination
AND < ea > ,Dn
AND Dn, < ea >
AND Logical
(M68000 Family)
AND
Size = (Byte, Word, Long)
Description: Performs an AND operation of the source operand with the destination operand and stores the result in the destination location. The size of the operation can be specified as byte, word, or long. The contents of an address register may not be used as an operand.
Condition Codes:
X
—
N
*
Z
*
V
0
C
0
X — Not affected.
N — Set if the most significant bit of the result is set; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
15
1
14
1
13
0
12
0
11 10
REGISTER
9 8 7
OPMODE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields:
Register field—Specifies any of the eight data registers.
Opmode field
Byte Word Long
000 001 010
100 101 110
Operation
< ea >
Λ
Dn
→
Dn
Dn
Λ
< ea >
→
< ea >
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-15
Integer Instructions
AND
AND Logical
(M68000 Family)
AND
Effective Address field—Determines addressing mode. a. If the location specified is a source operand, only data addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
MC68020, MC68030, and MC68040 only
(bd,An,Xn*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
Register
000
001
100
010
011
011
011
011
4-16 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
AND
AND Logical
(M68000 Family)
AND b. If the location specified is a destination operand, only memory alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
—
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register
—
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
NOTE
The Dn mode is used when the destination is a data register; the destination < ea > mode is invalid for a data register.
Most assemblers use ANDI when the source is immediate data.
Register
000
001
—
—
—
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-17
Integer Instructions
ANDI
AND Immediate
(M68000 Family)
Immediate Data
Λ
Destination
→
Destination
ANDI
Operation:
Assembler
Syntax:
Attributes:
ANDI # < data > , < ea >
Size = (Byte, Word, Long)
Description: Performs an AND operation of the immediate data with the destination operand and stores the result in the destination location. The size of the operation can be specified as byte, word, or long. The size of the immediate data matches the operation size.
Condition Codes:
15
0
14
0
X
—
13
0
N
*
Z
*
V
0
C
0
X — Not affected.
N — Set if the most significant bit of the result is set; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
12
0
11
0
10
0
16-BIT WORD DATA
9
1
8
0
7
SIZE
32-BIT LONG DATA
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
8-BIT BYTE DATA
0
4-18 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
ANDI
AND Immediate
(M68000 Family)
ANDI
Instruction Fields:
Size field—Specifies the size of the operation.
00 — Byte operation
01 — Word operation
10 — Long operation
Effective Address field—Specifies the destination operand. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
Immediate field—Data immediately following the instruction.
If size = 00, the data is the low-order byte of the immediate word.
If size = 01, the data is the entire immediate word.
If size = 10, the data is the next two immediate words.
—
—
—
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-19
Integer Instructions
ANDI to CCR
CCR AND Immediate
(M68000 Family)
Source
Λ
CCR
→
CCR
ANDI to CCR
Operation:
Assembler
Syntax:
Attributes:
ANDI # < data > ,CCR
Size = (Byte)
Description: Performs an AND operation of the immediate operand with the condition codes and stores the result in the low-order byte of the status register.
Condition Codes:
X
*
N
*
Z
*
V
*
C
*
X — Cleared if bit 4 of immediate operand is zero; unchanged otherwise.
N — Cleared if bit 3 of immediate operand is zero; unchanged otherwise.
Z — Cleared if bit 2 of immediate operand is zero; unchanged otherwise.
V — Cleared if bit 1 of immediate operand is zero; unchanged otherwise.
C — Cleared if bit 0 of immediate operand is zero; unchanged otherwise.
Instruction Format:
15
0
0
14
0
0
13
0
0
12
0
0
11
0
0
10
0
0
9
1
0
8
0
0
7
0
6
0
5
1
4
1
3
1
8-BIT BYTE DATA
2
1
1
0
0
0
4-20 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
ASL, ASR
Operation:
Arithmetic Shift
(M68000 Family)
Destination Shifted By Count
→
Destination
Assembler
Syntax:
ASd Dx,Dy
ASd # < data > ,Dy
ASd < ea > where d is direction, L or R
ASL, ASR
Attributes: Size = (Byte, Word, Long)
Description: Arithmetically shifts the bits of the operand in the direction (L or R) specified.
The carry bit receives the last bit shifted out of the operand. The shift count for the shifting of a register may be specified in two different ways:
1. Immediate—The shift count is specified in the instruction (shift range, 1 – 8).
2. Register—The shift count is the value in the data register specified in instruction modulo 64.
The size of the operation can be specified as byte, word, or long. An operand in memory can be shifted one bit only, and the operand size is restricted to a word.
For ASL, the operand is shifted left; the number of positions shifted is the shift count.
Bits shifted out of the high-order bit go to both the carry and the extend bits; zeros are shifted into the low-order bit. The overflow bit indicates if any sign changes occur during the shift.
.
C OPERAND O
ASL:
X
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-21
Integer Instructions
ASL, ASR
Arithmetic Shift
(M68000 Family)
ASL, ASR
For ASR, the operand is shifted right; the number of positions shifted is the shift count.
Bits shifted out of the low-order bit go to both the carry and the extend bits; the sign bit
(MSB) is shifted into the high-order bit.
MSB OPERAND C
ASR:
X
Condition Codes:
X
*
N
*
Z
*
V
*
C
*
X — Set according to the last bit shifted out of the operand; unaffected for a shift count of zero.
N — Set if the most significant bit of the result is set; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if the most significant bit is changed at any time during the shift operation; cleared otherwise.
C — Set according to the last bit shifted out of the operand; cleared for a shift count of zero.
Instruction Format:
REGISTER SHIFTS
15
1
14
1
13
1
12
0
11 10
COUNT?
REGISTER
9 8 dr
7
SIZE
6 5 i/r
4
0
3
0
2 1
REGISTER
0
Instruction Fields:
Count/Register field—Specifies shift count or register that contains the shift count:
If i/r = 0, this field contains the shift count. The values 1 – 7 represent counts of 1 –
7; a value of zero represents a count of eight.
If i/r = 1, this field specifies the data register that contains the shift count (modulo 64).
4-22 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
ASL, ASR
Arithmetic Shift
(M68000 Family) dr field—Specifies the direction of the shift.
0 — Shift right
1 — Shift left
Size field—Specifies the size of the operation.
00 — Byte operation
01 — Word operation
10 — Long operation i/r field
If i/r = 0, specifies immediate shift count.
If i/r = 1, specifies register shift count.
Register field—Specifies a data register to be shifted.
Instruction Format:
MEMORY SHIFTS
15
1
14
1
13
1
12
0
11
0
10
0
9
0
8 dr
7
1
6
1
Integer Instructions
ASL, ASR
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields: dr field—Specifies the direction of the shift.
0 — Shift right
1 — Shift left
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-23
Integer Instructions
ASL, ASR
Arithmetic Shift
(M68000 Family)
ASL, ASR
Effective Address field—Specifies the operand to be shifted. Only memory alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
—
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register
—
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
4-24 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
Bcc
Branch Conditionally
Bcc
(M68000 Family)
Operation: If Condition True
Then PC + d n
→
PC
Assembler
Syntax:
Attributes:
Bcc < label >
Size = (Byte, Word, Long*)
*(MC68020, MC68030, and MC68040 only)
Description: If the specified condition is true, program execution continues at location (PC)
+ displacement. The program counter contains the address of the instruction word for the Bcc instruction plus two. The displacement is a twos-complement integer that represents the relative distance in bytes from the current program counter to the destination program counter. If the 8-bit displacement field in the instruction word is zero, a 16-bit displacement (the word immediately following the instruction) is used. If the 8-bit displacement field in the instruction word is all ones ($FF), the 32-bit displacement (long word immediately following the instruction) is used. Condition code cc specifies one of the following conditional tests (refer to Table 3-19 for more information on these conditional tests):
Mnemonic
CC(HI)
CS(LO)
EQ
GE
GT
HI
LE
Condition Codes:
Not affected.
Condition
Carry Clear
Carry Set
Equal
Greater or Equal
Greater Than
High
Less or Equal
Mnemonic
LS
LT
MI
NE
PL
VC
VS
Condition
Low or Same
Less Than
Minus
Not Equal
Plus
Overflow Clear
Overflow Set
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-25
Integer Instructions
Bcc
Branch Conditionally
(M68000 Family)
Bcc
Instruction Format:
15
0
14
1
13
1
12
0
11 10 9
CONDITION
8 7 6 5 4 3
8-BIT DISPLACEMENT
2
16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00
32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF
Instruction Fields:
Condition field—The binary code for one of the conditions listed in the table.
1 0
8-Bit Displacement field—Twos complement integer specifying the number of bytes between the branch instruction and the next instruction to be executed if the condition is met.
16-Bit Displacement field—Used for the displacement when the 8-bit displacement field contains $00.
32-Bit Displacement field—Used for the displacement when the 8-bit displacement field contains $FF.
NOTE
A branch to the immediately following instruction automatically uses the 16-bit displacement format because the 8-bit displacement field contains $00 (zero offset).
4-26 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
BCHG
Operation:
Test a Bit and Change
(M68000 Family)
BCHG
TEST ( < number > of Destination)
→
Z;
TEST ( < number > of Destination)
→
< bit number > of Destination
BCHG Dn, < ea >
BCHG # < data > , < ea >
Assembler
Syntax:
Attributes: Size = (Byte, Long)
Description: Tests a bit in the destination operand and sets the Z condition code appropriately, then inverts the specified bit in the destination. When the destination is a data register, any of the 32 bits can be specified by the modulo 32-bit number. When the destination is a memory location, the operation is a byte operation, and the bit number is modulo 8. In all cases, bit zero refers to the least significant bit. The bit number for this operation may be specified in either of two ways:
1. Immediate—The bit number is specified in a second word of the instruction.
2. Register—The specified data register contains the bit number.
Condition Codes:
X
—
N
—
Z
*
V
—
C
—
X — Not affected.
N — Not affected.
Z — Set if the bit tested is zero; cleared otherwise.
V — Not affected.
C — Not affected.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-27
Integer Instructions
BCHG
Test a Bit and Change
(M68000 Family)
Instruction Format:
BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER
BCHG
15
0
14
0
13
0
12
0
11 10
REGISTER
9 8
1
7
0
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields:
Register field—Specifies the data register that contains the bit number.
Effective Address field—Specifies the destination location. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn*
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)**
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Long only; all others are byte only.
**Can be used with CPU32.
(bd,PC,Xn)†
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
4-28 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
BCHG
Test a Bit and Change
(M68000 Family)
Instruction Format:
BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA
Integer Instructions
BCHG
15
0
0
14
0
0
13
0
0
12
0
0
11
1
0
10
0
0
9
0
0
8
0
0
7
0
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE
BIT NUMBER
REGISTER
0
Instruction Fields:
Effective Address field—Specifies the destination location. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn*
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)**
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Long only; all others are byte only.
**Can be used with CPU32.
Bit Number field—Specifies the bit number.
(bd,PC,Xn)†
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
(bd,An,Xn)**
([bd,An,Xn],od)
([bd,An],Xn,od)
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-29
Integer Instructions
BCLR
Operation:
Test a Bit and Clear
(M68000 Family)
BCLR
TEST ( < bit number > of Destination)
→
Z; 0
→
< bit number > of Destination
Assembler
Syntax:
Attributes:
BCLR Dn, < ea >
BCLR # < data > , < ea >
Size = (Byte, Long)
Description: Tests a bit in the destination operand and sets the Z condition code appropriately, then clears the specified bit in the destination. When a data register is the destination, any of the 32 bits can be specified by a modulo 32-bit number. When a memory location is the destination, the operation is a byte operation, and the bit number is modulo 8. In all cases, bit zero refers to the least significant bit. The bit number for this operation can be specified in either of two ways:
1. Immediate—The bit number is specified in a second word of the instruction.
2. Register—The specified data register contains the bit number.
Condition Codes:
X
—
N
—
Z
*
V
—
C
—
X — Not affected.
N — Not affected.
Z — Set if the bit tested is zero; cleared otherwise.
V — Not affected.
C — Not affected.
4-30 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
BCLR
Test a Bit and Clear
(M68000 Family)
Instruction Format:
BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER
Integer Instructions
BCLR
15
0
14
0
13
0
12
0
11 10
REGISTER
9 8
1
7
1
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields:
Register field—Specifies the data register that contains the bit number.
Effective Address field—Specifies the destination location. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn*
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)**
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Long only; all others are byte only.
**Can be used with CPU32.
(bd,PC,Xn)†
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-31
Integer Instructions
BCLR
Test a Bit and Clear
(M68000 Family)
Instruction Format:
BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA
BCLR
15
0
0
14
0
0
13
0
0
12
0
0
11
1
0
10
0
0
9
0
0
8
0
0
7
1
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE
BIT NUMBER
REGISTER
0
Instruction Fields:
Effective Address field—Specifies the destination location. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn*
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)**
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Long only; all others are byte only.
**Can be used with CPU32.
Bit Number field—Specifies the bit number.
(bd,PC,Xn)†
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
4-32 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
BFCHG
Test Bit Field and Change
(MC68020, MC68030, MC68040)
BFCHG
TEST ( < bit field > of Destination)
→
< bit field > of Destination Operation:
Assembler
Syntax:
Attributes:
BFCHG < ea > {offset:width}
Unsized
Description: Sets the condition codes according to the value in a bit field at the specified effective address, then complements the field.
A field offset and a field width select the field. The field offset specifies the starting bit of the field. The field width determines the number of bits in the field.
Condition Codes:
X
—
N
*
Z
*
V
0
C
0
X — Not affected.
N — Set if the most significant bit of the field is set; cleared otherwise.
Z — Set if all bits of the field are zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
15
1
0
14
1
0
13
1
0
12
0
0
11
1
Do
10
0
9
1
8
0
OFFSET
7
1
6
1
5
Dw
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
WIDTH
0
NOTE
For the MC68020, MC68030, and MC68040, all bit field instructions access only those bytes in memory that contain some portion of the bit field. The possible accesses are byte, word, 3-byte, long word, and long word with byte (for a 5-byte access).
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-33
Integer Instructions
BFCHG
Test Bit Field and Change
(MC68020, MC68030, MC68040)
BFCHG
Instruction Fields:
Effective Address field—Specifies the base location for the bit field. Only data register direct or control alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110
110
110
010
—
—
101
Register reg. number:Dn
— reg. number:An
—
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
Register
000
001
—
—
—
—
—
—
Do field—Determines how the field offset is specified.
0 — The offset field contains the bit field offset.
1 — Bits 8 – 6 of the extension word specify a data register that contains the offset; bits 10 – 9 are zero.
Offset field—Specifies the field offset, depending on Do.
If Do = 0, the offset field is an immediate operand; the operand value is in the range
0 – 31.
If Do = 1, the offset field specifies a data register that contains the offset. The value is in the range of – 2
31
to 2
31
– 1.
Dw field—Determines how the field width is specified.
0 — The width field contains the bit field width.
1 — Bits 2 – 0 of the extension word specify a data register that contains the width; bits 3 – 4 are zero.
Width field—Specifies the field width, depending on Dw.
If Dw = 0, the width field is an immediate operand; an operand value in the range 1
– 31 specifies a field width of 1 – 31, and a value of zero specifies a width of 32.
If Dw = 1, the width field specifies a data register that contains the width. The value is modulo 32; values of 1 – 31 specify field widths of 1 – 31, and a value of zero specifies a width of 32.
4-34 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
BFCLR
Test Bit Field and Clear
(MC68020, MC68030, MC68040)
0
→
< bit field > of Destination
BFCLR
Operation:
Assembler
Syntax:
Attributes:
BFCLR < ea > {offset:width}
Unsized
Description: Sets condition codes according to the value in a bit field at the specified effective address and clears the field.
The field offset and field width select the field. The field offset specifies the starting bit of the field. The field width determines the number of bits in the field.
Condition Codes:
15
1
0
14
1
0
X
—
13
1
0
N
*
12
0
0
Z
*
V
0
C
0
X — Not affected.
N — Set if the most significant bit of the field is set; cleared otherwise.
Z — Set if all bits of the field are zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
11
1
Do
10
1
9
0
8
0
OFFSET
7
1
6
1
5
Dw
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
WIDTH
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-35
Integer Instructions
BFCLR
Test Bit Field and Clear
(MC68020, MC68030, MC68040)
BFCLR
Instruction Fields:
Effective Address field—Specifies the base location for the bit field. Only data register direct or control alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110
110
110
010
—
—
101
Register reg. number:Dn
— reg. number:An
—
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
Register
000
001
—
—
—
—
—
—
Do field—Determines how the field offset is specified.
0 — The offset field contains the bit field offset.
1 — Bits 8 – 6 of the extension word specify a data register that contains the offset; bits 10 – 9 are zero.
Offset field—Specifies the field offset, depending on Do.
If Do = 0, the offset field is an immediate operand; the operand value is in the range of 0 – 31.
If Do = 1, the offset field specifies a data register that contains the offset. The value is in the range of – 2
31
to 2
31
– 1.
Dw field—Determines how the field width is specified.
0 — The width field contains the bit field width.
1 — Bits 2 – 0 of the extension word specify a data register that contains the width; bits 3 – 4 are zero.
Width field—Specifies the field width, depending on Dw.
If Dw = 0, the width field is an immediate operand; operand values in the range of 1
– 31 specify a field width of 1 – 31, and a value of zero specifies a width of 32.
If Dw = 1, the width field specifies a data register that contains the width. The value is modulo 32; values of 1 – 31 specify field widths of 1 – 31, and a value of zero specifies a width of 32.
4-36 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
BFEXTS
Operation:
Extract Bit Field Signed
(MC68020, MC68030, MC68040)
< bit field > of Source
→
Dn
Assembler
Syntax: BFEXTS < ea > {offset:width},Dn
BFEXTS
Attributes: Unsized
Description: Extracts a bit field from the specified effective address location, sign extends to 32 bits, and loads the result into the destination data register. The field offset and field width select the bit field. The field offset specifies the starting bit of the field. The field width determines the number of bits in the field.
Condition Codes:
15
1
0
X
—
N
*
14
1
13
1
REGISTER
12
0
Z
*
V
0
C
0
X — Not affected.
N — Set if the most significant bit of the field is set; cleared otherwise.
Z — Set if all bits of the field are zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
11
1
Do
10
0
9
1
8
1
OFFSET
7
1
6
1
5
Dw
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
WIDTH
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-37
Integer Instructions
BFEXTS
Extract Bit Field Signed
(MC68020, MC68030, MC68040)
BFEXTS
Instruction Fields:
Effective Address field—Specifies the base location for the bit field. Only data register direct or control addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110
110
110
010
—
—
101
Register reg. number:Dn
— reg. number:An
—
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
Register
000
001
—
010
011
011
011
011
Register field—Specifies the destination register.
Do field—Determines how the field offset is specified.
0 — The offset field contains the bit field offset.
1 — Bits 8 – 6 of the extension word specify a data register that contains the offset; bits 10 – 9 are zero.
Offset field—Specifies the field offset, depending on Do.
If Do = 0, the offset field is an immediate operand; the operand value is in the range of 0 – 31.
If Do = 1, the offset field specifies a data register that contains the offset. The value is in the range of – 2
31
to 2
31
– 1.
Dw field—Determines how the field width is specified.
0 — The width field contains the bit field width.
1 — Bits 2 – 0 of the extension word specify a data register that contains the width; bits 4 – 3 are zero.
4-38 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
BFEXTS
Extract Bit Field Signed
(MC68020, MC68030, MC68040)
BFEXTS
Width field—Specifies the field width, depending on Dw.
If Dw = 0, the width field is an immediate operand; operand values in the range of 1
– 31 specify a field width of 1 – 31, and a value of zero specifies a width of 32.
If Dw = 1, the width field specifies a data register that contains the width. The value is modulo 32; values of 1 – 31 specify field widths of 1 – 31, and a value of zero specifies a width of 32.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-39
Integer Instructions
BFEXTU
Operation:
Extract Bit Field Unsigned
(MC68020, MC68030, MC68040)
< bit offset > of Source
→
Dn
Assembler
Syntax: BFEXTU < ea > {offset:width},Dn
BFEXTU
Attributes: Unsized
Description: Extracts a bit field from the specified effective address location, zero extends to 32 bits, and loads the results into the destination data register. The field offset and field width select the field. The field offset specifies the starting bit of the field. The field width determines the number of bits in the field.
Condition Codes:
15
1
0
X
—
N
*
14
1
13
1
REGISTER
12
0
Z
*
V
0
C
0
X — Not affected.
N — Set if the most significant bit of the source field is set; cleared otherwise.
Z — Set if all bits of the field are zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
11
1
Do
10
0
9
0
8
1
OFFSET
7
1
6
1
5
Dw
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
WIDTH
0
4-40 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
BFEXTU
Extract Bit Field Unsigned
(MC68020, MC68030, MC68040)
BFEXTU
Instruction Fields:
Effective Address field—Specifies the base location for the bit field. Only data register direct or control addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110
110
110
010
—
—
101
Register reg. number:Dn
— reg. number:An
—
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
Register
000
001
—
010
011
011
011
011
Register field—Specifies the destination data register.
Do field—Determines how the field offset is specified.
0 — The offset field contains the bit field offset.
1 — Bits 8 – 6 of the extension word specify a data register that contains the offset; bits 10 – 9 are zero.
Offset field—Specifies the field offset, depending on Do.
If Do = 0, the offset field is an immediate operand; the operand value is in the range of 0 – 31.
If Do = 1, the offset field specifies a data register that contains the offset. The value is in the range of – 2
31
to 2
31
– 1.
Dw field—Determines how the field width is specified.
0 — The width field contains the bit field width.
1 — Bits 2 – 0 of the extension word specify a data register that contains the width; bits 4 – 3 are zero.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-41
Integer Instructions
BFEXTU
Extract Bit Field Unsigned
(MC68020, MC68030, MC68040)
BFEXTU
Width field—Specifies the field width, depending on Dw.
If Dw = 0, the width field is an immediate operand; operand values in the range of 1
– 31 specify a field width of 1 – 31, and a value of zero specifies a width of 32.
If Dw = 1, the width field specifies a data register that contains the width. The value is modulo 32; values of 1 – 31 specify field widths of 1 – 31, and a value of zero specifies a width of 32.
4-42 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
BFFFO
Find First One in Bit Field
(MC68020, MC68030, MC68040)
< bit offset > of Source Bit Scan
→
Dn
BFFFO
Operation:
Assembler
Syntax:
Attributes:
BFFFO < ea > {offset:width},Dn
Unsized
Description: Searches the source operand for the most significant bit that is set to a value of one. The bit offset of that bit (the bit offset in the instruction plus the offset of the first one bit) is placed in Dn. If no bit in the bit field is set to one, the value in Dn is the field offset plus the field width. The instruction sets the condition codes according to the bit field value. The field offset and field width select the field. The field offset specifies the starting bit of the field. The field width determines the number of bits in the field.
Condition Codes:
15
1
0
X
—
N
*
14
1
13
1
REGISTER
12
0
Z
*
V
0
C
0
X — Not affected.
N — Set if the most significant bit of the field is set; cleared otherwise.
Z — Set if all bits of the field are zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
11
1
Do
10
0
9
0
8
1
OFFSET
7
1
6
1
5
Dw
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
WIDTH
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-43
Integer Instructions
BFFFO
Find First One in Bit Field
(MC68020, MC68030, MC68040)
BFFFO
Instruction Fields:
Effective Address field—Specifies the base location for the bit field. Only data register direct or control addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110
110
110
010
—
—
101
Register reg. number:Dn
— reg. number:An
—
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
Register
000
001
—
010
011
011
011
011
Register field—Specifies the destination data register operand.
Do field—Determines how the field offset is specified.
0 — The offset field contains the bit field offset.
1 — Bits 8 – 6 of the extension word specify a data register that contains the offset; bits 10 – 9 are zero.
Offset field—Specifies the field offset, depending on Do.
If Do = 0, the offset field is an immediate operand; the operand value is in the range of 0 – 31.
If Do = 1, the offset field specifies a data register that contains the offset. The value is in the range of – 2
31
to 2
31
– 1.
Dw field—Determines how the field width is specified.
0 — The width field contains the bit field width.
1 — Bits 2 – 0 of the extension word specify a data register that contains the width; bits 4 – 3 are zero.
4-44 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
BFFFO
Find First One in Bit Field
(MC68020, MC68030, MC68040)
BFFFO
Width field—Specifies the field width, depending on Dw.
If Dw = 0, the width field is an immediate operand; operand values in the range of 1
– 31 specify a field width of 1 – 31, and a value of zero specifies a width of 32.
If Dw = 1, the width field specifies a data register that contains the width. The value is modulo 32; values of 1 – 31 specify field widths of 1 – 31, and a value of zero specifies a width of 32.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-45
Integer Instructions
BFINS
Insert Bit Field
(MC68020, MC68030, MC68040)
Dn
→
< bit field > of Destination
BFINS
Operation:
Assembler
Syntax:
Attributes:
BFINS Dn, < ea > {offset:width}
Unsized
Description: Inserts a bit field taken from the low-order bits of the specified data register into a bit field at the effective address location. The instruction sets the condition codes according to the inserted value. The field offset and field width select the field. The field offset specifies the starting bit of the field. The field width determines the number of bits in the field.
Condition Codes:
15
1
0
X
—
N
*
14
1
13
1
REGISTER
12
0
Z
*
V
0
C
0
X — Not affected.
N — Set if the most significant bit of the field is set; cleared otherwise.
Z — Set if all bits of the field are zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
11
1
Do
10
1
9
1
8
1
OFFSET
7
1
6
1
5
Dw
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
WIDTH
0
4-46 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
BFINS
Insert Bit Field
(MC68020, MC68030, MC68040)
BFINS
Instruction Fields:
Effective Address field—Specifies the base location for the bit field. Only data register direct or control alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110
110
110
010
—
—
101
Register reg. number:Dn
— reg. number:An
—
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
Register
000
001
—
—
—
—
—
—
Register field—Specifies the source data register operand.
Do field—Determines how the field offset is specified.
0 — The offset field contains the bit field offset.
1 — Bits 8 – 6 of the extension word specify a data register that contains the offset; bits 10 – 9 are zero.
Offset field—Specifies the field offset, depending on Do.
If Do = 0, the offset field is an immediate operand; the operand value is in the range of 0 – 31.
If Do = 1, the offset field specifies a data register that contains the offset. The value is in the range of – 2
31
to 2
31
– 1.
Dw field—Determines how the field width is specified.
0 — The width field contains the bit field width.
1 — Bits 2 – 0 of the extension word specify a data register that contains the width; bits 4 – 3 are zero.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-47
Integer Instructions
BFINS
Insert Bit Field
(MC68020, MC68030, MC68040)
BFINS
Width field—Specifies the field width, depending on Dw.
If Dw = 0, the width field is an immediate operand; operand values in the range of 1
– 31 specify a field width of 1 – 31, and a value of zero specifies a width of 32.
If Dw = 1, the width field specifies a data register that contains the width. The value is modulo 32; values of 1 – 31 specify field widths of 1 – 31, and a value of zero specifies a width of 32.
4-48 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
BFSET
Test Bit Field and Set
(MC68020, MC68030, MC68040)
1
→
< bit field > of Destination
BFSET
Operation:
Assembler
Syntax:
Attributes:
BFSET < ea > {offset:width}
Unsized
Description: Sets the condition codes according to the value in a bit field at the specified effective address, then sets each bit in the field.
The field offset and the field width select the field. The field offset specifies the starting bit of the field. The field width determines the number of bits in the field.
Condition Codes:
15
1
0
14
1
0
X
—
13
1
0
N
*
12
0
0
Z
*
V
0
C
0
X — Not affected.
N — Set if the most significant bit of the field is set; cleared otherwise.
Z — Set if all bits of the field are zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
11
1
Do
10
1
9
1
8
0
OFFSET
7
1
6
1
5
Dw
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
WIDTH
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-49
Integer Instructions
BFSET
Test Bit Field and Set
(MC68020, MC68030, MC68040)
BFSET
Instruction Fields:
Effective Address field—Specifies the base location for the bit field. Only data register direct or control alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110
110
110
010
—
—
101
Register reg. number:Dn
— reg. number:An
—
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
Register
000
001
—
—
—
—
—
—
Do field—Determines how the field offset is specified.
0 — The offset field contains the bit field offset.
1 — Bits 8 – 6 of the extension word specify a data register that contains the offset; bits 10 – 9 are zero.
Offset field—Specifies the field offset, depending on Do.
If Do = 0, the offset field is an immediate operand; the operand value is in the range of 0 – 31.
If Do = 1, the offset field specifies a data register that contains the offset. The value is in the range of – 2
31
to 2
31
– 1.
Dw field—Determines how the field width is specified.
0 — The width field contains the bit field width.
1 — Bits 2 – 0 of the extension word specify a data register that contains the width; bits 4 – 3 are zero.
Width field—Specifies the field width, depending on Dw.
If Dw = 0, the width field is an immediate operand; operand values in the range of 1
– 31 specify a field width of 1 – 31, and a value of zero specifies a width of 32.
If Dw = 1, the width field specifies a data register that contains the width. The value is modulo 32; values of 1 – 31 specify field widths of 1 – 31, and a value of zero specifies a width of 32.
4-50 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
BFTST
Test Bit Field
(MC68020, MC68030, MC68040)
BFTST
Operation:
Assembler
Syntax:
Attributes:
< bit field > of Destination
BFTST < ea > {offset:width}
Unsized
Description: Sets the condition codes according to the value in a bit field at the specified effective address location. The field offset and field width select the field. The field offset specifies the starting bit of the field. The field width determines the number of bits in the field.
Condition Codes:
X
—
N
∗
Z
∗
V
0
C
0
X — Not affected.
N — Set if the most significant bit of the field is set; cleared otherwise.
Z — Set if all bits of the field are zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
15
1
0
14
1
0
13
1
0
12
0
0
11
1
Do
10
0
9
0
8
0
OFFSET
7
1
6
1
5
Dw
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
WIDTH
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-51
Integer Instructions
BFTST
Test Bit Field
(MC68020, MC68030, MC68040)
BFTST
Instruction Fields:
Effective Address field—Specifies the base location for the bit field. Only data register direct or control addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110
110
110
010
—
—
101
Register reg. number:Dn
— reg. number:An
—
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
Register
000
001
—
010
011
011
011
011
Do field—Determines how the field offset is specified.
0 — The offset field contains the bit field offset.
1 — Bits 8 – 6 of the extension word specify a data register that contains the offset; bits 10 – 9 are zero.
Offset field—Specifies the field offset, depending on Do.
If Do = 0, the offset field is an immediate operand; the operand value is in the range of 0 – 31.
If Do = 1, the offset field specifies a data register that contains the offset. The value is in the range of – 2
31
to 2
31
– 1.
Dw field—Determines how the field width is specified.
0 — The width field contains the bit field width.
1 — Bits 2 – 0 of the extension word specify a data register that contains the width; bits 4 – 3 are zero.
Width field—Specifies the field width, depending on Dw.
If Dw = 0, the width field is an immediate operand, operand values in the range of 1
– 31 specify a field width of 1 – 31, and a value of zero specifies a width of 32.
If Dw = 1, the width field specifies a data register that contains the width. The value is modulo 32; values of 1 – 31 specify field widths of 1 – 31, and a value of zero specifies a width of 32.
4-52 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
BKPT
Breakpoint
(MC68EC000, MC68010, MC68020, MC68030, MC68040, CPU32)
BKPT
Operation:
Assembler
Syntax:
Attributes:
Run Breakpoint Acknowledge Cycle; TRAP As Illegal Instruction
BKPT # < data >
Unsized
Description: For the MC68010, a breakpoint acknowledge bus cycle is run with function codes driven high and zeros on all address lines. Whether the breakpoint acknowledge bus cycle is terminated with DTACK, BERR, or VPA, the processor always takes an illegal instruction exception. During exception processing, a debug monitor can distinguish different software breakpoints by decoding the field in the BKPT instruction.
For the MC68000 and MC68008, the breakpoint cycle is not run, but an illegal instruction exception is taken.
For the MC68020, MC68030, and CPU32, a breakpoint acknowledge bus cycle is executed with the immediate data (value 0 – 7) on bits 2 – 4 of the address bus and zeros on bits 0 and 1 of the address bus. The breakpoint acknowledge bus cycle accesses the CPU space, addressing type 0, and provides the breakpoint number specified by the instruction on address lines A2 – A4. If the external hardware terminates the cycle with DSACKx or STERM, the data on the bus (an instruction word) is inserted into the instruction pipe and is executed after the breakpoint instruction. The breakpoint instruction requires a word to be transferred so, if the first bus cycle accesses an 8- bit port, a second bus cycle is required. If the external logic terminates the breakpoint acknowledge bus cycle with BERR (i.e., no instruction word available), the processor takes an illegal instruction exception.
For the MC68040, this instruction executes a breakpoint acknowledge bus cycle.
Regardless of the cycle termination, the MC68040 takes an illegal instruction exception.
For more information on the breakpoint instruction refer to the appropriate user’s manual on bus operation.
This instruction supports breakpoints for debug monitors and real- time hardware emulators.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-53
Integer Instructions
BKPT
Breakpoint
(MC68EC000, MC68010, MC68020,
MC68030, MC68040, CPU32)
BKPT
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
0
9
0
8
0
7
0
6
1
5
0
4
0
3
1
2 1
VECTOR
0
Instruction Field:
Vector field—Contains the immediate data, a value in the range of 0 – 7. This is the breakpoint number.
4-54 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
BRA
PC + d n
→
PC
Branch Always
(M68000 Family)
BRA
Operation:
Assembler
Syntax:
Attributes:
BRA < label >
Size = (Byte, Word, Long*)
*(MC68020, MC68030, MC68040 only)
Description: Program execution continues at location (PC) + displacement. The program counter contains the address of the instruction word of the BRA instruction plus two.
The displacement is a twos complement integer that represents the relative distance in bytes from the current program counter to the destination program counter. If the 8-bit displacement field in the instruction word is zero, a 16-bit displacement (the word immediately following the instruction) is used. If the 8-bit displacement field in the instruction word is all ones ($FF), the 32-bit displacement (long word immediately following the instruction) is used.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
1
12
0
11
0
10
0
9
0
8
0
7 6 5 4 3
8-BIT DISPLACEMENT
2
16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00
32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF
1 0
Instruction Fields:
8-Bit Displacement field—Twos complement integer specifying the number of bytes between the branch instruction and the next instruction to be executed.
16-Bit Displacement field—Used for a larger displacement when the 8-bit displacement is equal to $00.
32-Bit Displacement field—Used for a larger displacement when the 8-bit displacement is equal to $FF.
NOTE
A branch to the immediately following instruction automatically uses the 16-bit displacement format because the 8-bit displacement field contains $00 (zero offset).
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-55
Integer Instructions
BSET
Operation:
Test a Bit and Set
(M68000 Family)
BSET
TEST ( < bit number > of Destination)
→
Z; 1
→
< bit number > of Destination
Assembler
Syntax:
Attributes:
BSET Dn, < ea >
BSET # < data > , < ea >
Size = (Byte, Long)
Description: Tests a bit in the destination operand and sets the Z condition code appropriately, then sets the specified bit in the destination operand. When a data register is the destination, any of the 32 bits can be specified by a modulo 32-bit number. When a memory location is the destination, the operation is a byte operation, and the bit number is modulo 8. In all cases, bit zero refers to the least significant bit.
The bit number for this operation can be specified in either of two ways:
1. Immediate—The bit number is specified in the second word of the instruction.
2. Register—The specified data register contains the bit number.
Condition Codes:
X
—
N
—
Z
∗
V
—
C
—
X — Not affected.
N — Not affected.
Z — Set if the bit tested is zero; cleared otherwise.
V — Not affected.
C — Not affected.
4-56 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
BSET
Test a Bit and Set
(M68000 Family)
Instruction Format:
BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER
Integer Instructions
BSET
15
0
14
0
13
0
12
0
11 10
REGISTER
9 8
1
7
1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields:
Register field—Specifies the data register that contains the bit number.
Effective Address field—Specifies the destination location. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn*
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)**
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Long only; all others are byte only.
**Can be used with CPU32.
(bd,PC,Xn)†
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-57
Integer Instructions
BSET
Test a Bit and Set
(M68000 Family)
Instruction Format:
BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA
BSET
15
0
0
14
0
0
13
0
0
12
0
0
11
1
0
10
0
0
9
0
0
8
0
7
1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE
BIT NUMBER
REGISTER
0
Instruction Fields:
Effective Address field—Specifies the destination location. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn*
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)**
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Long only; all others are byte only.
**Can be used with CPU32.
Bit Number field—Specifies the bit number.
(bd,PC,Xn)†
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
4-58 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
BSR
Branch to Subroutine
(M68000 Family)
SP – 4
→
SP; PC
→
(SP); PC + d n
→
PC
BSR
Operation:
Assembler
Syntax:
Attributes:
BSR < label >
Size = (Byte, Word, Long*)
*(MC68020, MC68030, MC68040 only)
Description: Pushes the long-word address of the instruction immediately following the
BSR instruction onto the system stack. The program counter contains the address of the instruction word plus two. Program execution then continues at location (PC) + displacement. The displacement is a twos complement integer that represents the relative distance in bytes from the current program counter to the destination program counter. If the 8-bit displacement field in the instruction word is zero, a 16-bit displacement (the word immediately following the instruction) is used. If the 8-bit displacement field in the instruction word is all ones ($FF), the 32-bit displacement
(long word immediately following the instruction) is used.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
1
12
0
11
0
10
0
9
0
8
1
7 6 5 4 3
8-BIT DISPLACEMENT
2
16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00
32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF
1 0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-59
Integer Instructions
BSR
Branch to Subroutine
(M68000 Family)
BSR
Instruction Fields:
8-Bit Displacement field—Twos complement integer specifying the number of bytes between the branch instruction and the next instruction to be executed.
16-Bit Displacement field—Used for a larger displacement when the 8-bit displacement is equal to $00.
32-Bit Displacement field—Used for a larger displacement when the 8-bit displacement is equal to $FF.
NOTE
A branch to the immediately following instruction automatically uses the 16-bit displacement format because the 8-bit displacement field contains $00 (zero offset).
4-60 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
BTST
Operation:
Assembler
Syntax:
Attributes:
Test a Bit
(M68000 Family)
TEST ( < bit number > of Destination)
→
Z
BTST Dn, < ea >
BTST # < data > , < ea >
BTST
Size = (Byte, Long)
Description: Tests a bit in the destination operand and sets the Z condition code appropriately. When a data register is the destination, any of the 32 bits can be specified by a modulo 32- bit number. When a memory location is the destination, the operation is a byte operation, and the bit number is modulo 8. In all cases, bit zero refers to the least significant bit. The bit number for this operation can be specified in either of two ways:
1. Immediate—The bit number is specified in a second word of the instruction.
2. Register—The specified data register contains the bit number.
Condition Codes:
X
—
N
—
Z
∗
V
—
C
—
X — Not affected.
N — Not affected.
Z — Set if the bit tested is zero; cleared otherwise.
V — Not affected.
C — Not affected.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-61
Integer Instructions
BTST
Test a Bit
(M68000 Family)
Instruction Format:
BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER
BTST
15
0
14
0
13
0
12
0
11 10
REGISTER
9 8
1
7
0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields:
Register field—Specifies the data register that contains the bit number.
Effective Address field—Specifies the destination location. Only data addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn*
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
100
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)**
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Long only; all others are byte only.
**Can be used with CPU32.
(bd,PC,Xn)†
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
011
011
011
4-62 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
BTST
Test a Bit
(M68000 Family)
Instruction Format:
BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA
Integer Instructions
BTST
15
0
0
14
0
0
13
0
0
12
0
0
11
1
0
10
0
0
9
0
0
8
0
0
7
0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE
BIT NUMBER
REGISTER
0
Instruction Fields:
Effective Address field—Specifies the destination location. Only data addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
—
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
Bit Number field—Specifies the bit number.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
011
011
011
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-63
Integer Instructions
CALLM
Call Module
(MC68020)
CALLM
Operation: Save Current Module State on Stack; Load New Module State from
Destination
Assembler
Syntax:
Attributes:
CALLM # < data > , < ea >
Unsized
Description: The effective address of the instruction is the location of an external module descriptor. A module frame is created on the top of the stack, and the current module state is saved in the frame. The immediate operand specifies the number of bytes of arguments to be passed to the called module. A new module state is loaded from the descriptor addressed by the effective address.
Condition Codes:
Not affected.
Instruction Format:
15
0
0
14
0
0
13
0
0
12
0
0
11
0
0
10
1
0
9
1
0
8
0
0
7
1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE
ARGUMENT COUNT
REGISTER
0
4-64 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
CALLM
Call Module
(MC68020)
CALLM
Instruction Fields:
Effective Address field—Specifies the address of the module descriptor. Only control addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn
An
—
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110
110
110
010
—
—
101
Register
—
— reg. number:An
—
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
Register
000
001
—
010
011
011
011
011
Argument Count field—Specifies the number of bytes of arguments to be passed to the called module. The 8-bit field can specify from 0 to 255 bytes of arguments. The same number of bytes is removed from the stack by the RTM instruction.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-65
Integer Instructions
CAS
CAS2
Operation:
Compare and Swap with Operand
(MC68020, MC68030, MC68040)
CAS
CAS2
CAS Destination – Compare Operand
→
cc;
If Z, Update Operand
→
Destination
Else Destination
→
Compare Operand
CAS2 Destination 1 – Compare 1
→
cc;
If Z, Destination 2 – Compare 2
→
cc
If Z, Update 1
→
Destination 1; Update 2
→
Destination 2
Else Destination 1
→
Compare 1; Destination 2
→
Compare 2
Assembler
Syntax:
Attributes:
CAS Dc,Du, < ea >
CAS2 Dc1:Dc2,Du1:Du2,(Rn1):(Rn2)
Size = (Byte
*
, Word, Long)
Description: CAS compares the effective address operand to the compare operand (Dc).
If the operands are equal, the instruction writes the update operand (Du) to the effective address operand; otherwise, the instruction writes the effective address operand to the compare operand (Dc).
CAS2 compares memory operand 1 (Rn1) to compare operand 1 (Dc1). If the operands are equal, the instruction compares memory operand 2 (Rn2) to compare operand 2 (Dc2). If these operands are also equal, the instruction writes the update operands (Du1 and Du2) to the memory operands (Rn1 and Rn2). If either comparison fails, the instruction writes the memory operands (Rn1 and Rn2) to the compare operands (Dc1 and Dc2).
Both operations access memory using locked or read-modify-write transfer sequences, providing a means of synchronizing several processors.
Condition Codes:
X
—
N
∗
Z
∗
V
∗
C
∗
X — Not affected.
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if an overflow is generated; cleared otherwise.
C — Set if a borrow is generated; cleared otherwise.
4-66
*.
CAS2 cannot use byte operands.
M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
CAS
CAS2
Compare and Swap with Operand
(MC68020, MC68030, MC68040)
Integer Instructions
CAS
CAS2
Instruction Format:
CAS
15
0
0
14
0
0
13
0
0
12
0
0
11
1
0
10
SIZE
9
0 0
8
0
7
1
Du
Instruction Fields:
Size field—Specifies the size of the operation.
01 — Byte operation
10 — Word operation
11 — Long operation
6
1
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0
REGISTER
Dc
0
Effective Address field—Specifies the location of the memory operand. Only memory alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn —
An
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
101
110
110
110
110
—
010
011
100
Register
—
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
111
(xxx).L
#<data>
111
—
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
Register
000
001
—
—
—
—
—
—
Du field—Specifies the data register that contains the update value to be written to the memory operand location if the comparison is successful.
Dc field—Specifies the data register that contains the value to be compared to the memory operand.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-67
Integer Instructions
CAS
CAS2
Compare and Swap with Operand
(MC68020, MC68030, MC68040)
CAS
CAS2
Instruction Format:
CAS2
15
0
D/A1
D/A2
14
0
13
0
Rn1
Rn2
12
0
11
1
0
0
10
SIZE
9
0
0
0
0
8
0
7
1
Du1
Du2
Instruction Fields:
Size field—Specifies the size of the operation.
10 — Word operation
11 — Long operation
6
1
0
0
5
1
0
0
4
1
0
0
3
1
2
1
1
0
Dc1
Dc2
0
0
D/A1, D/A2 fields—Specify whether Rn1 and Rn2 reference data or address registers, respectively.
0 — The corresponding register is a data register.
1 — The corresponding register is an address register.
Rn1, Rn2 fields—Specify the numbers of the registers that contain the addresses of the first and second memory operands, respectively. If the operands overlap in memory, the results of any memory update are undefined.
Du1, Du2 fields—Specify the data registers that contain the update values to be written to the first and second memory operand locations if the comparison is successful.
Dc1, Dc2 fields—Specify the data registers that contain the test values to be compared to the first and second memory operands, respectively. If Dc1 and Dc2 specify the same data register and the comparison fails, memory operand 1 is stored in the data register.
NOTE
The CAS and CAS2 instructions can be used to perform secure update operations on system control data structures in a multiprocessing environment.
In the MC68040 if the operands are not equal, the destination or destination 1 operand is written back to memory to complete the locked access for CAS or CAS2, respectively.
4-68 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
CHK
Check Register Against Bounds
(M68000 Family)
CHK
Operation: If Dn < 0 or Dn > Source
Then TRAP
Assembler
Syntax:
Attributes:
CHK < ea > ,Dn
Size = (Word, Long*)
*(MC68020, MC68030, MC68040 only)
Description: Compares the value in the data register specified in the instruction to zero and to the upper bound (effective address operand). The upper bound is a twos complement integer. If the register value is less than zero or greater than the upper bound, a CHK instruction exception (vector number 6) occurs.
Condition Codes:
X
—
N
∗
Z
U
V
U
C
U
X — Not affected.
N — Set if Dn < 0; cleared if Dn > effective address operand; undefined otherwise.
Z — Undefined.
V — Undefined.
C — Undefined.
Instruction Format:
15
0
14
1
13
0
12
0
11 10
REGISTER
9 8
SIZE
7 6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-69
Integer Instructions
CHK
Check Register Against Bounds
(M68000 Family)
CHK
Instruction Fields:
Register field—Specifies the data register that contains the value to be checked.
Size field—Specifies the size of the operation.
11— Word operation
10— Long operation
Effective Address field—Specifies the upper bound operand. Only data addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
100
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
011
011
011
4-70 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
CHK2
Check Register Against Bounds
(MC68020, MC68030, MC68040, CPU32)
CHK2
Operation: If Rn < LB or Rn > UB
Then TRAP
Assembler
Syntax:
Attributes:
CHK2 < ea > ,Rn
Size = (Byte, Word, Long)
Description: Compares the value in Rn to each bound. The effective address contains the bounds pair: the upper bound following the lower bound. For signed comparisons, the arithmetically smaller value should be used as the lower bound. For unsigned comparisons, the logically smaller value should be the lower bound.
The size of the data and the bounds can be specified as byte, word, or long. If Rn is a data register and the operation size is byte or word, only the appropriate low-order part of Rn is checked. If Rn is an address register and the operation size is byte or word, the bounds operands are sign-extended to 32 bits, and the resultant operands are compared to the full 32 bits of An.
If the upper bound equals the lower bound, the valid range is a single value. If the register value is less than the lower bound or greater than the upper bound, a CHK instruction exception (vector number 6) occurs.
Condition Codes:
X
—
N
U
Z
∗
V
U
C
∗
X — Not affected.
N — Undefined.
Z — Set if Rn is equal to either bound; cleared otherwise.
V — Undefined.
C — Set if Rn is out of bounds; cleared otherwise.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-71
Integer Instructions
CHK2
Check Register Against Bounds
(MC68020, MC68030, MC68040, CPU32)
CHK2
Instruction Format:
15
0
D/A
14
0
13
0
REGISTER
12
0
11
0
1
10
SIZE
9
0 0
8
0
0
7
1
0
Instruction Fields:
Size field—Specifies the size of the operation.
00 — Byte operation
01 — Word operation
10 — Long operation
6
1
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
Effective Address field—Specifies the location of the bounds operands. Only control addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
—
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
010
—
—
101
110
110
Register
—
— reg. number:An
—
— reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
111
111
111
Register
000
001
—
010
011
011
MC68020, MC68030, and MC68040 only
([bd,An,Xn],od) 110 reg. number:An
([bd,An],Xn,od) 110 reg. number:An
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
011
011
D/A field—Specifies whether an address register or data register is to be checked.
0 — Data register
1 — Address register
Register field—Specifies the address or data register that contains the value to be checked.
4-72 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
CLR
Clear an Operand
(M68000 Family)
0
→
Destination
CLR
Operation:
Assembler
Syntax:
Attributes:
CLR < ea >
Size = (Byte, Word, Long)
Description: Clears the destination operand to zero. The size of the operation may be specified as byte, word, or long.
Condition Codes:
X
—
N
0
Z
1
V
0
C
0
X — Not affected.
N — Always cleared.
Z — Always set.
V — Always cleared.
C — Always cleared.
Instruction Format:
15
0
14
1
13
0
12
0
11
0
10
0
9
1
8
0
7
SIZE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-73
Integer Instructions
CLR
Clear an Operand
(M68000 Family)
CLR
Instruction Fields:
Size field—Specifies the size of the operation.
00— Byte operation
01— Word operation
10— Long operation
Effective Address field—Specifies the destination location. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)* 110 reg. number:An
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110 reg. number:An reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
— —
— —
— —
NOTE
In the MC68000 and MC68008 a memory location is read before it is cleared.
4-74 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
CMP
Compare
(M68000 Family)
Destination – Source
→
cc
CMP
Operation:
Assembler
Syntax:
Attributes:
CMP < ea > , Dn
Size = (Byte, Word, Long)
Description: Subtracts the source operand from the destination data register and sets the condition codes according to the result; the data register is not changed. The size of the operation can be byte, word, or long.
Condition Codes:
X
—
N
∗
Z
∗
V
∗
C
∗
X — Not affected.
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if an overflow occurs; cleared otherwise.
C — Set if a borrow occurs; cleared otherwise.
Instruction Format:
15
1
14
0
13
1
12
1
11 10
REGISTER
9 8 7
OPMODE
6
Instruction Fields:
Register field—Specifies the destination data register.
Opmode field
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Byte Word Long
000 001 010
Operation
Dn – < ea >
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-75
Integer Instructions
CMP
Compare
(M68000 Family)
CMP
Effective Address field—Specifies the source operand. All addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An*
000
001
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
100
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)** 110 reg. number:An
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110 reg. number:An reg. number:An
*Word and Long only.
**Can be used with CPU32.
(bd,PC,Xn)†
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111 011
111 011
111 011
NOTE
CMPA is used when the destination is an address register. CMPI is used when the source is immediate data. CMPM is used for memory-to-memory compares. Most assemblers automatically make the distinction.
4-76 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
CMPA
Compare Address
(M68000 Family)
Destination – Source
→
cc
CMPA
Operation:
Assembler
Syntax:
Attributes:
CMPA < ea > , An
Size = (Word, Long)
Description: Subtracts the source operand from the destination address register and sets the condition codes according to the result; the address register is not changed. The size of the operation can be specified as word or long. Word length source operands are sign- extended to 32 bits for comparison.
Condition Codes:
X
—
N
∗
Z
∗
V
∗
C
∗
X — Not affected.
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if an overflow is generated; cleared otherwise.
C — Set if a borrow is generated; cleared otherwise.
Instruction Format:
15
1
14
0
13
1
12
1
11 10
REGISTER
9 8 7
OPMODE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-77
Integer Instructions
CMPA
Compare Address
(M68000 Family)
CMPA
Instruction Fields:
Register field—Specifies the destination address register.
Opmode field—Specifies the size of the operation.
011— Word operation; the source operand is sign-extended to a long operand, and the operation is performed on the address register using all 32 bits.
111— Long operation.
Effective Address field—Specifies the source operand. All addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
001
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
100
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
011
011
011
4-78 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
CMPI
Compare Immediate
(M68000 Family)
Destination – Immediate Data
→
cc
CMPI
Operation:
Assembler
Syntax:
Attributes:
CMPI # < data > , < ea >
Size = (Byte, Word, Long)
Description: Subtracts the immediate data from the destination operand and sets the condition codes according to the result; the destination location is not changed. The size of the operation may be specified as byte, word, or long. The size of the immediate data matches the operation size.
Condition Codes:
X
—
N
∗
Z
∗
V
∗
C
∗
X — Not affected.
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if an overflow occurs; cleared otherwise.
C — Set if a borrow occurs; cleared otherwise.
Instruction Format:
15
0
14
0
13
0
12
0
11
1
16-BIT WORD DATA
10
1
9
0
8
0
7
SIZE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE
8-BIT BYTE DATA
REGISTER
0
32-BIT LONG DATA
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-79
Integer Instructions
CMPI
Compare Immediate
(M68000 Family)
CMPI
Instruction Fields:
Size field—Specifies the size of the operation.
00 — Byte operation
01 — Word operation
10 — Long operation
Effective Address field—Specifies the destination operand. Only data addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)*
(d
8
,PC,Xn)*
111
111
Register
000
001
—
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)**
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110
110 reg. number:An reg. number:An reg. number:An
(bd,PC,Xn)†
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
*PC relative addressing modes do not apply to MC68000, MC680008, or MC6801.
**Can be used with CPU32.
Immediate field—Data immediately following the instruction.
If size = 00, the data is the low-order byte of the immediate word.
If size = 01, the data is the entire immediate word.
If size = 10, the data is the next two immediate words.
011
011
011
4-80 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
CMPM
Compare Memory
(M68000 Family)
Destination – Source
→
cc
CMPM
Operation:
Assembler
Syntax:
Attributes:
CMPM (Ay) + ,(Ax) +
Size = (Byte, Word, Long)
Description: Subtracts the source operand from the destination operand and sets the condition codes according to the results; the destination location is not changed. The operands are always addressed with the postincrement addressing mode, using the address registers specified in the instruction. The size of the operation may be specified as byte, word, or long.
Condition Codes:
X
—
N
∗
Z
∗
V
∗
C
∗
X — Not affected.
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if an overflow is generated; cleared otherwise.
C — Set if a borrow is generated; cleared otherwise.
Instruction Format:
15
1
14
0
13
1
12
1
11 10
REGISTER Ax
9 8
1
7
SIZE
6 5
0
4
0
3
1
2 1
REGISTER Ay
0
Instruction Fields:
Register Ax field—(always the destination) Specifies an address register in the postincrement addressing mode.
Size field—Specifies the size of the operation.
00 — Byte operation
01 — Word operation
10 — Long operation
Register Ay field—(always the source) Specifies an address register in the postincrement addressing mode.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-81
Integer Instructions
CMP2
Compare Register Against Bounds
(MC68020, MC68030, MC68040, CPU32)
CMP2
Operation:
Assembler
Syntax:
Attributes:
Compare Rn < LB or Rn > UB and Set Condition Codes
CMP2 < ea > ,Rn
Size = (Byte, Word, Long)
Description: Compares the value in Rn to each bound. The effective address contains the bounds pair: upper bound following the lower bound. For signed comparisons, the arithmetically smaller value should be used as the lower bound. For unsigned comparisons, the logically smaller value should be the lower bound.
The size of the data and the bounds can be specified as byte, word, or long. If Rn is a data register and the operation size is byte or word, only the appropriate low-order part of Rn is checked. If Rn is an address register and the operation size is byte or word, the bounds operands are sign-extended to 32 bits, and the resultant operands are compared to the full 32 bits of An.
If the upper bound equals the lower bound, the valid range is a single value.
NOTE
This instruction is identical to CHK2 except that it sets condition codes rather than taking an exception when the value in Rn is out of bounds.
Condition Codes:
X
—
N
U
Z
∗
V
U
C
∗
X — Not affected.
N — Undefined.
Z — Set if Rn is equal to either bound; cleared otherwise.
V — Undefined.
C — Set if Rn is out of bounds; cleared otherwise.
4-82 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
CMP2
Compare Register Against Bounds
(MC68020, MC68030, MC68040, CPU32)
Integer Instructions
CMP2
Instruction Format:
15
0
D/A
14
0
13
0
REGISTER
12
0
11
0
0
10
SIZE
9
0 0
8
0
0
7
1
0
Instruction Fields:
Size field—Specifies the size of the operation.
00 — Byte operation
01 — Word operation
10 — Long operation
6
1
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
Effective Address field—Specifies the location of the bounds pair. Only control addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
—
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
010
—
—
101
110
110
Register
—
— reg. number:An
—
— reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
111
111
111
Register
000
001
—
010
011
011
MC68020, MC68030, and MC68040 only
([bd,An,Xn],od) 110 reg. number:An
([bd,An],Xn,od) 110 reg. number:An
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
011
011
D/A field—Specifies whether an address register or data register is compared.
0 — Data register
1 — Address register
Register field—Specifies the address or data register that contains the value to be checked.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-83
Integer Instructions cpBcc
Branch on Coprocessor Condition
(MC68020, MC68030) cpBcc
Operation: If cpcc True
Then Scan PC + d n
→
PC
Assembler
Syntax:
Attributes: cpBcc < label >
Size = (Word, Long)
Description: If the specified coprocessor condition is true, program execution continues at location scan PC + displacement. The value of the scan PC is the address of the first displacement word. The displacement is a twos complement integer that represents the relative distance in bytes from the scan PC to the destination program counter. The displacement can be either 16 or 32 bits. The coprocessor determines the specific condition from the condition field in the operation word.
Condition Codes:
Not affected.
Instruction Format:
15
1
14
1
13
1
12
1
11 10 9
COPROCESSOR
ID
8
0
7
1
6
SIZE
5 4 3 2 1
COPROCESSOR CONDITION
OPTIONAL COPROCESSOR-DEFINED EXTENSION WORDS
WORD OR
LONG-WORD DISPLACEMENT
0
Instruction Fields:
Coprocessor ID field—Identifies the coprocessor for this operation. Coprocessor ID of
000 results in an F-line exception for the MC68030.
Size field—Specifies the size of the displacement.
0 — The displacement is 16 bits.
1 — The displacement is 32 bits.
Coprocessor Condition field—Specifies the coprocessor condition to be tested. This field is passed to the coprocessor, which provides directives to the main processor for processing this instruction.
16-Bit Displacement field—The displacement value occupies 16 bits.
32-Bit Displacement field—The displacement value occupies 32 bits.
4-84 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions cpDBcc
Test Coprocessor Condition
Decrement and Branch
(MC68020, MC68030) cpDBcc
Operation: If cpcc False
Then (Dn – 1
→
Dn; If Dn
≠
– 1 Then Scan PC + d n
→
PC)
Assembler
Syntax:
Attributes: cpDBcc Dn, < label >
Size = (Word)
Description: If the specified coprocessor condition is true, execution continues with the next instruction. Otherwise, the low-order word in the specified data register is decremented by one. If the result is equal to – 1, execution continues with the next instruction. If the result is not equal to – 1, execution continues at the location indicated by the value of the scan PC plus the sign-extended 16-bit displacement. The value of the scan PC is the address of the displacement word. The displacement is a twos complement integer that represents the relative distance in bytes from the scan PC to the destination program counter. The coprocessor determines the specific condition from the condition word that follows the operation word.
Condition Codes:
Not affected.
Instruction Format:
15
1
0
14
1
0
13
1
0
12
1
0
11 10 9
COPROCESSOR
ID
8
0
7
0
6
1
5
0
4
0
3
1
2 1
REGISTER
0 0 0 0 0 0 COPROCESSOR CONDITION
OPTIONAL COPROCESSOR-DEFINED EXTENSION WORDS
16-BIT DISPLACEMENT
0
Instruction Fields:
Coprocessor ID field—Identifies the coprocessor for this operation; coprocessor ID of
000 results in an F-line exception for the MC68030.
Register field—Specifies the data register used as the counter.
Coprocessor Condition field—Specifies the coprocessor condition to be tested. This field is passed to the coprocessor, which provides directives to the main processor for processing this instruction.
Displacement field—Specifies the distance of the branch (in bytes).
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-85
Integer Instructions cpGEN
Coprocessor General Function
(MC68020, MC68030) cpGEN
Operation:
Assembler
Syntax:
Attributes:
Pass Command Word to Coprocessor cpGEN < parameters as defined by coprocessor >
Unsized
Description: Transfers the command word that follows the operation word to the specified coprocessor. The coprocessor determines the specific operation from the command word. Usually a coprocessor defines specific instances of this instruction to provide its instruction set.
Condition Codes:
May be modified by coprocessor; unchanged otherwise.
Instruction Format:
15
1
14
1
13
1
12
1
11 10 9
COPROCESSOR
ID
8
0
7
0
6
0
5
COPROCESSOR-DEPENDENT COMMAND WORD
4
MODE
3 2
EFFECTIVE ADDRESS
1
REGISTER
OPTIONAL EFFECTIVE ADDRESS OR COPROCESSOR-DEFINED EXTENSIONWORDS
0
Instruction Fields:
Coprocessor ID field—Identifies the coprocessor for this operation; note that coprocessor ID of 000 is reserved for MMU instructions for the MC68030.
Effective Address field—Specifies the location of any operand not resident in the coprocessor. The allowable addressing modes are determined by the operation to be performed.
Coprocessor Command field—Specifies the coprocessor operation to be performed.
This word is passed to the coprocessor, which in turn provides directives to the main processor for processing this instruction.
4-86 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions cpScc
Set on Coprocessor Condition
(MC68020, MC68030) cpScc
Operation: If cpcc True
Then 1s
→
Destination
Else 0s
→
Destination
Assembler
Syntax:
Attributes: cpScc < ea >
Size = (Byte)
Description: Tests the specified coprocessor condition code. If the condition is true, the byte specified by the effective address is set to TRUE (all ones); otherwise, that byte is set to FALSE (all zeros). The coprocessor determines the specific condition from the condition word that follows the operation word.
Condition Codes:
Not affected.
Instruction Format:
15
1
0
14
1
0
13
1
0
12 11 10 9 8 7 6 5 4 3 2
EFFECTIVE ADDRESS
1
1
COPROCESSOR
ID
0 0 1
MODE
0 0 0 0 0 0 0
OPTIONAL EFFECTIVE ADDRESS OR COPROCESSOR-DEFINED EXTENSIONWORDS
REGISTER
COPROCESSOR CONDITION
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-87
Integer Instructions cpScc
Set on Coprocessor Condition
(MC68020, MC68030) cpScc
Instruction Fields:
Coprocessor ID field—Identifies the coprocessor for this operation. Coprocessor ID of
000 results in an F-line exception for the MC68030.
Effective Address field—Specifies the destination location. Only data alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110
110
110
010
011
100
101
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
Register
000
001
—
—
—
—
—
—
Coprocessor Condition field—Specifies the coprocessor condition to be tested. This field is passed to the coprocessor, which in turn provides directives to the main processor for processing this instruction.
4-88 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions cpTRAPcc
Trap on Coprocessor Condition
cpTRAPcc
(MC68020, MC68030)
Operation:
Assembler
Syntax:
Attributes:
If cpcc True
Then TRAP cpTRAPcc cpTRAPcc # < data >
Unsized or Size = (Word, Long)
Description: Tests the specified coprocessor condition code; if the selected coprocessor condition is true, the processor initiates a cpTRAPcc exception, vector number 7. The program counter value placed on the stack is the address of the next instruction. If the selected condition is not true, no operation is performed, and execution continues with the next instruction. The coprocessor determines the specific condition from the condition word that follows the operation word. Following the condition word is a userdefined data operand specified as immediate data to be used by the trap handler.
Condition Codes:
Not affected.
Instruction Format:
15
1
0
14
1
0
13
1
0
12
1
0
11 10 9
COPROCESSOR
ID
8
0
7
0
6
1
5
1
4
1
3
1
2 1
OPMODE
0 0 0 0 0 0 COPROCESSOR CONDITION
OPTIONAL COPROCESSOR-DEFINED EXTENSION WORDS
OPTIONAL WORD
OR LONG-WORD OPERAND
0
Instruction Fields:
Coprocessor ID field—Identifies the coprocessor for this operation; coprocessor ID of
000 results in an F-line exception for the MC68030.
Opmode field—Selects the instruction form.
010— Instruction is followed by one operand word.
011— Instruction is followed by two operand words.
100— Instruction has no following operand words.
Coprocessor Condition field—Specifies the coprocessor condition to be tested. This field is passed to the coprocessor, which provides directives to the main processor for processing this instruction.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-89
Integer Instructions
DBcc
Test Condition, Decrement, and Branch
DBcc
(M68000 Family)
Operation: If Condition False
Then (Dn – 1
→
Dn; If Dn
≠
– 1 Then PC + d n
→
PC)
Assembler
Syntax:
Attributes:
DBcc Dn, < label >
Size = (Word)
Description: Controls a loop of instructions. The parameters are a condition code, a data register (counter), and a displacement value. The instruction first tests the condition for termination; if it is true, no operation is performed. If the termination condition is not true, the low-order 16 bits of the counter data register decrement by one. If the result is – 1, execution continues with the next instruction. If the result is not equal to – 1, execution continues at the location indicated by the current value of the program counter plus the sign-extended 16-bit displacement. The value in the program counter is the address of the instruction word of the DBcc instruction plus two. The displacement is a twos complement integer that represents the relative distance in bytes from the current program counter to the destination program counter. Condition code cc specifies one of the following conditional tests (refer to Table 3-19 for more information on these conditional tests):
Mnemonic
CC(HI)
CS(LO)
EQ
F
GE
GT
HI
LE
Condition Codes:
Not affected.
Condition
Carry Clear
Carry Set
Equal
False
Greater or Equal
Greater Than
High
Less or Equal
Mnemonic
PL
T
VC
VS
LS
LT
MI
NE
Condition
Low or Same
Less Than
Minus
Not Equal
Plus
True
Overflow Clear
Overflow Set
4-90 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
DBcc
Test Condition, Decrement, and Branch
DBcc
(M68000 Family)
Instruction Format:
15
0
14
1
13
0
12
1
11 10 9
CONDITION
8 7
1
16-BIT DISPLACEMENT
6
1
5
0
4
0
3
1
2 1
REGISTER
0
Instruction Fields:
Condition field—The binary code for one of the conditions listed in the table.
Register field—Specifies the data register used as the counter.
Displacement field—Specifies the number of bytes to branch.
NOTE
The terminating condition is similar to the UNTIL loop clauses of high-level languages. For example: DBMI can be stated as
"decrement and branch until minus".
Most assemblers accept DBRA for DBF for use when only a count terminates the loop (no condition is tested).
A program can enter a loop at the beginning or by branching to the trailing DBcc instruction. Entering the loop at the beginning is useful for indexed addressing modes and dynamically specified bit operations. In this case, the control index count must be one less than the desired number of loop executions.
However, when entering a loop by branching directly to the trailing DBcc instruction, the control count should equal the loop execution count. In this case, if a zero count occurs, the DBcc instruction does not branch, and the main loop is not executed.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-91
Integer Instructions
DIVS, DIVSL
Signed Divide
(M68000 Family)
Operation:
Assembler
Syntax:
DIVS, DIVSL
Destination
÷
Source
→
Destination
DIVS.W < ea > ,Dn32/16
→
16r – 16q
*DIVS.L < ea > ,Dq 32/32
→
32q
*DIVS.L < ea > ,Dr:Dq 64/32
→
32r – 32q
*DIVSL.L < ea > ,Dr:Dq 32/32
→
32r – 32q
*Applies to MC68020, MC68030, MC68040, CPU32 only
Attributes: Size = (Word, Long)
Description: Divides the signed destination operand by the signed source operand and stores the signed result in the destination. The instruction uses one of four forms. The word form of the instruction divides a long word by a word. The result is a quotient in the lower word (least significant 16 bits) and a remainder in the upper word (most significant 16 bits). The sign of the remainder is the same as the sign of the dividend.
The first long form divides a long word by a long word. The result is a long quotient; the remainder is discarded.
The second long form divides a quad word (in any two data registers) by a long word.
The result is a long-word quotient and a long-word remainder.
The third long form divides a long word by a long word. The result is a long-word quotient and a long-word remainder.
Two special conditions may arise during the operation:
1. Division by zero causes a trap.
2. Overflow may be detected and set before the instruction completes. If the instruction detects an overflow, it sets the overflow condition code, and the operands are unaffected.
Condition Codes:
X
—
N
∗
Z
∗
V
∗
C
0
X—Not affected.
N — Set if the quotient is negative; cleared otherwise; undefined if overflow or divide by zero occurs.
Z — Set if the quotient is zero; cleared otherwise; undefined if overflow or divide by zero occurs.
V — Set if division overflow occurs; undefined if divide by zero occurs; cleared otherwise.
C — Always cleared.
4-92 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
DIVS, DIVSL
Signed Divide
(M68000 Family)
Instruction Format:
WORD
Integer Instructions
DIVS, DIVSL
15
1
14
0
13
0
12
0
11 10
REGISTER
9 8
1
7
1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields:
Register field—Specifies any of the eight data registers. This field always specifies the destination operand.
Effective Address field—Specifies the source operand. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
100
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
011
011
011
NOTE
Overflow occurs if the quotient is larger than a 16-bit signed integer.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-93
Integer Instructions
DIVS, DIVSL
Signed Divide
(M68000 Family)
Instruction Format:
LONG
DIVS, DIVSL
15
0
0
14
1
13
0
REGISTER Dq
12
0
11
1
1
10
1
SIZE
9
0
0
8
0
0
7
0
0
6
1
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0
REGISTER
REGISTER Dr
0
Instruction Fields:
Effective Address field—Specifies the source operand. Only data alterable addressing modes can be used as listed in the following tables:
MC68020, MC68030, and MC68040 only
Addressing Mode Mode Register
Dn
An
000
— reg. number:Dn
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
010
011
100
101
110
110 reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
111
111
111
Register
000
001
100
010
011
011
MC68020, MC68030, and MC68040 only
([bd,An,Xn],od) 110 reg. number:An
([bd,An],Xn,od) 110 reg. number:An
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
011
011
Register Dq field—Specifies a data register for the destination operand. The low-order
32 bits of the dividend comes from this register, and the 32-bit quotient is loaded into this register.
Size field—Selects a 32- or 64-bit division operation.
0 — 32-bit dividend is in register Dq.
1 — 64-bit dividend is in Dr – Dq.
4-94 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
DIVS, DIVSL
Signed Divide
(M68000 Family)
DIVS, DIVSL
Register Dr field—After the division, this register contains the 32-bit remainder. If Dr and Dq are the same register, only the quotient is returned. If the size field is 1, this field also specifies the data register that contains the high-order 32 bits of the dividend.
NOTE
Overflow occurs if the quotient is larger than a 32-bit signed integer.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-95
Integer Instructions
DIVU, DIVUL
Unsigned Divide
DIVU, DIVUL
(M68000 Family)
Operation:
Assembler
Syntax:
Destination
÷
Source
→
Destination
DIVU.W < ea > ,Dn32/16
→
16r – 16q
*DIVU.L < ea > ,Dq 32/32
→
32q
*DIVU.L < ea > ,Dr:Dq 64/32
→
32r – 32q
*DIVUL.L < ea > ,Dr:Dq 32/32
→
32r – 32q
*Applies to MC68020, MC68030, MC68040, CPU32 only.
Attributes: Size = (Word, Long)
Description: Divides the unsigned destination operand by the unsigned source operand and stores the unsigned result in the destination. The instruction uses one of four forms. The word form of the instruction divides a long word by a word. The result is a quotient in the lower word (least significant 16 bits) and a remainder in the upper word (most significant 16 bits).
The first long form divides a long word by a long word. The result is a long quotient; the remainder is discarded.
The second long form divides a quad word (in any two data registers) by a long word.
The result is a long-word quotient and a long-word remainder.
The third long form divides a long word by a long word. The result is a long-word quotient and a long-word remainder.
Two special conditions may arise during the operation:
1. Division by zero causes a trap.
2. Overflow may be detected and set before the instruction completes. If the instruction detects an overflow, it sets the overflow condition code, and the operands are unaffected.
Condition Codes:
X
—
N
∗
Z
∗
V
∗
C
0
X — Not affected.
N — Set if the quotient is negative; cleared otherwise; undefined if overflow or divide by zero occurs.
Z — Set if the quotient is zero; cleared otherwise; undefined if overflow or divide by zero occurs.
V — Set if division overflow occurs; cleared otherwise; undefined if divide by zero occurs.
C — Always cleared.
4-96 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
DIVU, DIVUL
Unsigned Divide
DIVU, DIVUL
(M68000 Family)
Instruction Format:
WORD
15
1
14
0
13
0
12
0
11 10
REGISTER
9 8
0
7
1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields:
Register field—Specifies any of the eight data registers; this field always specifies the destination operand.
Effective Address field—Specifies the source operand. Only data addressing modes can be used as listed in the following tables:
MC68020, MC68030, and MC68040 only
Addressing Mode Mode Register
Dn
An
000
— reg. number:Dn
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110 reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
100
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
**Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
NOTE
Overflow occurs if the quotient is larger than a 16-bit signed integer.
011
011
011
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-97
Integer Instructions
DIVU, DIVUL
Unsigned Divide
DIVU, DIVUL
(M68000 Family)
Instruction Format:
LONG
15
0
0
14
1
13
0
REGISTER Dq
12
0
11
1
0
10
1
SIZE
9
0
0
8
0
0
7
0
0
6
1
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0
REGISTER
REGISTER Dr
0
Instruction Fields:
Effective Address field—Specifies the source operand. Only data addressing modes can be used as listed in the following tables:
MC68020, MC68030, and MC68040 only
Addressing Mode Mode Register
Dn
An
000
— reg. number:Dn
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)*
010
011
100
101
110
110 reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)*
111
111
111
Register
000
001
100
010
011
011
MC68020, MC68030, and MC68040 only
([bd,An,Xn],od) 110 reg. number:An
([bd,An],Xn,od) 110 reg. number:An
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
011
011
Register Dq field—Specifies a data register for the destination operand. The low-order
32 bits of the dividend comes from this register, and the 32-bit quotient is loaded into this register.
Size field—Selects a 32- or 64-bit division operation.
0 — 32-bit dividend is in register Dq.
1 — 64-bit dividend is in Dr – Dq.
4-98 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
DIVU, DIVUL
Unsigned Divide
DIVU, DIVUL
(M68000 Family)
Register Dr field—After the division, this register contains the 32-bit remainder. If Dr and Dq are the same register, only the quotient is returned. If the size field is 1, this field also specifies the data register that contains the high-order 32 bits of the dividend.
NOTE
Overflow occurs if the quotient is larger than a 32-bit unsigned integer.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-99
Integer Instructions
EOR
Exclusive-OR Logical
(M68000 Family)
Source
⊕
Destination
→
Destination
EOR
Operation:
Assembler
Syntax:
Attributes:
EOR Dn, < ea >
Size = (Byte, Word, Long)
Description: Performs an exclusive-OR operation on the destination operand using the source operand and stores the result in the destination location. The size of the operation may be specified to be byte, word, or long. The source operand must be a data register. The destination operand is specified in the effective address field.
Condition Codes:
X
—
N
∗
Z
∗
V
0
C
0
X — Not affected.
N — Set if the most significant bit of the result is set; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
WORD
15
1
14
0
13
1
12
1
11 10
REGISTER
9 8 7
OPMODE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields:
Register field—Specifies any of the eight data registers.
Opmode field
Byte Word Long
100 101 110
Operation
< ea >
⊕
Dn
→
< ea >
4-100 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
EOR
Exclusive-OR Logical
(M68000 Family)
EOR
Effective Address field—Specifies the destination ope data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
NOTE
Memory-to-data-register operations are not allowed. Most assemblers use EORI when the source is immediate data.
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-101
Integer Instructions
EORI
Exclusive-OR Immediate
(M68000 Family)
Immediate Data
⊕
Destination
→
Destination
EORI
Operation:
Assembler
Syntax:
Attributes:
EORI # < data > , < ea >
Size = (Byte, Word, Long)
Description: Performs an exclusive-OR operation on the destination operand using the immediate data and the destination operand and stores the result in the destination location. The size of the operation may be specified as byte, word, or long. The size of the immediate data matches the operation size.
Condition Codes:
X
—
N
∗
Z
∗
V
0
C
0
X — Not affected.
N — Set if the most significant bit of the result is set; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
15
0
14
0
13
0
12
0
11
1
16-BIT WORD DATA
10
0
9
1
8
0
7
SIZE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE
8-BIT BYTE DATA
REGISTER
0
32-BIT LONG DATA
4-102 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
EORI
Exclusive-OR Immediate
(M68000 Family)
EORI
Instruction Fields:
Size field—Specifies the size of the operation.
00— Byte operation
01— Word operation
10— Long operation
Effective Address field—Specifies the destination operand. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
Immediate field—Data immediately following the instruction.
If size = 00, the data is the low-order byte of the immediate word.
If size = 01, the data is the entire immediate word.
If size = 10, the data is next two immediate words.
—
—
—
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-103
Integer Instructions
EORI to CCR
Exclusive-OR Immediate to Condition Code
(M68000 Family)
Source
⊕
CCR
→
CCR
EORI to CCR
Operation:
Assembler
Syntax:
Attributes:
EORI # < data > ,CCR
Size = (Byte)
Description: Performs an exclusive-OR operation on the condition code register using the immediate operand and stores the result in the condition code register (low-order byte of the status register). All implemented bits of the condition code register are affected.
Condition Codes:
X
∗
N
∗
Z
∗
V
∗
C
∗
X — Changed if bit 4 of immediate operand is one; unchanged otherwise.
N — Changed if bit 3 of immediate operand is one; unchanged otherwise.
Z — Changed if bit 2 of immediate operand is one; unchanged otherwise.
V — Changed if bit 1 of immediate operand is one; unchanged otherwise.
C — Changed if bit 0 of immediate operand is one; unchanged otherwise.
Instruction Format:
15
0
0
14
0
0
13
0
0
12
0
0
11
1
0
10
0
0
9
1
0
8
0
0
7
0
6
0
5
1
4
1
3
1
8-BIT BYTE DATA
2
1
1
0
0
0
4-104 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
EXG
Operation:
Assembler
Syntax:
Attributes:
Rx
←→
Ry
Exchange Registers
(M68000 Family)
EXG Dx,Dy
EXG Ax,Ay EXG Dx,Ay
EXG
Size = (Long)
Description: Exchanges the contents of two 32-bit registers. The instruction performs three types of exchanges.
1. Exchange data registers.
2. Exchange address registers.
3. Exchange a data register and an address register.
Condition Codes:
Not affected.
Instruction Format:
15
1
14
1
13
0
12
0
11 10
REGISTER Rx
9 8
1
7 6 5
OPMODE
4 3 2 1
REGISTER Ry
0
Instruction Fields:
Register Rx field—Specifies either a data register or an address register depending on the mode. If the exchange is between data and address registers, this field always specifies the data register.
Opmode field—Specifies the type of exchange.
01000—Data registers
01001—Address registers
10001—Data register and address register
Register Ry field—Specifies either a data register or an address register depending on the mode. If the exchange is between data and address registers, this field always specifies the address register.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-105
Integer Instructions
EXT, EXTB
Operation:
Sign-Extend
(M68000 Family)
Destination Sign-Extended
→
Destination
Assembler
Syntax:
EXT, EXTB
EXT.W Dnextend byte to word
EXT.L Dnextend word to long word
EXTB.L Dnextend byte to long word (MC68020, MC68030
MC68040, CPU32)
Attributes: Size = (Word, Long)
Description: Extends a byte in a data register to a word or a long word, or a word in a data register to a long word, by replicating the sign bit to the left. If the operation extends a byte to a word, bit 7 of the designated data register is copied to bits 15 – 8 of that data register. If the operation extends a word to a long word, bit 15 of the designated data register is copied to bits 31 – 16 of the data register. The EXTB form copies bit 7 of the designated register to bits 31 – 8 of the data register.
Condition Codes:
X
—
N
∗
Z
∗
V
0
C
0
X — Not affected.
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
0
9
0
8 7
OPMODE
6 5
0
4
0
Instruction Fields:
Opmode field—Specifies the size of the sign-extension operation.
010— Sign-extend low-order byte of data register to word.
011— Sign-extend low-order word of data register to long.
111— Sign-extend low-order byte of data register to long.
3
0
Register field—Specifies the data register is to be sign-extended.
2 1
REGISTER
0
4-106 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
ILLEGAL
Take Illegal Instruction Trap
ILLEGAL
(M68000 Family)
Operation: *SSP – 2
→
SSP; Vector Offset
→
(SSP);
SSP – 4
→
SSP; PC
→
(SSP);
SSP – 2
→
SSP; SR
→
(SSP);
Illegal Instruction Vector Address
→
PC
*The MC68000 and MC68008 cannot write the vector offset and format code to the system stack.
Assembler
Syntax:
Attributes:
ILLEGAL
Unsized
Description: Forces an illegal instruction exception, vector number 4. All other illegal instruction bit patterns are reserved for future extension of the instruction set and should not be used to force an exception.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
0
9
1
8
0
7
1
6
1
5
1
4
1
3
1
2
1
1
0
0
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-107
Integer Instructions
JMP
Jump
(M68000 Family)
Destination Address
→
PC
JMP
Operation:
Assembler
Syntax:
Attributes:
JMP < ea >
Unsized
Description: Program execution continues at the effective address specified by the instruction. The addressing mode for the effective address must be a control addressing mode.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Field:
Effective Address field—Specifies the address of the next instruction. Only control addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
—
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
—
—
101
110
Register
—
— reg. number:An
—
— reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
—
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
011
011
011
4-108 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
JSR
Jump to Subroutine
(M68000 Family)
SP – 4
→
Sp; PC
→
(SP); Destination Address
→
PC
JSR
Operation:
Assembler
Syntax:
Attributes:
JSR < ea >
Unsized
Description: Pushes the long-word address of the instruction immediately following the
JSR instruction onto the system stack. Program execution then continues at the address specified in the instruction.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
1
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Field:
Effective Address field—Specifies the address of the next instruction. Only control addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
—
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
—
—
101
110
Register
—
— reg. number:An
—
— reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
—
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
011
011
011
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-109
Integer Instructions
LEA
Load Effective Address
(M68000 Family)
< ea >
→
An
LEA
Operation:
Assembler
Syntax:
Attributes:
LEA < ea > ,An
Size = (Long)
Description: Loads the effective address into the specified address register. All 32 bits of the address register are affected by this instruction.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11 10
REGISTER
9 8
1
7
1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields:
Register field—Specifies the address register to be updated with the effective address.
Effective Address field—Specifies the address to be loaded into the address register.
Only control addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
—
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
—
—
101
110
Register
—
— reg. number:An
—
— reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
—
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
011
011
011
4-110 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
LINK
Link and Allocate
(M68000 Family)
SP – 4
→
SP; An
→
(SP); SP
→
An; SP + d n
→
SP
LINK
Operation:
Assembler
Syntax:
Attributes:
LINK An, # < displacement >
Size = (Word, Long*)
*MC68020, MC68030, MC68040 and CPU32 only.
Description: Pushes the contents of the specified address register onto the stack. Then loads the updated stack pointer into the address register. Finally, adds the displacement value to the stack pointer. For word-size operation, the displacement is the sign-extended word following the operation word. For long size operation, the displacement is the long word following the operation word. The address register occupies one long word on the stack. The user should specify a negative displacement in order to allocate stack area.
Condition Codes:
Not affected.
Instruction Format:
WORD
15
0
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
0
WORD DISPLACEMENT
6
1
5
0
4
1
3
0
2 1
REGISTER
0
Instruction Format:
15
0
14
1
13
0
12
0
11
1
LONG
10
0
9
0
8
0
7
0
6
0
HIGH-ORDER DISPLACEMENT
LOW-ORDER DISPLACEMENT
5
0
4
0
3
1
2 1
REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-111
Integer Instructions
LINK
Link and Allocate
(M68000 Family)
LINK
Instruction Fields:
Register field—Specifies the address register for the link.
Displacement field—Specifies the twos complement integer to be added to the stack pointer.
NOTE
LINK and UNLK can be used to maintain a linked list of local data and parameter areas on the stack for nested subroutine calls.
4-112 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
LSL, LSR
Operation:
Logical Shift
(M68000 Family)
Destination Shifted By Count
→
Destination
Assembler
Syntax:
LSd Dx,Dy
LSd # < data > ,Dy
LSd < ea > where d is direction, L or R
LSL, LSR
Attributes: Size = (Byte, Word, Long)
Description: Shifts the bits of the operand in the direction specified (L or R). The carry bit receives the last bit shifted out of the operand. The shift count for the shifting of a register is specified in two different ways:
1. Immediate—The shift count (1 – 8) is specified in the instruction.
2. Register—The shift count is the value in the data register specified in the instruction modulo 64.
The size of the operation for register destinations may be specified as byte, word, or long. The contents of memory, < ea > , can be shifted one bit only, and the operand size is restricted to a word.
The LSL instruction shifts the operand to the left the number of positions specified as the shift count. Bits shifted out of the high-order bit go to both the carry and the extend bits; zeros are shifted into the low-order bit.
.
C OPERAND O
LSL:
X
The LSR instruction shifts the operand to the right the number of positions specified as the shift count. Bits shifted out of the low-order bit go to both the carry and the extend bits; zeros are shifted into the high-order bit.
.
O OPERAND C
LSR:
X
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-113
Integer Instructions
LSL, LSR
Logical Shift
(M68000 Family)
LSL, LSR
Condition Codes:
X
∗
N
∗
Z
∗
V
0
C
∗
X — Set according to the last bit shifted out of the operand; unaffected for a shift count of zero.
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Always cleared.
C — Set according to the last bit shifted out of the operand; cleared for a shift count of zero.
Instruction Format:
REGISTER SHIFTS
15
1
14
1
13
1
12
0
11 10
COUNT/
REGISTER
9 8 dr
7
SIZE
6 5 i/r
4
0
3
1
2 1
REGISTER
0
Instruction Fields:
Count/Register field
If i/r = 0, this field contains the shift count. The values 1 – 7 represent shifts of 1 – 7; value of zero specifies a shift count of eight.
If i/r = 1, the data register specified in this field contains the shift count (modulo 64). dr field—Specifies the direction of the shift.
0 — Shift right
1 — Shift left
Size field—Specifies the size of the operation.
00 — Byte operation
01 — Word operation
10 — Long operation i/r field
If i/r = 0, specifies immediate shift count.
If i/r = 1, specifies register shift count.
Register field—Specifies a data register to be shifted.
4-114 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
LSL, LSR
Logical Shift
(M68000 Family)
Integer Instructions
LSL, LSR
Instruction Format:
MEMORY SHIFTS
15
1
14
1
13
1
12
0
11
0
10
0
9
1
8 dr
7
1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields: dr field—Specifies the direction of the shift.
0 — Shift right
1 — Shift left
Effective Address field—Specifies the operand to be shifted. Only memory alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
—
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register
—
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-115
Integer Instructions
MOVE
Move Data from Source to Destination
MOVE
(M68000 Family)
Operation: Source
→
Destination
Assembler
Syntax: MOVE < ea > , < ea >
Attributes: Size = (Byte, Word, Long)
Description: Moves the data at the source to the destination location and sets the condition codes according to the data. The size of the operation may be specified as byte, word, or long. Condition Codes:
X
—
N
∗
Z
∗
V
0
C
0
X — Not affected.
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
15
0
14
0
13
SIZE
12 11 10
REGISTER
9 8
DESTINATION
7
MODE
6 5
Instruction Fields:
Size field—Specifies the size of the operand to be moved.
01 — Byte operation
11 — Word operation
10 — Long operation
4
MODE
3 2
SOURCE
1
REGISTER
0
4-116 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
MOVE
Move Data from Source to Destination
MOVE
(M68000 Family)
Destination Effective Address field—Specifies the destination location. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-117
Integer Instructions
MOVE
Move Data from Source to Destination
MOVE
(M68000 Family)
Source Effective Address field—Specifies the source operand. All addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
001
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
100
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)**
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110
110 reg. number:An reg. number:An reg. number:An
(bd,PC,Xn)**
([bd,PC,Xn],od)
([bd,PC],Xn,od)
*For byte size operation, address register direct is not allowed.
**Can be used with CPU32.
111 011
111 011
111 011
NOTE
Most assemblers use MOVEA when the destination is an address register.
MOVEQ can be used to move an immediate 8-bit value to a data register.
4-118 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
MOVEA
Move Address
(M68000 Family)
Source
→
Destination
MOVEA
Operation:
Assembler
Syntax:
Attributes:
MOVEA < ea > ,An
Size = (Word, Long)
Description: Moves the contents of the source to the destination address register. The size of the operation is specified as word or long. Word-size source operands are signextended to 32-bit quantities.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
0
13
SIZE
12 11 10
DESTINATION
REGISTER
9 8
0
7
0
6
1
5 4 3 2
SOURCE
1
REGISTER
0
MODE
Instruction Fields:
Size field—Specifies the size of the operand to be moved.
11 — Word operation; the source operand is sign-extended to a long operand and all 32 bits are loaded into the address register.
10 — Long operation.
Destination Register field—Specifies the destination address register.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-119
Integer Instructions
MOVEA
Move Address
(M68000 Family)
MOVEA
Effective Address field—Specifies the location of the source operand. All addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
001
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
100
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
011
011
011
4-120 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
MOVE from CCR
Move from the
Condition Code Register
(MC68010, MC68020, MC68030, MC68040, CPU32)
MOVE from CCR
Operation: CCR
→
Destination
Assembler
Syntax:
Attributes:
MOVE CCR, < ea >
Size = (Word)
Description: Moves the condition code bits (zero-extended to word size) to the destination location. The operand size is a word. Unimplemented bits are read as zeros.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11
0
10
0
9
1
8
0
7
1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-121
Integer Instructions
MOVE from CCR
Move from the
Condition Code Register
(MC68010, MC68020, MC68030, MC68040, CPU32)
MOVE from CCR
Instruction Field:
Effective Address field—Specifies the destination location. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn 000
An
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
—
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
111
(xxx).L
#<data>
111
—
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)* 110 reg. number:An
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110 reg. number:An reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
NOTE
MOVE from CCR is a word operation. ANDI, ORI, and EORI to
CCR are byte operations.
—
—
—
4-122 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
MOVE to CCR
Move to Condition Code Register
(M68000 Family)
Operation: Source
→
CCR
MOVE to CCR
Assembler
Syntax:
Attributes:
MOVE < ea > ,CCR
Size = (Word)
Description: Moves the low-order byte of the source operand to the condition code register.
The upper byte of the source operand is ignored; the upper byte of the status register is not altered.
Condition Codes:
X
∗
N
∗
Z
∗
V
∗
C
∗
X — Set to the value of bit 4 of the source operand.
N — Set to the value of bit 3 of the source operand.
Z — Set to the value of bit 2 of the source operand.
V — Set to the value of bit 1 of the source operand.
C — Set to the value of bit 0 of the source operand.
Instruction Format:
15
0
14
1
13
0
12
0
11
0
10
1
9
0
8
0
7
1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-123
Integer Instructions
MOVE to CCR
Move to Condition Code Register
(M68000 Family)
MOVE to CCR
Instruction Field:
Effective Address field—Specifies the location of the source operand. Only data addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn 000
An
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
—
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
111
(xxx).L
#<data>
111
111
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
100
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)* 110 reg. number:An
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110 reg. number:An reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
NOTE
MOVE to CCR is a word operation. ANDI, ORI, and EORI to
CCR are byte operations.
011
011
011
4-124 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
MOVE MOVE from SR
Move from the Status Register
from SR
(MC68000, MC68008)
Operation: SR
→
Destination
Assembler
Syntax:
Attributes:
MOVE SR, < ea >
Size = (Word)
Description: Moves the data in the status register to the destination location. The destination is word length. Unimplemented bits are read as zeros.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11
0
10
0
9
0
8
0
7
1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields:
Effective Address field—Specifies the destination location. Only data alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn 000
An
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
—
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
111
(xxx).L
#<data>
111
—
(d
16
,PC)
(d
8
,PC,Xn)
—
—
NOTE
Use the MOVE from CCR instruction to access only the condition codes. Memory destination is read before it is written to.
Register
000
001
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-125
Integer Instructions
MOVE16
Operation:
Move 16-Byte Block
(MC68040)
Source Block
→
Destination Block
Assembler
Syntax:
MOVE16 (Ax) + ,(Ay) +
MOVE16 (xxx).L,(An)
MOVE16 (xxx).L,(An) +
MOVE16 (An),(xxx).L
MOVE16 (An) + ,(xxx).L
MOVE16
Attributes: Size = (Line)
Description: Moves the source line to the destination line. The lines are aligned to 16-byte boundaries. Applications for this instruction include coprocessor communications, memory initialization, and fast block copy operations.
MOVE16 has two formats. The postincrement format uses the postincrement addressing mode for both source and destination; whereas, the absolute format specifies an absolute long address for either the source or destination.
Line transfers are performed using burst reads and writes, which begin with the long word pointed to by the effective address of the source and destination, respectively. An address register used in the postincrement addressing mode is incremented by 16 after the transfer.
Example: MOVE16 (A0) + $FE802 A0 = $1400F
The line at address $14000 is read into a temporary holding register by a burst read transfer starting with long-word $14000. Address values in A0 of $14000 – $1400F cause the same line to be read, starting at different long words. The line is then written to the line at address $FE800 beginning with long-word $FE800 after the instruction A0 contains $1401F.
Source line at $14000:
$14000
LONG WORD 0
$14004
LONG WORD 1
Destination line at $FE8000:
$14008
LONG WORD 2
$1400C
LONG WORD 3
$FE800
LONG WORD 0
$FE804
LONG WORD 1
$FE808
LONG WORD 2
$FE80C
LONG WORD 3
4-126 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
MOVE16
Move 16-Byte Block
(MC68040)
Integer Instructions
MOVE16
Condition Codes:
Not affected.
Instruction Format:
POSTINCREMENT SOURCE AND DESTINATION
15
1
1
14
1
13
1
REGISTER Ay
12
1
11
0
0
10
1
0
9
1
0
8
0
0
7
0
0
6
0
0
5
1
0
4
0
0
3
0
0
2 1
REGISTER Ax
0
0 0 0
Instruction Fields:
Register Ax—Specifies a source address register for the postincrement addressing mode.
Register Ay—Specifies a destination address register for the postincrement addressing mode.
Instruction Format:
Absolute Long Address Source or Destination
15
1
14
1
13
1
12
1
11
0
10
1
9
1
8
0
7
0
HIGH-ORDER ADDRESS
LOW-ORDER ADDRESS
6
0
5
0
4 3
OPMODE
2 1
REGISTER Ay
0
Instruction Fields:
Opmode field—Specifies the addressing modes used for source and destination:
Opmode
0 0
0 1
1 0
1 1
Source
(Ay) +
(xxx).L
(Ay)
(xxx).L
Destinati on
(xxx).L
(Ay) +
(xxx).L
(Ay)
Assembler Syntax
MOVE16 (Ay) + ,(xxx).L
MOVE16 (xxx).L,(Ay) +
MOVE16 (Ay),(xxx).L
MOVE16 (xxx).L,(Ay)
Register Ay—Specifies an address register for the indirect and postincrement addressing mode used as a source or destination.
32-Bit Address field—Specifies the absolute address used as a source or destination.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-127
Integer Instructions
MOVEM
Operation:
Assembler
Syntax:
Attributes:
Move Multiple Registers
(M68000 Family)
Registers
→
Destination; Source
→
Registers
MOVEM < list > , < ea >
MOVEM < ea > , < list >
MOVEM
Size = (Word, Long)
Description: Moves the contents of selected registers to or from consecutive memory locations starting at the location specified by the effective address. A register is selected if the bit in the mask field corresponding to that register is set. The instruction size determines whether 16 or 32 bits of each register are transferred. In the case of a word transfer to either address or data registers, each word is sign-extended to 32 bits, and the resulting long word is loaded into the associated register.
Selecting the addressing mode also selects the mode of operation of the MOVEM instruction, and only the control modes, the predecrement mode, and the postincrement mode are valid. If the effective address is specified by one of the control modes, the registers are transferred starting at the specified address, and the address is incremented by the operand length (2 or 4) following each transfer. The order of the registers is from D0 to D7, then from A0 to A7.
If the effective address is specified by the predecrement mode, only a register-to-memory operation is allowed. The registers are stored starting at the specified address minus the operand length (2 or 4), and the address is decremented by the operand length following each transfer. The order of storing is from A7 to A0, then from D7 to
D0. When the instruction has completed, the decremented address register contains the address of the last operand stored. For the MC68020, MC68030, MC68040, and
CPU32, if the addressing register is also moved to memory, the value written is the initial register value decremented by the size of the operation. The MC68000 and
MC68010 write the initial register value (not decremented).
If the effective address is specified by the postincrement mode, only a memory-to-register operation is allowed. The registers are loaded starting at the specified address; the address is incremented by the operand length (2 or 4) following each transfer. The order of loading is the same as that of control mode addressing. When the instruction has completed, the incremented address register contains the address of the last operand loaded plus the operand length. If the addressing register is also loaded from memory, the memory value is ignored and the register is written with the postincremented effective address.
4-128 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
MOVEM
Move Multiple Registers
(M68000 Family)
Integer Instructions
MOVEM
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10 dr
9
0
8
0
7
1
REGISTER LIST MASK
6
SIZE
Instruction Fields: dr field—Specifies the direction of the transfer.
0 — Register to memory.
1 — Memory to register.
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Size field—Specifies the size of the registers being transferred.
0 — Word transfer
1 — Long transfer
Effective Address field—Specifies the memory address for the operation. For registerto-memory transfers, only control alterable addressing modes or the predecrement addressing mode can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
—
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
—
100
101
110
Register
—
— reg. number:An
— reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-129
Integer Instructions
MOVEM
Move Multiple Registers
(M68000 Family)
MOVEM
For memory-to-register transfers, only control addressing modes or the postincrement addressing mode can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
—
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
—
101
110
Register
—
— reg. number:An reg. number:An
— reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
—
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
011
011
011
Register List Mask field—Specifies the registers to be transferred. The low-order bit corresponds to the first register to be transferred; the high-order bit corresponds to the last register to be transferred. Thus, for both control modes and postincrement mode addresses, the mask correspondence is:
15
A7
14
A6
13
A5
12
A4
11
A3
10
A2
9
A1
8
A0
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
For the predecrement mode addresses, the mask correspondence is reversed:
0
D0
15
D0
14
D1
13
D2
12
D3
11
D4
10
D5
9
D6
8
D7
7
A0
6
A1
5
A2
4
A3
3
A4
2
A5
1
A6
0
A7
4-130 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
MOVEP
Operation:
Assembler
Syntax:
Attributes:
Move Peripheral Data
(M68000 Family)
Source
→
Destination
MOVEP Dx,(d16,Ay)
MOVEP (d16,Ay),Dx
MOVEP
Size = (Word, Long)
Description: Moves data between a data register and alternate bytes within the address space starting at the location specified and incrementing by two. The high-order byte of the data register is transferred first, and the low-order byte is transferred last. The memory address is specified in the address register indirect plus 16-bit displacement addressing mode. This instruction was originally designed for interfacing 8-bit peripherals on a 16-bit data bus, such as the MC68000 bus. Although supported by the
MC68020, MC68030, and MC68040, this instruction is not useful for those processors with an external 32-bit bus.
Example: Long transfer to/from an even address.
Byte Organization in Register
31
HIGH ORDER
24 23
MID UPPER
16 15
MID LOWER
8 7
LOW ORDER
0
Byte Organization in
16-Bit Memory
(Low Address at Top)
7 15
HIGH ORDER
8
MID UPPER
MID LOWER
LOW ORDER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-131
Integer Instructions
MOVEP
Move Peripheral Data
(M68000 Family)
Byte Organization in 32-Bit Memory
MOVEP
31
HIGH ORDER
24
MID LOWER
23 7
31 24 23 16 15
HIGH ORDER
8
MID LOWER MID UPPER
LOW ORDER
Example:Word transfer to/from (odd address).
Byte Organization in Register
7
31
16 or
15
MID UPPER
LOW ORDER
8
31
0
0
24
24
23 16 15
HIGH ORDER
8
Byte Organization in
16-Bit Memory
(Low Address at Top)
15 8 7
HIGH ORDER
0
LOW ORDER
Byte Organization in 32-Bit Memory
23
LOW ORDER
16 or
15 8
7
LOW ORDER
0
7
HIGH ORDER
0
31 24 23
HIGH ORDER
16 15 8 7
LOW ORDER
0
4-132 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
MOVEP
Move Peripheral Data
(M68000 Family)
Integer Instructions
MOVEP
Condition Codes:
Not affected.
Instruction Format:
15
0
14
0
13
0
12
0
11 10 9
DATA REGISTER
8 7
OPMODE
6
16-BIT DISPLACEMENT
5
0
4
0
Instruction Fields:
Data Register field—Specifies the data register for the instruction.
3
1
Opmode field—Specifies the direction and size of the operation.
100— Transfer word from memory to register.
101— Transfer long from memory to register.
110— Transfer word from register to memory.
111— Transfer long from register to memory.
2 1 0
ADDRESS REGISTER
Address Register field—Specifies the address register which is used in the address register indirect plus displacement addressing mode.
Displacement field—Specifies the displacement used in the operand address.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-133
Integer Instructions
MOVEQ
Move Quick
(M68000 Family)
Immediate Data
→
Destination
MOVEQ
Operation:
Assembler
Syntax:
Attributes:
MOVEQ # < data > ,Dn
Size = (Long)
Description: Moves a byte of immediate data to a 32-bit data register. The data in an 8-bit field within the operation word is sign- extended to a long operand in the data register as it is transferred.
Condition Codes:
X
—
N
∗
Z
∗
V
0
C
0
X — Not affected.
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
15
0
14
1
13
1
12
1
11 10
REGISTER
9 8
0
7 6 5
Instruction Fields:
Register field—Specifies the data register to be loaded.
4
DATA
3 2
Data field—Eight bits of data, which are sign-extended to a long operand.
1 0
4-134 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
MULS
Operation:
Assembler
Syntax:
Signed Multiply
(M68000 Family)
Source x Destination
→
Destination
MULS.W < ea > ,Dn16 x 16
→
32
*MULS.L < ea > ,Dl 32 x 32
→
32
*MULS.L < ea > ,Dh – Dl 32 x 32
→
64
*Applies to MC68020, MC68030, MC68040, CPU32
MULS
Attributes: Size = (Word, Long)
Description: Multiplies two signed operands yielding a signed result. This instruction has a word operand form and a long operand form.
In the word form, the multiplier and multiplicand are both word operands, and the result is a long-word operand. A register operand is the low-order word; the upper word of the register is ignored. All 32 bits of the product are saved in the destination data register.
In the long form, the multiplier and multiplicand are both long- word operands, and the result is either a long word or a quad word. The long-word result is the low-order 32 bits of the quad- word result; the high-order 32 bits of the product are discarded.
Condition Codes:
X
—
N
∗
Z
∗
V
∗
C
0
X — Not affected.
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if overflow; cleared otherwise.
C — Always cleared.
NOTE
Overflow (V = 1) can occur only when multiplying 32-bit operands to yield a 32-bit result. Overflow occurs if the highorder 32 bits of the quad-word product are not the sign extension of the low- order 32 bits.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-135
Integer Instructions
MULS
Signed Multiply
(M68000 Family)
MULS
Instruction Format:
WORD
15
1
14
1
13
0
12
0
11 10
REGISTER
9 8
1
7
1
6
1
5
Instruction Fields:
Register field—Specifies a data register as the destination.
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Effective Address field—Specifies the source operand. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
100
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
011
011
011
4-136 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
MULS
Signed Multiply
(M68000 Family)
Integer Instructions
MULS
Instruction Format:
LONG
15
0
0
14
1
13
0
REGISTER DI
12
0
11
1
1
10
1
SIZE
9
0
0
8
0
0
7
0
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0
REGISTER
REGISTER Dh
0
Instruction Fields:
Effective Address field—Specifies the source operand. Only data addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
100
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
011
011
011
Register Dl field—Specifies a data register for the destination operand. The 32-bit multiplicand comes from this register, and the low-order 32 bits of the product are loaded into this register.
Size field—Selects a 32- or 64-bit product.
0 — 32-bit product to be returned to register Dl.
1 — 64-bit product to be returned to Dh – Dl.
Register Dh field—If size is one, specifies the data register into which the high-order
32 bits of the product are loaded. If Dh = Dl and size is one, the results of the operation are undefined. Otherwise, this field is unused.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-137
Integer Instructions
MULU
Operation:
Assembler
Syntax:
Unsigned Multiply
(M68000 Family)
Source x Destination
→
Destination
MULU.W < ea > ,Dn16 x 16
→
32
*MULU.L < ea > ,Dl 32 x 32
→
32
*MULU.L < ea > ,Dh – Dl 32 x 32
→
64
*Applies to MC68020, MC68030, MC68040, CPU32 only
MULU
Attributes: Size = (Word, Long)
Description: Multiplies two unsigned operands yielding an unsigned result. This instruction has a word operand form and a long operand form.
In the word form, the multiplier and multiplicand are both word operands, and the result is a long-word operand. A register operand is the low-order word; the upper word of the register is ignored. All 32 bits of the product are saved in the destination data register.
In the long form, the multiplier and multiplicand are both long- word operands, and the result is either a long word or a quad word. The long-word result is the low-order 32 bits of the quad- word result; the high-order 32 bits of the product are discarded.
Condition Codes:
X
—
N
∗
Z
∗
V
∗
C
0
X — Not affected.
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if overflow; cleared otherwise.
C — Always cleared.
NOTE
Overflow (V = 1) can occur only when multiplying 32-bit operands to yield a 32-bit result. Overflow occurs if any of the high-order 32 bits of the quad-word product are not equal to zero.
4-138 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
MULU
Unsigned Multiply
(M68000 Family)
Integer Instructions
MULU
Instruction Format:
WORD
15
1
14
1
13
0
12
0
11 10
REGISTER
9 8
0
7
1
6
1
5
Instruction Fields:
Register field—Specifies a data register as the destination.
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Effective Address field—Specifies the source operand. Only data addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
100
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
011
011
011
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-139
Integer Instructions
MULU
Unsigned Multiply
(M68000 Family)
MULU
Instruction Format:
LONG
15
0
0
14
1
13
0
REGISTER Dl
12
0
11
1
0
10
1
SIZE
9
0
0
8
0
0
7
0
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0
REGISTER
REGISTER Dh
0
Instruction Fields:
Effective Address field—Specifies the source operand. Only data addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
100
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
011
011
011
Register Dl field—Specifies a data register for the destination operand. The 32-bit multiplicand comes from this register, and the low-order 32 bits of the product are loaded into this register.
Size field—Selects a 32- or 64-bit product.
0 — 32-bit product to be returned to register Dl.
1 — 64-bit product to be returned to Dh – Dl.
Register Dh field—If size is one, specifies the data register into which the high-order
32 bits of the product are loaded. If Dh = Dl and size is one, the results of the operation are undefined. Otherwise, this field is unused.
4-140 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
NBCD
Negate Decimal with Extend
(M68000 Family)
0 – Destination
10
– X
→
Destination
NBCD
Operation:
Assembler
Syntax:
Attributes:
NBCD < ea >
Size = (Byte)
Description: Subtracts the destination operand and the extend bit from zero. The operation is performed using binary-coded decimal arithmetic. The packed binary-coded decimal result is saved in the destination location. This instruction produces the tens complement of the destination if the extend bit is zero or the nines complement if the extend bit is one. This is a byte operation only.
Condition Codes:
X
∗
N
U
Z
∗
V
U
C
∗
X — Set the same as the carry bit.
N — Undefined.
Z — Cleared if the result is nonzero; unchanged otherwise.
V — Undefined.
C — Set if a decimal borrow occurs; cleared otherwise.
NOTE
Normally the Z condition code bit is set via programming before the start of the operation. This allows successful tests for zero results upon completion of multiple-precision operations.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-141
Integer Instructions
NBCD
Negate Decimal with Extend
(M68000 Family)
NBCD
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
0
9
0
8
0
7
0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields:
Effective Address field—Specifies the destination operand. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
4-142 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
NEG
Negate
(M68000 Family)
0 – Destination
→
Destination
NEG
Operation:
Assembler
Syntax:
Attributes:
NEG < ea >
Size = (Byte, Word, Long)
Description: Subtracts the destination operand from zero and stores the result in the destination location. The size of the operation is specified as byte, word, or long.
Condition Codes:
X
∗
N
∗
Z
∗
V
∗
C
∗
X — Set the same as the carry bit.
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if an overflow occurs; cleared otherwise.
C — Cleared if the result is zero; set otherwise.
Instruction Format:
15
0
14
1
13
0
12
0
11
0
10
1
9
0
8
0
7
SIZE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-143
Integer Instructions
NEG
Negate
(M68000 Family)
NEG
Instruction Fields:
Size field—Specifies the size of the operation.
00 — Byte operation
01 — Word operation
10 — Long operation
Effective Address field—Specifies the destination operand. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
4-144 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
NEGX
Negate with Extend
(M68000 Family)
0 – Destination – X
→
Destination
NEGX
Operation:
Assembler
Syntax:
Attributes:
NEGX < ea >
Size = (Byte, Word, Long)
Description: Subtracts the destination operand and the extend bit from zero. Stores the result in the destination location. The size of the operation is specified as byte, word, or long.
Condition Codes:
X
∗
N
∗
Z
∗
V
∗
C
∗
X — Set the same as the carry bit.
N — Set if the result is negative; cleared otherwise.
Z — Cleared if the result is nonzero; unchanged otherwise.
V — Set if an overflow occurs; cleared otherwise.
C — Set if a borrow occurs; cleared otherwise.
NOTE
Normally the Z condition code bit is set via programming before the start of the operation. This allows successful tests for zero results upon completion of multiple-precision operations.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-145
Integer Instructions
NEGX
Negate with Extend
(M68000 Family)
NEGX
Instruction Format:
15
0
14
1
13
0
12
0
11
0
10
0
9
0
8
0
7
SIZE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields:
Size field—Specifies the size of the operation.
00 — Byte operation
01 — Word operation
10 — Long operation
Effective Address field—Specifies the destination operand. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
4-146 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
NOP
No Operation
(M68000 Family)
NOP
Operation:
Assembler
Syntax:
Attributes:
None
NOP
Unsized
Description: Performs no operation. The processor state, other than the program counter, is unaffected. Execution continues with the instruction following the NOP instruction.
The NOP instruction does not begin execution until all pending bus cycles have completed. This synchronizes the pipeline and prevents instruction overlap.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
0
6
1
5
1
4
1
3
0
2
0
1
0
0
1
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-147
Integer Instructions
NOT
Logical Complement
(M68000 Family)
~ Destination
→
Destination
NOT
Operation:
Assembler
Syntax:
Attributes:
NOT < ea >
Size = (Byte, Word, Long)
Description:Calculates the ones complement of the destination operand and stores the result in the destination location. The size of the operation is specified as byte, word, or long.
Condition Codes:
X
—
N
∗
Z
∗
V
0
C
0
X — Not affected.
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
15
0
14
1
13
0
12
0
11
0
10
1
9
1
8
0
7
SIZE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
4-148 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
NOT
Logical Complement
(M68000 Family)
NOT
Instruction Fields:
Size field—Specifies the size of the operation.
00— Byte operation
01— Word operation
10— Long operation
Effective Address field—Specifies the destination operand. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-149
Integer Instructions
OR
Operation:
Assembler
Syntax:
Attributes:
Inclusive-OR Logical
(M68000 Family)
Source V Destination
→
Destination
OR < ea > ,Dn
OR Dn, < ea >
OR
Size = (Byte, Word, Long)
Description: Performs an inclusive-OR operation on the source operand and the destination operand and stores the result in the destination location. The size of the operation is specified as byte, word, or long. The contents of an address register may not be used as an operand.
Condition Codes:
X
—
N
∗
Z
∗
V
0
C
0
X — Not affected.
N — Set if the most significant bit of the result is set; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
15
1
14
0
13
0
12
0
11 10
REGISTER
9 8 7
OPMODE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields:
Register field—Specifies any of the eight data registers.
Opmode field
Byte Word Long
000 001 010
100 101 110
Operation
< ea > V Dn
→
Dn
Dn V < ea >
→
< ea >
4-150 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
OR
Inclusive-OR Logical
(M68000 Family)
OR
Effective Address field—If the location specified is a source operand, only data addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
100
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
011
011
011
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-151
Integer Instructions
OR
Inclusive-OR Logical
(M68000 Family)
OR
If the location specified is a destination operand, only memory alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
—
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register
—
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
NOTE
If the destination is a data register, it must be specified using the destination Dn mode, not the destination < ea > mode.
Most assemblers use ORI when the source is immediate data.
—
—
—
4-152 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
ORI
Inclusive-OR
(M68000 Family)
Immediate Data V Destination
→
Destination
ORI
Operation:
Assembler
Syntax:
Attributes:
ORI # < data > , < ea >
Size = (Byte, Word, Long)
Description: Performs an inclusive-OR operation on the immediate data and the destination operand and stores the result in the destination location. The size of the operation is specified as byte, word, or long. The size of the immediate data matches the operation size.
Condition Codes:
X
—
N
∗
Z
∗
V
0
C
0
X — Not affected.
N — Set if the most significant bit of the result is set; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
15
0
14
0
13
0
12
0
11
0
16-BIT WORD DATA
10
0
9
0
8
0
7
SIZE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE
8-BIT BYTE DATA
REGISTER
0
32-BIT LONG DATA
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-153
Integer Instructions
ORI
Inclusive-OR
(M68000 Family)
ORI
Instruction Fields:
Size field—Specifies the size of the operation.
00— Byte operation
01— Word operation
10— Long operation
Effective Address field—Specifies the destination operand. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
Immediate field—Data immediately following the instruction.
If size = 00, the data is the low-order byte of the immediate word.
If size = 01, the data is the entire immediate word.
If size = 10, the data is the next two immediate words.
—
—
—
—
—
—
4-154 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
ORI ORI to CCR
Inclusive-OR Immediate
to CCR
to Condition Codes
(M68000 Family)
Operation: Source V CCR
→
CCR
Assembler
Syntax:
Attributes:
ORI # < data > ,CCR
Size = (Byte)
Description: Performs an inclusive-OR operation on the immediate operand and the condition codes and stores the result in the condition code register (low-order byte of the status register). All implemented bits of the condition code register are affected.
Condition Codes:
X
∗
N
∗
Z
∗
V
∗
C
∗
X — Set if bit 4 of immediate operand is one; unchanged otherwise.
N — Set if bit 3 of immediate operand is one; unchanged otherwise.
Z — Set if bit 2 of immediate operand is one; unchanged otherwise.
V — Set if bit 1 of immediate operand is one; unchanged otherwise.
C — Set if bit 0 of immediate operand is one; unchanged otherwise.
Instruction Format:
15
0
0
14
0
0
13
0
0
12
0
0
11
0
0
10
0
0
9
0
0
8
0
0
7
0
6
0
5
1
4
1
3
1
8-BIT BYTE DATA
2
1
1
0
0
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-155
Integer Instructions
PACK
Operation:
Assembler
Syntax:
Pack
(MC68020, MC68030, MC68040)
PACK – (Ax), – (Ay),# < adjustment >
PACK Dx,Dy,# < adjustment >
PACK
Source (Unpacked BCD) + Adjustment
→
Destination (Packed BCD)
Attributes: Unsized
Description: Adjusts and packs the lower four bits of each of two bytes into a single byte.
When both operands are data registers, the adjustment is added to the value contained in the source register. Bits 11 – 8 and 3 – 0 of the intermediate result are concatenated and placed in bits 7 – 0 of the destination register. The remainder of the destination register is unaffected.
Source:
15 x
14 x
13 x
12 x
11 a
10 b
9 c
8 d
Dx
7 x
6 x
5 x
4 x
3 e
2 f
1 g
0 h
Add Adjustment Word:
15 0
16-BIT EXTENSION
Resulting in:
15 x’
14 x’
13 x’
Destination:
12 x’
11 a’
10 b’
9 c’
8 d’
7 x’
6 x’
5 x’
4 x’
3 e’
2 f’
1 g’
0 h’
15 u
14 u
13 u
12 u
11 u
10 u
9 u
8 u
Dy
7 a’
6 b’
5 c’
4 d’
3 e’
2 f’
1 g’
0 h’
When the predecrement addressing mode is specified, two bytes from the source are fetched and concatenated. The adjustment word is added to the concatenated bytes.
Bits 3 – 0 of each byte are extracted. These eight bits are concatenated to form a new byte which is then written to the destination.
4-156 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
PACK
Pack
(MC68020, MC68030, MC68040)
Source:
7 x x
6 x x
5 x x
4 x x
Ax
3 a e
Concatenated Word:
15 x
14 x
13 x
12 x
11 a
Add Adjustment Word:
10 b
15
9 c
2 b f
8 d
1 c g
7 x
0 d h
6 x
5 x
16-BIT EXTENSION
4 x
Destination:
7 a’
6 b’
5 c’
4 d’
Ay
3 e’
2 f’
1 g’
0 h’
Condition Codes:
Not affected.
Instruction Format:
15
1
14
0
13
0
12
0
11 10 9
REGISTER Dy/Ay
8
1
7
0
6
1
16-BIT ADJUSTMENT EXTENSION:
5
0
3 e
Integer Instructions
2 f
PACK
1 g
0 h
0
4
0
3
R/M
2 1 0
REGISTER Dx/Ax
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-157
Integer Instructions
PACK
Pack
(MC68020, MC68030, MC68040)
PACK
Instruction Fields:
Register Dy/Ay field—Specifies the destination register.
If R/M = 0, specifies a data register.
If R/M = 1, specifies an address register in the predecrement addressing mode.
R/M field—Specifies the operand addressing mode.
0 — The operation is data register to data register.
1 — The operation is memory to memory.
Register Dx/Ax field—Specifies the source register.
If R/M = 0, specifies a data register.
If R/M = 1, specifies an address register in the predecrement addressing mode.
Adjustment field—Immediate data word that is added to the source operand. This word is zero to pack ASCII or EBCDIC codes. Other values can be used for other codes.
4-158 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
PEA
Push Effective Address
(M68000 Family)
SP – 4
→
SP; < ea >
→
(SP)
PEA
Operation:
Assembler
Syntax:
Attributes:
PEA < ea >
Size = (Long)
Description: Computes the effective address and pushes it onto the stack. The effective address is a long address.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
0
9
0
8
0
7
0
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Field:
Effective Address field—Specifies the address to be pushed onto the stack. Only control addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
—
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
—
—
101
110
Register
—
— reg. number:An
—
— reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
—
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
011
011
011
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-159
Integer Instructions
ROL, ROR
Rotate (Without Extend)
ROL, ROR
(M68000 Family)
Operation: Destination Rotated By < count >
→
Destination
Assembler
Syntax:
ROd Dx,Dy
ROd # < data > ,Dy ROd < ea > where d is direction, L or R
Attributes: Size = (Byte, Word, Long)
Description: Rotates the bits of the operand in the direction specified (L or R). The extend bit is not included in the rotation. The rotate count for the rotation of a register is specified in either of two ways:
1. Immediate—The rotate count (1 – 8) is specified in the instruction.
2. Register—The rotate count is the value in the data register specified in the instruction, modulo 64.
The size of the operation for register destinations is specified as byte, word, or long.
The contents of memory, (ROd < ea > ), can be rotated one bit only, and operand size is restricted to a word.
The ROL instruction rotates the bits of the operand to the left; the rotate count determines the number of bit positions rotated. Bits rotated out of the high-order bit go to the carry bit and also back into the low-order bit.
.
ROL:
C OPERAND
The ROR instruction rotates the bits of the operand to the right; the rotate count determines the number of bit positions rotated. Bits rotated out of the low-order bit go to the carry bit and also back into the high-order bit.
.
ROR:
OPERAND C
4-160 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
ROL,ROR
Rotate (Without Extend)
(M68000 Family)
Condition Codes:
X
—
N
∗
Z
∗
V
0
C
∗
Integer Instructions
ROL,ROR
X — Not affected.
N — Set if the most significant bit of the result is set; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Always cleared.
C — Set according to the last bit rotated out of the operand; cleared when the rotate count is zero.
Instruction Format:
REGISTER ROTATE
15
1
14
1
13
1
12
0
11 10
COUNT/
REGISTER
9 8 dr
7
SIZE
6 5 i/r
4
1
3
1
2 1
REGISTER
0
Instruction Fields:
Count/Register field:
If i/r = 0, this field contains the rotate count. The values 1 – 7 represent counts of 1
– 7, and zero specifies a count of eight.
If i/r = 1, this field specifies a data register that contains the rotate count (modulo 64). dr field—Specifies the direction of the rotate.
0 — Rotate right
1 — Rotate left
Size field—Specifies the size of the operation.
00 — Byte operation
01 — Word operation
10 — Long operation i/r field—Specifies the rotate count location.
If i/r = 0, immediate rotate count.
If i/r = 1, register rotate count.
Register field—Specifies a data register to be rotated.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-161
Integer Instructions
ROL, ROR
Rotate (Without Extend)
ROL, ROR
(M68000 Family)
Instruction Format:
15
1
14
1
13
1
12
0
11
0
10
1
9
MEMORY ROTATE
8 7 6
1 dr 1 1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields: dr field—Specifies the direction of the rotate.
0 — Rotate right
1 — Rotate left
Effective Address field—Specifies the operand to be rotated. Only memory alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn —
An
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
—
010
011
100
101
110
Register
—
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
111 000
Register
(xxx).L
#<data>
111 001
— —
(d
16
,PC)
(d
8
,PC,Xn)
— —
— —
MC68020, MC68030, and MC68040 only
(bd,An,Xn)* 110 reg. number:An
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110 reg. number:An reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
4-162 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
ROXL, ROXR
Rotate with Extend
ROXL, ROXR
(M68000 Family)
Operation: Destination Rotated With X By Count
→
Destination
Assembler
Syntax:
ROXd Dx,Dy
ROXd # < data > ,Dy
ROXd < ea > where d is direction, L or R
Attributes: Size = (Byte, Word, Long)
Description: Rotates the bits of the operand in the direction specified (L or R). The extend bit is included in the rotation. The rotate count for the rotation of a register is specified in either of two ways:
1. Immediate—The rotate count (1 – 8) is specified in the instruction.
2. Register—The rotate count is the value in the data register specified in the instruction, modulo 64.
The size of the operation for register destinations is specified as byte, word, or long.
The contents of memory, < ea > , can be rotated one bit only, and operand size is restricted to a word. The ROXL instruction rotates the bits of the operand to the left; the rotate count determines the number of bit positions rotated. Bits rotated out of the highorder bit go to the carry bit and the extend bit; the previous value of the extend bit rotates into the low-order bit.
.
ROXL: C OPERAND X
The ROXR instruction rotates the bits of the operand to the right; the rotate count determines the number of bit positions rotated. Bits rotated out of the low-order bit go to the carry bit and the extend bit; the previous value of the extend bit rotates into the highorder bit.
.
ROXR: X OPERAND C
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-163
Integer Instructions
ROXL, ROXR
Rotate with Extend
ROXL, ROXR
(M68000 Family)
Condition Codes:
X
∗
N
∗
Z
∗
V
0
C
∗
X — Set to the value of the last bit rotated out of the operand; unaffected when the rotate count is zero.
N — Set if the most significant bit of the result is set; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Always cleared.
C — Set according to the last bit rotated out of the operand; when the rotate count is zero, set to the value of the extend bit.
Instruction Format:
15
1
14
1
13
1
12
0
11 10
COUNT/
REGISTER
REGISTER ROTATE
9 8 7 6 dr SIZE
5 i/r
4
1
3
0
2 1
REGISTER
0
Instruction Fields:
Count/Register field:
If i/r = 0, this field contains the rotate count. The values 1 – 7 represent counts of 1
– 7, and zero specifies a count of eight.
If i/r = 1, this field specifies a data register that contains the rotate count (modulo 64). dr field—Specifies the direction of the rotate.
0 — Rotate right
1 — Rotate left
4-164 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
ROXL, ROXR
Rotate with Extend
ROXL, ROXR
(M68000 Family)
Size field—Specifies the size of the operation.
00 — Byte operation
01 — Word operation
10 — Long operation i/r field—Specifies the rotate count location.
If i/r = 0, immediate rotate count.
If i/r = 1, register rotate count.
Register field—Specifies a data register to be rotated.
Instruction Format:
15
1
14
1
13
1
12
0
11
0
10
1
9
MEMORY ROTATE
8 7 6
0 dr 1 1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields: dr field—Specifies the direction of the rotate.
0 — Rotate right
1 — Rotate left
Effective Address field—Specifies the operand to be rotated. Only memory alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
—
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register
—
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-165
Integer Instructions
RTD
Return and Deallocate
(MC68010, MC68020, MC68030, MC68040, CPU32)
(SP)
→
PC; SP + 4 + d n
→
SP
RTD
Operation:
Assembler
Syntax:
Attributes:
RTD # < displacement >
Unsized
Description: Pulls the program counter value from the stack and adds the sign-extended
16-bit displacement value to the stack pointer. The previous program counter value is lost.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
0
16-BIT DISPLACEMENT
6
1
5
1
4
1
3
0
2
1
1
0
0
0
Instruction Field:
Displacement field—Specifies the twos complement integer to be sign-extended and added to the stack pointer.
4-166 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
RTM
Return from Module
(MC68020)
RTM
Operation:
Assembler
Syntax:
Attributes:
Reload Saved Module State from Stack
RTM Rn
Unsized
Description: A previously saved module state is reloaded from the top of stack. After the module state is retrieved from the top of the stack, the caller’s stack pointer is incremented by the argument count value in the module state.
Condition Codes:
Set according to the content of the word on the stack.
Instruction Format:
15
0
14
0
13
0
12
0
11
0
10
1
9
1
8
0
7
1
6
1
5
0
4
0
3
D/A
2 1
REGISTER
0
Instruction Fields:
D/A field—Specifies whether the module data pointer is in a data or an address register.
0 — the register is a data register
1 — the register is an address register
Register field—Specifies the register number for the module data area pointer to be restored from the saved module state. If the register specified is A7 (SP), the updated value of the register reflects the stack pointer operations, and the saved module data area pointer is lost.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-167
Integer Instructions
RTR
Return and Restore Condition Codes
(M68000 Family)
(SP)
→
CCR; SP + 2
→
SP; (SP)
→
PC; SP + 4
→
SP
RTR
Operation:
Assembler
Syntax:
Attributes:
RTR
Unsized
Description: Pulls the condition code and program counter values from the stack. The previous condition code and program counter values are lost. The supervisor portion of the status register is unaffected.
Condition Codes:
Set to the condition codes from the stack.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
0
6
1
5
1
4
1
3
0
2
1
1
1
0
1
4-168 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
RTS
Return from Subroutine
(M68000 Family)
(SP)
→
PC; SP + 4
→
SP
RTS
Operation:
Assembler
Syntax:
Attributes:
RTS
Unsized
Description: Pulls the program counter value from the stack. The previous program counter value is lost.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
0
6
1
5
1
4
1
3
0
2
1
1
0
0
1
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-169
Integer Instructions
SBCD
Operation:
Assembler
Syntax:
Attributes:
Subtract Decimal with Extend
(M68000 Family)
Destination10 – Source10 – X
→
Destination
SBCD Dx,Dy
SBCD – (Ax), – (Ay)
SBCD
Size = (Byte)
Description: Subtracts the source operand and the extend bit from the destination operand and stores the result in the destination location. The subtraction is performed using binary-coded decimal arithmetic; the operands are packed binary-coded decimal numbers. The instruction has two modes:
1. Data register to data register—the data registers specified in the instruction contain the operands.
2. Memory to memory—the address registers specified in the instruction access the operands from memory using the predecrement addressing mode.
This operation is a byte operation only.
Condition Codes:
X
∗
N
U
Z
∗
V
U
C
∗
X — Set the same as the carry bit.
N — Undefined.
Z — Cleared if the result is nonzero; unchanged otherwise.
V — Undefined.
C — Set if a borrow (decimal) is generated; cleared otherwise.
NOTE
Normally the Z condition code bit is set via programming before the start of an operation. This allows successful tests for zero results upon completion of multiple-precision operations.
4-170 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
SBCD
Subtract Decimal with Extend
(M68000 Family)
Integer Instructions
SBCD
Instruction Format:
15
1
14
0
13
0
12
0
11 10 9
REGISTER Dy/Ay
8
1
7
0
6
0
5
0
4
0
3
R/M
2 1 0
REGISTER Dx/Ax
Instruction Fields:
Register Dy/Ay field—Specifies the destination register.
If R/M = 0, specifies a data register.
If R/M = 1, specifies an address register for the predecrement addressing mode.
R/M field—Specifies the operand addressing mode.
0 — The operation is data register to data register.
1 — The operation is memory to memory.
Register Dx/Ax field—Specifies the source register.
If R/M = 0, specifies a data register.
If R/M = 1, specifies an address register for the predecrement addressing mode.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-171
Integer Instructions
Scc
Set According to Condition
(M68000 Family)
Scc
Operation: If Condition True
Then 1s
→
Destination
Else 0s
→
Destination
Assembler
Syntax:
Attributes:
Scc < ea >
Size = (Byte)
Description: Tests the specified condition code; if the condition is true, sets the byte specified by the effective address to TRUE (all ones). Otherwise, sets that byte to
FALSE (all zeros). Condition code cc specifies one of the following conditional tests
(refer to Table 3-19 for more information on these conditional tests):
Mnemonic
CC(HI)
CS(LO)
EQ
F
GE
GT
HI
LE
Condition Codes:
Not affected.
Condition
Carry Clear
Carry Set
Equal
False
Greater or Equal
Greater Than
High
Less or Equal
Mnemonic
LS
LT
MI
NE
PL
T
VC
VS
Condition
Low or Same
Less Than
Minus
Not Equal
Plus
True
Overflow Clear
Overflow Set
4-172 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Scc
Set According to Condition
(M68000 Family)
Integer Instructions
Scc
Instruction Format:
15
0
14
1
13
0
12
1
11 10 9
CONDITION
8 7
1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields:
Condition field—The binary code for one of the conditions listed in the table.
Effective Address field—Specifies the location in which the TRUE/FALSE byte is to be stored. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
NOTE
A subsequent NEG.B instruction with the same effective address can be used to change the Scc result from TRUE or
FALSE to the equivalent arithmetic value (TRUE = 1, FALSE =
0). In the MC68000 and MC68008, a memory destination is read before it is written.
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-173
Integer Instructions
SUB
Operation:
Assembler
Syntax:
Attributes:
Destination – Source
→
Destination
SUB < ea > ,Dn
SUB Dn, < ea >
Subtract
(M68000 Family)
SUB
Size = (Byte, Word, Long)
Description: Subtracts the source operand from the destination operand and stores the result in the destination. The size of the operation is specified as byte, word, or long.
The mode of the instruction indicates which operand is the source, which is the destination, and which is the operand size.
Condition Codes:
X
∗
N
∗
Z
∗
V
∗
C
∗
X — Set to the value of the carry bit.
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if an overflow is generated; cleared otherwise.
C — Set if a borrow is generated; cleared otherwise.
Instruction Format:
15
1
14
0
13
0
12
1
11 10
REGISTER
9 8 7
OPMODE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
4-174 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
SUB
Subtract
(M68000 Family)
Instruction Fields:
Register field—Specifies any of the eight data registers.
Opmode field
Integer Instructions
SUB
Byte
000
100
Word
001
101
Long
010
110
Operation
Dn – < ea >
→
Dn
< ea > – Dn
→
< ea >
Effective Address field—Determines the addressing mode. If the location specified is a source operand, all addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An*
000
001
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
100
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)**
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110
110 reg. number:An reg. number:An reg. number:An
(bd,PC,Xn)**
([bd,PC,Xn],od)
([bd,PC],Xn,od)
*For byte-sized operation, address register direct is not allowed.
**Can be used with CPU32.
111
111
111
011
011
011
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-175
Integer Instructions
SUB
Subtract
(M68000 Family)
SUB
If the location specified is a destination operand, only memory alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
—
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register
—
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
NOTE
If the destination is a data register, it must be specified as a destination Dn address, not as a destination < ea > address.
Most assemblers use SUBA when the destination is an address register and SUBI or SUBQ when the source is immediate data.
—
—
—
4-176 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
SUBA
Subtract Address
(M68000 Family)
Destination – Source
→
Destination
SUBA
Operation:
Assembler
Syntax:
Attributes:
SUBA < ea > ,An
Size = (Word, Long)
Description: Subtracts the source operand from the destination address register and stores the result in the address register. The size of the operation is specified as word or long.
Word-sized source operands are sign-extended to 32-bit quantities prior to the subtraction.
Condition Codes:
Not affected.
Instruction Format:
15
1
14
0
13
0
12
1
11 10
REGISTER
9 8 7
OPMODE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields:
Register field—Specifies the destination, any of the eight address registers.
Opmode field—Specifies the size of the operation.
011— Word operation. The source operand is sign-extended to a long operand and the operation is performed on the address register using all 32 bits.
111— Long operation.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-177
Integer Instructions
SUBA
Subtract Address
(M68000 Family)
SUBA
Effective Address field—Specifies the source operand. All addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
001
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> 111
(d
16
,PC)
(d
8
,PC,Xn)
111
111
Register
000
001
100
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
011
011
011
4-178 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
SUBI
Subtract Immediate
(M68000 Family)
Destination – Immediate Data
→
Destination
SUBI
Operation:
Assembler
Syntax:
Attributes:
SUBI # < data > , < ea >
Size = (Byte, Word, Long)
Description: Subtracts the immediate data from the destination operand and stores the result in the destination location. The size of the operation is specified as byte, word, or long. The size of the immediate data matches the operation size.
Condition Codes:
X
∗
N
∗
Z
∗
V
∗
C
∗
X — Set to the value of the carry bit.
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if an overflow occurs; cleared otherwise.
C — Set if a borrow occurs; cleared otherwise.
Instruction Format:
15
0
14
0
13
0
12
0
11
0
16-BIT WORD DATA
10
1
9
0
8
0
7
SIZE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE
8-BIT BYTE DATA
REGISTER
0
32-BIT LONG DATA
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-179
Integer Instructions
SUBI
Subtract Immediate
(M68000 Family)
SUBI
Instruction Fields:
Size field—Specifies the size of the operation.
00 — Byte operation
01 — Word operation
10 — Long operation
Effective Address field—Specifies the destination operand. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)* 110 reg. number:An
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110 reg. number:An reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
Immediate field—Data immediately following the instruction.
If size = 00, the data is the low-order byte of the immediate word.
If size = 01, the data is the entire immediate word.
If size = 10, the data is the next two immediate words.
— —
— —
— —
4-180 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
SUBQ
Subtract Quick
(M68000 Family)
Destination – Immediate Data
→
Destination
SUBQ
Operation:
Assembler
Syntax:
Attributes:
SUBQ # < data > , < ea >
Size = (Byte, Word, Long)
Description: Subtracts the immediate data (1 – 8) from the destination operand. The size of the operation is specified as byte, word, or long. Only word and long operations can be used with address registers, and the condition codes are not affected. When subtracting from address registers, the entire destination address register is used, despite the operation size.
Condition Codes:
X
∗
N
∗
Z
∗
V
∗
C
∗
X — Set to the value of the carry bit.
N — Set if the result is negative; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if an overflow occurs; cleared otherwise.
C — Set if a borrow occurs; cleared otherwise.
Instruction Format:
15
0
14
1
13
0
12
1
11 10
DATA
9 8
1
7
SIZE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-181
Integer Instructions
SUBQ
Subtract Quick
(M68000 Family)
SUBQ
Instruction Fields:
Data field—Three bits of immediate data; 1 – 7 represent immediate values of 1 – 7, and zero represents eight.
Size field—Specifies the size of the operation.
00 — Byte operation
01 — Word operation
10 — Long operation
Effective Address field—Specifies the destination location. Only alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An*
000
001
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)**
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Word and long only.
**Can be used with CPU32.
(bd,PC,Xn)**
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
4-182 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
SUBX
Operation:
Assembler
Syntax:
Attributes:
Subtract with Extend
(M68000 Family)
Destination – Source – X
→
Destination
SUBX Dx,Dy
SUBX – (Ax), – (Ay)
SUBX
Size = (Byte, Word, Long)
Description: Subtracts the source operand and the extend bit from the destination operand and stores the result in the destination location. The instruction has two modes:
1. Data register to data register—the data registers specified in the instruction contain the operands.
2. Memory to memory—the address registers specified in the instruction access the operands from memory using the predecrement addressing mode.
The size of the operand is specified as byte, word, or long.
Condition Codes:
X
∗
N
∗
Z
∗
V
∗
C
∗
X — Set to the value of the carry bit.
N — Set if the result is negative; cleared otherwise.
Z — Cleared if the result is nonzero; unchanged otherwise.
V — Set if an overflow occurs; cleared otherwise.
C — Set if a borrow occurs; cleared otherwise.
NOTE
Normally the Z condition code bit is set via programming before the start of an operation. This allows successful tests for zero results upon completion of multiple-precision operations.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-183
Integer Instructions
SUBX
Subtract with Extend
(M68000 Family)
SUBX
Instruction Format:
15
1
14
0
13
0
12
1
11 10 9
REGISTER Dy/Ay
8
1
7
SIZE
6 5
0
4
0
3
R/M
2 1 0
REGISTER Dx/Ax
Instruction Fields:
Register Dy/Ay field—Specifies the destination register.
If R/M = 0, specifies a data register.
If R/M = 1, specifies an address register for the predecrement addressing mode.
Size field—Specifies the size of the operation.
00 — Byte operation
01 — Word operation
10 — Long operation
R/M field—Specifies the operand addressing mode.
0 — The operation is data register to data register.
1 — The operation is memory to memory.
Register Dx/Ax field—Specifies the source register:
If R/M = 0, specifies a data register.
If R/M = 1, specifies an address register for the predecrement addressing mode.
4-184 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
SWAP
Operation:
Swap Register Halves
(M68000 Family)
Register 31 – 16
←→
Register 15 – 0
Assembler
Syntax:
Attributes:
SWAP Dn
Size = (Word)
Description: Exchange the 16-bit words (halves) of a data register.
Condition Codes:
X
—
N
∗
Z
∗
V
0
C
0
Integer Instructions
SWAP
X — Not affected.
N — Set if the most significant bit of the 32-bit result is set; cleared otherwise.
Z — Set if the 32-bit result is zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
0
9
0
8
0
7
0
6
1
Instruction Field:
Register field—Specifies the data register to swap.
5
0
4
0
3
0
2 1
REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-185
Integer Instructions
TAS
Test and Set an Operand
(M68000 Family)
TAS
Destination Tested
→
Condition Codes; 1
→
Bit 7 of Destination Operation:
Assembler
Syntax:
Attributes:
TAS < ea >
Size = (Byte)
Description: Tests and sets the byte operand addressed by the effective address field. The instruction tests the current value of the operand and sets the N and Z condition bits appropriately. TAS also sets the high-order bit of the operand. The operation uses a locked or read-modify-write transfer sequence. This instruction supports use of a flag or semaphore to coordinate several processors.
Condition Codes:
X
—
N
∗
Z
∗
V
0
C
0
X — Not affected.
N — Set if the most significant bit of the operand is currently set; cleared otherwise.
Z — Set if the operand was zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
0
9
1
8
0
7
1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
4-186 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
TAS
Test and Set an Operand
(M68000 Family)
TAS
Instruction Fields:
Effective Address field—Specifies the location of the tested operand. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn
— reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data> —
(d
16
,PC)
(d
8
,PC,Xn)
—
—
Register
000
001
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn],od)
110
110 reg. number:An reg. number:An
([bd,An],Xn,od) 110 reg. number:An
*Can be used with CPU32.
(bd,PC,Xn)*
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-187
Integer Instructions
TRAP
Operation:
Trap
(M68000 Family)
1
→
S-Bit of SR
*SSP – 2
→
SSP; Format/Offset
→
(SSP);
SSP – 4
→
SSP; PC
→
(SSP); SSP – 2
→
SSP;
SR
→
(SSP); Vector Address
→
PC
*The MC68000 and MC68008 do not write vector offset or format code to the system stack.
TRAP
Assembler
Syntax:
Attributes:
TRAP # < vector >
Unsized
Description: Causes a TRAP # < vector > exception. The instruction adds the immediate operand (vector) of the instruction to 32 to obtain the vector number. The range of vector values is 0 – 15, which provides 16 vectors.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
0
6
1
Instruction Fields:
Vector field—Specifies the trap vector to be taken.
5
0
4
0
3 2 1
VECTOR
0
4-188 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
TRAPcc
Trap on Condition
(MC68020, MC68030, MC68040, CPU32)
TRAPcc
Operation:
Assembler
Syntax:
If cc
Then TRAP
TRAPcc
TRAPcc.W # < data >
TRAPcc.L # < data >
Unsized or Size = (Word, Long) Attributes:
Description: If the specified condition is true, causes a TRAPcc exception with a vector number 7. The processor pushes the address of the next instruction word (currently in the program counter) onto the stack. If the condition is not true, the processor performs no operation, and execution continues with the next instruction. The immediate data operand should be placed in the next word(s) following the operation word and is available to the trap handler. Condition code cc specifies one of the following conditional tests (refer to Table 3-19 for more information on these conditional tests):
Mnemonic
CC(HI)
CS(LO)
EQ
F
GE
GT
HI
LE
Condition Codes:
Not affected.
Condition
Carry Clear
Carry Set
Equal
False
Greater or Equal
Greater Than
High
Less or Equal
Mnemonic
LS
LT
MI
NE
PL
T
VC
VS
Condition
Low or Same
Less Than
Minus
Not Equal
Plus
True
Overflow Clear
Overflow Set
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-189
Integer Instructions
TRAPcc
Trap on Condition
(MC68020, MC68030, MC68040, CPU32)
TRAPcc
Instruction Format:
15
0
14
1
13
0
12
1
11 10 9
CONDITION
8 7
1
OPTIONAL WORD
OR LONG WORD
6
1
5
1
4
1
3
1
2 1
OPMODE
0
Instruction Fields:
Condition field—The binary code for one of the conditions listed in the table.
Opmode field—Selects the instruction form.
010— Instruction is followed by word-sized operand.
011— Instruction is followed by long-word-sized operand.
100— Instruction has no operand.
4-190 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
TRAPV
Trap on Overflow
(M68000 Family)
TRAPV
Operation: If V
Then TRAP
Assembler
Syntax:
Attributes:
TRAPV
Unsized
Description: If the overflow condition is set, causes a TRAPV exception with a vector number 7. If the overflow condition is not set, the processor performs no operation and execution continues with the next instruction.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
0
6
1
5
1
4
1
3
0
2
1
1
1
0
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-191
Integer Instructions
TST
Test an Operand
(M68000 Family)
Destination Tested
→
Condition Codes
TST
Operation:
Assembler
Syntax:
Attributes:
TST < ea >
Size = (Byte, Word, Long)
Description: Compares the operand with zero and sets the condition codes according to the results of the test. The size of the operation is specified as byte, word, or long.
Condition Codes:
X
—
N
∗
Z
∗
V
0
C
0
X — Not affected.
N — Set if the operand is negative; cleared otherwise.
Z — Set if the operand is zero; cleared otherwise.
V — Always cleared.
C — Always cleared.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
0
9
1
8
0
7
SIZE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
4-192 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
TST
Test an Operand
(M68000 Family)
TST
Instruction Fields:
Size field—Specifies the size of the operation.
00 — Byte operation
01 — Word operation
10 — Long operation
Effective Address field—Specifies the addressing mode for the destination operand as listed in the following tables:
Addressing Mode Mode
Dn
An*
000
001
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
010
011
100
101
110
Register reg. number:Dn reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode
(xxx).W
(xxx).L
111
111
#<data>* 111
(d
16
,PC)**
(d
8
,PC,Xn)**
111
111
Register
000
001
100
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)***
([bd,An,Xn],od)
([bd,An],Xn,od)
110
110
110 reg. number:An reg. number:An reg. number:An
(bd,PC,Xn)***
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
*MC68020, MC68030, MC68040, and CPU32. Address register direct allowed only for word and long.
**PC relative addressing modes do not apply to MC68000, MC680008, or MC68010.
***Can be used with CPU32.
011
011
011
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-193
Integer Instructions
UNLK
Unlink
(M68000 Family)
An
→
SP; (SP)
→
An; SP + 4
→
SP
UNLK
Operation:
Assembler
Syntax:
Attributes:
UNLK An
Unsized
Description: Loads the stack pointer from the specified address register, then loads the address register with the long word pulled from the top of the stack.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
0
6
1
5
0
4
1
Instruction Field:
Register field—Specifies the address register for the instruction.
3
1
2 1
REGISTER
0
4-194 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
UNPK
Operation:
Assembler
Syntax:
Attributes:
Unpack BCD
(MC68020, MC68030, MC68040)
UNPACK – (Ax), – (Ay),# < adjustment >
UNPK Dx,Dy,# < adjustment >
UNPK
Source (Packed BCD) + Adjustment
→
Destination (Unpacked BCD)
Unsized
Description: Places the two binary-coded decimal digits in the source operand byte into the lower four bits of two bytes and places zero bits in the upper four bits of both bytes.
Adds the adjustment value to this unpacked value. Condition codes are not altered.
When both operands are data registers, the instruction unpacks the source register contents, adds the extension word, and places the result in the destination register.
The high word of the destination register is unaffected.
Source:
15 u
14 u
13 u
12 u
11 u
10 u
9 u
8 u
Dx
7 a
6 b
5 c
4 d
3 e
2 f
1 g
0 h
Intermediate Expansion:
15
0
14
0
13
0
12
0
11 a
Add Adjustment Word:
10 b
15 14 13 12 11 10
9 c
8 d
7
0
6
0
5
0
5
4
0
4
3 e
3
2 f
2
1 g
1
0 h
0 9 8 7
16-BIT EXTENSION
6
15 v
Destination:
14 v
13 v
12 v
11 a’
10 b’
9 c’
8 d’
Dy
7 w
6 w
5 w
4 w
3 e’
2 f’
1 g’
0 h’
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-195
Integer Instructions
UNPK
Unpack BCD
(MC68020, MC68030, MC68040)
UNPK
When the specified addressing mode is predecrement, the instruction extracts two binary-coded decimal digits from a byte at the source address. After unpacking the digits and adding the adjustment word, the instruction writes the two bytes to the destination address. Source:
7 a
6 b
5 c
4 d
Ax
3 e
Intermediate Expansion:
15
0
14
0
13
0
12
0
11 a
Add Adjustment Word:
10 b
15
9 c
2 f
8 d
1 g
7
0
0 h
16-BIT EXTENSION
6
0
Destination:
5
0
4
0
3 e
2 f
1 g
0 h
0
7 v w
6 v w
5 v w
4 v w
Ay
3 a’ e’
2 b’ f’
1 c’ g’
0 d’ h’
Condition Codes:
Not affected.
Instruction Format:
15
1
14
0
13
0
12
0
11 10 9
REGISTER Dy/Ay
8
1
7
1
6
0
16-BIT EXTENSION: ADJUSTMENT
5
0
4
0
3
R/M
2 1 0
REGISTER Dx/Ax
4-196 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Integer Instructions
UNPK
Unpack BCD
(MC68020, MC68030, MC68040)
UNPK
Instruction Fields:
Register Dy/Ay field—Specifies the destination register.
If R/M = 0, specifies a data register.
If R/M = 1, specifies an address register in the predecrement addressing mode.
R/M field—Specifies the operand addressing mode.
0 — The operation is data register to data register.
1 — The operation is memory to memory.
Register Dx/Ax field—Specifies the data register.
If R/M = 0, specifies a data register.
If R/M = 1, specifies an address register in the predecrement addressing mode.
Adjustment field—Immediate data word that is added to the source operand.
Appropriate constants can be used as the adjustment to translate from binarycoded decimal to the desired code. The constant used for ASCII is $3030; for
EBCDIC, $F0F0.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 4-197
Integer Instructions
4-198 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
SECTION 5
FLOATING POINT INSTRUCTIONS
This section contains information about the floating-point instructions for the MC68881,
MC68882, and MC68040. In this section, all references to the MC68040 do not include the
MC68LC040 and MC68EC040. Each instruction is described in detail, and the instruction descriptions are arranged in alphabetical order by instruction mnemonic.
All floating-point instructions apply to the MC68881 and MC68882 processors. The
MC68040 directly supports part of the floating-point instructions through hardware. It indirectly supports the remainder by providing special traps and/or stack frames for the unimplemented instructions and data types. The following identification is noted under the instruction title for the MC68040:
Directly Supported—(MC6888X, MC68040)
Software Supported—(MC6888X, MC68040FPSW)
For all MC68040 floating-point instructions, the coprocessor ID field must be 001.
Table 5-1 lists the floating-point instructions directly supported by the MC68040, and Table
5-2 lists the floating-point instructions indirectly supported.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-1
Floating Point Instructions
Table 5-1. Directly Supported Floating-Point Instructions
Mnemonic
FABS
FADD
FBcc
FCMP
FDBcc
FDIV
FMOVE
FMOVE
FMOVEM
FMOVEM
FMUL
FNEG
FNOP
FRESTORE*
FSAVE*
FScc
FSORT
FSUB
FSGLDIV
FSFLMUL
FTRAPcc
FTST
Description
Floating-Point Absolute Value
Floating-Point Add
Floating-Point Branch Conditionally
Floating-Point Compare
Floating-Point Test Condition, Decrement, and Branch
Floating-Point Divide
Move Floating-Point Data Register
Move Floating-Point System Control Register
Move Multiple Floating-Point System Data Register
Move Multiple Floating-Point Control Data Register
Floating-Point Multiply
Floating-Point Negate
No Operation
Restore Internal Floating-Point State*
Save Internal Floating-Point State*
Set According to Floating-Point Condition
Floating-Point Square Root
Floating-Point Subtract
Floating-Point Single-Precision Divide
Floating-Point Single-Precision Multiply
Trap on Floating-Point Condition
Test Floating-Point Operand
*These are privileged instructions; refer to Section 6 Supervisor (Privaleged) Instructions for detailed information.
5-2 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FLOGNP1
FMOD
FMOVECR
FREM
FSCALE
FSIN
FSINCOS
FSINH
FTAN
FTANH
FTENTOX
FTWOTOX
Mnemonic
FACOS
FASIN
FATAN
FATANH
FCOS
FCOSH
FETOX
FETOXM1
FGETEXP
FGETMAN
FINT
FINTRZ
FLOG10
FLOG2
FLOGN
Table 5-2. Indirectly Supported Floating-Point Instructions
Description
Floating-Point Arc Cosine
Floating-Point Arc Sine
Floating-Point Arc Tangent
Floating-Point Hyperbolic Arc Tangent
Floating-Point Cosine
Floating-Point Hyperbolic Cosine
Floating-Point e x
Floating-Point e x
– 1
Floating-Point Get Exponent
Floating-Point Get Mantissa
Floating-Point Integer Part
Floating-Point Integer Part, Round-to- Zero
Floating-Point Log10
Floating-Point Log2
Floating-Point Loge
Floating-Point Log e
(x + 1)
Floating-Point Modulo Remainder
Floating-Point Move Constant ROM
Floating-Point IEEE Remainder
Floating-Point Scale Exponent
Floating-Point Sine
Floating-Point Simultaneous Sine and Cosine
Floating-Point Hyperbolic Sine
Floating-Point Tangent
Floating-Point Hyperbolic Tangent
Floating-Point 10 x
Floating-Point 2 x
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-3
Floating Point Instructions
FABS
Floating-Point Absolute Value
(MC6888X, MC68040)
Absolute Value of Source
→
FPn
FABS
Operation:
Assembler
Syntax: FABS. < fmt > < ea > ,FPn
FABS.X
FPm,FPn
FABS.X
FPn
*FrABS. < fmt > < ea > ,FPn
*FrABS.X
*FrABS.X
FPm,FPn
Pn where r is rounding precision, S or D
*Supported by MC68040 only.
Attributes: Format = (Byte, Word, Long, Single, Quad, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and stores the absolute value of that number in the destination floating-point data register.
FABS will round the result to the precision selected in the floating-point control register.
FSABS and FDABS will round the result to single or double precision, respectively, regardless of the rounding precision selected in the floating-point control register.
Operation Table:
DESTINATION
Result Absolute Value
SOURCE
Range Zero – + Infinity
Absolute Value Absolute Value
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information
–
5-4 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FABS
Floating-Point Absolute Value
(MC6888X, MC68040)
FABS
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers
Cleared
Cleared
If the source is an extended-precision denormalized number, refer to exception processing in the appropriate user’s manual; cleared otherwise.
Cleared
Cleared
If < fmt > is packed, refer to exception processing in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in exception processing; refer to the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
OPMODE
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-5
Floating Point Instructions
FABS
Floating-Point Absolute Value
(MC6888X, MC68040)
FABS
Instruction Fields:
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field specifies the location of the source operand. Only data addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
5-6 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FABS
Floating-Point Absolute Value
(MC6888X, MC68040)
FABS
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding will cause an unimplemented data type exception in the MC68040 to allow emulation in software.
Destination Register field—Specifies the destination floating- point data register.
Opmode field—Specifies the instruction and rounding precision.
0011000 FABS
Rounding precision specified by the floating-point control register.
1011000 FSABS Single-precision rounding specified.
1011100 FDABS Double-precision rounding specified.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-7
Floating Point Instructions
FACOS
Operation:
Assembler
Syntax:
Arc Cosine
(MC6888X, M68040FPSP)
Arc Cosine of Source
→
FPn
FACOS. < fmt > < ea > ,FPn
FACOS.X
FPm,FPn
FACOS.X
FPn
FACOS
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates the arc cosine of that number. Stores the result in the destination floatingpoint data register. This function is not defined for source operands outside of the range
[ – 1... + 1]; if the source is not in the correct range, a NAN is returned as the result and the OPERR bit is set in the floating- point status register. If the source is in the correct range, the result is in the range of [0...
π
].
Operation Table:
DESTINATION
Result
SOURCE
Range Zero – + Infinity –
Arc Cosine +
π
/2 NAN
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing .
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers .
Set if the source is infinity, > + 1 or < – 1; cleared otherwise.
Cleared
Cleared
Cleared
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
5-8 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FACOS FACOS
Arc Cosine
(MC6888X, M68040FPSP)
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 1 1 0 0
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn*
An
000
—
Register reg. number:Dn
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
010 reg. number:An
011 reg. number:An
100 reg. number:An
101 reg. number:An
110
110
110
110 reg. number:An reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Addressing Mode Mode Register
(xxx).W
(xxx).L
# < data >
111
111
111
000
001
100
(d
(d
8
16
,PC)
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-9
Floating Point Instructions
FACOS
Arc Cosine
(MC6888X, M68040FPSP)
FACOS
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is taken from the specified floating-point data register, and the result is then written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
5-10 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FADD
Operation:
Assembler
Syntax:
Floating-Point Add
(MC6888X, MC68040)
Source + FPn
→
FPn
FADD. < fmt > < ea > ,FPn
FADD.X FPm,FPn
*FrADD. < fmt > < ea > ,FPn
*FrADD.X
FPm,FPn where r is rounding precision, S or D
*Supported by MC68040 only.
FADD
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and adds that number to the number contained in the destination floating-point data register.
Stores the result in the destination floating-point data register.
FADD will round the result to the precision selected in the floating-point control register.
FSADD and FDADD will round the result to single or double-precision, respectively, regardless of the rounding precision selected in the floating-point control register.
Operation Table:
DESTINATION
In Range
Zero
Infinity
+
–
+
–
+
–
+ In Range
Add
– +
Add
SOURCE
1
Zero – +
+ inf
Add
+ 0.0
0.0
2
0.0
2
– 0.0
+ inf
+ inf
– inf
+ inf
– inf
1. If either operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Returns + 0.0 in rounding modes RN, RZ, and RP; returns – 0.0 in RM.
3. Sets the OPERR bit in the floating-point status register exception byte.
+ inf
NAN
‡
Infinity –
– inf
– inf
NAN
3
– inf
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-11
Floating Point Instructions
FADD
Floating-Point Add
(MC6888X, MC68040)
FADD
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source and the destination are opposite-signed infinities; cleared otherwise.
Refer to exception processing in the appropriate user’s manual.
Refer to exception processing in the appropriate user’s manual.
Cleared
Refer to exception processing in the appropriate user’s manual.
If < fmt > is packed, refer to exception processing in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in exception processing in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
OPMODE
Instruction Fields:
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
5-12 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FADD
Floating-Point Add
(MC6888X, MC68040)
FADD
If R/M = 1, specifies the location of the source operand location. Only data addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding will cause an unimplemented data type exception to allow emulation in software.
Destination Register field—Specifies the destination floating- point data register.
Opmode field—Specifies the instruction and rounding precision.
0100010 FADD Rounding precision specified by the floating-point control register.
1100010 FSADD Single-precision rounding specified.
1100110 FDADD Double-precision rounding specified.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-13
Floating Point Instructions
FASIN
Operation:
Assembler
Syntax:
Arc Sine
(MC6888X, M68040FPSP)
Arc Sine of the Source
→
FPn
FASIN. < fmt > < ea > ,FPn
FASIN.X
FPm,FPn
FASIN.X FPn
FASIN
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates the arc sine of the number. Stores the result in the destination floating-point data register. This function is not defined for source operands outside of the range [ –
1... + 1]; if the source is not in the correct range, a NAN is returned as the result and the OPERR bit is set in the floating- point status register. If the source is in the correct range, the result is in the range of [ –
π
/2... +
π
/2].
Operation Table:
DESTINATION
Result
+ In Range – +
Arc Sine + 0.0
SOURCE
1
Zero – +
– 0.0
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
Infinity
NAN
2
–
5-14 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FASIN
Arc Sine
(MC6888X, M68040FPSP)
FASIN
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is infinity, > + 1 or < – 1; cleared otherwise
Cleared
Can be set for an underflow condition.
Cleared
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 1 1 0 0
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-15
Floating Point Instructions
FASIN
Arc Sine
(MC6888X, M68040FPSP)
FASIN
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is taken from the specified floating-point data register, and the result is then written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
5-16 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FATAN
Operation:
Assembler
Syntax:
Arc Tangent
(MC6888X, M68040FPSP)
Arc Tangent of Source
→
FPn
FATAN. < fmt > < ea > ,FPn
FATAN.X
FPm,FPn
FATAN.X
FPm,FPnz
FATAN
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates the arc tangent of that number. Stores the result in the destination floatingpoint data register. The result is in the range of [ –
π
/2... +
π
/2].
Operation Table:
DESTINATION
Result
+ In Range – +
Arc Tangent + 0.0
SOURCE
Zero – + Infinity –
– 0.0 +
π
/2 –
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Cleared
Refer to underflow in the appropriate user’s manual.
Cleared
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-17
Floating Point Instructions
FATAN
Arc Tangent
(MC6888X, M68040FPSP)
FATAN
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 1 1 0 0
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
5-18 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FATAN
Arc Tangent
(MC6888X, M68040FPSP)
FATAN
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is taken from the specified floating-point data register, and the result is then written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-19
Floating Point Instructions
FATANH
Operation:
Hyperbolic Arc Tangent
(MC6888X, M68040FPSP)
Hyperbolic Arc Tangent of Source
→
FPn
Assembler
Syntax:
FATANH. < fmt > < ea > ,FPn
FATANH.X
FPm,FPn
FATANH.X
FPn
FATANH
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates the hyperbolic arc tangent of that value. Stores the result in the destination floating-point data register. This function is not defined for source operands outside of the range ( – 1... + 1); and the result is equal to – infinity or + infinity if the source is equal to + 1 or – 1, respectively. If the source is outside of the range [ – 1... + 1], a NAN is returned as the result, and the OPERR bit is set in the floating-point status register.
Operation Table:
DESTINATION
Result
+ In Range – +
Hyperbolic
Arc Tangent
+ 0.0
SOURCE
1
Zero – +
– 0.0
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
Infinity
NAN
2
–
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte: Not affected.
5-20 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FATANH
Hyperbolic Arc Tangent
(MC6888X, M68040FPSP)
FATANH
Exception Byte: BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is > + 1 or < – 1; cleared otherwise.
Cleared
Refer to underflow in the appropriate user’s manual.
Set if the source is equal to + 1 or – 1; cleared otherwise.
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 1 1 0 1
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-21
Floating Point Instructions
FATANH
Hyperbolic Arc Tangent
(MC6888X, M68040FPSP)
FATANH
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is taken from the specified floating-point data register, and the result is then written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
5-22 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FBcc
Floating-Point Branch Conditionally
(MC6888X, MC68040)
FBcc
Operation: If Condition True
Then PC + d n
→
PC
Assembler:
Syntax:
Attributes:
FBcc. < size > , < label >
Size = (Word, Long)
Description: If the specified floating-point condition is met, program execution continues at the location (PC) + displacement. The displacement is a twos-complement integer that counts the relative distance in bytes. The value of the program counter used to calculate the destination address is the address of the branch instruction plus two. If the displacement size is word, then a 16- bit displacement is stored in the word immediately following the instruction operation word. If the displacement size is long word, then a 32-bit displacement is stored in the two words immediately following the instruction operation word. The conditional specifier cc selects any one of the 32 floating- point conditional tests as described in 3.6.2 Conditional Testing.
Floating-Point Status Register:
Condition Codes: Not affected.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVF
UNFL
DZ
INEX2
INEX1
Set if the NAN condition code is set and the condition selected is an IEEE nonaware test.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Accrued Exception Byte: The IOP bit is set if the BSUN bit is set in the exception byte. No other bit is affected.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-23
Floating Point Instructions
FBcc
Floating-Point Branch Conditionally
(MC6888X, MC68040)
Instruction Format:
FBcc
15
1
14
1
13
1
12
1
11 10 9
COPROCESSOR
ID
8
0
7
1
6
SIZE
5 4 3 2 1
CONDITIONAL PREDICATE
16-BIT DISPLACEMENT OR MOST SIGNIFICANT WORD OF 32-BITDISPLACEMENT
LEAST SIGNIFICANT WORD OF 32-BIT DISPLACEMENT (IF NEEDED)
Instruction Fields:
0
Size field—Specifies the size of the signed displacement.
If Format = 0, then the displacement is 16 bits and is sign- extended before use.
If Format = 1, then the displacement is 32 bits.
Conditional Predicate field—Specifies one of 32 conditional tests as defined in Table
3-23 Floating-Point Conditional Tests.
NOTE
When a BSUN exception occurs, the main processor takes a preinstruction exception. If the exception handler returns without modifying the image of the program counter on the stack frame
(to point to the instruction following the FBcc), then it must clear the cause of the exception (by clearing the NAN bit or disabling the BSUN trap), or the exception will occur again immediately upon return to the routine that caused the exception.
5-24 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FCMP
Floating-Point Compare
(MC6888X, MC68040)
FCMP
Operation:
Assembler
Syntax:
Attributes:
FPn – Source
FCMP. < fmt > < ea > ,FPn
FCMP.X FPm,FPn
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and subtracts the operand from the destination floating- point data register. The result of the subtraction is not retained, but it is used to set the floating-point condition codes as described in 3.6.2 Conditional Testing.
Operation Table: The entries in this operation table differ from those of the tables describing most of the floating-point instructions. For each combination of input operand types, the condition code bits that may be set are indicated. If the name of a condition code bit is given and is not enclosed in brackets, then it is always set. If the name of a condition code bit is enclosed in brackets, then that bit is either set or cleared, as appropriate. If the name of a condition code bit is not given, then that bit is always cleared by the operation. The infinity bit is always cleared by the FCMP instruction since it is not used by any of the conditional predicate equations. Note that the NAN bit is not shown since NANs are always handled in the same manner (as described in 1.6.5 Not-A-Numbers).
DESTINATION
In Range
Zero
–
+ In Range – +
SOURCE
Zero – + Infinity –
+
–
{NZ} none
N {NZ} none
N
none
N
N none
N none
+ N none
N none NZ NZ
N none
N none
– none none
N N none none
N N
Z none
N NZ
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-25
Floating Point Instructions
FCMP
Floating-Point Compare
(MC6888X, MC68040)
FCMP
Floating-Point Status Register:
Condition Codes: Affected as described in the preceding operation table.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Cleared
Cleared
Cleared
Cleared
If < fmt > is packed, refer to exception processing in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in exception processing in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 1 1 0 0
5-26 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FCMP
Floating-Point Compare
(MC6888X, MC68040)
FCMP
Instruction Fields:
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, specifies the location of the source operand location. Only data addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding in the MC68040 will cause an unimplemented data type exception to allow emulation in software.
Destination Register field—Specifies the destination floating- point data register.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-27
Floating Point Instructions
FCOS
Operation:
Assembler
Syntax:
Attributes:
Cosine
(MC6888X, M68040FPSP)
Cosine of Source
→
FPn
FCOS. < fmt > < ea > ,FPn
FCOS.X FPm,FPn FCOS.X FPn
FCOS
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates the cosine of that number. Stores the result in the destination floating-point data register. This function is not defined for source operands of
±
infinity. If the source operand is not in the range of [ – 2
π
... + 2
π
], then the argument is reduced to within that range before the cosine is calculated. However, large arguments may lose accuracy during reduction, and very large arguments (greater than approximately 10
20
) lose all accuracy. The result is in the range of [ – 1... + 1].
Operation Table:
DESTINATION
Result
+ In Range
Cosine
– +
SOURCE
1
Zero
+ 1.0
– +
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
Infinity
NAN
2
–
5-28 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FCOS
Cosine
(MC6888X, M68040FPSP)
FCOS
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source operand is
±
infinity; cleared otherwise.
Cleared
Cleared
Cleared
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 1 1 0 1
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-29
Floating Point Instructions
FCOS
Cosine
(MC6888X, M68040FPSP)
FCOS
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should contain zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is taken from the specified floating-point data register, and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
5-30 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FCOSH
Operation:
Assembler
Syntax:
Attributes:
Hyperbolic Cosine
(MC6888X, M68040FPSP)
Hyperbolic Cosine of Source
→
FPn
FCOSH. < fmt > < ea > ,FPn
FCOSH.X FPm,FPn FCOSH.X FPn
FCOSH
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates the hyperbolic cosine of that number. Stores the result in the destination floating-point data register.
Operation Table:
DESTINATION
Result
+ In Range – +
Hyperbolic Cosine
SOURCE
Zero
+ 1.0
– +
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
Infinity
+ inf
–
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Refer to overflow in the appropriate user’s manual.
Cleared
Cleared
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-31
Floating Point Instructions
FCOSH
Hyperbolic Cosine
(MC6888X, M68040FPSP)
FCOSH
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 1 1 0 1
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
5-32 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FCOSH
Hyperbolic Cosine
(MC6888X, M68040FPSP)
FCOSH
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is taken from the specified floating-point data register, and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-33
Floating Point Instructions
FDBcc
Floating-Point Test Condition,
Decrement, and Branch
(MC6888X, MC68040)
FDBcc
Operation: If Condition True
Then No Operation
Else Dn – 1
→
Dn
If Dn
≠
– 1
Then PC + d n
→
PC
Else Execute Next Instruction
Assembler
Syntax:
Attributes:
FDBcc Dn, < label >
Unsized
Description: This instruction is a looping primitive of three parameters: a floating-point condition, a counter (data register), and a 16-bit displacement. The instruction first tests the condition to determine if the termination condition for the loop has been met, and if so, execution continues with the next instruction in the instruction stream. If the termination condition is not true, the low-order 16 bits of the counter register are decremented by one. If the result is – 1, the count is exhausted, and execution continues with the next instruction. If the result is not equal to – 1, execution continues at the location specified by the current value of the program counter plus the signextended 16-bit displacement. The value of the program counter used in the branch address calculation is the address of the displacement word.
The conditional specifier cc selects any one of the 32 floating- point conditional tests as described in 3.6.2 Conditional Testing.
Floating-Point Status Register:
Condition Codes: Not affected.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
NEX2
INEX1
Set if the NAN condition code is set and the condition selected is an IEEE nonaware test.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Accrued Exception Byte: The IOP bit is set if the BSUN bit is set in the exception byte. No other bit is affected.
5-34 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
FDBcc
Floating-Point Test Condition,
Decrement, and Branch
(MC6888X, MC68040)
Floating Point Instructions
FDBcc
Instruction Format:
15
1
0
14
1
0
13
1
0
12
1
0
11 10 9
COPROCESSOR
ID
0 0
8
0
7
0
6
1
0 0 0 0
16-BIT DISPLACEMENT
5
0
4
0
3
1
2 1
COUNT
REGISTER
CONDITIONAL PREDICATE
0
Instruction Fields:
Count Register field—Specifies data register that is used as the counter.
Conditional Predicate field—Specifies one of the 32 floating-point conditional tests as described in 3.6.2 Conditional Testing.
Displacement field—Specifies the branch distance (from the address of the instruction plus two) to the destination in bytes.
NOTE
The terminating condition is like that defined by the UNTIL loop constructs of high-level languages. For example: FDBOLT can be stated as "decrement and branch until ordered less than".
There are two basic ways of entering a loop: at the beginning or by branching to the trailing FDBcc instruction. If a loop structure terminated with FDBcc is entered at the beginning, the control counter must be one less than the number of loop executions desired. This count is useful for indexed addressing modes and dynamically specified bit operations. However, when entering a loop by branching directly to the trailing FDBcc instruction, the count should equal the loop execution count. In this case, if the counter is zero when the loop is entered, the FDBcc instruction does not branch, causing a complete bypass of the main loop.
When a BSUN exception occurs, a preinstruction exception is taken by the main processor. If the exception handler returns without modifying the image of the program counter on the stack frame (to point to the instruction following the FDBcc), then it must clear the cause of the exception (by clearing the NAN bit or disabling the BSUN trap), or the exception will occur again immediately upon return to the routine that caused the exception.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-35
Floating Point Instructions
FDIV
Operation:
Assembler
Syntax:
Floating-Point Divide
(MC6888X, MC68040)
FPn
÷
Source
→
FPn
FDIV. < fmt > < ea > ,FPn
FDIV.X FPm,FPn
*FrDIV. < fmt > < ea > ,FPn
*FrDIV.X FPm,FPn where r is rounding precision, S or D
*Supported by MC68040 only
FDIV
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and divides that number into the number in the destination floating-point data register. Stores the result in the destination floating-point data register.
FDIV will round the result to the precision selected in the floating-point control register.
FSDIV and FDDIV will round the result to single or double precision, respectively, regardless of the rounding precision selected in the floating-point control register.
Operation Table:
DESTINATION +
In Range +
–
Zero +
–
+ 0.0
– 0.0
In Range – +
Divide
+ inf
2
– inf
2
+ 0.0
+ 0.0
SOURCE
1
Zero – +
– inf
2
+ inf
2
+ 0.0
– 0.0
NAN
3
+ 0.0
– 0.0
– inf
+ inf
+ inf
– inf
– inf
+ inf
–
– inf
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the DZ bit in the floating-point status register exception byte.
3. Sets the OPERR bit in the floating-point status register exception byte.
Infinity –
– 0.0
+ 0.0
– 0.0
+ 0.0
NAN‡
5-36 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FDIV
Floating-Point Divide
(MC6888X, MC68040)
FDIV
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set for 0
÷
0 or infinity
÷
infinity; cleared otherwise.
Refer to exception processing in the appropriate user’s manual.
Refer to exception processing in the appropriate user’s manual.
Set if the source is zero and the destination is in range; cleared otherwise.
Refer to exception processing in the appropriate user’s manual.
If < fmt > is packed, refer to exception processing in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in exception processing in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
OPMODE
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-37
Floating Point Instructions
FDIV
Floating-Point Divide
(MC6888X, MC68040)
FDIV
Instruction Fields:
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, specifies the location of the source operand location. Only data addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding in the MC68040 will cause an unimplemented data type exception to allow emulation in software.
5-38 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FDIV
Floating-Point Divide
(MC6888X, MC68040)
FDIV
Destination Register field—Specifies the destination floating- point data register.
Opmode field—Specifies the instruction and rounding precision.
0100000 FDIV Rounding precision specified by the floating- point control register.
1100000 FSDIV Single-precision rounding specified.
1100100 FDDIV Double-precision rounding specified.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-39
Floating Point Instructions
FETOX
Operation:
Assembler
Syntax:
Syntax:
Attributes:
e
x
(MC6888X, M68040FPSP) e
Source →
FPn
FETOX. < fmt > < ea > ,FPn
FETOX.X FPm,FPn
FETOX.X FPn
FETOX
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates e to the power of that number. Stores the result in the destination floatingpoint data register.
Operation Table:
DESTINATION
Result
+ In Range – + e x
SOURCE
Zero
+ 1.0
– +
+ inf
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
Infinity –
+ 0.0
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Refer to overflow in the appropriate user’s manual.
Refer to underflow in the appropriate user’s manual.
Cleared
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
5-40 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
FETOX
e
x
(MC6888X, M68040FPSP)
Floating Point Instructions
FETOX
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 1 1 0 0
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-41
Floating Point Instructions
FETOX
e
x
(MC6888X, M68040FPSP)
FETOX
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier Field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is taken from the specified floating-point data register, and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
5-42 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FETOXM1
Operation:
e
x
– 1
(MC6888X, M68040FPSP) e
Source
– 1
→
FPn
Assembler
Syntax:
FETOXM1. < fmt > < ea > ,FPn
FETOXM1.X FPm,FPn
FETOXM1.X FPn
FETOXM1
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates e to the power of that number. Subtracts one from the value and stores the result in the destination floating-point data register.
Operation Table:
DESTINATION
Result
+ In Range e x
– 1
– +
+ 0.0
SOURCE
Zero – +
– 0.0 + inf
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
Infinity –
– 1.0
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN Cleared
SNAN
OPERR
OVFL
Refer to 1.6.5 Not-A-Numbers.
Cleared
UNFL
DZ
INEX2
Refer to overflow in the appropriate user’s manual.
Refer to underflow in the appropriate user’s manual.
Cleared
INEX1
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-43
Floating Point Instructions
FETOXM1
e
x
– 1
(MC6888X, M68040FPSP)
FETOXM1
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 1 1 0 0
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
5-44 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FETOXM1
e
x
– 1
(MC6888X, M68040FPSP)
FETOXM1
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier Field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is taken from the specified floating-point data register, and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-45
Floating Point Instructions
FGETEXP
Operation:
Get Exponent
(MC6888X, M68040FPSP)
Exponent of Source
→
FPn
Assembler
Syntax:
FGETEXP. < fmt > < ea > ,FPn
FGETEXP.X FPm,FPn
FGETEXP.X FPn
FGETEXP
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and extracts the binary exponent. Removes the exponent bias, converts the exponent to an extended-precision floating- point number, and stores the result in the destination floating- point data register.
Operation Table:
DESTINATION
Result
+ In Range
Exponent
– +
+ 0.0
SOURCE
1
Zero – +
– 0.0
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
Infinity
NAN
2
–
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is
±
infinity; cleared otherwise.
Cleared
Cleared
Cleared
Cleared
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
5-46 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
FGETEXP
Get Exponent
(MC6888X, M68040FPSP)
Floating Point Instructions
FGETEXP
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 1 1 1 0
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-47
Floating Point Instructions
FGETEXP
Get Exponent
(MC6888X, M68040FPSP)
FGETEXP
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is taken from the specified floating-point data register, and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
5-48 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FGETMAN
Operation:
Get Mantissa
(MC6888X, M68040FPSP)
Mantissa of Source
→
FPn
Assembler
Syntax:
FGETMAN. < fmt > < ea > ,FPn
FGETMAN.X FPm,FPn
FGETMAN.X FPn
FGETMAN
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and extracts the mantissa. Converts the mantissa to an extended-precision value and stores the result in the destination floating-point data register. The result is in the range
[1.0...2.0] with the sign of the source mantissa, zero, or a NAN.
Operation Table:
DESTINATION
Result
+ In Range – +
Mantissa + 0.0
SOURCE
1
Zero – +
– 0.0
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
Infinity
NAN
2
–
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is
±
infinity; cleared otherwise.
Cleared
Cleared
Cleared
Cleared
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-49
Floating Point Instructions
FGETMAN
Get Mantissa
(MC6888X, M68040FPSP)
FGETMAN
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 1 1 1 1
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
5-50 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FGETMAN
Get Mantissa
(MC6888X, M68040FPSP)
FGETMAN
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is taken from the specified floating-point data register, and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-51
Floating Point Instructions
FINT
Operation:
Assembler
Syntax:
Integer Part
(MC6888X, M68040FPSP)
Integer Part of Source
→
FPn
FINT. < fmt > < ea > ,FPn
FINT.X FPm,FPn
FINT.X FPn
FINT
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary), extracts the integer part, and converts it to an extended-precision floating-point number. Stores the result in the destination floating-point data register. The integer part is extracted by rounding the extended-precision number to an integer using the current rounding mode selected in the floating-point control register mode control byte. Thus, the integer part returned is the number that is to the left of the radix point when the exponent is zero, after rounding. For example, the integer part of 137.57 is 137.0 for the round-to-zero and round-to- negative infinity modes and 138.0 for the round-to-nearest and round-topositive infinity modes. Note that the result of this operation is a floating-point number.
Operation Table:
DESTINATION
Result
+ In Range – +
Integer + 0.0
SOURCE
Zero – +
– 0.0
Infinity
+ inf – inf
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
–
5-52 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FINT
Integer Part
(MC6888X, M68040FPSP)
FINT
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Cleared
Cleared
Cleared
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 0 0 1
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-53
Floating Point Instructions
FINT
Integer Part
(MC6888X, M68040FPSP)
FINT
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is taken from the specified floating-point data register, and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
5-54 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FINTRZ
Operation:
Assembler
Syntax:
Integer Part, Round-to-Zero
(MC6888X, M68040FPSP)
Integer Part of Source
→
FPn
FINTRZ. < fmt > < ea > ,FPn
FINTRZ.X FPm,FPn
FINTRZ.X FPn
FINTRZ
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and extracts the integer part and converts it to an extended-precision floating-point number.
Stores the result in the destination floating-point data register. The integer part is extracted by rounding the extended-precision number to an integer using the round-tozero mode, regardless of the rounding mode selected in the floating-point control register mode control byte (making it useful for FORTRAN assignments). Thus, the integer part returned is the number that is to the left of the radix point when the exponent is zero. For example, the integer part of 137.57 is 137.0; the integer part of
0.1245 x 102 is 12.0. Note that the result of this operation is a floating-point number.
Operation Table:
DESTINATION
Result
+ In Range – +
Integer, Forced
Round-to- Zero
+ 0.0
SOURCE
Zero – +
– 0.0 + inf
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
Infinity –
– inf
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-55
Floating Point Instructions
FINTRZ
Integer Part, Round-to-Zero
(MC6888X, M68040FPSP)
FINTRZ
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Cleared
Cleared
Cleared
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 0 1 1
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
5-56 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FINTRZ
Integer Part, Round-to-Zero
(MC6888X, M68040FPSP)
FINTRZ
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If RM = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is taken from the specified floating-point data register, and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-57
Floating Point Instructions
FLOG10
Operation:
Assembler
Syntax:
Log
10
(MC6888X, M68040FPSP)
Log
10
of Source
→
FPn
FLOG10. < fmt > < ea > ,FPn
FLOG10.X FPm,FPn
FLOG10.X FPn
FLOG10
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Convert the source operand to extended precision (if necessary) and calculates the logarithm of that number using base 10 arithmetic. Stores the result in the destination floating-point data register. This function is not defined for input values less than zero.
Operation Table:
DESTINATION
Result
+ In Range – +
Log
10
NAN
2
SOURCE
1
Zero
– inf
3
– +
+ inf
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
3. Sets the DZ bit in the floating-point status register exception byte.
Infinity –
NAN
2
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source operand is < 0; cleared otherwise.
Cleared
Cleared
Set if the source is
±
0; cleared otherwise
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
5-58 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
FLOG10
Log
10
(MC6888X, M68040FPSP)
Floating Point Instructions
FLOG10
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 0 1 0 1
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-59
Floating Point Instructions
FLOG10
Log
10
(MC6888X, M68040FPSP)
FLOG10
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is taken from the specified floating-point data register, and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
5-60 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FLOG2
Operation:
Assembler
Syntax:
Log
2
(MC6888X, M68040FPSP)
Log
2
of Source
→
FPn
FLOG2. < fmt > < ea > ,FPn
FLOG2.X FPm,FPn
FLOG2.X FPn
FLOG2
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates the logarithm of that number using base two arithmetic. Stores the result in the destination floating- point data register. This function is not defined for input values less than zero.
Operation Table:
DESTINATION
Result
+
Log
2
In Range – +
NAN
2
SOURCE
1
Zero
– inf
3
– +
+ inf
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
3. Sets the DZ bit in the floating-point status register exception byte.
Infinity –
NAN
2
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is < 0; cleared otherwise
Cleared
Cleared
Set if the source is
±
0; cleared otherwise
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-61
Floating Point Instructions
FLOG2
Log
2
(MC6888X, M68040FPSP)
FLOG2
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 0 1 1 0
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
5-62 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FLOG2
Log
2
(MC6888X, M68040FPSP)
FLOG2
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is taken from the specified floating-point data register, and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-63
Floating Point Instructions
FLOGN
Operation:
Assembler
Syntax:
Log
e
(MC6888X, M68040FPSP)
Log e
of Source
→
FPn
FLOGN. < fmt > < ea > ,FPn
FLOGN.X FPm,FPn
FLOGN.X FPn
FLOGN
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates the natural logarithm of that number. Stores the result in the destination floating-point data register. This function is not defined for input values less than zero.
Operation Table:
DESTINATION
Result
+
In(x)
In Range – +
NAN
2
SOURCE
1
Zero
– inf
3
– +
+ inf
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
3. Sets the DZ bit in the floating-point status register exception byte.
Infinity –
NAN
2
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source operand is < 0; cleared otherwise.
Cleared
Cleared
Set if the source is
±
0; cleared otherwise
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
5-64 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
FLOGN
Log
e
(MC6888X, M68040FPSP)
Floating Point Instructions
FLOGN
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 0 1 0 0
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-65
Floating Point Instructions
FLOGN
Log
e
(MC6888X, M68040FPSP)
FLOGN
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is taken from the specified floating-point data register, and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
5-66 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FLOGNP1
Operation:
Log
e
(x + 1)
(MC6888X, M68040FPSP)
Log e
of (Source + 1)
→
FPn
Assembler
Syntax:
FLOGNP1. < fmt > < ea > ,FPn
FLOGNP1.X FPm,FPn
FLOGNP1.X FPn
FLOGNP1
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary), adds one to that value, and calculates the natural logarithm of that intermediate result. Stores the result in the destination floating-point data register. This function is not defined for input values less than – 1.
Operation Table:
DESTINATION
Result
+
In(x + 1)
In Range – +
In(x + 1)
2 + 0.0
SOURCE
1
Zero – +
– 0.0 + inf
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. If the source is – 1, sets the DZ bit in the floating-point status register exception byte and returns a NAN. If the source is < – 1, sets the OPERR bit in the floating-point status register exception byte and returns a NAN.
3. Sets the OPERR bit in the floating-point status register exception byte.
Infinity –
NAN
2
3
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte: Not affected.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-67
Floating Point Instructions
FLOGNP1
Log
e
(x + 1)
(MC6888X, M68040FPSP)
FLOGNP1
Exception Byte: BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source operand is < – 1; cleared otherwise.
Cleared
Refer to underflow in the appropriate user’s manual.
Set if the source operand is – 1; cleared otherwise
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 1 1 0
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
5-68 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FLOGNP1
Log
e
(x + 1)
(MC6888X, M68040FPSP)
FLOGNP1
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is taken from the specified floating-point data register, and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-69
Floating Point Instructions
FMOD
Operation:
Assembler
Syntax:
Attributes:
Modulo Remainder
(MC6888X, M68040FPSP)
Modulo Remainder of (FPn
÷
Source)
→
FPn
FMOD. < fmt > < ea > ,FPn
FMOD.X FPm,FPn
FMOD
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates the modulo remainder of the number in the destination floating-point data register, using the source operand as the modulus. Stores the result in the destination floating-point data register and stores the sign and seven least significant bits of the quotient in the floating-point status register quotient byte (the quotient is the result of
FPn
÷
Source). The modulo remainder function is defined as:
FPn – (Source x N) where N = INT(FPn
÷
Source) in the round-to-zero mode.
The FMOD function is not defined for a source operand equal to zero or for a destination operand equal to infinity. Note that this function is not the same as the FREM instruction, which uses the round-to-nearest mode and thus returns the remainder that is required by the IEEE Specification for Binary Floating-Point Arithmetic.
Operation Table:
DESTINATION + In Range
In Range
Zero
+
–
+
–
Modulo Remainder
+ 0.0
– 0.0
Infinity +
–
NAN
2
– +
SOURCE
1
Zero#
NAN
2
NAN
2
NAN
2
– +
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
3. Returns the value of FPn before the operation. However, the result is processed by the normal instruction termination procedure to round it as required. Thus, an overflow and/or inexact result may occur if the rounding precision has been changed to a smaller size since the FPn value was loaded
Infinity
FPn
3
+ 0.0
– 0.0
NAN
2
–
5-70 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FMOD
Modulo Remainder
(MC6888X, M68040FPSP)
FMOD
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Loaded with the sign and least significant seven bits of the quotient (FPn
÷
Source). The sign of the quotient is the exclusive-OR of the sign bits of the source and destination operands.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is zero or the destination is infinity; cleared otherwise.
Cleared
Refer to underflow in the appropriate user’s manual.
Cleared
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, in the appropriate user’s manual for inexact result on decimal input; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
1
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 1 1 0 1
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-71
Floating Point Instructions
FMOD
Modulo Remainder
(MC6888X, M68040FPSP)
FMOD
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register.
5-72 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FMOVE
Move Floating-Point Data Register
FMOVE
(MC6888X, MC68040)
Operation: Source
→
Destination
Assembler
Syntax:
FMOVE. < fmt > < ea > ,FPn
FMOVE. < fmt > FPm, < ea >
FMOVE.P FPm, < ea > {Dn}
FMOVE.P FPm, < ea > {k}
*FrMOVE. < fmt > < ea > ,FPn where r is rounding precision, S or D
*Supported by MC68040 only
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Moves the contents of the source operand to the destination operand.
Although the primary function of this instruction is data movement, it is also considered an arithmetic instruction since conversions from the source operand format to the destination operand format are performed implicitly during the move operation. Also, the source operand is rounded according to the selected rounding precision and mode.
Unlike the MOVE instruction, the FMOVE instruction does not support a memory-tomemory format. For such transfers, it is much faster to utilize the MOVE instruction to transfer the floating- point data than to use the FMOVE instruction. The FMOVE instruction only supports memory-to-register, register-to- register, and register-tomemory operations (in this context, memory may refer to an integer data register if the data format is byte, word, long, or single). The memory-to-register and register- to-register operation uses a command word encoding distinctly different from that used by the register-to-memory operation; these two operation classes are described separately.
Memory-to-Register and Register-to-Register Operation: Converts the source operand to an extended-precision floating-point number (if necessary) and stores it in the destination floating-point data register. MOVE will round the result to the precision selected in the floating-point control register. FSMOVE and FDMOVE will round the result to single or double precision, respectively, regardless of the rounding precision selected in the floating-point control register. Depending on the source data format and the rounding precision, some operations may produce an inexact result. In the following table, combinations that can produce an inexact result are marked with a dot (
⋅
), but all other combinations produce an exact result.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-73
Floating Point Instructions
FMOVE
Move Floating-Point Data Register
FMOVE
(MC6888X, MC68040)
Rounding
Precision
Single
Double
Extended
B W
⋅
L
Source Format
S D X
⋅ ⋅ ⋅
⋅ ⋅
⋅
P
Floating-Point Status Register ( < ea > to Register):
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Cleared
Refer to exception processing in the appropriate user’s manual if the source is an extended-precision denormalized number; cleared otherwise.
Cleared
Refer to exception processing in the appropriate user’s manual if < fmt > is L,D, or
X; cleared otherwise.
Refer to exception processing in the appropriate user’s manual if < fmt > is P; cleared otherwise.
Accrued Exception Byte: Affected as described in exception processing in the appropriate user’s manual.
5-74 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FMOVE
Move Floating-Point Data Register
FMOVE
(MC6888X, MC68040)
Instruction Format:
< EA > TO REGISTER
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
OPMODE
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, specifies the location of the source operand. Only data addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-75
Floating Point Instructions
FMOVE
Move Floating-Point Data Register
FMOVE
(MC6888X, MC68040)
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding in the MC68040 will cause an unimplemented data type exception to allow emulation in software.
Destination Register field—Specifies the destination floating- point data register.
Opmode field—Specifies the instruction and rounding precision.
0000000 FMOVE Rounding precision specified by the floating-point control register.
1000000 FSMOVE Single-precision rounding specified.
1000100 FDMOVE Double-precision rounding specified.
Register-to-Memory Operation: Rounds the source operand to the size of the specified destination format and stores it at the destination effective address. If the format of the destination is packed decimal, a third operand is required to specify the format of the resultant string. This operand, called the k-factor, is a 7-bit signed integer (twos complement) and may be specified as an immediate value or in an integer data register. If a data register contains the k-factor, only the least significant seven bits are used, and the rest of the register is ignored.
5-76 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FMOVE
Move Floating-Point Data Register
FMOVE
(MC6888X, MC68040)
Floating-Point Status Register (Register-to-Memory):
Condition Codes: Not affected.
Quotient Byte:
Exception Byte:
Not affected.
BSUN Cleared
< fmt > is B, W, or L
< fmt > is S, D, or X
< fmt > is P
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
BSUN
SNAN
OVFL
UNFL
DZ
INEX2
INEX1
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
Refer to 1.6.5 Not-A-Numbers.
Set if the source operand is infinity or if the destination size is exceeded after conversion and rounding; cleared otherwise.
Cleared
Cleared
Cleared
Refer to exception processing in the appropriate user’s manual.
Cleared
Cleared
Refer to 1.6.5 Not-A-Numbers
Refer to exception processing in the appropriate user’s manual.
Refer to exception processing in the appropriate user’s manual.
Cleared
Refer to exception processing in the appropriate user’s manual.
Cleared
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the k-factor > + 17 or the magnitude of the decimal exponent exceeds three digits; cleared otherwise.
Cleared
Cleared
Cleared
Refer to exception processing in the appropriate user’s manual.
Cleared INEX1
Accrued Exception Byte: Affected as described in exception processing in the appropriate user’s manual.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-77
Floating Point Instructions
FMOVE
Move Floating-Point Data Register
FMOVE
(MC6888X, MC68040)
Instruction Format:
REGISTER—TO-MEMORY
15
1
0
14
1
1
13
1
1
12 11 10
COPROCESSOR
ID
DESTINATION
FORMAT
Instruction Fields:
9
1
8
0
SOURCE
REGISTER
7
0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
REGISTER MODE
K-FACTOR
(IF REQUIRED)
0
Effective Address field—Specifies the destination location. Only data alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
—
001
—
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
—
—
—
—
Destination Format field—Specifies the data format of the destination operand:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real with Static k-Factor (P{#k})*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
111 — Packed-Decimal Real with Dynamic k-Factor (P{Dn})*
*This encoding will cause an unimplemented data type exception in the
MC68040 to allow emulation in software.
5-78 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FMOVE
Move Floating-Point Data Register
FMOVE
(MC6888X, MC68040)
Source Register field—Specifies the source floating-point data register. k-Factor field—If the destination format is packed decimal, used to specify the format of the decimal string. For any other destination format, this field should be set to all zeros. For a static k-factor, this field is encoded with a twos-complement integer where the value defines the format as follows:
– 64 to 0—Indicates the number of significant digits to the right of the decimal point (FORTRAN "F" format).
+ 1 to + 17—Indicates the number of significant digits in the mantissa (FOR-
TRAN "E" format).
+ 18 to + 63—Sets the OPERR bit in the floating-point status register exception byte and treated as + 17.
The format of this field for a dynamic k-factor is: r r r 0 0 0 0 where "rrr" is the number of the main processor data register that contains the k-factor value.
The following table gives several examples of how the k-factor value affects the format of the decimal string that is produced by the floating-point coprocessor. The format of the string that is generated is independent of the source of the k-factor (static or dynamic). k- Factor Source Operand Value
– 5 + 12345.678765
Destination String
+ 1.234567877E + 4
– 3 + 12345.678765
+ 1.2345679E + 4
– 1 + 12345.678765
+ 1.23457E + 4
0 + 12345.678765
+ 1.2346E + 4
+ 1 + 12345.678765
+ 1.E + 4
+ 3 + 12345.678765
+ 1.23E + 4
+ 5 + 12345.678765
+ 1.2346E + 4
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-79
Floating Point Instructions
FMOVE
Operation:
Assembler
Syntax:
Attributes:
Move Floating-Point
System Control Register
(MC6888X, MC68040)
Source
→
Destination
FMOVE.L < ea > ,FPCR
FMOVE.L FPCR, < ea >
FMOVE
Size = (Long)
Description: Moves the contents of a floating-point system control register (floating-point control register, floating-point status register, or floating-point instruction address register) to or from an effective address. A 32-bit transfer is always performed, even though the system control register may not have 32 implemented bits. Unimplemented bits of a control register are read as zeros and are ignored during writes (must be zero for compatibility with future devices). For the MC68881, this instruction does not cause pending exceptions (other than protocol violations) to be reported. Furthermore, a write to the floating-point control register exception enable byte or the floating-point status register exception status byte cannot generate a new exception, regardless of the value written.
Floating-Point Status Register: Changed only if the destination is the floating-point status register, in which case all bits are modified to reflect the value of the source operand.
Instruction Format:
15
1
1
14
1
0
13
1 dr
12
1
11 10 9
COPROCESSOR
ID
REGISTER
SELECT
0
8
0
0
7
0
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 0 0 0
5-80 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FMOVE
Move Floating-Point
System Control Register
(MC6888X, MC68040)
FMOVE
Instruction Fields:
Effective Address field—(Memory-to-Register) All addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn 000
Register reg. number:Dn
An*
(An)
001
010 reg. number:An reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
(d
16
(d
8
,PC)
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
*Only if the source register is the floating-point instruction address register.
111
111
111
111
111
111
111
001
100
010
011
011
011
011
Effective Address field—(Register-to-Memory) Only alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn 000
Register reg. number:Dn
An*
(An)
001
010 reg. number:An reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
(d
16
(d
8
,PC)
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
*Only if the source register is the floating-point instruction address register.
111
—
—
—
—
—
—
001
—
—
—
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-81
Floating Point Instructions
FMOVE
Move Floating-Point
System Control Register
(MC6888X, MC68040)
FMOVE dr field—Specifies the direction of the data transfer.
0 — From < ea > to the specified system control register.
1 — From the specified system control register to < ea > .
Register Select field—Specifies the system control register to be moved:
100 Floating-Point Control Register
010 Floating-Point Status Register
001 Floating-Point Instruction Address Register
5-82 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FMOVECR
Move Constant ROM
(MC6888X, M68040FPSP)
Operation: ROM Constant
→
FPn
Assembler
Syntax: FMOVECR.X # < ccc > ,FPn
FMOVECR
Attributes: Format = (Extended)
Description: Fetches an extended-precision constant from the floating- point coprocessor on-chip ROM, rounds the mantissa to the precision specified in the floating-point control register mode control byte, and stores it in the destination floating-point data register. The constant is specified by a predefined offset into the constant ROM. The values of the constants contained in the ROM are shown in the offset table at the end of this description.
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
Cleared
Cleared
Cleared
Cleared
Cleared
Cleared
Refer to inexact result in the appropriate user’s manual.
Cleared INEX1
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
1
13
1
0
12
1
1
11 10 9
COPROCESSOR
ID
1 1
8
0
DESTINATION
REGISTER
7
0
6
0
5
0
4
0
3
0
ROM OFFSET
2
0
1
0
0
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-83
Floating Point Instructions
FMOVECR
Move Constant ROM
(MC6888X, M68040FPSP)
FMOVECR
Instruction Fields:
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
Destination Register field—Specifies the destination floating- point data register.
ROM Offset field—Specifies the offset into the floating-point coprocessor on-chip constant ROM where the desired constant is located. The offsets for the available constants are as follows:
Offset Constant
$00
π
$0B Log
10
(2)
$0C e
$0D Log
2
(e)
$0E Log
10
(e)
$0F 0.0
$30 1n(2)
$31 1n(10)
$32 100
$33 10
1
$34 10
2
$35 10
4
$36 10
8
$37 10
16
$38 10
32
$39 10
64
$3A 10
128
$3B 10
256
$3C 10
512
$3D 10
1024
$3E 10
2048
$3F 10
4096
The on-chip ROM contains other constants useful only to the on- chip microcode routines. The values contained at offsets other than those defined above are reserved for the use of Motorola and may be different on various mask sets of the floating-point coprocessor. These undefined values yield the value 0.0 in the M68040FPSP.
5-84 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FMOVEM
Move Multiple Floating-Point
FMOVEM
Data Registers
(MC6888X, MC68040)
Operation: Register List
→
Destination
Source
→
Register List
Assembler
Syntax:
FMOVEM.X < list > , < ea >
FMOVEM.X Dn, < ea >
FMOVEM.X < ea > , < list > FMOVEM.X < ea > ,Dn
Attributes: Format = (Extended)
Description:Moves one or more extended-precision numbers to or from a list of floatingpoint data registers. No conversion or rounding is performed during this operation, and the floating-point status register is not affected by the instruction. For the MC68881, this instruction does not cause pending exceptions (other than protocol violations) to be reported. Furthermore, a write to the floating- point control register exception enable byte or the floating-point status register exception status byte connot generate a new exception, despite the value written.
Any combination of the eight floating-point data registers can be transferred, with the selected registers specified by a user- supplied mask. This mask is an 8-bit number, where each bit corresponds to one register; if a bit is set in the mask, that register is moved. The register select mask may be specified as a static value contained in the instruction or a dynamic value in the least significant eight bits of an integer data register (the remaining bits of the register are ignored).
FMOVEM allows three types of addressing modes: the control modes, the predecrement mode, or the postincrement mode. If the effective address is one of the control addressing modes, the registers are transferred between the processor and memory starting at the specified address and up through higher addresses. The order of the transfer is from FP0 – FP7.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-85
Floating Point Instructions
FMOVEM
Move Multiple Floating-Point
FMOVEM
Data Registers
(MC6888X, MC68040)
If the effective address is the predecrement mode, only a register- to-memory operation is allowed. The registers are stored starting at the address contained in the address register and down through lower addresses. Before each register is stored, the address register is decremented by 12 (the size of an extended-precision number in memory) and the floating-point data register is then stored at the resultant address.
When the operation is complete, the address register points to the image of the last floating- point data register stored. The order of the transfer is from FP7 – FP0.
If the effective address is the postincrement mode, only a memory- to-register operation is allowed. The registers are loaded starting at the specified address and up through higher addresses. After each register is stored, the address register is incremented by 12 (the size of an extended-precision number in memory). When the operation is complete, the address register points to the byte immediately following the image of the last floating-point data register loaded. The order of the transfer is the same as for the control addressing modes: FP0 – FP7.
Floating-Point Status Register: Not Affected. Note that the FMOVEM instruction provides the only mechanism for moving a floating- point data item between the floating-point unit and memory without performing any data conversions or affecting the condition code and exception status bits.
Instruction Format:
15
1
1
14
1
1
13
1 dr
12
1
MODE
11 10 9
COPROCESSOR
ID
0 0
8
0
0
7
0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE
REGISTER LIST
REGISTER
0
5-86 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FMOVEM
Move Multiple Floating-Point
FMOVEM
Data Registers
(MC6888X, MC68040)
Instruction Fields:
Effective Address field—(Memory-to-Register) Only control addressing modes or the postincrement addressing mode can be used as listed in the following table:
Addressing Mode Mode
Dn —
An
(An)
—
Register
—
—
010 reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
— —
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
—
001
—
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
Effective Address field—(Register-to-Memory) Only control alterable addressing modes or the predecrement addressing mode can be used as listed in the following table:
Addressing Mode Mode
Dn
An
—
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
010 reg. number:An
— —
100 reg. number:An
101 reg. number:An
110
110
110
110
Register
—
— reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
(xxx).L
# < data >
111
111
—
000
001
—
(d
(d
8
16
,PC)
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
—
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-87
Floating Point Instructions
FMOVEM
Move Multiple Floating-Point
FMOVEM
Data Registers
(MC6888X, MC68040) dr field—Specifies the direction of the transfer.
0 — Move the listed registers from memory to the floating-point unit.
1 — Move the listed registers from the floating-point unit to memory.
Mode field—Specifies the type of the register list and addressing mode.
00 — Static register list, predecrement addressing mode.
01 — Dynamic register list, predecrement addressing mode.
10 — Static register list, postincrement or control addressing mode.
11 — Dynamic register list, postincrement or control addressing mode.
Register List field:
Static list—contains the register select mask. If a register is to be moved, the corresponding bit in the mask is set as shown below; otherwise it is clear.
Dynamic list—contains the integer data register number, rrr, as listed in the following table:
List Type
Static, – (An)
Static, (An) + , or Control
Dynamic
FP7
FP0
0
FP6
FP1 r
FP5
Register List Format
FP4 FP3 FP2
FP2 r
FP3 r
FP4
0
FP5
0
FP1
FP6
0
FP0
FP7
0
The format of the dynamic list mask is the same as for the static list and is contained in the least significant eight bits of the specified main processor data register.
Programming Note: This instruction provides a very useful feature, dynamic register list specification, that can significantly enhance system performance. If the calling conventions used for procedure calls utilize the dynamic register list feature, the number of floating-point data registers saved and restored can be reduced.
To utilize the dynamic register specification feature of the FMOVEM instruction, both the calling and the called procedures must be written to communicate information about register usage. When one procedure calls another, a register mask must be passed to the called procedure to indicate which registers must not be altered upon return to the calling procedure. The called procedure then saves only those registers that are modified and are already in use. Several techniques can be used to utilize this mechanism, and an example follows.
5-88 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
MOVE.W
#ACTIVE,D7
BSR PROC_2
Floating Point Instructions
FMOVEM
Move Multiple Floating-Point
FMOVEM
Data Registers
(MC6888X, MC68040)
In this example, a convention is defined by which each called procedure is passed a word mask in D7 that identifies all floating-point registers in use by the calling procedure. Bits 15 – 8 identify the registers in the order FP0 – FP7, and bits 7 – 0 identify the registers in the order FP7 – FP0 (the two masks are required due to the different transfer order used by the predecrement and postincrement addressing modes). The code used by the calling procedure consists of simply moving the mask (which is generated at compile time) for the floating-point data registers currently in use into D7:
Calling procedure...
Load the list of FP registers that are in use.
The entry code for all other procedures computes two masks. The first mask identifies the registers in use by the calling procedure that are used by the called procedure (and therefore saved and restored by the called procedure). The second mask identifies the registers in use by the calling procedure that are used by the called procedure (and therefore not saved on entry). The appropriate registers are then stored along with the two masks:
Called procedure...
MOVE.W
D7,D6
AND.W
#WILL_USE,D7
Copy the list of active registers.
Generate the list of doubly-used registers.
FMOVEM D7, – (A7) Save those registers.
MOVE.W
D7, – (A7)
EOR.W
D7,D6 registers.
MOVE.W
D6, – (A7)
Save the register list.
Generate the list of not saved active
Save it for later use.
If the second procedure calls a third procedure, a register mask is passed to the third procedure that indicates which registers must not be altered by the third procedure.
This mask identifies any registers in the list from the first procedure that were not saved by the second procedure, plus any registers used by the second procedure that must not be altered by the third procedure.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-89
Floating Point Instructions
FMOVEM
Move Multiple Floating-Point
FMOVEM
Data Registers
(MC6888X, MC68040)
An example of the calculation of this mask is as follows:
Nested calling sequence...
MOVE.W
UNSAVED (A7),D7 Load the list of active registers not saved at entry.
OR.W
BSR
#WILL_USE,D7
PROC_3
Combine with those active at this time
Upon return from a procedure, the restoration of the necessary registers follows the same convention, and the register mask generated during the save operation on entry is used to restore the required floating-point data registers:
Return to caller...
ADDQ.L
MOVE.B
#2,A7
(A7) + ,D7 use byte).
FMOVEM (A7) + ,D7
*
*
*
RTS
Discard the list of registers not saved.
Get the saved register list (pop word,
Restore the registers.
Return to the calling routine.
5-90 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FMOVEM
Move Multiple Floating-Point
FMOVEM
Control Registers
(MC6888X, MC68040)
Operation: Register List
→
Destination
Source
→
Register List
Assembler
Syntax:
FMOVEM.L < list > , < ea >
FMOVEM.L < ea > , < list >
Attributes: Size = (Long)
Description: Moves one or more 32-bit values into or out of the specified system control registers. Any combination of the three system control registers may be specified. The registers are always moved in the same order, regardless of the addressing mode used; the floating-point control register is moved first, followed by the floating-point status register, and the floating-point instruction address register is moved last. If a register is not selected for the transfer, the relative order of the transfer of the other registers is the same. The first register is transferred between the floating-point unit and the specified address, with successive registers located up through higher addresses.
For the MC68881, this instruction does not cause pending exceptions (other than protocol violations) to be reported. Furthermore, a write to the floating-point control register exception enable byte or the floating-point status register exception status byte connot generate a new exception, despite the value written.
When more than one register is moved, the memory or memory- alterable addressing modes can be used as shown in the addressing mode tables. If the addressing mode is predecrement, the address register is first decremented by the total size of the register images to be moved (i.e., four times the number of registers), and then the registers are transferred starting at the resultant address. For the postincrement addressing mode, the selected registers are transferred to or from the specified address, and then the address register is incremented by the total size of the register images transferred.
If a single system control register is selected, the data register direct addressing mode may be used; if the only register selected is the floating-point instruction address register, then the address register direct addressing mode is allowed. Note that if a single register is selected, the opcode generated is the same as for the FMOVE single system control register instruction.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-91
Floating Point Instructions
FMOVEM
Move Multiple Floating-Point
FMOVEM
Control Registers
(MC6888X, MC68040)
Floating-Point Status Register: Changed only if thedestinationlist includes the floatingpoint status register in which case all bits are modified to reflect the value of the source register image.
Instruction Format:
15
1
1
14
1
0
13
1 dr
12
1
11 10 9
COPROCESSOR
ID
REGISTER
LIST
0
Instruction Fields:
8
0
0
7
0
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 0 0 0
Effective Address field—Determines the addressing mode for the operation.
Memory-to-Register—Only control addressing modes or the postincrement addressing mode can be used as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An**
(An)
001
010 reg. number:An reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
(d
16
(d
8
,PC)
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
111
111
*Only if a single floating-point instruction address register, floating-point status register, or floating-point control register is selected.
**Only if the floating-point instruction address register is the single register selected.
001
100
010
011
011
011
011
5-92 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FMOVEM
Move Multiple Floating-Point
FMOVEM
Control Registers
(MC6888X, MC68040)
Register-to-Memory—Only control alterable addressing modes or the predecrement addressing mode can be used as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An**
(An)
001
010 reg. number:An reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
(d
16
(d
8
,PC)
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
—
—
—
—
—
—
*Only if a single floating-point control register is selected.
**Only if the floating-point instruction address register is the single register selected.
001
—
—
—
—
—
— dr field—Specifies the direction of the transfer.
0 — Move the listed registers from memory to the floating-point unit.
1 — Move the listed registers from the floating-point unit to memory.
Register List field—Contains the register select mask. If a register is to be moved, the corresponding bit in the list is set; otherwise, it is clear. At least one register must be specified.
Bit Number
12
11
10
Register
Floating-Point Control Register
Floating-Point Status Register
Floating-Point Instruction
Address Register
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-93
Floating Point Instructions
FMUL
Operation:
Assembler
Syntax:
Floating-Point Multiply
(MC6888X, MC68040)
Source x FPn
→
FPn
FMUL. < fmt > < ea > ,FPn
FMUL.X FPm,FPn
*FrMUL < fmt > < ea > ,FPn
*FrMUL.X FPm,FPn where r is rounding precision, S or D
*Supported by MC68040 only
FMUL
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and multiplies that number by the number in the destination floating-point data register.
Stores the result in the destination floating-point data register.
FMUL will round the result to the precision selected in the floating-point control register.
FSMUL and FDMUL will round the result to single or double precision, respectively, regardless of the rounding precision selected in the floating-point control register.
Operation Table:
DESTINATION
In Range
+
+
–
–
+ 0.0
– 0.0
–
+ inf
– inf
In Range – +
Multiply
+ 0.0
– 0.0
SOURCE
1
Zero
– 0.0
+ 0.0
+ 0.0
– 0.0
– inf
+ inf
NAN
2
– +
– 0.0
+ 0.0
+ inf
– inf
– 0.0
+ 0.0
+ inf
– inf
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
Infinity
NAN
2
–
– inf
+ inf
– inf
+ inf
5-94 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FMUL
Floating-Point Multiply
(MC6888X, MC68040)
FMUL
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set for 0 x infinity; cleared otherwise.
Refer to exception processing in the appropriate user’s manual.
Refer to exception processing in the appropriate user’s manual.
Cleared
Refer to exception processing in the appropriate user’s manual.
If < fmt > is packed, refer to exception processing in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in exception processing in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
OPMODE
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-95
Floating Point Instructions
FMUL
Floating-Point Multiply
(MC6888X, MC68040)
FMUL
Instruction Fields:
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, specifies the location of the source operand location. Only data addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding will cause an unimplemented data type exception in the
MC68040 to allow emulation in software.
5-96 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FMUL
Floating-Point Multiply
(MC6888X, MC68040)
FMUL
Destination Register field—Specifies the destination floating- point data register.
Opmode field—Specifies the instruction and rounding precision.
0100011 FMUL Rounding precision specified by the floating-point control register.
1100011 FSMUL Single-precision rounding specified.
1100111 FDMUL Double-precision rounding specified.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-97
Floating Point Instructions
FNEG
Operation:
Assembler
Syntax:
Floating-Point Negate
(MC6888X, MC68040)
– (Source)
→
FPn
FNEG. < fmt > < ea > ,FPn
FNEG.X FPm,FPn
FNEG.X FPn
*FrNEG. < fmt > < ea > ,FPn
*FrNEG.X FPm,FPn
*FrNEG.X FPn where r is rounding precision, S or D
*Supported by MC68040 only
FNEG
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and inverts the sign of the mantissa. Stores the result in the destination floating-point data register.
FNEG will round the result to the precision selected in the floating-point control register.
FSNEG and FDNEG will round the result to single or double precision, respectively, regardless of the rounding precision selected in the floating-point control register.
Operation Table:
DESTINATION
Result
+ In Range – +
Negate – 0.0
SOURCE
Zero – +
+ 0.0 – inf
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
Infinity –
+ inf
5-98 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FNEG
Floating-Point Negate
(MC6888X, MC68040)
FNEG
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Cleared
If source is an extended-precision denormalized number, refer to exception processing in the appropriate user’s manual; cleared otherwise.
Cleared
Cleared
If < fmt > is packed, refer to exception processing in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in exception processing in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
OPMODE
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-99
Floating Point Instructions
FNEG
Floating-Point Negate
(MC6888X, MC68040)
FNEG
Instruction Fields:
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, specifies the location of the source operand. Only data addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding will cause an unimplemented data type exception to allow emulation in software.
5-100 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FNEG
Floating-Point Negate
(MC6888X, MC68040)
FNEG
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is taken from the specified floating-point data register and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
Opmode field—Specifies the instruction and rounding precision.
0011010 FNEG Rounding precision specified by the floating-point control register.
1011010 FSNEG Single-precision rounding specified.
1011110 FDNEG Double-precision rounding specified.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-101
Floating Point Instructions
FNOP
No Operation
(MC6888X, MC68040)
FNOP
Operation:
Assembler
Syntax:
Attributes:
None
FNOP
Unsized
Description: This instruction does not perform any explicit operation. However, it is useful to force synchronization of the floating- point unit with an integer unit or to force processing of pending exceptions. For most floating-point instructions, the integer unit is allowed to continue with the execution of the next instruction once the floating-point unit has any operands needed for an operation, thus supporting concurrent execution of floating-point and integer instructions. The FNOP instruction synchronizes the floating-point unit and the integer unit by causing the integer unit to wait until all previous floating-point instructions have completed. Execution of FNOP also forces any exceptions pending from the execution of a previous floating-point instruction to be processed as a preinstruction exception.
The MC68882 may not wait to begin execution of another floating- point instruction until it has completed execution of the current instruction. The FNOP instruction synchronizes the coprocessor and microprocessor unit by causing the microprocessor unit to wait until the current instruction (or both instructions) have completed.
The FNOP instruction also forces the processing of exceptions pending from the execution of previous instructions. This is also inherent in the way that the floating-point coprocessor utilizes the M68000 family coprocessor interface. Once the floating-point coprocessor has received the input operand for an arithmetic instruction, it always releases the main processor to execute the next instruction (regardless of whether or not concurrent execution is prevented for the instruction due to tracing) without reporting the exception during the execution of that instruction. Then, when the main processor attempts to initiate the execution of the next floating-point coprocessor instruction, a preinstruction exception may be reported to initiate exception processing for an exception that occurred during a previous instruction. By using the FNOP instruction, the user can force any pending exceptions to be processed without performing any other operations.
Floating-Point Status Register: Not Affected.
5-102 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
FNOP
No Operation
(MC6888X, MC68040)
Floating Point Instructions
FNOP
Instruction Format:
15
1
0
14
1
0
13
1
0
Instruction Fields:
12
1
0
11 10 9
COPROCESSOR ID
0 0 0
8
0
0
7
1
0
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
1
0
0
0
0
0
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
NOTE
FNOP uses the same opcode as the FBcc.W < label > instruction, with cc = F (nontrapping false) and < label > = + 2 (which results in a displacement of 0).
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-103
Floating Point Instructions
FREM
Operation:
Assembler
Syntax:
Attributes:
IEEE Remainder
(MC6888X, M68040FPSP)
IEEE Remainder of (FPn
÷
Source)
→
FPn
FREM. < fmt > < ea > ,FPn
FREM.X FPm,FPn
FREM
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates the modulo remainder of the number in the destination floating-point data register, using the source operand as the modulus. Stores the result in the destination floating-point data register and stores the sign and seven least significant bits of the quotient in the floating-point status register quotient byte (the quotient is the result of
FPn
÷
Source). The IEEE remainder function is defined as:
FPn – (Source x N) where N = INT (FPn
÷
Source) in the round-to-nearest mode.
The FREM function is not defined for a source operand equal to zero or for a destination operand equal to infinity. Note that this function is not the same as the FMOD instruction, which uses the round-to-zero mode and thus returns a remainder that is different from the remainder required by the IEEE Specification for Binary Floating-Point
Arithmetic.
Operation Table:
DESTINATION + In Range
In Range
Zero
+
–
+
–
IEEE Remainder
+ 0.0
– 0.0
Infinity +
–
NAN
2
– +
SOURCE
1
Zero#
NAN
2
NAN
2
NAN
2
– +
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
3. Returns the value of FPn before the operation. However, the result is processed by the normal instruction termination procedure to round it as required. Thus, an overflow and/or inexact result may occur if the rounding precision has been changed to a smaller size since the FPn value was loaded.
Infinity
FPn
2
+ 0.0
– 0.0
NAN†
2
–
5-104 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FREM
IEEE Remainder
(MC6888X, M68040FPSP)
FREM
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Loaded with the sign and least significant seven bits of the qotient (FPn
÷
Source). The sign of the quotient is the exclusive-OR of the sign bits of the source and destination operands.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is zero or the destination is infinity; cleared otherwise.
Cleared
Refer to underflow in the appropriate user’s manual.
Cleared
Cleared
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
1
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 1 0 1
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-105
Floating Point Instructions
FREM
IEEE Remainder
(MC6888X, M68040FPSP)
FREM
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register.
5-106 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FSCALE
Operation:
Scale Exponent
(MC6888X, M68040FPSP)
FPn x INT(2Source)
→
FPn
Assembler
Syntax:
FSCALE. < fmt > < ea > ,FPn
FSCALE.X FPm,FPn
FSCALE
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to an integer (if necessary) and adds that integer to the destination exponent. Stores the result in the destination floating-point data register. This function has the effect of multiplying the destination by 2
Source
, but is much faster than a multiply operation when the source is an integer value.
The floating-point coprocessor assumes that the scale factor is an integer value before the operation is executed. If not, the value is chopped (i.e., rounded using the roundto-zero mode) to an integer before it is added to the exponent. When the absolute value of the source operand is
≥
2
14
, an overflow or underflow always results.
Operation Table:
DESTINATION
In Range + –
Zero + –
Infinity + –
+ In Range – +
+ 0.0
Scale Exponent
– 0.0 + 0.0
+ inf – inf + inf
SOURCE
1
Zero
FPn
2
– +
– 0.0
– inf
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Returns the value of FPn before the operation. However, the result is processed by the normal instruction termination procedure to round it as required. Thus, an overflow and/or inexact result may occur if the rounding precision has been changed to a smaller size since the FPn value was loaded.
3. Sets the OPERR bit in the floating-point status register exception byte.
Infinity
NAN
3
NAN
3
NAN
3
–
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-107
Floating Point Instructions
FSCALE
Scale Exponent
(MC6888X, M68040FPSP)
FSCALE
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected
BSUN Cleared
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Refer to 1.6.5 Not-A-Numbers.
Set if the source operand is
±
infinity; cleared otherwise.
Refer to overflow in the appropriate user’s manual.
Refer to underflow in the appropriate user’s manual.
Cleared
Cleared
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
1
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 1 1 0
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
5-108 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FSCALE
Scale Exponent
(MC6888X, M68040FPSP)
FSCALE
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-109
Floating Point Instructions
FScc
Set According to Floating-Point Condition
FScc
(MC6888X, MC68040)
Operation: If (Condition True)
Then 1s
→
Destination
Else 0s
→
Destination
Assembler
Syntax:
Attributes:
FScc. < size > < ea >
Size = (Byte)
Description: If the specified floating-point condition is true, sets the byte integer operand at the destination to TRUE (all ones); otherwise, sets the byte to FALSE (all zeros). The conditional specifier cc may select any one of the 32 floating-point conditional tests as described in Table 3-23 Floating-Point Conditional Tests.
Floating-Point Status Register:
Condition Codes: Not affected.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Set if the NAN condition code is set and the condition selected is an IEEE nonaware test.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Accrued Exception Byte: The IOP bit is set if the BSUN bit is set in the exception byte. No other bit is affected.
5-110 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FScc
Set According to Floating-Point Condition
FScc
(MC6888X, MC68040)
Instruction Format:
15
1
0
14
1
0
13
1
0
12
1
0
11 10 9
COPROCESSOR
ID
0 0 0
8
0
0
7
0
0
6
1
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
CONDITIONAL PREDICATE
0
Instruction Fields:
Effective Address field—Specifies the addressing mode for the byte integer operand.
Only data alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
—
001
—
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
—
—
—
—
—
—
—
—
—
—
Conditional Predicate field—Specifies one of 32 conditional tests as defined in 3.6.2
Conditional Testing.
NOTE
When a BSUN exception occurs, a preinstruction exception is taken. If the exception handler returns without modifying the image of the program counter on the stack frame (to point to the instruction following the FScc), then it must clear the cause of the exception (by clearing the NAN bit or disabling the BSUN trap) or the exception occurs again immediately upon return to the routine that caused the exception.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-111
Floating Point Instructions
FSGLDIV
Operation:
Single-Precision Divide
(MC6888X, MC68040)
FPn
÷
Source
→
FPn
Assembler
Syntax:
FSGLDIV. < fmt > < ea > ,FPn
FSGLDIV.X
FPm,FPn
FSGLDIV
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and divides that number into the number in the destination floating-point data register. Stores the result in the destination floating-point data register, rounded to single precision (despite the current rounding precision). This function is undefined for 0
÷
0 and infinity
÷
infinity.
Both the source and destination operands are assumed to be representable in the single-precision format. If either operand requires more than 24 bits of mantissa to be accurately represented, the extraneous mantissa bits are trancated prior to the division, hence the accuracy of the result is not guaranteed. Furthermore, the result exponent may exceed the range of single precision, regardless of the rounding precision selected in the floating-point control register mode control byte. Refer to 3.6.1 Under-
flow, Round, Overflow for more information.
The accuracy of the result is not affected by the number of mantissa bits required to represent each input operand since the input operands just change to extended precision. The result mantissa is rounded to single precision, and the result exponent is rounded to extended precision, despite the rounding precision selected in the floatingpoint control register.
Operation Table:
DESTINATION +
In Range +
–
Zero +
–
+ 0.0
– 0.0
In Range – +
Divide
(Single Precision)
SOURCE
3,1
Zero – +
+ inf
– inf
2
2
–
+ inf
2
+ 0.0
– 0.0
Infinity
– 0.0
+ 0.0
NAN
3
+ 0.0
– 0.0
–
+ inf
– inf
– inf
+ inf
+ inf
– inf
– inf
+ inf
NAN
3
–
– 0.0
+ 0.0
– 0.0
+ 0.0
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the DZ bit in the floating-point status register exception byte.
3. Sets the OPERR bit in the floating-point status register exception byte.
5-112 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FSGLDIV
Single-Precision Divide
(MC6888X, MC68040)
FSGLDIV
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set for 0
÷
0 or infinity
÷
infinity.
Refer to overflow in the appropriate user’s manual.
Refer to underflow in the appropriate user’s manual.
Set if the source is zero and the destination is in range; cleared otherwise.
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to the appropriate user’s manual for inexact result on decimal input; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
1
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 1 0 0
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-113
Floating Point Instructions
FSGLDIV
Single-Precision Divide
(MC6888X, MC68040)
FSGLDIV
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register.
5-114 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FSGLMUL
Single-Precision Multiply
FSGLMUL
(MC6888X, MC68040)
Operation: Source x FPn
→
FPn
Assembler
Syntax:
FSGLMUL. < fmt > < ea > ,FPn
FSGLMUL.X FPm,FPn
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and multiplies that number by the number in the destination floating-point data register.
Stores the result in the destination floating-point data register, rounded to single precision (regardless of the current rounding precision).
Both the source and destination operands are assumed to be representable in the single-precision format. If either operand requires more than 24 bits of mantissa to be accurately represented, the extraneous mantissa bits are truncated prior to the multipliction; hence, the accuracy of the result is not guaranteed. Furthermore, the result exponent may exceed the range of single precision, regardless of the rounding precision selected in the floating-point control register mode control byte. Refer to 3.6.1
Underflow, Round, Overflow for more information.
Operation Table:
DESTINATION
In Range +
–
–
+ 0.0
– 0.0
SOURCE
1
Range Zero – + Infinity –
Multiply
(Single Precision)
+ 0.0
– 0.0
– 0.0
+ 0.0
+ inf
– inf
– inf
+ inf
– 0.0
+ 0.0
+ 0.0
– 0.0
– 0.0
+ 0.0
NAN
2
–
+ inf
– inf
– inf
+ inf
NAN
+ inf
– inf
– inf
+ inf
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
NOTE
The input operand mantissas truncate to single precision before the multiply operation. The result mantissa rounds to single precision despite the rounding precision selected in the floatingpoint control register.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-115
Floating Point Instructions
FSGLMUL
Single-Precision Multiply
FSGLMUL
(MC6888X, MC68040)
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN Cleared
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Refer to 1.6.5 Not-A-Numbers.
Set if one operand is zero and the other is infinity; cleared otherwise.
Refer to overflow in the appropriate user’s manual.
Refer to underflow in the appropriate user’s manual.
Cleared
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
1
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 1 1 1
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
5-116 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FSGLMUL
Single-Precision Multiply
FSGLMUL
(MC6888X, MC68040)
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-117
Floating Point Instructions
FSIN
Operation:
Assembler
Syntax:
Sine
(MC6888X, M68040FPSP)
Sine of Source
→
FPn
FSIN. < fmt > < ea > ,FPn
FSIN.X FPm,FPn
FSIN.X FPn
FSIN
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates the sine of that number. Stores the result in the destination floating-point data register. This function is not defined for source operands of
±
infinity. If the source operand is not in the range of [ – 2
π
... + 2
π
], the argument is reduced to within that range before the sine is calculated. However, large arguments may lose accuracy during reduction, and very large arguments (greater than approximately 10
20
) lose all accuracy. The result is in the range of [ – 1... + 1].
Operation Table:
DESTINATION
Result
+ In Range
Sine
– +
+ 0.0
SOURCE
1
Zero – +
– 0.0
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
Infinity
NAN
2
–
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte: Not affected.
5-118 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FSIN
Sine
(MC6888X, M68040FPSP)
FSIN
Exception Byte: BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is
±
infinity; cleared otherwise.
Cleared
Refer to underflow in the appropriate user’s manual.
Cleared
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 1 1 1 0
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-119
Floating Point Instructions
FSIN
Sine
(MC6888X, M68040FPSP)
FSIN
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, then the input operand is taken from the specified floating-point data register, and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
5-120 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FSINCOS
Simultaneous Sine and Cosine
FSINCOS
(MC6888X, M68040FPSP)
Operation: Sine of Source
→
FPs
Cosine of Source
→
FPc
Assembler
Syntax:
FSINCOS. < fmt > < ea > ,FPc,FPs
FSINCOS.X FPm,FPc,FPs
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates both the sine and the cosine of that number. Calculates both functions simultaneously; thus, this instruction is significantly faster than performing separate
FSIN and FCOS instructions. Loads the sine and cosine results into the destination floating-point data register. Sets the condition code bits according to the sine result. If
FPs and FPc are specified to be the same register, the cosine result is first loaded into the register and then is overwritten with the sine result. This function is not defined for source operands of
±
infinity.
If the source operand is not in the range of [ – 2
π
... + 2
π
], the argument is reduced to within that range before the sine and cosine are calculated. However, large arguments may lose accuracy during reduction, and very large arguments (greater than approximately 10
20
) lose all accuracy. The results are in the range of [ – 1... + 1].
Operation Table:
DESTINATION
FPs
FPc
+ In Range – +
Sine + 0.0
SOURCE
1
Zero – +
– 0.0
Cosine + 1.0
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
Infinity
NAN
2
NAN
2
–
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-121
Floating Point Instructions
FSINCOS
Simultaneous Sine and Cosine
FSINCOS
(MC6888X, M68040FPSP)
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing (for the sine result).
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is
±
infinity; cleared otherwise.
Cleared
Set if a sine underflow occurs, in which case the cosine result is 1. Cosine cannot underflow. Refer to underflow in the appropriate user’s manual.
Cleared
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER, FPs
7
0
Instruction Fields:
6
0
0
5
1
4 3 2
EFFECTIVE ADDRESS
1
MODE
1 0
0
REGISTER
DESTINATION
REGISTER FPc
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
5-122 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FSINCOS
Simultaneous Sine and Cosine
FSINCOS
(MC6888X, M68040FPSP)
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register, FPc field—Specifies the destination floating- point data register,
FPc. The cosine result is stored in this register.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-123
Floating Point Instructions
FSINCOS
Simultaneous Sine and Cosine
FSINCOS
(MC6888X, M68040FPSP)
Destination Register, FPs field—Specifies the destination floating- point data register, FPs.
The sine result is stored in this register. If FPc and FPs specify the same floating-point data register, the sine result is stored in the register, and the cosine result is discarded.
If R/M = 0 and the source register field is equal to either of the destination register fields, the input operand is taken from the specified floating-point data register, and the appropriate result is written into the same register.
5-124 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FSINH
Operation:
Assembler
Syntax:
Hyperbolic Sine
(MC6888X, M68040FPSP)
Hyperbolic Sine of Source
→
FPn
FSINH. < fmt > < ea > ,FPn
FSINH.X FPm,FPn
FSINH.X FPn
FSINH
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates the hyperbolic sine of that number. Stores the result in the destination floating-point data register.
Operation Table:
DESTINATION
Result
+ In Range
Hyperbolic Sine
– +
+ 0.0
SOURCE
Zero – +
– 0.0 + inf
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
Infinity –
– inf
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Refer to overflow in the appropriate user’s manual.
Refer to underflow in the appropriate user’s manual.
Cleared
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-125
Floating Point Instructions
FSINH
Hyperbolic Sine
(MC6888X, M68040FPSP)
FSINH
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 0 1 0
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
5-126 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FSINH
Hyperbolic Sine
(MC6888X, M68040FPSP)
FSINH
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, the input operand is taken from the specified floating-point data register, and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-127
Floating Point Instructions
FSQRT
Operation:
Assembler
Syntax:
Floating-Point Square Root
(MC6888X, MC68040)
Square Root of Source
→
FPn
FSQRT. < fmt > < ea > ,FPn
FSQRT.X FPm,FPn
FSQRT.X FPn
*FrSQRT. < fmt > < ea > ,FPn
*FrSQRT FPm,FPn
*FrSQRT FPn where r is rounding precision, S or D
*Supported by MC68040 only
FSQRT
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates the square root of that number. Stores the result in the destination floatingpoint data register. This function is not defined for negative operands.
FSQRT will round the result to the precision selected in the floating-point control register. FSFSQRT and FDFSQRT will round the result to single or double precision, respectively, regardless of the rounding precision selected in the floating-point control register.Operation Table:
DESTINATION
Result
+ x
In Range – +
NAN
2 + 0.0
SOURCE
1
Zero – +
– 0.0 + inf
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
Infinity –
NAN
2
5-128 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FSQRT
Floating-Point Square Root
(MC6888X, MC68040)
FSQRT
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source operand is not zero and is negative; cleared otherwise.
Cleared
Cleared
Cleared
Refer to exception processing in the appropriate user’s manual.
If < fmt > is packed, refer to exception processing in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in exception processing in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
OPMODE
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-129
Floating Point Instructions
FSQRT
Floating-Point Square Root
(MC6888X, MC68040)
FSQRT
Instruction Fields:
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, specifies the location of the source operand. Only data addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding will cause an unimplemented data type exception in the
MC68040 to allow emulation in software.
5-130 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FSQRT
Floating-Point Square Root
(MC6888X, MC68040)
FSQRT
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, the input operand is taken from the specified floating-point data register, and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
Opmode field—Specifies the instruction and rounding precision.
0000100 FSQRT Rounding precision specified by the floating-point control register.
1000001 FSSQRT Single-precision rounding specified.
1000101 FDSQRT Double-precision rounding specified.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-131
Floating Point Instructions
FSUB
Floating-Point Subtract
(MC6888X, MC68040)
FPn – Source
→
FPn
FSUB
Operation:
Assembler
Syntax: FSUB. < fmt > < ea > ,FPn
FSUB.X FPm,FPn
*FrSUB. < fmt > < ea > ,FPn
*FrSUB.X FPm,FPn where r is rounding precision, S or D
*Supported by MC68040 only
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and subtracts that number from the number in the destination floating-point data register.
Stores the result in the destination floating-point data register.
Operation Table:
DESTINATION + In Range – +
In Range
Zero +
–
+
–
Infinity +
–
Subtract
Subtract
+ inf
– inf
+ 0.0
2
+ 0.0
SOURCE
1
Zero
Subtract
+ inf
– inf
– +
– inf
+ 0.0
+ 0.0
2
– inf
NAN
2
– inf
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Returns + 0.0 in rounding modes RN, RZ, and RP; returns – 0.0 in RM.
3. Sets the OPERR bit in the floating-point status register exception byte.
Infinity –
+ inf
+ inf
– inf
NAN
2
5-132 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FSUB
Floating-Point Subtract
(MC6888X, MC68040)
FSUB
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if both the source and destination are like-signed infinities; cleared otherwise.
Refer to exception processing in the appropriate user’s manual.
Refer to exception processing in the appropriate user’s manual.
Cleared
Refer to exception processing in the appropriate user’s manual.
If < fmt > is packed, refer to exception processing in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
OPMODE
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-133
Floating Point Instructions
FSUB
Floating-Point Subtract
(MC6888X, MC68040)
FSUB
Instruction Fields:
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, specifies the location of the source operand. Only data addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding will cause an unimplemented data type exception in the
MC68040 to allow emulation in software.
5-134 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FSUB
Floating-Point Subtract
(MC6888X, MC68040)
FSUB
Destination Register field—Specifies the destination floating- point data register.
Opmode field—Specifies the instruction and rounding precision.
0101000 FSUB Rounding precision specified by the floating- point control register.
1101000 FSSUB Single-precision rounding specified.
1101100 FDSUB Double-precision rounding specified.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-135
Floating Point Instructions
FTAN
Operation:
Assembler
Syntax:
Tangent
(MC6888X/004SW)
Tangent of Source
→
FPn
FTAN. < fmt > < ea > ,FPn
FTAN.X FPm,FPn
FTAN.X FPn
FTAN
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates the tangent of that number. Stores the result in the destination floating-point data register. This function is not defined for source operands of
±
infinity. If the source operand is not in the range of [ –
π
/2... +
π
/2], the argument is reduced to within that range before the tangent is calculated. However, large arguments may lose accuracy during reduction, and very large arguments (greater than approximately 10
20
) lose all accuracy.
Operation Table:
DESTINATION
Result
+ In Range – +
Tangent + 0.0
SOURCE
1
Zero – +
– 0.0
NOTES:
1. If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
2. Sets the OPERR bit in the floating-point status register exception byte.
Infinity
NAN
2
–
5-136 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FTAN
Tangent
(MC6888X/004SW)
FTAN
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Set if the source is
±
infinity; cleared otherwise.
Refer to overflow in the appropriate user’s manual.
Refer to underflow in the appropriate user’s manual.
Cleared
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 1 1 1 1
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-137
Floating Point Instructions
FTAN
Tangent
(MC6888X/004SW)
FTAN
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, the input operand is taken from the specified floating-point data register, and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
5-138 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FTANH
Operation:
Assembler
Syntax:
Hyperbolic Tangent
(MC6888X, M68040FPSP)
Hyperbolic Tangent of Source
→
FPn
FTANH. < fmt > < ea > ,FPn
FTANH.X FPm,FPn
FTANH.X FPn
FTANH
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates the hyperbolic tangent of that number. Stores the result in the destination floating-point data register.
Operation Table:
DESTINATION
+ 0.0
SOURCE
Zero – + Infinity –
– 0.0 + 1.0
– 1.0 Result Hyperbolic Tangent
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Cleared
Refer to underflow in the appropriate user’s manual.
Cleared
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-139
Floating Point Instructions
FTANH
Hyperbolic Tangent
(MC6888X, M68040FPSP)
FTANH
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 1 0 0 1
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
5-140 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FTANH
Hyperbolic Tangent
(MC6888X, M68040FPSP)
FTANH
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, the input operand is taken from the specified floating-point data register, and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-141
Floating Point Instructions
FTENTOX
Operation:
10
x
(MC6888X, M68040FPSP)
10
Source →
FPn
Assembler
Syntax:
FTENTOX. < fmt > < ea > ,FPn
FTENTOX.X FPm,FPn
FTENTOX.X FPn
FTENTOX
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates 10 to the power of that number. Stores the result in the destination floatingpoint data register.
Operation Table:
DESTINATION
Result
+ In Range – +
10 x
SOURCE
Zero
+ 1.0
– +
+ inf
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
Infinity –
+ 0.0
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Refer to overflow in the appropriate user’s manual.
Refer to underflow in the appropriate user’s manual.
Cleared
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to the appropriate user’s manual inexact result on decimal input; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
5-142 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
FTENTOX
10
x
(MC6888X, M68040FPSP)
Floating Point Instructions
FTENTOX
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 0 0 1 0
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-143
Floating Point Instructions
FTENTOX
10
x
(MC6888X, M68040FPSP)
FTENTOX
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, the input operand is taken from the specified floating-point data register, and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
5-144 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FTRAPcc
Trap on Floating-Point Condition
FTRAPcc
(MC6888X, MC68040)
Operation:
Assembler
Syntax:
If Condition True
Then TRAP
FTRAPcc
FTRAPcc.W # < data >
FTRAPcc.L # < data >
Size = (Word, Long) Attributes:
Description: If the selected condition is true, the processor initiates exception processing.
A vector number is generated to reference the TRAPcc exception vector. The stacked program counter points to the next instruction. If the selected condition is not true, there is no operation performed and execution continues with the next instruction in sequence. The immediate data operand is placed in the word(s) following the conditional predicate word and is available for user definition for use within the trap handler.
The conditional specifier cc selects one of the 32 conditional tests defined in 3.6.2
Conditional Testing.
Floating-Point Status Register:
Condition Codes: Not affected.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Set if the NAN condition code is set and the condition selected is an IEEE nonaware test.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Not Affected.
Accrued Exception Byte: The IOP bit is set if the BSUN bit is set in the exception byte; no other bit is affected.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-145
Floating Point Instructions
FTRAPcc
Trap on Floating-Point Condition
FTRAPcc
(MC6888X, MC68040)
Instruction Format:
15
1
0
14
1
0
13
1
0
12
1
11 10 9
COPROCESSOR
ID
8
0
7
0
6
1
5
1
4
1
3
1
2 1
MODE
0 0 0 0 0 0 0 CONDITIONAL PREDICATE
16-BIT OPERAND OR MOST SIGNIFICANT WORD OF 32-BIT OPERAND (IFNEEDED)
LEAST SIGNIFICANT WORD OR 32-BIT OPERAND (IF NEEDED)
0
Instruction Fields:
Mode field—Specifies the form of the instruction.
010 — The instruction is followed by a word operand.
011 — The instruction is followed by a long-word operand.
100 — The instruction has no operand.
Conditional Predicate field—Specifies one of 32 conditional tests as described in 3.6.2
Conditional Testing.
Operand field—Contains an optional word or long-word operand that is user defined.
NOTE
When a BSUN exception occurs, a preinstruction exception is taken by the main processor. If the exception handler returns without modifying the image of the program counter on the stack frame (to point to the instruction following the FTRAPcc), it must clear the cause of the exception (by clearing the NAN bit or disabling the BSUN trap), or the exception occurs again immediately upon return to the routine that caused the exception.
5-146 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FTST
Operation:
Assembler
Syntax:
Attributes:
Test Floating-Point Operand
(MC6888X, MC68040)
Condition Codes for Operand
→
FPCC
FTST. < fmt > < ea >
FTST.X FPm
FTST
Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and sets the condition code bits according to the data type of the result.
Operation Table: The contents of this table differfromtheother operation tables. A letter in an entry of this table indicates that the designated condition code bit is always set by the FTST operation. All unspecified condition code bits are cleared during the operation.
DESTINATION
Result
+ In Range – + none N Z
SOURCE
Zero – +
NZ I
NOTE: If the source operand is a NAN, set the NAN condition code bit. If the source operand is an SNAN, set the SNAN bit in the floating-point status register exception byte
Infinity –
NI
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Cleared
Cleared
Cleared
Cleared
If < fmt > is packed, refer to exception processing in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in exception processing in the appropriate user’s manual.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-147
Floating Point Instructions
FTST
Test Floating-Point Operand
(MC6888X, MC68040)
Instruction Format:
FTST
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
1
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 1 0 1 0
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, specifies the location of the source operand. Only data addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
5-148 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Floating Point Instructions
FTST
Test Floating-Point Operand
(MC6888X, MC68040)
FTST
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)*
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
*This encoding will cause an unimplemented data type exception in the
MC68040 to allow emulation in software.
Destination Register field—Since the floating-point unit uses a common command word format for all of the arithmetic instructions (including FTST), this field is treated in the same manner for FTST as for the other arithmetic instructions, even though the destination register is not modified. This field should be set to zero to maintain compatibility with future devices; however, the floating-point unit does not signal an illegal instruction trap if it is not zero.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-149
Floating Point Instructions
FTWOTOX
Operation:
2
x
(MC6888X, M68040FPSP)
2
Source →
FPn
Assembler
Syntax:
FTWOTOX. < fmt > < ea > ,FPn
FTWOTOX.X FPm,FPn
FTWOTOX.X FPn
FTWOTOX
Attributes: Format = (Byte, Word, Long, Single, Double, Extended, Packed)
Description: Converts the source operand to extended precision (if necessary) and calculates two to the power of that number. Stores the result in the destination floatingpoint data register.
Operation Table:
DESTINATION
Result
+ In Range – +
2 x
SOURCE
Zero
+ 1.0
– +
+ inf
NOTE: If the source operand is a NAN, refer to 1.6.5 Not-A-Numbers for more information.
Infinity –
+ 0.0
Floating-Point Status Register:
Condition Codes: Affected as described in 3.6.2 Conditional Testing.
Quotient Byte:
Exception Byte:
Not affected.
BSUN
SNAN
OPERR
OVFL
UNFL
DZ
INEX2
INEX1
Cleared
Refer to 1.6.5 Not-A-Numbers.
Cleared
Refer to overflow in the appropriate user’s manual.
Refer to underflow in the appropriate user’s manual.
Cleared
Refer to inexact result in the appropriate user’s manual.
If < fmt > is packed, refer to inexact result on decimal input in the appropriate user’s manual; cleared otherwise.
Accrued Exception Byte: Affected as described in IEEE exception and trap compatibility in the appropriate user’s manual.
5-150 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
FTWOTOX
2
x
(MC6888X, M68040FPSP)
Floating Point Instructions
FTWOTOX
Instruction Format:
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9
COPROCESSOR
ID
SOURCE
SPECIFIER
8
0
DESTINATION
REGISTER
7
0
Instruction Fields:
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 0 0 0 1
Coprocessor ID field—Specifies which coprocessor in the system is to execute this instruction. Motorola assemblers default to ID = 1 for the floating-point coprocessor.
Effective Address field—Determines the addressing mode for external operands.
If R/M = 0, this field is unused and should be all zeros.
If R/M = 1, this field is encoded with an M68000 family addressing mode as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn],od)
([bd,An],Xn,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
*Only if < fmt > is byte, word, long, or single.
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn],od)
([bd,PC],Xn,od)
111
111
111
111
111
010
011
011
011
011
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 5-151
Floating Point Instructions
FTWOTOX
2
x
(MC6888X, M68040FPSP)
FTWOTOX
R/M field—Specifies the source operand address mode.
0 — The operation is register to register.
1 — The operation is < ea > to register.
Source Specifier field—Specifies the source register or data format.
If R/M = 0, specifies the source floating-point data register.
If R/M = 1, specifies the source data format:
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
Destination Register field—Specifies the destination floating- point data register. If R/
M = 0 and the source and destination fields are equal, the input operand is taken from the specified floating-point data register, and the result is written into the same register. If the single register syntax is used, Motorola assemblers set the source and destination fields to the same value.
5-152 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
SECTION 6
SUPERVISOR (PRIVILEGED) INSTRUCTIONS
This section contains information about the supervisor privileged instructions for the
M68000 family. Each instruction is described in detail, and the instruction descriptions are arranged in alphabetical order by instruction mnemonic.
Any differences within the M68000 family of instructions are identified in the instruction. If an instruction only applies to a certain processor or processors, the processor(s) that the instruction pertains to is identified under the title of the instruction. For example:
Invalidate Cache Lines
(MC68040)
All references to the MC68000, MC68020, and MC68030 include references to the corresponding embedded controllers, MC68EC000, MC68EC020, and MC68EC030. All references to the MC68040 include the MC68LC040 and MC68EC040. This applies throughout this section unless otherwise specified.
If the instruction applies to all the M68000 family but a processor or processors may use a different instruction field, instruction format, etc., the differences will be identified within the paragraph. For example:
MC68020, MC68030 and MC68040 only
(bd,An,Xn)* 110 reg. number: An
*Can be used with CPU32 processo
(bd,PC,Xn)* — —
The following instructions are listed separately for each processor due to the many differences involved within the instruction:
PFLUSH
PMOVE
PTEST
Flush ATC Entries
Move PMMU Register
Test Logical Address
Appendix A Processor Instruction Summary provides a listing of all processors and the instructions that apply to them for quick reference.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-1
Supervisor (Privileged) Instructions
ANDI to SR
AND Immediate to the Status Register
(M68000 Family)
ANDI to SR
Operation: If Supervisor State
Then Source L SR
→
SR
ELSE TRAP
Assembler
Syntax:
Attributes:
ANDI # < data > ,SR size = (word)
Description: Performs an AND operation of the immediate operand with the contents of the status register and stores the result in the status register. All implemented bits of the status register are affected.
Condition Codes:
X
∗
N
∗
Z
∗
V
∗
C
∗
X—Cleared if bit 4 of immediate operand is zero; unchanged otherwise.
N—Cleared if bit 3 of immediate operand is zero; unchanged otherwise.
Z—Cleared if bit 2 of immediate operand is zero; unchanged otherwise.
V—Cleared if bit 1 of immediate operand is zero; unchanged otherwise.
C—Cleared if bit 0 of immediate operand is zero; unchanged otherwise.
Instruction Format:
5
0
14
0
13
0
12
0
11
0
10
0
9
1
8
0
7
0
16-BIT WORD DATA
6
1
5
1
4
1
3
1
2
1
1
0
0
0
6-2 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
CINV
Invalidate Cache Lines
(MC68040, MC68LC040)
CINV
Operation: If Supervisor State
Then Invalidate Selected Cache Lines
ELSE TRAP
Assembler
Syntax: CINVL < caches > ,(An)
CINVP < caches > ,(An)
CINVA < caches >
Where < caches > specifies the instruction cache, data cache, both caches, or neither cache.
Unsized Attributes:
Description: Invalidates selected cache lines. The data cache, instruction cache, both caches, or neither cache can be specified. Any dirty data in data cache lines that invalidate are lost; the CPUSH instruction must be used when dirty data may be contained in the data cache.
Specific cache lines can be selected in three ways:
1. CINVL invalidates the cache line (if any) matching the physical address in the specified address register.
2. CINVP invalidates the cache lines (if any) matching the physical memory page in the specified address register. For example, if 4K-byte page sizes are selected and An contains $12345000, all cache lines matching page $12345000 invalidate.
3. CINVA invalidates all cache entries.
Condition Codes:
Not affected.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-3
Supervisor (Privileged) Instructions
CINV
Invalidate Cache Lines
(MC68040, MC68LC040)
Instruction Format:
CINV
15
1
14
1
13
1
12
1
11
0
10
1
9
0
Instruction Fields:
Cache field—Specifies the Cache.
00—No Operation
01—Data Cache
10—Instruction Cache
11—Data and Instruction Caches
8
0
7
CACHE
6 5
0
4
SCOPE
3 2 1
REGISTER
0
Scope field—Specifies the Scope of the Operation.
00—Illegal (causes illegal instruction trap)
01—Line
10—Page
11—All
Register field—Specifies the address register for line and page operations. For line operations, the low-order bits 3–0 of the address are don‘t cares. Bits 11–0 or 12–
0 of the address are don‘t care for 4K-byte or 8K-byte page operations, respectively.
6-4 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions cpRESTORE
Coprocessor
Restore Functions
(MC68020, MC68030) cpRESTORE
Operation: If Supervisor State
Then Restore Internal State of Coprocessor
ELSE TRAP
Assembler
Syntax:
Attributes: cpRESTORE < ea >
Unsized
Description: Restores the internal state of a coprocessor usually after it has been saved by a preceding cpSAVE instruction.
Condition Codes:
Not affected.
Instruction Format:
15
1
14
1
13
1
12
1
11 10 9
COPROCESSOR
ID
8
1
7
0
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-5
Supervisor (Privileged) Instructions cpRESTORE
Coprocessor
Restore Functions
(MC68020, MC68030) cpRESTORE
Instruction Fields:
Coprocessor ID field—Identifies the coprocessor that is to be restored. Coprocessor ID of 000 results in an F-line exception for the MC68030.
Effective Address field—Specifies the location where the internal state of the coprocessor is located. Only postincrement or control addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn —
An
(An)
—
Register
—
—
010 reg. number:An
(An) +
— (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn], od)
([bd,An],Xn,od)
011 reg. number:An
— —
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg.number:An
Addressing Mode Mode Register
(xxx).W 111 000
(xxx).L
# < data >
111
111
001
100
(d
16
(d
8
,PC) 111
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn], od)
([bd,PC],Xn, od
111
111
111
111
010
011
011
011
011
NOTE
If the format word returned by the coprocessor indicates “come again”, pending interrupts are not serviced.
6-6 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions cpSAVE
Coprocessor Save Function
(MC68020, MC68030) cpSAVE
Operation: If Supervisor State
Then Save Internal State of Coprocessor
ELSE TRAP
Assembler
Syntax:
Attributes: cpSAVE < ea >
Unsized
Description: Saves the internal state of a coprocessor in a format that can be restored by a cpRESTORE instruction.
Condition Codes:
Not affected.
Instruction Format:
15
1
14
1
13
1
12
1
11 10 9
COPROCESSOR
ID
8
1
7
0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields:
Coprocessor ID field—Identifies the coprocessor for this operation. Coprocessor ID of
000 results in an F-line exception for the MC68030.
Effective Address field—Specifies the location where the internal state of the coprocessor is to be saved. Only predecrement or control alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn —
An
(An)
—
Register
—
—
010 reg. number:An
(An) +
— (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn], od)
([bd,An],Xn, od)
— —
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W 111 000
(xxx).L 111
# < data > —
001
—
(d
16
,PC) —
(d
8
,PC,Xn) —
(bd,PC,Xn) —
([bd,PC,Xn],od) —
([bd,PC],Xn, od) —
—
—
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-7
Supervisor (Privileged) Instructions
CPUSH
Push and Invalidate Cache Lines
(MC68040, MC68LC040)
CPUSH
Operation:
Assembler
Syntax:
If Supervisor State
Then If Data Cache
Then Push Selected Dirty Data Cache Lines
Invalidate Selected Cache Lines
ELSE TRAP
CPUSHL < caches > ,(An)
CPUSHP < caches > ,(An)
CPUSHA < caches >
Where < caches > specifies the instruction cache, data cache, both caches, or neither cache.
Unsized Attributes:
Description: Pushes and then invalidates selected cache lines. The DATA cache, instruction cache, both caches, or neither cache can be specified. When the data cache is specified, the selected data cache lines are first pushed to memory (if they contain dirty DATA) and then invalidated. Selected instruction cache lines are invalidated.
Specific cache lines can be selected in three ways:
1. CPUSHL pushes and invalidates the cache line (if any) matching the physical address in the specified address register.
2. CPUSHP pushes and invalidates the cache lines (if any) matching the physical memory page in the specified address register. For example, if 4K-byte page sizes are selected and An contains $12345000, all cache lines matching page
$12345000 are selected.
3. CPUSHA pushes and invalidates all cache entries.
Condition Codes:
Not affected.
Instruction Format:
15
1
14
1
13
1
12
1
11
0
10
1
9
0
8
0
7
CACHE
6 5
1
4
SCOPE
3 2 1
REGISTER
0
6-8 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
CPUSH
Push and Invalidate Cache Lines
(MC68040, MC68LC040)
CPUSH
Instruction Fields:
Cache field—Specifies the Cache.
00—No Operation
01—Data Cache
10—Instruction Cache
11—Data and Instruction Caches
Scope field—Specifies the Scope of the Operation.
00—Illegal (causes illegal instruction trap)
01—Line
10—Page
11—All
Register field—Specifies the address register for line and page operations. For line operations, the low-order bits 3–0 of the address are don‘t care. Bits 11–0 or 12–
0 of the address are don‘t care for 4K-byte or 8K-byte page operations, respectively.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-9
Supervisor (Privileged) Instructions
EORI EORI to SR
Exclusive-OR Immediate to the Status Register
to SR
(M68000 Family)
Operation: If Supervisor State
Then Source
⊕
SR
→
SR
ELSE TRAP
Assembler
Syntax:
Attributes:
EORI # < data > ,SR
Size = (Word)
Description: Performs an exclusive-OR operation on the contents of the status register using the immediate operand and stores the result in the status register. All implemented bits of the status register are affected.
Condition Codes:
X
∗
N
∗
Z
∗
V
∗
C
∗
X—Changed if bit 4 of immediate operand is one; unchanged otherwise.
N—Changed if bit 3 of immediate operand is one; unchanged otherwise.
Z—Changed if bit 2 of immediate operand is one; unchanged otherwise.
V—Changed if bit 1 of immediate operand is one; unchanged otherwise.
C—Changed if bit 0 of immediate operand is one; unchanged otherwise.
Instruction Format:
15
0
14
0
13
0
12
0
11
1
10
0
9
1
8
0
7
0
16-BIT WORD DATA
6
1
5
1
4
1
3
1
2
1
1
0
0
0
6-10 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
FRESTORE
Restore Internal
Floating-Point State
(MC68881, MC68882, MC68040 only)
FRESTORE
Operation: If in Supervisor State
Then FPU State Frame
→
Internal State
ELSE TRAP
Assembler
Syntax:
Attributes:
FRESTORE < ea >
Unsized
Description: Aborts the execution of any floating-point operation in progress and loads a new floating-point unit internal state from the state frame located at the effective address. The first word at the specified address is the format word of the state frame.
It specifies the size of the frame and the revision number of the floating-point unit that created it. A format word is invalid if it does not recognize the size of the frame or the revision number does not match the revision of the floating-point unit. If the format word is invalid, FRESTORE aborts, and a format exception is generated. If the format word is valid, the appropriate state frame is loaded, starting at the specified location and proceeding through higher addresses.
The FRESTORE instruction does not normally affect the programmer’s model registers of the floating-point coprocessor, except for the NULL state size, as described below.
It is only for restoring the user invisible portion of the machine. The FRESTORE instruction is used with the FMOVEM instruction to perform a full context restoration of the floating-point unit, including the floating- point data registers and system control registers. To accomplish a complete restoration, the FMOVEM instructions are first executed to load the programmer’s model, followed by the FRESTORE instruction to load the internal state and continue any previously suspended operation.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-11
Supervisor (Privileged) Instructions
FRESTORE
Restore Internal
Floating-Point State
(MC68881, MC68882, MC68040 only)
FRESTORE
The current implementation supports the following four state frames:
NULL: This state frame is 4 bytes long, with a format word of $0000. An FRE-
STORE operation with this size state frame is equivalent to a hardware reset of the floating-point unit. The programmer’s model is set to the reset state, with nonsignaling NANs in the floating-point data registers and zeros in the floating-point control register, floating-point status register, and floatingpoint instruction address register. (Thus, it is unnecessary to load the programmer’s model before this operation.)
IDLE: This state frame is 4 bytes long in the MC68040, 28 ($1C) bytes long in the
MC68881, and 60 ($3C) bytes long in the MC68882. An FRESTORE operation with this state frame causes the floating-point unit to be restored to the idle state, waiting for the initiation of the next instruction, with no exceptions pending. The programmer’s model is not affected by loading this type of state frame.
UNIMP: This state frame is generated only by the MC68040. It is 48 ($30) bytes long.
An FSAVE that generates this size frame indicates either an unimplemented floating-point instruction or only an E1 exception is pending. This frame is never generated when an unsupported data type exception is pending or an
E3 exception is pending. If both E1 and E3 exceptions are pending, a BUSY frame is generated.
BUSY: This state frame is 96 ($60) bytes long in the MC68040, 184 ($B8) bytes long in the MC68881, and 216 ($D8) bytes long in the MC68882. An FRESTORE operation with this size state frame causes the floating-point unit to be restored to the busy state, executing the instructions that were suspended by a previous FSAVE operation. The programmer’s model is not affected by loading this type of state frame; however, the completion of the suspended instructions after the restore is executed may modify the programmer’s model.
Floating-Point Status Register: Cleared if the state size is NULL; otherwise, not affected.
6-12 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
FRESTORE
Restore Internal
Floating-Point State
(MC68881, MC68882, MC68040 only)
FRESTORE
Instruction Format:
15
1
14
1
13
1
12
1
11 10 9
COPROCESSOR
ID
8
1
7
0
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Field:
Effective Address field—Determines the addressing mode for the state frame. Only postincrement or control addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn —
An
(An)
—
Register
—
—
010 reg. number:An
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn], od)
([bd,An],Xn, od)
011 reg. number:An
— —
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
—
001
—
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn], od)
([bd,PC],Xn, od)
111
111
111
111
111
010
011
011
011
011
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-13
Supervisor (Privileged) Instructions
FSAVE
Save Internal Floating-Point State
(MC68881, MC68882, MC68040 only)
FSAVE
Operation: If in Supervisor State
Then FPU Internal State
→
State Frame
ELSE TRAP
Assembler
Syntax:
Attributes:
FSAVE < ea >
Unsized
Description: FSAVE allows the completion of any floating-point operation in progress for the MC68040. It saves the internal state of the floating-point unit in a state frame located at the effective address. After the save operation, the floating-point unit is in the idle state, waiting for the execution of the next instruction. The first word written to the state frame is the format word specifying the size of the frame and the revision number of the floating-point unit.
Any floating-point operations in progress when an FSAVE instruction is encountered can be completed before the FSAVE executes, saving an IDLE state frame. Execution of instructions already in the floating-point unit pipeline continues until completion of all instructions in the pipeline or generation of an exception by one of the instructions. An
IDLE state frame is created by the FSAVE if no exceptions occurred; otherwise, a
BUSY or an UNIMP stack frame is created.
FSAVE suspends the execution of any operation in progress and saves the internal state in a state frame located at the effective address for the MC68881/MC68882. After the save operation, the floating-point coprocessor is in the idle state, waiting for the execution of the next instruction. The first word written to the state frame is the format word, specifying the size of the frame and the revision number of the floating-point coprocessor. The microprocessor unit initiates the FSAVE instruction by reading the floating-point coprocessor save CIR. The floating-point coprocessor save CIR is encoded with a format word that indicates the appropriate action to be taken by the main processor. The current implementation of the floating-point coprocessor always returns one of five responses in the save CIR:
Value
$0018
$0118
$0218
$XX18
$XXB4
Definition
Save NULL state frame
Not ready, come again
Illegal, take format exception
Save IDLE state frame
Save BUSY state frame
NOTE: XX is the floating-point coprocessor version number.
6-14 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
FSAVE
Save Internal Floating-Point State
(MC68881, MC68882, MC68040 only)
FSAVE
The not ready format word indicates that the floating-point coprocessor is not prepared to perform a state save and that the microprocessor unit should process interrupts, if necessary, and re-read the save CIR. The floating-point coprocessor uses this format word to cause the main processor to wait while an internal operation completes, if possible, to allow an IDLE frame rather than a BUSY frame to be saved. The illegal format word aborts an FSAVE instruction that is attempted while the floating-point coprocessor executes a previous FSAVE instruction. All other format words cause the microprocessor unit to save the indicated state frame at the specified address. For state frame details see state frames in the appropriate user’s manual.
The following state frames apply to both the MC68040 and the MC68881/MC68882.
NULL: This state frame is 4 bytes long. An FSAVE instruction that generates this state frame indicates that the floating-point unit state has not been modified since the last hardware reset or FRESTORE instruction with a NULL state frame. This indicates that the programmer’s model is in the reset state, with nonsignaling NANs in the floating-point data registers and zeros in the floating- point control register, floating-point status register, and floating-point instruction address register. (Thus, it is not necessary to save the programmer’s model.)
IDLE: This state frame is 4 bytes long in the MC68040, 28 ($1C) bytes long in the
MC68881, and 60 ($3C) bytes long in the MC68882. An FSAVE instruction that generates this state frame indicates that the floating-point unit finished in an idle condition and is without any pending exceptions waiting for the initiation of the next instruction.
UNIMP: This state frame is generated only by the MC68040. It is 48 ($30) bytes long.
An FSAVE that generates this size frame indicates either an unimplemented floating-point instruction or that only an E1 exception is pending. This frame is never generated when an unsupported data type exception or an E3 exception is pending. If both E1 and E3 exceptions are pending, a BUSY frame is generated.
BUSY: This state frame is 96 ($60) bytes long in the MC68040, 184 ($B8) bytes long in the MC68881, and 216 ($D8) bytes long in the MC68882. An FSAVE instruction that generates this size state frame indicates that the floatingpoint unit encountered an exception while attempting to complete the execution of the previous floating-point instructions.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-15
Supervisor (Privileged) Instructions
FSAVE
Save Internal Floating-Point State
(MC68881, MC68882, MC68040 only)
FSAVE
The FSAVE does not save the programmer’s model registers of the floating-point unit; it saves only the user invisible portion of the machine. The FSAVE instruction may be used with the FMOVEM instruction to perform a full context save of the floating-point unit that includes the floating-point data registers and system control registers. To accomplish a complete context save, first execute an FSAVE instruction to suspend the current operation and save the internal state, then execute the appropriate
FMOVEM instructions to store the programmer’s model.
Floating-Point Status Register: Not affected.
Instruction Format:
15
1
14
1
13
1
12
1
11 10 9
COPROCESSOR
ID
8
1
7
0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Field:
Effective Address field—Determines the addressing mode for the state frame. Only predecrement or control alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn —
An
(An)
—
Register
—
—
010 reg. number:An
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn] ,od)
([bd,An],Xn ,od)
— —
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
—
001
—
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
—
—
—
—
—
—
—
—
—
—
6-16 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
MOVE MOVE from SR
Move from the Status Register
from SR
(MC68EC000, MC68010, MC68020,
MC68030, MC68040, CPU32)
Operation: If Supervisor State
Then SR
→
Destination
Else TRAP
Assembler
Syntax:
Attributes:
MOVE SR, < ea >
Size = (Word)
Description: Moves the data in the status register to the destination location. The destination is word length. Unimplemented bits are read as zeros.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11
0
10
0
9
0
8
0
7
1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-17
Supervisor (Privileged) Instructions
MOVE MOVE from SR
Move from the Status Register
from SR
(MC68EC000, MC68010, MC68020,
MC68030, MC68040, CPU32)
Instruction Field:
Effective Address field—Specifies the destination location. Only data alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
Register reg. number:Dn
—
(An)
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
010 reg. number:An
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
Addressing Mode Mode Register
(xxx).W
(xxx).L
# < data >
111
111
—
000
001
—
(d
(d
8
16
,PC)
,PC,Xn)
—
—
—
—
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn] ,od)
110 reg. number:An
110 reg. number:An
([bd,An],Xn ,od) 110 reg. number:An
*Available for the CPU32.
(bd,PC,Xn)*
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
NOTE
Use the MOVE from CCR instruction to access only the condition codes.
—
—
—
—
—
—
6-18 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
MOVE to SR
Move to the Status Register
(M68000 Family)
MOVE to SR
Operation: If Supervisor State
Then Source
→
SR
Else TRAP
Assembler
Syntax:
Attributes:
MOVE < ea > ,SR
Size = (Word)
Description: Moves the data in the source operand to the status register. The source operand is a word, and all implemented bits of the status register are affected.
Condition Codes:
Set according to the source operand.
Instruction Format:
15
0
14
1
13
0
12
0
11
0
10
1
9
1
8
0
7
1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-19
Supervisor (Privileged) Instructions
MOVE to SR
Move to the Status Register
(M68000 Family)
MOVE to SR
Instruction Field:
Effective Address field—Specifies the location of the source operand. Only data addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn
An
000
—
Register reg. number:Dn
—
(An)
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
010 reg. number:An
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
Addressing Mode Mode Register
(xxx).W
(xxx).L
# < data >
111
111
111
000
001
100
(d
(d
8
16
,PC)
,PC,Xn)
111
111
010
011
MC68020, MC68030, and MC68040 only
(bd,An,Xn)*
([bd,An,Xn] ,od)
110 reg. number:An
110 reg. number:An
([bd,An],Xn ,od) 110 reg. number:An
*Available for the CPU32.
(bd,PC,Xn)*
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
111
111
111
011
011
011
6-20 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
MOVE
USP
Move User Stack Pointer
(M68000 Family)
MOVE
USP
Operation:
Assembler
Syntax:
Attributes:
If Supervisor State
Then USP
→
An or An
→
USP
Else TRAP
MOVE USP,An
MOVE An,USP
Size = (Long)
Description: Moves the contents of the user stack pointer to or from the specified address register.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
0
6
1
5
1
4
0
Instruction Fields: dr field—Specifies the direction of transfer.
0—Transfer the address register to the user stack pointer.
1—Transfer the user stack pointer to the address register.
Register field—Specifies the address register for the operation.
3 dr
2 1
REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-21
Supervisor (Privileged) Instructions
MOVEC
Move Control Register
(MC68010, MC68020, MC68030, MC68040, CPU32)
MOVEC
Operation:
Assembler
Syntax:
Attributes:
If Supervisor State
Then Rc
→
Rn or Rn
→
Rc
Else TRAP
MOVEC Rc,Rn
MOVEC Rn,Rc
Size = (Long)
Description: Moves the contents of the specified control register (Rc) to the specified general register (Rn) or copies the contents of the specified general register to the specified control register. This is always a 32-bit transfer, even though the control register may be implemented with fewer bits. Unimplemented bits are read as zeros.
Condition Codes:
Not affected.
Instruction Format:
15
0
A/D
14
1
13
0
REGISTER
12
0
11
1
10
1
9
1
8
0
7
0
6
1
5
1
CONTROL REGISTER
4
1
Instruction Fields: dr field—Specifies the direction of the transfer.
0—Control register to general register.
1—General register to control register.
A/D field—Specifies the type of general register.
0—Data Register
1—Address Rregister
3
1
2
0
1
1
0 dr
6-22 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
MOVEC
Move Control Register
(MC68010, MC68020, MC68030, MC68040, CPU32)
MOVEC
Register field—Specifies the register number.
Control Register field—Specifies the control register.
Hex
1
Control Register
MC68010/MC68020/MC68030/MC68040/CPU32
000 Source Function Code (SFC)
001 Destination Function Code (DFC)
800 User Stack Pointer (USP)
801 Vector Base Register (VBR)
002
MC68020/MC68030/MC68040
Cache Control Register (CACR)
802
803
Cache Address Register (CAAR)
2
Master Stack Pointer (MSP)
804
003
Interrupt Stack Pointer (ISP)
MC68040/MC68LC040
MMU Translation Control Register (TC)
004 Instruction Transparent Translation Register 0 (ITT0)
005 Instruction Transparent Translation Register 1 (ITT1)
006 Data Transparent Translation Register 0 (DTT0)
007 Data Transparent Translation Register 1 (DTT1)
805 MMU Status Register (MMUSR)
806 User Root Pointer (URP)
807
004
Supervisor Root Pointer (SRP)
MC68EC040 only
Instruction Access Control Register 0 (IACR0)
005 Instruction Access Control Register 1 (IACR1)
006 Data Access Control Register 0 (DACR1)
007 Data Access Control Register 1 (DACR1)
NOTES:
1. Any other code causes an illegal instruction exception
2. For the MC68020 and MC68030 only.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-23
Supervisor (Privileged) Instructions
MOVES
Move Address Space
(MC68010, MC68020, MC68030, MC68040, CPU32)
MOVES
Operation:
Assembler
Syntax:
Attributes:
If Supervisor State
Then Rn
→
Destination [DFC] or Source [SFC]
→
Rn
Else TRAP
MOVES Rn, < ea >
MOVES < ea > ,Rn
Size = (Byte, Word, Long)
Description: This instruction moves the byte, word, or long operand from the specified general register to a location within the address space specified by the destination function code (DFC) register, or it moves the byte, word, or long operand from a location within the address space specified by the source function code (SFC) register to the specified general register. If the destination is a data register, the source operand replaces the corresponding low-order bits of that data register, depending on the size of the operation. If the destination is an address register, the source operand is signextended to 32 bits and then loaded into that address register.
Condition Codes:
Not affected.
Instruction Format:
15
0
A/D
14
0
13
0
REGISTER
12
0
11
1 dr
10
1
0
9
1
0
8
0
0
7
SIZE
6
0 0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
6-24 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
MOVES
Move Address Space
(MC68010, MC68020, MC68030, MC68040, CPU32)
MOVES
Instruction Fields:
Size field—Specifies the size of the operation.
00—Byte Operation
01—Word Operation
10—Long Operation
Effective Address field—Specifies the source or destination location within the alternate address space. Only memory alterable addressing modes can be used as listed in the following tables:
Addressing Mode Mode
Dn —
An
(An)
—
Register
—
—
010 reg. number:An
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
011
100
101
110 reg. number:An reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
—
001
—
(d
(d
8
16
,PC)
,PC,Xn)
—
—
—
—
(bd,An,Xn)*
([bd,An,Xn] ,od)
([bd,An],Xn ,od)
MC68020, MC68030, and MC68040 only
110 reg. number:An (bd,PC,Xn)*
110 reg. number:An
110 reg. number:An
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
*Available for the CPU32.
A/D field—Specifies the type of general register.
0—Data Register
1—Address Register
Register field—Specifies the register number. dr field—Specifies the direction of the transfer.
0—From < ea > to general register.
1—From general register to < ea > .
—
—
—
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-25
Supervisor (Privileged) Instructions
MOVES
Move Address Space
(MC68010, MC68020, MC68030, MC68040, CPU32)
MOVES
NOTE
The value stored is undefined for either of the two following examples with the same address register as both source and destination.
MOVES.x An,(An) +
MOVES.x An,D(An)
The current implementations of the MC68010, MC68020,
MC68030, and MC68040 store the incremented or decremented value of An. Check the following code sequence to determine what value is stored for each case.
MOVEA.L #$1000,A0
MOVES.L A0,(A0) +
MOVES.L A0,D(A0)
Because the MC68040 implements a merged instruction and data space, the MC68040’s integer unit into data references
(SFC/DFC = 5 or 1) translates MOVES accesses to the
OinstructionO address spaces (SFC/DFC = 6 or 2). The data memory unit handles these translated accesses as normal data accesses. If the access fails due to an ATC fault or a physical bus error, the resulting access error stack frame contains the converted function code in the TM field for the faulted access. To maintain cache coherency, MOVES accesses to write the
OinstructionO address space must be preceded by invalidation of the instruction cache line containing the referenced location.
6-26 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
ORI ORI to SR
Inclusive-OR Immediate to the Status Register
to SR
(M68000 Family)
Operation: If Supervisor State
Then Source V SR
→
SR
Else TRAP
Assembler
Syntax:
Attributes:
ORI # < data > ,SR
Size = (Word)
Description: Performs an inclusive-OR operation of the immediate operand and the status register’s contents and stores the result in the status register. All implemented bits of the status register are affected.
Condition Codes:
X
∗
N
∗
Z
∗
V
∗
C
∗
X—Set if bit 4 of immediate operand is one; unchanged otherwise.
N—Set if bit 3 of immediate operand is one; unchanged otherwise.
Z—Set if bit 2 of immediate operand is one; unchanged otherwise.
V—Set if bit 1 of immediate operand is one; unchanged otherwise.
C—Set if bit 0 of immediate operand is one; unchanged otherwise.
Instruction Format:
15
0
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
0
16—BIT WORD DATA
6
1
5
1
4
1
3
1
2
1
1
0
0
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-27
Supervisor (Privileged) Instructions
PBcc
Branch on PMMU Condition
(MC68851)
PBcc
Operation: If Supervisor State
Then If cc True
Then (PC) + dn
→
PC
Else TRAP
Assembler
Syntax:
Attributes:
PBcc. < size > < label >
Size = (Word, Long)
Description: If the specified paged memory management unit condition is met, execution continues at location (PC) + displacement. The displacement is a twos complement integer that counts the relative distance in bytes. The value in the program counter is the address of the displacement word(s). The displacement may be either 16 or 32 bits.
The condition specifier cc indicates the following conditions:
Specifier Description Condition Field
BS B set 000000
LS
SS
L set
S set
000010
000100
AS
WS
IS
GS
CS
A set
W set
I set
G set
C set
000110
001000
001010
001100
001110
Specifier Description Condition Field
BC B clear 000001
LC
SC
L clear
S clear
000011
000101
AC
WC
IC
GC
CC
A clear
W clear
I clear
G clear
C clear
000111
001001
001011
001101
001111
PMMU Status Register: Not affected.
Instruction Format:
15
1
14
1
13
1
12
1
11
0
10
0
9
0
8
0
7
1
6
SIZE
5 4 3 2
MC68851 CONDITION
1
16-BIT DISPLACEMENT OR MOST SIGNIFICANT WORD OF 32-BITDISPLACEMENT
LEAST SIGNIFICANT WORD OF 32-BIT DISPLACEMENT (IF NEEDED)
0
6-28 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PBcc
Branch on PMMU Condition
(MC68851)
PBcc
Instruction Fields:
Size field—Specifies the size of the displacement.
0—Displacement is 16 bits.
1—Displacement is 32 bits.
MC68851 Condition field—Specifies the coprocessor condition to be tested. This field is passed to the MC68851, which provides directives to the main processor for processing this instruction.
Word Displacement field—The shortest displacement form for MC68851 branches is
16 bits.
Long-Word Displacement field—Allows a displacement larger than 16 bits.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-29
Supervisor (Privileged) Instructions
PDBcc
Test, Decrement, and Branch
(MC68851)
PDBcc
Operation: If Supervisor State
Then If cc False
Then (DnD1
→
Dn; If Dn < > D1 then (PC) + d 3 PC)
Else No Operation
Else TRAP
Assembler
Syntax:
Attributes:
PDBcc Dn, < label >
Size = (Word)
Description: This instruction is a looping primitive of three parameters: an MC68851 condition, a counter (an MC68020 data register), and a 16-bit displacement. The instruction first tests the condition to determine if the termination condition for the loop has been met. If so, the main processor executes the next instruction in the instruction stream. If the termination condition is not true, the low-order 16 bits of the counter register are decremented by one. If the result is not D1, execution continues at the location specified by the current value of the program counter plus the sign-extended
16-bit displacement. The value of the program counter used in the branch address calculation is the address of the PDBcc instruction plus two.
The condition specifier cc indicates the following conditions:
Specifier Description Condition Field
BS B set 000000
LS
SS
L set
S set
000010
000100
AS
WS
IS
GS
CS
A set
W set
I set
G set
C set
000110
001000
001010
001100
001110
Specifier Description Condition Field
BC B clear 000001
LC
SC
L clear
S clear
000011
000101
AC
WC
IC
GC
CC
A clear
W clear
I clear
G clear
C clear
000111
001001
001011
001101
001111
6-30 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
PDBcc
Test, Decrement, and Branch
(MC68851)
PMMU Status Register:Not affected.
Instruction Format:
Supervisor (Privileged) Instructions
PDBcc
15
1
0
14
1
0
13
1
0
12
1
0
11
0
0
10
0
0
9
0
8
0
7
0
0 0 0 0
16-BIT DISPLACEMENT
6
1
5
0
4
0
3
1
2 1 0
COUNT REGISTER
MC68851 CONDITION
Instruction Fields:
Register field—Specifies the data register in the main processor to be used as the counter.
MC68851 Condition field—Specifies the MC68851 condition to be tested. This field is passed to the MC68851, which provides directives to the main processor for processing this instruction.
Displacement field—Specifies the distance of the branch in bytes.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-31
Supervisor (Privileged) Instructions
PFLUSH
Flush Entry in the ATC
(MC68030 only)
PFLUSH
Operation:
Assembler
Syntax:
If Supervisor State
Then Invalidate ATC Entries for Destination Addresses
Else TRAP
PFLUSHA
PFLUSH FC,MASK
PFLUSH FC,MASK, < ea >
Unsized Attributes:
Description: PFLUSH invalidates address translation cache entries. The instruction has three forms. The PFLUSHA instruction invalidates all entries. When the instruction specifies a function code and mask, the instruction invalidates all entries for a selected function code(s). When the instruction also specifies an < ea > , the instruction invalidates the page descriptor for that effective address entry in each selected function code.
The mask operand contains three bits that correspond to the three function code bits.
Each bit in the mask that is set to one indicates that the corresponding bit of the FC operand applies to the operation. Each bit in the mask that is zero indicates a bit of FC and of the ignored function code. For example, a mask operand of 100 causes the instruction to consider only the most significant bit of the FC operand. If the FC operand is 001, function codes 000, 001, 010, and 011 are selected.
The FC operand is specified in one of the following ways:
1. Immediate—Three bits in the command word.
2. Data Register—The three least significant bits of the data register specified in the instruction.
3. Source Function Code (SFC) Register
4. Destination Function Code (DFC) Register
Condition Codes:
Not affected.
MMU Status Register:
Not affected.
6-32 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
PFLUSH
Flush Entry in the ATC
(MC68030 only)
Supervisor (Privileged) Instructions
PFLUSH
Instruction Format:
15
1
0
14
1
0
13
1
1
12
1
11
0
MODE
10
0
9
0
0
8
0
0
7
0
6
0
MASK
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
FC
0
Instruction Fields:
Effective Address field—Specifies a control alterable address. The address translation cache entry for this address is invalidated. Valid addressing modes are in the following table:
Addressing Mode Mode
Dn —
An
(An)
—
Register
—
—
010 reg. number:An
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn] ,od)
([bd,An],Xn ,od)
—
—
—
—
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
—
001
—
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
—
—
—
—
—
—
—
—
—
—
NOTE
The address field must provide the memory management unit with the effective address to be flushed from the address translation cache, not the effective address describing where the
PFLUSH operand is located. For example, to flush the address translation cache entry corresponding to a logical address that is temporarily stored on top of the system stack, the instruction
PFLUSH [(SP)] must be used since PFLUSH (SP) would invalidate the address translation cache entry mapping the system stack (i.e., the effective address passed to the memory management unit is the effective address of the system stack, not the effective address formed by the operand located on the top of the stack).
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-33
Supervisor (Privileged) Instructions
PFLUSH
Flush Entry in the ATC
(MC68030 only)
PFLUSH
Mode field—Specifies the type of flush operation.
001—Flush all entries.
100—Flush by function code only.
110—Flush by function code and effective address.
Mask field—Mask for selecting function codes. Ones in the mask correspond to applicable bits; zeros are bits to be ignored. When mode is 001, mask must be
000.
FC field—Function code of entries to be flushed. If the mode field is 001, FC field must be 00000; otherwise:
10XXX — Function code is specified as bits XXX.
01DDD — Function code is specified as bits 2–0 of data register DDD.
00000 — Function code is specified as SFC register.
00001 — Function code is specified as DFC register.
6-34 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PFLUSH
Flush ATC Entries
(MC68040, MC68LC040)
PFLUSH
Operation:
Assembler
Syntax:
Syntax:
Syntax:
Attributes:
Description: Invalidates address translation cache entries in both the instruction and data address translation caches. The instruction has two forms. The PFLUSHA instruction invalidates all entries. The PFLUSH (An) instruction invalidates the entry in each address translation cache which matches the logical address in An and the specified function code.
The function code for PFLUSH is specified in the destination function code register.
Destination function code values of 1 or 2 will result in flushing of user address translation cache entries in both address translation caches; whereas, values of 5 or 6 will result in flushing of supervisor address translation cache entries. PFLUSH is undefined for destination function code values of 0, 3, 4, and 7 and may cause flushing of an unexpected entry.
The PFLUSHN and PFLUSHAN instructions have a global option specified and invalidate only nonglobal entries. For example, if only page descriptors for operating system code have the global bit set, these two PFLUSH variants can be used to flush only user address translation cache entries during task swaps.
Condition Codes:
Not affected.
If Supervisor State
Then Invalidate Instruction and Data ATC Entries for Destination
Address
Else TRAP
PFLUSH (An)
PFLUSHN (An)
PFLUSHA
PFLUSHAN
Unsized
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-35
Supervisor (Privileged) Instructions
PFLUSH
Flush ATC Entries
(MC68040, MC68LC040)
Instruction Format:
Postincrement Source and Destination
PFLUSH
15
1
14
1
13
1
12
1
11
0
10
1
9
0
8
1
7
0
Instruction Fields:
Opmode field—Specifies the flush operation.
6
0
5
0
4 3
OPMODE
2 1
REGISTER
0
Opcode
00
01
10
11
Operation
Flush page entry if not global
Flush page entry
Flush all except global entries
Flush all entries
Assembler Syntax
PFLUSHN (An)
PFLUSH (An)
PFLUSHAN
PFLUSHA
Register field—Specifies the address register containing the effective address to be flushed when flushing a page entry.
6-36 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PFLUSH
Flush ATC Entries
(MC68EC040)
PFLUSH
Operation:
Assembler
Syntax:
Attributes:
If Supervisor State
Then No Operation
Else TRAP
PFLUSH (An)
PFLUSHN (An)
Unsized
Description: This instruction should not be executed when using an MC68EC040. The
PFLUSH encoding suspends operation of the MC68EC040 for an indefinite period of time and subsequently continues with no adverse effects.
Condition Codes:
Not affected.
Instruction Format:
Postincrement Source and Destination
15
1
14
1
13
1
12
1
11
0
10
1
9
0
8
1
7
0
Instruction Fields:
Opmode field—Specifies the flush operation.
6
0
5
0
4 3
OPMODE
2 1
REGISTER
0
Opcode
00
01
10
11
Operation
Flush page entry if not global
Flush page entry
Flush all except global entries
Flush all entries
Assembler Syntax
PFLUSHN (An)
PFLUSH (An)
PFLUSHAN
PFLUSHA
Register field—Specifies the address register containing the effective address to be flushed when flushing a page entry.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-37
Supervisor (Privileged) Instructions
PFLUSH
PFLUSHA
PFLUSH
PFLUSHA
PFLUSHS
Invalidate Entries in the ATC
PFLUSHS
(MC68851)
Operation:
Assembler
Syntax:
If Supervisor State
Then Address Translation Cache Entries For Destination Address
Are Invalidated
Else TRAP
PFLUSHA
PFLUSH FC,MASK
PFLUSHS FC,MASK
PFLUSH FC,MASK, < ea >
PFLUSHS FC,MASK, < ea >
Attributes: Unsigned
Description: PFLUSHA invalidates all entries in the address translation cache.
PFLUSH invalidates a set of address translation cache entries whose function code bits satisfy the relation: (address translation cache function code bits and mask) = (FC and MASK) for all entries whose task alias matches the task alias currently active when the instruction is executed. With an additional effective address argument, PFLUSH invalidates a set of address translation cache entries whose function code satisfies the relation above and whose effective address field matches the corresponding bits of the evaluated effective address argument. In both of these cases, address translation cache entries whose SG bit is set will not be invalidated unless the PFLUSHS is specified.
The function code for this operation may be specified as follows:
1. Immediate—The function code is four bits in the command word.
2. Data Register—The function code is in the lower four bits of the MC68020 data register specified in the instruction.
3. Source Function Code (SFC) Register—The function code is in the CPU SFC register. Since the SFC of the MC68020 has only three implemented bits, only function codes $0D$7 can be specified in this manner.
4. Destination Function Code (DFC) Register—The function code is in the CPU
DFC register. Since the DFC of the MC68020 has only three implemented bits, only function codes $0D$7 can be specified in this manner.
6-38 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PFLUSH
PFLUSHA
PFLUSH
PFLUSHA
PFLUSHS
Invalidate Entries in the ATC
PFLUSHS
(MC68851)
PMMU Status Register: Not affected.
Instruction Format:
15
1
0
14
1
0
13
1
1
12
1
11
0
MODE
10
0
9
0
0
8
0
7
0
MASK
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
FC
0
Instruction Fields:
Effective Address field—Specifies an address whose page descriptor is to be flushed from (invalidated) the address translation cache. Only control alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn —
An
(An)
—
Register
—
—
010 reg. number:An
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn] ,od)
([bd,An],Xn ,od)
—
—
—
—
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
—
001
—
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
—
—
—
—
—
—
—
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-39
Supervisor (Privileged) Instructions
PFLUSH
PFLUSHA
PFLUSH
PFLUSHA
PFLUSHS
Invalidate Entries in the ATC
PFLUSHS
(MC68851)
NOTE
The effective address field must provide the MC68851 with the effective address of the entry to be flushed from the address translation cache, not the effective address describing where the
PFLUSH operand is located. For example, in order to flush the address translation cache entry corresponding to a logical address that is temporarily stored on the top of the system stack, the instruction PFLUSH [(SP)] must be used since PFLUSH
(SP) would invalidate the address translation cache entry mapping the system stack (i.e., the effective address passed to the MC68851 is the effective address of the system stack, not the effective address formed by the operand located on the top of the stack).
Mode field—Specifies how the address translation cache is to be flushed.
001—Flush all entries.
100—Flush by function code only.
101—Flush by function code including shared entries.
110—Flush by function code and effective address.
111—Flush by function code and effective address including shared entries.
Mask field—Indicates which bits are significant in the function code compare. A zero indicates that the bit position is not significant; a one indicates that the bit position is significant. If mode = 001 (flush all entries), mask must be 0000.
FC field—Function code of address to be flushed. If the mode field is 001 (flush all entries), function code must be 00000; otherwise:
1DDDD — Function code is specified as four bits DDDD.
01RRR — Function code is contained in CPU data register RRR.
00000 — Function code is contained in CPU SFC register.
00001 — Function code is contained in CPU DFC register.
6-40 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PFLUSHR
Invalidate ATC and RPT Entries
PFLUSHR
(MC68851)
Operation: If Supervisor State
Then RPT Entry (If Any) Matching Root Pointer Specified by < ea >
Corresponding Address Translation Cache Entries Are Invalidated
Else TRAP
Assembler
Syntax:
Attributes:
PFLUSHR < ea >
Unsized
Description: The quad word pointed to by < ea > is regarded as a previously used value of the CPU root pointer register. The root pointer table entry matching this CPU root pointer register (if any) is flushed, and all address translation cache entries loaded with this value of CPU root pointer register (except for those that are globally shared) are invalidated. If no entry in the root pointer table matches the operand of this instruction, no action is taken.
If the supervisor root pointer is not in use, the operating system should not issue the
PFLUSHR command to destroy a task identified by the current CPU root pointer register. It should wait until the CPU root pointer register has been loaded with the root pointer identifying the next task until using the PFLUSHR instruction. At any time, execution of the PFLUSHR instruction for the current CPU root pointer register causes the current task alias to be corrupted.
Instruction Format:
15
1
1
14
1
0
13
1
1
12
1
0
11
0
0
10
0
0
9
0
0
8
0
0
7
0
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-41
Supervisor (Privileged) Instructions
PFLUSHR
Invalidate ATC and RPT Entries
PFLUSHR
(MC68851)
Instruction Field:
Effective Address field—Specifies the address of a previous value of the CPU root pointer register register. Only memory addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn —
An
(An)
—
Register
—
—
010 reg. number:An
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn] ,od)
([bd,An],Xn ,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
111
001
100
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
111
111
111
111
111
010
011
011
011
011
NOTE
The effective address usage of this instruction is different than that of other PFLUSH variants.
6-42 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PLOAD
Load an Entry into the ATC
(MC68030 only, MC68851)
PLOAD
Operation: If Supervisor State
Then Search Translation Table and Make Address Translation
Cache Entry for Effective Address
Else TRAP
Assembler
Syntax:
Attributes:
PLOADR FC, < ea >
PLOADW FC, < ea >
Unsized
Description: For the MC68851, PLOAD searches the translation table for a translation of the specified effective address. If one is found, it is flushed from the address translation cache, and an entry is made as if a bus master had run a bus cycle. Used and modified bits in the table are updated as part of the table search. The MC68851 ignores the logical bus arbitration signals during the flush and load phases at the end of this instruction. This prevents the possibility of an entry temporarily disappearing from the address translation cache and causing a false table search.
This instruction will cause a paged memory management unit illegal operation exception (vector $39) if the E-bit of the translation control register is clear.
The function code for this operation may be specified to be:
1. Immediate—The function code is specified as four bits in the command word.
2. Data Register—The function code is contained in the lower four bits in the
MC68020 data register specified in the instruction.
3. Source Function Code (SFC) Register—The function code is in the CPU SFC register. Since the SFC of the MC68020 has only three implemented bits, only function codes $0D$7 can be specified in this manner.
4. Destination Function Code (DFC) Register—The function code is in the CPU
DFC register. Since the DFC of the MC68020 has only three implemented bits, only function codes $0D$7 can be specified in this manner.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-43
Supervisor (Privileged) Instructions
PLOAD
Load an Entry into the ATC
(MC68030 only, MC68851)
PLOAD
For the MC68030, PLOAD searches the address translation cache for the specified effective address. It also searches the translation table for the descriptor corresponding to the specified effective address. It creates a new entry as if the MC68030 had attempted to access that address. Sets the used and modified bits appropriately as part of the search. The instruction executes despite the value of the E-bit in the translation control register or the state of the MMUDIS signal.
The < function code > operand is specified in one of the following ways:
1. Immediate—Three bits in the command word.
2. Data Register—The three least significant bits of the data register specified in the instruction.
3. Source Function Code (SFC) Register
4. Destination Function Code (DFC) Register
The effective address field specifies the logical address whose translation is to be loaded.
PLOADR causes U bits in the translation tables to be updated as if a read access had occurred. PLOADW causes U and M bits in the translation tables to be updated as if a write access had occurred.
PMMU Status Register: Not affected.
Instruction Format:
15
1
0
14
1
0
13
1
1
12
1
0
11
0
0
10
0
0
9
0
R/ W
8
0
0
7
0
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
FC
0
6-44 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PLOAD
Load an Entry into the ATC
(MC68030 only, MC68851)
PLOAD
Instruction Fields:
Effective Address field—Specifies the logical address whose translation is to be loaded into the address translation cache. Only control alterable addressing modes are allowed as listed in the following table:
Addressing Mode Mode
Dn —
An
(An)
—
Register
—
—
010 reg. number:An
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn] ,od)
([bd,An],Xn ,od)
—
—
—
—
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
—
001
—
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
—
—
—
—
—
—
—
—
—
—
NOTE
The effective address field must provide the MC68851 with the effective address of the entry to be loaded into the address translation cache, not the effective address describing where the
PLOAD operand is located. For example, to load an address translation cache entry to map a logical address that is temporarily stored on the system stack, the instruction PLOAD
[(SP)] must be used since PLOAD (SP) would load an address translation cache entry mapping the system stack (i.e., the effective address passed to the MC68851 is the effective address of the system stack, not the effective address formed by the operand located on the top of the stack).
R/W field—Specifies whether the tables should be updated for a read or a write.
1—Read
0—Write
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-45
Supervisor (Privileged) Instructions
PLOAD
Load an Entry into the ATC
(MC68030 only, MC68851)
PLOAD
FC field (MC68851)—Function code of address to load.
1DDDD — Function code is specified as four bits DDDD.
01RRR — Function code is contained in CPU data register RRR.
00000 — Function code is contained in CPU SFC register.
00001 — Function code is contained in CPU DFC register.
FC field (MC68030)—Function code of address corresponding to entry to be loaded.
10XXX — Function code is specified as bits XXX.
01DDD — Function code is specified as bits 2–0 of data register DDD.
00000 — Function code is specified as SFC register.
00001 — Function code is specified as DFC register.
6-46 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PMOVE
Move to/from MMU Registers
(MC68030 only)
PMOVE
Operation:
Assembler
Syntax:
If Supervisor State
Then (Source)
→
MRn or MRn
→
(Destination)
PMOVE MRn, < ea >
PMOVE < ea > ,MRn
PMOVEFD < ea > ,MRn
Attributes: Size = (Word, Long, Quad)
Description: Moves the contents of the source effective address to the specified memory management unit register or moves the contents of the memory management unit register to the destination effective address.
The instruction is a quad-word (8 byte) operation for the CPU root pointer and the supervisor root pointer. It is a long-word operation for the translation control register and the transparent translation registers (TT0 and TT1). It is a word operation for the
MMU status register.
The PMOVEFD form of this instruction sets the FD-bit to disable flushing the address translation cache when a new value loads into the supervisor root pointer, CPU root pointer, TT0, TT1 or translation control register (but not the MMU status register).
Writing to the following registers has the indicated side effects:
CPU Root Pointer—When the FD-bit is zero, it flushes the address translation cache.
If the operand value is invalid for a root pointer descriptor, the instruction takes an memory management unit configuration error exception after moving the operand to the CPU root pointer.
Supervisor Root Pointer—When the FD-bit is zero, it flushes the address translation cache. If the operand value is invalid as a root pointer descriptor, the instruction takes an memory management unit configuration error exception after moving the operand to the supervisor root pointer.
Translation Control Register—When the FD-bit is zero, it flushes the address translation cache. If the E-bit = 1, consistency checks are performed on the PS and TIx fields.
If the checks fail, the instruction takes an memory management unit configuration exception after moving the operand to the translation control register. If the checks pass, the translation control register is loaded with the operand and the E-bit is cleared.
TT0, TT1—When the FD-bit is zero, it flushes the address translation cache. It enables or disables the transparent translation register according to the E-bit written. If the Ebit = 1, the transparent translation register is enabled. If the E- bit = 0, the register is disabled.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-47
Supervisor (Privileged) Instructions
PMOVE
Move to/from MMU Registers
(MC68030 only)
PMOVE
Condition Codes:
Not affected.
MMU Status Register:
Not affected (unless the MMU status register is specified as the destination operand).
Instruction Format:
SRP, CRP, and TC Registers
15
1
0
14
1
1
13
1
0
12
1
11
0
P-REGISTER
10
0
9
0
R/ W
8
0
FD
7
0
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
Instruction Fields:
Effective Address field—Specifies the memory location for the transfer. Only control alterable addressing modes can be used as in the following table:
Addressing Mode Mode
Dn —
An
(An)
—
Register
—
—
010 reg. number:An
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn] ,od)
([bd,An],Xn ,od)
—
—
—
—
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
—
001
—
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
—
—
—
—
—
—
—
—
—
—
6-48 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PMOVE
Move to/from MMU Registers
(MC68030 only)
PMOVE
P-Register field—Specifies the memory management unit register.
000—Translation Control Register
010—Supervisor Root Pointer
011—CPU Root Pointer
R/W field—Specifies the direction of transfer.
0—Memory to memeory management unit register.
1—Memeory management unit register to memory.
FD field—Disables flushing of the address translation cache on writes to memeory management unit registers.
0—Address translation cache is flushed.
1—Address translation cache is not flushed.
Instruction Format:
MMU Status Register
15
1
0
14
1
1
13
1
1
12
1
0
11
0
0
10
0
0
9
0
R/ W
8
0
0
7
0
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
Instruction Fields:
Effective Address field—Specifies the memory location for the transfer. Control alterable addressing modes shown for supervisor root pointer register apply.
R/W field—Specifies the direction of transfer.
0—Memory to MMU status register.
1—MMU status register to memory.
NOTE
The syntax of assemblers for the MC68851 use the symbol
PMMU status register for the MMU status register.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-49
Supervisor (Privileged) Instructions
PMOVE
Move to/from MMU Registers
(MC68030 only)
Instruction Format:
TT Registers
PMOVE
15
1
0
14
1
0
13
1
0
12
1
11
0
P-REGISTER
10
0
9
0
R/ W
8
0
FD
7
0
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
Instruction Fields:
Effective Address field—Specifies the memory location for the transfer. Control alterable addressing modes shown for supervisor root pointer register apply.
P-Register field—Specifies the transparent translation register.
010—Transparent Translation Register 0
011—Transparent Translation Register 1
R/W field—Specifies the direction of transfer.
0—Memory to MMU status register.
1—MMU status register to memory.
FD field—Disables flushing of the address translation cache.
0—Address translation cache is flushed.
1—Address translation cache does not flush.
6-50 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PMOVE
Move to/from MMU Registers
(MC68EC030)
PMOVE
Operation:
Assembler
Syntax:
Attributes:
If Supervisor State
Then (Source)
→
MRn or MRn
→
(Destination)
PMOVE MRn, < ea >
PMOVE < ea > ,MRn
Size = (Word, Long, Quad)
Description: Moves the contents of the source effective address to an access control register or moves the contents of an access control register to the destination effective address.
The instruction is a long-word operation for the access control registers (AC0 and
AC1). It is a word operation for the access control unit status register (ACUSR).
Writing to the ACx registers enables or disables the access control register according to the E-bit written. If the E-bit = 1, the access control register is enabled. If the E-bit =
0, the register is disabled
Condition Codes:
Not affected.
ACUSR:
Not affected unless the ACUSR is specified as the destination operand.
Instruction Format:
ACUSR
15
1
0
14
1
1
13
1
1
12
1
0
11
0
0
10
0
0
9
0
R/W
8
0
0
7
0
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
Instruction Fields:
Effective Address field—Specifies the memory location for the transfer.
R/W field—Specifies the direction of transfer.
0—Memory to ACUSR
1—ACUSR to memory
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-51
Supervisor (Privileged) Instructions
PMOVE
Move to/from MMU Registers
(MC68EC030)
PMOVE
NOTE
Assembler syntax for the MC68851 uses the symbol PMMU status register for the ACUSR; and for the MC68030, the symbols TT0 and TT1 for AC0 and AC1.
Instruction Format:
ACx Registers
15
1
0
14
1
0
13
1
0
12
1
11
0
P-REGISTER
10
0
9
0
R/W
8
0
0
7
0
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
Instruction Fields:
Effective Address field—Specifies the memory location for the transfer.
P-Register field—Specifies the ACx register.
001—Access Control Register 0
011—Access Control Register 1
R/W field—Specifies the direction of transfer.
0—Memory to ACUSR
1—ACUSR to memory
6-52 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PMOVE
Move PMMU Register
(MC68851)
PMOVE
Operation:
Assembler
Syntax:
Attributes:
If Supervisor State
Then MC68851 Register
→
Destination
Or Source
→
MC68851 Register
Else TRAP
PMOVE < PMMU Register > , < ea >
PMOVE < ea > , < PMMU Register >
Size = (Byte, Word, Long, Double Long)
Description: The contents of the MC68851 register copies to the address specified by < ea
> , or the data at < ea > copies into the MC68851 register.
The instruction is a quad-word operation for CPU root pointer, supervisor root pointer, and DMA root pointer registers. It is a long-word operation for the translation control register and a word operation for the breakpoint acknowledge control, breakpoint acknowledge data, access control, PMMU status, and PMMU cache status registers.
PMOVE is a byte operation for the current access level, valid access level, and stack change control registers.
The following side effects occur when data is read into certain registers:
CPU Root Pointer—Causes the internal root pointer table to be searched for the new value. If there is no matching value, an entry in the root pointer table is selected for replacement, and all address translation cache entries associated with the replaced entry are invalidated.
Supervisor Root Pointer—Causes all entries in the address translation cache that were formed with the supervisor root pointer (even globally shared entries) to be invalidated.
DMA Root Pointer—Causes all entries in the address translation cache that were formed with the DMA root pointer (even globally shared entries) to be invalidated.
Translation Control Register—If data written to the translation control register attempts to set the E-bit and the E-bit is currently clear, a consistency check is performed on the IS, TIA, TIB, TIC, TID, and PS fields.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-53
Supervisor (Privileged) Instructions
PMOVE
Move PMMU Register
(MC68851)
PMOVE
PMMU Status Register: Not affected unless the PMMU status register is written to by the instruction.
Instruction Format 1:
PMOVE to/from TC, CRP, DRP, SRP, CAL, VAL, SCC, AC
15
1
0
14
1
1
13
1
0
12
1
11
0
P-REGISTER
10
0
9
0
R/ W
8
0
0
7
0
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
Instruction Fields:
Effective Address field—for memory-to-register transfers, any addressing mode is allowed as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An*
(An)
001
010 reg. number:An reg. number:An
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn] ,od)
([bd,An],Xn ,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
(d
16
(d
8
,PC)
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
*PMOVE to CRP, SRP, and DMA root pointer not allowed with these modes
111
111
111
111
111
111
111
001
100
010
011
011
011
011
6-54 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PMOVE
Move PMMU Register
(MC68851)
PMOVE
For register-to-memory transfers, only alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn* 000
Register reg. number:Dn
An*
(An)
001
010 reg. number:An reg. number:An
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn] ,od)
([bd,An],Xn ,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
—
001
—
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
—
—
—
—
—
—
—
—
—
—
*PMOVE to CRP, SRP, and DMA root pointer not allowed with these modes
Register field—Specifies the MC68851 register.
000—Translation Control Register
001—DMA Root Pointer
010—Supervisor Root Pointer
011—CPU Root Pointer
100—Current Access Level
101—Valid Access Level
110—Stack Change Control Register
111—Access Control Register
R/W field—Specifies the direction of transfer.
0—Transfer < ea > to MC68851 register.
1—Transfer MC68851 register to < ea > .
Instruction Format 2:
PMOVE to/from BADx, BACx
15
1
0
14
1
1
13
1
1
12
1
11
0
P-REGISTER
10
0
9
0
R/ W
8
0
0
7
0
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
NUM
REGISTER
0
0
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-55
Supervisor (Privileged) Instructions
PMOVE
Move PMMU Register
(MC68851)
PMOVE
Instruction Fields:
Effective Address field—Same as format 1.
P-Register field—Specifies the type of MC68851 register.
100—Breakpoint Acknowledge Data
101—Breakpoint Acknowledge Control
R/W field—Specifies the direction of transfer.
0—Transfer < ea > to MC68851 register
1—Transfer MC68851 register to < ea >
Num field—Specifies the number of the BACx or BADx register to be used.
Instruction Format 3:
PMOVE to/from PSR, from PCSR
15
1
0
14
1
1
13
1
1
12
1
11
0
P-REGISTER
10
0
9
0
R/ W
8
0
0
Instruction Fields:
Effective Address field—Same as format 1.
7
0
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
P Register field—Specifies the MC68851 register.
000 — PMMU Status Register
001 — PMMU Cache Status Register
R/W field—Specifies direction of transfer.
0—Transfer < ea > to MC68851 register.
1—Transfer MC68851 register to < ea > (must be one to access PMMU cache status register using this format).
6-56 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PRESTORE
PMMU Restore Function
PRESTORE
(MC68851)
Operation: If Supervisor State
Then MC68851 State Frame
→
Internal State, Programmer
Registers
Else TRAP
Assembler
Syntax:
Attributes:
PRESTORE < ea >
Unsized, Privileged
Description: The MC68851 aborts execution of any operation in progress. New programmer registers and internal states are loaded from the state frame located at the effective address. The first word at the specified address is the format word of the state frame, specifying the size of the frame and the revision number of the MC68851 that created it. The MC68020 writes the first word to the MC68851 restore coprocessor interface register, initiating the restore operation. Then it reads the response coprocessor interface register to verify that the MC68851 recognizes the format as valid. The format is invalid if the MC68851 does not recognize the frame size or the revision number does not match. If the format is invalid, the MC68020 takes a format exception, and the MC68851 returns to the idle state with its user visible registers unchanged. However, if the format is valid, then the appropriate state frame loads, starting at the specified location and proceeding up through the higher addresses.
The PRESTORE instruction restores the nonuser visible state of the MC68851 as well as the PMMU status register, CPU root pointer, supervisor root pointer, current access level, valid access level, and stack change control registers of the user programming model. In addition, if any breakpoints are enabled, all breakpoint acknowledge control and breakpoint acknowledge data registers are restored. This instruction is the inverse of the PSAVE instruction.
The current implementation of the MC68851 supports four state frame sizes:
NULL: This state frame is 4 bytes long, with a format word of $0. A PRESTORE with this size state frame places the MC68851 in the idle state with no coprocessor or module operations in progress.
IDLE: This state frame is 36 ($24) bytes long. A PRESTORE with this size state frame causes the MC68851 to place itself in an idle state with no coprocessor operations in progress and no breakpoints enabled. A module operation may or may not be in progress. This state frame restores the minimal set of
MC68851 registers.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-57
Supervisor (Privileged) Instructions
PRESTORE
PMMU Restore Function
PRESTORE
(MC68851)
MID-COPROCESSOR: This state frame is 44 ($2C) bytes long. A PRESTORE with this size frame restores the MC68851 to a state with a coprocessor operation in progress and no breakpoints enabled.
BREAKPOINTS ENABLED: This state frame is 76 ($4C) bytes long. A PRESTORE with this size state frame restores all breakpoint registers, along with other states. A coprocessor operation may or may not be in progress.
PMMU Status Register: Set according to restored data.
Instruction Format:
15
1
14
1
13
1
12
1
11
0
10
0
9
0
8
1
7
0
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields:
Effective Address field—Specifies the source location. Only control or post-increment addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn —
An
(An)
—
Register
—
—
010 reg. number:An
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn] ,od)
([bd,An],Xn ,od)
011 reg. number:An
— —
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
—
001
—
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
111
111
111
111
111
010
011
011
011
011
6-58 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PSAVE
PMMU Save Function
(MC68851)
PSAVE
Operation: If Supervisor State
Then MC68851 Internal State, Programmer
Registers
→
State Frame
Else TRAP
Assembler
Syntax:
Attributes:
PSAVE < ea >
Unsized, Privileged
Description: The MC68851 suspends execution of any operation that it is performing and saves its internal state and some programmer registers in a state frame located at the effective address. The following registers are copied: PMMU status, control root pointer, supervisor root pointer, current access level, valid access level, and stack change control. If any breakpoint is enabled, all breakpoint acknowledge control and breakpoint acknowledge data registers are copied. After the save operation, the
MC68851 is in an idle state waiting for another operation to be requested. Programmer registers are not changed.
The state frame format saved by the MC68851 depends on its state at the time of the
PSAVE operation. In the current implementation, three state frames are possible:
IDLE: This state frame is 36 ($24) bytes long. A PSAVE of this size state frame indicates that the MC68851 was in an idle state with no coprocessor operations in progress and no breakpoints enabled. A module call operation may or may not have been in progress when this state frame was saved.
MID-COPROCESSOR:This state frame is 44 ($2C) bytes long. A PSAVE of this size frame indicates that the MC68851 was in a state with a coprocessor or module call operation in progress and no breakpoints enabled.
BREAKPOINTS ENABLED:This state frame is 76 ($4C) bytes long. A PSAVE of this size state frame indicates that one or more breakpoints were enabled. A coprocessor or module call operation may or may not have been in progress.
PMMU Status Register: Not affected
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-59
Supervisor (Privileged) Instructions
PSAVE
PMMU Save Function
(MC68851)
Instruction Format:
PSAVE
15
1
14
1
13
1
12
1
11
0
10
0
9
0
8
1
7
0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
Instruction Fields:
Effective Address field—Specifies the destination location. Only control or predecrement addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn —
An
(An)
—
Register
—
—
010 reg. number:An
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn] ,od)
([bd,An],Xn ,od)
— —
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
—
001
—
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
—
—
—
—
—
—
—
—
—
—
6-60 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PScc
Set on PMMU unit Condition
(MC68851)
PScc
Operation: If Supervisor State
Then If cc True
Then 1s
→
Destination
Else 0s
→
Destination
Else TRAP
Assembler
Syntax:
Attributes:
PScc < ea >
Size = (Byte)
Description: The specified MC68851 condition code is tested. If the condition is true, the byte specified by the effective address is set to TRUE (all ones); otherwise, that byte is set to FALSE (all zeros).
The condition code specifier cc may specify the following conditions:
Specifier Description Condition Field
BS B set 000000
LS
SS
L set
S set
000010
000100
AS
WS
IS
GS
CS
A set
W set
I set
G set
C set
000110
001000
001010
001100
001110
PMMU Status Register: Not affected
Specifier Description Condition Field
BC B clear 000001
LC
SC
L clear
S clear
000011
000101
AC
WC
IC
GC
CC
A clear
W clear
I clear
G clear
C clear
000111
001001
001011
001101
001111
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-61
Supervisor (Privileged) Instructions
PScc
Set on PMMU Condition
(MC68851)
Instruction Format:
PScc
15
1
0
14
1
0
13
1
0
12
1
0
11
0
0
10
0
0
9
0
0
8
0
0
7
0
0
6
1
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
MC68851 CONDITION
0
Instruction Fields:
Effective Address field—Specifies the destination location. Only data alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn 000
Register reg. number:Dn
An
(An)
—
010
— reg. number:An
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn] ,od)
([bd,An],Xn ,od)
011 reg. number:An
100 reg. number:An
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
—
001
—
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
—
—
—
—
—
—
—
—
—
—
MC68851 Condition field—Specifies the coprocessor condition to be tested. This field is passed to the MC68851, which provides directives to the main processor for processing this instruction.
6-62 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PTEST
Test a Logical Address
(MC68030 only)
PTEST
Operation:
Assembler
Syntax:
If Supervisor State
Then Logical Address Status
→
MMUSR
Else TRAP
PTESTR FC, < ea > ,# < level >
PTESTR FC, < ea > ,# < level > ,An
PTESTW FC, < ea > ,# < level >
PTESTW FC, < ea > ,# < level > ,An
Unsized Attributes:
Description: This instruction searches the address translation cache or the translation tables to a specified level. Searching for the translation descriptor corresponding to the
< ea > field, it sets the bits of the MMU status register according to the status of the descriptor. Optionally, PTEST stores the physical address of the last table entry accessed during the search in the specified address register. The PTEST instruction searches the address translation cache or the translation tables to obtain status information, but alters neither the used or modified bits of the translation tables nor the address translation cache. When the level operand is zero, only the transparent translation of either read or write accesses causes the operations of the PTESTR and
PTESTW to return different results.
The < function code > operand is specified as one of the following:
1. Immediate—Three bits in the command word.
2. Data Register—The three least significant bits of the data register specified in the instruction.
3. Source Function Code (SFC) Register
4. Destination Function Code (DFC) Register
The effective address is the address to test. The < level > operand specifies the level of the search. Level 0 specifies searching the addrass translation cache only. Levels
1–7 specify searching the translation tables only. The search ends at the specified level. A level 0 test does not return the same MMU status register values as a test at a nonzero level number.
Execution of the instruction continues to the requested level or until detecting one of the following conditions:
• Invalid Descriptor
• Limit Violation
• Bus Error Assertion (Physical Bus Error)
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-63
Supervisor (Privileged) Instructions
PTEST
Test a Logical Address
(MC68030 only)
PTEST
The instruction accumulates status as it accesses successive table entries. When the instruction specifies an address translation cache search with an address register operand, the MC68030 takes an F-line unimplemented instruction exception.
If there is a parameter specification for a translation table search, the physical address of the last descriptor successfully fetched loads into the address register. A successfully fetched descriptor occurs only if all portions of the descriptor can be read by the
MC68030 without abnormal termination of the bus cycle. If the root pointer’s DT field indicates page descriptor, the returned address is $0. For a long descriptor, the address of the first long word is returned. The size of the descriptor (short or long) is not returned and must be determined from a knowledge of the translation table.
Condition Codes:
Not affected.
MMUSR:
B
∗
L
∗
S
∗
W
∗ ∗
I M
∗
T
0
N
0 0 0 0 0 0
∗
6-64 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PTEST
Test a Logical Address
(MC68030 only)
PTEST
The MMU status register contains the results of the search. The values in the fields of the MMU status register for an address translation cache search are given in the following table:
MMUSR Bit
Bus Error (B)
Limit (L)
PTEST, Level 0 PTEST, Levels 1–7
This bit is set if the bus error bit is set in the
ATC entry for the specified logical address.
This bit is set if a bus error is encountered during the table search for the PTEST instruction.
This bit is cleared.
This bit is set if an index exceeds a limit during the table search.
Supervis or
Violatio n (S)
Write
Protecte d (W)
Invalid (I)
Modified (M)
This bit is cleared.
This bit is set if the S-bit of a long (S) format table descriptor or long format page descriptor encountered during the search is set and if the FC2-bit of the function code specified by the PTEST instruction is not equal to one. The S-bit is undefined if the Ibit is set.
The bit is set if the WP-bit of the ATC entry is set. It is undefined if the I-bit is set.
This bit is set if a descriptor or page descriptor is encountered with the WP-bit set during the table search. The W-bit is undefined if the I-bit is set.
This bit indicates an invalid translation. The
I- bit is set if the translation for the specified logical address is not resident in the ATC or if the B-bit of the corresponding ATC entry is set.
This bit indicates an invalid translation. The
I-bit is set if the DT field of a table or a page descriptor encountered during the search is set to invalid or if either the B or L bits of the MMUSR are set during the table search.
This bit is set if the ATC entry corresponding to the specified address has the modified bit set. It is undefined if the I-bit is set.
This bit is set if the page descriptor for the specified address has the modified bit set.
It is undefined if I-bit is set.
Transparent (T) This bit is set if a match occurred in either
(or both) of the transparent translation registers (TT0 or TT1).
This bit is set to zero.
Number of
Levels (N)
This 3-bit field is set to zero.
This 3-bit field contains the actual number of tables accessed during the search.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-65
Supervisor (Privileged) Instructions
PTEST
Test a Logical Address
(MC68030 only)
Instruction Format:
PTEST
15
1
1
14
1
0
13
1
0
12
1
11
0
LEVEL
10
0
9
0
R/ W
8
0
A
7
0
6
0
5
REGISTER
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
FC
0
Instruction Fields:
Effective Address field—Specifies the logical address to be tested. Only control alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn —
An
(An)
—
Register
—
—
010 reg. number:An
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn] ,od)
([bd,An],Xn ,od)
—
—
—
—
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
—
001
—
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
—
—
—
—
—
—
—
—
—
—
Level field—Specifies the highest numbered level to be searched in the table. When this field contains 0, the A field and the register field must also be 0. The instruction takes an F-line exception when the level field is 0 and the A field is not
0.
R/W field—Specifies simulating a read or write bus cycle (no difference for MC68030
MMU).
0—Write
1—Read
A field—Specifies the address register option.
0—No address register.
1—Return the address of the last descriptor searched in the address register specified in the register field.
6-66 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PTEST
Test a Logical Address
(MC68030 only)
PTEST
Register field—Specifies an address register for the instruction. When the A field contains 0, this field must contain 0.
FC field—Function code of address to be tested.
10XXX — Function code is specified as bits XXX.
01DDD — Function code is specified as bits 2–0 of data register DDD.
00000 — Function code is specified as source function code register.
00001 — Function code is specified as destination function code register.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-67
Supervisor (Privileged) Instructions
PTEST
Test a Logical Address
(MC68EC030)
PTEST
Operation:
Assembler
Syntax:
Attributes:
If Supervisor State
Then Logical Address Status
→
ACUSR
Else TRAP
PTESTR FC, < ea >
PTESTW FC, < ea >
Unsized
Description: This instruction searches the access control registers for the address descriptor corresponding to the < ea > field and sets the bit of the access control unit status register (ACUSR) according to the status of the descriptor.
The < function code > operand is specified in one of the following ways:
1. Immediate—Three bits in the command word.
2. Data Register—The three least significant bits of the data register specified in the instruction.
3. Source Function Code (SFC) Register
4. Destination Function Code (DFC) Register
The effective address is the address to test.
Condition Codes:
Not affected.
ACUSR: x x x = May be 0 or 1. x 0 x x x 0 0 AC 0 0 0 x x x
The AC-bit is set if a match occurs in either (or both) of the access control registers.
Instruction Format:
15
1
1
14
1
0
13
1
0
12
1
0
11
0
0
10
0
0
9
0
R/ W
8
0
0
7
0
6
0
REGISTER
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
FC
0
6-68 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PTEST
Test a Logical Address
(MC68EC030)
PTEST
Instruction Fields:
Effective Address field—Specifies the logical address to be tested. Only control alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn —
An
(An)
—
Register
—
—
010 reg. number:An
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn] ,od)
([bd,An],Xn ,od)
—
—
—
—
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
—
001
—
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
—
—
—
—
—
—
—
—
—
—
R/W field—Specifies simulating a read or write bus cycle.
0—Write
1—Read
Register field—Specifies an address register for the instruction. When the A field contains 0, this field must contain 0.
FC field—Function code of address to be tested.
10XXX — Function code is specified as bits XXX.
01DDD — Function code is specified as bits 2–0 of data register DDD.
00000 — Function code is specified as source function code register.
00001 — Function code is specified as destination function code register.
NOTE
Assembler syntax for the MC68030 is PTESTR FC, < ea > ,#0 and PTESTW FC, < ea > ,#0.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-69
Supervisor (Privileged) Instructions
PTEST
Test a Logical Address
(MC68040, MC68LC040)
PTEST
Operation:
Assembler
Syntax:
Attributes:
If Supervisor State
Then Logical Address Status
→
MMUSR; Entry
→
ATC
Else TRAP
PTESTR (An)
PTESTW (An)
Unsized
Description: This instruction searches the translation tables for the page descriptor corresponding to the test address in An and sets the bits of the MMU status register according to the status of the descriptors. The upper address bits of the translated physical address are also stored in the MMU status register. The PTESTR instruction simulates a read access and sets the U-bit in each descriptor during table searches;
PTESTW simulates a write access and also sets the M-bit in the descriptors, the address translation cache entry, and the MMU status register.
A matching entry in the address translation cache (data or instruction) specified by the function code will be flushed by PTEST. Completion of PTEST results in the creation of a new address translation cache entry. The specification of the function code for the test address is in the destination function code (DFC) register. A PTEST instruction with a DFC value of 0, 3, 4, or 7 is undefined and will return an unknown value in the
MMUSR.
Execution of the instruction continues until one of the following conditions occurs:
• Match with one of the two transparent translation registers.
• Transfer Error Assertion (physical transfer error)
• Invalid Descriptor
• Valid Page Descriptor
Condition Codes:
Not affected.
MMU Status Register:
PHYSICAL ADDRESS
∗
B
∗
G
∗
U1
∗
U0
∗
S
∗
CM
∗
M
∗
W
∗
T
∗
R
∗
0
6-70 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PTEST
Test a Logical Address
(MC68040, MC68LC040)
PTEST
The MMUSR contains the results of the search. The values in the fields of the MMUSR for a search are:
Physical Address—This 20-bit field contains the upper bits of the translated physical address. Merging these bits with the lower bits of the logical address forms the actual physical address.
Bus Error (B)—Set if a transfer error is encountered during the table search for the
PTEST instruction. If this bit is set, all other bits are zero.
Globally Shared (G)—Set if the G-bit is set in the page descriptor.
User Page Attributes (U1, U0)—Set if corresponding bits in the page descriptor are set.
Supervisor Protection (S)—Set if the S-bit in the page descriptor is set. This bit does not indicate that a violation has occurred.
Cache Mode (CM)—This 2-bit field is copied from the CM-bit in the page descriptor.
Modified (M)—Set if the M-bit is set in the page descriptor associated with the address.
Write Protect (W)—Set if the W-bit is set in any of the descriptors encountered during the table search. Setting of this bit does not indicate that a violation occurred.
Transparent Translation Register Hit (T)—Set if the PTEST address matches an instruction or data transparent translation register and the R-bit is set; all other bits are zero.
Resident (R)—Set if the PTEST address matches a transparent translation register or if the table search completes by obtaining a valid page descriptor.
Instruction Format:
15
1
14
1
13
1
12
1
11
0
10
1
9
0
8
1
7
0
6
1
5
R/ W
Instruction Fields:
R/W field—Specifies simulating a read or write bus transfer.
0—Write
1—Read
4
0
3
1
2
REGISTER
1 0
Register field—Specifies the address register containing the effective address for the instruction.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-71
Supervisor (Privileged) Instructions
PTEST
Test a Logical Address
(MC68EC040)
PTEST
Operation:
Assembler
Syntax:
Attributes:
If Supervisor State
Then No Operation, Possibly Run Extraneous Bus Cycles
Else TRAP
PTESTR (An)
PTESTW (An)
Unsized
Description: This instruction must not be executed on an MC68EC040. This instruction may cause extraneous bus cycles to occur and may result in unexpected exception types.
Instruction Format:
15
1
14
1
13
1
12
1
11
0
10
1
9
0
8
1
7
0
6
1
5
R/ W
Instruction Fields:
R/W field—Specifies simulating a read or write bus transfer.
0—Write
1—Read
4
0
3
1
2
REGISTER
1 0
Register field—Specifies the address register containing the effective address for the instruction.
6-72 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PTEST
Get Information About Logical Address
PTEST
(MC68851)
Operation:
Assembler
Syntax:
Attributes:
If Supervisor State
Then Information About Logical Address
→
PSTATUS
Else TRAP
PTESTR FC, < ea > ,# < level > ,(An)
PTESTW FC, < ea > ,# < level > ,(An)
Unsized
Description: If the E-bit of the translation control register is set, information about the logical address specified by FC and < ea > is placed in the PMMU status register. If the E-bit of the translation control register is clear, this instruction will cause a paged memory management unit illegal operation exception (vector $39).
The function code for this operation may be specified as follows:
1. Immediate—The function code is four bits in the command word.
2. Data Register—The function code is in the lower four bits in the MC68020 data register specified in the instruction.
3. Source Function Code (SFC) Register—The function code is in the SFC register in the CPU. Since the SFC of the MC68020 has only three implemented bits, only function codes $0D$7 can be specified in this manner.
4. Destination Function Code (DFC) Register—The function code is in the DFC register in the CPU. Since the DFC of the MC68020 has only three implemented bits, only function codes $0D$7 can be specified in this manner.
The effective address field specifies the logical address to be tested.
The # < level > parameter specifies the depth to which the translation table is to be searched. A value of zero specifies a search of the address translation cache only. Values 1–7 cause the address translation cache to be ignored and specify the maximum number of descriptors to fetch.
NOTE
Finding an address translation cache entry with < level > set to zero may result in a different value in the PMMU status register than forcing a table search. Only the I, W, G, M, and C bits of the
PMMU status register are always the same in both cases.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-73
Supervisor (Privileged) Instructions
PTEST
Get Information About Logical Address
PTEST
(MC68851)
Either PTESTR or PTESTW must be specified. These two instructions differ in the setting of the A-bit of the PMMU status register. For systems where access levels are not in use, either PTESTR or PTESTW may be used. U and M bits in the translation table are not modified by this instruction.
If there is a specified address register parameter, the physical address of the last successfully fetched descriptor is loaded into the address register. A descriptor is successfully fetched if all portions of the descriptor can be read by the MC68851 without abnormal termination of the bus cycle. If the DT field of the root pointer used indicates page descriptor, the returned address is $0.
The PTEST instruction continues searching the translation tables until reaching the requested level or until a condition occurs that makes further searching impossible (i.e., a DT field set to invalid, a limit violation, or a bus error from memory). The information in the PMMU status register reflects the accumulated values.
PMMU Status Register:
Bus Error (B)—Set if a bus error was received during a descriptor fetch, or if < level >
= 0 and an entry was found in the address translation cache with its BERR bit set; cleared otherwise.
Limit (L)—Set if the limit field of a long descriptor was exceeded; cleared otherwise.
Supervisor Violation (S)—Set if a long descriptor indicated supervisor-only access and the < fc > parameter did not have bit 2 set; cleared otherwise.
Access Level Violation (A)—If PTESTR was specified, set if the RAL field of a long descriptor would deny access. If PTESTW was specified, set if a WAL or RAL field of a long descriptor would deny access; cleared otherwise.
Write Protection (W)—Set if the WP-bit of a descriptor was set or if a WAL field of a long descriptor would deny access; cleared otherwise.
Invalid (I)—Set if a valid translation was not available; cleared otherwise.
Modified (M)—If the tested address is found in the address translation cache, set to the value of the M-bit in the address translation cache. If the tested address is found in the translation table, set if the M-bit of the page descriptor is set; cleared otherwise.
6-74 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PTEST
Get Information About Logical Address
PTEST
(MC68851)
Gate (G)—If the tested address is found in the address translation cache, set to the value of the G-bit in the address translation cache. If the tested address is found in the translation table, set if the G-bit of the page descriptor is set; cleared otherwise.
Globally Shared (C)—Set if the address is globally shared; cleared otherwise.
Level Number (N)—Set to the number of levels searched. A value of zero indicates an early termination of the table search in the root pointer (DT = page descriptor) if the level specification was not zero. If the level specification was zero, N is always set to zero.
Instruction Format:
15
1
1
14
1
0
13
1
0
12
1
11
0
LEVEL
10
0
9
0
R/ W
8
0
7
0
A-REGISTER
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
FC
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-75
Supervisor (Privileged) Instructions
PTEST
Get Information About Logical Address
PTEST
(MC68851)
Instruction Fields:
Effective Address field—Specifies the logical address about which information is requested. Only control alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn —
An
(An)
—
Register
—
—
010 reg. number:An
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn] ,od)
([bd,An],Xn ,od)
—
—
—
—
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
—
001
—
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
—
—
—
—
—
—
—
—
—
—
NOTE
The effective address field must provide the MC68851 with the effective address of the logical address to be tested, not the effective address describing where the PTEST operand is located. For example, to test a logical address that is temporarily stored on the system stack, the instruction PTEST [(SP)] must be used since PTEST (SP) would test the mapping of the system stack (i.e., the effective address passed to the MC68851 is the effective address of the system stack, not the effective address formed by the operand located on the top of the stack).
6-76 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PTEST
Get Information About Logical Address
PTEST
(MC68851)
Level field—Specifies the depth to which the translation table should be searched.
R/W field—Specifies whether the A-bit should be updated for a read or a write.
1—Read
0—Write
A-Register field—Specifies the address register in which to load the last descriptor address.
0xxx — Do not return the last descriptor address to an address register.
1RRR — Return the last descriptor address to address register RRR.
NOTE
When the PTEST instruction specifies a level of zero, the Aregister field must be 0000. Otherwise, an F-line exception is generated.
FC field—Function code of address to test.
1DDDD — Function code is specified as four bits DDDD.
01RRR — Function code is contained in CPU data register RRR.
00000 — Function code is contained in CPU source function code register.
00001 — Function code is contained in CPU destination function code register.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-77
Supervisor (Privileged) Instructions
PTRAPcc
TRAP on PMMU Condition
PTRAPcc
(M68851)
Operation:
Assembler
Syntax:
Attributes:
If Supervisor State
Then If cc True
Then TRAP
Else TRAP
PTRAPcc
PTRAPcc.W # < data > PTRAPcc.L # < data >
Unsized or Size = (Word, Long)
Description: If the selected MC68851 condition is true, the processor initiates exception processing. The vector number is generated referencing the cpTRAPcc exception vector; the stacked program counter is the address of the next instruction. If the selected condition is not true, no operation is performed, and execution continues with the next instruction. The immediate data operand is placed in the next word(s) following the MC68851 condition and is available for user definition to be used within the trap handler. Following the condition word, there may be a user-defined data operand, specified as immediate data, to be used by the trap handler.
The condition specifier cc may specify the following conditions:
Specifier Description Condition Field
BS B set 000000
LS
SS
L set
S set
000010
000100
AS
WS
IS
GS
CS
A set
W set
I set
G set
C set
000110
001000
001010
001100
001110
PMMU Status Register: Not affected
Specifier Description Condition Field
BC B clear 000001
LC
SC
L clear
S clear
000011
000101
AC
WC
IC
GC
CC
A clear
W clear
I clear
G clear
C clear
000111
001001
001011
001101
001111
6-78 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PTRAPcc
TRAP on PMMU Condition
PTRAPcc
(M68851)
Instruction Format:
15
1
0
14
1
0
13
1
0
12
1
11
0
10
0
9
0
8
0
7
0
6
1
5
1
4
1
3
1
2
0 0 0 0 0 0 0 MC68851 CONDITION
16-BIT OPERAND OR MOST SIGNIFICANT WORD OF 32-BIT OPERAND (IFNEEDED)
1
OPMODE
LEAST SIGNIFICANT WORD OF 32-BIT OPERAND (IF NEEDED)
0
Instruction Fields:
Opmode field—Selects the instruction form.
010 — Instruction is followed by one operand word.
011 — Instruction is followed by two operand words.
100 — Instruction has no following operand words.
MC68851 Condition field—Specifies the coprocessor condition to be tested. This field is passed to the MC68851, which provides directives to the main processor for processing this instruction.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-79
Supervisor (Privileged) Instructions
PVALID
Operation:
Validate a Pointer
(MC68851)
If (Source AL Bits)
→
(Destination AL Bits)
Then TRAP
PVALID
Assembler
Syntax:
Attributes:
PVALID VAL, < ea >
PVALID An, < ea >
Size = (Long)
Description: The upper bits of the source, VAL or An, compare with the upper bits of the destination, < ea > . The ALC field of the access control register defines the number of bits compared. If the upper bits of the source are numerically greater than (less privileged than) the destination, they cause a memory management access level exception. Otherwise, execution continues with the next instruction. If the MC field of the access control register = 0, then this instruction always causes a paged memory management unit access level exception.
PMMU Status Register: Not affected.
Instruction Format 1:
VAL Contains Access Level to Test Against
15
1
0
14
1
0
13
1
1
12
1
0
11
0
1
10
0
0
9
0
0
8
0
0
7
0
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
6-80 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
PVALID
Validate a Pointer
(MC68851)
PVALID
Instruction Field:
Effective Address field—Specifies the logical address to be evaluated and compared against the valid access level register. Only control alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn —
An
(An)
—
Register
—
—
010 reg. number:An
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn] ,od)
([bd,An],Xn ,od)
—
—
—
—
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
—
001
—
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
—
—
—
—
—
—
—
—
—
—
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-81
Supervisor (Privileged) Instructions
PVALID
Validate a Pointer
(MC68851)
Instruction Format 2:
Main Processor Register Contains Access Level to Test Against
PVALID
15
1
0
14
1
0
13
1
1
12
1
0
11
0
1
10
0
0
9
0
0
8
0
0
7
0
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0
REGISTER
REGISTER
0
Instruction Fields:
Effective Address field—Specifies the logical address to be evaluated and compared against specified main processor address register. Only control alterable addressing modes can be used as listed in the following table:
Addressing Mode Mode
Dn —
An
(An)
—
Register
—
—
010 reg. number:An
(An) +
—(An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An,Xn] ,od)
([bd,An],Xn ,od)
—
—
—
—
101 reg. number:An
110 reg. number:An
110
110
110 reg. number:An reg. number:An reg. number:An
Addressing Mode Mode Register
(xxx).W
111 000
(xxx).L
# < data >
111
—
001
—
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC,Xn] ,od)
([bd,PC],Xn ,od)
—
—
—
—
—
—
—
—
—
—
NOTE
The effective address field must provide the MC68851 with the effective address of the logical address to be validated, not the effective address describing where the PVALID operand is located. For example, to validate a logical address that is temporarily stored on the system stack, the instruction PVALID
VAL,[(SP)] must be used since PVALID VAL,(SP) would validate the mapping on the system stack (i.e., the effective address passed to the MC68851 is the effective address of the system stack, not the effective address formed by the operand located on the top of the stack).
Register field—Specifies the main processor address register to be used in the compare.
6-82 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
RESET
Reset External Devices
(M68000 Family)
RESET
Operation: If Supervisor State
Then Assert RESET (RSTO, MC68040 Only) Line
Else TRAP
Assembler
Syntax:
Attributes:
RESET
Unsized
Description: Asserts the RSTO signal for 512 (124 for MC68000, MC68EC000,
MC68HC000, MC68HC001, MC68008, MC68010, and MC68302) clock periods, resetting all external devices. The processor state, other than the program counter, is unaffected, and execution continues with the next instruction.
Condition Codes:
Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
0
6
1
5
1
4
1
3
0
2
0
1
0
0
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-83
Supervisor (Privileged) Instructions
RTE
Return from Exception
(M68000 Family)
RTE
Operation: If Supervisor State
Then (SP)
→
SR; SP + 2
→
SP; (SP)
→
PC; SP + 4
→
SP; Restore
State and Deallocate Stack According to (SP)
Else TRAP
Assembler
Syntax:
Attributes:
RTE
Unsized
Description: Loads the processor state information stored in the exception stack frame located at the top of the stack into the processor. The instruction examines the stack format field in the format/offset word to determine how much information must be restored.
Condition Codes:
Set according to the condition code bits in the status register value restored from the stack.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
0
6
1
5
1
4
1
Format/Offset Word (in Stack Frame):
MC68010, MC68020, MC68030, MC68040, CPU32
3
0
2
0
1
1
0
1
15 14 13
FORMAT
12 11
0
10
0
9 8 7 6 5 4
VECTOR OFFSET
3 2 1 0
Format Field of Format/Offset Word:
Contains the format code, which implies the stack frame size (including the format/ offset word). For further information, refer to Appendix B Exception Processing
Reference.
6-84 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Supervisor (Privileged) Instructions
STOP
Load Status Register and Stop
(M68000 Family)
STOP
Operation: If Supervisor State
Then Immediate Data
→
SR; STOP
Else TRAP
Assembler
Syntax:
Attributes:
STOP # < data >
Unsized
Description: Moves the immediate operand into the status register (both user and supervisor portions), advances the program counter to point to the next instruction, and stops the fetching and executing of instructions. A trace, interrupt, or reset exception causes the processor to resume instruction execution. A trace exception occurs if instruction tracing is enabled (T0 = 1, T1 = 0) when the STOP instruction begins execution. If an interrupt request is asserted with a priority higher than the priority level set by the new status register value, an interrupt exception occurs; otherwise, the interrupt request is ignored. External reset always initiates reset exception processing.
Condition Codes:
Set according to the immediate operand.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
0
IMMEDIATE DATA
6
1
5
1
4
1
3
0
2
0
Instruction Fields:
Immediate field—Specifies the data to be loaded into the status register.
1
1
0
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 6-85
Supervisor (Privileged) Instructions
6-86 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
SECTION 7
CPU32 INSTRUCTIONS
This section describes the instructions provided for the CPU32. The CPU32 can execute object code from an MC68000 and MC68010 and many of the instructions of the MC68020.
There are three new instructions provided for the CPU32: enter background mode (BGND), low-power stop (LPSTOP), and table lookup and interpolate (TBLS, TBLSN, TBLU, and
TBLUN). Table 7-1 lists the MC68020 instructions not supported by the CPU32.
Mnemonic
BFCHG
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
CALLM
CAS
CAS2 cpBcc cpDBcc cpGEN cpRESTORE cpSAVE cpScc cpTRAPcc
RTM
PACK
UNPK
Table 7-1. MC68020 Instructions Not Supported
Description
Test Bit Field and Change
Test Bit Field and Clear
Signed Bit Field Extract
Unsigned Bit Field Extract
Bit Field Find First One
Bit Field Insert
Test Bit Field and Set
Test Bit Field
CALL Module
Compare and Swap Operands
Compare and Swap Dual Operands
Branch on Coprocessor Condition
Test Coprocessor Condition Decrement and Branch
Coprocessor General Function
Coprocessor Restore Function
Coprocessor Save Function
Set on Coprocessor Condition
Trap on Coprocessor Condition
Return from Module
Pack BCD
Unpack BCD
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 7-1
CPU32 Instructions
Addressing in the CPU32 is register oriented. Most instructions allow the results of the specified operation to be placed either in a register or directly in memory. This flexibility eliminates the need for extra instructions to store register contents in memory. Table 7- 2 lists the M68000 family addressing modes with cross-references to the MC68000, MC68010,
CPU32, and MC68020. When referring to instructions in the previous sections, refer to Table
7-2 to identify the addressing modes available to the CPU32. Table 7-3 lists the instructions for the CPU32.
Table 7-2. M68000 Family Addressing Modes
Addressing Mode
Register Indirect
Address Register Indirect
Address Register Indirect with Postincrement
Address Register Indirect with Postdecrement
Address Register Indirect with Displacement
Address Register Indirect with Index
(8-Bit Displacement)
Address Register Indirect with Index
(Base Displacement)
Memory Indirect with Postincrement
Memory Indirect with Preincrement
Absolute Short
Absolute Long
Program Counter Indirect with Displacement
Program Counter Indirect with Index
(8-Bit Displacement)
Program Counter Indirect with Index
(Base Displacement)
Immediate
PC Memory Indirect with Postincrement
PC Memory Indirect with Predecrement
Syntax
Rn
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(d
8
,An,Xn
∗
SCALE)
([bd,An],Xn, od)
([bd,An],Xn, od)
(xxx).W
(xxx).L
(d
16
,PC)
(d
8
,PC,Xn)
(d
8
,PC,Xn*SC ALE)
# < data >
([bd,PC],Xn, od)
([bd,PC],Xn, od)
MC68000
MC68010 CPU32 MC68020
X X X
X
X
X
X
X
X
X
X
X
X X X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOTE: Xn,SIZE*SCALE—Denotes index register n (data or address), the index size (W for word, L for long word and scale factor (1, 2, 4, or 8 for no-word, long-word, or 8 for quad- word scaling, respectively).
X—Supported
7-2 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
CPU32 Instructions
CHK
CHK2
CLR
CMP
CMPA
CMPI
CMPM
CMP2
Mnemonic
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR
ASL, ASR
Bcc
BCHG
BCLR
BGND
BKPT
BRA
BSET
BSR
BTST
DBcc
DIVS, DIVSL
DIVU, DIVUL
EOR
EORI
EORI to CCR
EORI to SR
EXG
EXT, LSR
ILLEGAL
JMP
JSR
LEA
LINK
LPSTOP
LSL, LSR
Table 7-3. CPU32 Instruction Set
Description Description
Add Decimal with Extend
Add
Add Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
AND Immediate to Condition Code
Register
AND Immediate to Status Register
Arithmetic Shift Left and Right
Branch Conditionally
Test Bit and Change
Test Bit and Clear
Enter Background Mode
Breakpoint
Branch
Test Bit and Set
Branch to Subroutine
Test Bit
Check Register Against Bound
Check Register Against Upper and
Lower Bound
Clear
Compare
Compare Address
Compare Immediate
Compare Memory to Memory
Compare Register Against Upper and
Lower Bounds
Mnemonic
MOVE
MOVEA
MOVE from
CCR
Move from SR
MOVE to SR
MOVE USP
MOVEC
MOVEM
MOVEP
MOVEQ
MOVES
MULS
MULU
NBCD
NEG
NEGX
NOP
NOT
PEA
RESET
ROL, ROR
ROXL, ROXR
RTD
RTE
RTR
RTS
Move
Move Address
Move Condition Code Register
Move from Status Register
Move to Status Register
Move User Stack Pointer
Move Control Register
Move Multiple Registers
Move Peripheral
Move Quick
Move Alternate Address Space
Signed Multiply
Unsigned Multiply
Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement
Push Effective Address
Reset External Devices
Rotate Left and Right
Rotate with Extend Left and Right
Return and Deallocate
Return from Exception
Return and Restore Codes
Return from Subroutine
Test Condition, Decrement, and
Branch
Signed Divide
Unsigned Divide
Logical Exclusive-OR
Logical Exclusive-OR Immediate
Exclusive-OR Immediate to
Condition Code Register
Exclusive-OR Immediate to
Status Register
Exchange Registers
Sign-Extend
Take Illegal Instruction Trap
Jump
Jump to Subroutine
Load Effective Address
Link and Allocate
Low Power Stop
Logical Shift Left and Right
SBCD
Scc
STOP
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TAS
TBLS, TBLSN
TBLU, TBLUN
TRAP
TRAPcc
TRAPV
TST
UNLK
Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words
Test Operand and Set
Signed/Unsigned Table Lookup and
Interpolate
Signed/Unsigned Table Lookup and
Interpolate
Trap
Trap Conditionally
Trap an Overflow
Test Operand
Unlink
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 7-3
CPU32 Instructions
BGND
Operation:
Enter Background Mode
(CPU32)
If Background Mode Enabled
Then Enter Background Mode
Else Format/Vector Offset
→
– (SSP);
PC
SR
→
→
– (SSP)
– (SSP)
(Vector)
→
PC
BGND
Assembler
Syntax:
Attributes:
BGND
Size = (Unsized)
Description: The processor suspends instruction execution and enters background mode if background mode is enabled. The freeze output is asserted to acknowledge entrance into background mode. Upon exiting background mode, instruction execution continues with the instruction pointed to by the current program counter. If background mode is not enabled, the processor initiates illegal instruction exception processing.
The vector number is generated to reference the illegal instruction exception vector.
Refer to the appropriate user’s manual for detailed information on background mode.
Condition Codes:
X
—
N
—
Z
—
V
—
C
—
X — Not affected.
N — Not affected.
Z — Not affected.
V — Not affected.
C — Not affected.
Instruction Format:
15
0
14
1
13
0
12
0
11
1
10
0
9
1
8
0
7
1
6
1
5
1
4
1
3
1
2
0
1
1
0
0
7-4 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
CPU32 Instructions
LPSTOP
Operation:
Low-Power Stop
(CPU32)
If Supervisor State
Immediate Data
→
SR
Interrupt Mask
→
External Bus Interface (EBI)
STOP
Else TRAP
LPSTOP
Assembler
Syntax:
Attributes:
LPSTOP # < data >
Size = (Word) Privileged
Description: The immediate operand moves into the entire status register, the program counter advances to point to the next instruction, and the processor stops fetching and executing instructions. A CPU LPSTOP broadcast cycle is executed to CPU space $3 to copy the updated interrupt mask to the external bus interface (EBI). The internal clocks are stopped.
Instruction execution resumes when a trace, interrupt, or reset exception occurs. A trace exception will occur if the trace state is on when the LPSTOP instruction is executed. If an interrupt request is asserted with a higher priority that the current priority level set by the new status register value, an interrupt exception occurs; otherwise, the interrupt request is ignored. If the bit of the immediate data corresponding to the S-bit is off, execution of the instruction will cause a privilege violation. An external reset always initiates reset exception processing.
Condition Codes:
Set according to the immediate operand.
Instruction Format:
15
1
0
14
1
0
13
1
0
12
1
0
11
1
0
10
0
0
9
0
0
8
0
7
0
1 1
IMMEDIATE DATA
6
0
1
5
0
0
4
0
0
3
0
0
Instruction Fields:
Immediate field—Specifies the data to be loaded into the status register.
2
0
0
1
0
0
0
0
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 7-5
CPU32 Instructions
TBLS
TBLSN
Table Lookup and Interpolate (Signed)
(CPU32)
TBLS
TBLSN
Operation: Rounded:
ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n)) x Dx 7 – 0}
÷
256
→
Dx
Unrounded:
ENTRY(n) x 256 + {(ENTRY(n + 1) – ENTRY(n)) x Dx 7 – 0}
→
Dx
Where ENTRY(n) and ENTRY(n + 1) are either:
1. Consecutive entries in the table pointed to by the < ea > and indexed by Dx 15 – 8
π
SIZE or;
2. The registers Dym, Dyn respectively.
Assembler
Syntax:
TBLS. < size > < ea > ,Dx
TBLSN. < size > < ea > ,Dx
Result rounded
Result not rounded
TBLS. < size > Dym:Dyn, Dx Result rounded
TBLSN. < size > Dym:Dyn, Dx Result not rounded
Size = (Byte, Word, Long) Attributes:
Description: The TBLS and TBLSN instructions allow the efficient use of piecewise linear compressed data tables to model complex functions. The TBLS instruction has two modes of operation: table lookup and interpolate mode and data register interpolate mode.
For table lookup and interpolate mode, data register Dx 15 – 0 contains the independent variable X. The effective address points to the start of a signed byte, word, or long-word table containing a linearized representation of the dependent variable, Y, as a function of X. In general, the independent variable, located in the low-order word of Dx, consists of an 8-bit integer part and an 8-bit fractional part. An assumed radix point is located between bits 7 and 8. The integer part, Dx 15 – 8, is scaled by the operand size and is used as an offset into the table. The selected entry in the table is subtracted from the next consecutive entry. A fractional portion of this difference is taken by multiplying by the interpolation fraction, Dx 7 – 0 .The adjusted difference is then added to the selected table entry. The result is returned in the destination data register, Dx.
7-6 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
CPU32 Instructions
TBLS
TBLSN
Table Lookup and Interpolate (Signed)
(CPU32)
TBLS
TBLSN
For register interpolate mode, the interpolation occurs using the Dym and Dyn registers in place of the two table entries. For this mode, only the fractional portion, Dx 7 – 0, is used in the interpolation, and the integer portion, Dx 15 – 8, is ignored. The register interpolation mode may be used with several table lookup and interpolations to model multidimensional functions.
Signed table entries range from – 2 n – 1
to 2 n – 1
– 1; whereas, unsigned table entries range from 0 to 2 n – 1
where n is 8, 16, or 32 for byte, word, and long-word tables, respectively.
Rounding of the result is optionally selected via the "R" instruction field. If R = 0
(TABLE), the fractional portion is rounded according to the round-to-nearest algorithm.
The following table summerizes the rounding procedure:
Adjusted Difference
Fraction
≤
– 1/2
> – 1/2 and < 1/2
≥
1/2
Rounding
Adjustment
– 1
+ 0
+ 1
The adjusted difference is then added to the selected table entry. The rounded result is returned in the destination data register, Dx. Only the portion of the register corresponding to the selected size is affected.
BYTE
WORD
LONG
31 24
UNAFFECTED
UNAFFECTED
RESULT
23 16
UNAFFECTED
UNAFFECTED
RESULT
15
UNAFFECTED
8
RESULT
RESULT
7
RESULT
RESULT
RESULT
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 7-7
CPU32 Instructions
TBLS
TBLSN
Table Lookup and Interpolate (Signed)
(CPU32)
TBLS
TBLSN
If R = 1 (TABLENR), the result is returned in register Dx without rounding. If the size is byte, the integer portion of the result is returned in Dx 15 – 8; the integer portion of a word result is stored in Dx 23 – 8; the least significant 24 bits of a long result are stored in Dx 31 – 8. Byte and word results are sign-extended to fill the entire 32-bit register.
31 24 23 16
BYTE SIGN-EXTENDED SIGN-EXTENDED
WORD SIGN-EXTENDED RESULT
LONG RESULT RESULT
15
RESULT
RESULT
RESULT
8 7
FRACTION
FRACTION
FRACTION
0
NOTE
The long-word result contains only the least significant 24 bits of integer precision.
For all sizes, the 8-bit fractional portion of the result is returned to the low byte of the data register, Dx 7 – 0. User software can make use of the fractional data to reduce cumulative errors in lengthy calculations or implement rounding algorithms different from that provided by other forms of TBLS. The previously described assumed radix point places two restrictions on the programmer:
1. Tables are limited to 257 entries in length.
2. Interpolation resolution is limited to 1/256, the distance between consecutive table entries. The assumed radix point should not, however, be construed by the programmer as a requirement that the independent variable be calculated as a fractional number in the range 0 <
π
< 255. On the contrary, X should be considered an integer in the range 0 <
π
< 65535, realizing that the table is actually a compressed representation of a linearized function in which only every 256th value is actually stored in memory.
7-8 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
TBLS
TBLSN
Condition Codes:
X
—
N
∗
Z
∗
Table Lookup and Interpolate (Signed)
(CPU32)
V
∗
C
0
CPU32 Instructions
TBLS
TBLSN
X — Not affected.
N — Set if the most significant bit of the result is set; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if the integer portion of an unrounded long result is not in the range, – (2
23
≤
Result
≤
(2
23
) – 1; cleared otherwise.
)
C — Always cleared.
Instruction Format:
TABLE LOOKUP AND INTERPOLATE
15
1
0
15
1
0
14
1
13
1
REGISTER Dx
12
1
14
1
13
1
REGISTER Dx
12
1
11
1
1
11
1
1
10
0
R
10
0
R
9
0
0
8
0
1
7
0
6
0
5
SIZE 0
DATA REGISTER INTERPOLATE
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
9
0
0
8
0
1
7
0
SIZE
6
0
5
0
0
4
0
0
3
0
0
2 1 0
REGISTER Dym
REGISTER Dyn
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 7-9
CPU32 Instructions
TBLS TBLS
TBLSN
Table Lookup and Interpolate (Signed)
TBLSN
(CPU32)
Instruction Fields:
Effective address field (table lookup and interpolate mode only)—Specifies the destination location. Only control alterable addressing modes are allowed as listed in the following table:
Addressing Mode Mode
Dn
An
—
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
Register
—
—
—
—
—
—
100 reg. number:An
101 reg. number:An
110 reg. number:An
110 reg. number:An
Addressing Mode Mode Register
(xxx).W
(xxx).L
# < data >
111
111
—
000
001
—
(d
(d
8
16
,PC)
,PC,Xn)
(bd,PC,Xn)
111
111
111
010
011
011
Size Field—Specifies the size of operation.
00 — Byte Operation
01 — Word Operation
10 — Long Operation
Register field—Specifies the destination data register, Dx. On entry, the register contains the interpolation fraction and entry number.
Dym, Dyn field—If the effective address mode field is nonzero, this operand register is unused and should be zero. If the effective address mode field is zero, the surface interpolation variant of this instruction is implied, and Dyn specifies one of the two source operands.
Rounding mode field—The R-bit controls the rounding of the final result. When R = 0, the result is rounded according to the round-to-nearest algorithm. When R = 1, the result is returned unrounded.
7-10 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
CPU32 Instructions
TBLU TBLU
TBLUN
Table Lookup and Interpolation (Unsigned)
TBLUN
(CPU32)
Operation: Rounded:
ENTRY(n) + {(ENTRY(n + 1) – ENTRY(n)) x Dx 7 – 0}
÷
256
→
Dx
Unrounded:
ENTRY(n) x 256 + {(ENTRY(n + 1) – ENTRY(n)) x Dx 7 – 0}
→
Dx
Where ENTRY(n) and ENTRY(n + 1) are either:
1. Consecutive entries in the table pointed to by the < ea > and indexed by Dx 15 – 8
π
SIZE or;
2. The registers Dym, Dyn respectively
Assembler
Syntax:
TBLU. < size > < ea > ,Dx
TBLUN. < size > < ea > ,Dx
Result rounded
Result not rounded
TBLU. < size > Dym:Dyn, Dx Result rounded
TBLUN. < size > Dym:Dyn, Dx Result not rounded
Size = (Byte, Word, Long) Attributes:
Description: The TBLU and TBLUN instructions allow the efficient use of piecewise linear, compressed data tables to model complex functions. The TBLU instruction has two modes of operation: table lookup and interpolate mode and data register interpolate mode.
For table lookup and interpolate mode, data register Dx 15 – 0 contains the independent variable X. The effective address points to the start of a unsigned byte, word, or long-word table containing a linearized representation of the dependent variable, Y, as a function of X. In general, the independent variable, located in the loworder word of Dx, consists of an 8-bit integer part and an 8-bit fractional part. An assumed radix point is located between bits 7 and 8. The integer part, Dx 15 – 8, is scaled by the operand size and is used as an offset into the table. The selected entry in the table is subtracted from the next consecutive entry. A fractional portion of this difference is taken by multiplying by the interpolation fraction, Dx 7 – 0. The adjusted difference is then added to the selected table entry. The result is returned in the destination data register, Dx.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 7-11
CPU32 Instructions
TBLU TBLU
TBLUN
Table Lookup and Interpolation (Unsigned)
TBLUN
(CPU32)
For register interpolate mode, the interpolation occurs using the Dym and Dyn registers in place of the two table entries. For this mode, only the fractional portion, Dx 7 – 0, is used in the interpolation and the integer portion, Dx 15 – 8, is ignored. The register interpolation mode may be used with several table lookup and interpolations to model multidimensional functions.
Signed table entries range from – 2 n – 1
to 2 n – 1
– 1; whereas, unsigned table entries range from 0 to 2 n – 1
where n is 8, 16, or 32 for byte, word, and long-word tables, respectively. The unsigned and unrounded table results will be zero-extended instead of sign-extended.
Rounding of the result is optionally selected via the "R" instruction field. If R = 0
(TABLE), the fractional portion is rounded according to the round-to-nearest algorithm.
The rounding procedure can be summarized by the following table:
Adjusted Difference
Fraction
≥
1/2
< 1/2
Rounding
Adjustme nt
+ 1
+ 0
The adjusted difference is then added to the selected table entry. The rounded result is returned in the destination data register, Dx. Only the portion of the register corresponding to the selected size is affected.
BYTE
WORD
LONG
31 24
UNAFFECTED
UNAFFECTED
RESULT
23 16
UNAFFECTED
UNAFFECTED
RESULT
15
UNAFFECTED
8
RESULT
RESULT
7
RESULT
RESULT
RESULT
0
If R = 1 (TBLUN), the result is returned in register Dx without rounding. If the size is byte, the integer portion of the result is returned in Dx 15 – 8; the integer portion of a word result is stored in Dx 23 – 8; the least significant 24 bits of a long result are stored in Dx 31 – 8. Byte and word results are sign-extended to fill the entire 32-bit register.
7-12 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
CPU32 Instructions
TBLU TBLU
TBLUN
Table Lookup and Interpolation (Unsigned)
TBLUN
(CPU32)
31 24 23 16
BYTE SIGN-EXTENDED SIGN-EXTENDED
WORD SIGN-EXTENDED RESULT
LONG RESULT RESULT
15
RESULT
RESULT
RESULT
8 7
FRACTION
FRACTION
FRACTION
0
NOTE
The long-word result contains only the least significant 24 bits of integer precision.
For all sizes, the 8-bit fractional portion of the result is returned in the low byte of the data register, Dx 7 – 0. User software can make use of the fractional data to reduce cumulative errors in lengthy calculations or implement rounding algorithms different from that provided by other forms of TBLU. The previously described assumed radix point places two restrictions on the programmer:
1. Tables are limited to 257 entries in length.
2. Interpolation resolution is limited to 1/256, the distance between consecutive table entries. The assumed radix point should not, however, be construed by the programmer as a requirement that the independent variable be calculated as a fractional number in the range 0
≤
X
≤
255. On the contrary, X should be considered to be an integer in the range 0
≤
X
≤
65535, realizing that the table is actually a compressed representation of a linearized function in which only every
256th value is actually stored in memory.
Condition Codes:
X
—
N
∗
Z
∗
V
∗
C
0
X — Not affected.
N — Set if the most significant bit of the result is set; cleared otherwise.
Z — Set if the result is zero; cleared otherwise.
V — Set if the integer portion of an unrounded long result is not in the range, – (2
23
≤
Result
≤
(2
23
) – 1; cleared otherwise.
)
C — Always cleared.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 7-13
CPU32 Instructions
TBLU TBLU
TBLUN
Table Lookup and Interpolation (Unsigned)
TBLUN
(CPU32)
Instruction Format:
TABLE LOOKUP AND INTERPOLATE
15
1
0
14
1
13
1
REGISTER Dx
12
1
11
1
0
10
0
R
9
0
0
8
0
1
7
0
SIZE
6
0
0
5
0
DATA REGISTER INTERPOLATE
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
15
1
0
14
1
13
1
REGISTER Dx
12
1
11
1
0
10
0
R
9
0
0
8
0
0
7
0
SIZE
6
0
5
0
0
4
0
0
3
0
0
2 1 0
REGISTER Dym
REGISTER Dyn
Instruction Fields:
Effective address field (table lookup and interpolate mode only)—Specifies the destination location. Only control alterable addressing modes are allowed as listed in the following table:
Addressing Mode Mode
Dn
An
—
—
(An)
(An) +
– (An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
Register
—
—
010 reg. number:An
— —
100 reg. number:An
101 reg. number:An
110 reg. number:An
110 reg. number:An
Addressing Mode Mode Register
(xxx).W
(xxx).L
# < data >
111
111
—
000
001
—
(d
(d
8
16
,PC)
,PC,Xn)
(bd,PC,Xn)
111
111
111
010
011
011
Size field—Specifies the size of operation.
00 — Byte Operation
01 — Word Operation
10 — Long Operation
7-14 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
CPU32 Instructions
TBLU TBLU
TBLUN
Table Lookup and Interpolation (Unsigned)
TBLUN
(CPU32)
Register field—Specifies the destination data register, Dx. On entry, the register contains the interpolation fraction and entry number.
Dym, Dyn field—If the effective address mode field is nonzero, this operand register is unused and should be zero. If the effective address mode field is zero, the surface interpolation variant of this instruction is implied, and Dyn specifies one of the two source operands.
Rounding mode field—The R-bit controls the rounding of the final result. When R = 0, the result is rounded according to the round-to-nearest algorithm. When R = 1, the result is returned unrounded.
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 7-15
CPU32 Instructions
7-16 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
SECTION 8
INSTRUCTION FORMAT SUMMARY
This section contains a listing of the M68000 family instructions in binary format. It is listed in opcode order for the M68000 family instruction set.
8.1 INSTRUCTION FORMAT
The following paragraphs present a summary of the binary encoding fields.
8.1.1 Coprocessor ID Field
This field specifies which coprocessor in a system is to perform the operation. When using directly supported floating-point instructions for the MC68040, this field must be set to one.
8.1.2 Effective Address Field
This field specifies which addressing mode is to be used. For some operations, there are hardware-enforced restrictions on the available addressing modes allowed.
8.1.3 Register/Memory Field
This field is common to all arithmetic instructions. A zero in this field indicates a register-toregister operation, and a one indicates an < ea > -to-register operation.
8.1.4 Source Specifier Field
This field is common to all artihmetic instructions. The value of the register/memory (R/M) field affects this field,s definition. If R/M = 0, specifies the source floating-point data register
(FPDR). If R/M = 1, specifies the source operand data format.
000 — Long-Word Integer (L)
001 — Single-Precision Real (S)
010 — Extended-Precision Real (X)
011 — Packed-Decimal Real (P)
100 — Word Integer (W)
101 — Double-Precision Real (D)
110 — Byte Integer (B)
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-1
Instruction Format Summary
8.1.5 Destination Register Field
This field is common to all arithmetic instructions. It specifies the FPDR that that will be the destination. The results are always stored in this register.
8.1.6 Conditional Predicate Field
This field is common to all conditional instructions and specifies the conditional test that is to be evaluated. Table 8-1 shows the binary encodings for the conditional tests.
8.1.7 Shift and Rotate Instructions
The following paragraphs define the fields used with the shift and rotate instructions.
8.1.7.1 Count Register Field. If i/r = 0, this field contains the rotate (shift) count of 1 – 8 (a zero specifies 8). If i/r = 1, this field specifies a data register that contains the rotate (shift) count. The following shift and rotate fields are encoded as follows: dr field
0 — Rotate (shift) Right
1 — Rotate (shift) Left i/r field
0 — Immediate Rotate (shift) Count
1 — Register Rotate (shift) Count
8.1.7.2 Register Field. This field specifies a data register to be rotated (shifted).
8-2 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Format Summary
Mnemonic
F
NGL
NLE
NLT
NGE
NGT
SNE
ST
SEQ
GT
GE
LT
LE
GL
GLE
NGLE
UEQ
UGT
UGE
ULT
ULE
NE
T
SF
EQ
OGT
OGE
OLT
OLE
OGL
OR
UN
Table 8-1. Conditional Predicate Field Encoding
Conditional
Predicate
000000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
001001
001010
001011
001100
001101
001110
001111
010000
000001
000010
000011
000100
000101
000110
000111
001000
Definition
False
Equal
Ordered Greater Than
Ordered Greater Than or Equal
Ordered Less Than
Ordered Less Than or Equal
Ordered Greater Than or Less Than
Ordered
Unordered
Unordered or Equal
Unordered or Greater Than
Unordered or Greater Than or Equal
Unordered or Less Than
Unordered or Less Than or Equal
Not Equal
True
Signaling False
Signaling Equal
Greater Than
Greater Than or Equal
Less Than
Less Than or Equal
Greater Than or Less Than
Greater Than or Less Than or Equal
Not (Greater Than or Less Than or Equal)
Not (Greater Than or Less Than)
Not (Less Than or Equal)
Not (Less Than)
Not (Greater Than or Equal)
Not (Greater Than)
Signaling Not Equal
Signaling True
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-3
Instruction Format Summary
8.1.8 Size Field
This field specifies the size of the operation. The encoding is as follows:
00 — Byte Operation
01 — Word Operation
10 — Long Operation
8.1.9 Opmode Field
Refer to the applicable instruction descriptions for the encoding of this field in Section 4
Integer Instructions , Section 5 Floating Point Instructions , Section 6 Supervisor
(Privaleged) Instructions , and Section 7 CPU32 Instructions .
8.1.10 Address/Data Field
This field specifies the type of general register. The encoding is:
0 — Data Register
1 — Address Register
8.2 OPERATION CODE MAP
Table 8-2 lists the encoding for bits 15 – 12 and the operation performed.
Table 8-2. Operation Code Map
Bits 15 – 12
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Operation
Bit Manipulation/MOVEP/Immed iate
Move Byte
Move Long
Move Word
Miscellaneous
ADDQ/SUBQ/Scc/DBcc/TRAPc c
Bcc/BSR/BRA
MOVEQ
OR/DIV/SBCD
SUB/SUBX
(Unassigned, Reserved)
CMP/EOR
AND/MUL/ABCD/EXG
ADD/ADDX
Shift/Rotate/Bit Field
Coprocessor Interface/MC68040 and
CPU32 Extensions
8-4 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Format Summary
ORI to CCR
15
0
0
14
0
0
ORI to SR
13
0
0
15
0
14
0
13
0
12
0
0
11
0
0
12
0
11
0
10
0
0
10
0
9
0
0
8
0
0
7
0
9
0
8
0
7
0
16-BIT WORD DATA
6
1
6
0
ORI
15
0
14
0
13
0
12
0
11
0
16-BIT WORD DATA
10
0
9
0
8
0
7
SIZE
32-BIT LONG DATA
6
ANDI to CCR
15
0
0
14
0
0
ANDI to SR
13
0
0
15
0
14
0
13
0
12
0
0
11
0
0
12
0
11
0
10
0
0
10
0
9
1
0
8
0
0
7
0
9
1
8
0
7
0
16-BIT WORD DATA
6
1
6
0
ANDI
15
0
14
0
13
0
12
0
11
0
16-BIT WORD DATA
10
0
9
0
8
0
7
SIZE
32-BIT LONG DATA
6
5
1
4
1
3
1
8-BIT BYTE DATA
2
1
1
0
0
0
5
1
4
1
3
1
2
1
1
0
0
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE
8-BIT BYTE DATA
REGISTER
0
5
1
4
1
3
1
8-BIT BYTE DATA
2
1
1
0
0
0
5
1
4
1
3
1
2
1
1
0
0
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE
8-BIT BYTE DATA
REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-5
Instruction Format Summary
SUBI
15
0
14
0
13
0
12
0
11
0
16-BIT WORD DATA
10
1
9
0
8
0
7
SIZE
6
32-BIT LONG DATA
RTM
15
0
CALLM
14
0
13
0
12
0
11
0
10
1
9
1
8
0
7
1
6
1
15
0
0
ADDI
14
0
0
15
0
14
0
13
0
0
12
0
0
11
0
0
13
0
12
0
11
0
16-BIT WORD DATA
10
1
10
1
0
9
1
9
1
0
8
0
8
0
0
7
1
7
SIZE
6
6
1
32-BIT LONG DATA
CMP2
15
0
D/A
CHK2
14
0
13
0
REGISTER
12
0
15
0
D/A
14
0
13
0
REGISTER
12
0
11
0
1
11
0
0
10
SIZE
9
0 0
10
SIZE
9
0 0
8
0
0
8
0
0
7
1
0
7
1
0
6
1
0
6
1
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE
8-BIT BYTE DATA
REGISTER
0
5
0
4
0
3
D/A
2 1
REGISTER
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE
ARGUMENT COUNT
REGISTER
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE
8-BIT BYTE DATA
REGISTER
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
8-6 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Format Summary
EORI to CCR
15
0
0
14
0
0
EORI to SR
13
0
0
15
0
14
0
13
0
12
0
0
11
1
0
12
0
11
1
10
0
0
10
0
9
1
0
8
0
0
7
0
9
1
8
0
7
0
16-BIT WORD DATA
6
1
6
0
5
1
5
1
4
1
3
1
BYTE DATA (8 BITS)
2
1
4
1
3
1
2
1
1
0
1
0
0
0
0
0
EORI
15
0
14
0
13
0
12
0
11
1
16-BIT WORD DATA
10
0
9
1
8
0
7
SIZE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE
16-BIT BYTE DATA
REGISTER
0
32-BIT LONG DATA
CMPI
15
0
14
0
13
0
12
0
11
1
16-BIT WORD DATA
10
1
9
0
8
0
7
SIZE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE
8-BIT BYTE DATA
REGISTER
0
32-BIT LONG DATA
BTST
15
0
0
BCHG
14
0
0
13
0
0
12
BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA
11 10 9 8 7 6 5 4 3 2
EFFECTIVE ADDRESS
1
0 1 0 0 0 0 0
MODE REGISTER
0 0 0 0 0 BIT NUMBER
0
15
0
0
14
0
0
13
0
0
12
BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA
11 10 9 8 7 6 5 4 3 2
EFFECTIVE ADDRESS
1
0 1 0 0 0 0 1
MODE REGISTER
0 0 0 0 0 BIT NUMBER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-7
Instruction Format Summary
BCLR
15
0
0
BSET
14
0
0
13
0
0
12
BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA
11 10 9 8 7 6 5 4 3 2
EFFECTIVE ADDRESS
1
0 1 0 0 0 1 0
MODE REGISTER
0 0 0 0 0 BIT NUMBER
0
15
0
0
14
0
0
MOVES
13
0
0
12
BIT NUMBER STATIC, SPECIFIED AS IMMEDIATE DATA
11 10 9 8 7 6 5 4 3 2
EFFECTIVE ADDRESS
1
0 1 0 0 0 1 1
MODE REGISTER
0 0 0 0 BIT NUMBER
0
11
1 dr
10
1
0
9
1
0
8
0
0
7
SIZE
6
0 0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
15
0
A/D
CAS2
14
0
13
0
REGISTER
12
0
15
0
D/A1
D/A2
CAS
14
0
13
0
Rn1
Rn2
12
0
11
1
0
0
10
SIZE
9
0
0
0
0
8
0
7
1
Du1
Du2
6
1
0
0
5
1
0
0
4
1
0
0
3
1
2
1
1
0
Dc1
Dc2
0
0
15
0
0
BTST
14
0
0
13
0
0
12
0
0
11
1
0
10
SIZE
9
0 0
8
0
7
1
Du
6
1
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0
REGISTER
Dc
0
15
0
14
0
13
0
12
0
BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER
11 10 9 8 7 6 5 4 3 2
EFFECTIVE ADDRESS
1
REGISTER 1 0 0
MODE REGISTER
0
8-8 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Format Summary
BCHG
15
0
14
0
13
0
12
0
BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER
11 10 9 8 7 6 5 4 3 2
EFFECTIVE ADDRESS
1
REGISTER 1 0 1
MODE REGISTER
0
BCLR
15
0
14
0
13
0
12
0
BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER
11 10 9 8 7 6 5 4 3 2
EFFECTIVE ADDRESS
1
REGISTER 1 1 0
MODE REGISTER
0
BSET
15
0
14
0
13
0
12
0
BIT NUMBER DYNAMIC, SPECIFIED IN A REGISTER
11 10 9 8 7 6 5 4 3 2
EFFECTIVE ADDRESS
1
REGISTER 1 1 1
MODE REGISTER
0
MOVEP
15
0
14
0
13
0
12
0
11 10 9 8 7 6
DATA REGISTER OPMODE
16-BIT DISPLACEMENT
MOVEA
15
0
14
0
13
SIZE
12
MOVE
15
0
14
0
13
SIZE
12
MOVE from SR
15 14 13
0 1 0
12
0
11 10
DESTINATION
REGISTER
9 8
0
7
0
11 10
REGISTER
9 8
DESTINATION
7
MODE
6
11
0
10
0
9
0
8
0
7
1
6
1
6
1
5
0
4
0
3
1
2 1
ADDRESS
REGISTER
0
5 4
MODE
3 2
SOURCE
1
REGISTER
0
5 4
MODE
3 2
SOURCE
1
REGISTER
0
5 4
MODE
3 2
SOURCE
1
REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-9
Instruction Format Summary
MOVE from CCR
15 14 13 12
0 1 0 0
11
0
10
0
NEGX
15 14
0 1
13
0
12
0
11
0
10
0
CLR
15
0
14
1
13
0
12
0
MOVE to CCR
15 14 13
0 1 0
12
0
11
0
11
0
10
0
10
1
NEG
15
0
14
1
NOT
15
0
14
1
13
0
13
0
MOVE to SR
15
0
14
1
13
0
12
0
11
0
12
0
11
0
12
0
11
0
10
1
10
1
10
1
9
1
9
0
9
1
9
0
9
0
9
1
9
1
8
0
7
1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
8
0
7
SIZE1
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
8
0
7
SIZE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
8
0
7
1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
8
0
7
SIZE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
8
0
7
SIZE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
8
0
7
1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
8-10 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Format Summary
EXT, EXTB
15
0
LINK
14
1
13
0
12
0
11
1
10
0
9
0
8 7
OPMODE
6
15
0
14
1
13
0
12
0
11
1
10
0
9
0
8
0
LONG
7
0
6
0
HIGH-ORDER DISPLACEMENT
LOW-ORDER DISPLACEMENT
5
0
5
0
NBCD
15
0
14
1
SWAP
15
0
BKPT
14
1
15
0
PEA
14
1
15
0
14
1
BGND
15
0
14
1
13
0
12
0
11
1
13
0
12
0
11
1
13
0
12
0
11
1
13
0
12
0
11
1
13
0
12
0
11
1
10
0
10
0
10
0
10
0
10
0
9
0
9
0
9
1
9
0
9
0
8
0
8
0
8
0
8
0
8
0
7
0
7
0
7
1
7
0
7
0
6
1
6
0
6
1
6
1
6
1
5
1
5
0
5
0
4
0
4
0
3
1
3
0
2 1
REGISTER
0
2 1
REGISTER
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
4
0
4
0
4
1
3
1
3
0
2 1
REGISTER
0
2 1
VECTOR
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
3
1
2
0
1
1
0
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-11
Instruction Format Summary
ILLEGAL
13
0
12
0
11
1
15
0
TAS
14
1
15
0
14
1
13
0
12
0
11
1
TST
15
0
14
1
MULU
13
0
12
0
11
1
10
0
10
0
10
0
9
1
9
1
9
1
8
0
7
1
6
1
5
1
4
1
3
1
2
1
1
0
0
0
8
0
7
1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
8
0
7
SIZE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
15
0
0
MULS
14
1
13
0
REGISTER DI
12
0
11
1
0
10
1
SIZE
9
0
0
0
0
8
LONG
7
0
0
15
0
0
14
1
13
0
REGISTER DI
12
0
DIVU, DIVUL
11
1
1
10
1
SIZE
9
0
0
0
0
8
LONG
7
0
0
15
0
0
14
1
13
0
REGISTER Dq
12
0
11
1
0
10
1
SIZE
9
0
0
0
0
8
LONG
7
0
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0
REGISTER
REGISTER Dh
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0
REGISTER
REGISTER Dh
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0
REGISTER
REGISTER Dr
0
8-12 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Format Summary
DIVS, DIVSL
15
0
0
TRAP
14
1
13
0
REGISTER Dq
12
0
15
0
LINK
14
1
13
0
12
0
11
1
11
1
1
10
1
SIZE
9
0
0
10
1
9
1
15
0
14
1
13
0
12
0
11
1
10
1
8
0
0
0
8
LONG
7
0
0
7
0
9
1
8
WORD
7
0 0
WORD DISPLACEMENT
6
1
6
1
0
6
1
UNLK
15
0
14
1
MOVE USP
13
0
15
0
RESET
14
1
13
0
13
0
15
0
NOP
14
1
15
0
14
1
13
0
12
0
11
1
12
0
11
1
12
0
11
1
12
0
11
1
10
1
10
1
10
1
10
1
9
1
9
1
9
1
9
1
8
0
8
0
8
0
8
0
7
0
7
0
7
0
7
0
6
1
6
1
6
1
6
1
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0
REGISTER
REGISTER Dr
0
5
0
4
0
3 2 1
VECTOR
0
5
0
4
1
3
0
2 1
REGISTER
0
5
0
4
1
3
1
2 1
REGISTER
0
5
1
4
0
3 dr
2 1
REGISTER
0
5
1
4
1
3
0
2
0
1
0
0
0
5
1
4
1
3
0
2
0
1
0
0
1
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-13
Instruction Format Summary
STOP
15
0
14
1
13
0
12
0
11
1
10
1
9
1
8
0
7
0
IMMEDIATE DATA
6
1
RTE
15
0
RTD
14
1
15
0
14
1
13
0
12
0
11
1
13
0
12
0
11
1
10
1
10
1
9
1
8
0
7
0
9
1
8
0
7
0
16-BIT DISPLACEMENT
6
1
6
1
RTS
15
0
TRAPV
14
1
13
0
12
0
15
0
RTR
14
1
15
0
14
1
MOVEC
15
0
A/D
13
0
13
0
12
0
12
0
14
1
13
0
REGISTER
12
0
11
1
11
1
11
1
11
1
10
1
10
1
10
1
10
1
9
1
9
1
9
1
9
1
8
0
8
0
8
0
8
0
7
0
7
0
7
0
6
1
6
1
6
1
5
1
5
1
5
1
5
1
5
1
5
1
7
0
6
1
5
1
CONTROL REGISTER
4
1
4
1
4
1
4
1
4
1
4
1
4
1
3
0
2
0
1
1
0
0
3
0
2
0
1
1
0
1
3
0
2
1
1
0
0
0
3
0
2
1
1
0
0
1
3
0
2
1
1
1
0
0
3
0
2
1
1
1
0
1
3
1
2
0
1
1
0 dr
8-14 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Format Summary
JSR
15
0
14
1
JMP
15
0
14
1
MOVEM
15
0
14
1
13
0
12
0
11
1
13
0
12
0
11
1
13
0
12
0
11
1
10
1
10
1
9
1
9
1
8
0
8
0
7
1
7
1
6
1
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
10 dr
LEA
15
0
14
1
CHK
15
0
14
1
ADDQ
15
0
14
1
SUBQ
15
0
14
1
13
0
12
0
11 10
REGISTER
9
13
0
12
0
11 10
REGISTER
9
13
0
12
1
11 10
DATA
9
13
0
12
1
11 10
DATA
9
9
0
8
0
7
1
REGISTER LIST MASK
6
SIZE
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
8
1
8
0
8
1
8
SIZE
7
7
1
7
SIZE
6
7
SIZE
6
6
0
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-15
Instruction Format Summary
DBcc
15
0
14
1
13
0
12
1
11 10 9
CONDITION
8 7
1
16-BIT DISPLACEMENT
6
1
TRAPcc
15
0
14
1
13
0
12
1
11 10 9
CONDITION
8 7
1
OPTIONAL WORD
OR LONG WORD
6
1
Scc
15
0
14
1
13
0
12
1
11 10 9
CONDITION
8 7
1
6
1
BRA
15
0
14
1
13
1
12
0
5
1
5
0
4
1
4
0
3
1
3
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
11
0
10
0
9
0
8
0
7 6 5 4 3
8-BIT DISPLACEMENT
2
16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00
32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF
2 1
REGISTER
0
2 1
OPMODE
0
1 0
BSR
15
0
14
1
13
1
12
0
11
0
10
0
9
0
8
1
7 6 5 4 3
8-BIT DISPLACEMENT
2
16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00
32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF
1 0
Bcc
15
0
14
1
13
1
12
0
11 10 9
CONDITION
8 7 6 5 4 3
8-BIT DISPLACEMENT
2
16-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $00
32-BIT DISPLACEMENT IF 8-BIT DISPLACEMENT = $FF
1 0
8-16 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Format Summary
MOVEQ
15
0
14
1
DIVU, DIVUL
13
1
12
1
11 10
REGISTER
9 8
0
7 6 5 4
DATA
3 2 1 0
15
1
14
0
OR
15
1
14
0
13
0
12
0
13
0
12
0
11 10
REGISTER
9
SBCD
15
1
PACK
14
0
15
1
14
0
13
0
12
0
11 10 9
REGISTER Dy/Ay
8
1
7
0
6
0
13
0
12
0
11 10 9
REGISTER Dy/Ay
8
1
7
0
6
1
16-BIT EXTENSION: ADJUSTMENT
5
0
5
0
4
0
3
R/M
2 1 0
REGISTER Dx/Ax
4
0
3
R/M
2 1 0
REGISTER Dx/Ax
UNPK
15
1
14
0
DIVS, DIVSL
13
0
12
0
11 10 9
REGISTER Dy/Ay
8
1
7
1
6
0
16-BIT EXTENSION: ADJUSTMENT
5
0
15
1
14
0
13
0
12
0
11 10
REGISTER
9 8
WORD
7
1 1
6
1
4
0
3
R/M
2 1 0
REGISTER Dx/Ax
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
11 10
REGISTER
9
8
WORD
7
0 1
8 7
OPMODE
6
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-17
Instruction Format Summary
SUBX
13
0
12
1
11 10 9
REGISTER Dy/Ay
15
1
SUB
14
0
15
1
14
0
13
0
12
1
11 10
REGISTER
9
SUBA
15
1
14
0
CMPM
15
1
CMP
14
0
15
1
14
0
CMPA
15
1
14
0
EOR
15
1
14
0
13
0
13
1
13
1
13
1
13
1
12
1
12
1
12
1
12
1
12
1
11 10
REGISTER
9
11 10
REGISTER Ax
9
11 10
REGISTER
9
11 10
REGISTER
9
11 10
REGISTER
9
8
1
7
SIZE
6 5
0
4
0
3
R/M
2 1 0
REGISTER Dx/Ax
8 7
OPMODE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
8 7
OPMODE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
8
1
7
SIZE
6 5
0
4
0
3
1
2 1
REGISTER Ay
0
8 7
OPMODE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
8 7
OPMODE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
8 7
OPMODE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
8-18 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Format Summary
MULU
15
1
14
1
13
0
12
0
11 10
REGISTER
9
ABCD
15
1
MULS
14
1
13
0
12
0
11 10
REGISTER Rx
9
8
WORD
7
0 1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
8
1
7
0
6
0
5
0
4
0
3
R/M
2 1
REGISTER Ry
0
15
1
14
1
13
0
12
0
11 10
REGISTER
9
EXG
15
1
AND
14
1
15
1
14
1
ADDX
15
1
ADDA
14
1
15
1
14
1
13
0
12
0
11 10
REGISTER Rx
9
13
0
12
0
11 10
REGISTER
9
13
0
12
1
11 10
REGISTER Rx
9
13
0
12
1
11 10
REGISTER
9
8
WORD
7
1 1
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
8
1
7 6 5
OPMODE
4 3 2 1
REGISTER Ry
0
8 7
OPMODE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
8
1
7
SIZE
6 5
0
4
0
3
R/M
2 1
REGISTER Ry
0
8 7
OPMODE
6 5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-19
Instruction Format Summary
ADD
15
1
14
1
13
0
12
1
11 10
REGISTER
9
ASL, ASR
15
1
14
1
13
1
12
0
11
0
10
0
8 7
OPMODE
6
9
MEMORY SHIFT
8 7 6
0 dr 1 1
LSL, LSR
15
1
14
1
13
1
12
0
11
0
10
0
9
MEMORY SHIFT
8 7 6
1 dr 1 1
ROXL, ROXR
15
1
14
1
13
1
12
0
11
0
10
1
ROL, ROR
9
MEMORY ROTATE
8 7 6
0 dr 1 1
9
MEMORY ROTATE
8 7 6
1 dr 1 1
15
1
14
1
13
1
12
0
11
0
10
1
BFTST
15
1
0
14
1
0
13
1
0
12
0
0
11
1
Do
10
0
9
0
8
0
OFFSET
7
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
6
1
5
Dw
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
WIDTH
0
8-20 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Format Summary
BFEXTU
15
1
0
BFCHG
14
1
13
1
REGISTER
12
0
15
1
0
14
1
0
BFEXTS
13
1
0
12
0
0
15
1
0
BFCLR
14
1
13
1
REGISTER
12
0
15
1
0
BFFFO
14
1
0
13
1
0
12
0
0
15
1
0
BFSET
14
1
13
1
REGISTER
12
0
15
1
0
14
1
0
13
1
0
12
0
0
11
1
Do
10
0
11
1
Do
10
0
11
1
Do
10
0
11
1
Do
10
1
11
1
Do
10
1
11
1
Do
10
1
9
0
8
1
OFFSET
7
1
9
1
8
0
OFFSET
7
1
9
1
8
1
OFFSET
7
1
9
0
8
0
OFFSET
7
1
9
0
OFFSET
8
1
9
1
8
0
OFFSET
7
1
7
1
6
1
5
Dw
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
WIDTH
0
6
1
5
Dw
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
WIDTH
0
6
1
5
Dw
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
WIDTH
0
6
1
5
Dw
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
WIDTH
0
6
1
5
Dw
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
WIDTH
0
6
1
5
Dw
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
WIDTH
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-21
Instruction Format Summary
BFINS
15
1
0
14
1
13
1
REGISTER
12
0
ASL, ASR
11
1
Do
15
1
14
1
13
1
12
0
10
1
9
1
8
1
OFFSET
7
1
11 10
COUNT/
REGISTER
9
REGISTER SHIFT
8 7 6 dr SIZE
6
1
LSL, LSR
15
1
14
1
13
1
12
0
11 10
COUNT/
REGISTER
9
REGISTER SHIFT
8 7 6 dr SIZE
ROXL, ROXR
15
1
14
1
13
1
12
0
11 10
COUNT/
REGISTER
REGISTER ROTATE
9 8 7 6 dr SIZE
ROL, ROR
15
1
14
1
13
1
12
0
11 10
COUNT/
REGISTER
REGISTER ROTATE
9 8 7 6 dr SIZE
PMOVE
15
1
0
14
1
0
13
1
0
5
Dw
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
WIDTH
0
5 i/r
5 i/r
5 i/r
5 i/r
4
1
4
1
4
0
4
0
3
1
3
0
3
1
3
0
2 1
REGISTER
0
2 1
REGISTER
0
2 1
REGISTER
0
2 1
REGISTER
0
12
1
11
0
P REGISTER
10
MC68EC030, ACX REGISTERS
9 8 7 6 5
0 0
R/W
0
0
0
0
0
0 0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
8-22 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Format Summary
PMOVE
15
1
0
PLOAD
14
1
0
13
1
0
12
1
11
0
P REGISTER
MC68030 ONLY, TT REGISTERS
10 9 8 7 6 5
0 0
R/W
0
FD
0
0
0
0 0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
15
1
0
PVALID
14
1
0
15
1
0
14
1
0
PVALID
15
1
0
14
1
0
MAIN PROCESSOR REGISTER CONTAINS ACCESS LEVEL TO TEST AGAINST
13 12 11 10 9 8 7 6 5 4 3 2
EFFECTIVE ADDRESS
1
1 1 0 0 0 0 0 0
MODE REGISTER
1 0 1 0 0 0 0 0 0 0 0 REGISTER
0
PFLUSH
13
1
1
12
1
0
VAL CONTAINS ACCESS LEVEL TO TEST AGAINST
11 10 9 8 7 6 5 4 3 2
EFFECTIVE ADDRESS
1
0 0 0 0 0 0
MODE REGISTER
1 0 0 0 0 0 0 0 0 0 0
0
0
15
1
0
14
1
0
13
1
1
13
1
1
12
1
0
11
0
0
12
1
11
0
MODE
10
0
10
0
0
9
0
R/W
8
0
0
7
0
0
0
0
9
MC68030 ONLY
8 7 6
0 0 0
0 MASK
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
FC
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
FC
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-23
Instruction Format Summary
PFLUSH
PFLUSHA
PFLUSHS
15
1
0
14
1
0
12
1
11
0
MODE
10
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
FC
0
PMOVE
15
1
0
14
1
1
MC68851, TO/FROM TC, CRP, DRP, SRP, CAL, VAL, SCC, AND AC REGISTERS
13 12 11 10 9 8 7 6 5 4 3 2
EFFECTIVE ADDRESS
1
1 1 0 0 0 0 0 0
MODE REGISTER
0 P REGISTER R/W 0 0 0 0 0 0 0 0
0
0
PMOVE
13
1
1
9
0
0
MC68851
8 7
0 0
MASK
6
0
15
1
0
14
1
1
PMOVE
13
1
0
12
1
MC68030 ONLY, SRP, CRP, AND TC REGISTERS
11 10 9 8 7 6 5 4 3 2
EFFECTIVE ADDRESS
1
0 0 0 0 0 0
MODE REGISTER
P REGISTER R/W FD 0 0 0 0 0 0 0
0
0
15
1
0
14
1
1
PMOVE
13
1
1
12
1
0
11
0
0
10
0
0
MC68030 ONLY, MMUSR
9 8 7 6
0
R/W
0
0
0
0
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
15
1
0
14
1
1
13
1
1
12
1
0
11
0
0
10
0
0
MC68EC030, ACUSR
9 8 7 6
0
R/W
0
0
0
0
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
8-24 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Format Summary
PMOVE
15
1
0
PMOVE
14
1
1
13
1
1
12
1
MC68851, TO/FROM PSR AND PCSR REGISTERS
11 10 9 8 7 6 5 4 3 2
EFFECTIVE ADDRESS
1
0 0 0 0 0 0
MODE REGISTER
P REGISTER R/W 0 0 0 0 0 0 0 0
0
0
15
1
0
PTEST
14
1
1
13
1
1
12
1
MC68851, TO/FROM BAD X AND BAC X REGISTERS
11 10 9 8 7 6 5 4 3 2
EFFECTIVE ADDRESS
1
0 0 0 0 0 0
MODE REGISTER
P REGISTER R/W 0 0 0 0 NUM 0
0
0
15
1
1
PTEST
14
1
0
13
1
0
12
1
0
11
0
0
10
0
0
9
0
R/W
MC68EC030
8 7
0
0
0
6
0
REGISTER
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
FC
0
15
1
1
PTEST
14
1
0
13
1
0
12
1
11
0
LEVEL
10
0
9
MC68030 ONLY
8 7 6
0
R/W
0 0 0
A REGISTER
15
1
1
14
1
0
13
1
0
12
1
11
0
LEVEL
10
0
9
0
R/W
MC68851
8
0
7
0
A REGISTER
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE
FC
REGISTER
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
FC
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-25
Instruction Format Summary
PFLUSHR
15
1
1
PScc
15
1
0
PDBcc
14
1
0
14
1
0
13
1
0
13
1
1
12
1
0
12
1
0
11
0
0
11
0
0
10
0
0
10
0
0
9
0
0
9
0
0
8
0
0
8
0
0
7
0
0
7
0
0
6
1
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
MC68851 CONDITION
0
15
1
0
PTRAPcc
15
1
0
14
1
0
13
1
12
1
11
0
10
0
9
0
8
0
7
0
6
1
5
1
4
1
2
0 0 0 0 0 0 0 0 MC68851 CONDITION
16-BIT OPERAND OR MOST SIGNIFICANT WORD OF 32-BIT OPERAND (IF NEEDED)
LEAST SIGNIFICANT WORD OF 32-BIT OPERAND (IF NEEDED)
3
1
1
OPMODE
0
PBcc
15
1
14
1
14
1
0
13
1
0
12
1
0
11
0
0
10
0
0
9
0
8
0
7
0
0 0 0 0
16-BIT DISPLACEMENT
6
1
5
0
4
0
3
1
2 1 0
COUNT REGISTER
MC68851 CONDITION
13
1
12
1
11
0
10
0
9
0
8
0
7
1
6
SIZE
5 4 3 2
MC68851 CONDITION
1
16-BIT DISPLACEMENT OR MOST SIGNIFICANT WORD OF 32-BIT DISPLACEMENT
LEAST SIGNIFICANT WORD OF 32-BIT DISPLACEMENT (IF NEEDED)
0
PSAVE
15
1
14
1
13
1
12
1
11
0
10
0
9
0
8
1
7
0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
8-26 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Format Summary
PRESTORE
15
1
14
1
13
1
12
1
11
0
10
0
9
0
8
1
7
0
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
PFLUSH
15
1
14
1
PFLUSH
13
1
MC68EC040, POSTINCREMENT SOURCE AND DESTINATION
12 11 10 9 8 7 6 5 4 3
1 0 1 0 1 0 0 0 OPMODE
2 1
REGISTER
0
15
1
PTEST
14
1
13
1
12
1
11
0
10
1
MC68040/MC68LC040
9 8 7 6
0 1 0 0
5
0
4 3
OPMODE
2 1
REGISTER
0
15
1
PTEST
14
1
13
1
12
1
11
0
10
1
MC68040/MC68LC040
9 8 7 6
0 1 0 1
5
R/W
4
0
3
1
2 1
REGISTER
0
13
1
12
1
11
0
10
1
9
0
MC68EC040
8 7
1 0
6
1
5
R/W
4
0
3
1
2 1
REGISTER
0 15
1
CINV
14
1
15
1
CPUSH
14
1
15
1
14
1
13
1
13
1
12
1
12
1
11
0
11
0
10
1
10
1
9
0
9
0
8
0
8
0
7
CACHE
6
7
CACHE
6 5
1
5
0
4
SCOPE
3
4
SCOPE
3
2 1
REGISTER
0
2 1
REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-27
Instruction Format Summary
MOVE16
15
1
14
1
13
1
ABSOLUTE LONG ADDRESS SOURCE OR DESTINATION
12 11 10 9 8 7 6 5 4 3
1 0 1 0 OPMODE 1 0 0 0
HIGH-ORDER ADDRESS
LOW-ORDER ADDRESS
MOVE16
15
1
1
14
1
13
1
REGISTER Ay
12
1
TBLU, TBLUN
POSTINCREMENT SOURCE AND DESTINATION
11 10 9 8 7 6 5 4
0
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
3
0
0
15
1
0
14
1
13
1
REGISTER Dx
12
1
TBLS, TBLSN
2 1
REGISTER Ay
0
2 1
REGISTER Ax
0
0 0 0
11
1
0
TABLE LOOKUP AND INTERPOLATE
10 9 8 7 6 5
0
R
0
0
0
1
0
SIZE
0
0 0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
15
1
0
14
1
13
1
REGISTER Dx
12
1
TBLU, TBLUN
11
1
1
TABLE LOOKUP AND INTERPOLATE
10 9 8 7 6 5
0
R
0
0
0
1
0
SIZE
0
0
4 3 2
EFFECTIVE ADDRESS
1
MODE
0 0 0
REGISTER
0
0
0
15
1
0
14
1
13
1
REGISTER Dx
12
1
11
1
0
DATA REGISTER INTERPOLATE
10 9 8 7 6 5
0
R
0
0
0
0
0
SIZE
0 0
0
4
0
0
3
0
0
2 1 0
REGISTER Dym
REGISTER Dyn
8-28 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Format Summary
TBLS, TBLSN
15
1
0
14
1
13
1
REGISTER Dx
12
1
LPSTOP
15
1
0
14
1
0
13
1
0
12
1
0
11
1
1
11
1
0
DATA REGISTER INTERPOLATE
10 9 8 7 6 5
0
R
0
0
0
0
0
SIZE
0 0
0
10
0
0
9
0
0
8
0
7
0
1 1
IMMEDIATE DATA
6
0
1
FMOVECR
15
1
0
14
1
1
13
1
0
FINT
15
1
0
14
1
R/M
13
1
0
FSINH
15
1
0
14
1
R/M
13
1
0
FINTRZ
15
1
0
14
1
R/M
13
1
0
12
1
1
11 10 9
COPROCESSOR
ID
1 1
8
0
DESTINATION
REGISTER
7
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
6
0
6
0
0
6
0
0
6
0
0
5
0
0
5
0
4
0
0
4
0
0
3
0
0
3
0
0
4
0
3
0
ROM
OFFSET
2
0
2
0
0
2 1 0
REGISTER Dym
REGISTER Dyn
1
0
1
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 0 0 1
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 0 1 0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 0 1 1
0
0
0
0
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-29
Instruction Format Summary
FLOGNP1
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
FETOXM1
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
FTANH
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
FATAN
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
FASIN
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 1 1 0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 1 0 0 0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 1 0 0 1
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 1 0 1 0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 1 1 0 0
8-30 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Format Summary
FATANH
15
1
0
14
1
R/M
13
1
0
FSIN
15
1
0
14
1
R/M
13
1
0
FTAN
15
1
0
14
1
R/M
13
1
0
FETOX
15
1
0
14
1
R/M
13
1
0
FTWOTOX
15
1
0
14
1
R/M
13
1
0
FTENTOX
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 1 1 0 1
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 1 1 1 0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 1 1 1 1
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 0 0 0 0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 0 0 0 1
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 0 0 1 0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-31
Instruction Format Summary
FLOGN
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
FLOG10
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
FLOG2
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
FCOSH
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
FACOS
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
FCOS
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 0 1 0 0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 0 1 0 1
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 0 1 1 0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 1 0 0 1
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 1 1 0 0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 1 1 0 1
8-32 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Format Summary
FGETEXP
15
1
0
14
1
R/M
13
1
0
FGETMAN
15
1
0
14
1
R/M
13
1
0
FMOD
15
1
0
14
1
R/M
13
1
0
FSGLDIV
15
1
0
14
1
R/M
13
1
0
FREM
15
1
0
14
1
R/M
13
1
0
FSCALE
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 1 1 1 0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 1 1 1 1
6
0
0
5
1
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 0 0 1
6
0
0
5
1
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 1 0 0
6
0
0
5
1
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 1 0 1
6
0
0
5
1
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 1 1 0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-33
Instruction Format Summary
FSGLMUL
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
FSINCOS
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
FCMP
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
FTST
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
FABS
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
FADD
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
6
0
0
5
1
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 1 1 1
6
0
0
5
1
4 3 2
EFFECTIVE ADDRESS
1
MODE
1 0
REGISTER
DESTINATION
REGISTER, FPc
0
6
0
0
5
1
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 1 0 0 0
6
0
0
5
1
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
1 1 0 1 0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
OPMODE
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
OPMODE
8-34 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Format Summary
FDIV
15
1
0
14
1
R/M
13
1
0
FMOVE
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
OPMODE
12
1
DATA REGISTER, EFFECTIVE ADDRESS TO REGISTER
11 10 9
COPROCESSOR
ID
8
0
7
0
6
0
5 4
EFFECTIVE ADDRESS
MODE
3 2 1
REGISTER
SOURCE
SPECIFIER
DESTINATION
REGISTER
OPMODE
0 15
1
0
14
1
R/M
13
1
0
FMUL
15
1
0
14
1
R/M
13
1
0
FNEG
15
1
0
14
1
R/M
13
1
0
FSQRT
15
1
0
14
1
R/M
13
1
0
FSUB
15
1
0
14
1
R/M
13
1
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
12
1
11 10 9 8 7
COPROCESSOR
ID
SOURCE
SPECIFIER
0
DESTINATION
REGISTER
0
6
0
6
0
6
0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
OPMODE
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
OPMODE
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
OPMODE
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
OPMODE
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-35
Instruction Format Summary
FMOVE
15
1
0
14
1
1
13
1
1
12
1
11
DATA REGISTER, REGISTER TO MEMORY
10 9 8 7 6 5 4 3 2
EFFECTIVE ADDRESS
1
0 0 1 0 0 0
MODE REGISTER
SOURCE
SPECIFIER
DESTINATION
REGISTER
K-FACTOR
(IF REQUIRED)
0
FMOVE
15
1
1
14
1
0
13
1 dr
12
1
11 10
SYSTEM CONTROL REGISTER
9
COPROCESSOR
ID
REGISTER
SELECT
0
8
0
0
7
0
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 0 0 0
FMOVEM
15
1
1
14
1
0
13
1 dr
12
1
11 10
CONTROL REGISTERS
9
COPROCESSOR
ID
REGISTER
SELECT
0
8
0
0
7
0
0
6
0
0
5
0
4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
0 0 0 0 0
FMOVEM
15
1
1 cpGEN
14
1
1
13
1 dr
12 11 10
1
MODE
COPROCESSOR
ID
0 0
9
DATA REGISTERS
8 7 6
0
0
0 0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE
REGISTER LIST
REGISTER
0
15
1
14
1
13
1
12
1
11 10 9
COPROCESSOR
ID
8
0
7
0
6
0
5
COPROCESSOR ID-DEPENDENT COMMAND WORD
4
MODE
3 2
EFFECTIVE ADDRESS
1
REGISTER
OPTIONAL EFFECTIVE ADDRESS OR COPROCESSOR ID-DEFINED EXTENSION WORDS
0
8-36 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Format Summary
FScc
15
1
0 cpScc
14
1
0
15
1
0
14
1
0
13
1
0
12
1
0
11 10 9
COPROCESSOR
ID
0 0 0
8
0
0
7
0
0
6
1
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE
CONDITIONAL PREDICATE
REGISTER
0
FBcc
15
1
14
1
13
1
12 11 10 9 8 7 6 5 4 3 2
1
COPROCESSOR
ID
0 1 SIZE CONDITIONAL PREDICATE
16-BIT DISPLACEMENT OR MOST SIGNIFICANT WORD OF 32-BIT DISPLACEMENT
LEAST SIGNIFICANT WORD OF 32-BIT DISPLACEMENT (IF NEEDED)
1 cpBcc
15
1
14
1
13 12 11 10 9 8 7 6 5 4 3 2
EFFECTIVE ADDRESS
1
1 1
COPROCESSOR
ID
0 0 1
MODE
0 0 0 0 0 0 0 0
OPTIONAL EFFECTIVE ADDRESS OR COPROCESSOR ID-DEFINED EXTENSION WORDS
REGISTER
COPROCESSOR ID CONDITION
0
0
13
1
12
1
11 10 9
COPROCESSOR
ID
8
0
7
1
6
SIZE
5 4 3 2 1
COPROCESSOR ID CONDITION
OPTIONAL COPROCESSOR ID-DEFINED EXTENSION WORDS
WORD OR
LONG-WORD DISPLACEMENT
0 cpSAVE
15
1
14
1
FSAVE
15
1
14
1
13
1
12
1
11 10 9
COPROCESSOR
ID
13
1
12
1
11 10 9
COPROCESSOR
ID
8
1
8
1
7
0
7
0
6
0
6
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-37
Instruction Format Summary cpRESTORE
15
1
14
1
13
1
12
1
11 10 9
COPROCESSOR
ID
FRESTORE
8
1
7
0
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
15
1
14
1
13
1
12
1
11 10 9
COPROCESSOR
ID
8
1
7
0
6
1
5 4 3 2
EFFECTIVE ADDRESS
1
MODE REGISTER
0
FDBcc
15
1
0
14
1
0
13
1
0
12
1
0
11 10 9
COPROCESSOR
ID
0 0
8
0
7
0
6
1
0 0 0 0
16-BIT DISPLACEMENT
5
0
4
0
3
1
2 1
COUNT
REGISTER
CONDITIONAL PREDICATE
0 cpDBcc
15
1
0
14
1
0
13
1
0
12
1
0
11 10 9
COPROCESSOR
ID
8
0
7
0
6
1
5
0
4
0
3
1
2 1
REGISTER
0 0 0 0 0 0 COPROCESSOR ID CONDITION
OPTIONAL COPROCESSOR ID-DEFINED EXTENSION WORDS
16-BIT DISPLACEMENT
0
FTRAPcc
15
1
0
14
1
0
13
1
12
1
11 10 9
COPROCESSOR
ID
8
0
7
0
6
1
5
1
4
1
3
1
2 1
MODE
0 0 0 0 0 0 0 0 CONDITIONAL PREDICATE
16-BIT OPERAND OR MOST SIGNIFICANT WORD OF 32-BIT OPERAND (IF NEEDED)
LEAST SIGNIFICANT WORD OR 32-BIT OPERAND (IF NEEDED)
0
8-38 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Instruction Format Summary cpTRAPcc
15
1
0
14
1
0
13
1
0
12
1
0
11 10 9
COPROCESSOR
ID
8
0
7
0
6
1
5
1
4
1
3
1
2 1
OPMODE
0 0 0 0 0 0 COPROCESSOR ID CONDITION
OPTIONAL COPROCESSOR ID-DEFINED EXTENSION WORDS
OPTIONAL WORD
OR LONG-WORD OPERAND
0
FNOP
15
1
0
14
1
0
13
1
0
12
1
0
11 10 9
COPROCESSOR
ID
0 0 0
8
0
0
7
1
0
6
0
0
5
0
0
4
0
0
3
0
0
2
0
0
1
0
0
0
0
0
MOTOROLA M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL 8-39
Instruction Format Summary
8-40 M68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
APPENDIX A
PROCESSOR INSTRUCTION SUMMARY
This appendix provides a quick reference of the M68000 family instructions. The organization of this section is by processors and their addressing modes. All references to the
MC68000, MC68020, and MC68030 include references to the corresponding embedded controllers, MC68EC000, MC68EC020, and MC68EC030. All references to the MC68040 include the MC68LC040 and MC68EC040. This referencing applies throughout this section unless otherwise specified. Table A-1 lists the M68000 family instructions by mnemonic and indicates which processors they apply to.
Table A-1. M68000 Family Instruction Set And
Processor Cross-Reference
Mnemonic 68000 68008 68010 68020 68030 68040
ABCD
ADD
X
X
X
X
X
X
X
X
X
X
X
X
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR
1
ASL, ASR
Bcc
BCHG
BCLR
BFCHG
BFCLR
BFEXTS
BFEXTU
BFFFO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
68881/
68882 68851 CPU32
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL A-1
Processor Instruction Summary
Table A-1. M68000 Family Instruction Set And
Processor Cross-Reference (Continued)
68881/
68882 68851 CPU32 Mnemonic 68000 68008 68010 68020 68030 68040
BFINS
BFSET
X
X
X
X
X
X
X X X
CMPM
CMP2 cpBcc cpDBcc cpGEN cpRESTORE 1 cpSAVE 1 cpScc cpTRAPcc
CPUSH 1
DBcc
DIVS
DIVSL
DIVU
DIVUL
BFTST
BGND
BKPT
BRA
BSET
BSR
BTST
CALLM
CAS, CAS2
CHK
CHK2
CINV 1
CLR
CMP
CMPA
CMPI
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A-2 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Processor Instruction Summary
Table A-1. M68000 Family Instruction Set And
Processor Cross-Reference (Continued)
Mnemonic 68000 68008 68010 68020 68030 68040
EOR
EORI
X
X
X
X
X
X
X
X
X
X
X
X
EORI to CCR
EORI to SR 1
EXG
EXT
EXTB
FABS
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X 2
FSABS,
X 2
FDABS
FACOS
FADD
2,3
X 2
FSADD,
X 2
FDADD
FASIN
FATAN
FATANH
FBcc
2,3
2,3
2,3
FCMP
X 2
X 2
2,3 FCOS
FCOSH
FDBcc
2,3
FDIV
FSDIV, FDDIV
X 2
X 2
X 2
2,3 FETOX
FETOXM1
FGETEXP
FGETMAN
FINT
FINTRZ
FLOG10
FLOG2
FLOGN
2,3
2,3
2,3
2,3
2,3
2,3
2,3
2,3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
68881/
68882 68851 CPU32
X
X
X
X
X
X
X
X
X
X
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL A-3
Processor Instruction Summary
Table A-1. M68000 Family Instruction Set And
Processor Cross-Reference (Continued)
68881/
68882 68851 CPU32 Mnemonic 68000 68008 68010 68020 68030 68040
FLOGNP1
FMOD
2,3
2,3
FMOVE X 2
FSMOVE,
X 2
FDMOVE
FMOVECR
FMOVEM
FMUL
2,3
X 2
X 2
FSMUL,
X 2
FDMUL
FNEG
X 2
FSNEG,
X 2
FDNEG
FNOP X 2
2,3 FREM
FRESTORE 1
FSAVE*
FSCALE
FScc
X 2
X 2
2,3
X 2
2,3 FSGLDIV
FSGLMUL
FSIN
FSINCOS
FSINH
FSQRT
2,3
2,3
2,3
2,3
X 2
FSSQRT,
X 2
FDSQRT
FSUB X 2
FSSUB,
X 2
FDSUB
FTAN
FTANH
FTENTOX
FTRAPcc
FTST
2,3
2,3
2,3
X 2
X 2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A-4 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Processor Instruction Summary
Table A-1. M68000 Family Instruction Set And
Processor Cross-Reference (Continued)
Mnemonic 68000 68008 68010 68020 68030 68040
FTWOTOX
ILLEGAL X X X X X
2,3
X
MOVEC 1
MOVEM
MOVEP
MOVEQ
MOVES 1
MULS
MULU
NBCD
NEG
NEGX
NOP
NOT
OR
JMP
JSR
LEA
LINK
LPSTOP
LSL,LSR
MOVE
MOVEA
MOVE from CCR
MOVE to CCR
MOVE from SR 1
MOVE to SR 1
MOVE USP 1
MOVE16
X
X
X
X
X
X
X
X
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
68881/
68882 68851 CPU32
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL A-5
Processor Instruction Summary
Table A-1. M68000 Family Instruction Set And
Processor Cross-Reference (Continued)
ROXR
RTD
RTE 1
RTM
RTR
RTS
SBCD
Scc
STOP 1
SUB
SUBA
SUBI
SUBQ
SUBX
Mnemonic 68000 68008 68010 68020 68030 68040
ORI
ORI to CCR
X
X
X
X
X
X
X
X
X
X
X
X
ORI to SR 1
PACK
PBcc 1
PDBcc 1
PEA
PFLUSH 1
PFLUSHA 1
PFLUSHR 1
PFLUSHS 1
PLOAD 1
PMOVE 1
PRESTORE 1
PSAVE 1
PScc 1
PTEST 1
PTRAPcc 1
PVALID
RESET 1
ROL,ROR
ROXL,
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X 5
X 5
X 5
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
68881/
68882 68851 CPU32
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
A-6 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Processor Instruction Summary
Table A-1. M68000 Family Instruction Set And
Processor Cross-Reference (Concluded)
Mnemonic 68000 68008 68010 68020 68030 68040
SWAP
TAS
X
X
X
X
X
X
X
X
X
X
X
X
TBLS,
TBLSN
TBLU,
TBLUN
TRAP
TRAPcc
TRAPV
TST
UNLK
UNPK
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOTES:
1. Privileged (Supervisor) Instruction.
2. Not applicable to MC68EC040 and MC68LC040
3. These instructions are software supported on the MC68040.
4. This instruction is not privileged for the MC68000 and MC68008.
5. Not applicable to MC68EC030.
68881/
68882 68851 CPU32
X
X
X
X
X
X
X
X
X
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL A-7
Processor Instruction Summary
Table A-2 lists the M68000 family instructions by mnemonics, followed by the descriptive name.
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
BGND
BKPT
BRA
BSET
BSR
BTST
CALLM
CAS
CAS2
CHK
CHK2
CINV
CLR
CMP
CMPA
CMPI
CMPM
CMP2 cpBcc cpDBcc cpGEN cpRESTORE
Mnemonic
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR
ASL, ASR
Bcc
BCHG
BCLR
BFCHG
Table A-2. M68000 Family Instruction Set
Description
Add Decimal with Extend
Add
Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
AND Immediate to Condition Code Register
AND Immediate to Status Register
Arithmetic Shift Left and Right
Branch Conditionally
Test Bit and Change
Test Bit and Clear
Test Bit Field and Change
Test Bit Field and Clear
Signed Bit Field Extract
Unsigned Bit Field Extract
Bit Field Find First One
Bit Field Insert
Test Bit Field and Set
Test Bit Field
Enter Background Mode
Breakpoint
Branch
Test Bit and Set
Branch to Subroutine
Test Bit
CALL Module
Compare and Swap Operands
Compare and Swap Dual Operands
Check Register Against Bound
Check Register Against Upper and Lower Bounds
Invalidate Cache Entries
Clear
Compare
Compare Address
Compare Immediate
Compare Memory to Memory
Compare Register Against Upper and Lower Bounds
Branch on Coprocessor Condition
Test Coprocessor Condition Decrement and Branch
Coprocessor General Function
Coprocessor Restore Function
A-8 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Processor Instruction Summary
Table A-2. M68000 Family Instruction Set (Continued)
Mnemonic cpSAVE cpScc cpTRAPcc
CPUSH
DBcc
DIVS, DIVSL
DIVU, DIVUL
EOR
EORI
EORI to CCR
EORI to SR
EXG
EXT, EXTB
FABS
FSFABS, FDFABS
FACOS
FADD
FSADD, FDADD
FASIN
FATAN
FATANH
FBcc
FCMP
FCOS
FCOSH
FDBcc
FDIV
FSDIV, FDDIV
FETOX
FETOXM1
FGETEXP
FGETMAN
FINT
FINTRZ
FLOG10
FLOG2
FLOGN
FLOGNP1
FMOD
FMOVE
FSMOVE,FDMOVE
FMOVECR
FMOVEM
FMUL
FSMUL,FDMUL
FNEG
FSNEG,FDNEG
FNOP
Description
Coprocessor Save Function
Set on Coprocessor Condition
Trap on Coprocessor Condition
Push then Invalidate Cache Entries
Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide
Logical Exclusive-OR
Logical Exclusive-OR Immediate
Exclusive-OR Immediate to Condition Code Register
Exclusive-OR Immediate to Status Register
Exchange Registers
Sign Extend
Floating-Point Absolute Value
Floating-Point Absolute Value (Single/Double Precision)
Floating-Point Arc Cosine
Floating-Point Add
Floating-Point Add (Single/Double Precision)
Floating-Point Arc Sine
Floating-Point Arc Tangent
Floating-Point Hyperbolic Arc Tangent
Floating-Point Branch
Floating-Point Compare
Floating-Point Cosine
Floating-Point Hyperbolic Cosine
Floating-Point Decrement and Branch
Floating-Point Divide
Floating-Point Divide (Single/Double Precision)
Floating-Point ex
Floating-Point ex - 1
Floating-Point Get Exponent
Floating-Point Get Mantissa
Floating-Point Integer Part
Floating-Point Integer Part, Round-to-Zero
Floating-Point Log10
Floating-Point Log2
Floating-Point Loge
Floating-Point Loge (x + 1)
Floating-Point Modulo Remainder
Move Floating-Point Register
Move Floating-Point Register (Single/Double Precision)
Move Constant ROM
Move Multiple Floating-Point Registers
Floating-Point Multiply
Floating-Point Multiply (Single/Double Precision)
Floating-Point Negate
Floating-Point Negate (Single/Double Precision)
Floating-Point No Operation
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL A-9
Processor Instruction Summary
Table A-2. M68000 Family Instruction Set (Continued)
Mnemonic
FREM
FRESTORE
FSAVE
MOVEC
MOVEM
MOVEP
MOVEQ
MOVES
MULS
MULU
NBCD
NEG
NEGX
NOP
NOT
FSCALE
FScc
FSGLDIV
FSGLMUL
FSIN
FSINCOS
FSINH
FSQRT
FSSQRT,FDSQRT
FSUB
FSSUB,FDSUB
FTAN
FTANH
FTENTOX
FTRAPcc
FTST
FTWOTOX
ILLEGAL
JMP
JSR
LEA
LINK
LPSTOP
LSL, LSR
MOVE
MOVEA
MOVE from CCR
MOVE from SR
MOVE to CCR
MOVE to SR
MOVE USP
MOVE16
Description
IEEE Remainder
Restore Floating-Point Internal State
Save Floating-Point Internal State
Floating-Point Scale Exponent
Floating-Point Set According to Condition
Single-Precision Divide
Single-Precision Multiply
Sine
Simultaneous Sine and Cosine
Hyperbolic Sine
Floating-Point Square Root
Floating-Point Square Root (Single/Double Precision)
Floating-Point Subtract
Floating-Point Subtract (Single/Double Precision)
Tangent
Hyperbolic Tangent
Floating-Point 10x
Floating-Point Trap On Condition
Floating-Point Test
Floating-Point 2x
Take Illegal Instruction Trap
Jump
Jump to Subroutine
Load Effective Address
Link and Allocate
Low-Power Stop
Logical Shift Left and Right
Move
Move Address
Move from Condition Code Register
Move from Status Register
Move to Condition Code Register
Move to Status Register
Move User Stack Pointer
16-Byte Block Move
Move Control Register
Move Multiple Registers
Move Peripheral
Move Quick
Move Alternate Address Space
Signed Multiply
Unsigned Multiply
Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement
A-10 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Processor Instruction Summary
Table A-2. M68000 Family Instruction Set (Concluded)
Mnemonic
OR
ORI
ORI to CCR
RTS
SBCD
Scc
STOP
SUB
SUBA
SUBI
SUBQ
PVALID
RESET
ROL, ROR
ROXL, ROXR
RTD
RTE
RTM
RTR
ORI to SR
PACK
PBcc
PDBcc
PEA
PFLUSH
PFLUSHA
PFLUSHR
PFLUSHS
PLOAD
PMOVE
PRESTORE
PSAVE
PScc
PTEST
PTRAPcc
SUBX
SWAP
TAS
TBLS, TBLSN
TBLU, TBLUN
TRAP
TRAPcc
TRAPV
TST
UNLK
UNPK
Description
Logical Inclusive-OR
Logical Inclusive-OR Immediate
Inclusive-OR Immediate to Condition Code Register
Inclusive-OR Immediate to Status Register
Pack BCD
Branch on PMMU Condition
Test, Decrement, and Branch on PMMU Condition
Push Effective Address
Flush Entry(ies) in the ATCs
Flush Entry(ies) in the ATCs
Flush Entry(ies) in the ATCs and RPT Entries
Flush Entry(ies) in the ATCs
Load an Entry into the ATC
Move PMMU Register
PMMU Restore Function
PMMU Save Function
Set on PMMU Condition
Test a Logical Address
Trap on PMMU Condition
Validate a Pointer
Reset External Devices
Rotate Left and Right
Rotate with Extend Left and Right
Return and Deallocate
Return from Exception
Return from Module
Return and Restore
Return from Subroutine
Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words
Test Operand and Set
Signed Table Lookup with Interpolate
Unsigned Table Lookup with Interpolate
Trap
Trap Conditionally
Trap on Overflow
Test Operand
Unlink
Unpack BCD
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL A-11
Processor Instruction Summary
A.1 MC68000, MC68008, MC68010 PROCESSORS
The following paragraphs provide information on the MC68000, MC68008, and MC68010 instruction set and addressing modes.
A.1.1 M68000, MC68008, and MC68010 Instruction Set
Table A-3 lists the instructions used with the MC68000 and MC68008 processors, and Table
A-4 lists the instructions used with MC68010.
Table A-3. MC68000 and MC68008 Instruction Set
BSET
BSR
BTST
CHK
CLR
CMP
CMPA
CMPI
CMPM
DBcc
DIVS
DIVU
EOR
EORI
EORI to CCR
EORI to SR
EXG
EXT
ILLEGAL
JMP
JSR
Mnemonic
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR
ASL, ASR
Bcc
BCHG
BCLR
BRA
Description
Add Decimal with Extend
Add
Add Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
AND Immediate to Condition Code Register
AND Immediate to Status Register
Arithmetic Shift Left and Right
Branch Conditionally
Test Bit and Change
Test Bit and Clear
Branch
Test Bit and Set
Branch to Subroutine
Test Bit
Check Register Against Bound
Clear
Compare
Compare Address
Compare Immediate
Compare Memory to Memory
Test Condition, Decrement, and Branch
Signed Divide
Unsigned Divide
Logical Exclusive-OR
Logical Exclusive-OR Immediate
Exclusive-OR Immediate to Condition Code Register
Exclusive-OR Immediate to Status Register
Exchange Registers
Sign Extend
Take Illegal Instruction Trap
Jump
Jump to Subroutine
A-12 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Processor Instruction Summary
Table A-3. MC68000 and MC68008 Instruction Set
(Continued)
Mnemonic
LEA
LINK
LSL, LSR
SUBI
SUBQ
SUBX
SWAP
TAS
TRAP
TRAPV
TST
UNLK
RTE
RTR
RTS
SBCD
Scc
STOP
SUB
SUBA
OR
ORI
ORI to CCR
ORI to SR
PEA
RESET
ROL, ROR
ROXL, ROXR
MOVE
MOVEA
MOVE to CCR
MOVE from SR
MOVE to SR
MOVE USP
MOVEM
MOVEP
MOVEQ
MULS
MULU
NBCD
NEG
NEGX
NOP
NOT
Description
Load Effective Address
Link and Allocate
Logical Shift Left and Right
Move
Move Address
Move to Condition Code Register
Move from Status Register
Move to Status Register
Move User Stack Pointer
Move Multiple Registers
Move Peripheral
Move Quick
Signed Multiply
Unsigned Multiply
Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement
Logical Inclusive-OR
Logical Inclusive-OR Immediate
Inclusive-OR Immediate to Condition Code Register
Inclusive-OR Immediate to Status Register
Push Effective Address
Reset External Devices
Rotate Left and Right
Rotate with Extend Left and Right
Return from Exception
Return and Restore
Return from Subroutine
Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words
Test Operand and Set
Trap
Trap on Overflow
Test Operand
Unlink
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL A-13
Processor Instruction Summary
BRA
BSET
BSR
BTST
CHK
CLR
CMP
CMPA
CMPI
CMPM
DBcc
DIVS
DIVU
EOR
EORI
EORI to CCR
EORI to SR
EXG
EXT
ILLEGAL
JMP
JSR
Mnemonic
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR
ASL, ASR
Bcc
BCHG
BCLR
BKPT
Table A-4. MC68010 Instruction Set
Description
Add Decimal with Extend
Add
Add Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
AND Immediate to Condition Code Register
AND Immediate to Status Register
Arithmetic Shift Left and Right
Branch Conditionally
Test Bit and Change
Test Bit and Clear
Breakpoint
Branch
Test Bit and Set
Branch to Subroutine
Test Bit
Check Register Against Bound
Clear
Compare
Compare Address
Compare Immediate
Compare Memory to Memory
Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide
Logical Exclusive-OR
Logical Exclusive-OR Immediate
Exclusive-OR Immediate to Condition Code Register
Exclusive-OR Immediate to Status Register
Exchange Registers
Sign Extend
Take Illegal Instruction Trap
Jump
Jump to Subroutine
A-14 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Processor Instruction Summary
Mnemonic
LEA
LINK
LSL, LSR
Scc
STOP
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TAS
TRAP
TRAPV
TST
UNLK
NEGX
NOP
NOT
OR
ORI
ORI to CCR
ORI to SR
PEA
RESET
ROL, ROR
ROXL, ROXR
RTD
RTE
RTR
RTS
SBCD
MOVE
MOVEA
MOVE from CCR
MOVE from SR
MOVE to CCR
MOVE to SR
MOVE USP
MOVEC
MOVEM
MOVEP
MOVEQ
MOVES
MULS
MULU
NBCD
NEG
Table A-4. MC68010 Instruction Set (Continued)
Description
Load Effective Address
Link and Allocate
Logical Shift Left and Right
Move
Move Address
Move from Condition Code Register
Move from Status Register
Move to Condition Code Register
Move to Status Register
Move User Stack Pointer
Move Control Register
Move Multiple Registers
Move Peripheral
Move Quick
Move Address Space
Signed Multiply
Unsigned Multiply
Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement
Logical Inclusive-OR
Logical Inclusive-OR Immediate
Inclusive-OR Immediate to Condition Code Register
Inclusive-OR Immediate to Status Register
Push Effective Address
Reset External Devices
Rotate Left and Right
Rotate with Extend Left and Right
Return and Deallocate
Return from Exception
Return and Restore
Return from Subroutine
Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words
Test Operand and Set
Trap
Trap on Overflow
Test Operand
Unlink
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL A-15
Processor Instruction Summary
A.1.2 MC68000, MC68008, and MC68010 Addressing Modes
The MC68000, MC68008, and MC68010 support 14 addressing modes as shown in Table
A-5.
Table A-5. MC68000, MC68008, and MC68010
Data Addressing Modes
Generation Mode
Register Direct Addressing
Data Register Direct
Address Register Direct
Absolute Data Addressing
Absolute Short
Absolute Long
Program Counter Relative Addressing
Relative with Offset
Relative with Index and Offset
Register Indirect Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset
<ea> = Dn
<ea> = An
<ea> = (Next Word)
<ea> = (Next Two Words)
<ea> = (PC) + d
16
<ea> = (PC) + d
8
<ea> = (An)
<ea> = (An), An
¯
An + N
An
¯
An–N, <ea> = (An)
<ea> = (An) + d
16
<ea> = (An) + (Xn) + d
8
Immediate Data Addressing
Immediate
Quick Immediate
Implied Addressing
Implied Register
DATA = Next Word(s)
Inherent Data
<ea> = SR, USP, SSP, PC, VBR,
SFC, DFC
N = 1 for byte, 2 for word, and 4 for long word. If An is the stack pointer and the operand size is byte, N = 2 to keep the stack pointer on a word boundary.
A-16 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Processor Instruction Summary
A.2 MC68020 PROCESSORS
The following paragraphs provide information on the MC68020 instruction set and addressing modes.
A.2.1 MC68020 Instruction Set
Table A-6 lists the instructions used with the MC68020 processors.
Table A-6. MC68020 Instruction Set Summary
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
BKPT
BRA
BSET
BSR
BTST
CALLM
CAS
CAS2
CHK
CHK2
CLR
CMP
CMP2
CMPA
CMPI
Mnemonic
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR
ASL, ASR
Bcc
BCHG
BCLR
BFCHG
Description
Add Decimal with Extend
Add
Add Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
AND Immediate to Condition Code Register
AND Immediate to Status Register
Arithmetic Shift Left and Right
Branch Conditionally
Test Bit and Change
Test Bit and Clear
Test Bit Field and Change
Test Bit Field and Clear
Signed Bit Field Extract
Unsigned Bit Field Extract
Bit Field Find First One
Bit Field Insert
Test Bit Field and Set
Test Bit Field
Breakpoint
Branch
Test Bit and Set
Branch to Subroutine
Test Bit
CALL Module
Compare and Swap Operands
Compare and Swap Dual Operands
Check Register Against Bound
Check Register Against Upper and Lower Bounds
Clear
Compare
Compare Register Against Upper and Lower Bounds
Compare Address
Compare Immediate
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL A-17
Processor Instruction Summary
Table A-6. MC68020 Instruction Set Summary
(Continued)
CMPM
Mnemonic
MOVEQ
MOVES
MULS
MULU
NBCD
NEG
NEGX
NOP
NOT cpBcc cpDBcc cpGEN cpRESTORE cpSAVE cpScc cpTRACPcc
DBcc
DIVS, DIVSL
DIVU, DIVUL
EOR
EORI
EORI to CCR
EORI to SR
EXG
EXT, EXTB
ILLEGAL
JMP
JSR
LEA
LINK
LSL, LSR
MOVE
MOVEA
MOVE from CCR
MOVE from SR
MOVE to CCR
MOVE to SR
MOVE USP
MOVEC
MOVEM
MOVEP
Description
Compare Memory to Memory
Branch to Coprocessor Condition
Test Coprocessor Condition, Decrement and Branch
Coprocessor General Function
Coprocessor Restore Function
Coprocessor Save Function
Set on Coprocessor Condition
Trap on Coprocessor Condition
Test Condition, Decrement, and Branch
Signed Divide
Unsigned Divide
Logical Exclusive-OR
Logical Exclusive-OR Immediate
Exclusive-OR Immediate to Condition Code Register
Exclusive-OR Immediate to Status Register
Exchange Registers
Sign Extend
Take Illegal Instruction Trap
Jump
Jump to Subroutine
Load Effective Address
Link and Allocate
Logical Shift Left and Right
Move
Move Address
Move from Condition Code Register
Move from Status Register
Move to Condition Code Register
Move to Status Register
Move User Stack Pointer
Move Control Register
Move Multiple Registers
Move Peripheral
Move Quick
Move Alternate Address Space
Signed Multiply
Unsigned Multiply
Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement
A-18 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Processor Instruction Summary
Table A-6. MC68020 Instruction Set Summary
(Concluded)
Mnemonic
OR
ORI
ORI to CCR
SUBI
SUBQ
SUBX
SWAP
TAS
TRAP
TRAPcc
TRAPV
TST
UNLK
UNPK
RTM
RTR
RTS
SBCD
Scc
STOP
SUB
SUBA
ORI to SR
PACK
PEA
RESET
ROL, ROR
ROXL, ROXR
RTD
RTE
Description
Logical Inclusive-OR
Logical Inclusive-OR Immediate
Inclusive-OR Immediate to Condition Code Register
Inclusive-OR Immediate to Status Register
Pack BCD
Push Effective Address
Reset External Devices
Rotate Left and Right
Rotate with Extend Left and Right
Return and Deallocate
Return from Exception
Return from Module
Return and Restore
Return from Subroutine
Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words
Test Operand and Set
Trap
Trap Conditionally
Trap on Overflow
Test Operand
Unlink
Unpack BCD
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL A-19
Processor Instruction Summary
A.2.2 MC68020 Addressing Modes
The MC68020 supports 18 addressing modes as shown in Table A-7.
Table A-7. MC68020 Data Addressing Modes
Addressing Modes
Register Direct
Address Register Direct
Address Register Direct
Register Indirect
Address Register Indirect
Address Register Indirect with Postincrement
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
Register Indirect with Index
Address Register Indirect with Index (8-Bit Displacement)
Address Register Indirect with Index (Base Displacement)
Memory Indirect
Memory Indirect Postindexed
Memory Indirect Preindexed
Program Counter Indirect with Displacement
Program Counter Indirect with Index
PC Indirect with Index (8-Bit Displacement)
PC Indirect with Index (Base Displacement)
Program Counter Memory Indirect
PC Memory Indirect Postindexed
PC Memory Indirect Preindexed
Absolute
Absolute Short
Absolute Long
Immediate
Dn
An
(An)
(An)+
–(An)
(d
16
,An)
(xxx).W
(xxx).L
#<data>
Syntax
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An],Xn,od)
([bd,An,Xn],od)
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC],Xn,od)
([bd,PC,Xn],od)
A-20 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Processor Instruction Summary
A.3 MC68030 PROCESSORS
The following paragraphs provide information on the MC68030 instruction set and addressing modes.
A.3.1 MC68030 Instruction Set
Table A-8 lists the instructions used with the MC68030 processors.
Table A-8. MC68030 Instruction Set Summary
BRA
BSET
BSR
BTST
CAS
CAS2
CHK
CHK2
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
BKPT
CLR
CMP
CMPA
CMPI
CMPM
Mnemonic
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR
ASL, ASR
Bcc
BCHG
BCLR
BFCHG
Description
Add Decimal with Extend
Add
Add Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
AND Immediate to Condition Code Register
AND Immediate to Status Register
Arithmetic Shift Left and Right
Branch Conditionally
Test Bit and Change
Test Bit and Clear
Test Bit Field and Change
Test Bit Field and Clear
Signed Bit Field Extract
Unsigned Bit Field Extract
Bit Field Find First One
Bit Field Insert
Test Bit Field and Set
Test Bit Field
Breakpoint
Branch
Test Bit and Set
Branch to Subroutine
Test Bit
Compare and Swap Operands
Compare and Swap Dual Operands
Check Register Against Bound
Check Register Against Upper and Lower Bounds
Clear
Compare
Compare Address
Compare Immediate
Compare Memory to Memory
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL A-21
Processor Instruction Summary
Mnemonic
CMP2 cpBcc cpDBcc
MULS
MULU
NBCD
NEG
NEGX
NOP
NOT cpGEN cpRESTORE cpSAVE cpScc cpTRAPcc
DBcc
DIVS, DIVSL
DIVU, DIVUL
EOR
EORI
EORI to CCR
EORI to SR
EXG
EXT, EXTB
ILLEGAL
JMP
JSR
LEA
LINK
LSL, LSR
MOVE
MOVEA
MOVE from CCR
MOVE to CCR
MOVE from SR
MOVE to SR
MOVE USP
MOVEC
MOVEM
MOVEP
MOVEQ
MOVES
Table A-8. MC68030 Instruction Set Summary
(Continued)
Description
Compare Register Against Upper and Lower Bounds
Branch on Coprocessor Condition
Test Coprocessor Condition, Decrement and Branch
Coprocessor General Function
Coprocessor Restore Function
Coprocessor Save Function
Set on Coprocessor Condition
Trap on Coprocessor Condition
Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide
Logical Exclusive-OR
Logical Exclusive-OR Immediate
Exclusive-OR Immediate to Condition Code Register
Exclusive-OR Immediate to Status Register
Exchange Registers
Sign Extend
Take Illegal Instruction Trap
Jump
Jump to Subroutine
Load Effective Address
Link and Allocate
Logical Shift Left and Right
Move
Move Address
Move from Condition Code Register
Move to Condition Code Register
Move from Status Register
Move to Status Register
Move User Stack Pointer
Move Control Register
Move Multiple Registers
Move Peripheral
Move Quick
Move Alternate Address Space
Signed Multiply
Unsigned Multiply
Negate Decimal with Extend
Negate
Negate with Extend
No Operation
Logical Complement
A-22 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Processor Instruction Summary
Table A-8. MC68030 Instruction Set Summary
(Concluded)
SBCD
Scc
STOP
SUB
SUBA
SUBI
SUBQ
SUBX
PTEST
RESET
ROL, ROR
ROXL, ROXR
RTD
RTE
RTR
RTS
SWAP
TAS
TRAP
TRAPcc
TRAPV
TST
UNLK
UNPK
Mnemonic
NBCD
NEG
NEGX
NOP
NOT
OR
ORI
ORI to CCR
ORI to SR
PACK
PEA
PFLUSH*
PFLUSHA*
PLOAD*
PMOVE
Negate Decimal with Extend
Description
Negate
Negate with Extend
No Operation
Logical Complement
Logical Inclusive-OR
Logical Inclusive-OR Immediate
Inclusive-OR Immediate to Condition Code Register
Inclusive-OR Immediate to Status Register
Pack BCD
Push Effective Address
Invalidate Entries in the ATC
Invalidate all Entries in the ATC
Load an Entry into the ATC
Move PMMU Register
Get Information about Logical Address
Reset External Devices
Rotate Left and Right
Rotate with Extend Left and Right
Return and Deallocate
Return from Exception
Return and Restore
Return from Subroutine
Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words
Test Operand and Set
Trap
Trap Conditionally
Trap on Overflow
Test Operand
Unlink
Unpack BCD
*Not applicable to the MC68EC030
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL A-23
Processor Instruction Summary
A.3.2 MC68030 Addressing Modes
The MC68030 supports 18 addressing modes as shown in Table A-9.
Table A-9. MC68030 Data Addressing Modes
Addressing Modes
Register Direct
Data Register Direct
Address Register Direct
Register Indirect
Address Register Indirect
Address Register Indirect with Postincrement
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
Register Indirect with Index
Address Register Indirect with Index (8-Bit Displacement)
Address Register Indirect with Index (Base Displacement)
Memory Indirect
Memory Indirect Postindexed
Memory Indirect Preindexed
Program Counter Indirect with Displacement
Program Counter Indirect with Index
PC Indirect with Index (8-Bit Displacement)
PC Indirect with Index (Base Displacement)
Program Counter Memory Indirect
PC Memory Indirect Postindexed
PC Memory Indirect Preindexed
Absolute
Absolute Short
Absolute Long
Immediate
Dn
An
(An)
(An)+
–(An)
(d
16
,An)
(xxx).W
(xxx).L
#<data>
Syntax
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An],Xn,od)
([bd,An,Xn],od)
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC],Xn,od)
([bd,PC,Xn],od)
A-24 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Processor Instruction Summary
A.4 MC68040 PROCESSORS
The following paragraphs provide information on the MC68040 instruction set and addressing modes.
A.4.1 MC68040 Instruction Set
Table A-10 lists the instructions used with the MC68040 processor.
BRA
BSET
BSR
BTST
CAS
CAS2
CHK
CHK2
BFCLR
BFEXTS
BFEXTU
BFFFO
BFINS
BFSET
BFTST
BKPT
CINV
CLR
CMP
CMPA
Mnemonic
ABCD
ADD
ADDA
ADDI
ADDQ
ADDX
AND
ANDI
ANDI to CCR
ANDI to SR
ASL, ASR
Bcc
BCHG
BCLR
BFCHG
Table A-10. MC68040 Instruction Set
Description
Add Decimal with Extend
Add
Add Address
Add Immediate
Add Quick
Add with Extend
Logical AND
Logical AND Immediate
AND Immediate to Condition Code Register
AND Immediate to Status Register
Arithmetic Shift Left and Right
Branch Conditionally
Test Bit and Change
Test Bit and Clear
Test Bit Field and Change
Test Bit Field and Clear
Signed Bit Field Extract
Unsigned Bit Field Extract
Bit Field Find First One
Bit Field Insert
Test Bit Field and Set
Test Bit Field
Breakpoint
Branch
Test Bit and Set
Branch to Subroutine
Test Bit
Compare and Swap Operands
Compare and Swap Dual Operands
Check Register Against Bound
Check Register Against Upper and Lower Bounds
Invalidate Cache Entries
Clear
Compare
Compare Address
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL A-25
Processor Instruction Summary
Table A-10. MC68040 Instruction Set (Continued)
CMPI
CMPM
Mnemonic
CMP2
CPUSH
DBcc
DIVS, DIVSL
DIVU, DIVUL
EOR
EORI
EORI to CCR
EORI to SR
EXG
EXT, EXTB
FABS
1
FSABS, FDABS
1
FACOS
1,2
FADD
1
FSADD, FDADD
1
FASIN
1,2
FATAN
1,2
FATANH
1,2
FBcc
1
FCMP
1
FCOS
1,2
FCOSH
1,2
FDBcc
1
FDIV
1
FSDIV, FDDIV
1
FETOX
1,2
FETOXM1
1,2
FGETEXP
1,2
FGETMAN
1,2
FINT
1,2
FINTRZ
1,2
FLOG10
1,2
FLOG2
1,2
FLOGN
1,2
FLOGNP1
1,2
FMOD
1,2
FMOVE
1
FSMOVE, FDMOVE
1
FMOVECR
1
FMOVEM
1
FMUL
1
FSMUL, FDMUL
1
Description
Compare Immediate
Compare Memory to Memory
Compare Register Against Upper and Lower Bounds
Push then Invalidate Cache Entries
Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide
Logical Exclusive-OR
Logical Exclusive-OR Immediate
Exclusive-OR Immediate to Condition Code Register
Exclusive-OR Immediate to Status Register
Exchange Registers
Sign Extend
Floating-Point Absolute Value
Floating-Point Absolute Value (Single/Double Precision)
Floating-Point Arc Cosine
Floating-Point Add
Floating-Point Add (Single/Double Precision)
Floating-Point Arc Sine
Floating-Point Arc Tangent
Floating-Point Hyperbolic Arc Tangent
Floating-Point Branch
Floating-Point Compare
Floating-Point Cosine
Floating-Point Hyperbolic Cosine
Floating-Point Decrement and Branch
Floating-Point Divide
Floating-Point Divide (Single/Double Precision)
Floating-Point e x
Floating-Point e x
- 1
Floating-Point Get Exponent
Floating-Point Get Mantissa
Floating-Point Integer Part
Floating-Point Integer Part, Round-to-Zero
Floating-Point Log
10
Floating-Point Log
2
Floating-Point Log e
Floating-Point Log e
(x + 1)
Floating-Point Modulo Remainder
Move Floating-Point Register
Move Floating-Point Register (Single/Double Precision)
Move Constant ROM
Move Multiple Floating-Point Registers
Floating-Point Multiply
Floating-Point Multiply (Single/Double Precision)
A-26 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Processor Instruction Summary
Table A-10. MC68040 Instruction Set (Continued)
FNEG
1
Mnemonic
FSNEG, FDNEG
1
FNOP
1
FREM
1,2
FRESTORE
1
FSAVE
1
FSCALE
1,2
FScc
1
FSGLDIV
1,2
FSGLMUL
1,2
FSIN
1,2
FSINCOS
1,2
FSINH
1,2
FSQRT
1
FSSQRT, FDSQRT
1
FSUB
1
FSSUB, FDSUB
1
FTAN
1,2
FTANH
1,2
FTENTOX
1,2
FTRAPcc
1,2
FTST
1
FTWOTOX
1,2
ILLEGAL
JMP
JSR
LEA
LINK
LSL, LSR
MOVE
MOVEA
MOVE from CCR
MOVE to CCR
MOVE from SR
MOVE to SR
MOVE USP
MOVEC
MOVEM
MOVEP
MOVEQ
MOVES
MOVE16
MULS
MULU
Description
Floating-Point Negate
Floating-Point Negate (Single/Double Precision)
Floating-Point No Operation
IEEE Remainder
Restore Floating-Point Internal State
Save Floating-Point Internal State
Floating-Point Scale Exponent
Floating-Point Set According to Condition
Single-Precision Divide
Single-Precision Multiply
Sine
Simultaneous Sine and Cosine
Hyperbolic Sine
Floating-Point Square Root
Floating-Point Square Root (Single/Double Precision)
Floating-Point Subtract
Floating-Point Subtract (Single/Double Precision)
Tangent
Hyperbolic Tangent
Floating-Point 10 x
Floating-Point Trap On Condition
Floating-Point Test
Floating-Point 2 x
Take Illegal Instruction Trap
Jump
Jump to Subroutine
Load Effective Address
Link and Allocate
Logical Shift Left and Right
Move
Move Address
Move from Condition Code Register
Move to Condition Code Register
Move from Status Register
Move to Status Register
Move User Stack Pointer
Move Control Register
Move Multiple Registers
Move Peripheral
Move Quick
Move Alternate Address Space
16-Byte Block Move
Signed Multiply
Unsigned Multiply
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL A-27
Processor Instruction Summary
Table A-10. MC68040 Instruction Set (Concluded)
STOP
SUB
SUBA
SUBI
SUBQ
SUBX
SWAP
TAS
ROL, ROR
ROXL, ROXR
RTD
RTE
RTR
RTS
SBCD
Scc
TRAP
TRAPcc
TRAPV
TST
UNLK
UNPK
Mnemonic
NBCD
NEG
NEGX
NOP
NOT
OR
ORI
ORI to CCR
ORI to SR
PACK
PEA
PFLUSH
PFLUSHA
PTEST
RESET
Negate Decimal with Extend
Description
Negate
Negate with Extend
No Operation
Logical Complement
Logical Inclusive-OR
Logical Inclusive-OR Immediate
Inclusive-OR Immediate to Condition Code Register
Inclusive-OR Immediate to Status Register
Pack BCD
Push Effective Address
Flush Entry(ies) in the ATCs
Flush all Entry(ies) in the ATCs
Test a Logical Address
Reset External Devices
Rotate Left and Right
Rotate with Extend Left and Right
Return and Deallocate
Return from Exception
Return and Restore
Return from Subroutine
Subtract Decimal with Extend
Set Conditionally
Stop
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
Swap Register Words
Test Operand and Set
Trap
Trap Conditionally
Trap on Overflow
Test Operand
Unlink
Unpack BCD
NOTES:
1. Not applicable to the MC68EC040 and MC68LC040.
2. These instructions are software supported.
A-28 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Processor Instruction Summary
A.4.2 MC68040 Addressing Modes
The MC68040 supports 18 addressing modes as shown in Table A-11.
Table A-11. MC68040 Data Addressing Modes
Addressing Modes
Register Direct
Data Register Direct
Address Register Direct
Register Indirect
Address Register Indirect
Address Register Indirect with Postincrement
Address Register Indirect with Predecrement
Address Register Indirect with Displacement
Register Indirect with Index
Address Register Indirect with Index (8-Bit Displacement)
Address Register Indirect with Index (Base Displacement)
Memory Indirect
Memory Indirect Postindexed
Memory Indirect Preindexed
Program Counter Indirect with Displacement
Program Counter Indirect with Index
PC Indirect with Index (8-Bit Displacement)
PC Indirect with Index (Base Displacement)
Program Counter Memory Indirect
PC Memory Indirect Postindexed
PC Memory Indirect Preindexed
Absolute
Absolute Short
Absolute Long
Immediate
Syntax
Dn
An
(An)
(An) +
–(An)
(d
16
,An)
(d
8
,An,Xn)
(bd,An,Xn)
([bd,An],Xn,od)
([bd,An,Xn],od)
(d
16
,PC)
(d
8
,PC,Xn)
(bd,PC,Xn)
([bd,PC],Xn,od)
([bd,PC,Xn],od) xxx.W xxx.L
# < data >
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL A-29
Processor Instruction Summary
A.5 MC68881/MC68882 COPROCESSORS
The following paragraphs provide information on the MC68881/MC68882 instruction set and addressing modes.
A.5.1 MC68881/MC68882 Instruction Set
Table A-12 lists the instructions used with the MC68881/MC68882 coprocessors.
Mnemonic
FABS
FACOS
FADD
FLOG2
FLOGN
FLOGNP1
FMOD
FMOVE
FMOVECR
FMOVEM
FMUL
FNEG
FNOP
FREM
FRESTORE
FSAVE
FSCALE
FScc
FSGLDIV
FSGLMUL
FSIN
FSINCOS
FSINH
FASIN
FATAN
FATANH
FBcc
FCMP
FCOS
FCOSH
FDBcc
FDIV
FETOX
FETOXM1
FGETEXP
FGETMAN
FINT
FINTRZ
FLOG10
Table A-12. MC68881/MC68882 Instruction Set
Description
Floating-Point Absolute Value
Floating-Point Arc Cosine
Floating-Point Add
Floating-Point Arc Sine
Floating-Point Arc Tangent
Floating-Point Hyperbolic Arc Tangent
Floating-Point Branch
Floating-Point Compare
Floating-Point Cosine
Floating-Point Hyperbolic Cosine
Floating-Point Decrement and Branch
Floating-Point Divide
Floating-Point ex
Floating-Point ex - 1
Floating-Point Get Exponent
Floating-Point Get Mantissa
Floating-Point Integer Part
Floating-Point Integer Part, Round-to-Zero
Floating-Point Log10
Floating-Point Log2
Floating-Point Loge
Floating-Point Loge (x + 1)
Floating-Point Modulo Remainder
Move Floating-Point Register
Move Constant ROM
Move Multiple Floating-Point Registers
Floating-Point Multiply
Floating-Point Negate
Floating-Point No Operation
IEEE Remainder
Restore Floating-Point Internal State
Save Floating-Point Internal State
Floating-Point Scale Exponent
Floating-Point Set According to Condition
Single-Precision Divide
Single-Precision Multiply
Sine
Simultaneous Sine and Cosine
Hyperbolic Sine
A-30 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Processor Instruction Summary
Mnemonic
FSQRT
FSUB
FTAN
FTANH
FTENTOX
FTRAPcc
FTST
FTWOTOX
Table A-12. MC68881/MC68882 Instruction Set
Description
Floating-Point Square Root
Floating-Point Subtract
Tangent
Hyperbolic Tangent
Floating-Point 10x
Floating-Point Trap On Condition
Floating-Point Test
Floating-Point 2x
A.5.2 MC68881/MC68882 Addressing Modes
The MC68881/MC68882 does not perform address calculations. When the floating-point coprocessor instructs the processor to transfer an operand via the coprocessor interface, the processor performs the addressing mode calculation requested in the instruction.
A.6 MC68851 COPROCESSORS
The following paragraphs provide information on the MC68851 instruction set and addressing modes.
A.6.1 MC68851 Instruction Set
Table A-13 lists the instructions used with the MC68851 coprocessor.
Mnemonic
PBcc
PDBcc
PFLUSH
PFLUSHA
PFLUSHR
PFLUSHS
PLOAD
PMOVE
PRESTORE
PSAVE
PScc
PTEST
PTRAPcc
PVALID
Table A-13. MC68851 Instruction Set
Branch on PMMU Condition
Description
Test, Decrement, and Branch on PMMU Condition
Flush Entry(ies) in the ATCs
Flush Entry(ies) in the ATCs
Flush Entry(ies) in the ATCs and RPT Entries
Flush Entry(ies) in the ATCs
Load an Entry into the ATC
Move PMMU Register
PMMU Restore Function
PMMU Save Function
Set on PMMU Condition
Test a Logical Address
Trap on PMMU Condition
Validate a Pointer
A.6.2 MC68851 Addressing Modes
The MC68851 supports the same addressing modes as the MC68020 (see Table A-7).
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL A-31
APPENDIX B
EXCEPTION PROCESSING REFERENCE
This appendix provides a quick reference for system programmers who are already familiar with the stack frames. For more detail, please refer to the appropriate userOs manual.
B.1 EXCEPTION VECTOR ASSIGNMENTS FOR THE M68000 FAMILY
Table B-1 lists all vector assignments up to and including the MC68040 and its derivatives.
Many of these vector assignments are processor specific. For instance, vector 13, the coprocessor protocol violation vector, only applies to the MC68020, MC68EC020,
MC68030, and MC68EC030. Refer to the appropriate user’s manual to determine which exception type is applicable to a specific processor.
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL B-1
Exception Processing Reference
Table B-1. Exception Vector Assignments for the M68000 Family
Vector
Offset (Hex)
000
080–0BC
0C0
0C4
0C8
0CC
0D0
0D4
0D8
060
064
068
06C
070
074
078
07C
024
028
02C
030
034
038
03C
040–05C
004
008
00C
010
014
018
01C
020
0DC
0E0
0E4
0E8
0ECD0FC
100D3FC
Vector
Number( s)
0
32–47
48
49
50
51
52
53
54
28
29
30
31
24
25
26
27
9
10
11
12
13
14
15
16–23
7
8
5
6
3
4
1
2
55
56
57
58
59–63
64–255
Assignment
Reset Initial Interrupt Stack Pointer
Reset Initial Program Counter
Access Fault
Address Error
Illegal Instruction
Integer Divide by Zero
CHK, CHK2 Instruction
FTRAPcc, TRAPcc, TRAPV Instructions
Privilege Violation
Trace
Line 1010 Emulator (Unimplemented A- Line Opcode)
Line 1111 Emulator (Unimplemented F-Line Opcode)
(Unassigned, Reserved)
Coprocessor Protocol Violation
Format Error
Uninitialized Interrupt
(Unassigned, Reserved)
Spurious Interrupt
Level 1 Interrupt Autovector
Level 2 Interrupt Autovector
Level 3 Interrupt Autovector
Level 4 Interrupt Autovector
Level 5 Interrupt Autovector
Level 6 Interrupt Autovector
Level 7 Interrupt Autovector
TRAP #0 D 15 Instruction Vectors
FP Branch or Set on Unordered Condition
FP Inexact Result
FP Divide by Zero
FP Underflow
FP Operand Error
FP Overflow
FP Signaling NAN
FP Unimplemented Data Type (Defined for MC68040)
MMU Configuration Error
MMU Illegal Operation Error
MMU Access Level Violation Error
(Unassigned, Reserved)
User Defined Vectors (192)
B-2 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Exception Processing Reference
B.2 EXCEPTION STACK FRAMES
Figures B-1 through B-15 illustrate all exception stack frames for the M68000 family..
SP
7
15
ODD BYTE EVEN BYTE
0 7
STATUS REGISTER
PROGRAM COUNTER HIGH
PROGRAM COUNTER LOW
0
0
HIGHER
ADDRESS
Figure B-1. MC68000 Group 1 and 2 Exception Stack Frame
LOWER
ADDRESS
15 5 4 3 2
ACCESS ADDRESS
R/W I/N FUNCTION CODE
HIGH
LOW
PROGRAM COUNTER
INSTRUCTION REGISTER
STATUS REGISTER
HIGH
0
LOW
R/W (READ/WRITE): WRITE = 0, READ = 1. I/N
(INSTRUCTION/NOT): INSTRUCTION = 0, NOT = 1.
Figure B-2. MC68000 Bus or Address Error Exception Stack Frame
SP
+$02
+$06
15
0 0 0 0
STATUS REGISTER
PROGRAM COUNTER
VECTOR OFFSET
0
Figure B-3. Four-Word Stack Frame, Format $0
SP
+$02
+$06
15
0 0 0 1
STATUS REGISTER
PROGRAM COUNTER
VECTOR OFFSET
0
Figure B-4. Throwaway Four-Word Stack Frame, Format $1
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL B-3
Exception Processing Reference
SP
+$02
+$06
+$08
15
0 0 1 0
STATUS REGISTER
PROGRAM COUNTER
VECTOR OFFSET
ADDRESS
0
Figure B-5. Six-Word Stack Frame, Format $2
SP
+$02
+$06
+$08
15
0 0 1 0
STATUS REGISTER
PROGRAM COUNTER
VECTOR OFFSET
EFFECTIVE ADDRESS
0
Figure B-6. MC68040 Floating-Point Post-Instruction Stack Frame, Format $3
B-4 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Exception Processing Reference
SP
+$02
+$06
+$08
15
0 1 0 0
STATUS REGISTER
PROGRAM COUNTER
VECTOR OFFSET
EFFECTIVE ADDRESS (EA)
+$0C PC OF FAULTED
INSTRUCTION
0
Figure B-7. MC68EC040 and MC68LC040 Floating-Point Unimplemented Stack
Frame, Format $4
SP
+$02
+$06
+$08
+$0A
+$0C
+$0E
+$10
+$12
+$14
15 0
STATUS REGISTER
PROGRAM COUNTER
0 1 1 1
$00
$00
$00
VECTOR OFFSET
EFFECTIVE ADDRESS (EA)
SPECIAL STATUS WORD
WRITEBACK 3 STATUS (WB3S)
WRITEBACK 2 STATUS (WB2S)
WRITEBACK 1 STATUS (WB1S)
FAULT ADDRESS (FA)
+$18
WRITEBACK 3 ADDRESS (WB3A)
+$1C
WRITEBACK 3 DATA (WB3D)
+$20
WRITEBACK 2 ADDRESS (WB2A)
+$24
WRITEBACK 2 DATA (WB2D)
+$28
WRITEBACK 1 ADDRESS (WB1A)
+$2C
WRITEBACK 1 DATA/PUSH DATA LW0 (WB1D/PD0)
+$30
PUSH DATA LW 1 (PD1)
+$34
PUSH DATA LW 2 (PD2)
+$38
PUSH DATA LW 3 (PD3)
Figure B-8. MC68040 Access Error Stack Frame, Format $7
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL B-5
Exception Processing Reference
SP
+$02
+$06
+$08
+$0C
+$10
+$14
+$16
+$18
$1A
+$50
15
STATUS REGISTER
PROGRAM COUNTER HIGH
PROGRAM COUNTER LOW
1 0 0 0 VECTOR OFFSET
SPECIAL STATUS WORD
FAULT ADDRESS HIGH
FAULT ADDRESS LOW
UNUSED, RESERVED
DATA OUTPUT BUFFER
UNUSED, RESERVED
DATA INPUT BUFFER
UNUSED, RESERVED
INSTRUCTION OUTPUT BUFFER
|VERSION|
|NUMBER|
INTERNAL INFORMATION, 16 WORDS
0
NOTE: The stack pointer decrements by 29 words, although only 26 words of information actually write to memory. Motorola reserves the three additional words for future use.
Figure B-9. MC68010 Bus and Address Error Stack Frame, Format $8
SP
+$02
15
+$06
+$08
STATUS REGISTER
PROGRAM COUNTER
1 0 0 1 VECTOR OFFSET
INSTRUCTION ADDRESS
+$0C
INTERNAL REGISTERS
4 WORDS
+$12
0
Figure B-10. MC68020 Bus and MC68030 Coprocessor Mid-Instruction Stack Frame,
Format $9
B-6 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Exception Processing Reference
SP
+$02
+$06
+$08
+$0A
+$0C
+$0E
+$10
+$12
+$14
+$16
+$18
+$1A
+$1C
+$1E
15
STATUS REGISTER
PROGRAM COUNTER
1 0 1 0 VECTOR OFFSET
INTERNAL REGISTER
SPECIAL STATUS REGISTER
INSTRUCTION PIPE STAGE C
INSTRUCTION PIPE STATE B
DATA CYCLE FAULT ADDRESS
INTERNAL REGISTER
INTERNAL REGISTER
DATA OUTPUT BUFFER
INTERNAL REGISTER
INTERNAL REGISTER
0
Figure B-11. MC68020 and MC68030 Short Bus Cycle Stack Frame, Format $A
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL B-7
Exception Processing Reference
SP
+$02
+$06
+$08
+$0A
+$0C
+$0E
+$10
+$12
+$14
+$16
+$18
+$1A
+$1C
+$1E
15
STATUS REGISTER
PROGRAM COUNTER
1 0 1 1 VECTOR OFFSET
INTERNAL REGISTER
SPECIAL STATUS REGISTER
INSTRUCTION PIPE STAGE C
INSTRUCTION PIPE STAGE B
DATA CYCLE FAULT ADDRESS
INTERNAL REGISTER
INTERNAL REGISTER
DATA OUTPUT BUFFER
INTERNAL REGISTERS, 4 WORDS
+$22
+$24
STAGE B ADDRESS
+$28
+$2A
+$2C
INTERNAL REGISTERS, 2 WORDS
DATA INPUT BUFFER
+$30
INTERNAL REGISTERS, 3 WORDS
+$36
+$38 VERSION # INTERNAL INFORMATION
0
INTERNAL REGISTERS 18 WORDS
+$5A
Figure B-12. MC68020 and MC68030 Long Bus Cycle Stack Frame, Format $B
SP
+$02
+$06
+$08
+$0C
+$10
+$14
+$16
15
STATUS REGISTER
RETURN PROGRAM COUNTER HIGH
RETURN PROGRAM COUNTER LOW
1 1 0 0 VECTOR OFFSET
FAULTED ADDRESS HIGH
FAULTED ADDRESS LOW
DBUF HIGH
DBUF LOW
CURRENT INSTRUCTION PROG. COUNTER HIGH
CURRENT INSTRUCTION PROG. COUNTER LOW
INTERNAL TRANSFER COUNT REGISTER
0 0 SPECIAL STATUS WORD
0
Figure B-13. CPU32 Bus Error for Prefetches and Operands Stack Frame, Format $C
B-8 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Exception Processing Reference
SP
+$02
+$06
+$08
+$0C
+$10
+$14
+$16
15
STATUS REGISTER
RETURN PROGRAM COUNTER HIGH
RETURN PROGRAM COUNTER LOW
1 1 0 0 VECTOR OFFSET
FAULTED ADDRESS HIGH
FAULTED ADDRESS LOW
DBUF HIGH
DBUF LOW
CURRENT INSTRUCTION PROG. COUNTER HIGH
CURRENT INSTRUCTION PROG. COUNTER LOW
INTERNAL TRANSFER COUNT REGISTER
0 1 SPECIAL STATUS WORD
0
Figure B-14. CPU32 Bus Error on MOVEM Operand Stack Frame, Format $C
SP
+$02
+$06
+$08
+$0C
+$10
+$14
+$16
15
STATUS REGISTER
RETURN PROGRAM COUNTER HIGH
RETURN PROGRAM COUNTER LOW
1 1 0 0 VECTOR OFFSET
FAULTED ADDRESS HIGH
FAULTED ADDRESS LOW
DBUF HIGH
DBUF LOW
CURRENT INSTRUCTION PROG. COUNTER HIGH
CURRENT INSTRUCTION PROG. COUNTER LOW
INTERNAL TRANSFER COUNT REGISTER
1 0 SPECIAL STATUS WORD
0
Figure B-15. CPU32 Four- and Six-Word Bus Error Stack Frame, Format $C
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL B-9
Exception Processing Reference
B.3 FLOATING-POINT STACK FRAMES
Figures B-16 through B-23 illustrate floating-point stack frames for the MC68881/MC68882 and the MC68040.
+$00
31
$00
23
(UNDEFINED)
15 7
(RESERVED)
0
Figure B-16. MC68881/MC68882 and MC68040 Null Stack Frame
+$00
+$04
+$08
+$0C
+$10
+$14
+$18
31 23
VERSION NUMBER +$18
COMMAND/CONDITION REGISTER
15
EXCEPTIONAL OPERAND
(12 BYTES)
OPERAND REGISTER
BIU FLAGS
7
(RESERVED)
(RESERVED)
Figure B-17. MC68881 Idle Stack Frame
0
B-10 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
Exception Processing Reference
+$00
+$04
+$08
+$0C
+$AC
+$B0
+$B4
31
VERSION NUMBER
23
+$B4
15
INTERNAL REGISTERS
(180 BYTES)
7
(RESERVED)
Figure B-18. MC68881 Busy Stack Frame
0
+$24
+$28
+$2C
+$30
+$34
+$38
+$00
+$04
+$08
31
VERSION NUMBER
23
+$38
COMMAND/CONDITION REGISTER
15
INTERNAL REGISTERS
(32 BYTES)
EXCEPTIONAL OPERAND
(12 BYTES)
OPERAND REGISTER
BIU FLAGS
7
(RESERVED)
(RESERVED)
Figure B-19. MC68882 Idle Stack Frame
0
+$00
+$04
+$08
+$0C
+$CC
+$D0
+$D4
31
VERSION NUMBER
23
+$D4
15
INTERNAL REGISTERS
(212 BYTES)
7
(RESERVED)
Figure B-20. MC68882 Busy Stack Frame
0
B-11 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
$00
31
VERSION $41
24 23 16 15
$00
Figure B-21. MC68040 Idle Stack Frame
(RESERVED)
31
$00
$04
$08
$0C
$10
$14
$18
$1C
$20
$24
$28
$2C
$30
FPTS
ETS
STAG
DTAG
VERSION = $41
24 23
WBT WBT WBT
M66 M1 M0
SBIT
CMDREG1B
E1 E3
FPTE
ETE
CMDREG3B
$30
WBT
E15
T
Reserved
16 15
FPTM 63–32
FPTM 31–00
ETM 63–32
ETM 31–00
Figure B-22. MC68040 Unimplimented Instruction Stack Frame
0
0
31
$30
$34
$38
$3C
$40
$44
$48
$1C
$20
$24
$28
$2C
$4C
$50
$54
$58
$5C
$60
$00
$04
$08
$0C
$10
$14
$18 WBTS
FPTS
ETS
STAG
DTAG
VERSION = $41
CU_SAVEPC
E1 E3
24 23
WBTE 14–00
WBT WBT WBT
M66 M1 M0
SBIT
CMDREG1B
FPTE
ETE
CMDREG3B
$60
WBT
E15
T
Reserved
16 15
WBTM 65–34
WBTM 33–02
FPIARCU
FPTM 63–32
FPTM 31–00
ETM 63–32
ETM 31–00
Figure B-23. MC68040 Busy Stack Frame
0
APPENDIX C
S-RECORD OUTPUT FORMAT
The S-record format for output modules is for encoding programs or data files in a printable format for transportation between computer systems. The transportation process can be visually monitored, and the S-records can be easily edited.
C.1 S-RECORD CONTENT
Visually, S-records are essentially character strings made of several fields that identify the record type, record length, memory address, code/data, and checksum. Each byte of binary data encodes as a two- character hexadecimal number: the first character represents the high- order four bits, and the second character represents the low-order four bits of the byte.
Figure C-1 illustrates the five fields that comprise an S-record. Table C-1 lists the composition of each S- record field.
TYPE RECORD LENGTH ADDRESS CODE/DATA
Figure C-1. Five Fields of an S-Record
CHECKSUM
Field
Type
Record Length
Address
Code/Data
Checksum
Table C-1. Field Composition of an S-Record
Contents Printable
Characters
2
2
4, 6, or 8
0–2n
2
S-record type—S0, S1, etc.
The count of the character pairs in the record, excluding the type and record length.
The 2-, 3-, or 4-byte address at which the data field is to be loaded into memory.
From 0 to n bytes of executable code, memory loadable data, or descriptive information. For compatibility with teletypewriters, some programs may limit the number of bytes to as few as 28 (56 printable characters in the S-record).
The least significant byte of the one’s complement of the sum of the values represented by the pairs of characters making up the record length, address, and the code/data fields.
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL C-1
S-Record Output Format
When downloading S-records, each must be terminated with a CR. Additionally, an S-record may have an initial field that fits other data such as line numbers generated by some timesharing systems. The record length (byte count) and checksum fields ensure transmission accuracy.
C.2 S-RECORD TYPES
There are eight types of S-records to accommodate the encoding, transportation, and decoding functions. The various Motorola record transportation control programs (e.g.
upload, download, etc.), cross assemblers, linkers, and other file creating or debugging programs, only utilize S-records serving the programOs purpose. For more information on support of specific S-records, refer to the userOs manual for that program.
An S-record format module may contain S-records of the following types:
S0 — The header record for each block of S-records. The code/data field may contain any descriptive information identifying the following block of S-records.
Under VERSAdos, the resident linkerOs IDENT command can be used to designate module name, version number, revision number, and description information that will make up the header record. The address field is normally zeros.
S1 — A record containing code/data and the 2-byte address at which the code/data is to reside.
S2 — A record containing code/data and the 3-byte address at which the code/data is to reside.
S3 — A record containing code/data and the 4-byte address at which the code/data is to reside.
S5 — A record containing the number of S1, S2, and S3 records transmitted in a particular block. This count appears in the address field. There is no code/data field.
S7 — A termination record for a block of S3 records. The address field may optionally contain the 4-byte address of the instruction to which control is to be passed.
There is no code/data field.
S8 — A termination record for a block of S2 records. The address field may optionally contain the 3-byte address of the instruction to which control is to be passed.
There is no code/data field.
S9 — A termination record for a block of S1 records. The address field may optionally contain the 2-byte address of the instruction to which control is to be passed.
Under VERSAdos, the resident linkerOs ENTRY command can be used to specify this address. If this address is not specified, the first entry point specification encountered in the object module input will be used. There is no code/ data field.
Each block of S-records uses only one termination record. S7 and S8 records are only active when control is to be passed to a 3- or 4- byte address; otherwise, an S9 is used for termination. Normally, there is only one header record, although it is possible for multiple header records to occur.
C-2 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
S-Record Output Format
C.3 S-RECORD CREATION
Dump utilities, debuggers, a VERSAdos resident linkage editor, or cross assemblers and linkers produce S-record format programs. On VERSAdos systems, the build load module
(MBLM) utility allows an executable load module to be built from S-records. It has a counterpart utility in BUILDS that allows an S-record file to be created from a load module.
Programs are available for downloading or uploading a file in S- record format from a host system to an 8- or 16-bit microprocessor- based system. A typical S-record-format module is printed or displayed as follows:
S00600004844521B
S1130000285F245F2212226A000424290008237C2A
S11300100002000800082629001853812341001813
S113002041E900084E42234300182342000824A952
S107003000144ED492
S9030000FC
The module has an S0 record, four S1 records, and an S9 record. The following character pairs comprise the S-record-format module.
S0 Record:
S0 — S-record type S0, indicating that it is a header record.
06 — Hexadecimal 06 (decimal 6), indicating that six character pairs (or ASCII bytes) follow.
0000—A 4-character, 2-byte address field; zeros in this example.
48 — ASCII H
44 — ASCII D
52 — ASCII R
1B — The checksum.
First S1 Record:
S1 — S-record type S1, indicating that it is a code/data record to be loaded/verified at a 2-byte address.
13 — Hexadecimal 13 (decimal 19), indicating that 19 character pairs, representing
19 bytes of binary data, follow.
0000—A 4-character, 2-byte address field (hexadecimal address 0000) indicating where the data that follows is to be loaded.
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL C-3
S-Record Output Format
The next 16 character pairs of the first S1 record are the ASCII bytes of the actual program code/data. In this assembly language example, the programOs hexadecimal opcodes are sequentially written in the code/data fields of the S1 records.
Opcode
285F
245F
2212
MOVE.L
MOVE.L
MOVE.L
226A0004 MOVE.L
24290008 MOVE.L
237C MOVE.L
Instruction
(A7) +, A4
(A7) +, A2
(A2), D1
4(A2), A1
FUNCTION(A1), D2
#FORCEFUNC, FUNCTION(A1)
The rest of this code continues in the remaining S1 recordOs code/data fields and stores in memory location 0010, etc.
2A — The checksum of the first S1 record.
The second and third S1 records also contain hexadecimal 13 (decimal 19) character pairs and end with checksums 13 and 52, respectively. The fourth S1 record contains 07 character pairs and has a checksum of 92.
S9 Record:
S9 — S-record type S9, indicating that it is a termination record.
03 — Hexadecimal 03, indicating that three character pairs (3 bytes) follow.
0000—The address field, zeros.
FC — The checksum of the S9 record.
Each printable character in an S-record encodes in hexadecimal (ASCII in this example) representation of the binary bits that transmit. Figure C-2 illustrates the sending of the first
S1 record. Table C-2 lists the ASCII code for S-records.
.
S
TYPE
1
RECORD LENGTH
1 3 0 0
ADDRESS
0 0 2 8
CODE/DATA
5
5 3 3 1 3 1 3 3 3 0 3 0 3 0 3 0 3 2 3 8 3 5 4 6
010100110011000100110001001100110011000000110000001100000011000000110010001110000011010101000110
F
Figure C-2. Transmission of an S1 Record
CHECKSUM
****
2 A
**** 3 2 4 1
**** 0011001001000001
C-4 MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL MOTOROLA
S-Record Output Format
Table C-2. ASCII Code
Least
Significant
Digit
E
F
C
D
A
B
8
9
6
7
4
5
2
3
0
1
LF
VT
FF
CR
ACK
BEL
BS
HT
SO
SI
0
NUL
SOH
STX
ETX
EOT
ENQ
SYN
ETB
CAN
EM
SUB
ESC
FS
GS
RS
US
1
DLE
DC1
DC2
DC3
DC4
NAK
>
?
<
=
;
:
8
9
6
7
4
5
2
3
0
1
2
Most Significant Digit
3 4 5
/
.
,
–
*
+
)
(
&
’
$
%
SP
!
“
#
L
M
N
O
J
K
H
I
F
G
D
E
@
A
B
C
^
_
]
\
Z
[
X
Y
T
U
V
W
R
S
P
Q
|
} z
{ x y v w
~
DEL t u r s
7 p q l m j k n o h i f g d e b c
6
‘ a
MOTOROLA MC68000 FAMILY PROGRAMMER’S REFERENCE MANUAL C-5
advertisement
Key Features
- 32-bit integer unit and a 64-bit floating-point unit
- Memory management unit (MMU) with support for virtual memory
- Rich set of peripherals, including a UART, a timer, and a watchdog
- High performance for a wide range of tasks
- Suitable for a variety of applications
Related manuals
Frequently Answers and Questions
What is the NXP MC68332?
What are the key features of the NXP MC68332?
What are the benefits of using the NXP MC68332?
advertisement