Memory

-

Up to 8 kB flash

-

Flash is in-system programmable in 512-Byte sectors

-

Up to 512 Bytes RAM (256 + 256)

On-Chip Debug

-

On-chip debug circuitry facilitates full speed, non-intrusive insystem debug (no emulator required)

-

Provides breakpoints, single stepping, inspect/modify memory and registers

12-Bit Analog-to-Digital Converter

-

Up to 16 input channels

-

Up to 200 ksps 12-bit mode or 800 ksps 10-bit mode

-

Internal VREF or external VREF supported

Internal Low-Power Oscillator

-

Calibrated to 24.5 MHz

-

Low supply current

-

±2% accuracy over supply and temperature

Internal Low-Frequency Oscillator

-

80 kHz nominal operation

-

Low supply current

-

Independent clock source for watchdog timer

2 Analog Comparators

-

Programmable hysteresis and response time

-

Configurable as interrupt or reset source

-

Low current

C8051F850-GDI

Tested 25 MIPS 8 kB Flash

Mixed-Signal MCU Die in Wafer Form

Additional Support Peripherals

-

Independent watchdog timer clocked from LFO

-

16-bit CRC engine

High-Speed CIP-51 µC Core

-

Efficient, pipelined instruction architecture

-

Up to 25 MIPS throughput with 25 MHz clock

-

Uses standard 8051 instruction set

-

Expanded interrupt handler

General-Purpose I/O

-

Up to 18 pins

-

5 V-Tolerant

-

Crossbar-enabled

Communication Peripherals

-

UART

-

I

2

C / SMBus™

-

SPI™

Timer/Counters and PWM

-

4 General-Purpose 16-bit Timer/Counters

-

16-bit programmable counter array (PCA) with three channels of PWM, capture/compare, or frequency output capability, and hardware kill/safe state capability

Temperature Range

-

–40 to +85 °C

Supply Voltage

-

2.2 to 3.6 V

Full Technical Data Sheet

-

C8051F85x-86x

Core / Memory / Support

2-8 kB Flash Core LDO

CIP-51

(25 MHz)

256-512 B RAM Supply Monitor

Watchdog 16-bit CRC

C2 Serial Debug / Programming

Clocking / Oscillators

24.5 MHz Low Power Oscillator

80 kHz Low Frequency Oscillator

External Clock (CMOS Input)

Digital Peripherals

UART

I2C / SMBus

SPI

4 x 16-bit Timers

3-Channel PCA

Analog Peripherals

SAR ADC

(12-bit 200 ksps,10-bit 800 ksps)

Voltage Reference

2 x Low Current Comparators

Rev. 1.0 8/14 Copyright © 2014 by Silicon Laboratories C8051F850-GDI

C8051F850-GDI

1. Ordering Information

Table 1.1. Product Selection Guide

C8051F850-C-G1DI 25 8k 512 1 1 1 1 1 4 3 18 16 16 28.5433 mil / 725 µm

(No backgrind)

2 Rev. 1.0

C8051F850-GDI

2. Pin Definitions

Table 2.1 lists the pin definitions for the C8051F850-GDI. For a full description of each pin, refer to the

C8051F85x-C8051F86x data sheet.

Table 2.1. Pin Definitions for C8051F850-GDI

Pin Name

GND

VDD

RST /

C2CK

P0.0

P0.1

P0.2

P0.4

Type

Ground

Power

Active-low Reset /

C2 Debug Clock

Standard I/O

Standard I/O

Standard I/O

Standard I/O

22

23

24

21

20

19

P0.3 /

EXTCLK

Standard I/O /

External CMOS Clock Input

17

16

Yes

Yes

P0MAT.0

INT0.0

INT1.0

P0MAT.1

INT0.1

INT1.1

Yes

Yes

Yes

P0MAT.2

INT0.2

INT1.2

P0MAT.3

EXTCLK

INT0.3

INT1.3

P0MAT.4

INT0.4

INT1.4

ADC0.0

CP0P.0

CP0N.0

VREF

ADC0.1

CP0P.1

CP0N.1

AGND

ADC0.2

CP0P.2

CP0N.2

ADC0.3

CP0P.3

CP0N.3

ADC0.4

CP0P.4

CP0N.4

Rev. 1.0

3

C8051F850-GDI

Table 2.1. Pin Definitions for C8051F850-GDI (Continued)

4

Pin Name

P0.5

P0.6

P1.3

P1.4

P1.5

P0.7

P1.0

P1.1

P1.2

Type

Standard I/O

Standard I/O

Standard I/O

Standard I/O

Standard I/O

Standard I/O

Standard I/O

Standard I/O

Standard I/O

15

13

12

11

9

8

6

5

3

Yes

Yes

Yes

Yes

P0MAT.5

INT0.5

INT1.5

P0MAT.6

CNVSTR

INT0.6

INT1.6

P0MAT.7

INT0.7

INT1.7

P1MAT.0

Yes

Yes

Yes

Yes

Yes

P1MAT.1

P1MAT.2

P1MAT.3

P1MAT.4

P1MAT.5

ADC0.5

CP0P.5

CP0N.5

ADC0.6

CP0P.6

CP0N.6

ADC0.7

CP0P.7

CP0N.7

ADC0.8

CP1P.0

CP1N.0

ADC0.9

CP1P.1

CP1N.1

ADC0.10

CP1P.2

CP1N.2

ADC0.11

CP1P.3

CP1N.3

ADC0.12

CP1P.4

CP1N.4

ADC0.13

CP1P.5

CP1N.5

Rev. 1.0

C8051F850-GDI

Table 2.1. Pin Definitions for C8051F850-GDI (Continued)

Pin Name

P1.6

P1.7

P2.0 /

C2D

P2.1

Type

Standard I/O

Standard I/O

Standard I/O /

C2 Debug Data

Standard I/O

25

4

2

1

Yes P1MAT.6

Yes

ADC0.14

CP1P.6

CP1N.6

ADC0.15

CP1P.7

CP1N.7

Rev. 1.0

5

C8051F850-GDI

3. Bonding Instructions

Figure 3.1. Die Bonding Example (QSOP-24)

6 Rev. 1.0

C8051F850-GDI

Physical Pad

Number

Table 3.1. Bond Pad Coordinates (Relative to Center of Die)

Example Package Pin

Number (QSOP-24)

Package Pin

Name

Physical Pad X

(µm)

Physical Pad Y

(µm)

13

14

15

16

9

10

11

12

4

8

6

7

3

5

1

2

21

22

23

24

25

17

18

19

20

*Note: Pins marked “Reserved” should not be connected.

9

10

11

12

14

15

Reserved*

16

17

Reserved*

18

19

20

Reserved*

21

22

23

Reserved*

2

3

6

7

4

5

8

P1.1

—

P1.0

P0.7

P0.6

—

P0.5

P0.4

P1.7

P1.6

P1.5

P2.1

P1.4

P1.3

—

P1.2

P0.3

—

P0.2

P0.1

P0.0

GND

VDD

RST/C2CK

P2.0/C2D

622

622

331

246

622

622

622

622

–451

–366

–281

–196

–111

–26

63

622

161

72

–17

–622

–622

–622

–622

–622

–622

–371

–282

–193

–108

–23

522

627

627

–627

–627

–627

–627

–627

–627

–627

–456

627

627

627

302

217

132

–274

–371

–456

Rev. 1.0

7

C8051F850-GDI

Table 3.2. Wafer and Die Information

Wafer ID

Wafer Dimensions

C8051F850C

8 in

Die Dimensions

Wafer Thickness (No backgrind)

1399.94 µm x 1409.22 µm

28.5433 mil ±1 mil (725 µm)

Wafer Identification

Scribe Line Width

Notch

60 µm

Die Per Wafer*

Passivation

Contact Sales For Info

Standard

Wafer Packaging Detail

Bond Pad Dimensions

Wafer Jar

57.12 µm x 57.12 µm

Maximum Processing Temperature

Electronic Die Map Format

250 °C

.txt

Bond Pad Pitch Minimum

75 µm

*Note: This is the Expected Known Good Die yielded per wafer and represents the batch order quantity (one wafer).

8 Rev. 1.0

C8051F850-GDI

4. Wafer Storage Guidelines

It is necessary to conform to appropriate wafer storage practices to avoid product degradation or contamination.

 Wafers may be stored for up to 18 months in the original packaging supplied by Silicon Labs.

 Wafers must be stored at a temperature of 18–24 °C.

 Wafers must be stored in a humidity-controlled environment with a relative humidity of <30%.

 Wafers should be stored in a clean, dry, inert atmosphere (e.g., nitrogen or clean, dry air).

Rev. 1.0

9

C8051F850-GDI

5. Failure Analysis (FA) Guidelines

Certain conditions must be met for Silicon Laboratories to perform Failure Analysis on devices sold in wafer form.

 In order to conduct failure analysis on a device in a customer-provided package, Silicon

Laboratories must be provided with die assembled in an industry standard package that is pin compatible with existing packages Silicon Laboratories offers for the device. Initial response time for FA requests that meet this requirements will follow the standard FA guidelines for packaged parts.

 If retest of the entire wafer is requested, Silicon Laboratories must be provided with the whole wafer. Silicon Laboratories cannot retest any wafers that have been sawed, diced, backgrind or are on tape. Initial response time for FA requests that meet this requirements will be 3 weeks.

10 Rev. 1.0

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Disclaimer

Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications. Silicon Laboratories products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.

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