datasheet for SGN01G64D2BG1SA

datasheet for SGN01G64D2BG1SA
Data Sheet
Rev.1.1
20.07.2011
1024MB DDR3 – SDRAM SO-DIMM
204 Pin SO-DIMM
Features:
SGN01G64D2BG1SA-xxRT

1GByte in FBGA Technology


RoHS compliant


Options:


Data Rate / Latency
DDR3 1066 MT/s CL7
DDR3 1333 MT/s CL9
Marking
-BB
-CC

204-pin 64-bit DDR3 Small Outline Dual-In-Line Double
Data Rate Synchronous DRAM module
Module organization: single rank 128M x 64
On-board I2C temperature sensor with integrated serial
presence-detect (SPD) EEPROM
Gold-contact pads
This module is fully pin and functional compatible to the
JEDEC PC3-10600 spec. and JEDEC- Standard MO-268.
(see www.jedec.org)
The pcb and all components are manufactured according
to the RoHS compliance specification [EU Directive
2002/95/EC Restriction of Hazardous Substances (RoHS)]
Module Density
1024MB with 8 dies and 1 rank






DDR3 - SDRAM component Samsung K4B1G0846G
128Mx8 DDR3 SDRAM in PG-TFBGA-78 package
VDD = 1.5V ±0.075V, VDDQ 1.5V ±0.075V
Grade E
1.5V I/O ( SSTL_15 compatible)
8-bit pre-fetch architecture
Grade W
Programmable CAS Latency, CAS Write Latency, Additive
Latency, Burst Length and Burst Type.
*) The refresh rate has to be doubled when 85°C<TC<95°C*) The
rate has to be doubled
when
C<TC<95°
C for improved
 refresh
On-Die-Termination
(ODT)
and85°
Dynamic
ODT
signal integrity.
Environmental Requirements:

Refresh. Self Refresh and Power Down Modes.

ZQ Calibration for output driver and ODT.

Operating temperature (ambient)

System Level Timing Calibration Support via Write Leveling
Standard Grade
0°C to 70°C
Grade E
0°C to 85°C
and Multi Purpose Register (MPR) Read Pattern.

Standard Grade
Grade W





(TA)
(TC)
(TA)
(TC)
(TA)
(TC)
0°C to 70°C
0°C to 85°C
0°C to 85°C
0°C to 95°C *)
-40°C to 85°C
-40°C to 95°C *)
-40°C to 85°C
Operating Humidity
10% to 90% relative humidity, noncondensing
Operating Pressure
105 to 69 kPa (up to 10000 ft.)
Storage Temperature
-55°C to 100°C
Storage Humidity
5% to 95% relative humidity, noncondensing
Storage Pressure
1682 PSI (up to 5000 ft.) at 50°C
Figure: mechanical dimensions
1
1
if no tolerances specified ± 0.15mm
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
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Fax: +41 (0) 71 913 03 15
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eMail: [email protected]
Page 1
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Data Sheet
Rev.1.1
20.07.2011
This Swissbit module is an industry standard 204-pin 8-byte DDR3 SDRAM Small Outline Dual-In-line Memory
Module (SO-DIMM) which is organized as x64 high speed CMOS memory arrays. The module uses internally
configured octal-bank DDR3 SDRAM devices. The module uses double data rate architecture to achieve highspeed operation. DDR3 SDRAM modules operate from a differential clock (CK and CK#). READ and WRITE
accesses to a DDR3 SDRAM module is burst-oriented; accesses start at a selected location and continue for a
programmed number of locations in a programmed sequence. The burst length is either four or eight locations. An
auto precharge function can be enabled to provide a self-timed row precharge that is initiated at the end of a burst
access. The DDR3 SDRAM devices have a multibank architecture which allows a concurrent operation that is
providing a high effective bandwidth. A self refresh mode is provided and a power-saving “power-down” mode. All
inputs and all full drive-strength outputs are SSTL_15 compatible.
The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM
2
using the standard I C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are
utilized by the SO-DIMM manufacturer (Swissbit) to identify the module type, the module’s organization and
several timing parameters. The second 128 bytes are available to the end user.
Module Configuration
Organization
DDR3 SDRAMs used
Row
Addr.
Device Bank
Addr.
Column
Addr.
Refresh
Module
Bank Select
128M x 64bit
8 x 128M x 8bit (1024Mbit)
14
BA0, BA1, BA2
10
8k
S0#
Module Dimensions
in mm
67.60 (long) x 30(high) x 3.80 [max] (thickness)
Timing Parameters
Part Number
Module Density Transfer Rate
Clock Cycle/Data bit rate
Latency
SGN01G64D2BG1SA-BB[E/W]RT
1024 MB
8.5 GB/s
1.87ns/1066MT/s
7-7-7
SGN01G64D2BG1SA-CC[E/W]RT
1024 MB
10.6 GB/s
1.5ns/1333MT/s
9-9-9
Pin Name
A0-9, A11 – A13
Address Inputs
A10/AP
Address Input / Autoprecharge Bit
BA0 – BA2
Bank Address Inputs
DQ0 – DQ63
Data Input / Output
DM0-DM7
Input Data Mask
DQS0 - DQS7
Data Strobe, positive line
DQS0# - DQS7#
Data Strobe, negative line (only used when differential data strobe mode is enabled)
S0#
Chip Select
RAS#
Row Address Strobe
CAS#
Column Address Strobe
WE#
Write Enable
CKE
Clock Enable
ODT0
On-Die Termination
CK0
Clock Inputs, positive line
CK0#
Clock Inputs, negative line
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Page 2
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Data Sheet
Rev.1.1
20.07.2011
VDD
Supply Voltage (1.5V± 0.075V)
VREFDQ
Reference voltage: DQ, DM (VDD/2)
VREFCA
Reference voltage: Control, command, and address (VDD/2)
VSS
Ground
VTT
Termination voltage: Used for control, command, and address (VDD/2).
VDDSPD
Serial EEPROM Positive Power Supply
SCL
Serial Clock for Presence Detect
SDA
Serial Data Out for Presence Detect
SA0 – SA1
Presence Detect Address Inputs
Event#
Temperature event: The EVENT# pin is asserted by the temperature sensor when critical
NC
No Connection
Pin Configuration
Frontside
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
1
VREFDQ
53
DQ19
103
CK0#
155
VSS
3
VSS
55
VSS
105
VDD
157
DQ42
5
DQ0
57
DQ24
107
A10/AP
159
DQ43
7
DQ1
59
DQ25
109
BA0
161
VSS
9
VSS
61
VSS
111
VDD
163
DQ48
11
DM0
63
DM3
113
WE#
165
DQ49
13
VSS
65
VSS
115
CAS#
167
VSS
15
DQ2
67
DQ26
117
VDD
169
DQS6#
17
DQ3
69
DQ27
119
A13
171
DQS6
19
VSS
71
VSS
121
NC (S1#)
173
VSS
21
DQ8
123
VDD
175
DQ50
23
DQ9
73
CKE0
125
NC (TEST)
177
DQ51
25
VSS
75
VDD
127
VSS
179
VSS
27
DQS1#
77
NC
129
DQ32
181
DQ56
29
DQS1
79
BA2
131
DQ33
183
DQ57
31
VSS
81
VDD
133
VSS
185
VSS
33
DQ10
83
A12/BC#
135
DQS4#
187
DM7
35
DQ11
85
A9
137
DQS4
189
VSS
37
VSS
87
VDD
139
VSS
191
DQ58
39
DQ16
89
A8
141
DQ34
193
DQ59
41
DQ17
91
A5
143
DQ35
195
VSS
43
VSS
93
VDD
145
VSS
197
SA0
45
DQS2#
95
A3
147
DQ40
199
VDDSPD
47
DQS2
97
A1
149
DQ41
201
SA1
49
VSS
99
VDD
151
VSS
203
VTT
51
DQ18
101
CK0
153
DM5
KEY
(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module
Swissbit AG
Industriestrasse 4
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Page 3
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Data Sheet
Rev.1.1
20.07.2011
Backside
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
2
VSS
54
VSS
104
NC (CK1#)
156
VSS
4
DQ4
56
DQ28
106
VDD
158
DQ46
6
DQ5
58
DQ29
108
BA1
160
DQ47
8
VSS
60
VSS
110
RAS#
162
VSS
10
DQS0#
62
DQS3#
112
VDD
164
DQ52
12
DQS0
64
DQS3
114
S0#
166
DQ53
14
VSS
66
VSS
116
ODT0
168
VSS
16
DQ6
68
DQ30
118
VDD
170
DM6
18
DQ7
70
DQ31
120
NC (ODT1)
172
VSS
20
VSS
72
VSS
122
NC
174
DQ54
22
DQ12
124
VDD
176
DQ55
24
DQ13
74
NC (CKE1)
126
VREFCA
178
VSS
26
VSS
76
VDD
128
VSS
180
DQ60
28
DM1
78
NC (A15)
130
DQ36
182
DQ61
30
NC (RESET#)
80
NC (A14)
132
DQ37
184
VSS
32
VSS
82
VDD
134
VSS
186
DQS7#
34
DQ14
84
A11
136
DM4
188
DQS7
36
DQ15
86
A7
138
VSS
190
VSS
38
VSS
88
VDD
140
DQ38
192
DQ62
40
DQ20
90
A6
142
DQ39
194
DQ63
42
DQ21
92
A4
144
VSS
196
VSS
44
VSS
94
VDD
146
DQ44
198
EVENT#
46
DM2
96
A2
148
DQ45
200
SDA
48
VSS
98
A0
150
VSS
202
SCL
50
DQ22
100
VDD
152
DQS5#
204
VTT
52
DQ23
102
NC (CK1)
154
DQS5
KEY
(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
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Page 4
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Data Sheet
Rev.1.1
20.07.2011
FUNCTIONAL BLOCK DIAGRAMM 1024MB DDR3 SDRAM SODIMM,
1 RANK AND 8 COMPONENTS
S0
DQS4
DQS4
DM4
DQS0
DQS0
DM0
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS DQS
D0
ZQ
DQ40
DQ41
DQ42
I/O 0
I/O 1
I/O 2
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ48
DQ49
DQ50
I/O 0
I/O 1
I/O 2
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
I/O 0
I/O 1
I/O 2
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
D4
ZQ
DQS5
DQS5
DM5
DQS1
DQS1
DM1
DM
DQ8
DQ9
DQ10
I/O 0
I/O 1
I/O 2
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS DQS
D1
ZQ
CS
DQS DQS
D5
ZQ
DQS6
DQS6
DM6
DQS2
DQS2
DM2
DM
DQ16
DQ17
DQ18
I/O 0
I/O 1
I/O 2
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
DQS DQS
D2
ZQ
CS
DQS DQS
D6
ZQ
DQS7
DQS7
DM7
DQS3
DQS3
DM3
DM
BA0-BA2
A0-A13
RAS
CAS
WE
ODT0
CKE0
CK0
CK0
RESET
DQ35
DQ36
DQ37
DQ38
DQ39
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ32
DQ33
DQ34
DQ24
DQ25
DQ26
I/O 0
I/O 1
I/O 2
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D3
ZQ
BA0-BA2: SDRAM D0-D7
A0-A13: SDRAM D0-D7
RAS: SDRAM D0-D7
CAS: SDRAM D0-D7
WE: SDRAM D0-D7
ODT: SDRAM D0-D7
CKE: SDRAM D0-D7
CK: SDRAM D0-D7
CK: SDRAM D0-D7
RESET: SDRAM D0-D7
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DM
DQS DQS
VDDSPD
SPD
VDD/VDDQ
D0-D7
VREFDQ
D0-D7
VREFCA
D0-D7
VSS
D0-D7
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CS
DQS DQS
D7
ZQ
Notes:
1. DQ-to-I/O wiring is shown as recommended but may
be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationship must be
maintained as shown.
3. DQ, DM, DQS/DQS resistors: Refer to associated
topology diagram.
4. Refer to the appropriate clock wiring topology under
the DIMM wiring details section of the JEDED document.
5. For each DRAM, a unique ZQ resistor is connected to
GND. The ZQ resistor is 240O±1%.
6. Refer to associated figure for SPD details.
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Page 5
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Data Sheet
Rev.1.1
20.07.2011
MAXIMUM ELECTRICAL DC CHARACTERISTICS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
VDDL Supply Voltage
Voltage on any pin relative to VSS
INPUT LEAKAGE CURRENT
SYMBOL
VDD
VDDQ
VDDL
VIN, VOUT
Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V
(All other pins not under test = 0V)
MIN
-0.4
-0.4
-0.4
-0.4
MAX
1.975
1.975
1.975
1.975
II
UNITS
V
V
V
V
µA
Command/Address
-16
16
IOZ
-16
-2
-5
16
2
5
µA
IVREF
-8
8
µA
RAS#, CAS#, WE#, S#, CKE
CK, CK#
DM
OUTPUT LEAKAGE CURRENT
(DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ)
DQ, DQS, DQS#
VREF LEAKAGE CURRENT ; VREF is on a valid level
DC OPERATING CONDITIONS
PARAMETER/ CONDITION
Supply Voltage
I/O Supply Voltage
VDDL Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
MIN
VDD
1.425
VDDQ
1.425
VDDL
1.425
VREF
0.49 x VDDQ
VTT
0.49 x VDDQ-20mV
VIH (DC)
VREF + 0.1
VIL (DC)
-0.3
NOM
1.5
1.5
1.5
0.50 x VDDQ
0.50 x VDDQ
MAX
1.575
1.575
1.575
0.51x VDDQ
0.51x VDDQ+20mV
VDDQ + 0.3
VREF – 0.1
UNITS
V
V
V
V
V
V
V
AC INPUT OPERATING CONDITIONS
PARAMETER/ CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
SYMBOL
VIH (AC)
VIL (AC)
MIN
VREF + 0.175
-
MAX
VREF - 0.175
UNITS
V
V
CAPACITANCE
At DDR3 data rates, it is recommended to simulate the performance of the module to achieve optimum values.
When inductance and delay parameters associated with trace lengths are used in simulations, they are
significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then
render a considerably more accurate result. JEDEC modules are now designed by using simulations to close
timing budgets.
Swissbit AG
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Page 6
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Data Sheet
Rev.1.1
20.07.2011
IDD Specifications and Conditions
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
Parameter
& Test Condition
OPERATING CURRENT *) :
One device bank Active-Precharge;
tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH
between valid commands;
DQ inputs changing once per clock cycle; Address and
control inputs changing once every two clock cycles
OPERATING CURRENT *) :
One device bank; Active-Read-Precharge;
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD),
tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between
valid commands; Address inputs changing once every
two clock cycles; Data Pattern is same as IDD4W
Fast Exit
PRECHARGE POWER-DOWN
CURRENT:
All device banks idle; Power-down mode;
tCK = tCK (IDD); CKE is LOW; All Control and Slow Exit
Address bus inputs are not changing; DQ’s
are floating at VREF
PRECHARGE QUIET STANDBY CURRENT:
All device banks idle;
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All Control and Address bus inputs are not changing;
DQ’s are floating at VREF
PRECHARGE STANDBY CURRENT:
All device banks idle;
tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
ACTIVE POWER-DOWN CURRENT:
All device banks open; tCK = tCK (IDD); CKE is LOW; All
Control and Address bus inputs are not changing; DQ’s
are floating at VREF (always fast exit)
ACTIVE STANDBY CURRENT:
All device banks open; tCK = tCK (IDD),
tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
All other Control and Address bus inputs are changing
once every two clock cycles; DQ inputs changing once
per clock cycle
OPERATING READ CURRENT:
All device banks open, Continuous burst reads; One
module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD),
AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP
(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are changing once
every two clock cycles; DQ inputs changing once per
clock cycle
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CH – 9552 Bronschhofen
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Symbol
max.
Unit
10600-999
8500-777
IDD0
400
360
mA
IDD1
480
440
mA
IDD2P
160
160
mA
80
80
IDD2Q
200
200
mA
IDD2N
200
200
mA
IDD3P
200
200
mA
IDD3N
400
360
mA
IDD4R
800
680
mA
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Data Sheet
Parameter
& Test Condition
OPERATING WRITE CURRENT:
All device banks open, Continuous burst writes; One
module rank active; BL = 4, CL = CL (IDD), AL = 0;
tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are changing once every two clock
cycles; DQ inputs changing once per clock cycle
BURST REFRESH CURRENT:
tCK = tCK (IDD); refresh command at every tRFC (IDD)
interval, CKE is HIGH, CS# is HIGH between valid
commands; All other Control and Address bus inputs
are changing once every two clock cycles; DQ inputs
changing once per clock cycle
SELF REFRESH CURRENT:
CK and CK# at 0V; CKE ≤ 0.2V; All other Control and
Address bus inputs are floating at VREF; DQ’s are
floating at VREF
OPERATING CURRENT*) :
Four device bank interleaving READs, IOUT = 0mA; BL = 4,
CL = CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK
(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD);
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are not changing during
DESELECT; DQ inputs changing once per clock cycle
Rev.1.1
Symbol
20.07.2011
max.
Unit
10600-999
8500-777
IDD4W
840
720
mA
IDD5
920
920
mA
IDD6
80
80
mA
IDD7
1400
1160
mA
*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW)
mode.
TIMING VALUES USED FOR IDD MEASUREMENT
IDD MEASUREMENT CONDITIONS
SYMBOL
10600-999
8500-777
9
7
CL (IDD)
13.5
13.125
tRCD (IDD)
49.5
50.625
tRC (IDD)
6
7.5
tRRD (IDD)
1.5
1.87
tCK (IDD)
36
37.5
tRAS MIN (IDD)
70’200
70’200
tRAS MAX (IDD)
13.5
13.125
tRP (IDD)
110
110
tRFC (IDD)
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Unit
tCK
ns
ns
ns
ns
ns
ns
ns
ns
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Page 8
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Data Sheet
Rev.1.1
20.07.2011
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
AC CHARACTERISTICS
PARAMETER
Clock cycle time
CL = 10
CL = 9
CL = 8
CL = 7
CL = 6
CK high-level width
CK low-level width
Data-out high-impedance
window from CK/CK#
Data-out low-impedance window
from CK/CK#
DQ and DM input setup time
relative to DQS
tCK (10)
tCK (9)
tCK (8)
tCK (7)
tCK (6)
tCH (avg)
tCL (avg)
tHZ
10600-999
MIN
MAX
1.5
<1.875
1.5
<1.875
1.875
<2.5
1.875
<2.5
2.5
3.3
0.47
0.53
0.47
0.53
250
8500-777
MIN
MAX
1.875
<2.5
2.5
3.3
0.47
0.53
0.47
0.53
300
tLZ
-500
-600
SYMBOL
250
Unit
ns
ns
ns
ns
ns
tCK
tCK
ps
300
ps
tDS(Base)
30
25
ps
DQ and DM input hold time
relative to DQS
DQ and DM input setup time
relative to DQS VREF=1V/ns
tDH(Base)
65
100
ps
tDS1V
180
200
ps
DQ and DM input hold time
relative to DQS VREF=1V/ns
DQ and DM input pulse width
( for each input )
DQS, DQS# to DQ skew, per
access
DQ-DQS hold, DQS to first DQ
to go non-valid, per access
DQS input high pulse width
DQS input low pulse width
DQS, DQS# rising to/from CK,
CK#
DQS, DQS# rising to/from CK,
CK# when DLL disabled
DQS falling edge to CK rising
- setup time
DQS falling edge from CK rising
- hold time
DQS read preamble
DQS read postamble
DQS write preamble
DQS write postamble
Positive DQS latching edge to
associated clock edge
Address and control input pulse
width ( for each input )
CTRL, CMD, Addr setup to CK,
CK#
CTRL, CMD, Addr setup to CK,
CK#
VREF @ 1V/ns
tDH1V
165
200
ps
tDIPW
400
490
ps
1
2
125
tDQSQ
0.38
tQH
150
0.38
ps
tCK
(AVG)
tDQSH
tDQSL
tDQSCK
0.45
0.45
-255
0.55
0.55
255
0.45
0.45
-300
0.55
0.55
300
tCK
tCK
ps
tDQSCK
1
10
1
10
ns
DLL_DIS
tDSS
0.2
0.2
tCK
tDSH
0.2
0.2
tCK
tRPRE
tRPST
tWPRE
tWPST
tDQSS
0.9
0.3
0.9
0.3
- 0.25
Note1
Note2
+ 0.25
0.9
0.3
0.9
0.3
- 0.25
Note1
Note2
+ 0.25
tCK
tCK
tCK
tCK
tCK
tIPW
620
780
ps
tIS(Base)
65
125
ps
tIS(1V)
240
300
ps
The maximum preamble is bound by tLZDQS (MAX)
The maximum postamble is bound by tHZDQS (MAX)
Swissbit AG
Industriestrasse 4
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Page 9
of 15
Data Sheet
Rev.1.1
20.07.2011
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
AC CHARACTERISTICS
PARAMETER
SYMBOL
CTRL, CMD, Addr hold to CK,
tIH(Base)
CK#
CTRL, CMD, Addr hold to CK,
tIH(1V)
CK#
VREF @ 1V/ns
CAS# to CAS# command delay
tCCD
ACTIVE to ACTIVE (same bank)
tRC
command period
ACTIVE bank a to ACTIVE bank
tRRD
b command
ACTIVE to READ or WRITE
tRCD
delay
Four bank
1K Page size
tFAW
Activate period
2K Page size
ACTIVE to PRECHARGE
tRAS
command
Internal READ to precharge
tRTP
command delay
Write recovery time
tWR
Auto precharge write recovery +
tDAL
precharge time
Internal WRITE to READ
tWTR
command delay
PRECHARGE command period
tRP
LOAD MODE command cycle
tMRD
time
REFRESH to ACTIVE or
REFRESH to REFRESH
tRFC
command interval
Average periodic refresh interval
0 °C ≤ TCASE ≤ 85°C
85 °C < TCASE ≤ 95°C
RTT turn-on from ODTL on
reference
RTT turn-on from ODTL off
reference
Asynchronous RTT turn-on
delay (power Down with DLL off)
Asynchronous RTT turn-off
delay (power Down with DLL off)
RTT dynamic change skew
Exit self refresh to commands
not requiring a locked DLL
Write levelling setup from rising
CK, CK# crossing to rising DQS,
DQS# crossing
Write levelling setup from rising
DQS, DQS# crossing to rising
CK, CK# crossing
First DQS, DQS# rising edge
DQS, DQS# delay
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
10600-999
MIN
MAX
8500-777
MIN
MAX
140
200
ps
240
300
ps
4
4
tCK
49.5
50.625
ns
ns
Unit
max
max
4nCK,10ns
4nCK,7.5ns
13.5
13.125
ns
30
45
37.5
50
ns
36
70’200
37.5
70’200
ns
max
max
4nCK,7.5ns
4nCK,7.5ns
15
15
ns
tWR + tRP/tCK
tWR + tRP/tCK
ns
ns
ns
max
max
4nCK,7.5ns
4nCK,7.5ns
15
13.125
ns
4
4
tCK
110
70’200
110
70’200
tREFI
7.8
7.8
tREFI (IT)
3.9
3.9
ns
µs
tAON
-250
250
-300
300
ps
tAOF
0.3
0.7
0.3
0.7
tCK
tAONPD
2
8,5
2
8,5
ns
tAOFPD
2
8,5
2
8,5
ns
tADC
0.3
max
0.7
0.3
max
0.7
tCK
tXS
5nCK,tR
FC + 10ns
5nCK,tR
FC + 10ns
ns
tWLS
195
245
ps
tWLH
195
245
ps
tWLMRD
tWLDQSEN
40
25
40
25
tCK
tCK
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Fax: +41 (0) 71 913 03 15
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eMail: [email protected]
Page 10
of 15
Data Sheet
Rev.1.1
20.07.2011
DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED
AC OPERATING CONDITIONS (Continued)
(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)
AC CHARACTERISTICS
PARAMETER
Exit reset from CKE HIGH to a
valid command
Begin power supply ramp to
power supplies stable
RESET# LOW to power supplies
stable
RESET# LOW to I/O and RTT
High-Z
Exit precharge power-down to
any non-READ command
CKE minimum high/low time
10600-999
MIN
MAX
max
SYMBOL
tXPR
8500-777
MIN
MAX
max
5nCK,
tRFC + 10ns
5nCK,
tRFC + 10ns
Unit
tCK
tVDDPR
200
200
ms
tRPS
200
200
ms
tIOz
20
20
ns
tXP
tCKE
max
max
3nCK,6ns
3nCK,7.5ns
max
max
3nCK,
5.625ns
3nCK,
5.625ns
tCK
tCK
Temperature Sensor with Serial Presence-Detect EEPROM
SCL
SDA
WP/ EVENT
EVENT
R1
0
SA0
SA1
SA0
SA1
SA2
Temperature Sensor with Serial Presence-Detect EEPROM Operating Conditions
Parameter / Condition
Supply voltage
Supply current: Vdd = 3.3V
Input high voltage: Logic 1; SCL, SDA
Input low voltage: Logic 0; SCL, SDA
Output low voltage: Iout = 2.1mA
Input current
Temperature sensing range
Temperature sensor accuracy
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Symbol
VDDSPD
IDD
VIH
VIL
VOL
IIN
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
MIN
+3
MAX
+3.6
+2.0
+1.45
-5.0
TBD
TBD
VDDSPD +1
550
400
5.0
TBD
TBD
www.swissbit.com
eMail: [email protected]
Unit
V
mA
V
mV
mV
µA
°C
°C
Page 11
of 15
Data Sheet
Rev.1.1
20.07.2011
A.C. Characteristics of Temperature Sensor
VCC = 3.3 V ± 10%, TA = −40°C to +125°C
Symbol
fSCL
tBUF
tF
tR
tHD:DAT
tH:STA
tHIGH
tLOW
tSU:DAT
tSU:STA
tSU:STO
tTIMEOUT
tI
tWR
tPU
Parameter / Condition
SCL clock frequency
Bus Free Time Between STOP and START
SDA fall time
SDA rise time
Data hold time (accepted for Input Data)
Data Hold Time (guaranteed for Output Data)
Start condition hold time
High Period of SCL
Low Period of SCL
Data setup time
Start condition setup time
Stop condition setup time
SMBus SCL Clock Low Timeout
Noise Pulse Filtered at SCL and SDA Inputs
Write Cycle Time
Power-up Delay to Valid Temperature Recording
MIN
10
1300
MAX
400
300
300
0
300
600
600
1300
100
600
600
25
900
35
100
5
100
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
ms
ms
Temperature Characteristics of Temperature Sensor
VCC = 3.3 V ± 10%, TA = −40°C to +125°C
Parameter
Test Conditions/Comments
+75°C ≤ TA ≤ +95°C, active range
+40°C ≤ TA ≤ +125°C, monitor range
-40°C ≤ TA ≤ +125°C, sensing range
Temperature Reading Error
Class B, JC42.4 compliant
ADC Resolution
Temperature Resolution
Conversion Time
1
Thermal Resistance JA
Junction-to-Ambient (Still Air)
MAX
±1.0
±2.0
±3.0
12
0.0625
100
92
Unit
°C
°C
°C
Bits
°C
Ms
°C/W
Power Dissipation is defined as PJ = (TJ − TA)/ JA, where TJ is the junction temperature and TA is the ambient temperature. The thermal
resistance value refers to the case of a package being used on a standard 2-layer PCB.
1
Slave Address Bits of Temperature Sensor
Device
EEPROM
Temp. Sensor
1
Device Type Identifier
1
b7
b6
b5
b4
1
0
1
0
0
0
1
1
Select Address Signals
b3
b2
b1
A2
A1
A0
A2
A1
A0
R/W#
b0
R/W#
R/W#
The most significant bit, b7, is sent first.
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 12
of 15
Data Sheet
Rev.1.1
20.07.2011
SERIAL PRESENCE-DETECT MATRIX
Byte
Byte Description
10600-999
8500-777
0
CRC RANGE, EEPROM BYTES, BYTES USED
0x92
1
SPD REVISON
0x10
2
DRAM DEVICE TYPE
0x0B
3
MODULE TYPE (FORM FACTOR)
0x03
4
SDRAM DEVICE DENSITY & BANKS
0x02
5
SDRAM DEVICE ROW & COLUMN COUNT
0x11
6
BYTE 6 RESERVED
0x00
7
MODULE RANKS & DEVICE DQ COUNT
0x01
8
ECC TAG & MODULE MEMORY BUS WIDTH
0x03
9
FINE TIMEBASE DIVIDEND/DIVISOR
0x52
10
MEDIUM TIMEBASE DIVIDEND
0x01
11
MEDIUM TIMEBASE DIVISOR
0x08
12
MIN SDRAM CYCLE TIME (tCK MIN)
13
BYTE 13 RESERVED
14
CAS LATENCIES SUPPORTED (CL4 => CL11)
15
CAS LATENCIES SUPPORTED (CL12 => CL18)
0x00
16
MIN CAS LATENCY TIME (tAA MIN)
0x69
17
MIN WRITE RECOVERY TIME (tWR MIN)
0x78
18
MIN RAS# TO CAS# DELAY (tRCD MIN)
0x69
19
MIN ROW ACTIVE TO ROW ACTIVE DELAY (tRRD MIN)
20
MIN ROW PRECHARGE DELAY (TRP MIN)
0x69
21
UPPER NIBBLE FOR tRAS & tRC
0x11
22
MIN ACTIVE TO PRECHARGE DELAY (tRAS MIN)
0x20
0x2C
23
MIN ACTIVE TO ACTIVE/REFRESH DELAY (tRC MIN)
0x89
0x95
24
MIN REFRESH RECOVERY DELAY (tRFC MIN) LSB
0x70
25
MIN REFRESH RECOVERY DELAY (tRFC MIN) MSB
0x03
26
MIN INTERNAL WRITE TO READ CMD DELAY (tWTR MIN)
0x3C
27
MIN INTERNAL READ TO PRECHARGE CMD DELAY
(tRTP MIN)
0x3C
28
MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) MSB
0x00
0x01
29
MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) LSB
0xF0
0x2C
30
SDRAM DEVICE OUTPUT DRIVERS SUPPORTED
0x83
31
SDRAM DEVICE THERMAL & REFRESH OPTIONS
0x01
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
0x0C
0x0F
0x00
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
0x3C
0x1C
0x30
0x3C
www.swissbit.com
eMail: [email protected]
Page 13
of 15
Data Sheet
Byte
32
Rev.1.1
Byte Description
10600-999
20.07.2011
8500-777
DDR3-MODULE THERMAL SENSOR
0x80
BYTES 32-59 RESERVED
0x00
60
MODULE HEIGHT (NOMINAL)
0x0F
61
MODULE THICKNESS (MAX)
0x11
62
REFERENCE RAW CARD ID
0x01
63
ADDRESS MAPPING EDGE CONECTOR TO DRAM
0x00
BYTES 64-116 RESEVED
0x00
117
MODULE MFR ID (LSB)
0x83
118
MODULE MFR ID (MSB)
0xDA
119
MODULE MFR LOCATION ID
0x01 (Switzerland)
0x02 (Germany)
0x03 (USA)
120
MODULE MFR YEAR
X
121
MODULE MFR WEEK
X
122-125
MODULE SERIAL NUMBER
X
126-127
CRC
128-145
MODULE PART NUMBER
33-59
64-116
0x3F04
0x7DAD
"SGN01G64D2BG1SA-xx"
146
MODULE DIE REV
X
147
MODULE PCB REV
0x54
148
DRAM DEVICE MFR ID (LSB)
0x80
149
DRAM DEVICE MFR (MSB)
0xCE
150-175
MFR RESERVED BYTES 150-175
0x00
176-255
CUSTOMER RESERVED BYTES 176-255
0xff
Part Number Code
S
G
N
01G
64
D2
B
G
1
SA
1
2
3
4
5
6
7
8
9
10
-
CC
*
R
**
11
12
13
14
*RoHs compl.
DDR3-1333MT/s
Swissbit AG
SDRAM DDR3
204 Pin SoDIMM 1.5V
Depth (1GB)
Width
PCB-Type (S3D3B101)
Chip Vendor (Samsung)
1 Module Rank
Chip Rev. G
Chip organisation x8
* optional / additional information
** T= thermal sensor
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 14
of 15
Data Sheet
Rev.1.1
20.07.2011
Locations
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Switzerland
Phone:
+41 (0)71 913 03 03
Fax:
+41 (0)71 913 03 15
_____________________________
Swissbit Germany GmbH
Wolfener Strasse 36
D – 12681 Berlin
Germany
Phone:
+49 (0)30 93 69 54 – 0
Fax:
+49 (0)30 93 69 54 – 55
_____________________________
Swissbit NA, Inc.
14 Willett Avenue, Suite 301A
Port Chester, NY 10573
USA
Phone:
+1 914 935 1400
Fax:
+1 914 935 9865
_____________________________
Swissbit NA, Inc.
3913 Todd Lane, Suite – 307
Austin, TX 78744
USA
Phone:
+1 512 302 9001
Fax:
+1 512 302 4808
_____________________________
Swissbit Japan, Inc.
3F Core Koenji,
2-1-24 Koenji-Kita, Suginami-Ku,
Tokyo 166-0002
Japan
Phone: +81 3 5356 3511
Fax:
+81 3 5356 3512
Swissbit AG
Industriestrasse 4
CH – 9552 Bronschhofen
Fon: +41 (0) 71 913 03 03
Fax: +41 (0) 71 913 03 15
www.swissbit.com
eMail: [email protected]
Page 15
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