"Broadband Lumped-Element Integrated N-Way Power Dividers for Voltage Standards,"

"Broadband Lumped-Element Integrated N-Way Power Dividers for Voltage Standards,"
IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 8, AUGUST 2009
2055
Broadband Lumped-Element Integrated N -Way
Power Dividers for Voltage Standards
Michael M. Elsbury, Student Member, IEEE, Paul D. Dresselhaus, Norman F. Bergren, Charles J. Burroughs,
Samuel P. Benz, Senior Member, IEEE, and Zoya Popović, Fellow, IEEE
Abstract—This paper presents a monolithically integrated
broadband lumped-element Wilkinson power divider centered
at 20 GHz, which was designed and fabricated to uniformly
distribute power to arrays of Josephson junctions (JJs) for superconducting voltage standards. This solution achieves a fourfold
decrease in chip area, and a twofold increase in bandwidth (BW)
when compared to the previous narrowband distributed circuit. A
single Wilkinson divider demonstrates 0.4-dB maximum insertion
loss (IL), a 10-dB match BW of 10–24.5 GHz, and a 10-dB isolation
BW of 13–30 GHz. A 16-way four-level binary Wilkinson power
divider network is characterized in a divider/attenuator/combiner
back-to-back measurement configuration with a 10-dB match BW
of 10–25 GHz. In the 15–22-GHz band of interest, the maximum
IL for the 16-way divider network is 0.5 dB, with an average of
0.2 dB. The amplitude balance of the divider at 15, 19, and 22 GHz
is measured to be 1.0 dB utilizing 16 arrays of 15 600 JJs as
on-chip power detectors.
Index Terms—Cryogenic electronics, Josephson arrays, lumpedelement microwave circuits, microwave integrated circuits (ICs),
power dividers, superconducting coils, superconducting ICs, superconducting microwave devices.
I. INTRODUCTION
HIS PAPER addresses the design, analysis, and testing
of superconducting microwave integrated-circuit (IC)
lumped-element Wilkinson power dividers for a programmable
Josephson voltage standard [1]. On-chip power division is
needed to enable multiple arrays of many Josephson junctions
(JJs) periodically loading coplanar waveguide (CPW) transmission lines in niobium (Nb) on a silicon (Si) substrate [2].
The goal of the current research is to utilize a monolithically
integrated 16-way power divider to excite 250 000 junctions
at 20 GHz producing a 10-V programmable Josephson voltage
standard [3]. The present National Institute of Standards
and Technology (NIST) programmable Josephson voltage
standard systems are limited to 1 V without on-chip power
division. The scale of the inverse of the Josephson constant,
T
Manuscript received February 27, 2008; revised October 13, 2008. First published July 28, 2009; current version published August 12, 2009. This work
was supported in part by the University of Colorado (CU)–National Institute of
Standards and Technology (NIST) seed research funding for collaborations and
the Department of Education Graduate Assistance in Areas of National Need
(GAANN) Fellowship.
M. M. Elsbury and Z. Popović are with the Department of Electrical and Computer Engineering, University of Colorado at Boulder, Boulder, CO 80309-0425
USA (e-mail: michael.elsbury@colorado.edu; zoya.popovic@colorado.edu).
P. D. Dresselhaus, N. F. Bergren, C. J. Burroughs, and S. P. Benz are with
the National Institute of Standards and Technology (NIST), Boulder, CO 80305
USA (e-mail: paul.dresselhaus@nist.gov).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TMTT.2009.2025464
Fig. 1. Micrograph of a portion of the broadband balanced 16-way divider/combiner configuration. Three binary levels of power division utilizing
the 20-GHz lumped-element Wilkinson divider are shown. The light colored
yellow material (in online version) is Nb, the darker blue material (in online
version) is the Si substrate.
V/GHz per junction, drives the increase
in frequency and number of junctions to achieve the higher
output voltage [1].
The superconducting Nb used for the junctions gives the
IC designer the advantage of creating complex low-loss circuits using integrated superconducting CPW transmission lines,
high-quality inductors, and very low series resistance capacitors
[4]. This enables broadband lumped-element Wilkinson power
dividers with very low loss, compact size, and broad bandwidth (BW) compared to commercial and published dividers
in CMOS, stripline, and other technologies [5]–[10]. Fig. 1
is a micrograph showing a section of a fabricated Wilkinson
divider test circuit with a design frequency of 20 GHz and BW
in excess of 10 GHz.
Here, the design of a lumped-element Wilkinson divider
unit cell is presented, followed by a discussion of fabrication,
and then cryogenic measurement results are shown from 10 to
30 GHz. Next, a four-level binary balanced divider utilizing
these unit cells was designed to meet the challenge of increasing
the number of junction arrays under parallel microwave excitation on a chip. Cryogenic measurements are performed on
the 16-way Wilkinson divider in a back-to-back divider/10-dB
attenuator/combiner configuration. This configuration preserves the desired matched-load -way divider in a two-port
through test circuit suitable for insertion-loss measurements. A
0018-9480/$26.00 © 2009 IEEE
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L
TABLE I
45
AND C VALUES FOR =
EQUIVALENT SECTIONS
OF VARIOUS USEFUL IMPEDANCES AT 20 GHz
a negligible penalty in loss and a very modest 30% increase in
area for approximately double the BW compared to that of a
single-section lumped-element Wilkinson divider.
A. Design
The values for a cannonical low-pass network with series
and shunt capacitance
of electrical length
inductance
in radians, frequency
in hertz, and characteristic impedance
in ohms are given by [11]
and
Fig. 2. 20-GHz broadband Wilkinson power divider circuit schematics. (a) Distributed 50-
input and output impedance divider. (b) Forward even-mode divider half-circuit Butterworth transformers. (c) Divider with =4 transmission
line elements replaced by 5 section lumped-element equivalents.
prototype 10-V programmable Josephson voltage standard is
also built and utilized as an on-chip power detector to evaluate
the amplitude balance of the divider. Finally, the unit cell is
successfully implemented in Triquint’s commercial TQPED1
process at room temperature with a modest penalty in area and
loss.
II. BROADBAND LUMPED ELEMENT CPW WILKINSON
A lumped-element Wilkinson power divider can be synthesections of transmissized by replacing the typical physical
sion line with lumped-element equivalent networks [11]. This
lumped-element topology allows a tenfold reduction in physical
length. The availability of superconducting planar spiral inducequivalent sections
tors allows multiple lumped-element
in a broadband Butterworth configuration [5], [12]–[15]. The
two-section Wilkinson power divider, shown in Fig. 2, incurs
1Certain commercial equipment, instruments, or materials are identified in
this paper in order to specify the experimental procedure adequately. Such identification is not intended to imply recommendation or endorsement by NIST, nor
is it intended to imply that the materials or equipment identified are necessarily
the best available for the purpose.
(1)
While used most often to realize
transmission-line segments, these expressions can be used to generate arbitrary length
and impedance transmission-line equivalents. This allows pseudodistributed circuit design in lumped elements, examples of
which are shown in Table I.
A broadband Wilkinson power divider can be synthesized
matching section from 100 to
by replacing the single
50 in the forward even-mode Wilkinson analysis circuit with
multiple
sections designed for a Butterworth/binomial
response. A published study of several possible distributed
broadband Wilkinson designs shows that a design with two
sections has a broader BW than a design
series (low-pass)
with one series (low-pass) and one shunt (high-pass)
section, trading BW for out-of-band isolation [13]. A reduced
component count and smaller area can be achieved by placing
section before, rather than after, the
the additional series
split between the two legs of the Wilkinson, as in Fig. 2(a),
with negligible effect on divider performance.
Analysis of the even-mode half circuit, shown in Fig. 2(b),
yields design equations for the characteristic impedance of each
and
in terms of the desired input and output port
section
and
, respectively,
impedances
(2)
(3)
These expressions are derived from the general binomial transformer equations [14]
(4)
(5)
Here,
is the total number of binomial transformer sections
and is the current section.
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ELSBURY et al.: BROADBAND LUMPED-ELEMENT INTEGRATED
-WAY POWER DIVIDERS FOR VOLTAGE STANDARDS
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TABLE II
NIST IC FABRICATION PROCESS LAYER STACK. Nb TRACES ARE MODELED
IN HFSS USING PEC. NB1 AND NB2 ARE USED WITH THE SiO
INTERLAYER DIELECTRIC TO FORM MIM CAPACITORS. THE JJ
BARRIER IS NOT USED IN THE DIVIDER CIRCUITS
B. Layout and Fabrication
Fig. 3. Layout of the broadband lumped-element 20-GHz Wilkinson from
Fig. 2(c). Red (in online version) hatch is Nb1, black hatch is Nb1–2 via,
blue (in online version) hatch is Nb2 and green (in online version) hatch
is AuPd. Solid blue lines (in online version) in the CPW ground planes show
the HFSS simulation cell boundaries. Approximate divider dimensions are
400 m (0:07) 300 m (0:05) with minimum trace width and spacing of
1.5 m (0:0002).
2
These distributed sections can then be converted to LC
sections using (1), as shown in Fig. 2(c). For a two-stage
broadband Wilkinson centered at 20 GHz, the desired
section impedances and corresponding L and C values are
shown in Table I. These values are well within the range of
impedance values realizable in the NIST IC process discussed
in Section II-B.
The lumped-element Wilkinson models derived from the
closed-form expressions were optimized in Agilent’s ADS
circuit simulator to obtain the desired tradeoff between BW and
reflections. Initial layout geometries were obtained based on
an ideal parallel plate capacitor model and Stanford Spiralcalc
[16] planar spiral inductor models, then simulated and tuned as
single L and C elements embedded in a CPW transmission line
using Ansoft’s High Frequency Structure Simulator (HFSS)
v10 3-D FEM simulator. Superconducting Nb traces are modeled with 3-D perfect electric conductors (PECs) in HFSS. The
solid blue lines (in the online version) in the ground planes of
the divider layout in Fig. 3 indicate the HFSS cell boundaries.
The HFSS results were exported as -parameter blocks into
ADS for further tuning of the entire circuit via this hybrid simulation. This final design was then verified using a complete
HFSS simulation. For comparison: the single L or C element
HFSS simulations required less than 50 000 tetrahedra, a few
hundred megabytes of memory, and less then 20 min of processor time per element simulation; the hybrid simulations in
ADS utilized a few megabytes of memory and less than 1 min;
the full divider simulations in HFSS required 141 000 tetrahedra, over 4 GB of memory space, and 7 h of real time to solve
on a 32-bit Pentium D 3.4 GHz with 3-GB RAM.
The NIST superconducting IC fabrication process layer stack
is shown in Table II. Minimum linewidths and spacings are
,
1 m for all layers. This process generates resistors of 2
metal–insulator–metal (MIM) capacitors of 0.1 fF m , and
under-passed spiral inductors in the range of 100–5000 pH.
sections with
and
integrated into Nb on Si
Lumped
CPW with a center conductor width of 16 m and gap of 8 m
can be realized in a 130- m length of CPW, as compared to
section at 20 GHz.
1600 m for a distributed
Fig. 3 shows a typical layout of a 20-GHz center-frequency broadband lumped-element Wilkinson power divider with 50- input and output impedances. Approximate dimensions of this lumped-element Wilkinson are
300 m
, as compared with a
400 m
standard distributed Wilkinson at 20 GHz, which would be
400 m
in this
approximately 1600 m
technology.
Several test circuits were considered to facilitate testing,
shown in Fig. 4. In the test circuit 1, Fig. 4(a), no on-chip
termination is required, but the port 2 and port 3 -parameter
responses are not directly measurable. In addition, power
reflections between the two dividers can cause deviations in
the measurement from the desired matched load case. Circuit 2
[see Fig. 4(b)] allows port 2 characterization, but introduces
another unknown in the on-chip termination. Circuit 3 [see
Fig. 4(c)] uses an on-chip resistive termination at port 1. This
allows isolation characterization of port 2 to port 3 with the
caveat of a separate physical device and possible process
variations across the wafer. Only circuits 2 and 3 were realized
for Wilkinson unit-cell testing. All superconducting circuits
reported here were fabricated in the NIST Boulder Quantum
Device Fabrication Facility.
C. Testing
Measurements were performed with an Agilent 8722ES
vector network analyzer (VNA). Calibration was accomplished
using on-chip through-reflect (short)-line (1.5 mm) (TRL)
standards custom-fabricated with a band of 8–35 GHz at 4K
dewar. The repeataimmersed in a liquid helium
bility of the measurements is limited by several factors in the
test setup. The calibration procedure requires three thermal
cycles from room temperature to 4 K, boiling 1 L of helium.
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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 57, NO. 8, AUGUST 2009
Fig. 4. Three-port Wilkinson divider to two-port network analysis conversion
circuits. (a) Circuit 1: back-to-back dividers. (b) Circuit 2: port 3 terminated
on-chip. (c) Circuit 3: port 1 terminated on-chip.
Fig. 5. Broadband lumped-element Wilkinson (Fig. 3) HFSS simulated data
(blue dashed lines in online version) and measurement results (red solid lines
in online version) from test circuit 2 [see Fig. 4(b)] using 4K TRL calibration
on-chip. S is marked with , S with 2, and S with .
+
TABLE III
BROADBAND DIVIDER MEASUREMENT SUMMARY COMPARING THE NIST
SUPERCONDUCTING IC PROCESS, SECTION II, AND THE TRIQUINT
COMMERCIAL TQPED PROCESS , SECTION IV. SUMMARY DATA IS
CALCULATED FROM THE RESULTS SHOWN IN FIGS. 5, 6, AND 11
This changes the thermal gradient along the 1.2-m cryoprobe
coaxial cable; hence, its electrical length and loss, with each
successive measurement. The chip contact is made via a pressure screw that engages a set of copper–beryllium (Cu–Be)
spring fingers with the gold–palladium (Au–Pd) coated pads
on the chip with only moderate repeatability. The economical
subminiature A (SMA) connectors used have resonances in the
upper end of the band of interest. A flip-chip bonded permanent
mounting solution has been developed by the authors to address these issues in the final programmable Josephson voltage
standard system [17], but is not practical for use with the many
test circuits and VNA calibration standards needed here.
Table III shows a summary of Wilkinson divider test circuit
measurement results. Fig. 5 shows a comparison of HFSS simulations and measurements for test circuit 2 from Fig. 4(b).
HFSS simulation and measurement results for test circuit 3 from
Fig. 4(c) are shown in Fig. 6. The 15–22-GHz band is considered the band of interest for this design, allowing for ample
tuning around the 20-GHz junction array design point. Average
Fig. 6. Broadband lumped-element Wilkinson (Fig. 3) HFSS simulated data
(blue dashed lines in online version) and measurement results (red solid lines
in online version) from test circuit 3 [see Fig. 4(c)] using 4K TRL calibration
on-chip, in red solid lines (in online version). S is marked with 2, S is
marked with .
in-band values in Table III are computed as the base-10 logarithm of mean power
Mean
(6)
Insertion loss (IL) for this work is defined as
(7)
is asBy circuit symmetry and from simulation results,
sumed to be approximately equal to
for IL calculations in
Table III.
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ELSBURY et al.: BROADBAND LUMPED-ELEMENT INTEGRATED
-WAY POWER DIVIDERS FOR VOLTAGE STANDARDS
2059
Fig. 7. Simplified schematic of the balanced divider/attenuator/combiner configuration test circuit, showing broadband lumped-element Wilkinson power dividers,
=4 lumped 5 sections for reflection cancellation, 10-dB isolation attenuators, and 1.2-pF coupling capacitors between the third and fourth levels of division and
combination. Simulated transmission line interconnects and bends are not shown. The dotted cut plane indicates the position of the junction arrays in the 10-V
programmable Josephson voltage standard.
III. BALANCED 16-WAY POWER DIVIDER
The concept of a balanced divider/combiner (D/C), widely
used in broadband amplifier design [14], can be applied here to
achieve a many-way power division to many identical arrays of
junctions. A balanced divider relies upon the fact that each array
has a nearly identical return loss. By inserting an additional
transmission line between port 2 of the Wilkinson and the junction array, the round-trip reflection path is 180 longer than the
corresponding round-trip reflection path from the junction array
connected to port 3 of the Wilkinson. These two reflections are
out of phase at port 1 and cancel, leading to a well matched
and very broadband system. Many-way power division can be
achieved as shown in Fig. 7. This solution addresses the fundamental issue with 360 , round-trip in-phase reflection com-section binary power dividers rebining in -way evenported in [6]. Here, the total interconnect layout length between
delta between branches
dividers is unconstrained, only the
(implemented in lumped elements) is required.
the output, as well as the ability to measure IL through the device. The back-to-back circuit shown in Fig. 4(a) has a fundamental flaw of terminating a divider circuit with its own complex
output impedance, rather than the desired real 50- load needed
to obtain valid -parameters. To solve this problem 10-dB attenuators are monolithically integrated between the divider circuit
under test, and the combiner output circuit. A schematic of this
balanced divider/attenuator/combiner (D/A/C) configuration is
shown in Fig. 7.
Identical length 50- CPW superconducting transmission
lines were used to interconnect the divider, attenuators, and
sections were arranged such that the net
combiner; the
phase delays along any given division and recombination path
are equal. A 1.2-pF coupling capacitor was inserted between the
third and fourth levels of power division and recombination to
ac-couple each pair of junction arrays and enable connecting all
of the arrays in series at dc to achieve 10 V. A lithographically
identical 10-dB attenuator was fabricated on the same test chip
as the D/A/C to allow deembedding of the divider performance.
A. Design
A 16-way power split allows 16 junction arrays of 15 600
junctions [2] fabricated on a prototype 10-V programmable
Josephson voltage standard chip at 20 GHz reported in [3].
The chip area required for a 16-way divider on-chip is reduced
by a factor of 4 using the lumped-element Wilkinson dividers
50- LC sections, from Table I, compared to the
and
distributed matching sections. The
previously used single
entire 16-way divider network is simulated in ADS using the
hybrid simulation methodology discussed in Section II-A.
In order to appropriately characterize a many-way divider, a
test circuit is needed that preserves both the desired loading at
B. Testing
The 16-way D/A/C configuration test chip was evaluated in
the same manner as the Wilkinson divider chips, discussed in
Section II-C. A 16-way D/C test circuit without attenuators,
shown in Fig. 1, was also fabricated and tested to demonstrate
the utility of the added attenuators. Figs. 8 and 9 compare measured and simulated results from the 16-way balanced D/C and
D/A/C configurations, respectively. Table IV summarizes the
measurement data from both configurations and the 10-dB attenuator (10 dB A). The measured IL and return loss of the
back-to-back test configuration both improve markedly with the
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TABLE IV
16-WAY BALANCED DIVIDER SUMMARY. VALUES ARE CALCULATED FROM
THE MEASUREMENTS OF D/C CONFIGURATION (FIG. 8), THE ON-CHIP
10-dB ATTENUATOR, AND D/A/C CONFIGURATION (FIG. 9)
Fig. 8. D/C configuration measured versus simulated results for 16-way balanced broadband Wilkinson divider (Fig. 1). Hybrid HFSS 3-D FEM and ADS
circuit simulated data (blue dashed lines in online version), and measurements
using 4K TRL calibration on-chip (red solid lines in online version). S is
marked with , S is marked with 2, and IL is marked with . Note the
standing waves between the divider and the combiner apparent in the S measurement.
+
Fig. 10. Measured power division uniformity results from broadband
Wilkinson in 16-way balanced divider feeding a prototype 10-V chip with 16
arrays of 15 600 junctions at 15 GHz (red solid line in online version marked
), 19 GHz (blue dashed–dotted line in online version marked 2), and 22 GHz
(green dashed line in online version marked ). The x-axis indicates the
array number, coinciding with Fig. 7 with 1 at the bottom and 16 at the top.
The y -axis is the change from nominal source input power at which each
=I ratio (an indicator of equal microwave power
array exhibits a equal I
delivered to that array).
+
Fig. 9. D/A/C configuration 16-way balanced Wilkinson divider measured
versus simulated (Fig. 7) results. S and IL are calculated by deembedding
the 10-dB attenuator data from the D/A/C test configuration data. Hybrid HFSS
3-D FEM and ADS circuit simulated data (blue dashed lines in online version),
and measurements (red solid lines in online version) using 4K TRL calibration
on-chip. S is marked with , S is marked with 2, and IL is marked with .
+
incorporation of the 10-dB attenuators. This D/A/C configuration is a useful measurement technique for characterization of
many-port integrated dividers.
Assuming the loss in the division is the same as the loss in the
recombination, the average and maximum IL through a single
can be computed as half of the
16-way divider network
. The D/A/C measured data in Fig. 9 and
total for the D/C,
Table IV has been calculated by deembedding the measured IL
of a matched lithographically identical 10-dB attenuator on the
same chip. The 0.5-dB maximum 16-way power divider loss
is very small compared to the 3-dB cable loss incurred in the
1.2-m cryoprobe, or to any commercially available broadband
divider solution in the 15–22-GHz band. While not measured,
the simulated isolation of the 16-way divider is similar for adjacent branches, and improved for nonadjacent branches, when
compared to the single Wilkinson divider.
The bulk of the IL is due to the balanced out-of-phase divider
reflections producing a voltage drop across the Wilkinson isolation resistor before they cancel. This assertion is supported by
simulations, as well as the noted drop in IL with the addition of
the attenuators, suppressing the reflections from the combiner.
A tradeoff in a balanced divider, versus a standard corporate direflection canceling sections, is that the
vider without the
uniformity of division in simulations suffers slightly away from
section. By inspection, a balthe center frequency of the
anced divider will have a 90 phase progression between outputs rather than phase balance.
A prototype 10-V programmable Josephson voltage standard was fabricated using the 16-way balanced divider to
split a single microwave feed from a room temperature power
amplifier into 16 arrays of 15 600 junctions each [3]. The
dc-bias current range over which the Shapiro zero-voltage step
is quantized in the junction dc IV curve is a strong indicator
of microwave current through the junction [2]. This property
allows the arrays themselves to be used as an on-chip relative
power meter to evaluate the amplitude balance of the divider.
Fig. 10 shows the amplitude balance of the divider at 15, 19,
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ELSBURY et al.: BROADBAND LUMPED-ELEMENT INTEGRATED
-WAY POWER DIVIDERS FOR VOLTAGE STANDARDS
TABLE V
COMPARISON OF THIS WORK AND OTHER PUBLISHED AND COMMERCIALLY AVAILABLE POWER DIVIDERS SORTED BY
2061
N , THEN IL/BW
and 22 GHz across the 16 output arrays. This data is derived
for the top of the zero-voltage
from a measurement of
Shapiro step over a sweep of power from approximately 2 to
200 mW on-chip for all 16 arrays. The normalization by
helps account for junction variation across the wafer, where
is the junction critical current [1]. With the exception of
array 3, all of the arrays cross an arbitrarily selected constant
within a 1-dB range of input power, indicating a
good microwave power division amplitude balance. Array three
displayed an isolated junction fabrication defect and is omitted.
IV. DISCUSSION AND CONCLUSIONS
Table V shows a comparison of this work to other published
and commercially available -way power dividers. Comparisons can be made upon the basis of number of divider outputs,
, BW (defined by match and isolation specification
), BW,
maximum IL in band, IL, and size. Table V is sorted first by
, then by IL/BW to aid in this comparison. The availability
of superconducting low-loss inductors enables very large and
complex circuits including many
lumped sections to emulate distributed microwave circuit designs in a small fraction
of the area with very little penalty in loss. This work exhibits
the best BW and IL for its size scale, normalized across ,
when compared to published work and commercially available
devices.
The lumped-element Wilkinson divider shown in Fig. 2(c)
was also implemented in the Triquint commercial TQPED
GaAs monolithic microwave integrated circuit (MMIC) process
in 4- m-thick gold microstrip on a 100- m substrate. The port
1 and port 2 through test configuration shown in Fig. 4(b) was
designed and fabricated requiring an area of approximately
1200 m 1500 m. This normal metal design at room temperature exhibited a measured average IL of 0.6 dB compared
to the measured superconducting device average IL of 0.1 dB in
the 15–22-GHz band of interest, shown in Table III. The measured and simulated -parameters of this device are compared
Fig. 11. Broadband lumped-element TQPED Wilkinson simulated data (blue
dashed lines in online version) and measurement results (red solid lines in onis marked
line version) using room-temperature TRL calibration on-chip.
is marked with 2, and
is marked with . This device was fabriwith ,
cated using the commercial Triquint TQPED GaAs MMIC process and tested
at room-temperature. Port 3 is terminated with an on-chip resistor. The inset is
a micrograph of the fabricated device.
S
S
+
S
in Fig. 11 using wafer probe measurements with on-chip TRL
calibration. Even without the advantage of superconducting
inductors, this implementation compares favorably to other
published and commercial dividers, as shown in Table V. This
validates the broadband lumped-element design methodology
presented here for room-temperature IC design with a modest
penalty in loss and area.
In this work, very broadband low-loss compact lumped-element many-way Wilkinson power dividers were demonstrated
using NIST and Triquint TQPED microfabrication processes.
A balanced power division solution was presented to address the
-segfundamental in-phase reflections problem of an evenment many-way binary power divider [6]. This solution occu-segment dividers, and removes the
pies less area than three-
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constraints on the interconnect layout, at the cost of phase balance. Additionally the balanced divider solution improves the
divider match assuming phase and amplitude matched loads,
as is often the case for integrated devices. A back-to-back test
configuration for many-way dividers utilizing integrated 10-dB
attenuators was devised to present a 50- load at the divider
output while maintaining the ability to measure IL through the
device. The area and performance gains of these innovative circuits over conventional distributed power dividers are an enabling microwave technology for the NIST 10-V programmable
Josephson voltage standard.
ACKNOWLEDGMENT
The authors would like to thank Triquint, Hillsboro, OR, for
providing the IC fabrication services utilized to fabricate the
room-temperature devices reported here.
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Michael M. Elsbury (S’07) received the B.S. degree
in electrical engineering (magna cum laude) from the
University of Idaho, Moscow, in 2003, and is currently working toward the Ph.D. degree in electrical
engineering at the University of Colorado at Boulder.
While with the University of Idaho, he performed
undergraduate research in analog IC design and microwave circuits. He was an Undergraduate Intern
in analog IC design for three summers with both
Micron Technology and the Boeing Company. He
was then with the Boeing Company as an RF Integration Engineer for two years, during which time he supported the 737
AEW&C System Integration Laboratory. In 2005, he joined the Microwave
Active Antenna Group, University of Colorado at Boulder. His current
research, in collaboration with the National Institute of Standards and Technology (NIST), regards broadband superconducting K -band ICs to optimize
the microwave performance of Josephson voltage references and quantized
arbitrary signal generators. This work enables higher quantized output voltages and increased operating margins in systems deployed to the NIST
Calibration Laboratory.
Paul D. Dresselhaus was born on January 5, 1963,
in Arlington, MA. He received the B.S. degree
in both physics and electrical engineering from
the Massachusetts Institute of Technology (MIT),
Cambridge, in 1985, and the Ph.D. degree in applied
physics from Yale University, New Haven, CT, in
1991.
In 1999, he joined the Quantum Voltage Project,
National Institute of Standards and Technology
(NIST), Boulder, CO, where he has developed novel
superconducting circuits and broadband bias electronics for precision voltage waveform synthesis and programmable voltage
standard systems. While with Northrop Grumman for three years, he designed
and tested numerous gigahertz speed superconductive circuits including code
generators and analog-to-digital converters. He also upgraded the simulation
and layout capabilities at Northrop Grumman to be among the world’s best. His
previous research as a Postdoctoral Assistant with the State University of New
York (SUNY) at Stony Brook focused on the nanolithographic fabrication and
study of Nb–AlOx–Nb junctions for single-electron and single-flux quantum
applications, single-electron transistors and arrays in Al–AlOx tunnel junctions,
and the properties of ultra-small JJs.
Norman F. Bergren was born on March 28, 1959,
in Denver, CO. He received the Associate degree in
electronics from Front Range Community College,
Westminster, CO, in 1988.
He served six years in the U.S. Navy, four years
aboard the Fleet Ballistic Missile Submarine USS
Sam Rayburn SSBN 635. He was Leading Petty
Officer of the Torpedo Fire Control Division. In
1988, he joined the National Institute of Standards
and Technology (NIST), where he began testing
large-scale superconductors. In 1997, he became involved with superconducting electronics, fabricating superconducting quantum
interference devices (SQUIDS), and Qbits. Most recently, he has focused on
the fabrication and testing of Josephson voltage standards.
Charles J. Burroughs was born on June 18, 1966.
He received the B.S. degree in electrical engineering
from the University of Colorado at Boulder, in 1988.
He was with the National Institute of Standards
and Technology (NIST), Boulder, CO, initially as
a student, and since 1988, as a Permanent Staff
Member. While with NIST, he has been involved in
the area of superconductive electronics, including the
design, fabrication, and testing of Josephson voltage
standards and digital-to-analog and analog-to-digital
converters. He has authored or coauhoted 45 publications. He holds three patents in the field of superconducting electronics.
Authorized licensed use limited to: NIST Research Library. Downloaded on August 17, 2009 at 15:48 from IEEE Xplore. Restrictions apply.
ELSBURY et al.: BROADBAND LUMPED-ELEMENT INTEGRATED
-WAY POWER DIVIDERS FOR VOLTAGE STANDARDS
Samuel P. Benz (SM’00) was born in Dubuque, IA,
on December 4, 1962. He received the B.A. degree
(with a major in both physics and math) (summa cum
laude) from Luther College, Decorah, IA, in 1985,
and the M.A. and Ph.D. degrees in physics from Harvard University, Boston, MA, in 1987 and 1990, respectively.
In 1990, he joined the National Institute of Standards and Technology (NIST) as a National Research
Council (NRC) Postdoctoral Fellow and joined the
permanent staff in January 1992. He has been Project
Leader of NIST’s Quantum Voltage Project since October 1999. He has authored or coauthored 135 publications. He holds three patents in the field of
superconducting electronics. He has been involved in a broad range of topics
within the field of superconducting electronics, including JJ array oscillators,
single flux quantum logic, ac and dc Josephson voltage standards, and Josephson
waveform synthesis.
Dr. Benz is a member of Phi Beta Kappa and Sigma Pi Sigma. He was the
recipient of the U.S. Department of Commerce Gold Medal for Distinguished
Achievement. He was also the reicpient of an R. J. McElroy Fellowship
(1985–1988).
2063
Zoya Popović (S’86–M’90–SM’99–F’02) received
the Dipl.Ing. degree from the University of Belgrade, Serbia, Yugoslavia, in 1985, and the Ph.D.
degree from the California Institute of Technology,
Pasadena, in 1990.
Since 1990, she has been with the University
of Colorado at Boulder, where she is currently the
Hudson Moore Jr. Chaired Professor of Electrical
and Computer Engineering. In 2001, she was a
Visiting Professor with the Technical University of
Munich, Munich, Germany. Since 1991, she has
graduated 32 Ph.D. students and currently advises a group of 16 graduate
students. Her research interests include high-efficiency, low-noise, and broadband microwave and millimeter-wave circuits, quasi-optical millimeter-wave
techniques for imaging, smart and multibeam antenna arrays, intelligent RF
front ends, RF optics, and wireless powering for batteryless sensors.
Dr. Popović is currently an associate editor for the IEEE TRANSACTIONS ON
MICROWAVE THEORY AND TECHNIQUES. She was the recipient of the 1993 and
2006 Microwave Prizes presented by the IEEE Microwave Theory and Techniques Society (IEEE MTT-S) for the best journal papers. She was the recipient
of the 1996 URSI Issac Koga Gold Medal. In 1997, Eta Kappa Nu students chose
her as a Professor of the Year. She was the recipient of a 2000 Humboldt Research Award for Senior U.S. Scientists from the German Alexander von Humboldt Stiftung. She was also the recipient of the 2001 Hewlett-Packard(HP)/
American Society for Engineering Education(ASEE) Terman Medal for combined teaching and research excellence.
Authorized licensed use limited to: NIST Research Library. Downloaded on August 17, 2009 at 15:48 from IEEE Xplore. Restrictions apply.
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