datasheet for VL470T5763A

datasheet for VL470T5763A
Product Specifications
PART NO.:
VL470T5763A-F7Y/E7Y/E6Y-S1
REV: 1.0
General Information
2GB 256Mx64 DDR2 SDRAM NON-ECC UNBUFFERED SODIMM 200-PIN
Description
The VL470T5763A is a 256Mx64 DDR2 SDRAM high density SODIMM. This memory module consists of eight CMOS
256Mx8 bit with 8 banks DDR2 synchronous DRAMs in BGA packages and a 2K EEPROM in an 8-pin TSSOP package.
This module is a 200-pin small-outline dual in-line memory module and is intended for mounting into a connector socket.
Decoupling capacitors are mounted on the printed circuit board for each DDR2 SDRAM.
Features
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Pin Description
200-pin, small-outline dual in-line memory module (SODIMM)
JEDEC pin out
Fast data transfer rates: PC2-6400, PC2-5300
VDD = VDDQ = 1.8V
JEDEC standard 1.8V (SSTL_18 compatible)
VDDSPD = 1.7V to 3.6V
Differential data strobe (DQS, DQS# ) option
Differential clock inputs (CK, CK#)
Four-bit pre-fetch architecture
DLL aligns DQ and DQS transition with CK
On-die termination (ODT)
Programmable CAS# latency: 5, 6 (DDR2-800), 5 (DDR2-667)
Write latency = Read latency - 1 tCK
Eight internal component banks for concurrent operation
Programmable burst; length (4, 8)
Adjustable data-output drive strength
Auto & self refresh, (8K/64ms refresh)
Serial presence detect (SPD)
Gold edge contacts
Lead-free, RoHS compliant
PCB: Height 30.00mm (1.181”), double sided components
Operating temperature (TOPER): -40OC to +85OC (module screening)
Pin Name
Function
A0~A14
Address Inputs
A10/AP
Address Input/ Autoprecharge
BA0~BA2
Bank Address Inputs
DQ0~DQ63
Data Input/Output
DQS0~DQS7
Data Strobes
DQS0#~DQS7#
Data Strobes Complement
ODT0
On-die Termination Control
CK0, CK0#, CK1, CK1#
Clock Input
CKE0
Clock Enables
CS0#
Chip Selects
RAS#
Row Address Strobes
CAS#
Column Address Strobes
WE#
Write Enable
DM0~DM7
Data Masks
VDD
Voltage Supply 1.8V +/- 0.1V
VSS
Ground
SA0~SA1
SPD Address
SDA
SPD Data Input/Output
SCL
SPD Clock Input
S1: Temperature screening
VDDSPD
SPD Voltage Supply 1.7V to 3.6V
DRAM DIE (option)
VREF
SSTL_18 Reference Voltage
DRAM MANUFACTURER
Y - HYNIX
NC
No Connect
Order Information:
VL470T5763A-F7 Y X - S1
MODULE SPEED
F7: PC2-6400 @ CL5
E7: PC2-6400 @ CL6
E6: PC2-5300 @ CL5
VL: Lead-free/RoHS
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1
Product Specifications
PART NO.:
VL470T5763A-F7Y/E7Y/E6Y-S1
REV: 1.0
Pin Configuration
200-PIN DDR2 SODIMM FRONT
200-PIN DDR2 SODIMM BACK
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
VREF
51
DQS2
101
A1
151
DQ42
2
VSS
52
DM2
102
A0
152
DQ46
3
VSS
53
VSS
103
VDD
153
DQ43
4
DQ4
54
VSS
104
VDD
154
DQ47
5
DQ0
55
DQ18
105
A10/AP
155
VSS
6
DQ5
56
DQ22
106
BA1
156
VSS
7
DQ1
57
DQ19
107
BA0
157
DQ48
8
VSS
58
DQ23
108
RAS#
158
DQ52
9
VSS
59
VSS
109
WE#
159
DQ49
10
DM0
60
VSS
110
CS0#
160
DQ53
11
DQS0#
61
DQ24
111
VDD
161
VSS
12
VSS
62
DQ28
112
VDD
162
VSS
13
DQS0
63
DQ25
113
CAS#
163
NC
14
DQ6
64
DQ29
114
OTD0
164
CK1
15
VSS
65
VSS
115
CS1#*
165
VSS
16
DQ7
66
VSS
116
A13
166
CK1#
17
DQ2
67
DM3
117
VDD
167
DQS6#
18
VSS
68
DQS3#
118
VDD
168
VSS
19
DQ3
69
NC
119
ODT1*
169
DQS6
20
DQ12
70
DQS3
120
NC
170
DM6
21
VSS
71
VSS
121
VSS
171
VSS
22
DQ13
72
VSS
122
VSS
172
VSS
23
DQ8
73
DQ26
123
DQ32
173
DQ50
24
VSS
74
DQ30
124
DQ36
174
DQ54
25
DQ9
75
DQ27
125
DQ33
175
DQ51
26
DM1
76
DQ31
126
DQ37
176
DQ55
27
VSS
77
VSS
127
VSS
177
VSS
28
VSS
78
VSS
128
VSS
178
VSS
29
DQS1#
79
CKE0
129
DQS4#
179
DQ56
30
CK0
80
CKE1*
130
DM4
180
DQ60
31
DQS1
81
VDD
131
DQS4
181
DQ57
32
CK0#
82
VDD
132
VSS
182
DQ61
33
VSS
83
NC
133
VSS
183
VSS
34
VSS
84
NC
134
DQ38
184
VSS
35
DQ10
85
BA2
135
DQ34
185
DM7
36
DQ14
86
A14
136
DQ39
186
DQS7#
37
DQ11
87
VDD
137
DQ35
187
VSS
38
DQ15
88
VDD
138
VSS
188
DQS7
39
VSS
89
A12
139
VSS
189
DQ58
40
VSS
90
A11
140
DQ44
190
VSS
41
VSS
91
A9
141
DQ40
191
DQ59
42
VSS
92
A7
142
DQ45
192
DQ62
43
DQ16
93
A8
143
DQ41
193
VSS
44
DQ20
94
A6
144
VSS
194
DQ63
45
DQ17
95
VDD
145
VSS
195
SDA
46
DQ21
96
VDD
146
DQS5#
196
VSS
47
VSS
97
A5
147
DM5
197
SCL
48
VSS
98
A4
148
DQS5
198
SA0
49
DQS2#
99
A3
149
VSS
199
VDDSPD
50
NC
100
A2
150
VSS
200
SA1
(*): These pins are not used on this module.
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2
Product Specifications
PART NO.:
VL470T5763A-F7Y/E7Y/E6Y-S1
REV: 1.0
Function Block Diagram
3 Ohms
CS0#
DQS4
DQS4#
DM4
DQS0
DQS0#
DM0
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM
CS# DQS DQS#
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
DQS1
DQS1#
DM1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
DM
D1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
DM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
DQS3
DQS3#
DM3
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
Serial PD
10 Ohms
CS0#: DDR2 SDRAMs D0~D7
BA0~BA2: DDR2 SDRAMs D0~D7
A0~A14: DDR2 SDRAMs D0~D7
RAS#: DDR2 SDRAMs D0~D7
CAS#: DDR2 SDRAMs D0~D7
WE#: DDR2 SDRAMs D0~D7
CKE0
ODT0
CS# DQS DQS#
D5
CS# DQS DQS#
D6
DQS7
DQS7#
DM7
DM
CS0#
BA0~BA2
A0~A14
RAS#
CAS#
WE#
D4
DQS6
DQS6#
DM6
DM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS2
DQS2#
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS# DQS DQS#
DQS5
DQS5#
DM5
DM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
A0
CS# DQS DQS#
D7
* Clock W iring
SCL
WP
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
A1
A2
Clock Input
DDR2 SDRAMs
*CK0, CK0#
*CK1, CK1#
4 SDRAMs
4 SDRAMs
SDA
SA0 SA1
* Wire per Clock Loading
Table/Wiring Diagrams
CKE0: DDR2 SDRAMs D0~D7
ODT0: DDR2 SDRAMs D0~D7
3 Ohms
VDDSPD
Notes:
1. Unless otherwise noted, resistor value are 22 Ohms
Serial SPD
VDD/VDDQ
D0-D7
VREF
D0-D7
VSS
D0-D7
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3
Product Specifications
PART NO.:
VL470T5763A-F7Y/E7Y/E6Y-S1
REV: 1.0
Absolute Maximum Ratings
Symbol
MIN
MAX
Unit
Voltage on VDD pin relative to VSS
-1.0
2.3
V
VDDQ
Voltage on VDDQ pin relative to VSS
-0.5
2.3
V
VDDL
Voltage on VDDL pin relative to VSS
-0.5
2.3
Voltage on any pin relative to VSS
-0.5
2.3
VDD
VIN, VOUT
TSTG
IL
IOZ
IVREF
Parameter
Storage temperature
Input leakage current; Any input 0V<VIN<VDD;
VREF input 0V<VIN<0.95V;
Other pins not under test = 0V
Output leakage current;
0V<VOUT<VDDQ; DQs and ODT are disabled
V
0
-55
100
Address, BA,
RAS#, CAS#, WE#
-16
16
uA
CS#, CKE, ODT
-16
16
uA
CK, CK#
-8
8
uA
DM
-2
2
uA
-5
5
uA
-16
16
uA
DQ, DQS, DQS#
VREF supply leakage current; VREF = Valid VREF level
C
DC Operating Conditions
Symbol
Min
Typical
Max
Unit
Notes
Supply voltage
1.7
1.8
1.9
V
1
VDDQ
I/O supply voltage
1.7
1.8
1.9
V
4
VDDL
VDDL supply voltage
1.7
1.8
1.9
V
4
VREF
I/O reference voltage
0.49 x VDDQ
0.50 x VDDQ
0.51 x VDDQ
V
2
VREF-0.04
VREF
VREF+0.04
V
3
VDD
VTT
Parameter
I/O termination voltage
Note:
1. VDD, VDDQ must track each other. VDDQ must be less than or equal to VDD.
2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on
VREF may not exceed +/-1percent of the DC value. Peak-to-peak AC noise on VREF may not exceed +/-2 percent of VREF. This
measurement is to be taken at the nearest VREF bypass capacitor.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and
must track variations in the DC level of VREF.
4. VDDQ tracks with VDD; VDDL tracks with VDD.
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4
Product Specifications
PART NO.:
VL470T5763A-F7Y/E7Y/E6Y-S1
REV: 1.0
Operating Temperature Condition
Symbol
TOPER
Parameter
Rating
Operating temperature
Units
0
-40 to +85
C
Notes
1,2
Notes:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer
to JEDEC JESD51-2.
o
2. At -40 to +85 C, operation temperature range, all DRAM specifications will be supported.
Input DC Logic Level
All voltages referenced to VSS
Symbol
Parameter
Min
Max
Unit
VIH(DC)
Input High (Logic 1) Voltage
VREF + 0.125
VDDQ + 0.300
V
VIL(DC)
Input Low (Logic 0) Voltage
-0.300
VREF - 0.125
V
Min
Max
Unit
Input AC Logic Level
All voltages referenced to VSS
Symbol
Parameter
VIH(AC)
Input High (Logic 1) Voltage
VREF + 0.200
-
V
VIL(AC)
Input Low (Logic 0) Voltage
-
VREF - 0.200
V
Input/Output
Capacitance
0
TA=25 C, f=100MHz
Parameter
Symbol
DDR2-800
(-F7/-E7)
DDR2-667
(-E6)
Min
Max
Min
Max
Unit
Input capacitance (A0~A14, BA0~BA2, RAS#, CAS#, WE#)
CIN1
12
18
12
20
pF
Input capacitance (CKE0, ODT0, CS0#)
CIN2
12
18
12
20
pF
Input capacitance (CK0, CK0#, CK1, CK1#)
CIN3
8
12
8
12
pF
Input/Output capacitance (DQ, DQS, DQS#, DM)
CIO
6.5
7.5
6.5
7.5
pF
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5
Product Specifications
PART NO.:
VL470T5763A-F7Y/E7Y/E6Y-S1
REV: 1.0
IDD Specification
Condition
Symbol
-F7
-E7
-E6
Unit
Operating one bank active-pre-charge;
tCK= tCK(IDD); tRC= tRC(IDD); tRAS= tRAS MIN(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD0
760
760
720
mA
Operating one bank active-read-pre-charge;
IOUT = 0mA; BL = 4; CL = CL(IDD); AL = 0; tCK= tCK(IDD); tRC= tRC(IDD);
tRAS= tRAS MIN(IDD); tRCD= tRCD(IDD); CKE is HIGH, CS# is HIGH between valid
commands; Address bus inputs are SWITCHING; Data pattern is same as IDD4W.
IDD1
840
840
800
mA
Pre-charge power-down current;
All banks idle; tCK= tCK(IDD); CKE is LOW; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
IDD2P
96
96
96
mA
Pre-charge quiet standby current;
All banks idle; tCK= tCK(IDD); CKE is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
IDD2Q
400
400
360
mA
Pre-charge standby current;
All banks idle; tCK= tCK(IDD); CKE is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are SWITCHING.
IDD2N
440
440
400
mA
Active power-down current;
All banks open; tCK= tCK(IDD); CKE is LOW; Other
control and address bus inputs are STABLE; Data
bus inputs are FLOATING.
280
280
280
mA
IDD3P
144
144
144
mA
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
Active standby current;
All banks open; tCK= tCK(IDD); tRP= tRP(IDD); tRAS= tRAS MAX(IDD); CKE is HIGH, CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING.
IDD3N
640
640
560
mA
Operating burst write current;
All banks open; Continuous burst writes; BL = 8; CL = CL(IDD); AL = 0; tCK= tCK(IDD);
tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD4W
1920
1920
1600
mA
Operating burst read current;
All banks open; Continuous burst reads; IOUT = 0mA; BL = 4; CL = CL(IDD);
AL = 0; tCK= tCK(IDD); tRAS= tRAS MAX(IDD); tRP= tRP(IDD); CKE is HIGH, CS# is HIGH
between valid commands; Address bus inputs are SWITCHING; Data pattern is
same as IDD4W.
IDD4R
1760
1760
1480
mA
IDD5
1840
1840
1760
mA
120
120
mA
2440
2240
mA
Burst refresh current;
tCK=tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH; CS# is HIGH
between valid commands; Other control and address bus inputs are SWITCHING;
Data bus inputs are SWITCHING.
Self refresh current;
CK and CK# at 0V; CKE < 0.2V; Other control and address bus
inputs are FLOATING; Data bus inputs are FLOATING.
Normal
Operating bank interleave read current;
All bank interleaving reads; IOUT = 0mA; BL = 8; CL = CL(IDD);
AL = tRCD(IDD) - 1*tCK(IDD); tCK= tCK(IDD); tRC= tRC(IDD); tRRD = tRRD(IDD); tRCD = 1*tCK(IDD) ;
CKE is HIGH; CS# is HIGH between valid commands; Address bus inputs are
STABLE during DESELECTs; Data bus inputs are SWITCHING.
120
IDD7
2440
Notes: IDD specification is based on Hynix A-die components.
*: Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P ( CKE LOW) mode.
**: Value calculated reflects all module ranks in this operating condition.
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6
Product Specifications
PART NO.:
VL470T5763A-F7Y/E7Y/E6Y-S1
REV: 1.0
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
DDR2-800
(-F7/-E7)
Symbol
DDR2-667
(-E6)
Unit
Min
Max
Min
Max
Clock Timing
CL6
tCK(6)
2,500
8,000
-
-
ps
CL5
tCK(5)
3,000
8,000
3,000
8,000
ps
CK high-level width
tCH(avg)
0.48
0.52
0.48
0.52
tCK
CK low-level width
tCL(avg)
0.48
0.52
0.48
0.52
tCK
Half clock period
tHP
MIN
(tCH, tCL)
-
MIN
(tCH, tCL)
-
ps
Clock jitter
tJIT
-100
100
-125
125
ps
DQ output access time from CK/CK#
tAC
-400
400
-450
+450
ps
Data-out high impedance window from CK/CK#
tHZ
-
tAC(MAX)
-
tAC(MAX)
ps
Data-out low impedance window from CK/CK#
tLZ
tAC(MiN)
tAC(MAX)
tAC(MiN)
tAC(MAX)
ps
DQ and DM input setup time relative to DQS
tDS
50
-
100
-
ps
DQ and DM input hold time relative to DQS
tDH
125
-
175
-
ps
DQ and DM input pulse width ( for each input)
tDIPW
0.35
-
0.35
-
tCK
Data hold skew factor
tQHS
-
300
-
340
ps
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
tQH
tHP - tQHS
-
tHP - tQHS
-
ps
DQS input high pulse width
tDQSH
0.35
-
0.35
-
tCK
DQS input low pulse width
tDQSL
0.35
-
0.35
-
tCK
DQS output access time from CK/CK#
tDQSCK
-350
+350
-400
+400
ps
DQS failing edge to CK rising-setup time
tDSS
0.2
-
0.2
-
tCK
DQS failing edge from CK rising-hold time
tDSH
0.2
-
0.2
-
tCK
DQS-DQ skew, DQS to last DQ valid, per group, per
access
tDQSQ
-
200
-
240
ps
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
DQS read preamble
tRPST
0.4
0.6
0.4
0.6
tCK
DQS read preamble
tWPRE
0.35
-
0.35
-
tCK
DQS read preamble
tWPST
0.4
0.6
0.4
0.6
tCK
Write command to first DQS latching transition
tDQSS
WL-0.25
WL+0.25
WL-0.25
WL+0.25
tCK
Clock Cycle Time
Data Timing
Data Strobe Timing
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7
Product Specifications
PART NO.:
VL470T5763A-F7Y/E7Y/E6Y-S1
REV: 1.0
AC TIMING PARAMETERS & SPECIFICATIONS
Parameter
DDR2-800
(-F7/-E7)
Symbol
Min
DDR2-667
(-E6)
Max
Unit
Min
Max
Command and Address Timing
Address and control input pulse width for each input
tIPW
0.6
-
0.6
-
tCK
Address and control input setup time
tIS
175
-
200
-
ps
Address and control input hold time
tIH
250
-
275
-
ps
tCCD
2
-
2
-
ps
ACTIVE to ACTIVE (same bank) command
tRC
57.5/60
-
60
-
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
7.5
-
7.5
-
ns
ACTIVE to READ or WRITE delay
tRCD
12.5/15
-
15
-
ns
Four Bank Activate period
tFAW
35
-
37.5
-
ns
ACTIVE to PRECHARGE command
tRAS
45
70,000
45
70,000
ns
Internal READ to precharge Command delay
tRTP
7.5
-
7.5
-
ns
Write recovery time
tWR
15
-
15
-
ns
Auto precharge write recovery + precharge time
tDAL
t WR+tnRP
-
t WR+tnRP
-
nCK
Internal WRITE to READ Command delay
CAS# to CAS# command delay
tWTR
7.5
-
7.5
-
ns
PRECHARGE command period
tRP
15
-
15
-
ns
LOAD MODE command cycle time
tMRD
2
-
2
-
tCK
tDELAY
tIS+tCK
+tIH
-
tIS+tCK
+tIH
-
ns
tRFC
195
-
195
-
ns
CKE low to CK, CK# uncertainty
Self Refresh
Refresh to Active or Refresh to Refresh command
interval
Average periodic Refresh interval
tREFI
-
7.8
-
7.8
us
Exit Self Refresh to non-READ command
tXSNR
t RFC(MIN) +10
-
t RFC(MIN) +10
-
ns
Exit Self Refresh to READ
tXSRD
200
-
200
-
tCK
tAOND
2
2
2
2
tCK
ODT turn-on
tAON
t AC(MIN)
t AC(MAX)+ 700
t AC(MIN)
t AC(MAX)+ 700
ps
ODT turn-off delay
tAOFD
2.5
2.5
2.5
2.5
tCK
ODT turn-off
tAOF
t AC(MIN)
t AC(MAX)+ 600
t AC(MIN)
t AC(MAX)+ 600
ps
ODT
ODT turn-on delay
2tCK +
ODT turn-on(power-down mode)
tAONPD
t AC(MIN)+
2,000
ODT turn-off (power-down mode)
tAOFPD
t AC(MIN)+
2,000
ODT to power-down entry latency
tANPD
3
ODT power-down exit latency
tAXPD
8
-
tOIT
0
1,200
OCD drive mode output delay
t AC(MAX)+
1,000
2.5tCK +
t AC(MAX)+
1,000
-
t AC(MIN)+
2,000
2tCK +
t AC(MAX)+
1,000
2.5tCK +
t AC(MAX)+
1,000
ps
-
tCK
8
-
tCK
0
1,200
ps
t AC(MIN)+
2,000
3
ps
Power Down
Exit active power-down to READ command, MR[bit12=0]
tXARD
2
-
2
-
tCK
Exit active power-down to READ command, MR[bit12=1]
tXARDS
8-AL
-
7-AL
-
tCK
Exit precharge power-down to any non-READ command
tXP
2
-
2
-
tCK
CKE minimum high/low time
tCKE
3
-
3
-
tCK
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
8
Product Specifications
PART NO.:
VL470T5763A-F7Y/E7Y/E6Y-S1
REV: 1.0
Package Dimensions
FRONT VIEW
3.40
MAX
67.60
4.0 +/- 0.10 (2X)
30.00
1.80 (2X)
TYP
20.00
6.00 TYP
0.5 R
PIN 1
2.00 TYP
0.60 TYP
1.0 +/- 0.10
PIN 199
0.45 TYP
1.0 +/- 0.10
63.60 TYP
BACK VIEW
3.50 TYP
2.55 TYP
4.20 TYP
PIN 200
47.40
TYP
11.40
TYP
16.26
TYP
PIN 2
Note: 1. All dimension are in millimeters with tolerance +/- 0.15mm unless otherwise specified.
2. The dimensional diagram is for reference only.
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
9
Product Specifications
PART NO.:
VL470T5763A-F7Y/E7Y/E6Y-S1
REV: 1.0
Revision History:VN-081009
Date
12/01/09
Rev.
Page
1.0
All
Changes
Spec release
Tel 949.888.2444 – 30052 Tomas, Rancho Santa Margarita, CA 92688 USA – w w w .virtium.com
10
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