DM54194 4-Bit Bidirectional Universal Shift Registers General Description This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a shift register; it features parallel inputs, parallel outputs, right-shift and left-shift serial inputs, operating-mode-control inputs, and a direct overriding clear line. The register has four distinct modes of operation, namely: Parallel (broadside) load Shift right (in the direction QA toward QD) Shift left (in the direction QD toward QA) Inhibit clock (do nothing) Synchronous parallel loading is accomplished by applying the four bits of data and taking both mode control inputs, S0 and S1, high. The data is loaded into the associated flipflops and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is accomplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial data for this mode is entered at the shift-right data input. When S0 is low and S1 is high, data shifts left synchronously and new data is entered at the shift-left serial input. Clocking of the flip-flop is inhibited when both mode control inputs are low. The mode controls of the DM54194/ DM74194 should be changed only while the clock input is high. Features Y Y Y Y Y Y Parallel inputs and outputs Four operating modes: Synchronous parallel load Right shift Left shift Do nothing Positive edge-triggered clocking Direct overriding clear Typical clock frequency 36 MHz Typical power dissipation 195 mW Connection Diagram Dual-In-Line Package TL/F/6564 – 1 Order Number DM54194J or DM54194W See NS Package Number J16A or W16A C1995 National Semiconductor Corporation TL/F/6564 RRD-B30M105/Printed in U. S. A. DM54194 4-Bit Bidirectional Universal Shift Registers June 1989 Absolute Maximum Ratings (Note) Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage 7V Input Voltage 5.5V Operating Free Air Temperature Range b 55§ C to a 125§ C DM54 b 65§ C to a 150§ C Storage Temperature Range Recommended Operating Conditions Symbol VCC Supply Voltage VIH High Level Input Voltage VIL Low Level Input Voltage IOH High Level Output Current IOL Low Level Output Current fCLK Clock Frequency (Note 4) tW Pulse Width (Note 4) tSU DM54194 Parameter Units Min Nom Max 4.5 5 5.5 V 2 V 0 Setup Time (Note 4) Clock 20 Clear 20 Mode 30 Data 20 tH Hold Time (Note 4) tREL Clear Release Time (Note 4) TA Free Air Operating Temperature 36 0.8 V b 0.8 mA 16 mA 25 MHz ns ns 0 ns 25 ns b 55 125 §C Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min Typ (Note 1) Max Units b 1.5 V VI Input Clamp Voltage VCC e Min, II e b12 mA VOH High Level Output Voltage VCC e Min, IOH e Max VIL e Max, VIH e Min VOL Low Level Output Voltage VCC e Min, IOL e Max VIH e Min, VIL e Max II Input Current @ Max Input Voltage VCC e Max, VI e 5.5V IIH High Level Input Current VCC e Max, VI e 2.4V 40 mA IIL Low Level Input Current VCC e Max, VI e 0.4V b 1.6 mA IOS Short Circuit Output Current VCC e Max (Note 2) b 57 mA ICC Supply Current VCC e Max (Note 3) 63 mA 2.4 3.4 0.2 b 20 39 V 0.4 V 1 mA Note 1: All typicals are at VCC e 5V, TA e 25§ C. Note 2: Not more than one output should be shorted at a time. Note 3: With all outputs open, inputs A through D grounded, and 4.5V applied to S0, S1, CLEAR and the serial inputs, ICC is tested with a momentary ground, then 4.5V applied to CLOCK. Note 4: TA e 25§ C and VCC e 5V. 2 Switching Characteristics at VCC e 5V and TA e 25§ C (See Section 1 for Test Waveforms and Output Load) Symbol RL e 400X, CL e 15 pF From (Input) To (Output) Parameter Min Units Max fMAX Maximum Clock Frequency tPLH Propagation Delay Time Low to High Level Output Clock to Q 25 MHz 22 ns tPHL Propagation Delay Time High to Low Level Output Clock to Q 26 ns tPHL Propagation Delay Time High to Low Level Output Clear to Q 30 ns Function Table Inputs Mode Clear L H H H H H H H Clock S1 S0 X X H L L H H L X X H H H L L L X L u u u u u X Outputs Serial Parallel Left Right A B C D X X X X X H L X X X X H L X X X X X a X X X X X X X b X X X X X X X c X X X X X X X d X X X X X QA QB QC QD L QA0 a H L QBn QBn QA0 L QB0 b QAn QAn QCn QCn QB0 L QC0 c QBn QBn QDn QDn QC0 L QD0 d QCn QCn H L QD0 H e High Level (steady state), L e Low Level (steady state), X e Don’t Care (any input, including transitions) u e Transition from low to high level; a, b, c, d e The level of steady state input at inputs A, B, C, or D, respectively QA0, QB0, QC0, QD0 e The level of QA, QB, QC, or QD, respectively, before the indicated steady state input conditions were established. QAn, QBn, QCn, QDn e The level of QA, QB, QC, respectively, before the most recent transition of the clock. u 3 Logic Diagram 194 TL/F/6564 – 2 Timing Diagram Typical Clear, Load, Right-Shift, Left-Shift, Inhibit and Clear Sequences TL/F/6564 – 3 4 Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number DM54194J NS Package Number J16A 5 DM54194 4-Bit Bidirectional Universal Shift Registers Physical Dimensions inches (millimeters) (Continued) 16-Lead Ceramic Flat Package (W) Order Number DM54194W NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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