HD3SS3220 USB Type-C DRP Port Controller with SuperSpeed 2:1 MUX

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HD3SS3220

SLLSES1 – DECEMBER 2015

HD3SS3220 USB Type-C DRP Port Controller with SuperSpeed 2:1 MUX

1 Features

1

• USB Type-C Port Controller with Integrated 2:1

SuperSpeed Mux

• Compatible to USB Type-C™ Specifications

• Supports USB 3.1 G1 and G2 up to 10 Gbps

• Supports up to 15 W of Power Delivery with 3-A

Current Advertisement and Detection

• Mode Configuration

– Host Only – DFP/Source

– Device Only – UFP/Sink

– Dual Role Port - DRP

• Channel Configuration (CC)

– Attach of USB Port Detection

– Cable Orientation Detection

– Role Detection

– Type-C Current Mode (Default, Mid, High)

• V

(BUS)

Cables

Detection and VCONN Support for Active

• Audio and Debug Accessory Support

• Supports for Try.SRC and Try.SNK DRP Modes

• Configuration Control through GPIO and I

2

C

• Low Active and Standby Current Consumptions

• Industrial Temperature Range of –40 to 85°C

3 Description

HD3SS3220 is a USB SuperSpeed (SS) 2:1 mux with

DRP port controller. The device provides Channel

Configuration (CC) logic and 5V VCONN sourcing for ecosystems implementing USB Type-C.

The

HD3SS3220 can be configured as a Downstream

Facing Port (DFP), Upstream Facing Port (UFP) or a

Dual Role Port (DRP) making it ideal for any application.

The HD3SS3220, in DRP mode, alternates presenting itself as a DFP or UFP according to the

Type-C specifications. The CC logic block monitors the CC1 and CC2 pins for pull-up or pull-down resistances to determine when a USB port has been attached and its port role. Once a USB port has been attached, the CC logic also determines the orientation of the cable and configures the USB SS mux accordingly. Finally, CC logic advertises or detects

Type-C current mode – Default, Mid, or High in DFP and UFP modes respectively.

Excellent dynamic characteristics of the integrated mux allow switching with minimum attenuation to the

SS signal eye diagram and very little added jitter. The device’s switch paths deploy adaptive common mode voltage tracking resulting identical channel despite different common mode voltage for RX and TX channels.

2 Applications

• USB Host, Device, Hub

• Mobile Phones, Tablets and Notebooks

• USB Peripherals such as Thumb Drives, Portable

Hard Disks, Set Top Box space

Simplified Schematic

PART NUMBER

HD3SS3220

Device Information

(1)

PACKAGE BODY SIZE (NOM)

VQFN RNH (30) 2.50 mm x 4.50 mm

HD3SS3220I

(1) For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application

VDD5 VCONN

VBUS_DET

VBUS

Detection

Channel

Configuration

Mode

Configuration and Detection

CC1

CC2

I2C Controller GPIOs

TX

RX

USB

SS

Mux

TX2

RX2

TX1

RX1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

HD3SS3220


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1

Features ..................................................................

1

2

Applications ...........................................................

1

3

Description .............................................................

1

4

Revision History.....................................................

2

5

Pin Configuration and Functions .........................

3

6

Specifications.........................................................

5

6.1

Absolute Maximum Ratings ......................................

5

6.2

ESD Ratings..............................................................

5

6.3

Recommended Operating Conditions .......................

5

6.4

Thermal Information ..................................................

6

6.5

Electrical Characteristics...........................................

6

6.6

Timing Requirements ................................................

8

7

Detailed Description ............................................

10

7.1

Overview .................................................................

10

7.2

Functional Block Diagram .......................................

12

7.3

Feature Description.................................................

13

Table of Contents

7.4

Device Functional Modes........................................

16

7.5

Programming...........................................................

18

7.6

Register Maps ........................................................

19

8

Application and Implementation ........................

23

8.1

Application Information............................................

23

8.2

Typical Application, DRP Port ................................

24

9

Power Supply Recommendations ......................

29

10

Layout...................................................................

30

10.1

Layout Guidelines .................................................

30

10.2

Layout ...................................................................

36

11

Device and Documentation Support .................

37

11.1

Community Resources..........................................

37

11.2

Trademarks ...........................................................

37

11.3

Electrostatic Discharge Caution ............................

37

11.4

Glossary ................................................................

37

12 Mechanical, Packaging, and Orderable

Information ...........................................................

37

4 Revision History

DATE

December 2015

REVISION

*

NOTES

Initial release.

2

Submit Documentation Feedback

Product Folder Links:

HD3SS3220

Copyright © 2015, Texas Instruments Incorporated

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5 Pin Configuration and Functions

RNH Package

30 Pin (VQFN)

Top View

CC2

CC1

CURRENT_MODE

PORT

VBUS_DET

30

1

4

5

2

3

8

9

6

7

29 28 27

25

26

SDA/OUT1

24

23

22

21

20

19

18

17

VCONN_FAULT

INT_N/OUT3

ADDR

TX2p

TXp

TXn

VCC33

RXp

Thermal

Pad

TX2n

RX2p

RX2n

TX1p

RXn

11

10 12

13

14 16

15

TX1n

HD3SS3220


NAME

CC2

CC1

CURRENT_

MODE

PORT

VBUS_DET

TXp

TXn

VCC33

RXp

RXn

DIR

ENn_MUX

GND

RX1n

RX1p

PIN

NO.

1

2

3

4

12

13, 28

14

15

5

6

7

8

9

10

11

I

G

I/O

I/O

I/O

I/O

I/O

I

I

I

I/O

I/O

P

I/O

I/O

O


Pin Functions

DESCRIPTION

Type-C Configuration channel signal 2

Type-C Configuration channel signal 1

Tri-level input pin to indicate current advertisement in DFP (or DFP in DRP) mode while in

GPIO mode. Don’t care in UFP mode. Provides the flexibility to advertise higher current without I

2

C. The pin has 250 K internal pull-down.

L – Low - Default – 900 mA

M - Medium (Install 500 K to VDD on the PCB) – 1.5 A

H - High (Install 10 K to VDD on the PCB) – 3 A

Tri-level input pin to indicate port mode. The state of this pin is sampled when HD3SS3220’s

ENn_CC is asserted low, and VDD is active. This pin is also sampled following a

I2C_SOFT_RESET.

H - DFP (Pull-up to VDD if DFP mode is desired)

NC - DRP (Leave unconnected if DRP mode is desired)

L - UFP (Pull-down or tie to GND if UFP mode is desired)

5-28V VBUS input voltage. VBUS detection determines UFP attachment. One 900K external resistor required between system VBUS and VBUS_DET pin.

Host/Device USB SuperSpeed differential Signal TX positive

Host/Device USB SuperSpeed differential Signal TX negative

3.3-V Power supply

Host/Device USB SuperSpeed differential Signal RX positive

Host/Device USB SuperSpeed differential Signal RX negative

Type-C plug orientation. Open drain output.

A pull-up resistor (that is, 200 K) must be installed for proper operation of the device.

Active Low MUX Enable:

L - Normal operation, and

H - Shutdown.

Ground

Type-C Port - USB SuperSpeed differential Signal RX1 negative

Type-C Port - USB SuperSpeed differential Signal RX1 positive


3


HD3SS3220

HD3SS3220


NAME

TX1n

TX1p

RX2n

RX2p

TX2n

TX2p

PIN

NO.

16

17

18

19

20

21

ADDR 22

INT_N/OUT3 23

VCONN_FAU

LT_N

24

SDA/OUT1 25

SCL/OUT2 26

ID

ENn_CC

VDD5

Thermal Pad

27

29

30

–

O

I

P

–

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I

O

O

I/O

I/O

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Pin Functions (continued)

DESCRIPTION

Type-C Port - USB SuperSpeed differential Signal TX1 negative

Type-C Port - USB SuperSpeed differential Signal TX1 positive

Type-C Port - USB SuperSpeed differential Signal RX2 negative

Type-C Port - USB SuperSpeed differential Signal RX2 positive

Type-C Port - USB SuperSpeed differential Signal TX2 negative

Type-C Port - USB SuperSpeed differential Signal TX2 positive

Tri-level input pin to indicate I

2

C address or GPIO mode:

H (connect to VDD5) - I

2

C is enabled and I2C 7-bit address is 0x67.

NC - GPIO mode (I2C is disabled)

L (connect to GND) - I

2

C is enabled and I2C 7-bit address is 0x47.

ADDR pin should be pulled up to VDD if high configuration is desired

The INT_N/OUT3 is a dual-function pin.

When used as the INT_N, the pin is an open drain output in I

2

C control mode and is an active low interrupt signal for indicating changes in I

2

C registers.

When used as OUT3, the pin is in audio accessory detect in GPIO mode:

H - no detection, and

L - audio accessory connection detected.

Open drain output. Asserted low when VCONN overcurrent detected.

The SDA/OUT1 is a dual-function pin.

When I2C is enabled (ADDR pin is high or low), this pin is the I

2

C communication data signal.

When in GPIO mode (ADDR pin is NC), this pin is an open drain output for communicating

Type-C current mode detect when the device is in UFP mode:

H – Default (900 mA) current mode detected, and

L – Medium (1.5 A) or High (3 A) Current Mode detected.

The SCL/OUT2 is a dual function pin.

When I

2

C is enabled (ADDR pin is high or low), this pin is the I

2

C communication clock signal.

When in GPIO mode (ADDR pin is NC), this pin is an open drain output for communicating

Type-C current mode detect when the device is in UFP mode:

H – Default or Medium current mode detected, and

L – High current mode detected.

Open drain output. Asserted low when CC pin detected device attachment when port is a source (DFP), or dual-role (DRP) acting as source (DFP).

Enable signal for CC controller. Enable is active low.

5-V Power supply

The thermal PAD must be connected to GND, see the Thermal Pad connection techniques

( SLMA002 ).

4



HD3SS3220


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6 Specifications

HD3SS3220


6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

5-V Supply Voltage

3.3-V Supply Voltage

Control Pins

Super-speed Differential Signal Pins

Storage temperature, T stg

VDD5

VCC33

CC1, CC2, ADDR, PORT, ID, DIR,

INT_N/OUT3, ENn_CC, ENn_MUX,

SDA/OUT1, SCL/OUT2

ENn_MUX, DIR

VBUS_DET

[RX/TX] [p/n], [RX/TX][2/1][p/n]

MIN

–0.3

–0.3

–0.3

–0.3

–0.3

–0.3

–65

MAX

6

4

VDD5 +0.3

VCC33 +0.3

4

2.5

150

UNIT

V

V

V

V

V

V

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

V

(ESD)

Electrostatic discharge

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

(1)

Charged-device model (CDM), per JEDEC specification JESD22-

C101

(2)

VALUE

±2000

±1500

UNIT

V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions. Pins listed as ±XXX V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process..

6.3 Recommended Operating Conditions


V

V

V

T

T

V

C

R

R

R

R

R

DD

(diff)

(cm)

A

A

(BUS)

(BULK)

(p_ODext)

(p_TLext)

(p_15A)

(p_3A)

(p_i2c_ext)

R

(VBUS)

C

(bus,I2c)

5-V Supply Voltage range

3.3-V Supply Voltage range

Supply range for I2C (SDA, SCL) pins

High speed signal pins differential voltage

High speed signal pins common mode voltage

Operating free-air/ambient temperature (HD3SS3220)

Operating free-air/ambient temperature (HD3SS3220I)

System V

(BUS) input voltage through 900-K resistor

Bulk capacitance on VCONN. Only when VCONN is on.

Disconnected when VCONN is off. Shall be placed on VDD5.

External Pull up resistor on Open Drain IOs (OUT1, OUT2,

INT/OUT3, ID, VCONN_FAULT_N, and DIR pins)

Tri-level input external pull-up resistor (PORT and ADDR pins)

External pull up resistor to advertise 1.5 A (CURRENT_MODE pin)

External pull up resistor to advertise 3 A (CURRENT_MODE pin)

External Pull up resistance on I

2

C bus

(Could be 4.7 K or higher. Nominal value listed)

External resistor on VBUS_DET pin

Total capacitive load for each I

2

C bus line

10

890

(1) With 200 mA VCONN current for VCONN ≥ 4.75 V at connector, VDD5 ≥ 5 V is recommended

MIN

4.5

(1)

3

1.65

0

0

0

–40

4

NOM

5

200

4.7

500

10

2.2

900

MAX

5.5

3.6

3.6

1.8

2

70

85

28

200

910

400

UNIT

V

V

V

V

PP

V

°C

°C

V

µF

K Ω

K Ω

K Ω

K

Ω

K Ω

K Ω pF



HD3SS3220


5

HD3SS3220


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6.4 Thermal Information

R

θJA

R

θJC(top)

R

θJB

ψ

JT

ψ

JB

R

θJC(bot)

THERMAL METRIC

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

(1)

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

HD3SS3220

RNH (VQFN)

30 PINS

60.9

50.4

22.8

1.7

22.6

12.1

UNIT

°C/W

°C/W

°C/W

°C/W

°C/W

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953 .

6.5 Electrical Characteristics


PARAMETER TEST CONDITIONS

Power Consumption

I

I

(ACTIVE)

CC

Current consumption in active mode- both CC controller and SS mux on

Current consumption in active mode – CC controller on and SS mux off

Current consumption in shutdown mode

ENn_CC/Mux = L

ENn_CC = L, ENn_Mux = H

I

(SHUTDOWN)

CC PINS

R

R

V

V

V

V

(CC_DB)

(CC_D)

(UFP_CC_USB)

(UFP_CC_MED)

(UFP_CC_HIGH)

(DFP_CC_USB)

Pulldown resistor when in dead-battery mode.

Pulldown resistor when in UFP or DRP mode.

Voltage level for detecting a DFP attach when configured as a UFP and DFP is advertising default current source capability.

Voltage level for detecting a DFP attach when configured as a UFP and DFP is advertising medium (1.5 A) current source capability.

Voltage level for detecting a DFP attach when configured as a UFP and DFP is advertising high (3 A) current source capability.

Voltage level for detecting a UFP attach when configured as a DFP and advertising default current source capability.

ENn_CC/Mux = H

V

V

V

(DFP_CC_MED)

(DFP_CC_HIGH)

(AC_CC_USB)

Voltage level for detecting a UFP attach when configured as a DFP and advertising 1.5-A current source capability.

Voltage level for detecting a UFP attach when configured as a DFP and advertising 3-A current source capability.

Voltage level for detecting an active cable attach when configured as a DFP and advertising default current source capability.

I

V

V

(AC_CC_MED)

(DFP_CC_HIGH)

CC(DEFAULT_P)

Voltage level for detecting an active cable attach when configured as a DFP and advertising 1.5-A current source capability.

Voltage level for detecting an active cable attach when configured as a DFP and advertising 3-A current source capability.

Default mode pull-up current source when operating in DFP or DRP mode.

I

I

CC(MED_P)

CC(HIGH_P)

Medium (1.5 A) mode pull-up current source when operating in DFP or DRP mode.

High (3 A) mode pull-up current source when operating in DFP or DRP mode.

3-Level Input Pins: PORT, ADDR, ENn_CC and CURRENT_MODE

V

IL

Low-level input voltage

MIN

4.1

4.6

0.25

0.7

1.31

1.51

1.51

2.46

0.15

0.35

0.75

64

166

34

TYP

0..7

0.2

5

5.1

5.1

1.6

1.6

2.6

0.2

0.4

0.8

80

180

330

MAX

0.9

6.1

5.6

0.61

1.16

2.04

1.64

1.64

2.74

0.25

0.45

0.84

96

194

356

0.4

UNIT

µA

µA

µA k Ω k Ω

V mA mA

µA

V

V

V

V

V

V

V

V

V

6




HD3SS3220

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Electrical Characteristics (continued)


V

M

V

IH

I

IH

I

IL

I

ID(LKG)

PARAMETER

Mid-Level (Floating) voltage (PORT, ADDR and

CURRENT_MODE pins)

High-level input voltage

High-level input current

Low-level input current

Current Leakage on ID pin

R

R

(pu)

(pd)

Internal pull-up resistance (PORT and ADDR pins)

Internal pull-down resistance (PORT and

ADDR pins)

R

(pd_CURRENT)

Internal pull-down resistance

(CURRENT_MODE pin)

R

(ENn_CC)

Internal pull-up resistance (ENn_CC pin)

Input Pins: ENn_MUX

TEST CONDITIONS

VDD5 = 0 V, ID = 5 V

V

IL


V

IH


I

I

IH

I

IL

High-level input current

Low-level input current

Open Drain Output Pins: OUT1, OUT2, INT_N/OUT3, ID, VCONN_FAULT_N, DIR

V

OL

Low-level signal output voltage

I2C– SDA/OUT1, SCL/OUT2 can Operate from 1.8/3.3 V (±10%)

(1)

I

OL

= –1.6 mA

V

IH

V

IL



V

OL

Low-level output voltage (open-drain)

VBUS_DET IO Pin (Connected to System VBUS Signal)

V

(BUS_THR)

R

(VBUS_DET_INT)

VCONN

VBUS threshold range

Internal pull-down resistor at VBUS_DET pin

I

OL

= –1.6 mA

R

ON

V

(TOL)

V

(pass)

On resistance of the VCONN power FET

Voltage tolerance on VCONN power FET

Voltage to pass through VCONN power FET

I

(VCONN)

VCONN current limit. VCONN will be disconnected above this value

MUX High Speed Performance Parameters

L

Differential Insertion Loss f = 0.3 Mhz f = 2.5 Ghz f = 5 Ghz

BW Bandwidth

R

O

X

L

IRR

TALK

Differential return loss

Differential OFF isolation

Differential Cross Talk f = 0.3 Mhz f = 2.5 Ghz f = 5 Ghz f = 0.3 Mhz f = 2.5 Ghz f = 5 Ghz f = 0.3 Mhz f = 2.5 Ghz f = 5 Ghz

R

ON

On resistance

(1) When using 3.3 V for I

2

C, customer must ensure VDD is above 3 V at all times.



HD3SS3220

HD3SS3220


MIN

0.28 x

VDD5

VDD5 - 0.3

20

–10

0.7 x

VCC33

–1

–1

1.05

2.95

225

–9

–79

–23

–20

–89

–34

–30

–0.43

–1.07

–1.42

8

–27

–9

TYP

588

1.1

275

1.1

3.3

95

300

MAX

0.56 x

VDD5

VDD5

20

10

10

UNIT

V

V

µA

µA

µA k

Ω

M Ω k Ω

M Ω

0.3 x

VCC33

1

1

0.4

V

V

µA

µA

0.4

0.4

3.8

1.25

5.5

5.5

375

V

V

V

V

V k Ω

Ω

V

V mA dB dB

Ghz dB

8 dB

Ω


7

HD3SS3220


6.6 Timing Requirements

t

I2C (SDA, SCL)

SU:DAT t

SU;STA t

HD,STA t

SU:STO t

BUF f

SCL t r t f

SS MUX

t

PD t

SW_ON t

SW_OFF t

SK_INTRA t

SK_INTER

Data setup time

Set-up time, SCL to start condition

Hold time,(repeated) start condition to SCL

Set up time for STOP condition

Bus free time between a STOP and START condition

SCL clock frequency; I

2

C mode for local I

2

C control

Rise time of both SDA and SCL signals

Fall time of both SDA and SCL signals

Switch propagation delay See

Figure 3

Switching time DIR-to-Switch ON See

Switching time DIR-to-Switch OFF See

Intra-pair output skew See

Inter-pair output skew See

Figure 3

Figure 3

Figure 2

Figure 2

V

CC

Axp

R

SC

= 50

Axn

R

SC

= 50

DIR

Figure 1. Test Setup

Bxp/Cxp

R

L

= 50

R

L

= 50

Bxn/Cxn

MIN

250

4.7

0.4

0.4

4.7

NOM www.ti.com

100

1000

300

80

0.5

0.5

5

20

MAX UNIT

ns

µs

µs

µs

µs ns ns ns ps

µs

µs ps ps

SEL

50% 50%

90%

V

OUT

10% t

SW_ON t

SW_OFF

Figure 2. Switch On and Off Timing Diagram

8



HD3SS3220


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V

IN

50%

50%

V

OUTp0

V

OUTn0

V

OUTp1

V

OUTn1

V

OUT t

1

50% t

P1 t

2 t

SK(O)

50% t

3

50% t

P2 t

4

Figure 3. Timing Diagrams and Test Setup

HD3SS3220




HD3SS3220


9

HD3SS3220


7 Detailed Description

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7.1 Overview

The USB Type-C ecosystem operates around a small form factor connector and cable that is flippable and reversible. Due to the nature of the connector, a scheme is needed to determine the connector orientation.

Additional schemes are needed to determine when a USB port is attached, determine the acting role of the USB port (DFP, UFP, DRP), and communicate Type-C current capabilities. These schemes are implemented over the

CC pins according to the USB Type-C specifications. The HD3SS3220 provides Configuration Channel (CC) logic for determining USB port attach/detach, role detection, cable orientation, and Type-C current mode. The

HD3SS3220 also contains several features such as VCONN sourcing, audio and debug accessory modes,

Try.SRC and Try.SNK DRP configurations which make this device ideal for source, sink or dual role applications with USB 2.0 or USB 3.1.

HD3SS3220 has integrated USB 3.0/3.1 SS/SS+ MUX with 2 channel 2:1 switching required to handle cable flips. The CC controller determines the orientation of the cable and controls the MUX selection. The device also provides this orientation signal as a GPIO signal DIR that can be used in the system for increased flexibility and features.

7.1.1 Cables, Adapters, and Direct Connect Devices

Type-C Specification defines several cables, plugs and receptacles to be used to attach ports. The HD3SS3220 supports all cables, receptacles, and plugs. The HD3SS3220 device does not support any USB feature which requires USB Power Delivery (PD) communications over CC lines, such as e-marking or alternate mode.

7.1.1.1 USB Type-C receptacles and Plugs

The following is alist of Type-C receptacles and plugs supported by the HD3SS3220 device:

• USB Type-C receptacle for USB2.0 and USB3.1 and full-featured platforms and devices

• USB Full-Featured Type-C plug

• USB2.0 Type-C Plug

7.1.1.2 USB Type-C Cables

The following is a list of Type-C cables supported by the HD3SS3220 device:

• USB Full-featured Type-C cable with USB3.1 full featured plug

• USB2.0 Type-C cable with USB2.0 plug

• Captive cable with either a USB Full featured plug or USB2.0 plug

7.1.1.3 Legacy Cables and Adapters

The HD3SS3220 supports legacy cable adapters as defined by the Type-C specifications. The cable adapter must correspond to the mode configuration of the HD3SS3220 device.

10



HD3SS3220


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Overview (continued)

VBUS

Rp (56 k Ÿ ±5%)

HD3SS3220


To System VBUS Detection

900 NŸ ±1%

VBUS_DET

CC

CC

HD3SS3220

Rd (5.1 k Ÿ ± 10%)

Legacy Host Adapter

Figure 4. Legacy Adapter Implementation Circuit

7.1.1.4 Direct Connect Device

HD3SS3220 supports the attaching and detaching of a direct connect device such as cradle dock.

7.1.1.5 Audio Adapters

Additionally, HD3SS3220 supports audio adapters for audio accessory mode, including:

• Passive Audio Adapte

• Charge Through Audio Adapter



HD3SS3220


11

HD3SS3220


7.2 Functional Block Diagram

VCC33

VBUS_DET

ENn_CC

DIR

INT_N/OUT3

ID

ADDR

PORT

VCONN_FAULT_N

CURRENT_MODE

SDA/OUT1

SCL/OUT2

TXP

TXN

RXP

RXN

Digital Controller

I2C

Slave

CSR

Connection and Cable

Detection

DIR

DIR = 0

USB

SS

MUX

DIR = 1

GND ENn_Mux

VDD5

VCO

NN

www.ti.com

CC1

CC2

TX2P

TX2N

RX2P

RX2N

TX1P

TX1N

RX1P

RX1N

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HD3SS3220


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HD3SS3220


7.3 Feature Description

The HD3SS3220 can be configured as a DFP, UFP, or DRP using the 3-level PORT pin. The PORT pin should be strapped high to VDD5 using a pull-up resistance to achieve DFP mode, low to GND for UFP mode or left floating for DRP mode on the PCB. This flexibility allows the HD3SS3220 to be used in a variety of applications.

The HD3SS3220 samples the PORT pin after reset and maintains the desired mode until the HD3SS3220 is reset again. It shall be static.

Table 1

shows the supported features in each mode.

Table 1. Supported Features for HD3SS3220 by Mode

PORT PIN

Supported Features

Port Attach/Detach

Cable Orientation

Current Advertisement

Current Detection

Audio Accessory

Debug Accessory Modes

Active Cable Detection

Try.SRC

Try.SNK

I2C/GPIO

Legacy Cables

VBUS Detection

VCONN

USB 3.1 G1 and G2 SS mux

Adaptive common mode tracking for SS channels

High

DFP Only

√

√

√

√

√

√

√

√

√

√

√

Low

UFP Only

√

√

√

√

√

√

√

√

√

√

NC

DRP

√

√

√(DFP)

√(UFP)

√

√

√(DFP)

√

√

√

√

√(UFP)

√(DFP)

√

√

7.3.1 DFP/Source – Downstream Facing Port

The HD3SS3220 can be configured as a DFP only by pulling the PORT pin high through a resistance to VDD.

The HD3SS3220 device can also be configured as a DFP-only device by changing the MODE_SELECT register default setting with PORT pin left floating. In DFP mode, the HD3SS3220 constantly presents R

(p) on both CC lines. In this mode, the HD3SS3220 will initially advertise default USB Type-C current. The Type-C current can be adjusted through CURRENT_MODE pin or I

2

C if the system wishes to increase the current advertisement.

The HD3SS3220 will adjust the R

(p) resistors to match the desired advertisement.

A DFP monitors the voltage level on the CC pins looking for the R

(d) termination of a UFP. When a UFP is detected and HD3SS3220 is in the attached. SRC state, the HD3SS3220 pulls the ID pin low to indicate to the system the port is attached to a device (UFP). Additionally, when a UFP is detected, the HD3SS3220 supplies

VCONN on the unconnected CC pin if R

(a) is also detected.

The following list describes the steps for enabling DFP through I

2

C:

1. Write a 1'b1 to DISABLE_TERM register (address 0x0A bit 0)

2. Write a 2'b10 to MODE_SELECT register (address 0x0A bits 5:4)


When configured as a DFP, the HD3SS3220 can operate with older USB Type-C 1.0 devices except for a USB

Type-C 1.0 DRP device. The HD3SS3220 cannot operate with a USB Type-C 1.0 DRP device. This limitation is a result of a backwards compatibility problem between USB Type-C 1.1 DFP and a USB Type-C 1.0 DRP.

7.3.2 UFP/Sink – Upstream Facing Port

The HD3SS3220 can be configured as a UFP only by pulling the PORT pin low to GND. In UFP mode, the

HD3SS3220 constantly presents Rd (pull-down resistors) on both CC pins.



HD3SS3220


13

HD3SS3220


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In UFP mode, the HD3SS3220 monitors the voltage level at the CC pins for attachment of a DFP and also to determine Type-C current advertisement by the connected DFP. The HD3SS3220 will debounce the CC pins and wait for VBUS detection before successful attachment. As a UFP, the HD3SS3220 will detect and communicate the DFP’s advertised current level to the system through the OUT1 and OUT2 pins if in GPIO mode or through the I2C CURRENT_MODE_DETECT register once in the Attached.SNK state.

The following list describes the steps for enabling DFP through I

2

C:


2. Write a 2'b10 to MODE_SELECT register (address 0x0A bits 5:4)


7.3.3 DRP – Dual Role Port

The HD3SS3220 can be configured to operate as DRP when the PORT pin is left floating on the PCB. In DRP mode, the HD3SS3220 toggles between presenting as a DFP (Rp on both CC pins) and presenting as a UFP

(Rd on both CC pins according to USB Type-C specification.

When presenting as a DFP, the HD3SS3220 monitors the voltage level on the CC pins looking for the R

(d) termination of a UFP. When a UFP is detected and HD3SS3220 is in the attached. SRC state, the HD3SS3220 pulls the ID pin low to indicate to the system the port is attached to a sink (UFP). Additionally, when a UFP is detected, the HD3SS3220 supplies VCONN on the unconnected CC pin if Ra is also detected. In DFP mode, the

HD3SS3220 will initially advertise default USB Type-C current. The Type-C current can be adjusted through I

2

C if the system wishes to increase the amount advertised. HD3SS3220 will adjust the R desired Type-C current advertisement.

(p) resistors to match the

When presenting as a UFP, the HD3SS3220 monitors the CC pins for the voltage level corresponding to the

Type-C current advertisement by the connected DFP. The HD3SS3220 will debounce the CC pins and wait for

VBUS detection before successfully attaching. As a UFP, the HD3SS3220 detects and communicate the DFP advertised current level to the system through the OUT1 and OUT2 pins if in GPIO mode or through the I2C

CURRENT_MODE_DETECT register once in the attached.SNK state.

The HD3SS3220 supports two optional Type-C DRP features called Try.SRC and Try.SNK. Products supporting dual-role functionality may have a requirement to be a source (DFP) or a sink (UFP) when connected to another dual-role capable product. For example, a dual-role capable notebook can be used as a source when connected to a tablet, or a cell phone could be a sink when connected to a notebook or tablet. When standard DRP products (products which don’t support either Try.SRC or Try.SNK) are connected together, the role (UFP or

DFP) outcome is not predetermined. These two optional DRP features provide a means for dual-role capable products to connect to another dual-role capable product in the role desired. Try.SRC and Try.SNK are only available when HD3SS3220 is configured in I

2

C mode. When operating in GPIO mode, the HD3SS3220 will always operate as a standard DRP.

The Try.SRC feature of the HD3SS3220 device provides a means for a DRP product to connect as a DFP when connected to another DRP product that doesn’t implement Try.SRC. When two products which implement

Try.SRC are connected together, the role outcome of either UFP or DFP is the same as a standard DRP.

Try.SRC is enabled by changing I

2

C register SOURCE_PREF to 2’b11. Once the register is changed to 2’b11, the HD3SS3220 will always attempt to connect as a DFP when attached to another DRP capable device.

7.3.4 Cable Orientation and Mux Control

The HD3SS3220 detects the cable orientation by monitoring the voltage on the CC pins. When a voltage level within the proper threshold is detected on CC1, the DIR pin is pulled low. When a voltage level within the proper threshold is detected on CC2, the DIR is high. The DIR pin is an open drain output and a pull-up resistor must be installed. The cable orientation status is also be communicated by I

2

C for HD3SS3220. The device also controls the integrated SS mux to switch appropriate SS signals pairs (RX1/TX1 or RX2/TX2).

7.3.5 Type-C Current Mode

Once a valid cable detection and attach have been completed, the DFP has the option to advertise the level of

Type-C current a UFP can sink. The default current advertisement for HD3SS3220 can be configured using

CURRENT_MODE pin or I2C CURRENT_MODE_ADVERTISE register. When a different than default current is chosen, the device adjusts the R

(p) resistors for the specified current level.

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HD3SS3220

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Type-C Current

Default – 500mA for

(USB2.0)

900 mA for (USB3.1)

Mid – 1.5 A

High – 3 A

HD3SS3220


Table 2. Type-C Current Advertisement for GPIO and I

2

C Modes

GPIO Mode (ADDR pin NC)

UFP (PORT pin L) DFP (PORT pin H)

I

2

C Mode (ADDR pin H, L)

UFP DFP

Detected current mode provided through

OUT1/OUT2

CURRENT_MODE=L

CURRENT_MODE=M

CURRENT_MODE=H

Detected current mode provided through I

2

C register

Advertisement selected through writing I

2

C register

7.3.6 Accessory Support

HD3SS3220 supports audio and debug accessories in UFP, DFP and DRP mode. Audio and debug accessory support is provided through reading of I2C registers. Audio accessory is also support through GPIO mode with

INT_N/OUT3 pin (audio accessory has been detected when INT_N/OUT3 is low).

7.3.7 Audio Accessory

Audio accessory mode is supported through two types of adapters. First, the passive audio adapter can be used to convert the Type-C connector into an audio port. In order to effectively detect the passive audio adapter, the

HD3SS3220 must detect a resistance < R

(a) on both the CC pins.

Secondly, a charge through audio adapter can be used. The primary difference between a passive and charge through adapter is that the charge through adapter supports supplying 500 mA of current over VBUS. The charge through adapter contains a receptacle and a plug. The plug shall act as a DFP and supply VBUS when it sees it’s connected.

When HD3SS3220 is configured in GPIO mode, OUT3 pin shall be used to determine if an Audio Accessory is connected. When an Audio Accessory is detected, the OUT3 pin is pulled low.

7.3.8 Debug Accessory

Debug is an additional state supported by USB Type-C. The specification does not define a specific user scenario for this state, but the end user could use debug accessory mode to enter a test state for production specific to the application. Charge through debug accessory is not supported by HD3SS3220 when in DRP or

UFP mode. The HD3SS3220 when configured as a DFP-only or as a DRP acting as a DFP detects a debug accessory which presents R

(d) on both CC1 and CC2 pins. The HD3SS3220 sets ACCESSORY_CONNECTED register to 3'b110 to indicate a UFP debug accessory. The HD3SS3220 when configured as a UFP-only or as a

DRP acting as a UFP detects a debug accessory which presents R

(p) on both CC1 and CC2 pins. The

HD3SS3220 sets ACCESSORY_CONNECTED register to 3b'111 to indicate a DFP debug accessory.

7.3.9 VCONN support for Active Cables

The HD3SS3220 supplies VCONN to active cables when configured in DFP mode or DRP acting as a DFP.

VCONN is provided only when it is determined that the unconnected CC pin is terminated to a resistance, R

(a) and after a UFP is detected and the attached. SRC state is entered. VCONN is supplied from VDD5 through a

, low resistance power FET out to the unconnected CC pin. VCONN is removed when a detach event is detected and the active cable is removed.

HD3SS3220 provides a current limiting function which will disconnect VCONN when the current being drawn

I from a device is above the max allowed for VCONN. When a VCONN fault has occurred, the VCONN flag in the

2

C register is set and HD3SS3220 stops supplying VCONN (switch turns off), until the register flag has been cleared. If HD3SS3220 is in GPIO mode when a fault occurs, the VCONN switch is turned off and HD3SS3220 will not supply VCONN until a port detach and re-attach occurs.

7.3.10 I

2

C and GPIO Control

The HD3SS3220 can be configured for I

2

C or GPIO using the ADDR pin. The ADDR pin is a 3-level control pin.

When the ADDR pin is left floating (NC), the HD3SS3220 is in GPIO mode. When the ADDR pin is pulled High, the HD3SS3220 is in I

2

C mode with address bit 6 equal to 1. When the ADDR pin is pulled low, the HD3SS3220 is in I

2

C mode with address bit 6 equal to 0.

All outputs for HD3SS3220 are open drain configuration.



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HD3SS3220


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The OUT1 and OUT2 pins are used to output the Type-C current mode when in GPIO mode. Additionally, the

OUT3 pin is used to communicate the Audio Accessory mode in GPIO mode. The specifics of the output pins can be found in

Table 3

.

OUT1

H

H

L

L

Table 3. Simplified Operation for OUT1 and OUT2

OUT2

H

L

H

L

ADVERTISEMENT

Default

Default

Medium

High

When operating in I

2

C mode, HD3SS3220 uses the SCL and SDA lines for clock and data and the INT pin. The

INT pin communicates an interrupt, or a change in I

2

C registers, to the system. The INT pin will be pulled low when the HD3SS3220 updates the registers with new information. The INT_N pin is open drain. The

INTERRUPT_STATUS register should be set when the INT pin is pulled low. The customer shall write to I

2

C to clear the INTERRUPT_STATUS register.

When operating in GPIO mode, the OUT3 pin is used in place of INT pin to determine if an Audio Accessory has been detected and attached. The OUT3 pin is pulled low when an Audio Accessory is detected.

NOTE

When using the 3.3-V supply for I

2

C pull-up, the customer must ensure that the VDD is 3

V and above. Otherwise, the I

2

C may back power the device.

7.3.11 HD3SS3220 V

(BUS)

Detection

The HD3SS3220 device supports VBUS detection according to the Type-C Specification. VBUS detection is used to determine the attachment and detachment of a UFP and to determine the entering and exiting of accessary modes. VBUS detection is also used to successfully resolve the role in DRP mode. The system VBUS voltage must be routed through a 900-k Ω resistor to the VBUS_DET pin on the HD3SS3220 device.

7.4 Device Functional Modes

The HD3SS3220 has four functional modes.

Table 4

lists these modes:

MODES

Unattached

Active

Table 4. USB Type-C States according to HD3SS3220 Functional Modes

GENERAL BEHAVIOR MODE STATES

(1)

USB port unattached. ID, PORT operational.

I

2

C on.

USB port attached. All GPIOs operational.

I

2

C on.

UFP-Only

DFP

DFP-Only

UFP-Only

DRP

DFP-Only

Unattached.SNK

AttachWait.SNK

Toggle Unattached.SNK

→ Unattached.SRC

AttachedWait.SRC or AttachedWait.SNK

Unattached.SRC

AttachWait.SRC

Attached.SNK

Audio Accessory

Debug Accessory

Attached.SNK

Attached.SRC

Audio accessory

Debug accessory

Attached.SRC

Audio accessory

Debug accessory

(1) (1) Required; not in sequential order

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HD3SS3220

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HD3SS3220


Device Functional Modes (continued)

Table 4. USB Type-C States according to HD3SS3220 Functional Modes (continued)

MODES

Dead battery

Shutdown

GENERAL BEHAVIOR

No operation. VDD5 not available.

No operation. VDD5 available and ENn_CC pin is high

MODE

DRP

DRP

STATES

(1)

Default device state to UFP/SNK with R

(d)

.

Default device state to UFP/SNK with R

(d)

.

7.4.1 Unattached Mode

Unattached mode isthe primary mode of operation for the HD3SS3220 since a USB port can be unattached for a lengthy period of time. In Unattached mode, VDD5 is available, and all IOs and I

2

C are operational. VCONN is disabled.

After HD3SS3220 are powered up, the part enters unattached mode until a successful attach has been determined. Initially, right after power up, the HD3SS3220 comes up as an unattached.SNK. The HD3SS3220 checks the PORT pin and operate according to the mode configuration. This means that the HD3SS3220 toggle between UFP and DFP if configured as a DRP

7.4.2 Active Mode

Active mode is defined as the port being attached. In active mode, all GPIOs are operational, and I

2

C is read / write (R/W). When in active mode, the HD3SS3220 device communicates to the AP that the USB port is attached. This communication happens through the ID pin if HD3SS3220 is configured as a DFP or DRP connect as source. If HD3SS3220 is configured as a UFP or a DRP connected as a sink, the OUT1/OUT2 and

INT_N/OUT3 pins are used. The HD3SS3220 device exits active mode under the following conditions:

• Cable unplug

• VBUS removal if attached as a UFP

• Dead battery; system battery or supply is removed

• EN_N is floated or pulled high

7.4.3 Dead Battery

During Dead battery mode VDD5 is not available. CC pins always default to pull down resistors in dead battery mode. Dead battery mode to means:

• HD3SS3220 in UFP with 5.1 k Ω ±20% R

(d)

; cable connected and providing charge.

• HD3SS3220 in UFP with 5.1 k Ω ±20% R

(d) battery)

; nothing connected (application could be off or have a discharged

NOTE

When VDD5 is off, the HD3SS3220 non-failsafe pins (DIR, VBUS_DET, ADDR, OUT[3:1] pins) could back-drive the HD3SS3220 device if not handled properly. When necessary to pull these pins up, it is recommended to pullup DIR, ADDR, and INT_N/OUT3 to the device’s VDD5 supply. The VBUS_DET must be pulled up to VBUS through a 900-k Ω resistor.

7.4.4 Shutdown Mode

Shutdown mode for HD3SS3220 is defined as follows:

• Supply voltage available and EN_N pin is high or floating.

• EN_N pin has internal pullup resistor

• The HD3SS3220 device is off, but still maintains the R

(d) on the CC pins.



HD3SS3220


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HD3SS3220


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7.5 Programming

For further programmability, the HD3SS3220 can be controlled using I

2

C. The HD3SS3220 local I

2

C interface is available for reading/writing after x clock cycles when the device is powered up. The SCL and SDA terminals are used for I

2

C clock and I

2

C data respectively. If I

2

C is the preferred method of control, the ADDR pin must be set accordingly.

ADDR pin

H

L

Bit 7 (MSB)

1

1

Bit 6

1

0

Table 5. HD3SS3220 I

2

C Target Address

Bit 5

0

0

Bit 4

0

0

Bit 3

1

1

Bit 2

1

1

Bit 1

1

1

Bit 0 (W/R)

0/1

0/1

The following procedure should be followed to write to HD3SS3220 I

2

C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the HD3SS3220 7-bit address and a zero-value R/W bit to indicate a write cycle.

2. The HD3SS3220 device acknowledges the address cycle.

3. The master presents the sub-address (I

2

C register within the HD3SS3220 device) to be written, consisting of one byte of data, MSB-first.

4. The HD3SS3220 device acknowledges the sub-address cycle.

5. The master presents the first byte of data to be written to the I

2

C register.

6. The HD3SS3220 device acknowledges the byte transfer.

7. The master can continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the HD3SS3220 device.

8. The master terminates the write operation by generating a stop condition (P).

The following procedure should be followed to read the HD3SS3220 I

2

C registers:

1. The master initiates a read operation by generating a start condition (S), followed by the HD3SS3220 7-bit address and a one-value R/W bit to indicate a read cycle.


3. The HD3SS3220 device transmits the contents of the memory registers MSB-first starting at register 00h or last read sub-address+1. If a write to the I

2

C register occurred prior to the read, then the HD3SS3220 device starts at the sub-address specified in the write.

4. The HD3SS3220 device waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I

2

C master acknowledges reception of each data byte transfer.

5. If an ACK is received, the HD3SS3220 device transmits the next byte of data.

6. The master terminates the read operation by generating a stop condition (P).

The following procedure should be followed for setting a starting sub-address for I

2

C reads:

1. The master initiates a write operation by generating a start condition (S), followed by the HD3SS3220 7-bit address and a zero-value R/W bit to indicate a read cycle.


3. The master presents the sub-address (I

2

C register within the HD3SS3220 device) to be read, consisting of one byte of data, MSB-first.

4. The HD3SS3220 device acknowledges the sub-address cycle.

5. The master terminates the read operation by generating a stop condition (P).

NOTE

If no sub-addressing is included for the read procedure, then the reads start at register offset 00h and continue byte-by-byte through the registers until the I

2

C master terminates the read operation. If a I

2

C address write occurred prior to the read, then the reads start at the sub-address specified by the address write.

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HD3SS3220


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7.6 Register Maps

HD3SS3220


OFFSET

0x07 through 0x00

0x08

0x09

0x0A

0xA0

Table 6. CSR Registers

RESET

[0x00, 0x54, 0x55, 0x53, 0x42,

0x33, 0x32, 0x32]

0x00

REGISTER NAME

Device Identification

Connection Status

0x20

0x00

0x02

Connection Status and Control

General Control

Device Revision

SECTION

Device Identification Register

Connection Status Register

Connection Status and Control

Register

General Control Register

Device Revision Register

7.6.1 Device Identification Register (offset = 0x07 through 0x00) [reset = 0x00, 0x54, 0x55, 0x53, 0x42,

0x33, 0x32, 0x32]

Figure 5. Device Identification Register

7 6 5 4

DEVICE_ID

R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

3 2 1 0

Bit

7:0

Field

DEVICE_ID

Table 7. Device Identification Register Field Descriptions

Type

R

Reset

0x00

Description

For the HD3SS3220 device these fields return a string of ASCII characters returning HD3SS3220 addresses:

0x07 - 0x00 = {0x00, 0x54, 0x55, 0x53, 0x42, 0x33, 0x32, 0x32}



HD3SS3220


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7.6.2 Connection Status Register (offset = 0x08) [reset = 0x00]

Figure 6. Connection Status Register

7 6

CURRENT_MODE_ADVERTISE

5 4

CURRENT_MODE_DETECT

3 2

ACCESSORY_CONNECTED

1 0

ACTIVE_CABL

E_DETECTION

R/U R/W R/U

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, R/U = Read/Update

R/U

Table 8. Connection Status Register Field Descriptions

Bit

7:6

5:4

3:1

0

Field

CURRENT_MODE_ADVERTISE

CURRENT_MODE_DETECT

ACCESSORY_CONNECTED

ACTIVE_CABL E_DETECTION

Type

R/W

R/U

R/U

R/U

Reset

2’b00

2’b00

3’b000

1’b0

Description

These bits are programmed by the application to raise the current advertisement from Default.

00 – Default (500mA/900mA) Initial value at startup

01 – Mid (1.5A)

10 – High (3A)

11 – Reserved

These bits are set when a UFP determines the Type-C current mode.

00 – Default (value at start up)

01 – Medium

10 –Charge Through Accessory – 500mA

11 – High

These bits are read by the application to determine if an accessory was attached.

000 –No Accessory attached (Default)

001 - Reserved

010 – Reserved

011 – Reserved

100 – Audio Accessory

101 – Charged Thru Audio Accessory

110 - Debug Accessory when HD3SS3220 is connected as a

DFP

111 – Debug accessory when HD3SS3220 is connected as a

UFP

This flag indicates that an active cable has been plugged into the Type-C connector

0 - No active cable

1 – Active Cable Attach

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HD3SS3220


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HD3SS3220


7.6.3 Connection Status and Control Register (offset = 0x09) [reset = 0x20]

Figure 7. Connection Status and Control Register

7 6

ATTACHED_STATE

5

CABLE_DIR

4

INTERRUPT

_STATUS

3

VCONN

_FAULT

2 1

DRP_DUTY_CYCLE

0

DISABLE

_UFP_

ACCESSORY

R/W R/U R/U R/U R/U

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset, R/U = Read/Update

R/W

Table 9. Connection Status Register Field Descriptions

Bit

7:6

5

4

3

2:1

0

Field

ATTACHED_STATE

CABLE_DIR

INTERRUPT _STATUS

VCONN _FAULT

DRP_DUTY_CYCLE

DISABLE _UFP_ ACCESSORY

Type

R/U

R/U

R/U

R/U

R/W

R/W

Reset

2’b00

1’b0

1’b0

1’b0

2’b00

1’b0

Description

This is an additional method to communicate attach other than the ID pin. These bits can be read by the application to determine what was attached.

00 – Not Attached (Default)

01 – Attached.SRC (DFP)

10 – Attached.SNK (UFP)

11 – Attached to an Accessory

Cable orientation. The application can read these bits for cable orientation information.

0 – CC2

1 – CC1 (Default)

The INT pin will be pulled low whenever a CSR changes. When a CSR change has occurred this bit should be held at 1 until the application clears teh bit.

0 – Clear 1 – Interrupt (When INT pulled low, this bit must be

1. This bit will be 1 whenever any CSR have been changed)

Bit is set whenever VCONN overcurrent limit is triggered.

0 – Clear

1 – VCONN fault is detected

Percentage of time that a DRP shall advertise DFP during t

DRP

00 – 30% default

01 – 40%

10 – 50%

11 – 60%

Setting this field will disable UFP accessory support

0 – UFP accessory support enabled (Default)

1 – UFP accessory support disabled



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7.6.4 General Control Register (offset = 0x0A) [reset = 0x00]

Figure 8. General Control Register

7

DEBOUNCE

6 5

MODE_SELECT

4 3

I2C_SOFT

_RESET

R/U

2

SOURCE_PREF

1

R/W R/W


R/W

Table 10. General Control Register Field Descriptions

Bit

7:6

5:4

3

2:1

0

Field

DEBOUNCE

MODE_SELECT

I2C_SOFT _RESET

SOURCE_PREF

DISABLE _TERM

Type

R/W

R/W

R/U

R/W

R/W

Reset

2’b00

2’b00

1’b0

2’b00

1’b0

0

DISABLE

_TERM

R/W

Description

The nominal amount of time the HD3SS3220 debounces the voltages on the CC pins.

00 – 168 ms (Default)

01 – 118 ms

10 – 134 ms

11 – 152 ms

This register can be written to set the HD3SS3220 mode operation. The ADDR pin must be set to I

2

C mode. If the default is maintained, HD3SS3220 shall operate according to the PORT pin levels and modes. The MODE_SELECT can only be changed when in the unattached state.

00 – DRP mode (start from unattached.SNK) (default)

01 – UFP mode (unattached.SNK)

10 – DFP mode (unattached.SRC)

11 – DRP mode (start from unattached.SNK)

This register resets the digital logic. The bit is self-clearing. A write of 1 starts the reset. The following registers can be affected after setting this bit:

CURRENT_MODE_DETECT

ACTIVE_CABLE_DETECTION

ACCESSORY_CONNECTED

ATTACHED_STATE

CABLE_DIR

This field controls the TUSB322I behavior when configured as a

DRP.

00 – Standard DRP (default)

01 – DRP performs Try.SNK

10 – Reserved

11 – DRP performs Try.SRC

This field disables the termination on CC pins and transition the

CC state machine to the disabled state.

0 – Termination enabled according TUSB322I mode of operation

(default)

1 – Termination disabled and state machine held in disable state

7.6.5 Device Revision Register (offset = 0xA0) [reset = 0x02]

Figure 9. Device Revision Register

7 6 5 4

REVISION

R


3 2

Bit

7:0

Field

REVISION

1

Table 11. Device Revision Register Field Descriptions

Type

R

Reset

‘h02

Description

Revision of HD3SS3220. Defaults to 0x02

0

22



HD3SS3220


www.ti.com

8 Application and Implementation

HD3SS3220


NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

HD3SS3220 can be used to design USB Type-C systems implementing DRP, DFP and UFP port for applications requiring USB SupeSpeed or SuperSpeedPlus. The device supports native USB-C power handshake for power negotiation up to 15 W. HD3SS3220 can advertise 900 mA, 1.5 A and 3 A current capability as DFP (provider) and detect these settings as UFP (consumer).

Use of I

2

C is optional but strongly encouraged and provides additional control of the device and status of the

USB-C interface resulting robust and flexible system implementation. A constant I

2C polling is not required and device provides an interrupt signal for servicing microprocessor.

HD3SS3220 mux channels have independent adaptive common mode tracking allowing RX and TX paths to have different common mode voltage simplifying system implementation and avoiding inter-op issues.

Layout for SS signals to USB-C connector needs to be adjusted based on receptacle type.

NOTE

HD3SS3220 mux does not provide common mode biasing for the channel. Therefore it is required that the device is biased from either side for all active channels. Also note that mux channels are for differential SS signals only.

If power support larger than 15W is required USBPD function is needed and not supported by this device. If split data/power role is desired such as USB host but power consumer or

USB device but power provider, an USBPD function is needed as well.



HD3SS3220


23

HD3SS3220


8.2 Typical Application, DRP Port

DM

DP

PS_EN

PS_FAULT#

VBUS

USB3 and

PMIC

INT#

ID

SCL

SDA

VCONN_FAULT#

SSTXP

SSTXN

SSRXP

SSRXN

SS_EN#

www.ti.com

System VBUS

SCL

SDA

DM_OUT

DP_OUT

VIN

EN

FAULT#

DM_IN

DP_IN

VOUT

USB VBUS Switch

(Optional BC 1.2 Support for Legacy)

I2C I/O

1.8V or 3.3V

VDD_5V

4.7 k

4.7 k 200 k 200 k

200 k

10 k

VCC_3.3V

200 k

VCONN Bulk Cap

150uF

100uF 100nF

PORT

INT_N/OUT3

ID

SCL/OUT2

SDA/OUT1

VCONN_FAULT_N

CURRENT_MODE

VBUS_DET

900 k

CC2

CC1

CC2

CC1

RXP2

RXN2

TXN1

TXP1

DIR

VCC33

TXp

TXn

RXp

RXn

ENn_Mux

HD3SS3220

TX2p

TX2n

RX2p

RX2n

TX1p

TX1n

RX1p

RX1n

DM

DP

VBUS

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

B8

B9

B10

B11

B12

B4

B5

B6

B7

B1

B2

B3

TXP2

TXN2

RXN1

RXP1

100nF

TXP2

TXN2

RXP2

RXN2

100nF

100nF

TXN1

TXP1

RXN1

RXP1

100nF

Note: HD3SS3220 Does Not Care

About Differential Pair Polarity

Figure 10. DRP Application Using HD3SS3220DRP

24



HD3SS3220


www.ti.com

Typical Application, DRP Port (continued)

8.2.1 Design Requirements

For this design example, use the parameters shown in

Table 12 .

VDD5

VCC33

PARAMETER

System_VBUS

I

2

C I/O Supply

AC Coupling Capacitors for SS signals

Pull-up Resistors: DIR, ID, INT_N,

VCONN_FAULT_N

Pull-up Resistors: I

2

C

Pull-up Resistors: CURRENT_MODE

Series resistor: VBUS_DET

Decoupling Capacitors: VCONN Bulk

Decoupling Capacitors: VBUS Bulk

HD3SS3220


Table 12. Design Parameters, DRP Port

EXAMPLE

5.25 V

5.25 V

3.3 V

3.3 V

100 nF

200 K

COMMENTS

VDD5 is used to provide VCONN power to CC pins. Value of this supply should be ≥ 5 V to keep VCONN ≥ 4.75 V.

VDD5 and System_VBUS can be shorted together; however careful consideration is needed to maintain desired VBUS and VCONN for the Type-C port.

1.8 V is also an option.

When using the 3.3-V supply, the customer must ensure that the VDD is 3 V and above. Otherwise the I

2

C may back power the device

3-3.6 V range allowed.

75-200 nF range allowed.

For TX pairs only, RX pairs will be biased by host Receiver. Note that

HD3SS3220 requires a common mode biasing of 0-2 V. If host receiver has bias voltage outside this range, appropriate additional ac coupling caps and biasing of HD3SS3220 RX pairs needed.

Smaller values can be used, but leakage needs to be considered for device power budget calculations.

4.7 K

10 K

Example here is for 3 A. If 1.5 A or 900 mA needed different values are required.

900 K

100 μF

150 μF As indicated in schematic needs to be switched out when in UFP.

8.2.2 Detailed Design Procedure

HD3SS3220 can be used to design a USB Type-C DRP Port. In DRP mode the device alternate itself as DFP and UFP according to USB-C specifications. An example schematic for DRP implementation is illustrated in

Figure 10 .



HD3SS3220


25

HD3SS3220


www.ti.com

8.2.3 Typical Application, DFP Port

HD3SS3220 can be used to design a USB Type-C DFP Port. An example schematic for DFP implementation is illustrated in

Figure 11 .

DM

DP

PS_EN

PS_FAULT#

VBUS

System VBUS

SCL

SDA

DM_OUT

DP_OUT

VIN

EN

FAULT#

DM_IN

DP_IN

VOUT

USB VBUS Switch

(Optional BC 1.2 Support for Legacy)

I2C I/O

1.8V or 3.3V

VDD_5V

200 k

VCONN Bulk Cap

150uF

100uF 100nF

DM

DP

VBUS

4.7 k

4.7 k 200 k 200 k

200 k

10 k

VBUS_DET

900 k

RXP2

RXN2

TXP2

TXN2

USB3 and

PMIC

INT#

ID

SCL

SDA

VCONN_FAULT#

VCC_3.3V

PORT

INT_N/OUT3

ID

SCL/OUT2

SDA/OUT1

VCONN_FAULT_N

CURRENT_MODE

CC2

CC1

CC2

CC1

TXN1

TXP1

A6

A5

A4

A3

A2

A1

A12

A11

A10

A9

A8

A7

B9

B10

B11

B12

B6

B7

B8

B1

B2

B3

B4

B5

RXN1

RXP1

200 k

SSTXP

SSTXN

SSRXP

SSRXN

SS_EN#

DIR

VCC33

TXp

TXn

RXp

RXn

ENn_Mux

HD3SS3220

TX2p

TX2n

RX2p

RX2n

TX1p

TX1n

RX1p

RX1n

100nF

TXP2

TXN2

RXP2

RXN2

100nF

100nF

TXN1

TXP1

RXN1

RXP1

100nF



Figure 11. DFP Application Using HD3SS3220DFP

26



HD3SS3220


www.ti.com

8.2.3.1 Design Requirements


Table 13 .

VDD5

VCC33

PARAMETER

System_VBUS

I

2

C I/O Supply


Pull-up Resistors: DIR, ID, INT_N,

VCONN_FAULT_N


2

C

Pull-up Resistors: CURRENT_MODE

Decoupling Capacitors: VCONN Bulk

Decoupling Capacitors: VBUS Bulk

HD3SS3220


Table 13. Design Parameters, DFP Port

EXAMPLE

5.25 V

5.25 V

3.3 V

3.3 V

100 nF

200 K

COMMENTS

VDD5 is used to provide VCONN power to CC pins. Value of this supply should be ≥ 5 V to keep VCONN ≥ 4.75 V.

VDD5 and System_VBUS can be shorted together; however careful consideration is needed to maintain desired VBUS and VCONN for the Type-C port.



2







4.7 K

10 K

Example here is for 3 A. If 1.5 A or 900 mA needed different values are required.

100 μF

150 μF

8.2.3.2 Detailed Design Procedure

HD3SS3220 can be used to design a USB Type-C DFP Port. An example schematic for DFP implementation is illustrated in

Figure 11 .



HD3SS3220


27

HD3SS3220


www.ti.com

8.2.4 Typical Application, UFP Port

HD3SS3220 can be used to design a USB Type-C UFP Port. An example schematic for UFP implementation is illustrated in

Figure 12 .

DM

DP

VBUS

USB3 and

PMIC

INT#

SCL

SDA

SSTXP

SSTXN

SSRXP

SSRXN

SS_EN#

I2C I/O

1.8V or 3.3V

VDD_5V

4.7 k

4.7 k

4.7 k 200 k

VCC_3.3V

200 k

100nF

PORT

INT_N/OUT3

ID

SCL/OUT2

SDA/OUT1

VCONN_FAULT_N

CURRENT_MODE

VBUS_DET

900 k

CC2

CC1

CC2

CC1

RXP2

RXN2

TXN1

TXP1

DIR

VCC33

TXp

TXn

RXp

RXn

ENn_Mux

HD3SS3220

TX2p

TX2n

RX2p

RX2n

TX1p

TX1n

RX1p

RX1n

DM

DP

VBUS

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

B8

B9

B10

B11

B12

B1

B2

B3

B4

B5

B6

B7

TXP2

TXN2

RXN1

RXP1

100nF

TXP2

TXN2

RXP2

RXN2

100nF

100nF

TXN1

TXP1

RXN1

RXP1

100nF



Figure 12. UFP Application Using HD3SS3220DFP

28



HD3SS3220


www.ti.com

8.2.4.1 Design Requirements


Table 14 .

VDD5

VCC33

PARAMETER

I

2

C I/O Supply


Pull-up Resistors: DIR, INT_N


2

C

Series resistor: VBUS_DET

HD3SS3220


Table 14. Design Parameters, UFP Port

EXAMPLE

5 V

3.3 V

3.3 V

100 nF

200 K

COMMENTS

VBUS from Type-C port can be used.



2







4.7 K

900 K

8.2.4.2 Detailed Design Procedure

HD3SS3220 can be used to design a USB Type-C DFP Port. An example schematic for UFP implementation is illustrated in

Figure 12 .

9 Power Supply Recommendations

HD3SS3220 has 4.5 to 5.5-V supply voltage requirement. The device can be powered from the same rail that provides power for V

(BUS)

.



HD3SS3220


29

HD3SS3220


10 Layout

www.ti.com

10.1 Layout Guidelines

10.1.1 Suggested PCB Stackups

TI recommends a PCB of at least six layers.

Table 15

provides example PCB stackups.

6-LAYER

SIGNAL

GROUND

SIGNAL

(1)

SIGNAL

(1)

POWER/GROUND

(2)

SIGNAL

Table 15. Example PCB Stackups

8-LAYER

SIGNAL

GROUND

SIGNAL

SIGNAL

POWER/GROUND

(2)

SIGNAL

GROUND

SIGNAL

10-LAYER

SIGNAL

GROUND

SIGNAL

(1)

SIGNAL

(1)

POWER

POWER/GROUND

(2)

SIGNAL

(1)

SIGNAL

(1)

GROUND

SIGNAL

(1) Route directly adjacent signal layers at a 90° offset to each other

(2) Plane may be split depending on specific board considerations. Ensure that traces on adjacent planes do not cross splits.

10.1.2 High-Speed Signal Trace Length Matching

Match the etch lengths of the relevant differential pair traces of each interface. The etch length of the differential pair groups do not need to match (that is, the length of the transmit pair does not need to match the length of the receive pair). When matching the intrapair length of the high-speed signals, add serpentine routing to match the lengths as close to the mismatched ends as possible. See

Figure 13

for more details.

Length-Matching at Matched Ends

Length-Matching at Mismatched Ends

Figure 13. Length Matching

30



HD3SS3220


www.ti.com

HD3SS3220


10.1.3 Differential Signal Spacing

To minimize crosstalk in high-speed interface implementations, the spacing between the signal pairs must be a minimum of 5 times the width of the trace. This spacing is referred to as the 5W rule. A PCB design with a calculated trace width of 6 mils requires a minimum of 30 mils spacing between high-speed differential pairs.

Also, maintain a minimum keep-out area of 30 mils to any other signal throughout the length of the trace. Where the high-speed differential pairs abut a clock or a periodic signal, increase this keep-out to a minimum of 50 mils to ensure proper isolation. For examples of high-speed differential signal spacing, see

Figure 14

and

Figure 15 .

TXn

TXp RXn

RXp

30

General Keep-Out

6 8 6

50

Inter-Pair Keep-Out

6 8 6

50

High-Speed/Periodic Keep-Out

Figure 14. USB3/SATA/PCIe Differential Signal Spacing (mils)

DP

DM

30

General Keep-Out

6 8 6 50

High-Speed/Periodic Keep-Out

Figure 15. USB2 Differential Signal Spacing (mils)

10.1.4 High-Speed Differential Signal Rules

• Do not place probe or test points on any high-speed differential signal.

• Do not route high-speed traces under or near crystals, oscillators, clock signal generators, switching power regulators, mounting holes, magnetic devices, or ICs that use or duplicate clock signals.

• After BGA breakout, keep high-speed differential signals clear of the SoC because high current transients produced during internal state transitions can be difficult to filter out.

• When possible, route high-speed differential pair signals on the top or bottom layer of the PCB with an adjacent GND layer. TI does not recommend stripline routing of the high-speed differential signals.

• Ensure that high-speed differential signals are routed ≥ 90 mils from the edge of the reference plane.

• Ensure that high-speed differential signals are routed at least 1.5 W (calculated trace-width × 1.5) away from voids in the reference plane. This rule does not apply where SMD pads on high-speed differential signals are voided.

• Maintain constant trace width after the SoC BGA escape to avoid impedance mismatches in the transmission lines.

• Maximize differential pair-to-pair spacing when possible.



HD3SS3220


31

HD3SS3220


www.ti.com

10.1.5 Symmetry in the Differential Pairs

Route all high-speed differential pairs together symmetrically and parallel to each other. Deviating from this requirement occurs naturally during package escape and when routing to connector pins. These deviations must be as short as possible and package break-out must occur within 0.25 inches of the package.

Figure 16. Differential Pair Symmetry

10.1.6 Via Discontinuity Mitigation

A via presents a short section of change in geometry to a trace and can appear as a capacitive and/or an inductive discontinuity. These discontinuities result in reflections and some degradation of a signal as it travels through the via. Reduce the overall via stub length to minimize the negative impacts of vias (and associated via stubs).

Because longer via stubs resonate at lower frequencies and increase insertion loss, keep these stubs as short as possible. In most cases, the stub portion of the via present significantly more signal degradation than the signal portion of the via. TI recommends keeping via stubs to less than 15 mils. Longer stubs must be back-drilled. For examples of short and long via lengths, see

Figure 17

and

Figure 18

.

32



HD3SS3220


www.ti.com

Layer 3

HD3SS3220


Long Stub Via

Layer 10

Layer 1

Figure 17. Via Length (Long Stub)

Short Stub Via

These long via stubs should be back-drilled.

Layer 8

Layer 10

< 15 mils

Figure 18. Via Length (Short Stub)



HD3SS3220


33

HD3SS3220


www.ti.com

10.1.7 Surface-Mount Device Pad Discontinuity Mitigation

Avoid including surface-mount devices (SMDs) on high-speed signal traces because these devices introduce discontinuities that can negatively affect signal quality. When SMDs are required on the signal traces (for example, the USB SuperSpeed transmit AC coupling capacitors) the maximum permitted component size is

0603. TI strongly recommends using 0402 or smaller. Place these components symmetrically during the layout process to ensure optimum signal quality and to minimize reflection. For examples of correct and incorrect AC coupling capacitor placement, see

Figure 19 .

Figure 19. AC-Coupling Placement

34



HD3SS3220


www.ti.com

HD3SS3220


To minimize the discontinuities associated with the placement of these components on the differential signal traces, TI recommends partially voiding the SMD mounting pads of the reference plane by approximately 60% because this value strikes a balance between the capacitive effects of a 0% reference void and the inductive effects of a 100% reference void. This void should be at least two PCB layers deep. For an example of a reference plane voiding of surface mount devices, see

Figure 20 .

SIGNAL TRACE

SMD

PAD

VOID

SMD

PAD

SIGNAL TRACE

Figure 20. Reference Plane Voiding of Surface-Mount Devices

10.1.8 ESD/EMI Considerations

When choosing ESD/EMI components, TI recommends selecting devices that permit flow-through routing of the

USB differential signal pair because they provide the cleanest routing. For example, the TI TPD4EUSB30 can be combined with the TI TPD2EUSB30 to provide flow-through ESD protection for both USB2 and USB3 differential signals without the need for bends in the signal pairs. For an example of flow-through routing, see

Figure 21

.

USB 3.0

Host Controller

8 mm

Figure 21. Flow-Through Routing



HD3SS3220


35

HD3SS3220


10.2 Layout

www.ti.com

Figure 22. Layout Example

36


Figure 23. Layout Example 2


HD3SS3220


www.ti.com

11 Device and Documentation Support

HD3SS3220


11.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use .

TI E2E™ Online Community

TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.

Design Support

TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

11.2 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.



HD3SS3220


37

RNH0030A

SCALE 3.300

PIN 1 INDEX AREA

A

2.6

2.4

B

4.6

4.4

PACKAGE OUTLINE

WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

0.8 MAX

0.05

0.00

C

SEATING PLANE

4X (0.2)

26X 0.4

10

11

2X 1.6

1.2±0.05

15

16

EXPOSED

THERMAL PAD

2X

3.6

3.2±0.05

(0.2) TYP

1

25

PIN 1 ID

(OPTIONAL)

30 26

0.1

0.05

C A B

4221819/A 04/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

RNH0030A

EXAMPLE BOARD LAYOUT



(1.2)

30 26

(0.7) TYP

30X (0.5)

1

30X (0.2)

26X (0.4)

SYMM

25

(1.2)

TYP

(3.2)

(4.4)

( 0.2

) TYP

VIA

FULL R

TYP

10

(R 0.05

) TYP

16

11

SYMM

15

(2.4)

LAND PATTERN EXAMPLE

SCALE:18X

4X (0.2)

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

METAL SOLDER MASK

OPENING

NON SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

OPENING

SOLDER MASK DETAILS

SOLDER MASK

DEFINED

METAL UNDER

SOLDER MASK

4221819/A 04/2015

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

RNH0030A

EXAMPLE STENCIL DESIGN



(1.13)

SYMM

30 26

30X (0.5)

1

30X (0.2)

25

26X (0.4)

2X

(1.39)

SYMM

(4.4)

METAL

TYP

FULL R

TYP

10

(R 0.05

) TYP

11 15

(2.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD

82% PRINTED SOLDER COVERAGE BY AREA

SCALE:20X

16

(0.8)

4X (0.2)

4221819/A 04/2015

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations. www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

23-Dec-2015

PACKAGING INFORMATION

Orderable Device

HD3SS3220IRNHR

HD3SS3220IRNHT

Status

(1)

ACTIVE

ACTIVE

Package Type Package

Drawing

WQFN

WQFN

RNH

RNH

Pins Package

30

30

Qty

Eco Plan

(2)

3000 Green (RoHS

& no Sb/Br)

250 Green (RoHS

& no Sb/Br)

Lead/Ball Finish

(6)

CU NIPDAU

CU NIPDAU

MSL Peak Temp

(3)

Level-2-260C-1 YEAR

Op Temp (°C)

-40 to 85

Level-2-260C-1 YEAR -40 to 85

Device Marking

(4/5)

HD3220

HD3220

HD3SS3220RNHR ACTIVE WQFN RNH 30 3000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-2-260C-1 YEAR 0 to 70 HD3220

HD3SS3220RNHT ACTIVE WQFN RNH 30 250 Green (RoHS

& no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

CU NIPDAU Level-2-260C-1 YEAR

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

0 to 70 HD3220

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Addendum-Page 1

Samples

PACKAGE OPTION ADDENDUM

www.ti.com

23-Dec-2015

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

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Addendum-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

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www.dlp.com

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power.ti.com

microcontroller.ti.com

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