Maxim ICM7212AMIPL (73-761-63)

Maxim ICM7212AMIPL (73-761-63)
2001-04-02
PRODUKTINFORMATION
Vi reserverar oss mot fel samt förbehåller oss rätten till ändringar utan föregående meddelande
ELFA artikelnr
73-760-07 ICM7211AIPL
73-761-63 ICM7212AMIPL displaydriv
ICM7211, ICM7212
4-Digit, ICM7211 (LCD) and
ICM7212 (LED) Display Drivers
August 1997
Features ICM7211 (LCD)
Description
• Four Digit Non-Multiplexed 7 Segment LCD Display
Outputs with Backplane Driver
The ICM7211 (LCD) and ICM7212 (LED) devices constitute
a family of non-multiplexed four-digit seven-segment CMOS
display decoder-drivers.
• Complete Onboard RC Oscillator to Generate Backplane
Frequency
• Backplane Input/Output Allows Simple Synchronization
of Slave-Devices to a Master
• ICM7211 Devices Provide Separate Digit Select Inputs to
Accept Multiplexed BCD Input (Pinout and Functionally
Compatible with Siliconix DF411)
• ICM7211M Devices Provide Data and Digit Address
Latches Controlled by Chip Select Inputs to Provide a
Direct High Speed Processor Interface
• ICM7211 Decodes Binary to Hexadecimal; ICM7211A
Decodes Binary to Code B (0-9, Dash, E, H, L, P, Blank)
• ICM7211A Available in Surface Mount Package
Features ICM7212AM (LED)
• 28 Current-Limited Segment Outputs Provide 4-Digit
Non-Multiplexed Direct LED Drive at >5mA Per Segment
• Brightness Input Allows Direct Control of LED
Segment Current with a Single Potentiometer or
Digitally as a Display Enable
• ICM7212AM Device Provides Same Input Configuration
and Output Decoding Options as the ICM7211AM
The ICM7211 devices are configured to drive conventional
LCD displays by providing a complete RC oscillator, divider
chain, backplane driver, and 28 segment outputs.
The ICM7212 devices are configured to drive commonanode LED displays, providing 28 current-controlled, low
leakage, open-drain N-Channel outputs. These devices
provide a brightness input, which may be used at normal
logic levels as a display enable, or with a potentiometer as a
continuous display brightness control.
These devices are available with multiplexed or microprocessor input configurations. The multiplexed versions provide four
data inputs and four Digit Select inputs. This configuration is
suitable for interfacing with multiplexed BCD or binary output
devices, such as the ICM7217, ICM7226, and ICL7135. The
microprocessor versions provide data input latches and Digit
Address latches under control of high-speed Chip Select
inputs. These devices simplify the task of implementing a
cost-effective alphanumeric seven-segment display for microprocessor systems, without requiring extensive ROM or CPU
time for decoding and display updating.
The standard devices will provide two different decoder
configurations. The basic device will decode the four bit
binary inputs into a seven-segment alphanumeric hexadecimal output. The “A” versions will provide the “Code B” output
code, i.e., 0-9, dash, E, H, L, P, blank. Either device will correctly decode true BCD to seven-segment decimal outputs.
Ordering Information
PART NUMBER
DISPLAY
TYPE
DISPLAY
DECODING
INPUT
INTERFACING
DISPLAY DRIVE
TYPE
TEMP.
RANGE (oC)
PACKAGE
PKG. NO.
ICM7211lPL
LCD
Hexadecimal
Multiplexed
Direct Drive
-40 to 85
40 Ld PDIP
E40.6
ICM7211MlPL
LCD
Hexadecimal
Microprocessor
Direct Drive
-40 to 85
40 Ld PDIP
E40.6
ICM7211AlPL
LCD
Code B
Multiplexed
Direct Drive
-40 to 85
40 Ld PDIP
E40.6
ICM7211AMlPL
LCD
Code B
Microprocessor
Direct Drive
-40 to 85
40 Ld PDIP
E40.6
ICM7211AlM44
LCD
Code B
Multiplexed
Direct Drive
-40 to 85
44 Ld MQFP
Q44.10x10
ICM7211AMlM44
LCD
Code B
Microprocessor
Direct Drive
-40 to 85
44 Ld MQFP
Q44.10x10
ICM7212AMlPL
LED
Code B
Microprocessor
Common Anode
-40 to 85
40 Ld PDIP
E40.6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
9-6
File Number
3158.1
ICM7211, ICM7212
Pinouts
ICM7211, ICM7211A
(PDIP)
TOP VIEW
ICM7211M, ICM7211AM
(PDIP)
TOP VIEW
VDD 1
40 d1
VDD 1
40 d1
e1 2
39 c1
e1 2
39 c1
g1 3
38 b1
g1 3
38 b1
f1 4
37 a1
f1 4
37 a1
BP 5
36 OSC
BP 5
36 OSC
a2 6
35 VSS
a2 6
35 VSS
b2 7
34 D4
b2 7
34 CHIP SELECT 2
c2 8
33 D3
c2 8
33 CHIP SELECT 1
d2 9
32 D2
d2 9
32 DIGIT ADRESS BIT 2
DIGIT
SELECT
INPUTS
e2 10
31 D1
e2 10
31 DIGIT ADRESS BIT 1
g2 11
30 B3
g2 11
30 B3
f2 12
29 B2
f2 12
29 B2
a3 13
28 B1
a3 13
28 B1
b3 14
27 B0
b3 14
27 B0
c3 15
26 f4
c3 15
26 f4
d3 16
25 g4
d3 16
25 g4
e3 17
24 e4
e3 17
24 e4
g3 18
23 d4
g3 18
23 d4
f3 19
22 c4
f3 19
22 c4
a4 20
21 b4
a4 20
21 b4
DATA
INPUTS
ICM7212AM
(PDIP)
TOP VIEW
VDD 1
40 d1
e1 2
39 c1
g1 3
38 b1
f1 4
37 a1
BRT 5
36 VSS
a2 6
35 VSS
b2 7
34 CHIP SELECT 2
c2 8
33 CHIP SELECT 1
d2 9
32 DIGIT ADRESS BIT 2
e2 10
31 DIGIT ADRESS BIT 1
g2 11
30 B3
f2 12
29 B2
a3 13
28 B1
b3 14
27 B0
c3 15
26 f4
d3 16
25 g4
e3 17
24 e4
g3 18
23 d4
f3 19
22 c4
a4 20
21 b4
9-7
DATA
INPUTS
DATA
INPUTS
ICM7211, ICM7212
(Continued)
OSC
a1
b1
c1
NC
d1
VDD
e1
g1
BP
f1
ICM7211A
(MQFP)
TOP VIEW
b2
44 43 42 41 40 39 38 37 36 35 34
33
2
32
D4
c2
3
31
D3
d2
4
30
D2
e2
5
29
D1
NC
6
28
NC
g2
7
27
B3
a2
VSS
1
24
B0
11
23
12 13 14 15 16 17 18 19 20 21 22
DIGIT
SELECT
INPUTS
DATA
INPUTS
f4
g4
e4
10
c3
c4
d4
b3
b4
B1
NC
B2
25
g3
f3
a4
26
9
e3
8
d3
f2
d3
OSC
a1
b1
c1
d1
NC
VDD
e1
g1
BP
f1
ICM7211AM
(MQFP)
TOP VIEW
b2
44 43 42 41 40 39 38 37 36 35 34
33
2
32
c2
3
31
CHIP SELECT 1
d2
4
30
DIGITAL ADRESS BIT 2
e2
5
29
DIGITAL ADRESS BIT 1
NC
6
28
NC
g2
7
27
B3
f2
8
26
B2
d3
9
25
B1
b3
10
24
B0
c3
11
23
12 13 14 15 16 17 18 19 20 21 22
9-8
g4
e4
c4
d4
b4
NC
g3
f3
a4
1
e3
a2
d3
Pinouts
VSS
CHIP SELECT 2
f4
DATA
INPUTS
ICM7211, ICM7212
Functional Block Diagrams
ICM7211A
D4
SEGMENT OUTPUTS
D3
SEGMENT OUTPUTS
D2
SEGMENT OUTPUTS
D1
SEGMENT OUTPUTS
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE LATCH EN
7 WIDE LATCH EN
7 WIDE LATCH EN
7 WIDE LATCH EN
PROGRAMMABLE
4 TO 7 DECODER
PROGRAMMABLE
4 TO 7 DECODER
PROGRAMMABLE
4 TO 7 DECODER
PROGRAMMABLE
4 TO 7 DECODER
DATA
INPUTS
DIGIT
SELECT
INPUTS
OSCILLATOR
19kHz
FREE-RUNNING
OSCILLATOR
INPUT
÷128
BLACKPLANE
DRIVER
ENABLE
BP INPUT/OUTPUT
ENABLE
DIRECTOR
ICM7211AM
DATA
INPUTS
2-BIT
DIGIT
ADRESS
INPUT
CHIP
SELECT 1
CHIP
SELECT 2
D4
SEGMENT OUTPUTS
D3
SEGMENT OUTPUTS
D2
SEGMENT OUTPUTS
D1
SEGMENT OUTPUTS
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE LATCH EN
7 WIDE LATCH EN
7 WIDE LATCH EN
7 WIDE LATCH EN
PROGRAMMABLE
4 TO 7 DECODER
PROGRAMMABLE
4 TO 7 DECODER
PROGRAMMABLE
4 TO 7 DECODER
PROGRAMMABLE
4 TO 7 DECODER
4-BIT
LATCH
ENABLE
2-BIT
LATCH
2 TO 4
DECODER
ENABLE
ONE
SHOT
OSCILLATOR
19kHz
FREE-RUNNING
OSCILLATOR
INPUT
ENABLE
DIRECTOR
9-9
÷128
BLACKPLANE
DRIVER
ENABLE
BP INPUT/OUTPUT
ICM7211, ICM7212
Functional Block Diagrams
(Continued)
DATA
INPUTS
2-BIT
DIGIT
ADRESS
INPUT
CHIP
SELECT 1
CHIP
SELECT 2
D4
SEGMENT OUTPUTS
D3
SEGMENT OUTPUTS
D2
SEGMENT OUTPUTS
D1
SEGMENT OUTPUTS
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE DRIVER
7 WIDE LATCH EN
7 WIDE LATCH EN
7 WIDE LATCH EN
7 WIDE LATCH EN
PROGRAMMABLE
4 TO 7 DECODER
PROGRAMMABLE
4 TO 7 DECODER
PROGRAMMABLE
4 TO 7 DECODER
PROGRAMMABLE
4 TO 7 DECODER
4-BIT
LATCH
ENABLE
2-BIT
LATCH
2 TO 4
DECODER
ENABLE
ONE
SHOT
9-10
BRIGHTNESS
ICM7212AM
ICM7211, ICM7212
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VDD - VSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V
Input Voltage (Any Terminal) (Note 1) . . VSS - 0.3V to VDD , + 0.3V
Thermal Resistance (Typical, Note 2)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
80
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
(MQFP - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. Due to the SCR structure inherent in the CMOS process, connecting any terminal to voltages greater than VDD or less than VSS may
cause destructive device latchup. For this reason, it is recommended that no inputs from external sources not operating on the same
power supply be applied to the device before its supply is established, and that in multiple supply systems, the supply to the ICM7211
and ICM7212 be turned on first.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
3
5
6
V
-
10
50
µA
ICM7211 CHARACTERISTICS (LCD) VDD = 5V ±10%, TA = 25oC, VSS = 0V Unless Otherwise Specified
Operating Supply Voltage Range (VDD - VSS), VSUPPLY
Operating Current, IDD
Test circuit, Display blank
Oscillator Input Current, IOSCI
Pin 36
-
±2
±10
µA
Segment Rise/Fall Time, tr , tf
CL = 200pF
-
0.5
-
µs
Backplane Rise/Fall Time, tr , tf
CL = 5000pF
-
1.5
-
µs
Oscillator Frequency, fOSC
Pin 36 Floating
-
19
-
kHz
Backplane Frequency, fBP
Pin 36 Floating
-
150
-
Hz
ICM7212 CHARACTERISTICS (Common Anode LED)
Operating Supply Voltage Range (VDD - VSS), VSUPPLY
4
5
6
V
Operating Current Display Off, ISTBY
Pin 5 (Brightness), Pins 27-34 VSS
-
10
50
µA
Operating Current, IDD
Pin 5 at VDD , Display all 8’s
-
200
-
mA
Segment Leakage Current, ISLK
Segment Off
-
±0.01
±1
µA
Segment On Current, ISEG
Segment On, VO = +3V
5
8
-
mA
4
-
-
V
INPUT CHARACTERISTICS (ICM7211 and ICM7212)
Logical “1” Input Voltage, VIH
Logical “0” Input Voltage, VIL
-
-
1
V
-
±0.01
±1
µA
±0.01
±1
µA
-
200
-
pF
1
-
-
µs
Data Setup Time, tDS
500
-
-
ns
Data Hold Time, tDH
200
-
-
ns
2
-
-
µs
200
-
-
ns
Input Leakage Current, IILK
Pins 27-34
Input Capacitance, ClN
Pins 27-34
-
5
BP/Brightness Input Leakage, IBPLK
Measured at Pin 5 with Pin 36 at VSS
-
BP/Brightness Input Capacitance, CBPI
All Devices
pF
AC CHARACTERISTICS - MULTIPLEXED INPUT CONFIGURATION
Digit Select Active Pulse Width, tWH
Refer to Timing Diagrams
Inter-Digit Select Time, tIDS
AC CHARACTERISTICS - MICROPROCESSOR INTERFACE
Chip Select Active Pulse Width, tWL
Other Chip Select Either Held Active,
or Both Driven Together
Data Setup Time, tDS
100
-
-
ns
Data Hold Time, tDH
10
0
-
ns
Inter-Chip Select Time, tICS
2
-
-
µs
9-11
ICM7211, ICM7212
Input Definitions
In this table, VDD and VSS are considered to be normal operating input logic levels. Actual input low and high levels are
specified under Operating Characteristics. For lowest power consumption, input signals should swing over the full supply.
INPUT
TERMINAL
CONDITIONS
FUNCTION
B0
27
VDD = Logical One
VSS = Logical Zero
Ones (Least Significant)
B1
28
VDD = Logical One
VSS = Logical Zero
Twos
B2
29
VDD = Logical One
VSS = Logical Zero
Fours
B3
30
VDD = Logical One
VSS = Logical Zero
Eights (Most Significant)
OSC (LCD Devices
Only)
36
Floating or with External
Capacitor to VDD
Oscillator Input
VSS
Disables BP output devices, allowing segments to be synchronized to
an external signal input at the BP terminal (Pin 5).
Data Input Bits
ICM7211 Multiplexed-Binary Input Configuration
INPUT
TERMINAL
D1
31
CONDITIONS
FUNCTION
D2
32
D3
33
D3 Digit Select
D4
34
D4 Digit Select (Most Significant)
VDD = Inactive
VSS = Active
D1 Digit Select (Least Significant)
D2 Digit Select
ICM7211M/ICM7212M Microprocessor Interface Input Configuration
INPUT
DESCRIPTION
TERMINAL
CONDITIONS
DA1
Digit Address
Bit 1 (LSB)
31
VDD = Logical One
VSS = Logical Zero
DA2
Digit Address
Bit 2 (MSB)
32
VDD = Logical One
VSS = Logical Zero
CS1
Chip Select 1
33
VDD = Inactive
VSS = Active
CS2
Chip Select 2
34
VDD = Inactive
VSS = Active
FUNCTION
DA1 and DA2 serve as a 2-bit Digit Address Input
DA2, DA1 = 00 selects D4
DA2, DA1 = 01 selects D3
DA2, DA1 = 10 selects D2
DA2, DA1 = 11 selects D1
When both CS1 and CS2 are taken low, the data at the Data
and Digit Select code inputs are written into the input latches.
On the rising edge of either Chip Select, the data is decoded
and written into the output latches.
Timing Diagrams
tIDS
DIGIT SELECT
DN-1
tWH
tIDS
tDH
DIGIT SELECT
DN
DATA VALID
DN-1
DATA VALID
DN
tDS
FIGURE 1. MULTIPLEXED INPUT
CS1
(CS2)
CS2
(CS1)
DATA AND
DIGIT
ADDRESS
tICS
tWI
tDH
tDS
= DON’T CARE
FIGURE 2. MICROPROCESSOR INTERFACE INPUT
9-12
ICM7211, ICM7212
Typical Performance Curves
30
180
LCD DEVICES, TA = 25oC
LCD DEVICES, TEST CIRCUIT
DISPLAY BLANK, PIN 36 OPEN
25
150
COSC = 0pF
(PIN 36 OPEN)
TA = -20oC
120
TA = 25oC
ƒBP (Hz)
IOP (µA)
20
15
10
COSC = 22pF
90
60
TA = 70oC
5
COSC = 220pF
30
0
1
2
3
4
5
6
1
7
2
3
VSUPP (V)
FIGURE 3. ICM7211 OPERATING SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE
15
4
VSUPP (V)
5
6
FIGURE 4. ICM7211 BACKPLANE FREQUENCY AS A
FUNCTION OF SUPPLY VOLTAGE
12
PIN 5 AT VDD , TA = 25oC
SEGMENT OUTPUT AT +3V
TA = 25oC
10
VSUPP = 6V
10
ISEG (mA)
ISEG(mA)
8
VSUPP = 5V
5
VSUPP = 4V
6
4
2
0
0
1
2
3
4
VO (V)
5
6
0
FIGURE 5. ICM7212 LED SEGMENT CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE
1
2
3
4
VOLTAGE ON BRT PIN 5 (V)
POWER (mW)
LED DEVICES, DISPLAY ALL EIGHTS
LED FORWARD VOLTAGE DROP
VFLED = 1.7V, PIN 5 AT VDD , TA = 25oC
1200
900
600
300
0
4
6
FIGURE 6. ICM7212 LED SEGMENT CURRENT AS A
FUNCTION OF BRIGHTNESS CONTROL VOLTAGE
1800
1500
5
5
VSUPP (V)
6
FIGURE 7. ICM7212 OPERATING POWER (LED DISPLAY) AS A FUNCTION OF SUPPLY VOLTAGE
9-13
ICM7211, ICM7212
Description Of Operation
OSCILLATOR
FREQUENCY
LCD Devices
128 CYCLES
The LCD devices in the family (ICM7211, ICM7211A,
ICM7211M, ICM7211AM) provide outputs suitable for driving
conventional four-digit, seven-segment LCD displays. These
devices include 28 individual segment drivers, backplane
driver, and a self-contained oscillator and divider chain to
generate the backplane frequency.
The segment and backplane drivers each consist of a
CMOS inverter, with the N-Channel and P-Channel devices
ratioed to provide identical on resistances, and thus equal
rise and fall times. This eliminates any DC component, which
could arise from differing rise and fall times, and ensures
maximum display life.
The backplane output devices can be disabled by connecting the OSCillator input (pin 36) to VSS . This allows the 28
segment outputs to be synchronized directly to a signal input
at the BP terminal (pin 5). In this manner, several slave
devices may be cascaded to the backplane output of one
master device, or the backplane may be derived from an
external source. This allows the use of displays with characters in multiples of four and a single backplane. A slave
device represents a load of approximately 200pF (comparable to one additional segment). Thus the limitation of the
number of devices that can be slaved to one master device
backplane driver is the additional load represented by the
larger backplane of displays of more than four digits. A good
rule of thumb to observe in order to minimize power consumption is to keep the backplane rise and fall times less
than about 5µs. The backplane output driver should handle
the backplane to a display of 16 one-half inch characters. It
is recommended, if more than four devices are to be slaved
together, the backplane signal be derived externally and all
the ICM7211 devices be slaved to it. This external signal
should be capable of driving very large capacitive loads with
short (1 - 2µs) rise and fall times. The maximum frequency
for a backplane signal should be about 150Hz although this
may be too fast for optimum display response at lower display temperatures, depending on the display type.
The onboard oscillator is designed to free run at approximately 19kHz at microampere current levels. The oscillator
frequency is divided by 128 to provide the backplane frequency, which will be approximately 150Hz with the oscillator
free-running; the oscillator frequency may be reduced by
connecting an external capacitor between the OSCillator terminal and VDD .
The oscillator may also be overdriven if desired, although care
must be taken to ensure that the backplane driver is not disabled during the negative portion of the overdriving signal
(which could cause a DC component to the display). This can
be done by driving the OSCillator input between the positive
supply and a level out of the range where the backplane disable
is sensed (about one fifth of the supply voltage above VSS).
Another technique for overdriving the oscillator (with a signal
swinging the full supply) is to skew the duty cycle of the overdriving signal such that the negative portion has a duration
shorter than about one microsecond. The backplane disable
sensing circuit will not respond to signals of this duration.
BACKPLANE
INPUT/OUTPUT
64 CYCLES
64 CYCLES
OFF
SEGMENTS
ON
SEGMENTS
FIGURE 8. DISPLAY WAVEFORMS
LED Devices
The LED device in the family (ICM7212AM) provides outputs
suitable for directly driving four-digit, seven-segment
common-anode LED displays. These devices include 28
individual segment drivers, each consisting of a low-leakage,
current-controlled, open-drain, N-Channel transistor.
The drain current of these transistors can be controlled by
varying the voltage at the BRtrighTness input (pin 5). The voltage at this pin is transferred to the gates of the output devices
for “on” segments, and thus directly modulates the transistor’s
“on” resistance. A brightness control can be easily implemented with a single potentiometer controlling the voltage at
pin 5, connected as in Figure 9. The potentiometer should be
a high value (100kΩ to 1MΩ) to minimize power consumption,
which can be significant when the display is off.
VDD (LED ANODES)
100kΩ TO 1MΩ
BRIGHTNESS
PIN 5
FIGURE 9. BRIGHTNESS CONTROL
The brightness input may also be operated digitally as a display enable; when high, the display is fully on, and low fully
off. The display brightness may also be controlled by varying
the duty cycle of a signal swinging between the two voltages
at the brightness input.
Note that the LED device has two connections for VSS ; both
of these pins should be connected. The double connection is
necessary to minimize effects of bond wire resistance with
the large total display currents possible.
When operating LED devices at higher temperatures and/or
higher supply voltages, the device power dissipation may
need to be reduced to prevent excessive chip temperatures.
The maximum power dissipation is 1W at 25oC, derated linearly above 35oC to 500mW at 70oC (-15mW/ oC above
35oC). Power dissipation for the device is given by:
P = (VSUPP - VFLED)(lSEG)(nSEG)
where VFLED is the LED forward voltage drop, ISEG is
segment current, and nSEG is the number of “on” segments.
It is recommended that if the device is to be operated at
9-14
ICM7211, ICM7212
elevated temperatures the segment current be limited by use
of the brightness input to keep power dissipation within the
limits described above.
Input Configurations and Output Codes
The standard devices in the ICM7211 and ICM7212 family
accept a four-bit true binary (i.e., positive level = logical one)
input at pins 27 thru 30, least significant bit at pin 27 ascending to the most significant bit at pin 30. The ICM7211 and
ICM7211M devices decode this binary input into a sevensegment alphanumeric hexadecimal output, while the
ICM7211A, ICM7211AM, and ICM7212AM decode the
binary input into seven-segment alphanumeric “Code B” output, i.e., 0-9, dash, E, H, L, P, blank. These codes are shown
explicitly in Table 1. Either decoder option will correctly
decode true BCD to a seven-segment decimal output.
TABLE 1. OUTPUT CODES
BlNARY
B3
B2
B1
BO
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
HEXADECIMAL
ICM7211
ICM7211M
CODE B
ICM7211A
ICM7212AM
These devices are actually mask-programmable to provide
any 16 combinations of the seven segment outputs decoded
from the four input bits. For large quantity orders custom
decoder options can be arranged. Contact the factory for
details.
The ICM7211 and ICM7211A devices are designed to accept
multiplexed binary or BCD input. These devices provide four
separate digit lines (least significant digit at pin 31 ascending
to most significant digit at pin 34), each of which when taken
to a positive level decodes and stores in the output latches of
its respective digit the character corresponding to the data at
the input port, pins 27 through 30.
The ICM7211M, ICM7211AM, and ICM7212AM devices are
intended to accept data from a data bus under processor
control.
In these devices, the four data input bits and the two-bit digit
address (DA1 pin 31, DA2 pin 32) are written into input buffer
latches when both chip select inputs (CS1 pin 33, CS2 pin
34) are taken low. On the rising edge of either chip select
input, the content of the data input latches is decoded and
stored in the output latches of the digit selected by the contents of the digit address latches.
An address of 00 writes into D4, DA2 = 0, DA1 = 1 writes into
D3, DA2 = 1, DA1 = 0 writes into D2, and 11 writes into D1.
The timing relationships for inputting data are shown in
Figure 2, and the chip select pulse widths and data setup and
hold times are specified under Operating Characteristics.
a
0
1
0
0
0
1
0
1
0
1
1
0
f
b
g
e
c
d
FIGURE 10. SEGMENT ASSIGNMENT
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
BLANK
9-15
ICM7211, ICM7212
Test Circuit
VDD
+
VSS
-
1 VDD
2
40
3
38
4
37
5 BP
OSC
36
6
VSS
35
7
8
9
EACH SEGMENT
OUTPUT TO
BACKPLANE
WITH A 200pF
CAPACITOR
39
ICM7211AM
10
34
DIGIT/CHIP
SELECT
INPUTS
11
33
VDD
MICROPROCESSOR
VERSION
VSS
MULTIPLEXED
VERSION
32
31
30
12
DATA
INPUTS
13
29
VDD
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
FIGURE 11.
Typical Applications
D8
D7
D6
D5
D4
D3
D2
D1
BACKPLANE
8-DIGIT
LCD DISPLAY
BACKPLANE
SLAVE
+5V
VDD
BACKPLANE
MASTER
28
+5V
SEGMENTS
HIGH ORDER
ICM7211A
VSS
OSC
B3-B0
SEGMENTS
LOW ORDER
ICM7211A
VSS
OSC
D4 D3 D2 D1 BP
4
BCD/BINARY
DATA
VDD
28
B3-B0
D4 D3 D2 D1 BP
4
4
D8
D7
D6
DIGIT
SELECTS
D5
D4
D3
D2
D1
FIGURE 12. GANGED ICM7211’s DRIVING 8-DIGIT LCD DISPLAY
9-16
ICM7211, ICM7212
Typical Applications
(Continued)
8 DIGIT
LCD DISPLAY
ICM7211M
HIGH ORDER DIGITS
+5V
40 26
VCC VDD
NC
INPUT
20 P10 27
VSS
28
29
2 XTAL1
30
31
32
3 XTAL2
33
4 RESET
P17 34
P20 21
7 EA
22
23
24
35
5 SS
80C48
36
µCOMPUTER
37
P27 38
1 TO
DB0 12
13
39 T1
14
15
6 INT
16
17
18
DB7 19
ALE PSEN PROG WR
11
9
25 10
+5V
ICM7211M
LOW ORDER DIGITS
1 VDD
2, 3, 4
SEGMENTS 6-26
35 VSS
37-40
DATA
36 OSC B0-B3
I/O
BP 5
DS1 DS2 CS1 CS2
27 28 29 30 31 32 33 34
BP 5
DATA
B0-B3
2, 3, 4
1 VDD
6-26 SEGMENTS
35 VSS
37-40
36 OSC
+5V
DS1 DS2 CS1 CS2
27 28 29 30 31 32 33 34
I/O
RD
8
FIGURE 13. 80C48 MICROPROCESSOR INTERFACE
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
9-17
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement