sps32 dataremanence1

sps32 dataremanence1
Data remanence in non-volatile
semiconductor memory (Part I)
Security Group
Sergei Skorobogatov
Web: www.cl.cam.ac.uk/~sps32/
Email: [email protected]
Introduction
Data remanence is the residual physical representation of data that has
been erased or overwritten. In non-volatile programmable devices, such
as UV EPROM, EEPROM or Flash, bits are stored as charge in the
floating gate of a transistor. After each erase operation, some of this
charge remains. It shifts the threshold voltage (VTH) of the transistor
which can be detected by the sense amplifier while reading data.
Microcontrollers use a ‘protection fuse’ bit that restricts unauthorized
access to on-chip memory if activated. Very often, this fuse is
embedded in the main memory array. In this case, it is erased
simultaneously with the memory. Better protection can be achieved if
the fuse is located close to the memory but has a separate control
circuit. This allows it to be permanently monitored as well as hardware
protected from being erased too early, thus making sure that by the time
the fuse is reset no data is left inside the memory.
In some smartcards and microcontrollers, a password-protected bootloader restricts firmware updates and data access to authorized users
only. Usually, the on-chip operating system erases both code and data
memory before uploading new code, thus preventing any new
application from accessing previously stored secrets.
UV EPROM
EEPROM
Flash EEPROM
Structure, cross-section and operation modes for different memory types
How much residual charge is left inside the memory cells
after a standard erase operation? Is it possible to recover data
from erased memory?
Non-invasive data recovery from erased memory
UV erase of PIC12C509
7
6
V DD/V
5
4
3
2
1
0
0
2
4
6
8
10
12
14
t/min
EPROM OK
EPROM ERASED
OLD FUSE
NEW FUSE
EPROM memory state at various VDD
Electrical erase of PIC16F84A
7
6
V DD/V
5
4
3
2
1
0
0
20
40
60
80
100
120
140
t/µs
FLASH OK
FLASH ERASED
FUSE
Flash memory state at various VDD
Test board for data remanence evaluation
Threshold voltage change during erase cycles
Threshold voltage distribution
0.6
0.6
0.5
0.55
V TH/V
0.4
V TH/V
Erasing EPROM with UV light is a very slow
process, typically taking 10–20 minutes. Usually, the
read sense amplifier compares the threshold voltage
of memory transistors with half of the power-supply
voltage. This allows the memory to operate under a
wide range of supply voltages. We can change the
power supply voltage briefly, to affect this reference
Power glitching technique
Charge alteration technique
voltage enough to sense the ‘erased’ data, without
disturbing normal operation of the device. If the floating gate was discharged
deeply enough to reveal no data at any supply voltage, another technique can be
used. It involves careful injection of a precisely controlled amount of charge
into every memory cell, thus shifting their threshold voltages to the level where
a difference between programmed and non-programmed cells can be detected.
The fast write/erase process in EEPROM and Flash memory leaves us no
chance to recover information using the above techniques. If the floating gate is
Charge loss during electrical erase
discharged exponentially, like a capacitor, by the time the security fuse is reset,
no significant charge would be left inside the floating-gate transistor. Taking into account
that a standard erase cycle is 10 ms long, this ensures protection against attempts to recover
erased data.
To investigate the actual situation with data remanence in EEPROM and Flash devices, a
special test board was built. It applies power glitches synchronized to the clock signal. By
exploiting one of the previously found vulnerabilities of EEPROM/Flash memory in
conjunction with power glitching, precise measurements of the threshold voltage for each
individual memory transistor became possible. Applying this technique to the Microchip
PIC16F84A microcontroller revealed that, even after a hundred consecutive erase cycles, the
program code inside the Flash memory can be fully restored. However, the EEPROM data
memory could be recovered only if less than ten bulk erase cycles were applied.
Only a fraction of all microcontrollers are vulnerable to the above techniques, because many benefit from voltage monitors and internal supply
stabilizers. In addition, rewriting all the memory locations to their charged
state makes data recovery infeasible. Nevertheless, the fact that data can be
recovered from erased memory cells in such devices can form a significant
security risk. Secure devices should be tested for possible data remanence
effects.
V distribution along the memory
0.3
0.2
0.5
0.45
0.4
0.1
0
0.35
0
100
200
300
400
500
Number of erase cycles
PROGRAMMED
FULLY ERASED
Threshold change during erase cycles
600
0
7
14
21
28
Memory address
FIRST ERASE
SECOND ERASE
TH
2004-10-29
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