Epson | SED 1520 Series | SED1520 - Crystalfontz

s
e
ri
0
2
5
1
S
D
E
D
C
L
e
S
iv
r
d
w
r
e
ith
M
A
R
l
a
M
al
ic
n
ch
Te
a
nu
NOTICE
No parts of this material may be reproduced or duplicated in any form or by any means without the written
permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice.
Seiko Epson does not assume any liability of any kind aristing out of any inaccuracies contained in this
material or due to its application or use in any product or circuit and, further, there is no representation that
this material is applicable to products requiring high level reliability, such as, medical products. Moreover,
no license to any intellectual property rights is granted by implication or otherwise, and there is no
representation or warranty that anything made in accordance with this material will be free from any patent
or copyright infringement of a third party. This material or portions thereof may contain technology or the
subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control
Law of Japan and may require an export licence from teh Ministry of International Trade and Industry or other
approval from another government agency.
© Seiko Epson corporation 1998 All right reserved.
i8088 and i8086 are registered trademarks of Intel Corporation.
Z80 is registered trademark of Zilog Corporation.
V20 and V30 are registered trademarks of Nippon Electric Corporation.
SED1520 Series
Contents
OVERVIEW .......................................................................................................................................................... 2-1
BLOCK DIAGRAM ................................................................................................................................................ 2-2
PACKAGE OUTLINE ............................................................................................................................................ 2-3
PAD ...................................................................................................................................................................... 2-4
Pad Arrangement ......................................................................................................................................... 2-4
PAD ARRANGEMENT ......................................................................................................................................... 2-5
PIN DESCRIPTION .............................................................................................................................................. 2-6
(1) Power Pins ............................................................................................................................................. 2-6
(2) System Bus Connection Pins ................................................................................................................. 2-6
(3) LCD Drive Circuit Signals ....................................................................................................................... 2-7
BLOCK DESCRIPTION ........................................................................................................................................ 2-8
System Bus .................................................................................................................................................. 2-8
Display Start Line and Line Count Registers ............................................................................................... 2-9
Column Address Counter ............................................................................................................................. 2-9
Page Register .............................................................................................................................................. 2-9
Display Data RAM ........................................................................................................................................ 2-9
Common Timing Generator Circuit ............................................................................................................ 2-10
Display Data Latch Circuit .......................................................................................................................... 2-10
LCD Driver Circuit ...................................................................................................................................... 2-10
Display Timing Generator .......................................................................................................................... 2-10
Oscillator Circuit (SED1520*0A Only) ........................................................................................................ 2-11
Reset Circuit .............................................................................................................................................. 2-11
COMMANDS ...................................................................................................................................................... 2-14
Summary .................................................................................................................................................... 2-14
Command Description ............................................................................................................................... 2-15
SPECIFICATIONS .............................................................................................................................................. 2-20
Absolute Maximum Ratings ....................................................................................................................... 2-20
Electrical Specifications ............................................................................................................................. 2-20
APPLICATION NOTES ....................................................................................................................................... 2-26
MPU Interface Configuration ...................................................................................................................... 2-26
LCD Drive Interface Configuration ............................................................................................................. 2-27
LCD Panel Wiring Example ....................................................................................................................... 2-29
Package Dimensions ................................................................................................................................. 2-30
–i–
SED1520
Series
FEATURES ........................................................................................................................................................... 2-1
OVERVIEW
FEATURES
The SED1520 family of dot matrix LCD drivers are
designed for the display of characters and graphics. The
drivers generate LCD drive signals derived from bit
mapped data stored in an internal RAM.
The drivers are available in two configurations
The SED1520 family drivers incorporate innovative
circuit design strategies to achieve very low power
dissipation at a wide range of operating voltages.
These features give the designer a flexible means of
implementing small to medium size LCD displays for
compact, low power systems.
• The SED1520 which is able to drive two lines of
twelve characters each.
• The SED1521 which is able to drive 80 segments for
extention.
• The SED1522 which is able to drive one line of
thirteen characters each.
• Fast 8-bit MPU interface compatible with 80- and 68family microcomputers
• Many command set
• Total 80 (segment + common) drive sets
• Low power — 30 µW at 2 kHz external clock
• Wide range of supply voltages
VDD – VSS: –2.4 to –7.0 V
VDD – V5: –3.5 to –13.0 V
• Low-power CMOS
Line-up
Product
Name
SED1520*0*
SED1521*0*
SED1522*0*
SED1520*A*
SED1521*A*
SED1522*A*
Clock Frequency
Applicable Driver
On-Chip External
18 kHz
—
18 kHz
—
—
—
18 kHz
18 kHz
18 kHz
2 kHz
2 kHz
2 kHz
SED1520*0*, SED1521*0*
SED1520*0*, SED1522*0*
SED1522*0*, SED1521*0*
SED1520*A*, SED1521*A*
SED1520*A*, SED1522*A*
SED1522*A*, SED1521*A*
Number Number
of SEG of CMOS
Duty
Drivers Drivers
61
16
1/16, 1/32
80
0
1/8 to 1/32
69
8
1/8, 1/16
61
16
1/16, 1/32
80
0
1/8 to 1/32
69
8
1/8, 1/16
• Package code (For example SED1520)
SED1520T
SED1520F*A (QFP5-100pin)
SED1520F**: PKG
SED1520F*C (QFP15-100pin)
SED1520D*A (Al-pad)
SED1520D**: Chip
SED1520D*B (Au-bump)
EPSON
2–1
SED1520
Series
SED1520 Series
SED1520 Series
BLOCK DIAGRAM
An example of SED1520 AA:
LCD drive circuit
Display data RAM
(2560-bit)
I/O buffer
Display data latch circuit
Line address decoder
Line counter
Display start line register
Common counter
FR
Display
timing
generator
circuit
Column address counter
Column address register
Command
decoder
Status
2–2
RES
RD,WR
EPSON
(E,R/W)
M/S
A0,CS
D0~D7
MPU interface
Bus
holder
CL
Low-address
register
Column address decoder
VSS
VDD
SEG0 to SEG60
V1,V2,V3,V4,V5
COM0 to COM15
*
SED1520 Series
PACKAGE OUTLINE
85
45
90
40
Index
95
25
20
15
5
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
SEG44
SEG43
SEG42
100
10
35
SED1520
Series
55
60
65
75
CS2
CS3
CS4
CS5
CS6
CS7
VDD
RES
F2
V5
V1
V2
M/S
V4
V1
COM0
COM1
COM2
COM3
COM4
70
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
A0
CS(OSC1)
CL(OSC2)
E(RD)
R/W(WR)
VSS
CS0
CS1
QFP5
55
60
65
70
80
46
50
45
85
40
90
35
95
20
15
10
5
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
COM 7
COM 8
COM 9
COM10
COM11
COM12
COM13
COM14
COM15
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
SEG47
SEG46
SEG45
25
30
Index
1
VSS
D30
D31
D32
D33
D34
D35
D36
D37
VDD
RES
FR
V5
V3
V2
M/S
V4
V1
COM 0
COM 1
COM 2
COM 3
COM 4
COM 5
COM 6
75
46
R/W(WR)
E (RD)
CL (OSC2)
CS (OSC1)
AQ
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
QFP15
Note: This is an example of SED1520F pin assignment. The modified pin names are given below.
Product
Name
SED1520F0A
SED1521F0A
SED1522F0A
SED1520FAA
SED1521FAA
SED1522FAA
74
OSC1
CS
OSC1
CS
CS
CS
75
OSC2
CL
OSC2
CL
CL
CL
Pin/Pad Number
96 to 100, 1 to 11
93
COM0 to COM15*
M/S
SEG76 to SEG61
SEG79
COM0 to 7, SEG68 to 61
M/S
COM0 to COM15*
M/S
SEG76 to SEG61
SEG79
COM0 to 7, SEG68 to 61
M/S
94
V4
SEG78
V4
V4
SEG78
V4
95
V1
SEG77
V1
V1
SEG77
V1
SED1520: Common outputs COM0 to COM15 of the master LSI correspond to COM31 to COM16 of the
slave LSI.
SED1522: Common outputs COM0 to COM15 of the master LSI correspond to COM15 to COM8 of the
slave LSI.
EPSON
2–3
SED1520 Series
PAD
Pad Arrangement
Chip specifications of gold bump package
Chip specifications of AL pad package
Chip size: 4.80×7.04×0.400 mm
Pad pitch: 100×100 µm
100
Chip size:
Bump pitch:
Bump height:
Bump size:
95
90
4.80×7.04×0.525 mm
199 µm (Min.)
22.5 µm (Typ.)
132×111 µm (±20 µm) for mushroom
model
116×92 µm (±4 µm) for vertical model
85
80
1
5
75
Y
15
70
7.04 mm
10
X
(0, 0)
65
20
25
30
D1520D AA *
60
55
35
40
45
50
4.80 mm
Note: An example of SED1520DAA die numbers is given. These numbers are the same as the bump
package.
2–4
EPSON
SED1520 Series
PAD ARRANGEMENT
An example of SED1520DA* pin names is given. The
SED1520DAB Pad Center Coordinates
Pad
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Pin
X
Name
COM5 159
COM6 159
COM7 159
COM8 159
COM9 159
COM10 159
COM11 159
COM12 159
COM13 159
COM14 159
COM15 159
SEG60 159
SEG59 159
SEG58 159
SEG57 159
SEG56 159
SEG55 159
SEG54 159
SEG53 159
SEG52 159
SEG51 159
SEG50 159
SEG49 159
SEG48 159
SEG47 159
SEG46 159
SEG45 159
SEG44 159
SEG43 159
SEG42 159
SEG41 504
SEG40 704
SEG39 903
SEG38 1103
Y
6507
6308
6108
5909
5709
5510
5310
5111
4911
4712
4512
4169
3969
3770
3570
3371
3075
2876
2676
2477
2277
2078
1878
1679
1479
1280
1080
881
681
482
159
159
159
159
Pad
No.
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
Pin
Name
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
X
Y
1302
1502
1701
1901
2100
2300
2499
2699
2898
3098
3297
3497
3696
3896
4095
4295
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
159
482
681
881
1080
1280
1479
1679
1878
2078
2277
2477
2676
2876
3075
3275
3474
3674
3948
Pad
No.
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Pin
Name
SEG3
SEG2
SEG1
SEG0
A0
CS
CL
E (RD)
R/W (WR)
VSS
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
VDD
RES
FR
V5
V3
V2
M/S
V4
V1
COM0
COM1
COM2
COM3
COM4
X
Y
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4641
4295
4095
3896
3696
3497
3297
3098
2898
2699
2499
2300
2100
1901
1701
1502
1302
1103
903
704
504
4148
4347
4547
4789
5048
5247
5447
5646
5846
6107
6307
6506
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
6884
The other SED1520 series packages have the different pin names as shown.
Package/Pad No.
SED1520D0*
SED1522D0*
SED1522DA*
SED1521D0*
SED1521DA*
74
OSC1
OSC1
OSC1
CS
CS
75
OSC2
OSC2
OSC2
CL
CL
96 to 100, 1 to 11
COM0 to COM15 *
COM0 to 7, SEG68 to 61
COM0 to 7, SEG68 to 61
SEG76 to SEG61
SEG76 to SEG61
EPSON
93
M/S
M/S
M/S
SEG79
SEG79
94
V4
V4
V4
SEG78
SEG78
95
V1
V1
V1
SEG77
SEG77
2–5
SED1520
Series
asterisk (*) can be A for AL pad package or B for gold
bump package.
SED1520 Series
PIN DESCRIPTION
(1) Power Pins
Name
Description
VDD
Connected to the +5Vdc power. Common to the VCC MPU power pin.
VSS
0 Vdc pin connected to the system ground.
V1, V2, V3, V4, V5
Multi-level power supplies for LCD driving. The voltage determined for each liquid
crystal cell is divided by resistance or it is converted in impedance by the op amp,
and supplied. These voltages must satisfy the following:
VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
(2) System Bus Connection Pins
D7 to D0
Three-state I/O.
The 8-bit bidirectional data buses to be connected to the 8- or 16-bit standard MPU
data buses.
A0
Input.
Usually connected to the low-order bit of the MPU address bus and used to identify
the data or a command.
A0=0: D0 to D7 are display control data.
A0=1: D0 to D7 are display data.
RES
CS
E (RD)
R/W (WR)
2–6
Input.
When the RES signal goes
the 68-series MPU is initialized, and when it
goes
, the 80-series MPU is initialized. The system is reset during edge
sense of the RES signal. The interface type to the 68-series or 80-series MPU is
selected by the level input as follows:
High level: 68-series MPU interface
Low level: 80-series MPU interface
Input. Active low. Effective for an external clock operation model only.
An address bus signal is usually decoded by use of chip select signal, and it is
entered. If the system has a built-in oscillator, this is used as an input pin to the
oscillator amp and an Rf oscillator resistor is connected to it. In such case, the RD,
WR and E signals must be ORed with the CS signals and entered.
• If the 68-series MPU is connected:
Input. Active high.
Used as an enable clock input of the 68-series MPU.
• If the 80-series MPU is connected:
Input. Active low.
The RD signal of the 80-series MPU is entered in this pin. When this signal is
kept low, the SED1520 data bus is in the output status.
• If the 68-series MPU is connected:
Input.
Used as an input pin of read control signals (if R/W is high) or write control
signals (if low).
• If the 80-series MPU is connected:
Input. Active low.
The WR signal of the 80-series MPU is entered in this pin. A signal on the data
bus is fetched at the rising edge of WR signal.
EPSON
SED1520 Series
Name
Description
CL
Input. Effective for an external clock operation model only.
This is a display data latch signal to count up the line counter and common counter
at each signal falling and rising edges. If the system has a built-in oscillator, this is
used as an output pin of the oscillator amp and an Rf oscillator resistor is connected to it.
FR
Input/output.
This is an I/P pin of LCD AC signals, and connected to the M terminal of common
driver.
I/O selection
• Common oscillator built-in model: Output if M/S is 1;
Input if M/S is 0.
• Dedicate segment model:
Input
SEGn
Output.
The output pin for LCD column (segment) driving. A single level of VDD, V2, V3 and
V5 is selected by the combination of display RAM contents and RF signal.
1
0
FR signal
1
0
1
0
V DD
V2
V5
V3
Data
Output level
COMn
Output.
The output pin for LCD common (low) driving. A single level of VDD, V1, V4 and V5
is selected by the combination of common counter output and RF signal. The
slave LSI has the reverse common output scan sequence than the master LSI.
1
0
FR signal
1
0
1
0
V5
V1
V DD
V4
Counter output
Output level
M/S
Input.
The master or slave LSI operation select pin for the SED1520 or SED1522.
Connected to VDD (to select the master LSI operation mode) or VSS (to select the
slave LSI operation mode).
When this M/S pin is set, the functions of FR, COM0 to COM15, OSC1 (CS), and
OSC2 (CL) pins are changed.
M/S
FR
COM output
OSC1
OSC2
SED1520F0A
VDD
Output
COM0 to COM15
Input
Output
VSS
Input
COM31 to COM16
NC
Input
SED1522F0A
VDD
Output
COM0 to COM7
Input
Output
VSS
Input
COM15 to COM8
NC
Input
* The slave driver has the reverse common output scan sequence than the master
driver.
EPSON
2–7
SED1520
Series
(3) LCD Drive Circuit Signals
SED1520 Series
BLOCK DESCRIPTION
System Bus
MPU interface
level after reset (see Table 1).
When the CS signal is high, the SED1520 series is
disconnected from the MPU bus and set to stand by.
However, the reset signal is entered regardless of the
internal setup status.
1. Selecting an interface type
The SED1520 series transfers data via 8-bit bidirectional data buses (D0 to D7). As its Reset pin has the
MPU interface select function, the 80-series MPU or
the 68-series MPU can directly be connected to the
MPU bus by the selection of high or low RES signal
Table 1
RES signal input level
Active low
Active high
MPU type
68-series
80-series
A0
↑
↑
E
↑
RD
R/W
↑
WR
CS
↑
↑
D0 to D7
↑
↑
Data transfer
The SED1520 and SED1521 drivers use the A0, E (or
RD) and R/W (or WR) signals to transfer data between
the system MPU and internal registers. The combinations used are given in the table blow.
In order to match the timing requirements of the MPU
with those of the display data RAM and control registers
all data is latched into and out of the driver. This
introduces a one cycle delay between a read request for
data and the data arriving. For example when the MPU
Common
A0
1
1
0
0
2–8
68 MPU
R/W
1
0
1
0
executes a read cycle to access display RAM the current
contents of the latch are placed on the system data bus
while the desired contents of the display RAM are moved
into the latch.
This means that a dummy read cycle has to be executed
at the start of every series of reads. See Figure 1.
No dummy cycle is required at the start of a series of
writes as data is transferred automatically from the input
latch to its destination.
80 MPU
RD
0
1
0
1
WR
1
0
1
0
EPSON
Function
Read display data
Write display data
Read status
Write to internal register (command)
SED1520 Series
WRITE
WR
MPU
Internal
timing
N
N+1
N+2
N+3
SED1520
Series
DATA
Bus
N+1
N
hold
N+2
N+3
WR
READ
WR
RD
MPU
DATA
N
N
Address set
at N
n
Dummy read
Data read
at N
n+1
Data read
at N + 1
WR
RD
Internal
timing
Column
N
address
Bus
hold
N+1
N
n
N+2
n+1
n+2
Figure 1 Bus Buffer Delay
Busy flag
Column Address Counter
When the Busy flag is logical 1, the SED1520 series is
executing its internal operations. Any command other
than Status Read is rejected during this time. The Busy
flag is output at pin D7 by the Status Read command. If
an appropriate cycle time (tcyc) is given, this flag needs
not be checked at the beginning of each command and,
therefore, the MPU processing capacity can greatly be
enhanced.
The column address counter is a 7-bit presettable counter
that supplies the column address for MPU access to the
display data RAM. See Figure 2. The counter is
incremented by one every time the driver receives a Read
or Write Display Data command. Addresses above 50H
are invalid, and the counter will not increment past this
value. The contents of the column address counter are set
with the Set Column Address command.
Display Start Line and Line Count
Registers
Page Register
The contents of this register form a pointer to a line of
data in display data RAM corresponding to the first line
of the display (COM0), and are set by the Display Start
Line command. See section 3.
The contents of the display start line register are copied
into the line count register at the start of every frame, that
is on each edge of FR. The line count register is
incremented by the CL clock once for every display line,
thus generating a pointer to the current line of data, in
display data RAM, being transferred to the segment
driver circuits.
The page resiter is a 2-bit register that supplies the page
address for MPU access to the display data RAM. See
Figure 2. The contents of the page register are set by the
Set Page Register command.
Display Data RAM
The display data RAM stores the LCD display data, on a
1-bit per pixel basis. The relation-ship between display
data, display address and the display is shown in Figure
2.
EPSON
2–9
SED1520 Series
Common Timing Generator Circuit
Generates common timing signals and FR frame signals
from the CL basic clock. The 1/16 or 1/32 duty (for
SED1520) or 1/8 or 1/16 duty (for SED1522) can be
selected by the Duty Select command. If the 1/32 duty is
selected for the SED1520 and 1/16 duty is selected for the
SED1522, the 1/32 and 1/16 duties are provided by two
chips consisting of the master and slave chips in the
common multi-chip mode.
SED1520
FR signal
(Master output)
Master Common
0
1
2
14 15
Slave Common
0
16 17
1
15
30 31
16 17
31
8
15
SED1522
FR signal
(Master output)
Master Common
0
1
2
6
7
Slave Common
0
8
9
14 15
1
7
9
Display Data Latch Circuit
Display Timing Generator
This latch stores one line of display data for use by the
LCD driver interface circuitry. The output of this latch
is controlled by the Display ON/OFF and Static Drive
ON/OFF commands.
This circuit generates the internal display timing signal
using the basic clock, CL, and the frame signals, FR.
FR is used to generate the dual frame AC-drive waveform (type B drive) and to lock the line counter and
common timing generator to the system frame rate.
CL is used to lock the line counter to the system line scan
rate. If a system uses both SED1520s or SED1522 and
SED1521s they must have the same CL frequency rating.
LCD Driver Circuit
The LCD driver circuitry generates the 80 4-level signals
used to drive the LCD panel, using output from the
display data latch and the common timing generator
circuitry.
2–10
EPSON
SED1520 Series
Oscillator Circuit (SED1520
*0A Only)
SED1520
Series
A low power-consumption CR oscillator for adjusting
the oscillation frequency using Rf oscillation resistor
only. This circuit generates a display timing signal.
Some of SED1520 and SED1522 series models have a
built-in oscillator and others use an external clock. This
difference must be checked before use.
Connect the Rf oscillation resistor as follows. To suppress the built-in oscillator circuit and drive the MPU
using an external clock, enter the clock having the same
phase as the OSC2 of mater chip into OSC2 of the slave
chip.
• MPU having a built-in oscillator
V DD
Master chip
Slave chip
M/S
M/S
(CS)
OSC1
(CL)
OSC2
VSS
(CS)
OSC1
(CL)
OSC2
Rf
*2
Open
*1
*1 If the parasitic capacitance of this section increases, the oscillation frequency may shift to the lower
frequency. Therefore, the Rf oscillation frequency must be reduced below the specified level.
*2 A CMOS buffer is required if the oscillation circuit is connected to two or more slave MPU chips.
• MPU driven with an external clock
Y driver
SED1521FAA
CL2
CL
Detects a rising or falling edge of an RES input and
initializes the MPU during power-on.
• Initialization status
1. Display is off.
2. Display start line register is set to line 1.
3. Static drive is turned off.
4. Column address counter is set to address 0.
5. Page address register is set to page 3.
6. 1/32 duty (SED1520) or 1/16 duty (SED1522) is
selected.
7. Forward ADC is selected (ADC command D0 is
1 and ADC status flag is 1).
8. Read-modify-write is turned off.
The input signal level at RES pin is sensed, and an
MPU interface mode is selected as shown on Table 1.
For the 80-series MPU, the RES input is passed
through the inverter and the active high reset signal
must be entered. For the 68-series MPU, the active
low reset signal must be entered.
As shown for the MPU interface (reference example),
the RES pin must be connected to the Reset pin and
reset at the same time as the MPU initialization.
If the MPU is not initialized by the use of RES pin
during power-on, an unrecoverable MPU failure may
occur.
When the Reset command is issued, initialization
Reset Circuit
EPSON
2–11
SED1520 Series
Page address
Page 0
Line
address
Start line
(Example)
Start
1/16
Response
Common
output
COM 0
COM 1
COM 2
COM 3
COM 4
COM 5
COM 6
COM 7
COM 8
COM 9
COM 10
COM 11
COM 12
COM 13
COM 14
COM 15
COM 16
COM 17
COM 18
COM 19
COM 20
COM 21
COM 22
COM 23
COM 24
COM 25
COM 26
COM 27
COM 28
COM 29
COM 30
COM 31
Figure 2 Display Data RAM Addressing
D1,D2 = 0,0
Page 1
Page 2
Page 3
00 H
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
EPSON
2–12
4D
4E
4F
02
01
00
77
78
79
0,1
SEG 0
1
2
3
4
5
6
7
1,0
1,1
SEG pin
ADC
D0 = "1" D0 = "0"
4F H
00 H
01
4E
02
4D
4C
03
4B
04
05
4A
49
06
07
48
DATA
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Column address
Display area
SED1520 Series
1/5 bias, 1/16 duty
1/6 bias, 1/32 duty
15 0 1 2 3
31 0 1 2 3
FR
COM0
COM0
COM1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM2
COM8
COM9
COM10
COM11
COM12
SEG0
COM13
COM14
SEG4
SEG3
SEG2
SEG1
SEG0
COM15
SEG1
COM0—SEG0
COM0—SEG1
15
31
V DD
V SS
V DD
V1
V2
V3
V4
V5
SED1520
Series
0 1 2 3
0 1 2 3
V DD
V1
V2
V3
V4
V5
V DD
V1
V2
V3
V4
V5
V DD
V1
V2
V3
V4
V5
V DD
V1
V2
V3
V4
V5
V5
V4
V3
V2
V1
V DD
-V1
-V2
-V3
-V4
-V5
V5
V4
V3
V2
V1
V DD
-V1
-V2
-V3
-V4
-V5
Figure 4 LCD drive waveforms example
EPSON
2–13
SED1520 Series
COMMANDS
Summary
Command
A0
RD WR
D7
D6
Code
D5
D4
D3
D2
D1
D0
1
1
1
0/1
Display On/OFF
0
1
0
1
0
1
0
Display start line
0
1
0
1
1
0
Display start address (0 to 31)
Set page address
0
1
0
1
0
1
1
Set column
(segment) address
0
1
0
0
Read status
0
0
1
Busy
Write display data
1
1
0
Write data
Read display data
1
0
1
Read data
Select ADC
Statis drive
ON/OFF
0
1
0
1
0
1
0
1
0
1
0
Select duty
0
1
0
1
Read-Modify-Write
End
Reset
0
0
0
1
1
1
0
0
0
1
1
1
2–14
1
0
Page (0 to 3)
Column address (0 to 79)
ADC ON/OFF Reset
0
0
0
0
0
0
0
0
0/1
1
0
0
1
0
0/1
0
1
0
1
0
0
0/1
1
1
1
1
1
1
0
0
0
0
1
0
0
1
0
0
1
1
0
0
0
EPSON
Function
Turns display on or off.
1: ON, 0: OFF
Specifies RAM line corresponding to top line
of display.
Sets display RAM page in page address
register.
Sets display RAM column address in
column address register.
Reads the following status:
BUSY
1: Busy
0: Ready
ADC
1: CW output
0: CCW output
ON/OFF
1: Display off
0: Display on
RESET
1: Being reset
0: Normal
Writes data from data bus into display RAM.
Reads data from display RAM onto data
bus.
0: CW output, 1: CCW output
Selects static driving operation.
1: Static drive, 0: Normal driving
Selets LCD duty cycle
1: 1/32, 0: 1/16
Read-modify-write ON
Read-modify-write OFF
Software reset
SED1520 Series
Command Description
Table 3 is the command table. The SED1520 series identifies a data bus using a combination of A0 and R/W (RD or WR)
signals. As the MPU translates a command in the internal timing only (independent from the external clock), its speed
is very high. The busy check is usually not required.
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
1
1
1
D
SED1520
Series
Display ON/OFF
AEH, AFH
This command turns the display on and off.
• D=1: Display ON
• D=0: Display OFF
Display Start Line
This command specifies the line address shown in Figure 3 and indicates the display line that corresponds to COM0. The
display area begins at the specified line address and continues in the line address increment direction. This area having
the number of lines of the specified display duty is displayed. If the line address is changed dynamically by this command,
the vertical smooth scrolling and paging can be used.
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
0
A4
A3
A2
A1
A0
C0H to DFH
This command loads the display start line register.
A4 A3 A2 A1 A0 Line Address
0
0
0
0
1
1
0
0
:
:
1
0
0
0
1
1
1
0
1
:
:
31
See Figure 2.
Set Page Address
This command specifies the page address that corresponds to the low address of the display data RAM when it is accessed
by the MPU. Any bit of the display data RAM can be accessed when its page address and column address are specified.
The display status is not changed even when the page address is changed.
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
1
1
0
A1
A0
B8H to BBH
This command loads the page address register.
A1 A0 Page
0
0
1
1
0
1
0
1
0
1
2
3
See Figure 2.
EPSON
2–15
SED1520 Series
Set Column Address
This command specifies a column address of the display data RAM. When the display data RAM is accessed by the MPU
continuously, the column address is incremented by 1 each time it is accessed from the set address. Therefore, the MPU
can access to data continuously. The column address stops to be incremented at address 80, and the page address is not
changed continuously.
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
A6
A5
A4
A3
A2
A1
A0
00H to 4FH
This command loads the column address register.
A6 A5 A4 A3 A2 A1 A0 Column Address
0
0
0
0
0
0
1
0
0
0
0
:
:
1
0
0
0
0
0
1
1
1
1
0
1
:
:
79
Read Status
A0
RD
R/W
WR
0
0
1
D7
D6
D5
D4
BUSY ADC ON/OFF RESET
D3
D2
D1
D0
0
0
0
0
Reading the command I/O register (A0=0) yields system status information.
• The busy bit indicates whether the driver will accept a command or not.
Busy=1: The driver is currently executing a command or is resetting. No new command will be accepted.
Busy=0: The driver will accept a new command.
• The ADC bit indicates the way column addresses are assigned to segment drivers.
ADC=1: Normal. Column address n → segment driver n.
ADC=0: Inverted. Column address 79-u → segment driver u.
• The ON/OFF bit indicates the current status of the display.
It is the inverse of the polarity of the display ON/OFF command.
ON/OFF=1: Display OFF
ON/OFF=0: Display ON
• The RESET bit indicates whether the driver is executing a hardware or software reset or if it is in normal operating mode.
RESET=1: Currently executing reset command.
RESET=0: Normal operation
Write Display Data
A0
RD
R/W
WR
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Write data
Writes 8-bits of data into the display data RAM, at a location specified by the contents of the column address and page
address registers and then increments the column address register by one.
2–16
EPSON
SED1520 Series
Read Display Data
RD
R/W
WR
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Read data
Reads 8-bits of data from the data I/O latch, updates the contents of the I/O latch with display data from the display data
RAM location specified by the contents of the column address and page address registers and then increments the column
address register.
After loading a new address into the column address register one dummy read is required before valid data is obtained.
Select ADC
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
0
0
0
D
A0H, A1H
This command selects the relationship between display data RAM column addresses and segment drivers.
D=1: SEG0 ← column address 4FH, … (inverted)
D=0: SEG0 ← column address 00H, … (normal)
This command is provided to reduce restrictions on the placement of driver ICs and routing of traces during printed circuit
board design. See Figure 2 for a table of segments and column addresses for the two values of D.
Static Drive ON/OFF
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
0
1
0
D
A4H, A5H
Forces display on and all common outputs to be selected.
D=1: Static drive on
D=0: Static drive off
Select Duty
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
1
0
1
0
0
D
A8H, A9H
This command sets the duty cycle of the LCD drive and is only valid for the SED1520F and SED1522F. It is invalid for
the SED1521F which performs passive operation. The duty cycle of the SED1521F is determined by the externally
generated FR signal.
SED1520
SED1522
D=1: 1/32 duty cycle
1/16 duty cycle
D=0: 1/16 duty cycle
1/8 duty cycle
When using the SED1520F0A, SED1522F0A (having a built-in oscillator) and the SED1521F0A continuously, set the duty
as follows:
SED1520F0A
SED1522F0A
1/32
1/16
1/16
1/8
EPSON
SED1521F0A
1/32
1/16
1/32
1/16
2–17
SED1520
Series
A0
SED1520 Series
Read-Modify-Write
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
0
0
0
0
E0H
This command defeats column address register auto-increment after data reads. The current conetents of the column
address register are saved. This mode remains active until an End command is received.
• Operation sequence during cursor display
When the End command is entered, the column address is returned to the one used during input of Read-Modify-Write
command. This function can reduce the load of MPU when data change is repeated at a specific display area (such as cursor
blinking).
* Any command other than Data Read or Write can be used in the Read-Modify-Write mode. However, the Column
Address Set command cannot be used.
Set Page Address
Set Column Address
Read-Modify-Write
Dummy Read
Read Data
Write Data
No
Completed?
Yes
End
End
A0
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
1
1
1
0
EEH
This command cancels read-modify-write mode and restores the contents of the column address register to their value prior
to the receipt of the Read-Modify-Write command.
Return
Column address
N
N+1
N+2
N+3
Read-Modify-Write mode is selected.
2–18
EPSON
N+m
N
End
SED1520 Series
Reset
RD
R/W
WR
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
1
0
0
0
1
0
E2H
This command clears
• the display start line register.
• and set page address register to 3 page.
It does not affect the contents of the display data RAM.
When the power supply is turned on, a Reset signal is entered in the RES pin. The Reset command cannot be used instead
of this Reset signal.
Power Save (Combination command)
The Power Save mode is selected if the static drive is turned ON when the display is OFF. The current consumption can
be reduced to almost the static current level. In the Power Save mode:
(a) The LCD drive is stopped, and the segment and common driver outputs are set to the VDD level.
(b) The external oscillation clock input is inhibited, and the OSC2 is set to the floating mode.
(c) The display and operation modes are kept.
The Power Save mode is released when the display is turned ON or when the static drive is turned OFF. If the LCD drive
voltage is supplied from an external resistance divider circuit, the current passing through this resistor must be cut by the
Power Save signal.
VDD
VDD
V1
V2
V3
SED1520
SED1522
V4
V5
Power Save signal
VSSH
If the LCD drive power is generated by resistance division, the resistance and capacitance are determined by the LCD panel
size. After the panel size has been determined, reduce the resistance to the level where the display quality is not affected
and reduce the power consumption using the divider resistor.
EPSON
2–19
SED1520
Series
A0
SED1520 Series
SPECIFICATIONS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply voltage (1)
VSS
–8.0 to +0.3
V
Supply voltage (2)
V5
–16.5 to +0.3
V
Supply voltage (3)
V1, V4, V2, V3
V5 to +0.3
V
Input voltage
VIN
VSS–0.3 to +0.3
V
Output voltage
VO
VSS–0.3 to +0.3
V
Power dissipation
PD
250
mW
Operating temperature
Topr
–40 to +85
deg. C
Storage temperature
Tstg
–65 to +150
deg. C
Soldering temperature time at lead
Tsol
260, 10
deg. C, sec
Notes: 1. All voltages are specified relative to VDD = 0 V.
2. The following relation must be always hold
VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
3. Exceeding the absolute maximum ratings may cause permanent damage to the device. Functional
operation under these conditions is not implied.
4. Moisture resistance of flat packages can be reduced by the soldering process, so care should be taken to
avoid thermally stressing the package during board assembly.
Electrical Specifications
DC Characteristics
Ta = –20 to 75 deg. C, VDD = 0 V unless stated otherwise
Parameter
Symbol
Operating Recommended
voltage (1)
See note 1. Allowable
VSS
Recommended
Operating Allowable
voltage (2) Allowable
Allowable
High-level input voltage
Low-level input voltage
High-level output voltage
V5
V1, V2
V3, V4
VIHT
VIHC
VIHT
VIHC
VILT
VILC
VILT
VILC
VOHT
VOHC1
VOHC2
VOHT
VOHC1
VOHC2
Condition
Min.
Rating
Typ.
Max.
–5.5
–5.0
–4.5
–7.0
—
–2.4
—
—
—
—
—
—
—
—
–3.5
—
VDD
0.4×V5
VDD
VDD
VDD
VDD
VSS+0.8
0.8×VSS
0.85×VSS
0.8×VSS
—
—
—
Unit
V
–13.0
–13.0
0.6×V5
V5
VSS+2.0
0.2×VSS
VSS = –3 V
0.2×VSS
VSS = –3 V
0.2×VSS
VSS
VSS
VSS = –3 V
VSS
VSS = –3 V
VSS
IOH = –3.0 mA
VSS+2.4
IOH = –2.0 mA
VSS+2.4
IOH = –120 µA
0.2×VSS
VSS = –3 V
IOH = –2 mA 0.2×VSS
VSS = –3 V
IOH = –2 mA 0.2×VSS
VSS = –3 V
IOH = –50 µA 0.2×VSS
—
—
—
V
V
V
Applicable Pin
VSS
V5
See note 10.
V1, V2
V3, V4
See note 2 & 3.
See note 2 & 3.
V
See note 2 & 3.
See note 2 & 3.
V
OSC2
See note 4 & 5.
V
See note 4 & 5.
OSC2
(continued)
2–20
EPSON
SED1520 Series
DC Characteristics (Cont’d)
Ta = –20 to 75 deg. C, VDD = 0 V unless stated otherwise
Low-level output voltage
Input leakage current
Output leakage current
Symbol
VOLT
VOLC1
VOLC2
VOLT
VOLC1
VOLC2
ILI
ILO
Condition
IOL = 3.0 mA
IOL = 2.0 mA
IOL = 120 µA
VSS = –3 V
VSS = –3 V
VSS = –3 V
IOL = 2 mA
IOL = 2 mA
IOL = 50 µA
–1.0
–3.0
V5 = –5.0 V
LCD driver ON resistance
RON
IDDQ
CS = CL = VDD
fCL = 2 kHz
During display
Rf = 1 MΩ
V5 = –5.0 V
fCL = 18 kHz
IDD (1)
Dynamic current dissipation
IDD (2)
Input pin capacitance
CIN
Oscillation frequency
fOSC
Reset time
Notes: 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
—
Rating
Typ.
Max.
—
VSS+0.4
—
VSS+0.4
—
0.8×VSS
0.8×VSS
0.8×VSS
0.8×VSS
—
1.0
—
3.0
5.0
—
10.0
50.0
—
—
—
—
0.05
2.0
9.5
5.0
1.0
5.0
15.0
10.0
1.5
4.5
During display fCL = 2 kHz
V5 = –5 V
Rf = 1 MΩ
VSS = –3 V
During access tcyc = 200 kHz
VSS = –3V,
During access tcyc = 200 kHz
Ta = 25 deg. C, f = 1 MHz
Rf = 1.0 MΩ ±2%,
VSS = –5.0 V
Rf = 1.0 MΩ ±2%,
VSS = –3.0 V
6.0
12.0
300
500
150
300
—
5.0
8.0
15
18
21
11
16
21
—
Unit
Applicable Pin
V
OSC2
See note 4 & 5.
V
See note 4 & 5.
OSC2
µA
µA
See note 6.
See note 7.
kΩ
SEG0 to 79,
COM0 to 15,
See note 11
7.5
Ta = 25 deg. C
V5 = –3.5 V
Static current dissipation
Min.
—
—
—
µA
µA
VDD
VDD
See note 12,
13 & 14.
µA
VDD
See note 12 & 13.
µA
See note 8.
pF
All input pins
kHz
See note 9.
RES
See note 15.
Operation over the specified voltage range is guaranteed, except where the supply voltage changes
suddenly during CPU access.
A0, D0 to D7, E (or RD), R/W (or WR) and CS
CL, FR, M/S and RES
D0 to D7
FR
A0, E (or RD), R/W (or WR), CS, CL, M/S and RES
When D0 to D7 and FR are high impedance.
During continual write acess at a frequency of tcyc. Current consumption during access is effectively
proportional to the access frequency.
See figure below for details
See figure below for details
For a voltage differential of 0.1 V between input (V1, …, V4) and output (COM, SEG) pins. All voltages
within specified operating voltage range.
SED1520*A* and SED1521*A* and SED1522*A* only. Does not include transient currents due to
stray and panel capacitances.
SED1520*0* and SED1522*0* only. Does not include transient currents due to stray and panel
capacitances.
SED1521*0* only. Does not include transient currents due to stray and panel capacitances.
tR (Reset time) represents the time from the RES signal edge to the completion of reset of the internal
circuit. Therefore, the SED1520 series enters the normal operation status after this tR.
tR
1.0
EPSON
—
µS
2–21
SED1520
Series
Parameter
SED1520 Series
Relationship between fOSC, fFR and Rf, and operating bounds on VSS and V5
*9
• Relationship between oscillation frequency, frames and Rf
(SED1520F0A), (SED1522F0A)
OSC1
Rf
OSC2
Ta=25°C V SS =-5V
Ta=25°C VSS =-5V
[Hz]
200
30
VSS =-5V
SED1522
20
Frame
fosc
[kHz]
40
Same for 1/16 and 1/32 duties
VSS =-3V
100
SED1520
10
0
0.5
1.0
1.5
2.0
0
2.5
0.5
[M Ω]
Rf
1.0
Rf
Figure 5 (a)
1.5
2.0
2.5
[M Ω]
Figure 5 (b)
• Relationship between external clocks (fCL) and frames
(SED1520FAA) , (SED1522FAA)
duty1/32
duty1/16
200
[Hz]
duty1/8
Frame
100
0
1
2
f CL
[kHz]
3
Figure 5 (c)
*10 • Operating voltage range of VSS and V5 systems
(V)
–15
–10
V5
Operating voltage
range
–5
0
–2
–4
VSS
Figure 6
2–22
EPSON
–6
(V)
–8
SED1520 Series
AC Characteristics
• MPU Bus Read/Write I (80-family MPU)
t AW8
t CC
SED1520
Series
A0,CS
t AH8
WR,RD
tr
t CYC8
tf
t DH8
t DS8
D0 to D7
(WRITE)
t OH8
t ACC8
D0 to D7
(READ)
Ta = –20 to 75 deg. C, VSS = –5.0 V ±10% unless stated otherwise
Parameter
Address hold time
Address setup time
System cycle time
Control pulsewidth
Data setup time
Data hold time
RD access time
Output disable time
Rise and fall time
Symbol
tAH8
tAW8
tCYC8
tCC
tDS8
tDH8
tACC8
tCH8
tr, tf
Condition
CL = 100 pF
—
Rating
Min.
Max.
10
—
20
—
1000
—
200
—
80
—
10
—
—
90
10
60
—
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Signal
A0, CS
WR, RD
D0 to D7
—
(VSS = –2.7 to –4.5 V, Ta = –20 to +75°C)
Parameter
Address hold time
Address setup time
System cycle time
Control pulse width
Data setup time
Data hold time
RD access time
Output disable time
Rise and fall time
Symbol
tAH8
tAW8
tCYC8
tCC
tDS8
tDH8
tACC8
tCH8
tr, tf
Condition
—
—
—
CL = 100 pF
—
EPSON
Rating
Min.
Max.
20
—
40
—
2000
—
400
—
160
—
20
—
—
180
20
120
—
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Signal
A0, CS
WR, RD
D0 to D7
—
2–23
SED1520 Series
• MPU Bus Read/Write II (68-family MPU)
t CYC6
E
t EW
tr
tf
t AW6
t DS6
R/W
t AH6
A0,CS
t DH6
D0 to D7
(WRITE)
t ACC6
t OH6
D0 to D7
(READ)
Ta = –20 to 75 deg. C, VSS = –5 V ±10 unless stated otherwise
Parameter
System cycle time
Address setup time
Address hold time
Data setup time
Data hold time
Output disable time
Access time
Enable
Read
pulsewidth
Write
Rise and fall time
Symbol
tCYC6
tAW6
tAH6
tDS6
tDH6
tOH6
tACC6
Condition
CL = 100 pF
tEW
tr, tf
—
Rating
Min.
Max.
1000
—
20
—
10
—
80
—
10
—
10
60
—
90
100
—
80
—
—
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Signal
A0, CS, R/W
D0 to D7
E
—
(VSS = –2.7 to – 4.5 V, Ta = –20 to +75°C)
Parameter
System cycle time*1
Address setup time
Address hold time
Data setup time
Data hold time
Output disable time
Access time
Enable
Read
pulse width
Write
Rise and fall time
Symbol
Condition
tCYC6
tAW6
tAH6
tDS6
tDH6
tOH6
tACC6
—
—
—
CL = 100 pF
tEW
—
tr, tf
—
Rating
Min.
Max.
2000
—
40
—
20
—
160
—
20
—
20
120
—
180
200
—
160
—
—
15
Notes: 1. tCYC6 is the cycle time of CS. E = H, not the cycle time of E.
2–24
EPSON
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Signal
A0, CS, R/W
D0 to D7
E
—
SED1520 Series
• Display Control Signal Timing
tf
tr
CL
t WLCL
SED1520
Series
t WHCL
t DFR
FR
Input
Ta = –20 to 75 deg. C, VSS = –5.0 V ±10% unless stated otherwise
Parameter
Symbol
Low-level pulsewidth
High-level pulsewidth
Rise time
Fall time
FR delay time
tWLCL
tWHCL
tr
tf
tDFR
Condition
Min.
35
35
—
—
–2.0
Rating
Typ.
—
—
30
30
0.2
Max.
—
—
150
150
2.0
Min.
70
70
—
—
–4.0
Rating
Typ.
—
—
60
60
0.4
Max.
—
—
300
300
4.0
Unit
Signal
µs
µs
ns
ns
µs
FR
Unit
Signal
CL
VSS = –2.7 to –4.5 V, Ta = –20 to +75°C
Parameter
Symbol
Condition
Low-level pulse width
High-level pulse width
Rise time
Fall time
FR delay time
tWLCL
tWHCL
tr
tf
tDFR
—
—
—
—
—
µs
µs
ns
ns
µs
CL
FR
Note: The listed input tDFR applies to the SED1520 and SED1521 and SED1522 in slave mode.
Output
Ta = –20 to 75 deg. C, VSS = –5.0 V ±10% unless stated otherwise
Parameter
FR delay time
Symbol
Condition
tDFR
CL = 100 pF
Min.
—
Rating
Typ.
0.2
Max.
0.4
Min.
—
Rating
Typ.
0.4
Max.
0.8
Unit
Signal
µs
FR
Unit
Signal
µs
FR
VSS = –2.7 to –4.5 V, Ta = –20 to +75°C
Parameter
FR delay time
Symbol
Condition
tDFR
CL = 100 pF
Notes: 1. The listed output tDFR applies to the SED1520 and SED1522 in master mode.
EPSON
2–25
SED1520 Series
APPLICATION NOTES
MPU Interface Configuration
80 Family MPU
VCC
A1 to A7
IOQR
MPU
A0
A0
Decoder
RD
RD
WR
WR
RES
VSS
RES
RESET
2–26
CS
SED1520FAA
D0 to D7
D0 to D7
GND
VDD
EPSON
V5
SED1520 Series
LCD Drive Interface Configuration
To LCD SEG
To LCD COM
To LCD SEG
VDD
To LCD COM
SED1520F0A
SED1520F0A
Master
Slave
M/S
M/S
OSC1
OSC2
FR
OSC1
OSC2
FR
VSS
Rf
SED1520FAA–SED1520FAA
SED1522FAA–SED1522FAA
To LCD SEG
To LCD COM
To LCD SEG
SED1520FAA
VDD
To LCD COM
SED1520FAA
Master
Slave
M/S
M/S
CL
FR
CL
FR
VSS
External clock
SED1520F0A
)–SED1521F0A (See note 1)
SED1522F0A
To LCD SEG
To LCD SEG
SED1520F0A
SED1521F0A
Master
Slave
To LCD COM
VDD
M/S
OSC1
OSC2
FR
OSC1
OSC2
FR
Rf
*2
EPSON
2–27
SED1520
Series
SED1520F0A–SED1520F0A
SED1522F0A–SED1522F0A
SED1520 Series
SED1520FAA–SED1521FAA
To LCD SEG
To LCD COM
To LCD SEG
SED1520FAA
SED1521FAA
VDD
M/S
CL
FR
External clock
Notes: 1. The duty cycle of the slave must be the same as that for the master.
2. If a system has two or more slave drivers a CMOS buffer will be required.
2–28
EPSON
CL
FR
SED1520 Series
×8 dots.)
LCD Panel Wiring Example (The full-dot LCD panel displays a character in 6×
1/16 duty:
• 10 characters × 2 lines
SED1520
Series
1
LCD 16×61
16
1
61
SEG
SED1520F
COM
1/16 duty:
• 23 characters × 2 lines
1
LCD 16×141
16
1
COM
61
62
141
SEG
SEG
SED1520F
SED1521F
1/32 duty:
• 33 characters × 4 lines
1
LCD 32×202
16
1
COM
61
62
141
17
142
202 32
SEG
SEG
SEG
SED1520F
SED1521F
*
SED1520F
COM
* The SED1521F can be omitted (the 32×122-dot display mode is selected).
Note: A combination of AB or AA type chip (that uses internal clocks) and 0B or 0A type chip (that uses external
clocks) is NOT allowed.
EPSON
2–29
SED1520 Series
Package Dimensions
• Plastic QFP5–100 pin
Dimensions: inches (mm)
1.008 ± 0.016
(25.6 ± 0.4)
0.787 ± 0.004 (20 ± 0.1)
80
51
81
Index
31
0.106 ± 0.004
(2.7 ± 0.1)
0.006 ± 0.002
(0.15 ± 0.05)
100
0.772 ± 0.016 (19.6 ± 0.4)
0.551 ± 0.004
(14 ± 0.1)
50
0.026 ± 0.004
(0.65 ± 0.1)
1
30
0.012 ± 0.004
(0.30 ± 0.1)
0~12°
0.110
(2.8)
0.059 ± 0
.012
(1.5 ± 0.3
)
• Plastic QFP15–100 pin
0.630 ± 0.016 (16.0 ± 0.4)
0.551 ± 0.004 (14.0 ± 0.1)
75
51
Index
0.005 ± 0.002
(0.127 ± 0.05)
0.055 ± 0.004
(1.4 ± 0.1)
100
0.630 ± 0.016 (16.0 ± 0.4)
50
0.551 ± 0.004 (14.0 ± 0.1)
76
26
1
25
0.020 ± 0.004
(0.5 ± 0.1)
0.007 ± 0.004
(0.18 ± 0.1)
0~12°
0.020 ± 0.004 (0.5 ± 0.2)
0.039(1.0)
2–30
EPSON
Punching
hole for
good
product
(Mold, marking area)
EPSON
SED1520
Series
Specifications
• Base: U-rexS, 75µm
• Copper foil: Electrolytic copper foil, 35µm
• Sn plating
• Product pitch: 81P (28.5mm)
• Solder resist positional tolerance: ±0.3
Output terminal pattern shape
SED1520 Series
2–31
(Mold, marking area)
Download PDF