DM74164 8-Bit Serial In/Parallel Out Shift Registers September 1986 Revised July 2001 DM74164 8-Bit Serial In/Parallel Out Shift Registers General Description Features These 8-bit shift registers feature gated serial inputs and an asynchronous clear. A LOW logic level at either serial input inhibits entry of the new data, and resets the first flipflop to the LOW level at the next clock pulse, thus providing complete control over incoming data. A HIGH logic level on either input enables the other input, which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements will be entered. Clocking occurs on the LOW-to-HIGH level transition of the clock input. All inputs are diode-clamped to minimize transmission-line effects. ■ Gated (enable/disable) serial inputs ■ Fully buffered clock and serial inputs ■ Asynchronous clear ■ Typical clock frequency 36 MHz ■ Typical power dissipation 185 mW Ordering Code: Order Number DM74164 Package Number N14A Package Description 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Connection Diagram Function Table Inputs Outputs Clear Clock A B QA QB … L X X X L L … L H L X X QA0 QB0 … QH0 H ↑ H H H QAn … QGn H ↑ L X L QAn … QGn H ↑ X L L QAn … QGn QH H = HIGH Level (steady state) L = LOW Level (steady state) X = Don’t Care (any input, including transitions) ↑ = Transition from LOW-to-HIGH level QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. QAn, QGn = The level of QA or QG before the most recent ↑ transition of the clock; indicates a one-bit shift. © 2001 Fairchild Semiconductor Corporation DS006552 www.fairchildsemi.com DM74164 Logic Diagram Timing Diagram www.fairchildsemi.com 2 Supply Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 5.5V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA V 2 IOL LOW Level Output Current fCLK Clock Frequency (Note 2) tW Pulse Width Clock 20 (Note 2) Clear 20 V 0 8 mA 25 MHz ns tSU Data Setup Time (Note 2) 15 ns tH Data Hold Time (Note 2) 5 ns TA Free Air Operating Temperature 0 °C 70 Note 2: TA = 25°C and VCC = 5V. Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −14 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min LOW Level VCC = Min, IOL = Max Output Voltage VIH = Min, VIL = Max VOL Typ Min (Note 3) 2.4 Max Units −1.5 V 3.2 V 0.2 0.4 V mA II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V 1 IIH HIGH Level Input Current VCC = Max, VI = 2.4V 40 µA IIL LOW Level Input Current VCC = Max, VI = 0.4V −1.6 mA IOS Short Circuit Output Current VCC = Max (Note 4) −27.5 mA ICC Supply Current VCC = Max (Note 5) 54 mA −9 37 Note 3: All typicals are at VCC = 5V, TA = 25°C. Note 4: Not more than one output should be shorted at a time. Note 5: ICC is measured with all outputs OPEN, SERIAL inputs grounded, the CLOCK input at 2.4V, and a momentary ground, then 4.5V, applied to the CLEAR input. Switching Characteristics at VCC = 5V and TA = 25°C RL = 800Ω Symbol Parameter To (Output) fMAX Maximum Clock Frequency tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output CL = 15 pF From (Input) Min CL = 50 pF Max Min Units Max 25 MHz Clock to Output 27 30 ns Clock to Output 32 37 ns Clear to Output 36 42 ns 3 www.fairchildsemi.com DM74164 Absolute Maximum Ratings(Note 1) DM74164 8-Bit Serial In/Parallel Out Shift Registers Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 4 This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.
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