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DRV201A
SLVSBN6A – JUNE 2013 – REVISED AUGUST 2015
DRV201A Voice Coil Motor Driver for Camera Auto Focus
1 Features
1
• Configurable for Linear or PWM Mode VCM
Current Generation
• High Efficiency PWM Current Control for VCM
• Advanced Ringing Compensation
• Integrated 10-bit D/A Converter for VCM Current
Control
• Protection
– Open and Short-Circuit Detection
– Undervoltage Lockout (UVLO)
– Thermal Shutdown
– Internal Current Limit for VCM Driver
– 4-kV ESD-HBM
• I
2
C Interface
• Improved PWM-to-Linear Mode Setting Time vs.
DRV201
• Improved EMC Performance vs. DRV201
• Improved PWM-to-Linear Mode Settling Time vs.
DRV201
• Improved EMC Performance vs. DRV201
• Operating Temperature Range: -40ºC to 85ºC
• 6-Ball WCSP Package With 0.4-mm Pitch
• Max Die Size: 0.806 mm × 1.49 mm
• Max Package Height: 0.3 mm
2 Applications
• Cell Phone Auto Focus
• Digital Still Camera Auto Focus
• Iris and Exposure Controls
• Security Cameras
• Web and PC Cameras
• Actuator Controls
3 Description
The DRV201A is an advanced voice coil motor driver for camera auto focus. It has an integrated D/A converter for setting the VCM current. VCM current is controlled with a fixed frequency PWM controller or a linear mode driver. Current generation can be selected via I
2
C register. The DRV201A has an integrated sense resistor for current regulation and the current can be controlled through I
2
C.
When changing the current in the VCM, the lens ringing is compensated with an advanced ringing compensation function.
Ringing compensation reduces the needed time for auto focus significantly.
The device also has VCM short and open protection functions.
PART NUMBER
PACKAGE BODY SIZE (NOM)
DRV201A PicoStar (6) 0.80 mm × 1.48 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
Simplified Schematic
2.5 V to 4.8 V
DRV201A
I
SOURCE
SCL
SDA
Voice Coil
Motor Driver
I
SINK
+
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV201A
SLVSBN6A – JUNE 2013 – REVISED AUGUST 2015 www.ti.com
1 Features ..................................................................
2 Applications ...........................................................
3 Description .............................................................
4 Revision History.....................................................
5 Pin Configuration and Functions .........................
6 Specifications.........................................................
6.1
Absolute Maximum Ratings ......................................
6.2
ESD Ratings..............................................................
6.3
Recommended Operating Conditions .......................
6.4
Thermal Information ..................................................
6.5
Electrical Characteristics...........................................
6.6
Data Transmission Timing Requirements.................
6.7
Typical Characteristics ..............................................
7 Detailed Description ..............................................
7.1
Overview ...................................................................
7.2
Functional Block Diagram .......................................
7.3
Feature Description.................................................
Table of Contents
7.4
Device Functional Modes........................................
7.5
Programming...........................................................
7.6
Register Maps .........................................................
8 Application and Implementation ........................
8.1
Application Information............................................
8.2
Typical Application .................................................
9 Power Supply Recommendations ......................
10 Layout...................................................................
10.1
Layout Guidelines .................................................
10.2
Layout Example ....................................................
11 Device and Documentation Support .................
11.1
Device Support......................................................
11.2
Community Resources..........................................
11.3
Trademarks ...........................................................
11.4
Electrostatic Discharge Caution ............................
11.5
Glossary ................................................................
12 Mechanical, Packaging, and Orderable
Information ...........................................................
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (June 2013) to Revision A Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................
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5 Pin Configuration and Functions
YMB Package
6-Pin PicoStar
Bottom View
SCL
I
SOURCE
VBAT
SDA
I
SINK
GND
2
1
DRV201A
SLVSBN6A – JUNE 2013 – REVISED AUGUST 2015
YMB Package
6-Pin PicoStar
Top View
201A
YMDS
YMB Package
6-Pin PicoStar
Top View
201AB
YMDS
NAME
VBAT
GND
I_SOURCE
I_SINK
SCL
SDA
The coated package option has a backside polymer coating that is 40µm thick. The final package heights of both the packages are the same for both options. This coating helps minimize edge chipping or die cracking during assembly and manufacturing.
PIN
NO.
2A
1A
2B
1B
2C
1C
I/O
—
—
—
—
I
I/O
Pin Functions
DESCRIPTION
Power
Ground
Voice coil positive terminal
Voice coil negative terminal
I
2
C serial interface clock input
I
2
C serial interface data input/output (open drain)
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SLVSBN6A – JUNE 2013 – REVISED AUGUST 2015
6 Specifications
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6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
R
θJA
T
J
T
A
T stg
VBAT, ISOURCE, ISOURCE pin voltage
Voltage at SDA, SCL
Continuous total power dissipation
Junction-to-ambient thermal resistance
(3)
Operating junction temperature
Operating ambient temperature
Storage temperature
(2)
MIN
–0.3
–40
–40
–55
MAX
5.5
–0.3
3.6
Internally limited
130
125
85
150
UNIT
V
V
°C/W
°C
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) This thermal data is measured with high-K board (4-layer board).
6.2 ESD Ratings
V
(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
(1)
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins
(2)
VALUE
±4000
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VBAT - Supply voltage
Voltage Range - SDA and SCL
T
J
- Operating junction temperature
MIN
2.5
–0.1
–40
NOM
3.7
3.3
MAX
4.8
3.6
125
UNIT
V
UNIT
V
V
°C
6.4 Thermal Information
R
θJA
R
θJC(top)
R
θJB
ψ
JT
ψ
JB
THERMAL METRIC
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
(1)
Junction-to-board characterization parameter
DRV201A
YMB (PICOSTAR)
6 PINS
16.9
1.4
22.2
0.1
22.2
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953 .
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DRV201A
SLVSBN6A – JUNE 2013 – REVISED AUGUST 2015
6.5 Electrical Characteristics
Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature range of 25°C) (unless otherwise noted)
MIN TYP MAX UNIT
INPUT VOLTAGE
PARAMETER
V
BAT
Input supply voltage
TEST CONDITIONS
V
UVLO
Undervoltage lockout threshold
V
BAT rising
V
BAT falling
V
HYS
Undervoltage lockout hysteresis
INPUT CURRENT
I
I
SHUTDOWN
STANDBY
Input supply current shutdown, includes switch leakage currents
Input supply current standby, includes switch leakage currents
MAX: V
MAX: V
STARTUP, MODE TRANSITIONS, AND SHUTDOWN
BAT
BAT
= 4.4 V
= 4.4 V
I t
1 t
2
Shutdown to standby
Standby to active t
3 t
4
Active to standby
Shutdown time
VCM DRIVER STAGE
RES
Resolution
Relative accuracy
Differential nonlinearity
Zero code error
Offset error
Active or standby to shutdown
At code 32
Gain error
See
(1)
2.5
2
50
0.5
-10
-1
110
3.7
100
0.15
120
10
0
±3
0.3
0.3
102.3
160
4.8
2.2
V
V
250 mV
1 µA
200 µA
100 µs
100 µs
100 µs
1 ms bits
10
1
LSB mA
3 mA
% of
FSR
0.4
%/°C
0.5
%/°C mA
240 mA
I
MAX
I
LIMIT
Maximum output current
Average VCM current limit
I
DETCODE t set1 t set2
Minimum VCM code for OPEN and
SHORT detection f
SW
Switching frequency
V
DRP
L
VCM
Internal dropout
VCM inductance
R
VCM
VCM resistance
LENS MOVEMENT CONTROL
Lens settling time
Lens settling time
VCM resonance frequency f
VCM
Gain error drift
Offset error drift
VCM resonance frequency tolerance
See
(2)
Selectable through CONTROL register
See
(3)
±10% error band
±10% error band
When 1/f
VCM compensation is used
When 2/f
VCM compensation is used
256
0.5
30
11
50
-10%
-30%
2/f
VCM
1/f
VCM mA
4 MHz
0.4
V
150 µH
22 Ω ms ms
150 Hz
10%
30%
(1) During short circuit condition driver current limit comparator will trip and short is detected and driver goes into STANDBY and short flag is set high in the status register.
(2) When testing VCM open or short this is the recommended minimum VCM code (in dec) to be used.
(3) This is the voltage that is needed for the feedback resistor and high side driver. It should be noted that the maximum VCM resistance is limited by this voltage and supply voltage. E.g. 3-V supply maximum VCM resistance is: R
VCM
V)/102.3 mA = 25.4
Ω.
= (V
BAT
– V
DRP
)/I
VCM
= (3 V - 0.4
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SLVSBN6A – JUNE 2013 – REVISED AUGUST 2015 www.ti.com
Electrical Characteristics (continued)
Over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature range of 25°C) (unless otherwise noted)
PARAMETER
LOGIC I/Os (SDA AND SCL)
TEST CONDITIONS MIN TYP MAX UNIT
I
IN
Input leakage current
R
PullUp
V
IH
V
IL t
TIMEOUT
R
PD f
SCL
I
I
2
C pull-up resistors
Input high level
Input low level
SCL timeout for shutdown detection
Pull down resistor at SCL line
2
C clock frequency f
INTERNAL OSCILLATOR
OSC
Internal oscillator
Frequency accuracy
THERMAL SHUTDOWN
T
TRIP
Thermal shutdown trip point
V = 1.8 V, SCL
V = 1.8 V, SDA
SDA and SCL pins
See
(4)
See
(5)
20°C ≤ T
A
≤ 70°C
-40°C ≤ T
A
≤ 85°C
-4.25
-1
1.17
0
0.5
-3%
-5%
4.7
500
140
4.25
1
µA
3.6
0.63
k Ω
V
V
1 ms k Ω
400 kHz
3%
5%
°C
(4) During shutdown to standby transition V
IH
(5) During shutdown to standby transition V
IL low limit is 1.28 V.
high limit is 0.51 V.
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6.6 Data Transmission Timing Requirements
V
BAT
= 3.6 V ±5%, T
A
= 25ºC, C
L
= 100 pF (unless otherwise noted) f t t t t t t t t t
(SCL)
BUF
SP
LOW
HIGH t
S(DAT)
S(STA) t
S(STO) t
H(DAT) t
H(STA) r(SCL) f(SCL) r(SDA) f(SDA)
Serial clock frequency
Bus Free Time Between Stop and Start Condition
Tolerable spike width on bus
SCL low time
SCL high time
SDA
SDA
→ SCL setup time
Start condition setup time
Stop condition setup time
→ SCL hold time
Start condition hold time
Rise time of SCL Signal
Fall time of SCL Signal
Rise time of SDA Signal
Rise time of SDA Signal
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
SCL = 100 KHz
SCL = 400 KHz
DRV201A
SLVSBN6A – JUNE 2013 – REVISED AUGUST 2015
4.7
600
4
600
0
4.7
1.3
4
600
250
100
0
4
600
MIN
100
4.7
1.3
NOM MAX UNIT
400 kHz
µs
50 ns
3.45
0.9
1000
300
300
300
1000
300
300
300 ns ns ns
µs ns
µs ns
µs
µs ns ns
µs
µs ns ns
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DRV201A
SLVSBN6A – JUNE 2013 – REVISED AUGUST 2015
6.7 Typical Characteristics
120
100
80
60
40
20
0
0
VBAT = 3.7 V
20 40
I
OUT
(mA)
60 80 100
C001
Figure 1. Linear Mode: Supply Current vs Output Current
80%
70%
60%
50%
40%
30%
20%
10%
0%
0 20 40
I
OUT
(mA)
60
1 Mhz
4 Mhz
80
2 Mhz
6 Mhz
100
C003
VBAT = 3.7 V
Figure 3. PWM Mode: Efficiency vs Output Current www.ti.com
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
0%
0
VBAT = 3.7 V
20 40
I
OUT
(mA)
60 80 100
C002
Figure 2. Linear Mode: Efficiency vs Output Current
100
90
80
1MHz
4MHz
2MHz
6MHz
70
60
50
40
30
20
10
0
0 20 40
I
OUT
(mA)
60 80 100
C004
VBAT = 3.7 V
Figure 4. PWM Mode: Supply Current vs Output Current
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7 Detailed Description
DRV201A
SLVSBN6A – JUNE 2013 – REVISED AUGUST 2015
7.1 Overview
The DRV201A is intended for high performance autofocus in camera modules. It is used to control the current in the voice coil motor (VCM). The current in the VCM generates a magnetic field which forces the lens stack connected to a spring to move. The VCM current and thus the lens position can be controlled via the I
2
C interface and an auto focus function can be implemented.
The DRV201A offers a higher level of performance than the DRV201 in two areas. First, the transition between
PWM and linear modes is free of any resonance. This allows faster image capture after achieving focus in the
PWM mode. The other performance enhancement is in the area of EMC performance. When operating in PWM mode, transitions were significantly slowed down resulting in lower conducted and radiated noise versus the
DRV201.
The device connects to a video processor or image sensor through a standard I
2
C interface which supports up to
400-kbit/s data rate. The digital interface supports IO levels from 1.8 V to 3.3 V. All pins have 4-kV HBM ESD rating.
When SCL is low for at least 0.5 ms, the device enters SHUTDOWN mode. If SCL goes from low to high the driver enters STANDBY mode in less than 100 μs and default register values are set as shown in
.
ACTIVE mode is entered whenever the VCM_CURRENT register is set to something else than zero.
Vbat
ISC/SCL t 1 t 2 t 3 t 4
DAC mode SHUTDOWN
=0
STANDBY
0
ACTIVE
=0
STANDBY SHUTDOWN
Figure 5. Power Up and Down Sequence
VCM current can be controlled via an I
2
C interface and VCM_CURRENT registers. Lens stack is connected to a spring which causes a dampened ringing in the lens position when current is changed. This mechanical ringing is compensated internally by generating an optimized ramp whenever the current value in the VCM_CURRENT register is changed. This enables a fast autofocus algorithm and pleasant user experience.
Current in the VCM can be generated with a linear or PWM control. In linear mode the high side PMOS is configured as a current source and current is set by the VCM_CURRENT control register. In PWM control the
VCM is driven with a half bridge driver. With PWM control the VCM current is increased by connecting the VCM between V
BAT and GND through the high side PMOS and then released to a ‘freewheeling’ mode through the sense resistor and low side NMOS. PWM mode switching frequency can be selected from 0.5 MHz up to 4 MHz through a CONTROL register. PWM or linear mode can be selected with the PWM/LIN bit in the MODE register.
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DRV201A
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7.2 Functional Block Diagram
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Cin
VBAT
OSCILLATOR REFERENCE
POR
10-bit
DAC
ISOURCE
SCL
SDA
REGISTERS
DIGITAL
RINGING
COMPENSATION
I2C
R sense
ISINK
VCM
GND
7.3 Feature Description
7.3.1 VCM Driver Output Stage Operation
Current in the VCM can be controlled with a linear or PWM mode output stage. Output stage is enabled in
ACTIVE mode which can be controlled through VCM_CURRENT control register and the output stage mode is selected from MODE register bit PWM/LIN.
In linear mode the output PMOS is configured to a high side current source and current can be controlled from a
VCM_CURRENT registers.
In PWM control the VCM is driven with a half bridge driver. With PWM control the VCM current is increased by connecting the VCM between V
BAT and GND through the high side PMOS and then released to a ‘freewheeling’ mode through the sense resistor and low side NMOS. Current in the VCM is sensed with a 1Ω sense resistor which is connected into an error amplifier input where the other input is controlled by the 10-bit DAC output.
PWM mode switching frequency can be selected from 0.5 MHz up to 4 MHz through a CONTROL register. PWM or linear mode can be selected with the PWM/LIN bit in the MODE register.
7.3.2 Ringing Compensation
VCM current can be controlled via an I
2
C interface and VCM_CURRENT registers. Lens stack is connected to a spring which causes a dampened ringing in the lens position when current is changed. This mechanical ringing is compensated internally by generating an optimized ramp whenever the current value in the VCM_CURRENT register is changed. This enables a fast auto focus algorithm and pleasant user experience.
Ringing compensation is dependent on the VCM resonance frequency and this can be controlled via
VCM_FREQ register (07h) from 50 Hz up 150 Hz.
shows the VCM_FREQ register setting for each resonance frequency in 1-Hz steps. If more accurate resonance frequency is available, the control value can be calculated with
.
Ringing compensation is designed in a way that it can tolerate ±30% frequency variation in the VCM resonance frequency when 2/f
VCM compensation is used and ±10% variation with 1/f
VCM is needed in production.
VCM so only statistical data from the
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DRV201A
SLVSBN6A – JUNE 2013 – REVISED AUGUST 2015
72
73
74
75
69
70
71
66
67
68
62
63
64
65
79
80
81
76
77
78
82
83
VCM
Resonance
Frequency
[Hz]
50
51
52
53
54
55
59
60
61
56
57
58
Feature Description (continued)
Table 1. VCM Resonance Frequency Control Register (07h) Table
VCM_FREQ[7:0] (07h) VCM_FREQ[7:0] (07h)
DEC
105
109
113
116
120
124
127
73
78
83
88
92
96
101
130
134
137
140
143
146
149
152
58
63
68
40
46
52
0
7
14
21
27
34
BIN
1001001
1001110
1010011
1011000
1011100
1100000
1100101
1101001
1101101
1110001
1110100
1111000
1111100
1111111
0
111
1110
10101
11011
100010
101000
101110
110100
111010
111111
1000100
10000010
10000110
10001001
10001100
10001111
10010010
10010101
10011000
103
104
105
106
107
108
109
96
97
98
99
100
101
102
110
111
112
113
114
115
116
117
VCM
Resonance
Frequency
[Hz]
84
85
86
87
88
89
93
94
95
90
91
92
DEC
10110111
10111001
10111011
10111101
10111111
11000001
11000011
11000101
11000110
11001000
11001010
11001100
11001101
11001111
10011010
10011101
10100000
10100010
10100101
10100111
10101010
10101100
10101110
10110001
10110011
10110101
11010000
11010010
11010100
11010101
11010111
11011000
11011001
11011011
197
198
200
202
204
205
207
183
185
187
189
191
193
195
208
210
212
213
215
216
217
219
170
172
174
177
179
181
154
157
160
162
165
167
BIN
137
138
139
140
141
142
143
130
131
132
133
134
135
136
144
145
146
147
148
149
150
-
VCM
Resonance
Frequency
[Hz]
118
119
120
121
122
123
124
125
126
127
128
129
VCM_FREQ[7:0] (07h)
DEC BIN
243
244
245
246
247
248
249
235
236
238
239
240
241
242
250
251
251
252
253
254
255
-
228
229
231
232
233
234
220
222
223
224
226
227
11101011
11101100
11101110
11101111
11110000
11110001
11110010
11110011
11110100
11110101
11110110
11110111
11111000
11111001
11011100
11011110
11011111
11100000
11100010
11100011
11100100
11100101
11100111
11101000
11101001
11101010
11111010
11111011
11111011
11111100
11111101
11111110
11111111
-
7.4 Device Functional Modes
7.4.1 Modes of Operation
SHUTDOWN If the driver detects SCL has a DC level below 0.63 V for duration of at least 0.5 ms, the driver will enter shutdown mode. This is the lowest power mode of operation. The driver will remain in shutdown for as long as SCL pin remain low.
STANDBY If SCL goes from low to high the driver enters STANDBY mode and sets the default register values.
In this mode registers can be written to through the I
2
C interface. Device will be in STANDBY mode when VCM_CURRENT register is set to zero. From ACTIVE mode the device will enter STANDBY if the SW_RST bit of the CONTROL register is set. In this case all registers will be reset to default values.
STANDBY mode is entered from ACTIVE mode if any of the following faults occur: Over temperature protection fault (OTPF), VCM short (VCMS), or VCM open (VCMO). When
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Device Functional Modes (continued)
ACTIVE
STANDBY mode is entered due to a fault condition current register is cleared.
The device is in ACTIVE mode whenever the VCM_CURRENT control is set to something else than zero through the I
2
C interface. In ACTIVE mode VCM driver output stage is enabled all the time resulting in higher power consumption. The device remains in active mode until the SW_RST bit in the CONTROL register is set, SCL is pulled low for duration of 0.5 ms, VCM_CURRENT control is set to zero, or any of the following faults occur: Over temperature protection fault (OTPF),
VCM short (VCMS), or VCM open (VCMO). If active mode is entered after fault the status register is automatically cleared.
7.5 Programming
7.5.1 I
2
C Bus Operation
The I
2
C bus is a communications link between a controller and a series of slave terminals. The link is established using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is sourced from the controller in all cases where the serial data line is bi-directional for data communication between the controller and the slave terminals. Each device has an open drain output to transmit data on the serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high during data transmission.
The DRV201A hosts a slave I 2 C interface that supports data rates up to 400 kbit/s and auto-increment addressing and is compliant to I
2
C standard 3.0.
DRV201A supports four different read and two different write operations; single read from a defined location, single read from a current location, sequential read starting from a defined location, sequential read from current location, single write to a defined location, sequential write starting from a defined location. All different read and write operations are described below.
7.5.1.1 Single Write to a Defined Location
shows the format of a single write to a defined register. First, the master issues a start condition followed by a seven-bit I2C address. Next, the master writes a zero to conduct a write operation. Upon receiving an acknowledge from the slave, the master writes the eight-bit register number across the bus. Following a second acknowledge, DRV201A sets the I 2 C register to a defined value and the master writes the eight-bit data value across the bus. Upon receiving a third acknowledge, DRV201A auto increments the internal I
2
C register number by one and the master issues a stop condition. This action concludes the register write.
CURRENT REGISTER NUMBER K REGISTER NUMBER M M+1
DRV201A ADDRESS
0 0 0 1 1 1 0
0
REGISTER NUMBER
M
SINGLE WRITE TO A DEFINED LOCATION
Figure 6. Single Write
DATA
7.5.1.2 Single Read from a Defined Location and Current Location
shows the format of a single read from a defined location. First, the master issues a start condition followed by a seven-bit I 2 C address. Next, the master writes a zero to conduct a write operation. Upon receiving an acknowledge from the slave, the master writes the eight-bit register number across the bus. Following a second acknowledge, DRV201A sets the internal I 2 C register number to a defined value. Then the master issues a repeat start condition and a seven-bit I
2
C address followed by a one to conduct a read operation. Upon receiving a third acknowledge, the master releases the bus to the DRV201A. The DRV201A then writes the eight-bit data value from the register across the bus. The master acknowledges receiving this byte and issues a stop condition. This action concludes the register read.
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Programming (continued)
CURRENT REGISTER NUMBER K
DRV201A
SLVSBN6A – JUNE 2013 – REVISED AUGUST 2015
REGISTER NUMBER M M+1
DRV201A ADDRESS
0 0 0 1 1 1 0
0
REGISTER NUMBER
M
DRV201A ADDRESS
0 0 0 1 1 1 0
1
Figure 7. Single Read From A Defined Location
DATA
shows the single read from the current location. If the read command is issued without defining the register number first, DRV201A writes out the data from the current register from the device memory.
CURRENT REGISTER NUMBER K REGISTER NUMBER K+1 K+2
DRV201A ADDRESS
0 0 0 1 1 1 0
1 DATA DRV201A ADDRESS
0 0 0 1 1 1 0
1
Figure 8. Single Read From The Current Location
DATA
7.5.1.3 Sequential Read and Write
Sequential read and write allows simple and fast access to DRV201A registers.
shows sequential read from a defined location. If the master doesn’t issue a stop condition after giving ACK, DRV201A auto increments the register number and writes the data from the next register.
CURRENT REGISTER NUMBER K REGISTER NUMBER M REGISTER NUMBER M+1 K+2 REGISTER NUMBER M+L-1 M+L
DRV201A ADDRESS
0 0 0 1 1 1 0
0
REGISTER NUMBER
M
DRV201A ADDRESS
0 0 0 1 1 1 0
1 DATA DATA
L bytes of DATA
Figure 9. Sequential Read From A Defined Location
DATA
shows the sequential write. If the master doesn’t issue a stop condition after giving ACK, DRV201A auto increments it’s register by one and the master can write to the next register.
CURRENT REGISTER NUMBER K REGISTER NUMBER M REGISTER NUMBER M+1 M+2 REGISTER NUMBER M+L-1 M+L
DRV201A ADDRESS
0 0 0 1 1 1 0
0
REGISTER NUMBER
M
DATA DATA DATA
L bytes of DATA
Figure 10. Sequential Write
If read is started without writing the register value first, DRV201A writes out data from the current location. If the master doesn’t issue a stop condition after giving ACK, DRV201A auto increments the I 2 C register and writes out the data. This continues until the master issues a stop condition. This is shown in
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Programming (continued)
CURRENT REGISTER NUMBER K www.ti.com
REGISTER NUMBER K+1 K+2 REGISTER NUMBER K+L-1 K+L
DRV201A ADDRESS
0 0 0 1 1 1 0
1 DATA DATA DATA
L bytes of DATA
Figure 11. Sequential Read Starting From A Current Location
7.5.1.4 I
2
C Device Address, Start and Stop Condition
Data transmission is initiated with a start bit from the controller as shown in
Figure 12 . The start condition is
recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon reception of a start bit, the device will receive serial data on the SDA input and check for valid address and control information. SDA data is latched by DRV201A on the rising edge of the SCL line. If the appropriate device address bits are set for the device, DRV201A issues the ACK by pulling the SDA line low on the next falling edge after 8th bit is latched. SDA is kept low until the next falling edge of the SCL line.
Data transmission is completed by either the reception of a stop condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address, sub-address and data words. Reference
SDA
SCL
. . .
. . .
1 2 3 4 5 6 7 8 9
START CONDITION ACKNOWLEDGE
Figure 12. I
2
C Start/Stop/Acknowledge Protocol
STOP CONDITION t
LOW t r t f t
H(STA)
SCL t
H(STA) t
H(DAT) t
HIGH t
S(DAT) t
S(STA) t
S(STO)
SDA
P t
(BUF)
S
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S
Figure 13. I
2
C Data Transmission Protocol
P
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7.6 Register Maps
DRV201A
SLVSBN6A – JUNE 2013 – REVISED AUGUST 2015
REGISTER
3
4
1
2
5
6
7
ADDRESS (HEX)
01
02
03
04
05
06
07
FIELD NAME
RESET
EN_RING
Table 2. Register Maps
NAME
DEFAULT
VALUE not used
CONTROL
VCM_CURRENT_MSB
VCM_CURRENT_LSB
STATUS
MODE
VCM_FREQ
0000 0010
0000 0000
0000 0000
0000 0000
0000 0000
1000 0011
DESCRIPTION
Control register
Voice coil motor MSB current control
Voice coil motor LSB current control
Status register
Mode register
VCM resonance frequency
7.6.1 Control Register (Address – 0x02h)
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
Table 3. Control Register Address – 0x02h Description
D7 not used
R
0
D6 not used
R
0
D5 not used
R
0
D4 not used
R
0
D3 not used
R
0
D2 D1 not used EN_RING
R R/W
0 1
D0
RESET
R/W
0
Table 4. Control Register Address Field Definitions
BIT DEFINITION
Forced software reset (reset all registers to default values) and device goes into STANDBY. RESET bit is automatically cleared when written high.
0 – inactive
1 – device goes to STANDBY
Enables ringing compensation.
0 – disabled
1 – enabled
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7.6.2 VCM MSB Current Control Register (VCM_Current_MSB) Address – 0x03h www.ti.com
Table 5. VCM MSB Current Control Register (VCM_Current_MSB) Address – 0x03h Description
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7 not used
R
0
D6 not used
R
0
D5 not used
R
0
D4 not used
R
0
D3 not used
R
0
D2 not used
R
0
D1 D0
VCM_CURRENT[9:8]
R/W
0 0
FIELD NAME
VCM_CURRENT[9:8]
Table 6. VCM MSB Current Control Register Field Definitions
BIT DEFINITION
VCM current control
00 0000 0000b – 0 mA
00 0000 0001b – 0.1 mA
00 0000 0010b – 0.2 mA
…
11 1111 1110b – 102.2 mA
11 1111 1111b – 102.3 mA
NOTE
When setting the current in DRV201A both
VCM_CURRENT_MSB and VCM_CURRENT_LSB registers have to be updated. DRV201A starts updates the current after LSB register write is completed.
7.6.3 VCM LSB Current Control Register (VCM_Current_lSB) Address – 0x04h
Table 7. VCM LSB Current Control Register (VCM_Current_ISB) Address – 0x04hDescription
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7 D6
VCM_CURRENT[7:0]
R/W
0 0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
FIELD NAME
VCM_CURRENT[7:0]
Table 8. VCM LSB Current Control Register Field Definitions
BIT DEFINITION
VCM current control
00 0000 0000b – 0 mA
00 0000 0001b – 0.1 mA
00 0000 0010b – 0.2 mA
…
11 1111 1110b – 102.2 mA
11 1111 1111b – 102.3 mA
NOTE
When setting the current in DRV201A both
VCM_CURRENT_MSB and VCM_CURRENT_LSB registers have to be updated. DRV201A starts updates the current after LSB register write is completed.
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7.6.4 Status Register (Status) Address – 0x05h
(1)
DRV201A
SLVSBN6A – JUNE 2013 – REVISED AUGUST 2015
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
Table 9. Status Register (Status) Address – 0x05h Description
D7 not used
R
0
D6 not used
R/WR
0
D5 not used
R
0
D4
TSD
R
0
D3
VCMS
R
0
D2
VCMO
R
0
D1
UVLO
R
0
D0
OVC
R
0
(1) Status bits are cleared when device changes it’s state from standby to active. If TSD was tripped the device goes into Standby and will not allow the transition into Active until the device cools down and TSD is cleared.
FIELD NAME
OVC
UVLO
VCMO
VCMS
TSD
Table 10. Status Register Address Field Descriptions
BIT DEFINITION
Over current detection
Undervoltage Lockout
Voice coil motor open detected
Voice coil motor short detected
Thermal shutdown detected
7.6.5 Mode Register (Mode) Address – 0x06h
DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
Table 11. Mode Register (Mode) Address – 0x06h Description
D7 D6 D5 D4 D3 D2 not used
R
0 not used
R
0 not used
R
0
PWM_FREQ[2:0]
R/W
0
R/W
0
R/W
0
FIELD NAME
RING_MODE
PWM/LIN
PWM_FREQ[2:0]
Table 12. Mode Register (Mode) Address Field Definitions
Ringing compensation settling time
0 – 2x(1/f
VCM
)
1 – 1x(1/f
VCM
)
Driver output stage in linear or PWM mode
BIT DEFINITION
0 – PWM mode
1 – Linear mode
Output stage PWM switching frequency
000 – 0.5 MHz
001 – 1 MHz
010 – N/A
011 – 2 MHz
100 – N/A
101 – 4.8 MHz
110 – 6.0 MHz
111 – 4 MHz
D1
PWM/LIN
R/W
0
D0
RING_MOD
E
R/W
0
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7.6.6 VCM Resonance Frequency Register (VCM_FREQ) Address – 0x07h www.ti.com
Table 13. VCM Resonance Frequency Register (VCM_FREQ) Address – 0x07h Description
D5 D4 D3 D2 D1 DATA BIT
FIELD NAME
READ/WRITE
RESET VALUE
D7
VCM_FREQ[7:0]
R/W
1
D6
0 0 0 0 0 1
D0
1
FIELD NAME
VCM_FREQ[7:0]
Table 14. VCM Resonance Frequency Register Field Definitions
BIT DEFINITION
VCM mechanical ringing frequency for the ringing compensation can be selected with the below formula. The formula gives the VCM_FREQ[7:0] register value in decimal which should be rounded to the nearest integer.
VCM _ FREQ
=
383
-
19200
F res
Default VCM mechanical ringing frequency is 76.4 Hz.
VCM _ FREQ = 383
-
19200
76.4
=
131.69
Þ
132
Þ
'1000 0011'
(1)
(2)
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8 Application and Implementation
DRV201A
SLVSBN6A – JUNE 2013 – REVISED AUGUST 2015
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV201A device is a voice coil motor driver designed for camera auto focus control. The device allows for a highly efficient PWM current control for VCM, while reducing lens ringing in order to significantly lower the time needed for the lens to auto focus. The following design is a common application of the DRV201A device.
8.1.1 VCM Mechanical Ringing Frequency
Ringing compensation is dependent on the VCM resonance frequency, and this can be controlled through the
VCM_FREQ register (07h) from 50 Hz up to 150 Hz. VCM mechanical ringing frequency for the ringing compensation can be selected using
Equation 3 . The formula gives the VCM_FREQ[7:0] register value in
decimal which should be rounded to the nearest integer.
VCM _ FREQ
=
383
-
19200
F res (3)
Default VCM mechanical ringing frequency is 76.4 Hz.
VCM _ FREQ = 383 -
19200
76.4
= 131.69
Þ 132 Þ '1000 0011'
(4)
8.2 Typical Application
DRV201A
VBAT ISOURCE
+
VCM
Vin 1 µF
SCL
ISINK
To/From a controller
SDA GND
Figure 14. Typical Application Schematic
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Typical Application (continued)
8.2.1 Design Requirements
lists the design parameters.
www.ti.com
Table 15. Design Parameters
DESIGN PARAMETER
Supply voltage
Motor Winding
Resistance
Motor Winding
Inductance
Actuator Size
Lens in the VCM
Weight of VCM
TTL
FB
REFERENCE
Vin
RL
IL
EXAMPLE VALUE
3.7
15 Ω
100 µH
8.5 x 8.5 x 3.4 (mm)
M6 (Pitch: 0.35)
75 mg
4.2 mm
1.1 mm
8.2.2 Detailed Design Procedure
List of components:
• C in
- Panasonic ECJ0EB1A105M
• VCM - Mitsumi VCM KAF-V85S60
• Actuator size: 8.5 × 8.5 × 3.4 (mm)
• Lens in the VCM: M6 (Pitch: 0.35)
• Weight: 75 mg
• TTL: 4.2 mm
• FB: 1.1 mm
8.2.2.1 User Example 1
In
how the lens is controlled and what settling time is achieved:
Measured VCM resonance frequency = 100 Hz
• According to
Table 1 , VCM_FREQ[7:0] = ‘10111111’ (reg 0x07h)
VCM resonance frequency, f
VCM
, variation is within ±10% (min 90 Hz … max 110 Hz)
• 1/f
VCM ringing compensation is used : RING_MODE = ‘1’ (reg 0x06h)
Stepping the lens by 50 µm
• The lens is settled into a ±5-µm window within 10 ms (1/f
VCM
)
8.2.2.2 User Example 2
If the case is otherwise exactly the same, but VCM resonance frequency cannot be guaranteed to stay at more than ±30% variation, slower ringing compensation should be used:
Measured VCM resonance frequency = 100 Hz
• According to
Table 1 , VCM_FREQ[7:0] = ‘10111111’ (reg 0x07h)
VCM resonance frequency, f
VCM
, variation is within ±30% (min 70 Hz … max 130 Hz)
• 2/f
VCM ringing compensation is used : RING_MODE = ‘0’ (reg 0x06h)
Stepping the lens by 50 µm
• The lens is settled into a ±5-µm window within 20 ms (2/f
VCM
)
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±10% step size window settling time
DRV201A
SLVSBN6A – JUNE 2013 – REVISED AUGUST 2015
Lens position
8.2.3 Application Curves
Time
Figure 15. Lens Settling Time and Settling Window
Figure 16. Lens Positions With and Without Ringing
Compensation With 100-µm Step on the Lens Position
Figure 17. Lens Positions With and Without Ringing
Compensation With 100-µm Step on the Lens Position,
Zoomed In
Figure 18. Lens Positions With and Without Ringing
Compensation With 30-µm Step on the Lens Position
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Figure 19. Lens Positions With and Without Ringing
Compensation With 30-µm Step on the Lens Position,
Zoomed In
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9 Power Supply Recommendations
The DRV201A device is designed to operate from an input voltage supply, VBAT, range between 2.5 and 4.8 V.
The user must place at least a 1-uF ceramic bypass capacitor rated for a minimum of 6.3 V as close as possible to VBAT and GND pin.
10 Layout
10.1 Layout Guidelines
The VBAT pin should be bypassed to GND using a low-ESR ceramic bypass capacitor with a recommended value of at least 1-µF rated for a minimum of 6.3 V. Place this capacitor as close to the VBAT and GND pins as possible with a thick trace or ground plane connection to the device GND pin.
10.2 Layout Example
1µF
Figure 20. Recommended Layout Example
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11 Device and Documentation Support
DRV201A
SLVSBN6A – JUNE 2013 – REVISED AUGUST 2015
11.1 Device Support
11.1.1 Device Nomenclature
YMB package markings (see pinouts in
Pin Configuration and Functions ):
• YM = YEAR / MONTH DATE CODE
• D = DAY OF LASER MARK
• S = ASSEMBLY SITE CODE
• O = PinA1 (Filled Solid)
Table 16. YMB Package Dimensions
DIMENSION
Length
Width
Height
(1)
Ball pitch
Ball height
Coating thickness
(2)
(1) Height tolerances valid for both coated and non-coated packages.
(2) Coating thickness only applies to DRV201AYMBRB (coated) package option.
MIN
0.278
0.39
4.8
0.39
TYP
0.289
0.4
6
0.4
MAX
1.49
0.806
0.3
0.41
7.2
0.41
UNIT mm mm mm mm
µm mm
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use .
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
11.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Oct-2014
PACKAGING INFORMATION
Orderable Device
DRV201AYMBR
Status
(1)
Package Type Package
ACTIVE PICOSTAR
Drawing
YMB
Pins Package
Qty
6 3000
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Lead/Ball Finish
(6)
Call TI
MSL Peak Temp
(3)
Level-1-260C-UNLIM
Op Temp (°C)
-40 to 85 201A
Device Marking
(4/5)
DRV201AYMBRB ACTIVE PICOSTAR YMB 6 3000 Green (RoHS
& no Sb/Br)
Call TI Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
-40 to 85 201AB
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
29-Oct-2014 www.ti.com
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
17-Jun-2015
*All dimensions are nominal
Device
DRV201AYMBR
Package
Type
Package
Drawing
YMB
Pins
6
SPQ
3000
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
180.0
8.4
A0
(mm)
0.91
B0
(mm)
1.59
K0
(mm)
0.36
P1
(mm)
4.0
W
(mm)
Pin1
Quadrant
8.0
Q1
DRV201AYMBRB
PICOST
AR
PICOST
AR
YMB 6 3000 180.0
8.4
0.91
1.59
0.36
4.0
8.0
Q1
Pack Materials-Page 1
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PACKAGE MATERIALS INFORMATION
17-Jun-2015
*All dimensions are nominal
Device
DRV201AYMBR
DRV201AYMBRB
Package Type Package Drawing Pins
PICOSTAR
PICOSTAR
YMB
YMB
6
6
SPQ
3000
3000
Length (mm) Width (mm) Height (mm)
182.0
182.0
182.0
182.0
20.0
20.0
Pack Materials-Page 2
IMPORTANT NOTICE
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards.
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Products
Audio
Amplifiers
Data Converters
DLP® Products
DSP
Clocks and Timers
Interface
Logic
Power Mgmt
Microcontrollers
RFID
OMAP Applications Processors
Wireless Connectivity www.ti.com/audio amplifier.ti.com
dataconverter.ti.com
www.dlp.com
dsp.ti.com
www.ti.com/clocks interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
Applications
Automotive and Transportation
Communications and Telecom
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
Medical
Security
Space, Avionics and Defense
Video and Imaging www.ti-rfid.com
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