datasheet for PUMA68F16001 by Apta Group

datasheet for PUMA68F16001 by Apta Group
TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
PRODUCT MAY BE MADE OBSOLETE WITHOUT NOTICE
hmp
512K x 32 FLASH MODULE
PUMA 68F16001/A-12/15/20/25
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
Issue 4.0 : March 1998
NE29 8SE, England Tel. +44 (0)191 2930500 Fax. +44 (0) 191
2590997
Description
A version 'A' with four independent write enables
The PUMA 68F16001 is a 16Mbit CMOS FLASH (WE1-4) is available.
memory module organised as 512K x 32 in a
JEDEC 68 pin surface mount PLCC, available with
access times of 120, 150, 200 and 250ns. The
output width is user configurable as 8 , 16 or 32 bits
using four Chip Selects (CS1~4).
Page write (256 Bytes) is performed in 10ms with
Toggle bit and DATA polling indication of cycle
completion. The device features both hardware
and software data protection and a low power
standby of 6.6mW. Write cycle endurance is
10,000 Erase/Write cycles with a data retention
time of 10 years.
Features
• Access Times of 120, 150, 200 and 250ns.
• JEDEC 68 'J' leaded plastic Surface Mount
Substrate.
• Industrial or Military.
• User Configurable as 8 / 16 / 32 bit wide
output.
• Operating Power :
880 mW (max)
• Standby Power : -L Part (CMOS)
6.6 mW (max)
• Page Write (256 Bytes) in 10ms typ.
• DATA Polling and Toggle bit indication of end of
write.
• Hardware and Software Data Protection.
• Endurance of 104 Erase/write Cycles and Data
Retention Time of 10 years.
Pin Definition (See page 10 for 'A' version)
NC
A0
A1
A2
A3
A4
A5
CS3
GND
CS4
WE
A6
A7
A8
A9
A10
Vcc
Block Diagram (See page 10 for 'A' version)
512K x 8
512K x 8
512K x 8
512K x 8
FLASH
FLASH
FLASH
FLASH
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
VIEW
17
53
FROM
18
52
19
51
ABOVE
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
PUMA 68F16001
Vcc
A11
A12
A13
A14
A15
A16
CS1
OE
CS2
A17
NC
NC
NC
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
Pin Functions
A0~18
CS1~4
WE
VCC
Address Inputs
Chip Select
Write Enable
Power (+5V)
D0~31
OE
NC
GND
Data Inputs/Outputs
Output Enable
No Connect
Ground
A18
GND
NC
A0~A18
OE
WE
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
PUMA 68F16001/A-12/15/20/25
ISSUE 4.0 : MARCH 1998
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
Operating Temperature
Storage Temperature
Input voltages (including N.C. pins) with Respect to GND
Output voltages with respect to GND
TOPR
TSTG
VIN
VOUT
°
-55 to +125
-65 to +150
-0.6 to +6.25
-0.6 to VCC+0.6
C
C
V
V
°
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Recommended Operating Conditions
DC Power Supply Voltage
Input Low Voltage
Input High Voltage
Operating Temp Range
VCC
VIL
VIH
TA
TAI
TAM
min
typ
max
4.5
2.0
0
-40
-55
5.0
-
5.5
0.8
70
85
125
DC Electrical Characteristics (TA=-55°C to +125°C,V
Parameter
Symbol
V
V
V
°
C
°
C (I Suffix)
°
C (M Suffix)
=5V ± 10%)
CC
Test Condition
min
Input Leakage Current
Output Leakage Current
ILI1
32 bit ILO
VIN = GND to VCC
Operating Supply Current
32 bit ICC32
16 bit ICC16
8 bit ICC8
CS(1)=OE=VIL, WE=VIH, IOUT=0mA, ƒ=5MHz
Standby Supply Current TTL levels ISB1
CMOS levels ISB2
Output Low Voltage
Output High Voltage
VOL
VOH
max
Unit
-
40
40
µA
µA
-
160
86
49
mA
mA
mA
-
12
1.2
mA
mA
2.4
0.45
-
(1)
VIN = GND to VCC, CS =VIH
As above
As above
CS(1) = VIH, II/O = 0mA, Other Inputs = VIH
(1)
CS = VCC-0.3V, II/O = 0mA, Other Inputs = VCC
IOL = 2.1mA.
IOH = -400µA.
V
V
Notes (1) CS above are accessed through CS1-4. These inputs must be operated simultaneously for 32 bit operation, in pairs
in 16 bit mode and singly for 8 bit mode.
Capacitance (TA=25°C,ƒ=1MHz) Note: These parameters are calculated, not measured.
Parameter
Input Capacitance
Output Capacitance
Symbol
A0-A18, OE, WE
Other Inputs
Test Condition
typ
max Unit
CIN1
CIN2
VIN=0V
VIN=0V
-
30
10
pF
pF
COUT
VOUT=0V
-
52
pF
2
PUMA 68F16001/A-12/15/20/25
ISSUE 4.0 : MARCH 1998
AC OPERATING CONDITIONS
Read Cycle
Parameter
Symbol
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable Access Time
Chip Select High to High Z Output
Output Enable High to High Z Output
Output Hold from Address Change
tRC
tAA
tCS
tOE
tHZ
tOHZ
tOH
-12
min max
-15
min max
-20
min max
-25
min max
120
0
0
0
0
150
0
0
0
0
200
0
0
0
0
250
0
0
0
0
120
120
50
30
30
-
150
150
70
40
40
-
200
200
80
50
50
-
Notes:(1) tHZ is specified from OE or CS 1-4 whichever occurs first (Cl=5 pf).
(2) All parameter Units are nS
Write Cycle
Parameter
Symbol
min
typ
max
Unit
Write Cycle Time
tWC
-
-
10
ms
Address Set-up Time
tAS
10
-
-
ns
Address Hold Time
tAH
50
-
-
ns
Output Enable Set-up Time
tOES
10
-
-
ns
Output Enable Hold Time
tOEH
10
-
-
ns
Chip Select Set-up Time
tCS
0
-
-
ns
Chip Select Hold Time
tCH
0
-
-
ns
Write Pulse Width
tWP
90
-
-
ns
Write Enable High Recovery
tWPH
100
-
-
ns
Data Set-up Time
tDS
50
-
-
ns
Data Hold Time
tDH
10
-
-
ns
Byte Load Cycle
tBLC
-
-
150
µs
AC Test Conditions
Output Test Load
I/O Pin
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: 1 TTL gate + 100pF
* VCC=5V±10%
645 Ω
1.76V
100pF
3
250
250
90
60 (1)
60 (1)
-
PUMA 68F16001/A-12/15/20/25
ISSUE 4.0 : MARCH 1998
AC Write Waveform - WE Controlled
OE
t OEH
t OES
ADDRESS
t AS
CE
t CH
t AH
t CS
WE
t WPH
t WP
DATA
t DS
t DH
IN
AC Write Waveform - CS Controlled
OE
t OES
t OEH
ADDRESS
t AS
CE
t AH
t CH
t CS
WE
t WPH
t WP
t DS
DATA
IN
4
t DH
PUMA 68F16001/A-12/15/20/25
ISSUE 4.0 : MARCH 1998
Read Cycle Timing Waveform
Address
Address Valid
t RC
t CS
CS
t OHZ
t OE
t OLZ
OE
t HZ
t OH
t LZ
HIGH z
Dout
Output
Valid
Output
Valid
t AA
Software Protected Write Waveform
OE
CE
tWP
t BLC
WE
tAS
tWPH
tAH
A0~A7
BYTE ADDRESS
5555
2AAA
5555
A8~A18
PAGE ADDRESS
tDS tDH
Data
AA
55
tWC
A0
Byte 0
Byte 254
Byte 255
Note: (1) A8 through A18 must specify the page address during each high to low transition of Write Enable (or Chip select).
(2) Output Enable must be high only when Write Enable and Chip Select are both low.
(3) All bytes that are not loaded within the sector being programmed will be indeterminate.
5
PUMA 68F16001/A-12/15/20/25
ISSUE 4.0 : MARCH 1998
DATA Polling Waveform
WE/WE1~4
CS1~4
tOEH
OE
tDH
tWR
tOE
High Z
D7,D15,
D23,D31
tDW
An
A0-A18
An
An
An
An
Toggle Bit Waveform
WE
CS1~4
tOEH
OE
tOE
tDH
D6
tWR
HIGH Z
tDW
(1) Toggling either OE or CE or both OE and CE will operate toggle bit.
(2) Beginning and adding state of D7, D15, D23, D31 may vary.
(3) Any address location may be used but the address should not vary.
Page Mode Write Waveform
OE
CE
tW P
tB L C
W PH
WE
tA S
A 0 -A 7
A 8 -A 1 8
tD H
tA H
B y te
Add
S e c to r
Add
tD S
D a ta
V a lid
D ata
B y te 0
B y te 1
B y te 2
B y te 3
6
B y te 2 5 4
B y te 2 5 5
tW C
PUMA 68F16001/A-12/15/20/25
ISSUE 4.0 : MARCH 1998
Device Operation
Read
The PUMA 68F16001 read operations are initiated when Write Enable is high and both Output Enable and Chip
Select are LOW. The read operation is terminated by either Chip Select or Output Enable returning HIGH. This
2-line control architecture eliminates bus connection in a system environment. The data bus will be in a high
impedance state when either Output Enable or Chip Select is HIGH.
Write
The device is reprogrammed on a sector basis. Byte loads are used to enter the 256 bytes of a sector to be
programmed or the software codes for data protection. A byte load is performed by applying a low pulse on the WE
or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE,
whichever occurs last. The data is latched by the first rising edge of CE or WE.
If a byte of data within a sector is to be changed, data for the entire sector must be loaded into the device. Any byte
that is not loaded during the programming of its sector will be erased to read FFh.
During a reprogram cycle, the address locations and 256 bytes of data are internally latched, freeing the address
and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase
the sector and then program the latched data using an internal control timer. The end of a program cycle can be
detected by DATA polling on D7. Once the end of a program cycle has been detected, a new access for a read
or program can begin.
Each new byte to be programmed must have its high to low transition on WE (or CE) within 150µs of the high
to low transition of WE (or CE) of the preceding byte. If a high to low transition is not detected within 150 µs of
the last low to high transition, the load period will end and the internal programming period will start. A8 to A18
specify the sector address. The sector address must be valid during each high to low transition of WE (or CE).
A0 to A7 specify the byte address within the sector. The bytes may be loaded in any order; sequential loading
is not required.
DATA Polling
In order to detect the end of a write cycle, two methods are provided. During a write operation (Byte or Page)
an attempt to read the last byte written will result in the compliment of the written data appearing on D7 (or
D15, D23 or D31, depending on the device selected). Once the write cycle is completed, true data appears on
the outputs and the next write cycle may begin. Using this method of indicating the end of a write can
effectively reduce the total write time by 50%.
TOGGLE bit
In addition to DATA polling, another method is provided to determine the end of a Write Cycle. During a write
operation successive attempts to read data will result in D6 (or D14, D22 or D30, depending on the device selected).
toggling between 1 and 0. Once a write is complete, this toggling will stop and valid data will be read as normal,
allowing the next write cycle to be performed. This can eliminate the software housekeeping chore of saving and
fetching the last address and data written in order to implement DATA polling. This can be especially helpful in
an array composed of multiple PUMA 68F16001 modules that are frequently updated.
7
PUMA 68F16001/A-12/15/20/25
ISSUE 4.0 : MARCH 1998
Hardware Data Protection
Both hardware and software protection is provided as described below.
Four types of hardware protection give high security against accidental writes:
If Vcc - 3.8V, Write is inhibited.
OE low, CS or WE high inhibits inadvertant Write Cycles during power-on and power-off. Write Cycle timing
specifications must be observed concurrently.
• Pulses are less than 15ns on WE do not initiate a Write Cycle.
•
•
Software controlled data protection, once enabled by the user, means that a software algorithm must be used
before any write can be performed. To enable this feature the algorithm below is followed, and must be reused
for each subsequent write operation. Once set the data protection remains operational until it is disabled by
using the second algorithm overleaf: power transitions will not reset this feature.
Software Algorithms
Selecting the software data protection mode requires the host system to precede datawrite operations by a series
of three write operations to three specfic addresses. The three byte sequence opens the page write window
enabling the host to write 256 bytes of data. Once the page load cycle has been completed, the device will
automatically be returned to the data protected state
Software Data Protection Algorithm (1)
Regardless of whether the device has been protected or not, once the software data protected algorithm is used
and the data is written, the PUMA 68F16001 will automatically disable further writes unless another command is
issued to cancel it. If no further commands are issued the PUMA 68F16001 will be write protected during powerdown and any subsequent power-up.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
LOAD DATA
(4)
TO
SECTOR (256 BYTES)
WRITES
ENABLED (2)
Notes:
(1) Data Format I/O7-I/O0 (Hex);
Once initiated, this sequence of write operations should not be interrupted.
(2) Enable Write Protect state will be initiated at end of
write even if no other data is loaded.
(3) Disable Write Protect state will be initiated at end of
write period even if no other data is loaded.
(4) 256 bytes of data must be loaded.
ENTER DATA
PROTECT
STATE
8
PUMA 68F16001/A-12/15/20/25
ISSUE 4.0 : MARCH 1998
Software Data Protect Disable
In the event the user wants to deactivate the software data protection feature for testing or reprogramming in an
E2PROM programmer. The following six step algorithm will reset the internal protection circuit. After tWC, the
PUMA 68F16001 will be in standard operating mode.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
EXIT DATA
PROTECT
STATE (3)
LOAD DATA
(4)
TO
SECTOR (256 BYTES)
9
PUMA 68F16001/A-12/15/20/25
ISSUE 4.0 : MARCH 1998
Version 'A' Block Diagram
NC
A0
A1
A2
A3
A4
A5
CS3
GND
CS4
WE
A6
A7
A8
A9
A10
Vcc
Version 'A' Pin Definition
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
VIEW
17
53
FROM
18
52
19
51
ABOVE
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
PUMA 68F16001A
A0~A18
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
OE
WE4
WE3
WE2
WE1
512K x 8
FLASH
512K x 8
FLASH
512K x 8
FLASH
512K x 8
FLASH
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
Vcc
A11
A12
A13
A14
A15
A16
CS1
OE
CS2
A17
WE2
WE3
WE4
A18
GND
NC
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
Package Information
Dimensions in mm(inches)
Plastic 68 Pin JEDEC Surface mount PLCC
25.27 (0.995) sq.
5.08
(0.200) max
25.02 (0.985) sq.
0.10 (0.004)
0.90 (0.035) typ.
10
23.11 (0.910)
0.46
(0.018) typ.
24.13 (0.950)
1.27
(0.050) typ.
PUMA 68F16001/A-12/15/20/25
ISSUE 4.0 : MARCH 1998
Ordering Information
PUMA 68F16001AM - 12
Speed
12
15
20
25
=
=
=
=
120 ns
150 ns
200 ns
250 ns
Temp. range
Blank = Commercial Temperature
I = Industrial Temperature
M = Military Temperature
Special Features
Blank = Single WE
A = WE1-4
Organisation
16001 = 512K x 32, user configurable
as 1M x 16 and 2M x 8
Memory Type
Package
F = FLASH
PUMA 68 = 68 pin "J" Leaded PLCC
THIS PRODUCT IS NOT RECOMMENDED FOR NEW DESIGNS
11
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement