NEWS BRIEFS IN-DEPTH ART I C L E

NEWS BRIEFS IN-DEPTH ART I C L E

Volume Twenty-Two

NEWS BRIEFS

Maxim reports record revenues, earnings, and operating income

IN-DEPTH ART I C L E

Comparator/DAC combinations solve data-acquisition problems

2

3

D E S I G N S H O W C A S E

PC serial port drives 12-bit A/D converter

PFM control improves dual-output step-up converter

Synchronous buck-regulator output terminates high-speed data buses

Autotransformer regulator inverts 12V to -12V

Serial-data interface chip supplies bipolar voltages

Programmable current source delivers 0A to 5A

N E W P R O D U C T S

Op Amps/Comparators

Ultra-low-power, open-drain, comparator-plus-reference ICs draw only 4µA

(MAX971–974/

MAX981–984)

High-Speed Op Amps

350MHz, voltage-feedback op amp has 1300V/µs slew rate

275MHz quad video buffers drive 50

and 75

cables

Op-amp family provides low noise and ultra-low distortion

(MAX477)

(MAX496/497)

(MAX4106 – 4109)

500MHz, current-feedback video amplifiers draw 5mA and deliver 80mA out

(MAX4112/4113)

Analog Switches and Multiplexers

Quad, SPST analog switches offer 10

on-resistance

8-channel and dual 4-channel multiplexers have serial control

Low-voltage, quad, SPST analog switches offer low cost

Low-voltage, 8-channel SPST switch has serial interface

(MAX312/313/314)

(MAX349/350)

(MAX4066/4066A)

(MAX395)

Power Management ICs

Ultra-thin PCMCIA power supplies fit Type 1 and Type 2 cards

(MAX606/607)

Step-up controller generates fixed (5V) or adjustable (3V to 16.5V) outputs

(MAX608)

Lowest-dropout SOT-23 linear regulators deliver 50mA

(MAX8863/8864)

Interface ICs

Complete, isolated, full-duplex RS-485/RS-422 interface costs under $10

(MAX1490A/1490B)

Low-power, slew-rate-limited RS-485/RS-422 transceivers are

ESD protected to ±15kV

( M A X 4 8 1 E / 4 8 3 E / 4 8 5 E /

487E –491E/1487E)

19

20

21

22

23

22

22

23

19

19

20

20

21

23

10

12

13

15

16

17

News Briefs

MAXIM REPORTS RECORD REVENUES, EARNINGS,

AND OPERATING INCOME FOR THE SECOND QUARTER

Maxim Integrated Products, Inc., reported record net revenues of $106.2 million for the second quarter of fiscal 1996 ending December 31, 1995, compared to $56.2 million for the same period a year ago. This represents an 89% increase in net revenues from the same quarter a year ago. This growth rate is the result of the Company’s manufacturing efforts to get shipping levels more in line with customer booking and usage rates. Net income increased 258% to $31.9 million (or $0.45 per share) for the quarter, compared to net income of $8.9 million (or

$0.14 per share) for the same quarter in fiscal 1995. Bookings across all product lines continue to exceed shipments. Backlog shippable in the next 12 months remains at over $190 million. Operating income was a record

45.1% of net revenues, compared to 23.5% for Q295. Annualized return on equity increased to 58.4% for Q296 compared to 25.2% for fiscal 1995.

These results mark our 41st consecutive quarter of increased revenues and 39th consecutive quarter of increased earnings, a record unmatched by any company in the analog integrated circuit industry.

During the quarter, the Company increased cash and short-term investments by $6.2 million after paying for over $21 million in capital equipment and repurchasing $15.6 million of its common stock.

Factory shipments for the first 6 months of fiscal 1996 increased 88% as compared to the same period in fiscal 1995. Wafer fabrication production increased 124% over the same period in fiscal 1995. However, revenues reported for the quarter continue to be constrained by wafer fabrication production levels.

Jack Gifford, Chairman, President, and CEO, commented: “While Maxim built and shipped 88% more product during the first 6 months of fiscal 1996 than during the same period in 1995, it has been more difficult than planned to increase production levels at our Beaverton wafer fabrication facility. Productivity levels, as measured by quarterly wafers out per technician, reached a peak in Q495 and were essentially flat in the first half of FY96. The Beaverton facility’s production efficiency is currently 50% of Maxim’s Sunnyvale facility.”

Mr. Gifford commented further: “During the first two quarters after we acquired the facility from

Tektronix, we were able to take advantage of 60 trained technicians acquired with the facility. Since that time, we have added over 150 technicians who were untrained in our wafer manufacturing processes and equipment.

Although we believe that these technicians have accomplished a great deal in a short time, we anticipate that it will be several quarters before they will be fully trained and approaching the efficiency levels of our Sunnyvale facility. The availability of trained technicians in the Portland area has not been sufficient to meet our plan for manufacturing capacity.”

Gifford continued: “Based on this experience in Beaverton, I believe that the lack of qualified, trained technicians worldwide could be a challenge to the industry as the planned wafer capacity comes on line in 1996 and beyond. This factor, along with continued increased worldwide demand, will continue to put pressure on those facilities that are up and running today.”

During the quarter, the Board of Governors of NASDAQ added Maxim to its index of NASDAQ 100 companies. This positions Maxim as one of the top 100 issues traded on the NASDAQ today.

Comparator/DAC combinations solve data-acquisition problems

INPUT

TRANSIENT VOLTAGE MONITOR:

ADC APPROACH

BUFFER ADC

REF

µ

P

MEMORY

POWER

SUPPLY

The following discussion examines an overlooked option for many existing A/D converter applications: the A/D conversion is sometimes better implemented with a discrete comparator and D/A converter. This substitution generally entails a different measurement approach, but the advantages can include lower cost, higher speed, more flexibility, and lower power consumption.

Current trends, though, are in the other direction— designers who must implement A/D conversion usually specify a packaged A/D converter (ADC) for the job. Most engineers are not aware of an alternative, and the price/performance ratios for ADCs are falling all the time.

Yet, an analog comparator plus D/A converter (DAC), along with digital processing capability, form the core of a successive-approximation ADC.

The discrete comparator/DAC approach is already common in certain fields. Automatic test equipment, nuclear pulse-height discriminators, and automated timedomain reflectometers often use the technique whereby one comparator input is driven by the DAC, and the other is driven by the signal to be monitored. Following is a selection of general measurement problems and specific applications in which a comparator/DAC combination is actually more appropriate than an off-the-shelf ADC.

Transient voltage analysis

A brute-force technique for capturing fast-changing amplitude events (transients) is simply to digitize them with a high-speed ADC supported by a processor and fast

RAM (Figure 1). Single-shot events may compel the use of this approach, as may the need to discern fine detail in the transients. Otherwise, if the transients are repetitive, you can measure their peak amplitude and other features with the DAC/comparator approach (Figure 2).

The DAC sets a trial level at one input of the comparator while the transient signal is applied to the other input. You then determine peak transient amplitudes by adjusting the

DAC output, using a digital latch to capture the comparator’s output response when its threshold is exceeded. Only the comparator input need sustain the full

Figure 1. As the brute-force approach to transient analysis, an ADC circuit is power-hungry and expensive.

INPUT

TRANSIENT VOLTAGE MONITOR:

DAC/COMP APPROACH

1/4 MAX516

POWER

SUPPLY

PROCESSOR REQUIREMENTS: ~ 4 MIPS, I

CC

~ 20mA

A/D REQUIREMENTS: 2.5

µ s, I

CC

~ 15mA

TOTAL I

CC

~ 35mA

HIGH

TRANS

S

R

Q

RESET

F-F

LOW

TRANS

S

R

Q

1/4 MAX516

HIGH

LINE

S

R

Q

1/4 MAX516

LOW

LINE

S

R

Q

1/4 MAX516

µ

P

MEMORY

PROCESSOR REQUIREMENTS: 0.0002 MIPS, I

CC

< 1mA

DAC/COMPARATOR REQUIREMENTS: I

CC

= 10mA max

TOTAL I

CC

~ 11mA

Figure 2. If the Figure 1 application can accept an iterative approach to the amplitude measurements, replacing the ADC with

DAC/comparator combinations saves power and cost.

3

LCD

BATTERY

CONTRAST

ADJUST

DAC

MODEST A/D NEEDS

T

TEMP. SENSOR

MUX

µ

P

ADC

REF

RELATIVE COST:

2-CHANNEL ADC $3.00

DAC $2.00

TOTAL $5.00

Figure 3. This circuitry is commonly found in portable instruments.

LCD

T

TEMP. SENSOR

BATTERY

CONTRAST

ADJUST

DAC

µ

P

+

COMP

+

COMP

MODEST SOFTWARE OVERHEAD.

USE BETWEEN LCD UPDATES.

RELATIVE COST:

DAC $2.00

DUAL COMP $0.50

TOTAL $2.50

Figure 4. Adding two comparators to the circuit of Figure 3 enables the

DAC to double as an ADC, saving cost.

bandwidth of the transient, and the DAC output can exhibit arbitrarily long settling times without affecting the measurement accuracy. Thus, sensing in the analog domain lets you replace an expensive ADC with a lowcost DAC and comparator.

A related problem is monitoring an analog voltage with respect to tolerance limits. Many self-diagnostic instruments monitor system voltages, temperatures, and other analog quantities against limit values set in software.

However, if the comparisons are made by a comparator whose setpoint value is provided by a DAC, you can reduce the processor’s overhead because it need only read a single bit representing the out-of-limit condition.

This technique (analog-domain comparison) is just as accurate as the ADC technique (digital-domain comparison), so why digitize the whole value when you can simply compare it against a setpoint? One case should be mentioned: If the value must be compared against several setpoints, such as a low and high warning level and a low and high shutdown level, an ADC may be preferable to the four DACs and four comparators otherwise required.

Derive a simple ADC from an existing DAC

In portable instruments constrained by cost and size, an existing DAC can sometimes be persuaded to perform

A/D conversions as well. Cellular phones and medical electronics, for example, often include a DAC for adjusting the contrast voltage in an LCD (Figure 3). In some cases you can also monitor a temperature or battery voltage (as described above) simply by adding a comparator and switches. The existing DAC then does double duty, with the display blanked while the DAC participates in analog-to-digital conversions. As an alternative to blanking, a simple sample/hold consisting of an analog switch and capacitor (Figure 4) can maintain the

LCD contrast voltage during an A/D conversion.

Another alternative is to substitute a low-cost dual DAC for the existing single DAC. One half of the dual DAC produces a full-time LCD-contrast voltage, while the other half helps form a full-time ADC. Whether single or dual, the DAC and comparator require support from a fast, simple software routine that drives the DAC and samples the comparator to implement successive approximation (see sidebar, Successive Approximation).

Design considerations

Combining a DAC and comparator is simple. A signal is applied to the comparator’s noninverting input, and the

DAC provides a digitally programmable threshold at the inverting input. The comparator then produces a logichigh output whenever the signal is more positive than its threshold. But, you must apply care in several areas.

To ensure accurate threshold levels, the DAC’s dc output resistance should be low with respect the the comparator’s input bias current and scaling network. This concern arises mainly in very low-power circuits, for which the

DAC’s output resistance can be as high as 10k

.

Another DAC requirement is low ac output impedance.

Otherwise, the comparator output’s fast digital slew rate can couple through parasitic layout capacitance, producing input transients that degrade accuracy by causing oscillation. If some settling time can be sacrificed, you can lower the DAC’s ac output impedance by adding a bypass capacitor at the comparator input. Instability and oscillation can result from too much capacitive load on the DAC’s output amplifier, but that problem is easily fixed by adding a resistor in series with the DAC output.

The main issue for comparators is hysteresis. Most comparator circuits include hysteresis to prevent noise and oscillation, but hysteresis should be used sparingly—

4

DAC/Comparator Combo ICs

Maxim offers three monolithic devices that greatly simplify a design by combining the functions of a comparator and a DAC. Each device is suitable for the applications in this article, as well as many others.

The MAX516, for example, is a quad device with submicrosecond speed, suitable for many medium-speed, multiple-channel applications (Figure S1a).

The MAX910 is a single, high-speed, TTL-output

DAC/comparator with 8ns propagation delay (Figure

S1b). A similar device (the MAX911) is even faster—it

has complementary-ECL outputs and a propagation delay of 4ns.

+5V +5V

(a)

V

DD

22 6

GND

REF

19

AIN1

4 5

AIN0

(b)

MAX516

3

V

CC

2

C0

DATA

BUS

19

V

DD

6

V

CC

500k

8

LOAD

DAC0 D7–D0 10k

11–18

D7–D0

COMP 0

TH CTRL

16

8

A0

A1

WR

CS

10

9

8

7

CONTROL

LOGIC

8

LOAD

DAC1

8

LOAD

DAC2

8

LOAD

DAC3

21 20

AIN2 AIN3

COMP 1

COMP 2

COMP 3

1

C1

24

C2

23

C3

MAX910

10

11

13

RA

RB

12

TH OUT

CMP IN+

14

CMP IN-

CMP

GND

18

THRESHOLD OUTPUT RANGE +2.54V TO +2.56V;

1LSB = 20mV

GND

20

GND

15

V

EE

7

REFOUT

9

REF IN

CMP

OUT

8

17

500k

-5V

Figure S1. 8-bit DAC/comparator ICs from Maxim include the quad MAX516 (a), the high-speed, TTL-compatible MAX910 (b), and the ECL-compatible MAX911 (not shown).

Successive Approximation

Successive approximation is easily illustrated by the procedure that uses a balance and a set of binary trial weights (a series of weights whose relative values are 1,

2, 4, 8, 16, etc.) to determine an object’s weight. To sive-approximation register (SAR) of a packaged ADC, or in a software routine associated with the processor that controls a DAC/comparator circuit. The “pseudo-code” shown in Table S1 represents such a routine. For most determine the unknown weight by the quickest method

(successive approximation), first balance the unknown against the largest trial weight. According to processors, this routine can be realized with fewer than 20 lines of code.

Table S1. Pseudo-Code for Successive Approximation

the balance indication, either remove that weight or add the next largest, and continue

Begin: /Comments that process down to the smallest trial weight. The resulting best estimate of the object’s weight is the sum of trial weights remaining in the balance pan.

In successive-approximation ADCs, the bits of the internal DAC are analogous to the set of binary weights, and the comparator output is analogous to the balance indication. Logic for driving the bit-trial

Mask = 80h

Value = 80h

Loop:

Output DAC (Value)

Delay (settling time)

If input (comp. output) = high

Value = Value and not (mask)

Shift mask right:

Value = Value or mask

Loop until mask = 0

/Shifting weight value—start high

/Value = output (initially half scale)

/Output current Value to DAC

/Wait for DAC output to settle

/Check comparator output bit

/Clear mask bit (set by default)

/Next trial weight

/Loop until all bit weights are tried

End: Value contains the final result of the successive approximation.

procedure can reside either in the succes-

5

V

DD

100k

TP0606

SHUTDOWN

33

µ

F

2N7002

µ

P INTERFACE

NOTE: FOR SERIAL INTERFACE USE MAX531

18

REFOUT

17

REFGND

2.048V

REFERENCE

14

AGND

POWER-ON

RESET

11

10

16

15

8

9

CLR

A0

A1

CS

WR

LDAC

CONTROL

LOGIC

13

REFIN R

22

OFS

NBL

INPUT

LATCH

DAC

MAX530

12-BIT DAC LATCH

NBM

INPUT

LATCH

NBH

INPUT

LATCH

R

FB

21

V

OUT

20

10k

V

DD

23

DGND

V

SS

12

19

0.1

µ

F

V

DD

50pF

0.1

µ

F

100

MAX913

V

IN

0V to 2.048V

D0/D8 D1/D9 D2/D10

24 1 2

D3/D11 D4 D5 D6 D7

3 4 5 6 7

µ

P INTERFACE

4

1

V

DD

7

LE

8

Q

OUT

Q

PERFORMANCE:

COMPARATOR RESPONSE TIME: 10ns

DAC SETTLING TIME: 25

µ s

SUPPLY CURRENT: ACTIVE, 6.5mA

SHUTDOWN, 50

µ

A

OPERATING VOLTAGE RANGE: +4.5V to +5.5V

Figure 5. Because the comparator is stable in its linear region, this high-speed, 12-bit amplitude digitizer can handle slow-moving input voltages without oscillation.

it also causes the threshold value to change with output state. That behavior is acceptable if the system can compensate for state-dependent hysteresis; otherwise hysteresis should be avoided.

If the comparator to be used has internal hysteresis that cannot be disabled, you can eliminate any negative effect by ensuring that the DAC output always approaches the comparator threshold from the same direction. That action is easily established by setting the DAC to zero after each bit test; i.e., by adding one line to the pseudo-code listing at the end of this article (see sidebar, Successive

Approximation).

As another option, you can often eliminate the need for hysteresis by adding a small amount of capacitive feedback, which provides speedup in the comparator’s linear-transition region. Or, you can add an output flipflop or latch to capture the comparator’s output state at a given instant of time.

Modern comparators are better able to handle input signals that have a limited slew rate. The MAX913 and

MAX912 from Maxim, for example, are particularly effective in this respect because they are actually stable in their linear regions. Figure 5 illustrates the MAX913’s performance in a high-speed, 12-bit application. As another DAC/comparator example, the Figure 6 circuit

(an ultra-low-power 8-bit converter) conserves power by turning itself off when not in use.

Applications

This section presents a number of situations in which a

DAC/comparator approach offers advantages over the ADC approach. The application circuits discussed are neither unusual nor esoteric, but address common problems that arise frequently.

First, consider the need for a low-cost method to detect and log the sags, surges, and transients that occur on a power line. An ideal design would be a wall-cube device that detects power-line abnormalities and logs the time of each occurrence to RAM. (Sags and surges can last from milliseconds to hours; transients are as short as 10 microseconds.) The monitor must log the duration of complete failures in line power, so the monitor power should come from a battery.

The conventional solution to this problem is a controller and

ADC converter. As the converter continually samples the line voltage, the controller compares each value to usersettable limits stored in software, and logs any out-of-spec condition to RAM. Because the system must be capable of tracking transients as brief as 10µs, the ADC sample interval must be considerably shorter—perhaps 2.5µs maximum as a conservative estimate. The controller must therefore process the samples at 1/2.5µs = 400ksps.

If software comparisons can be coded efficiently and the

ADC requires no processor intervention, this system can operate with as few as ten instructions per sample,

6

3

1

DIN

SCLK

µ

P SERIAL

INTERFACE (SPI)

2 12

CS REFAB

DAC

LATCH

A

11

REFC

15pF

1000pF

6

OUT

8

COMP

MAX872

OUTA 8

DAC A

GND

4

IN

2

0.05

µ

F

OUTB 9

0.1

µ

F

SUPERTEX

TP0606

2 DACs

AVAILABLE

DAC

LATCH

B

DAC B 0.1

µ

F

DAC

LATCH

C

DAC C

MAX512

OUTC

10

L

OUT

14

100pF

V

DD

V

DD

0.1

µ

F

MAX941

2

3

V

SS

6

5

LE

7

SHDN

4

SHUTDOWN

CONTROL

PERFORMANCE:

COMPARATOR RESPONSE TIME: 75ns

DAC SETTLING TIME: 35

µ s

SUPPLY CURRENT: ACTIVE, 1.6mA

SHUTDOWN, 30

µ

A

OPERATING VOLTAGE RANGE: +2.7V to +5.5V

V

IN

> V

DAC

OUTPUT

LATCH

RESET

4

0.22

µ

F

V

5

DD

V

DD

2.7V to 5.5V

7

V

SS

0.22

µ

F

GND

6

V

IN

0V to 2.5V

Figure 6. This low-voltage, 8-bit digitizer offers several advantages over the ADC alternative: low cost, low power consumption, and between-sample shutdown capability.

requiring processor performance in the 4 MIPS range.

Such performance is substantial, and is not readily compatible with battery operation (Figure 1). You might then consider an analog method that responds to the derivative of an input transient instead of tracking it, but that approach appears untenable.

The alternate DAC/comparator approach in this case offers several significant advantages. It requires four DACs and four comparators (or a single MAX516), followed by a quad set/reset flip-flop. One DAC/comparator/FF combination monitors high transients, one monitors low transients, one is for sags, and one is for surges (Figure 2).

Transient voltages couple directly to the comparators, but the input to the sag and surge comparators is first rectified and filtered to obtain the average value of line voltage.

Appropriate rms adjustments can be made in software.

The system operates by sampling and resetting the flipflops every T seconds, where T is the time resolution required in the transient log (perhaps 60 seconds). DACs for the high and low transient levels are set to the desired high and low threshold values. The sag and surge DACs are adjusted after each T-second interval, using a successive-approximation technique to generate high-line and low-line limits that track the current average value.

Assuming a very conservative 1000-instruction routine to perform this successive approximation and the other housekeeping chores, the average CPU performance for T

= 60s is 17 instructions per second. The resulting execution rate is 0.00002 MIPS—quite suitable for lowpower systems, and far below the 4 MIPS required with an ADC approach. For further power savings the controller can “sleep” most of the time, waking only to process an abnormal line condition. The circuit thus reduces power, complexity, and cost by offloading the voltage comparison from software to analog hardware.

Low-maintenance fault detection and diagnostics

Printer-head control, carriage control, and many other electromechanical applications monitor critical internal voltages and temperatures to determine when to modify their operating mode. In extreme cases, this feedback enables the system to avoid self-destruction by shutting down altogether. For example, a stepper-motor controller must adjust gate drive to the output MOSFETs when necessary to avoid the excessive power dissipation associated with linear operation.

Again, the conventional solution to these monitoring problems is an ADC (Figure 7a). The processor directs the ADC to make periodic measurements consistent with the time constant of the process under control. It then scales the resulting digitized values and compares them with limits in software. If they go out of bounds, it can trigger corrective action or shut down the system completely.

7

(a)

T

TEMP.

SENSOR

ADC

REF

µ

P

SHUTDOWN ACTION

(b)

T

TEMP.

SENSOR

+

DAC

REF

SHUTDOWN ACTION

µ

P

µ

P PROCESSOR OVERHEAD

1. START CONVERSION

2. WAIT CONVERSION FINISH

3. INPUT A/D VALUE

4. SUBTRACT LIMIT VALUE

5. INPUT > LIMIT VALUE?

6. OUTPUT SHUTDOWN COMMAND

µ

P PROCESSOR OVERHEAD

1. WRITE LIMIT VALUE TO DAC

Figure 7. In this case, replacing an ADC (a) with a DAC and comparator (b) lowers system cost, response time, and software overhead.

An alternate approach uses the DAC/comparator combination (Figure 7b). The static DAC output establishes a shutdown limit or trip value for the comparator. When a temperature change causes the comparator to trip, the comparator sends an interrupt to the processor that initiates corrective action. If necessary, the processor can also determine the absolute temperature value by initiating a software-based successive-approximation routine.

On the other hand, to support an ADC the processor must poll the ADC, input the sample value, and compare it with the setpoint before jumping to the shutdown routine.

Thus, a DAC/comparator not only saves cost and offers a quicker response than does an ADC; it also reduces the processor overhead.

Time-domain reflectometry

Finally, the low cost and low power dissipation of

DAC/comparator combinations (vs. ADCs) has made practical the portable time-domain reflectometer

(TDR)—an instrument that detects cable discontinuities and measures the intervening transmission length.

Portable, inexpensive TDRs have become popular with the proliferation of network cabling.

A TDR operates like radar; it sends a brief pulse along the line and detects any echo returned by an open, short, or other abrupt discontinuity in the line impedance. The time interval for propagation of the outward-bound pulse and its returning reflection is about 3.3ns per foot, assuming a line propagation of 0.6c (six tenths the speed of light). Thus, a 10ns timing resolution in the electronics gives a resolution in distance to the discontinuity of approximately 3 feet.

The ratio of received-pulse amplitude to transmittedpulse amplitude is used to compute the reflection coefficient. Knowing the reflection coefficient and cable impedance you can compute the impedance of the discontinuity, and from that information deduce the nature of the discontinuity. Coaxial cables introduce a complication by attenuating the pulse on its return trip, so the software must compensate for this effect by applying an amplitude correction based on the distance measurement.

An ADC in this application would have to convert every

5ns (200Msps). Though available, such ADCs are expensive, power hungry, and generally unsuitable for portable applications.

The analog front end of an actual hand-held TDR

(Figure 8) serves to illustrate the ideas described above.

Digital circuitry is excluded for clarity. Though simple and without exotic components, this circuit has impressive performance. It measures termination impedance reliably and with 5% accuracy for cable lengths to 500 feet. For open or shorted terminations, it measures distances to 2000 feet. And best of all, the system

(including display and digital circuitry) can operate for

20 hours on a 9V alkaline battery.

The comparator in Figure 8 (IC3) provides single-supply operation with ground sensing and a propagation delay of just 10ns. The DAC (IC4) is a dual device in which one side helps with the pulse-height measurement and the other drives the LCD contrast control (as in Figure 3).

Note that the DACs are driven backwards; the (normal) current outputs are driven together by a buffered reference, and the (normal) reference inputs serve as voltage outputs (each buffered by an external op amp).

A simple glitch-monostable circuit (not shown) drives the base of Q1, which in turn drives the cable with positive, 10ns-duration pulses. Any reflections from the line are coupled to the comparator via C3.

IC5 is a bandgap reference whose 1.2V output is buffered by op amp IC2d to provide a reference voltage for the dual DACs in IC4. This reference voltage is also doubled by the gain-of-2 amplifier IC2c to provide a 2.5V dc level at the comparator’s noninverting input. DAC A applies 0V to 3.8V at the comparator’s inverting input.

Levels above 2.5V enable the determination of positivegoing pulse heights, and levels below 2.5V determine the amplitude of negative-going pulses.

8

TRANSMIT PULSE INPUT

TERM RELAY DRIVE

DIGITAL

CIRCUITS

POSITIVE PULSE

OUTPUT

DELAY GENERATOR

INPUT

NEGATIVE PULSE

OUTPUT

FLIP-FLOP RESET

LCD CONTRAST

C2

0.05

µ

F

R8

V

CC

R1

470

Q1

2N4957

LINE DRIVER

C1

0.05

µ

F

47

RELAY

5

6

9

8

8

Q

Q

V

CC

4

IC1a

74AC74

PR 2

D

3

CL

CLK

1

Q

Q

V

CC

10

IC1b

74AC74

PR 12

D

11

CL

CLK

13

9

10

R3

75

IC2a

K1

RLY R6

1k

C3

0.05

µ

F

R2

50

TERMINATION

IC3

MAX913

8

7

5

V

CC

1

4

2

3

R4

1k

C6

0.1µF

R11

C4

0.05

µ

F

1k

7

COMP

TRESHOLD

15k

13

R7

14

1k

R12

REFERENCE x2

RCVR QUIESCENT

IC2b

220k

MAX479

6

12

5

R9

R13

100k

MAX479

10

9

8

7

14

13

12

11

DB0

DB1

DB2

DB3

DB4

DB5

DB6

DB7

IC4

MX7528

RFBA

VRA

OUTA

RFBB

3

4

2

19

15

6

16

CS

A/D

WR

8-BIT DUAL DAC

VRB

18

20

OUTB

IC2c

MAX479

R10

15k

J1

BNC

TO

TRANSMISSION

LINE UNDER TEST,

50

OR 75

1

V

CC

4

IC2d

MAX479

3

11

2

IC5

D1

ICL8069

V

CC

R5

10k

BUFFERED

REFERENCE

C5

0.05

µ

F

Figure 8. This circuit—the analog section of a time-domain reflectometer—relies on a DAC/comparator in place of an ADC.

Each pulse entering the transmission line also enters a variable delay line in the digital circuitry, which consists of a string of 20ns delay elements controlled by a counter.

This delayed pulse from the digital section jointly drives the D inputs of two flip-flops (IC1a and IC1b), which in turn are clocked by complementary TTL outputs from the comparator. Thus, time measurements amount to a race between the return pulse and the pulse going through the delay line: if the D input arrives before a clock transition the flip-flop output is high; otherwise it is zero.

To measure, set the DAC output to a low absolute level and iteratively adjust the delay until the flip-flop output remains at zero, then read the counter. Similarly, to measure the height of return pulses, iteratively adjust the

DAC output until the flip-flop output remains at zero, then read the DAC. Note that two flip-flops are required to capture the comparator’s leading edge for both positive and negative pulses. This leading edge rises for positive pulses and falls for negative pulses; if both were applied to a single flip-flop, the pulse width would become an unwanted part of the delay.

References:

1. Edward Jordan, Reference Data for Engineers, 7th

Edition, (Howard Sams, 1989).

2. Brian Kenner and John Wettroth, The Design of a

Time-Domain Reflectometer, (Computer Applications

Journal #29, October/November 1992).

3. Paul Horowitz and Winfield Hill, The Art of

Electronics, 2nd Edition, (Cambridge University

Press, 1989).

(Circle 1)

9

DESIGN SHOWCASE

PC serial port drives 12-bit A/D converter

The Figure 1 circuit performs a task usually done by a microcontroller—that of driving a 12-bit A/D converter (ADC) from the serial port of a PC. Power consumption is low: the 2mA operating current drops to only 15µA in shutdown.

Interface to the PC is an RS-232 port rather than the transmitter/receiver lines of a UART. The port’s

Request to Send line (RTS) provides a chip-select signal, and its Data Terminal Ready line (DTR) provides a synchronous-clock signal. A single-supply

RS-232 interface chip (IC1) converts these signals from RS-232 levels to CMOS-logic levels (and inverts them in the process). Conversion data appears on the Data Set Ready line (DSR).

D1

1N4148

BT1

9V

C1

35

µ

F

C2

0.1

µ

F

Q1

VN10K

R2

100k

D2

1N4148

R4

100k

5

8

3

V

IN

LBI

SHDN

IC2

MAX666

V

OUT

1

2

SNS

V

SET

6

7

LBO

GND

4

R1

1M

C3

0.1

µ

F

R3

10k

IC3 is an 8-pin DIP that includes a 12-bit ADC, voltage reference, track/hold, serial interface, and clock generator, plus a 3-wire digital interface consisting of Chip Select (

CS), Serial Clock (SCLK), and Data Out (DOUT). Conversions are initiated by a high-to-low transition on

CS, and take less than

8.5µs. The end of conversion, indicated by a high level on DOUT, leaves the 12-bit result stored in the converter’s output shift register. The PC reads this result by clocking DTR while sampling DSR 12 times.

As a low-power version of the venerable (10mA)

MAX232, the MAX220 draws only 0.5mA. If power is not a concern, either device is suitable for levelshifting the converter’s SCLK, DOUT, and

CS signals to RS-232 levels. Power is supplied by a 9V battery via the linear regulator (IC2), whose output capacity is 40mA. This circuit draws only 2mA, so the extra capacity is available for powering an external sensor or amplifier.

When DTR is high, Q1 turns on and allows the circuit to operate normally. Charge on C3 allows Q1 to remain on during DTR’s brief negative clock pulses.

When DTR goes low for more than 100ms, C3 discharges and turns Q1 off, allowing IC2 to enter shutdown. For that condition the circuit’s supply current is essentially that of IC2—15µA maximum and 5µA typical.

TO PC

SERIAL

PORT

D8–D9

CONN

DTR

4

DSR

6

7

RTS

5

GND

C7

10

µ

F

C5

10

µ

F

N.C.

2

V+

4

C2+

16

V

CC

IC1

6

V-

C1+

1

MAX220

5

C2-

13

14

T1OUT

8

R1IN

R2IN

7

T2OUT

GND

15

C1-

R1OUT

T1IN

R2OUT

T2IN

3

12

11

9

10

C6

10

µ

F

N.C.

C4

10

µ

F

8

6

7

1

V

DD

SCLK

IC3

DOUT

MAX187

SHDN

3

2

AIN

4

CS REF

5

GND

C8

4.7

µ

F

C9

4.7

µ

F

R5

10k

C11

0.1

µ

F

Figure 1. This micropower circuit enables a PC’s RS-232 serial port to control a 12-bit A/D converter (IC3).

C10

0.1

µ

F

INPUT

VOLTAGE

0V to 4.096V

10

INVERTED 12-BITS

DTR

100ms

V

CC

RTS

INVERTED CS

WAKE/WAIT

START

CONVERT CLOCK RESULT DTR

(100ms)

LOW SLEEP

Figure 2. Timing Relationships for Figure 1.

The circuit is controlled by a simple C routine on the

PC (request EJ22 Listing from Maxim Customer

Service). The code drives DTR high to wake the converter, then starts a conversion, waits for completion, clocks out the data, displays the data, and puts the circuit back to sleep. You can then quit by pressing “Q”, or trigger another conversion by pressing any key. The software is easily modified for particular applications.

(Circle 2)

11

DESIGN SHOWCASE

PFM control improves dual-output step-up converter

V

IN

2V TO 12V

A discrete-component external charge pump enables the PFM-controlled dc-dc converter of Figure 1 to generate dual outputs with moderate regulation and high efficiency. The circuit accepts input voltages between 2V and 12V (typically 5V) and delivers simultaneous 0mA to 100mA outputs at ±12V

(Figure 2). Efficiencies range between 80% and

90%.

IC1 regulates 12V via its V+ terminal, but the -12V output has no direct feedback connection.

Nevertheless, changes in -12V load current are coupled via “flying capacitor” C1, where they affect the switching frequency just as 12V load changes do—via current-limited, minimum-off-time, pulsefrequency modulation of the chip’s internal switching MOSFET. The resulting pseudo-regulation is impressive: a load change of 10mA to 100mA at either output causes only a 4% change in the negative output (from -11.36V to -10.96V).

(Circle 3)

14.0

13.5

13.0

12.5

12.0

11.5

11.0

10.5

10.0

0

C1

33

µ

F

1

LBO

2

LBI

3

FB

4

SHDN

IC1

MAX761

V+

LX

GND

REF

8

7

6

5

C2

0.1

µ

F

C3

10

µ

F

L1

18

µ

H

(SUMIDA CD54-180)

D2

1N5817

+12V @

100mA

D3

1N5817

C4

33

µ

F

-12V @

100mA

D1

1N5817

C5

10

µ

F

Figure 1. An external charge pump (C3, C5, D1, and D3) enables this dc-dc step-up converter to generate ±12V dual outputs.

MAX761 ±12V APPLICATION

-12V UNLOADED

-12V LOADED

(UP TO 100mA)

20 40 60 80

LOAD (mA) ON +12V SIDE

100 120

Figure 2. “Pseudoregulation” stabilizes the -12V output in Figure 1.

12

DESIGN SHOWCASE

Synchronous buck-regulator output terminates high-speed data buses

The limitations of today’s 5V and 3.3V CMOS buses are causing a proliferation of high-speed, lowvoltage buses for the next generation of computers.

These new buses—Futurebus, RAMBUS, and GTL

(Gunning Transceiver Logic), for example—require low supply rails to reduce signal-voltage swings.

Others, such as HSTL and CTT (Center Terminated

Transceiver) are also center-terminated and therefore require a power source that can sink current as well as source it.

The termination supply for an HSTL or CTT bus must generate an output of about 0.75V, capable of sourcing and sinking current into a bunch of 50

Ω terminating resistors. Designing such supplies can be a headache for two reasons. First, the headroom needed by an emitter-follower pass element in a linear regulator makes it difficult to sink current at such a low voltage. Second, 0.75V is below the magic 1.25V level produced by bandgap circuits as a feedback reference in most linear and switch-mode power-supply ICs.

An efficient, synchronous buck regulator (Figure 1) avoids both of these problems. Sink capability at low voltage is accomplished by the use of a synchronous switch (Q2) and by allowing the inductor current to reverse. IC1 includes current-limiting circuitry that prevents inductor-current reversals (as do most buckregulator ICs), but it also includes a logic input

(

SKIP) that lets you disable that circuitry.

In noise-sensitive wireless applications, pulling

SKIP high forces the inductor current to be continuous, thereby avoiding the ringing associated with an otherwise discontinuous inductor current. In this circuit, pulling

SKIP high allows current to flow from the circuit output back into the inductor and through the synchronous switch to ground.

The other problem—that of regulating an output level below the 1.25V bandgap threshold—is overcome by dividing down the reference voltage and feeding it to an external integrator amplifier

(IC2). Summing this reduced reference with a directly coupled feedback signal ensures an excellent transient response, and produces an integrated feedback signal that feeds directly into the IC’s main high-speed PFM comparator.

Current sunk by the output doesn’t flow directly to ground as it would in a linear-regulator termination supply. Instead, the buck topology works in reverse and becomes a boost topology, producing a net positive current flow into the 5V supply. In most systems, this excess current is absorbed by the numerous other 5V loads.

(Circle 4)

13

INPUT

4.75V

TO 5.5V

ON/OFF

C6

0.01

µ

F

0.1

µ

F

SHDN

SS

V+

VL SKIP

BST

DH

LX

IC1

MAX797

DL

PGND

CSH

CSL

FB

SYNC

REF

D1

C3

0.1

µ

F

Q1

Q2

4.7

µ

F

L1

4.7

µ

H

D2

1N5820

C7

330pF

C1

220

µ

F

(OS-CON)

R1

20m

R5

150k

R6

49.9k

R7

124k

C2

2 x 220

µ

F

(OS-CON)

0.75V OUTPUT

AT 3A

GND

C5

0.33

µ

F

R3

232k

1%

R4

100k

1%

TO

VL

IC2

MAX495

REMOTE SENSE LINE

Q1 = Q2 = Si9410DY

Figure 1. Modifications to a conventional buck-regulator circuit produce a 0.75V, 3A output with sink/source capabilities, useful as a termination supply for high-speed data buses.

14

DESIGN SHOWCASE

Autotransformer regulator inverts 12V to -12V

In Figure 1, a dc-dc regulator with internal switching

MOSFET inverts 12V to produce an output of

200mA at -12V. The IC is a high-efficiency device whose low quiescent current (120µA maximum) is achieved with a CMOS process that limits the absolute maximum voltage to 21V (input to output).

Thus, to avoid 24V across its terminals, the IC must isolate itself from the inductor-flyback voltage by driving either an external switch in a non-bootstrapped configuration, or an internal switch in a flyback-transformer configuration.

Autotransformer T1 (a center-tapped inductor with

1:1 turns ratio) offers a design alternative. In the circuit shown, LX flies back to

1

2

V

OUT plus a diode drop, or approximately -6V. V+ remains at 12V, producing an 18V maximum between V+ and LX that is well within the 21V limit.

Because IC1 drives the gate of its internal MOSFET between the V+ and OUT voltages, you normally connect OUT to V

OUT to ensure sufficient gate drive

(in a typical application, the chip inverts 5V to -5V).

In this circuit the 12V input provides adequate gate drive, so OUT is connected to ground.

(Circle 5)

ON/OFF

+12V

C1

68

µ

F

(OS-CON)

3

SHDN

V+

7, 6

REF

4

IC1

MAX764

FB

2

LX

8

4

1

3

R1

15k

R2

C2

0.1

µ

F

120k

D1

1N5817

T1

CTX50-4

(COILTRONICS)

-12V @

C3

68

µ

F

(OS-CON)

200mA

GND

5

OUT

1 2

Figure 1. Autotransformer T1 limits the voltage across IC1, allowing use of a high-efficiency chip (with 21V absolute-maximum voltage) in this inverting dc-dc regulator.

15

DESIGN SHOWCASE

Serial-data interface chip supplies bipolar voltages

Some of the interface ICs currently available for serial-data transmission not only operate from low

V

CC levels (5V or 3.3V); they also generate bipolar dc voltages (±6.5V to ±10V) to support the minimum driver-output levels as specified by EIA/TIA-232.

With care, you can steal useful amounts of power from these voltage rails without interfering with the IC’s operation.

In Figure 1, the IC’s switch-mode controller operates with an external inductor, two diodes, and two capacitors to produce ±6.5V. FETs Q1 and Q2 ensure startup for the circuit by disconnecting the load until these switch-mode supply voltages are present. Note that Q1 must be a logic-level device.

Unlike ICs designed to generate supply voltages, an interface IC generally doesn’t specify how much current you can draw from its internally generated supply rails.

The amount available depends almost entirely on loads connected to the driver outputs. IC1, for example, guarantees that one transmitter can drive a parallel combination of 3k

Ω and 1000pF at 250kbps while the other two maintain dc outputs across 3k

Ω loads. These conditions let you calculate the chip’s maximum output current capability, but you can’t expect to draw extra current while delivering that maximum.

To calculate the maximum output current available, superimpose the ac and dc components: Output current flows alternately from each rail as the NRZ output waveform swings between the guaranteed minimum output levels (±5V). Assuming the output requires one whole data period (4µs at 250kbps) to slew from -5V to

+5V, the ac component equals C

LOAD

(dv/dt) =

1000pF(10V/4µs) = 2.5mA. For the dc component,

Ohm’s Law gives I = E/R = 5V/3k

= 1.67mA from one transmitter, so the three transmitters together represent a dc load of 5mA. Adding the ac and dc components together gives a conservative maximum rating of 2.5mA + 5mA = 7.5mA.

The 3k

Ω load is an EIA-232 requirement, but the data rate and load capacitance are application-dependent

2.7V

0.33

µ

F

3

9

10

11

12

7

4

13

14

15

8

26

25

5

6

FORCEON

FORCEOFF

TRAN

INVALID

T1IN

T2IN

T3IN

R1OUT

R2OUT

R3OUT

R4OUT

R5OUT

R5OUTB

EN

V

CC

0.68

µ

F

27

V+

MMBD6050

1

LN

15

µ

H

IC1

MAX3212

~

6.5V

LOAD

Q1

TP0610L

Q2

2N7000

0.33

µ

F

2

LP

MMBD6050

16

V-

~

-6.5V

T1OUT

T2OUT

T3OUT

19

18

17

R1IN

R2IN

R3IN

R4IN

R5IN

24

23

22

21

20

Figure 1. For data rates and driver-output loads less than the maximum allowed, the V+ and V- outputs of this serialinterface IC can supply modest amounts of current to an external circuit.

parameters. Lower values for these parameters make more current available for external use. A remotesensing system, for instance, might operate at 2400 bits/sec (2400bps) with a load of 3k

Ω in parallel with

1000pF (50 feet of cable at 20pF/ft). The dc load for three transmitters is 5mA, and the ac load for one transmitter (72µA) is almost negligible in this low-data-rate application. So, the available current in this case is calculated as 7.5mA - (5mA + 72µA) = 2.428mA.

The above calculation is conservative: with V

CC

=

2.7V and the three transmitters loaded with

3k

||

1000pF, a circuit transmitting valid EIA-232 levels at 2400bps will actually deliver 6.7mA to an external load (even more for V

CC

= 3V and up). As mentioned, Q1 and Q2 enable the circuit to start under these conditions. If you disconnect the transmitter loads, the maximum external load current that allows start-up is 11.5mA. With Q1 and Q2 removed, the maximum is only 5.7mA.

(Circle 6)

16

DESIGN SHOWCASE

Programmable current source delivers 0A to 5A

The variable current source of Figure 1 generates 0A to 5A with a compliance range of 4V to 30V. It offers two advantages: the 12-bit D/A converter

(IC2) makes it digitally programmable, and the switch-mode step-down regulator (IC1) is more efficient than the alternative current source with linear pass transistor. Applications include battery charging and dc motor control.

IC3 is a high-side, current-sense amplifier normally used in battery-powered systems to detect charge and discharge currents without disturbing the ground path. In this circuit, it senses output current as a voltage drop across R5, and produces a proportional signal current at OUT (pin 8) Thus, the regulator’s feedback voltage (pin 1 of IC1) is set by the DAC and modified by IC3’s current feedback, which flows across the parallel combination of R2 and R3. This current feedback opposes any change in load current due to a change in load resistance.

The DAC generates 0V to 10V, producing a source current that varies inversely with code:

FFF

HEX

(10V from IC2) produces 0mA, and 000

HEX

(0V from IC2) produces 5A. For a given programmed level the actual output varies somewhat with load resistance and the corresponding compliance voltage. When tested at 1.5A, for instance, the output of the circuit deviated about +15mA (from

1.5A) for compliance voltages between 10V and 20V

(Figure 2).

You can reconfigure the circuit for other ranges of output current (I

SOURCE

) by resizing R2 and R3:

2217[V

FB

(R2 + R3) - R3V

DAC

]

I

SOURCE

= ————————————— ,

R2R3 where V

FB

10V.

= 2.21V and V

DAC can range from 0V to

The desired range for I

SOURCE and R3: V

DAC defines values for R2

= 10V for the low value of I

SOURCE

, and V

DAC

= 0V for the high value of I

SOURCE

Substituting these two sets of values in the equation

.

yields two equations, to be solved simultaneously for the values of R2 and R3.

(Circle 7)

17

0.3V

10

µ

A

2.45V

SHUT

IC1

MAX724

µ

POWER

SHUTDOWN

CIRCUIT

BIAS

2.21V

REF

CURRENT-LIMIT

SHUTDOWN

1 FB

2 V

C

ERROR

AMPLIFIER

PWM

CONTROLLER

100kHz

OSC

GND

POWER TO

ENTIRE CIRCUIT

V

0.04

36V

5

V

IN

I

LIM

C2

220

µ

F

V

SW

4

D1

MBR745

(MOTOROLA)

L1

47

µ

H

7230-09

C3

470

µ

F

R1

2.7k

C1

0.1

µ

F

12V

22

V

DD

3

REFOUT

2

R

OFS

4

AGND

18 CS

19

WR

20 LDAC

CONTROL

LOGIC

V

REF

DAC

DAC LATCH

17

INPUT LATCH

DO . . D11

5

R

FB

23

V

OUT 24

V

SS

1

IC2

MAX507

DGND

12

CLR 21

Figure 1. This programmable current source generates 0A to 5A, with 12-bit resolution and a compliance range of 4V to

30V.

R2

R3

Q1

IC3

MAX472

3

R4

66.5

1%

R5

30m

A1 A2

R6

66.5

6

1%

0A TO 5A

Q2

V

CC

7

OUT 8

36V

COMP

SIGN 5

50

40

30

20

10

COMPLIANCE

I

SOURCE

= 1.5A

0

0 5 10 15 20 25

OUTPUT VOLTAGE (V)

30 35

Figure 2. For a programmed level of 1.5A, the output current in

Figure 1 deviates with output (compliance) voltage as shown.

18

Ultra-low-power, open-drain, comparator-plus-

N

EW PRODUCT

S

Open-drain outputs enable all comparators to implement wire-OR configurations.

By giving access to the output transistor’s source terminal (GND) as well, the

MAX971/MAX974/MAX981/MAX984 devices easily implement level translators

reference ICs draw only 4µA

and bipolar to single-ended converters. For standard complementary CMOS output

The MAX971–MAX974 and

MAX981–MAX984 single/dual/quad stages, consider these otherwise-similar families: MAX921–MAX924 (with ±1%

350MHz voltagefeedback op amp has 1300V/µs slew rate

The MAX477 is a fast, unity-gainstable op amp whose standard voltagefeedback topology allows all the gain configurations common to general-purpose op amps. Its unique input stage, however, comparator-plus-reference families offer the lowest power consumption available: references) and MAX931–MAX934 (with

±2% references).

less than 4µA over the extended temperature range for MAX971, MAX972, and lets it combine the advantages of current feedback (high slew rate and a large full-

MAX974 and MAX984 devices come in 16-pin DIP and narrow SO packages; all power bandwidth) with those of voltage feedback (low input offset voltage, low

MAX981 devices operating with a 5V supply. All devices operate from 2.5V to others come in 8-pin DIP, SO, and µMAX packages. The MAX98x family offers

11V, or with dual supplies of ±1.25V to

±5.5V. Input voltages may range from the input bias current, low current and voltage noise, and two high-impedance inputs).

versions tested for the commercial (0°C to

+70°C) and extended-industrial (-40°C to negative supply rail to within 1.3V of the positive rail.

All but the MAX972 include 1.182V

bandgap references: the MAX971/

+85°C) temperature ranges; the MAX97x family offers military (-55°C to +125°C) versions as well.

(Circle 8)

The MAX477 has a fast slew rate of

1300V/µs and is ideally suited for driving

50

Ω and 75

Ω loads. At unity gain, it has a small-signal bandwidth of 350MHz and a full-power bandwidth of 170MHz.

MAX973/MAX974 have ±1% references, and the MAX981–MAX984 have ±2%

INTER.

REF

INTER.

HYST

PRICE

$

DEVICE

In addition to high speed, the MAX477’s precision makes it suitable for use in references. Further, the MAX983

(hardwired for window-detector applica-

MAX971 Single 1% Yes 1.50

tions) and the MAX971/MAX973/

MAX981/MAX982 let you add hysteresis

MAX972 Dual

MAX973 Dual

None

1%

No

Yes

0.98

1.95

broadcast and high-definition TV systems, in video switching and routing applications, and as a preamplifier for flash A/D without recourse to feedback or complicated equations—by connecting two

MAX974 Quad

MAX981 Single

1%

2%

No

Yes

2.25

0.98

converters. Precision specifications include

2µA input bias current, 65dB open-loop gain, external resistors to the HYST input. The resulting hysteresis is independent of supply voltage and has no effect on high-Z inputs.

MAX982 Dual

MAX983 Dual

MAX984 Quad

2%

2%

2%

Yes

Yes

No

1.26

1.26

1.31

0.1dB gain flatness to 100MHz, low differential phase/gain errors of 0.01°/0.01%, and voltage/current noise densities of 5nV/

√ and 2pA/

Hz

, respectively.

Hz

275MHz quad video buffers drive

50

and 75

cables

The MAX496 and MAX497 are closedloop, quad video buffers optimized for driving 50

Ω and 75

Ω back-terminated cables directly. The MAX496 has a fixed gain of

1V/V (0dB), and the MAX497 has a fixed gain of 2V/V (6dB). The MAX496 features a

1550V/µs slew rate and a small-signal, -3dB

† 1000 up, FOB USA bandwidth of 375MHz; the MAX497 features a 1450V/µs slew rate and a smallsignal, -3dB bandwidth of 275MHz. Along with low differential gain and phase errors

(0.01% and 0.01°), this high-speed performance suits the buffers for broadcast-quality composite video, all component-video applications (multimedia, medical imaging graphics), and general high-speed signal processing.

The MAX477 comes in 8-pin DIP, SO, and µMAX packages, in versions tested for the extended-industrial (-40°C to +85°C) and military (-55°C to +125°C) temperature ranges. Prices start at $2.40 (1000 up,

FOB USA).

(Circle 9)

8

MAX496/MAX497 buffers operate on

±5V and draw only 8mA (typical) per channel. Gain flatness to within ±0.1dB

extends to 80MHz for the MAX496 and to

120MHz for the MAX497. High-speed performance is maximized by low channel input capacitance (2pF), which lets

MAX496/MAX497 buffers settle to 0.1% in only 14ns. To further minimize crosstalk and simplify board layout, the input channels are located on non-adjacent package pins.

6

4

MAX497

V

S

= ±5V, R

L

= 150

A

V

= +2

75

75

MAX497

75

2

0

-2

-4

-6

-8

-10

MAX496

V

S

= ±5V, R

L

= 150

A

V

= +2

A

V

= +2

A

V

= +2

75

75

75

75

75

Available in 16-pin plastic DIP and narrow-SO packages, the MAX496 and

MAX497 are screened for the commercial

(0°C to +70°C) temperature range. Prices start at $4.95 (1000 up, FOB USA).

(Circle 10)

0.1M

1M 10M

FREQUENCY (Hz, Log)

100M 1G

QUAD, +2 GAIN

19

Op-amp family provides low noise and ultra-low distortion

N

EW PRODUCT

S

MAX4106–MAX4109 op amps

500MHz, currentfeedback video amplifiers draw

5mA and deliver

80mA out

and both are well suited for high-performance pulse, RF, and video applications.

MAX4112/MAX4113 op amps come in 8-pin SO packages, tested for the extended-industrial (-40°C to +85°C) temperature range. Prices start at $1.95

(1000 up, FOB USA).

constitute a new family of high-speed, voltage-feedback devices that are unprece-

The MAX4112 and MAX4113 video amplifiers employ current-mode feedback to achieve very high slew rates and gain-

(Circle 12)

dented for their low levels of distortion and noise. Available in 8-pin SO packages, they operate on ±5V and deliver up to

90mA from ±3.5V output swings.

The MAX4106/MAX4107 are useful in ultra-low-noise ADC preamps, ultrabandwidth products. The MAX4112, stable for closed-loop gains (A

VCL

) of two or more, slews at 1200V/µs and has a -3dB bandwidth of 500MHz at A

VCL

= 2. Its full-power bandwidth is 300MHz at V

OUT

= 2Vp-p.

sound applications, and high-performance receivers. Their compensation for closedloop gain yields a minimum of 5V/V for the MAX4106 and 10V/V for the

The MAX4113 has a -3dB bandwidth of 275MHz and is stable for A

VCL

= 8 or more. Its full-power bandwidth at V

OUT

=

2Vp-p is 250MHz, and its slew rate is

MAX4107. They combine high speed

(350MHz for the MAX4106, 300MHz for

1800V/µs. Both devices specify 0.01°/

0.01% for differential phase and gain error, the MAX4107) with very low voltage noise (0.75nV

Hz

). Their spurious-free dynamic range (SFDR) at 5MHz, with

V

OUT

= 2Vp-p, is -63dBc for the

MAX4106 (at 5V/V) and -60dBc for the

MAX4107 (at 10V/V). Slew rates are

Quad, SPST analog switches offer 10

on-resistance

275V/µs (MAX4106) and 500V/ µs

(MAX4107).

M A X 3 1 2 / M A X 3 1 3 / M A X 3 1 4 switches come in 16-pin DIP and narrow-

SO packages, in versions tested for the commercial (0°C to +70°C), extendedindustrial (-40°C to +85°C), and military

(-55°C to +125°C) temperature ranges.

The MAX4108/MAX4109 op amps combine high speed with extremely low distortion, making them suitable for use in RGB and composite video, ADC preamps, and high-performance RF signal processing. The unity-gain-stable

MAX4108 has a 20MHz SFDR of -81dBc and a unity-gain bandwidth of 400MHz.

The MAX4109 (stable for A

VCL

= 2V/V or more) has a 20MHz SFDR of -80dBc and

The MAX312/MAX313/MAX314 are quad, single-pole/single-throw analog switches with low R

ON

(10

Ω max), R

ON variations no greater than 2

Ω over the specified signal range, and tight matching between channels (1.5

Ω max). MAX312 switches are normally closed (NC),

MAX313 switches are normally open

(NO), and the MAX314 has two NC and two NO switches.

Prices start at $2.49 (1000 up, FOB USA).

30

25

20

R

ON

vs. SIGNAL INPUT VOLTAGE

V+ = 15V

V- = -15V

DG411

(Circle 13)

a -3dB bandwidth of 225MHz. Both have

1200V/µs slew rates. For V

OUT

= 2Vp-p, the full-power bandwidths are 300MHz

(MAX4108) and 200MHz (MAX4109).

Each device operates on single (4.5V

to 30V) or dual (±4.5V to ±20V) power supplies, handles rail-to-rail signals, conducts equally well in both directions,

15

10

MAX312 and exhibits leakages of no more than

2.5nA at +85°C. Pin compatible with

The MAX4106/MAX4107 come in

8-pin SO packages, and the MAX4108/

5

DG411/DG412/DG413 devices, the

MAX312/MAX313/MAX314 guarantee

0

-15 -10 -5 0

MAX4109 come in 8-pin SO and µMAX packages. All are tested for the extended-

5 10 15

ESD protection greater than 2000V, per

Method 3015.7 of MIL-STD-883.

SIGNAL INPUT VOLTAGE (V) industrial (-40°C to +85°C) temperature range. Prices start at $3.88 (1000 up, FOB

Crosstalk at 20kHz is greater than 96dB.

USA).

(Circle 11)

20

8-channel and dual 4-channel multiplexers have serial control

N

EW PRODUCT

S as a shift register, it synchronously clocks in data (at DIN) with the rising edge of the clock (SCLK). The shift-register output

(DOUT) lets you connect several

MAX349/MAX350 multiplexers are available in 18-pin DIP, 18-pin wide-SO,

MAX349s or MAX350s together in a daisy-chain configuration. Because all and 20-pin SSOP packages, in versions tested for the commercial (0°C to +70°C), extended-industrial (-40°C to +85°C), and military (-55°C to +125°C) temperature

The MAX349 and MAX350 multiplexers (8-channel and dual 4-channel) offer serially controlled channel selection.

On-resistances are 100

Ω maximum, matched to within 16

Ω max between switches and flat to within 10

Ω max over the specified signal range. All channels conduct equally well in either direction.

digital inputs have 0.8V and 2.4V logic thresholds, the ICs ensure compatibility with TTL and CMOS logic when operating with 5V or ±5V supplies.

NO0 NO7 ranges. Prices start at $2.98 (1000 up, FOB

USA).

(Circle 14)

SCLK 1

MAX349

18 CS

Each CMOS device operates with a

±2.7V to ±8V dual supply or a 2.7V to

16V single supply. Each handles rail-torail input signals, and exhibits an offleakage current of only 0.1nA at +25°C

(5nA at +85°C). At power-up, an automatic reset opens all switches and fills all internal shift registers with zeros. Each

IC also provides an asynchronous

RESET input.

COM

DIN

RESET

SCLK

PARALLEL REGISTER AND TRANSLATOR

8-BIT SHIFT REGISTER

CLOCK TRANSLATOR

LATCH

DOUT

MAX349

V+

DIN

GND

COM

NO0

NO1

NO2

NO3

2

3

4

5

6

7

8

9

LOGIC

17

16

15

14

13

12

11

10

RESET

DOUT

V-

N.C.

NO7

NO6

NO5

NO4

The serial interface is compatible with the SPI™, QSPI™, and Microwire™ synchronous-serial standards. Functioning

CS

CS TRANSLATOR

DIP/SO

SPI and QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corp.

Complete, isolated, full-duplex RS-485/

RS-422 interface costs under $10

The MAX1490A/MAX1490B fullduplex data-communications transceivers provide an electrically isolated RS-485 or

RS-422 interface in a single package. Each fully isolated transceiver operates from a single 5V supply on the other (logic) side of the isolation barrier, and the entire circuit—including transceiver ICs, optocouplers, and transformer—fits in a 24-pin

DIP. The isolation barriers typically withstand 1600Vrms for one minute or

2000Vrms for one second.

The MAX1490A handles data rates as high as 2.5Mbps. The MAX1490B, which provides error-free transmissions to

250kbps, has slew-rate-limited drivers that minimize electromagnetic interference

(EMI) while reducing any reflections caused by improperly terminated cables.

Each driver output has short-circuit current limiting and thermal-shutdown circuitry, which prevents excessive power dissipation by placing the outputs in a high-impedance state. Each input and output meets all RS-485 and RS-422 specifications. As a fail-safe feature in response to an open-circuited input, the receivers guarantee a logic-high output state for RO.

+5V

MAX1490

TRANSFORMER

DRIVER

MAX845

V

CC

TXIN

MAX488/

MAX490

Z

Y

(The MAX1480A/MAX1480B are similar products, but offer half-duplex operation.)

The transceivers come in 24-pin wide plastic DIPs, tested for the commercial

(0°C to +70°C) and extended-industrial

(-40°C to +85°C) temperature ranges.

Prices start at $10.98 for the MAX1490A and at $10.50 for the MAX1490B (1000 up, FOB USA).

(Circle 15)

MAX1490

+5V

+5V

TO RS-485

BUS

RXOUT

V

CC

MAX488/

MAX490

B

A

IN THIS!

ISOLATION

BARRIER

ALL THIS...

21

N

EW PRODUCT

S

Low-voltage, quad, SPST analog switches offer low cost

match (with a 12V supply). MAX4066 leakage is 1nA max at +25°C.

Fully specified at 3V, 5V, and 12V, the MAX4066/MAX4066A switches

(100pA max for the MAX4066A) and low power consumption (0.5 µW) make

MAX4066/MAX4066A switches ideal for battery-operated applications. Each offers

MAX4066 and MAX4066A analog switches are designed to outperform the pin-compatible, industry-standard guarantee operation for supply voltages from 2V to 16V. At 12V, for example, both offer 45

Ω maximum on-resistance,

2

Ω channel-to-channel matching, and 4

Ω flatness over the specified signal range.

Input signals range from V+ to ground,

ESD protection beyond 2000V, per

Method 3015.7 of MIL-STD-883.

MAX4066/MAX4066A devices come in 14-pin DIPs, narrow-SO packages, and a 16-pin QSOP, in versions tested for the commercial (0°C to +70°C), extended-

74HC4066 types. MAX4066A switches

(unlike 74HC types) offer guaranteed limits for on-resistance (45

Ω with 12V supply), R

ON matching between channels

(2

Ω max), and leakage (100pA max at

+25°C). For even lower cost, the

MAX4066 offers 45

Ω max R

ON and a 4

Ω inclusive.

Each device is suitable for application as a multiplexer, demultiplexer, or bilateral switch. Channel selection is by applied

TTL/CMOS logic levels. Low off-leakage industrial (-40°C to +85°C), and military

(-55°C to +125°C) temperature ranges.

Prices start at $0.99 for the MAX4066 and at $1.87 for the MAX4066A (1000 up,

FOB USA).

(Circle 16)

Ultra-thin PCMCIA power supplies fit

Type 1 and Type 2

produces efficiencies between 80% and

90%. The output current is 60mA at 12V

(guaranteed) or 120mA at 5V.

cards

1MHz, 1.25mm-high boost converters occupy only 0.25in

2

MAX606/MAX607 dc-dc converters require less height and less pc area than any other equivalent ICs. Intended for

Type 1 and Type 2 PCMCIA cards and other low-profile applications, they stand only 1.11mm high in the 8-pin µMAX package. Their high switching frequency

(to 1.2MHz for the MAX606) enables the use of small external components that yield 1.35mm-high Type-1 circuits only

0.25in

2 in area, and slightly taller Type-2 circuits only 0.16in

2 in area.

MAX606/MAX607 devices accept input voltages between 3V and 5.5V, and produce regulated outputs of 5V or 12V according to the state of an applied logic signal. With two external resistors you can adjust the output to any level between V

IN and 12.5V. Output accuracy is guaranteed

INPUT

3.3V TO 5V

2.2

µ

F

±4%. For load currents between 2mA and

200mA, the converters’ current-limited pulsefrequency-modulated

(PFM) control scheme

ON/OFF

5V/12V OUT

Soft-Start

0.01

µ

F

SHDN

SEL

SS

The MAX606 switching frequency

(double that of the MAX607) ranges from

600kHz to 1.2MHz, depending on the input and output voltages and other operating conditions. Thus, the lowerfrequency MAX607 circuits require somewhat larger external components.

Both devices have a logic-controlled shutdown mode that saves battery life by reducing supply current to 1µA. At powerup, a user-set soft-start circuit prevents input surge currents.

A preassembled, Type-1 evaluation kit

(MAX606EVKIT-MM) is available to speed MAX606 designs. The MAX606 and MAX607 are available in 8-pin µMAX and SOIC packages, tested for the extended-industrial (-40°C to +85°C) temperature range. Prices start at $3.25

(1000 up, FOB USA).

(Circle 17)

V

CC

MAX606

MAX607

GND

LX

FB

5

µ

H

MBRO520

OUTPUT

5V ±4% at 150mA or

12V ±4% at 60mA

1

µ

F

Step-up controller generates fixed (5V) or adjustable (3V to

16.5V) outputs

The MAX608 is a low-voltage step-up controller that operates from a 1.8V to

16.5V input. Its output voltage is either fixed at 5V or (with an external resistor divider) variable from 3V to 16.5V. Noload operating current is only 85µA, or

2µA (5µA max) in the shutdown mode. For heavy loads, the regulator’s current-limited

PFM control scheme (pulse-frequency modulation) ensures high 85% efficiency from 30mA to 1.5A.

The MAX608 controller is an excellent choice for 2-cell and 3-cell battery-powered systems. Its high operating frequency (to 300kHz) allows the use of small, surface-mount external components. The MAX608 operates only in “bootstrapped” mode, with its output voltage connected to its supply terminal

(OUT). For a 12V output or for non-bootstrapped applications—in which the chip is powered by the input voltage—refer to the pin-compatible MAX1771.

An evaluation kit for the MAX608 is available as a design aid from Maxim.

MAX608s come in 8-pin plastic DIP or

SO packages, in versions tested for the commercial (0°C to +70°C) and extendedindustrial (-40°C to +85°C) temperature ranges. Prices start at $1.89 (1000 up, FOB

USA).

(Circle 18)

22

Low-voltage,

8-channel SPST switch has serial interface

N

EW PRODUCT

S

The MAX395 serial interface is compatible with the SPI™, QSPI™, and

Microwire™ synchronous-serial standards.

Functioning as a shift register, it lets you

The MAX395 includes eight indepenclock in data (at DIN) synchronously with the rising edges of CLK. Then, a rising edge at

CS transfers data to the switches, affecting them simultaneously. The shiftdent, separately controlled single-pole/ single-throw (SPST) switches in a 24-pin

MAX8863* and MAX8864* linear regulators are designed primarily for battery-powered applications. Operating register output (DOUT) lets you cascade several MAX395 devices in a daisy-chain

Lowest-dropout

SOT-23 linear regulators deliver

50mA

package. Conducting equally well in either direction, the switches guarantee on-resistances of 100

. R

ON is matched to within

5

Ω max between switches and flat to within 10

Ω over the specified signal range.

Off leakages are only 0.1nA at +25°C configuration.

At power-up, an automatic reset ensures that all switches are open and the internal shift registers are cleared to zero. In addition, the

RESET input lets the MAX395 respond to asynchronous reset commands. ESD from inputs in the 2.5V to 5.5V range, they deliver output currents as high as 50mA with a maximum dropout voltage of

120mV. PMOS pass transistors ensure that the low 80µA supply current remains independent of load current, making the

(10nA at +25°C).

MAX8863/MAX8864 regulators suitable for use in modems, cellular and cordless

A CMOS device, the MAX395 operates

(electrostatic discharge) protection is rated at greater than 2kV per Method 3015.7 of with dual supply voltages of ±2.7V to ±8V, or a single supply voltage in the 2.7V to telephones, and other portable equipment.

MIL-STD-883.

Each device features Dual Mode™

16V range. For 5V or ±5V supplies, the digital inputs’ guaranteed logic thresholds

(0.8V and 2.4V) ensure TTL/CMOS compatibility. Each switch can handle railto-rail analog voltages. The MAX395’s pinout is compatible with the industrystandard MAX335 octal analog switch.

The MAX395 comes in a 24-pin narrow

DIP or wide-SO package, in versions tested for the commercial (0°C to +70°C), extendedindustrial (-40°C to +85°C), and military

(-55°C to +125°C) temperature ranges. Prices start at $2.98 (1000 up, FOB USA).

(Circle 19)

operation, which offers the option of a fixed or adjustable output voltage:

MAX8863T/ MAX8864T regulators are preset at 3.175V, and MAX8863S/

MAX8864S regulators are preset at

2.850V. Both versions let you set their output in the range 1.25V to 5.5V with an external resistor divider.

Low-power, slew-rate-limited

RS-485/RS-422 transceivers are

ESD protected to ±15kV

The low-power transceivers

MAX481E, MAX483E, MAX485E,

MAX487E–MAX491E, and MAX1487E are intended for RS-485 and RS-422 communications in harsh environments.

Each device contains one driver and one receiver, for which the driver output and receiver input are protected to ±15kV against electrostatic discharge (ESD) simulated by the Human Body Model.

Further, the chips guarantee freedom from latchup in the presence of ESD.

Drivers in the MAX481E, MAX485E,

MAX490E, MAX491E, and MAX1487E allow data transmissions to 2.5Mbps.

Drivers in the MAX483E, MAX487E,

MAX488E, and MAX489E have reduced slew rates that minimize EMI (electromagnetic interference) and the reflections caused by improperly terminated cables. As a result, these transceivers can produce error-free data transmissions to 250kbps. Commonmode input ranges are -7V to 12V.

All transceivers operate from 5V.

When unloaded or when fully loaded with disabled drivers, the MAX488E and

MAX489E draw supply currents as low as

120µA. MAX481E, MAX483E, and

MAX487E transceivers each have a shutdown mode that lowers supply current to only 0.5µA. All driver outputs are current-limited for protection against short circuits. For protection against excessive power dissipation, all drivers include thermal-protection circuitry that drives the output to a high-impedance state when required. All receivers include fail-safe circuitry that guarantees logic-high outputs in the presence of open-circuited inputs.

MAX488E–MAX491E devices are designed for full-duplex communications;

MAX481E, MAX483E, MAX485E,

MAX487E, and MAX1487E devices are designed for half-duplex communications.

For the MAX487E and MAX1487E, receiver input impedances of

1

4

-unit load allow as many as 128 transceivers on an

RS-485 or RS-422 bus. (By comparison, these buses support only 32 standard

These regulators have a shutdown mode that lowers their supply current to

0.1µA. Shutdown causes the MAX8864 to actively discharge its output voltage to ground, but the devices are otherwise identical. Common features include shortcircuit protection, thermal-shutdown protection, and reverse-battery protection.

MAX8863/MAX8864 regulators come in a 5-pin SOT-23 package, screened for the extended-industrial temperature range

(-40°C to +85°C).

(Circle 20)

* Future product—contact factory for availability.

Dual Mode is a trademark of Maxim Integrated

Products.

transceivers.) For applications that are not

ESD sensitive, use the economical “non-E” transceivers: MAX481, MAX483, MAX485,

MAX487–MAX491, and MAX1487.

The MAX489E and MAX491E come in 14-pin plastic DIP and SO packages; all others come in 8-pin plastic DIP and SO packages. All are available in versions tested for the commercial (0°C to +70°C) and extended-industrial (-40°C to +85°C) temperature ranges. The MAX1487E is also available in a military version (-55°C to +125°C). Prices start at $1.50 (1000 up,

FOB USA).

(Circle 21)

23

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