datasheet for BS83B12A

8-Bit Touch Key Flash MCU
BS83B08A-3/BS83B08A-4
BS83B12A-3/BS83B12A-4
BS83B16A-3/BS83B16A-4
Revision: V1.00
Date: May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Table of Contents
Features ............................................................................................................ 6
CPU Features ......................................................................................................................... 6
Peripheral Features................................................................................................................. 6
General Description ........................................................................................ 7
Selection Table ................................................................................................. 7
Block Diagram.................................................................................................. 8
Pin Assignment ................................................................................................ 9
Pin Descriptions ............................................................................................ 10
Absolute Maximum Ratings.......................................................................... 13
D.C. Characteristics....................................................................................... 13
A.C. Characteristics....................................................................................... 15
Power-on Reset Characteristics .................................................................. 15
System Architecture ...................................................................................... 16
Clocking and Pipelining ......................................................................................................... 16
Program Counter................................................................................................................... 17
Stack ..................................................................................................................................... 18
Arithmetic and Logic Unit – ALU ........................................................................................... 18
Flash Program Memory ................................................................................. 19
Structure................................................................................................................................ 19
Special Vectors ..................................................................................................................... 19
Look-up Table ........................................................................................................................ 20
Table Program Example ........................................................................................................ 21
In Circuit Programming ......................................................................................................... 22
RAM Data Memory ......................................................................................... 23
Structure................................................................................................................................ 23
Special Function Register Description ........................................................ 23
Indirect Addressing Registers – IAR0, IAR1 ......................................................................... 23
Memory Pointers – MP0, MP1 .............................................................................................. 26
Bank Pointer – BP ................................................................................................................. 27
Accumulator – ACC ............................................................................................................... 27
Program Counter Low Register – PCL.................................................................................. 27
Look-up Table Registers – TBLP, TBHP, TBLH ..................................................................... 27
Status Register – STATUS .................................................................................................... 28
Rev. 1.00
2
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
EEPROM Data Memory.................................................................................. 30
EEPROM Data Memory Structure ........................................................................................ 30
EEPROM Registers .............................................................................................................. 30
Reading Data from the EEPROM ........................................................................................ 32
Writing Data to the EEPROM ................................................................................................ 32
Write Protection ..................................................................................................................... 32
EEPROM Interrupt ................................................................................................................ 32
Programming Considerations................................................................................................ 33
Oscillator ........................................................................................................ 34
Oscillator Overview ............................................................................................................... 34
System Clock Conigurations ................................................................................................ 34
Internal RC Oscillator – HIRC ............................................................................................... 35
Internal 32kHz Oscillator – LIRC ........................................................................................... 35
Operating Modes and System Clocks ......................................................... 35
System Clocks ...................................................................................................................... 35
System Operation Modes...................................................................................................... 36
Control Register .................................................................................................................... 38
Operating Mode Switching ................................................................................................... 40
NORMAL Mode to SLOW Mode Switching ........................................................................... 41
SLOW Mode to NORMAL Mode Switching .......................................................................... 41
Entering the SLEEP Mode .................................................................................................... 41
Entering the IDLE0 Mode ...................................................................................................... 41
Entering the IDLE1 Mode ...................................................................................................... 42
Standby Current Considerations ........................................................................................... 43
Wake-up ................................................................................................................................ 44
Programming Considerations................................................................................................ 44
Watchdog Timer ............................................................................................. 45
Watchdog Timer Clock Source .............................................................................................. 45
Watchdog Timer Control Register ......................................................................................... 45
Watchdog Timer Operation ................................................................................................... 46
Reset and Initialisation.................................................................................. 47
Reset Functions .................................................................................................................... 47
Reset Initial Conditions ......................................................................................................... 50
Input/Output Ports ......................................................................................... 56
I/O Register List .................................................................................................................... 56
Pull-high Resistors ................................................................................................................ 57
Port A Wake-up ..................................................................................................................... 58
I/O Port Control Registers ..................................................................................................... 59
I/O Pin Structures .................................................................................................................. 60
Programming Considerations................................................................................................ 60
Rev. 1.00
3
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Timer/Event Counter ..................................................................................... 61
Coniguring the Timer/Event Counter Input Clock Source .................................................... 61
Timer Register – TMR ........................................................................................................... 61
Timer Control Register – TMRC ............................................................................................ 62
Timer Operation .................................................................................................................... 62
Prescaler ............................................................................................................................... 63
Programming Considerations................................................................................................ 63
Touch Key Function ...................................................................................... 63
Touch Key Structure .............................................................................................................. 63
Touch Key Register Deinition ............................................................................................... 64
Touch Key Operation............................................................................................................. 69
Touch Key Interrupt ............................................................................................................... 72
Programming Considerations................................................................................................ 72
Serial Interface Module – SIM ...................................................................... 72
SPI Interface ........................................................................................................................ 72
SPI Interface Operation ........................................................................................................ 73
SPI Registers ........................................................................................................................ 74
SPI Communication ............................................................................................................. 77
I2C Interface ......................................................................................................................... 79
I2C Interface Operation ......................................................................................................... 79
I2C Registers ......................................................................................................................... 80
I2C Bus Communication ....................................................................................................... 85
I2C Bus Start Signal .............................................................................................................. 86
Slave Address ...................................................................................................................... 86
I2C Bus Read/Write Signal ................................................................................................... 86
I2C Bus Slave Address Acknowledge Signal ........................................................................ 86
I2C Bus Data and Acknowledge Signal ................................................................................ 87
I2C Time-out Control .............................................................................................................. 89
Interrupts ........................................................................................................ 90
Interrupt Registers................................................................................................................. 90
Interrupt Operation ................................................................................................................ 93
External Interrupt................................................................................................................... 94
Time Base Interrupt ............................................................................................................... 94
Timer/Event Counter Interrupt ............................................................................................... 95
EEPROM Interrupt ................................................................................................................ 95
Touch Key Interrupt ............................................................................................................... 96
SIM Interrupt ......................................................................................................................... 96
Interrupt Wake-up Function ................................................................................................... 96
Programming Considerations................................................................................................ 97
Rev. 1.00
4
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Application Circuits ....................................................................................... 98
Instruction Set................................................................................................ 99
Instruction.............................................................................................................................. 99
Instruction Timing .................................................................................................................. 99
Moving and Transferring Data ............................................................................................... 99
Arithmetic Operations............................................................................................................ 99
Logical and Rotate Operations............................................................................................ 100
Branches and Control Transfer ........................................................................................... 100
Bit Operations ..................................................................................................................... 100
Table Read Operations ....................................................................................................... 100
Other Operations................................................................................................................. 100
Instruction Set Summary ............................................................................ 101
Table conventions ............................................................................................................... 101
Instruction Deinition................................................................................... 103
Package Information ....................................................................................112
16-pin NSOP (150mil) Outline Dimensions ..........................................................................113
16-pin SSOP(150mil) Outline Dimensions ...........................................................................114
20-pin SOP (300mil) Outline Dimensions ............................................................................115
20-pin SSOP (150mil) Outline Dimensions ..........................................................................116
24-pin SOP (300mil) Outline Dimensions ............................................................................117
24-pin SSOP (150mil) Outline Dimensions ..........................................................................118
Rev. 1.00
5
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Features
CPU Features
• OperatingVoltage:
ForBS83B08A-3/BS83B12A-3/BS83B16A-3
–fSYS=8MHz:2.7V~5.5V
–fSYS=12MHz:2.7V~5.5V
–fSYS=16MHz:4.5V~5.5V
ForBS83B08A-4/BS83B12A-4/BS83B16A-4
–fSYS=8MHz:2.2V~5.5V
–fSYS=12MHz:2.7V~5.5V
–fSYS=16MHz:4.5V~5.5V
• Upto0.25 sinstructioncyclewith16MHzsystemclockatVDD=5V
• Fullyintegrated8/12/16touchkeyfunctions--requirenoexternalcomponents
• Powerdownandwake-upfunctionstoreducepowerconsumption
• Fullyintegratedlowandhighspeedinternaloscillators
• LowSpeed--32kHz
• Highspeed--8MHz,12MHz,16MHz
• Multi-modeoperation:NORMAL,SLOW,IDLEandSLEEP
• Allinstructionsexecutedinoneortwoinstructioncycles
• Tablereadinstructions
• 63powerfulinstructions
• Upto4-levelsubroutinenesting
• Bitmanipulationinstruction
Peripheral Features
• FlashProgramMemory:2K×16
• RAMDataMemory:160×8~288×8
• EEPROMMemory:64×8
• WatchdogTimerfunction
• Upto22bidirectionalI/Olines
• ExternalinterruptlinesharedwithI/Opin
• Single8-bitTimer/EventCounter
• SingleTime-Basefunctionforgenerationofixedtimeinterruptsignals
• I2CandSPIinterfaces
• Lowvoltageresetfunction
• 8/12/16touchkeyfunctions
• HighcurrentLEDdriver
Rev. 1.00
6
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
General Description
These devices are a series of Flash Memory type 8-bit high performance RISC architecture
microcontrollerswithfullyintegratedtouchkeyfunctions.Withalltouchkeyfunctionsprovided
internallyandwiththeconvenienceofFlashMemorymulti-programmingfeatures,thisdevicerange
hasallthefeaturestoofferdesignersareliableandeasymeansofimplementingTouchKeyeswithin
theirproductsapplications.
The touch key functions are fully integrated completely eliminating the need for external
components.Inadditiontothelashprogrammemory,othermemoryincludesanareaofRAMData
MemoryaswellasanareaofEEPROMmemoryforstorageofnon-volatiledatasuchasserial
numbers,calibrationdataetc.ProtectivefeaturessuchasaninternalWatchdogTimerandLow
VoltageResetfunctionscoupledwithexcellentnoiseimmunityandESDprotectionensurethat
reliableoperationismaintainedinhostileelectricalenvironments.
All devices include fully integrated low and high speed oscillators which require no external
componentsfortheirimplementation.Theabilitytooperateandswitchdynamicallybetweenarange
ofoperatingmodesusingdifferentclocksourcesgivesuserstheabilitytooptimisemicrocontroller
operationandminimisepowerconsumption.Easycommunicationwiththeoutsideworldisprovided
usingtheinternalI2CandSPIinterfaces,whiletheinclusionoflexibleI/Oprogrammingfeatures,
Timer/EventCountersandmanyotherfeaturesfurtherenhancedevicefunctionalityandlexibility.
ThesetouchkeydeviceswillfindexcellentuseinahugerangeofmodernTouchKeyproduct
applicationssuchasinstrumentation,householdappliances,electronicallycontrolledtoolstoname
butafew.
Selection Table
Mostfeaturesarecommontoalldevices,themaindistinguishingfeatureisthenumberofI/Osand
TouchKeys.Thefollowingtablesummarisesthemainfeaturesofeachdevice.
Internal
Clock
VDD
System
Clock
BS83B08A-3
8MHz
12MHz
16MHz
2.7V~
5.5V
8MHz~
16MHz
2K×16
160×8
64×8
14
1
1
8
BS83B08A-4
8MHz
12MHz
16MHz
2.2V~
5.5V
8MHz~
16MHz
2K×16
160×8
64×8
14
1
1
BS83B12A-3
8MHz
12MHz
16MHz
2.7V~
5.5V
8MHz~
16MHz
2K×16
288×8
64×8
18
18
1
BS83B12A-4
8MHz
12MHz
16MHz
2.2V~
5.5V
8MHz~
16MHz
2K×16
288×8
64×8
18
18
BS83B16A-3
8MHz
12MHz
16MHz
2.7V~
5.5V
8MHz~
16MHz
2K×16
288×8
64×8
22
BS83B16A-4
8MHz
12MHz
16MHz
2.2V~
5.5V
8MHz~
16MHz
2K×16
288×8
64×8
22
Rev. 1.00
Program
Data
Data
I/O
Memory Memory EEPROM
High
Current
LED
Output
Part No.
7
8-bit Time Touch SPI/
Timer Base Key
I2C
LVR
Stack
Package
1
2.55V
4
16NSOP/
SSOP
8
1
2.10V
4
16NSOP/
SSOP
1
12
1
2.55V
4
20SOP/
SSOP
1
1
12
1
2.10V
4
20SOP/
SSOP
22
1
1
16
1
2.55V
4
24SOP/
SSOP
22
1
1
16
1
2.10V
4
24SOP/
SSOP
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Block Diagram
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   8
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Pin Assignment
BS83B08A-3/BS83B08A-4
16 NSOP-A/SSOP-A
BS83B12A-3/BS83B12A-4
20 SOP-A/SSOP-A
BS83B16A-3/BS83B16A-4
24 SOP-A/SSOP-A
Rev. 1.00
9
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Pin Descriptions
Thefunctionofeachpinislistedinthefollowingtables,howeverthedetailsbehindhoweachpinis
conigurediscontainedinothersectionsofthedatasheet.
BS83B08A-3/BS83B08A-4
Pin Name
PA0/SDI/SDA
PA1/SDO
PA2/SCK/SCL
PA3/SCS
PA4/INT
PA7
PB0/KEY1~
PB3/KEY4
Function
OPT
I/T
PA0
PAWU
PAPU
ST
O/T
Description
CMOS General purpose I/O. Register enabled pull-up and wake-up
SDI
—
ST
SDA
—
ST
NMOS I2C data
PA1
PAWU
PAPU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up
SDO
SIMC0
—
CMOS SPI data output
PA2
PAWU
PAPU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up
SCK
SIMC0
ST
CMOS SPI serial clock
SCL
SIMC0
ST
NMOS I2C clock
PA3
PAWU
PAPU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up
SCS
SIMC0
ST
CMOS SPI slave select
PA4
PAWU
PAPU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up
INT
INTEG
ST
PA7
PAWU
PAPU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up
PB0~PB3
PBPU
ST
CMOS General purpose I/O. Register enabled pull-up
KEY1~KEY4 TKM0C1
NSI
—
—
—
SPI data input
External interrupt
Touch key inputs
CMOS General purpose I/O. Register enabled pull-up
PB4~PB7
PBPU
ST
KEY5~
KEY8
TKM1C1
NSI
—
Touch key inputs
VDD
VDD
—
PWR
—
Power supply *
AVDD
AVDD
—
PWR
—
Touch Key Circuit PWR and it should be double bonded to
VDD*
VSS
—
PWR
—
Ground **
—
Touch Key Circuit PWR and it should be double bonded to
VSS**
PB4/KEY5~
PB7/KEY8
VSS
AVSS
AVSS
—
PWR
Note:I/T:Inputtype
O/T:Outputtype
OP:Optionalbyregisterselection
PWR:Power
ST:chmittTriggerinput
CMOS:CMOSoutput
NMOS:NMOSoutput
NSI:Non-standardinput
*:VDDisthedevicepowersupplywhileAVDDisthetouchkeycircuitpowersupply.TheAVDDpinis
bondedtogetherinternallywithVDD.
**:VSSisthedevicegroundpinwhileAVSSisthetouchkeycircuitgroundpin.TheAVSSpinisbonded
togetherinternallywithVSS.
Rev. 1.00
10
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
BS83B12A-3/BS83B12A-4
Pin Name
PA0/SDI/SDA
PA1/SDO
PA2/SCK/SCL
PA3/SCS
PA4/INT
PA7
PB0/KEY1~
PB3/KEY4
PB4/KEY5~
PB7/KEY8
Function
OPT
I/T
PA0
PAWU
PAPU
ST
O/T
Description
CMOS General purpose I/O. Register enabled pull-up and wake-up
SDI
—
ST
SDA
—
ST
NMOS I2C data
—
SPI data input
PA1
PAWU
PAPU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up
SDO
SIMC0
—
CMOS SPI data output
PA2
PAWU
PAPU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up
SCK
SIMC0
ST
CMOS SPI serial clock
SCL
SIMC0
ST
NMOS I2C clock
PA3
PAWU
PAPU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up
SCS
SIMC0
ST
CMOS SPI slave select
PA4
PAWU
PAPU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up
INT
INTEG
ST
PA7
PAWU
PAPU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up
PB0~PB3
PBPU
ST
CMOS General purpose I/O. Register enabled pull-up
KEY1~KEY4 TKM0C1
PB4~PB7
PBPU
KEY5~KEY8 TKM1C1
NSI
ST
NSI
—
—
External interrupt
Touch key inputs
CMOS General purpose I/O. Register enabled pull-up
—
Touch key inputs
PC0~PC3
PCPU
ST
KEY9~
KEY12
TKM2C1
NSI
—
Touch key inputs
VDD
VDD
—
PWR
—
Power supply *
AVDD
AVDD
—
PWR
—
Touch Key Circuit PWR and it should be double bonded to
VDD*
VSS
—
PWR
—
Ground **
—
Touch Key Circuit PWR and it should be double bonded to
VSS**
PC0/KEY9~
PC3/KEY12
VSS
AVSS
AVSS
—
PWR
CMOS General purpose I/O. Register enabled pull-up
Note:I/T:Inputtype
O/T:Outputtype
OP:Optionalbyregisterselection
PWR:Power
ST:chmittTriggerinput
CMOS:CMOSoutput
NMOS:NMOSoutput
NSI:Non-standardinput
*:VDDisthedevicepowersupplywhileAVDDisthetouchkeycircuitpowersupply.TheAVDDpinis
bondedtogetherinternallywithVDD.
**:VSSisthedevicegroundpinwhileAVSSisthetouchkeycircuitgroundpin.TheAVSSpinisbonded
togetherinternallywithVSS.
Rev. 1.00
11
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
BS83B16A-3/BS83B16A-4
Pin Name
PA0/SDI/SDA
PA1/SDO
PA2/SCK/SCL
PA3/SCS
PA4/INT
PA7
PB0/KEY1~
PB3/KEY4
PB4/KEY5~
PB7/KEY8
Function
OPT
I/T
PA0
PAWU
PAPU
ST
O/T
Description
CMOS General purpose I/O. Register enabled pull-up and wake-up
SDI
—
ST
SDA
—
ST
NMOS I2C data
—
SPI data input
PA1
PAWU
PAPU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up
SDO
SIMC0
—
CMOS SPI data output
PA2
PAWU
PAPU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up
SCK
SIMC0
ST
CMOS SPI serial clock
SCL
SIMC0
ST
NMOS I2C clock
PA3
PAWU
PAPU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up
SCS
SIMC0
ST
CMOS SPI slave select
PA4
PAWU
PAPU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up
INT
INTEG
ST
PA7
PAWU
PAPU
ST
CMOS General purpose I/O. Register enabled pull-up and wake-up
PB0~PB3
PBPU
ST
CMOS General purpose I/O. Register enabled pull-up
KEY1~KEY4 TKM0C1
PB4~PB7
PBPU
KEY5~KEY8 TKM1C1
NSI
ST
NSI
—
—
External interrupt
Touch key inputs
CMOS General purpose I/O. Register enabled pull-up
—
Touch key inputs
PC0~PC3
PCPU
ST
KEY9~
KEY12
TKM2C1
NSI
PC4~PC7
PCPU
ST
KEY13~
KEY16
TKM3C1
NSI
—
Touch key inputs
VDD
VDD
—
PWR
—
Power supply *
AVDD
AVDD
—
PWR
—
Touch Key Circuit PWR and it should be double bonded to
VDD*
VSS
—
PWR
—
Ground **
—
Touch Key Circuit PWR and it should be double bonded to
VSS**
PC0/KEY9~
PC3/KEY12
PC4/KEY13~
PC7/KEY16
VSS
AVSS
AVSS
—
PWR
CMOS General purpose I/O. Register enabled pull-up
—
Touch key inputs
CMOS General purpose I/O. Register enabled pull-up
Note:I/T:Inputtype
O/T:Outputtype
OP:Optionalbyregisterselection
PWR:Power
ST:chmittTriggerinput
CMOS:CMOSoutput
NMOS:NMOSoutput
NSI:Non-standardinput
*:VDDisthedevicepowersupplywhileAVDDisthetouchkeycircuitpowersupply.TheAVDDpinis
bondedtogetherinternallywithVDD.
**:VSSisthedevicegroundpinwhileAVSSisthetouchkeycircuitgroundpin.TheAVSSpinisbonded
togetherinternallywithVSS.
Rev. 1.00
12
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Absolute Maximum Ratings
SupplyVoltage................................................................................................VSS−0.3VtoVSS+6.0V
InputVoltage..................................................................................................VSS−0.3VtoVDD+0.3V
StorageTemperature................................................................................................... -50°Cto125°C
OperatingTemperature................................................................................................. -40°Cto85°C
IOHTotal....................................................................................................................................-80mA
IOLTotal..................................................................................................................................... 80mA
TotalPowerDissipation........................................................................................................ 500mW
Note:Thesearestressratingsonly.Stressesexceedingtherangespecifiedunder"AbsoluteMaximum
Ratings"maycausesubstantialdamagetothedevice.Functionaloperationofthisdeviceatother
conditionsbeyondthoselistedinthespeciicationisnotimpliedandprolongedexposuretoextreme
conditionsmayaffectdevicereliability.
D.C. Characteristics
Ta=25°C
Symbol
VDD
VDD
Parameter
Operating Voltage (HIRC)
(BS83B08A-3/BS83B12A-3/
BS83B16A-3)
Operating Voltage (HIRC)
(BS83B08A-4/BS83B12A-4/
BS83B16A-4)
Test Conditions
VDD
—
—
3V
5V
IDD1
Operating Current
(HIRC, fSYS=fH, fS=fSUB=fLIRC)
3V
Conditions
Unit
fSYS=8MHz
2.7
—
5.5
V
fSYS=12MHz
2.7
—
5.5
V
fSYS=16MHz
4.5
—
5.5
V
fSYS=8MHz
2.2
—
5.5
V
fSYS=12MHz
2.7
—
5.5
V
fSYS=16MHz
4.5
—
5.5
V
No load, fH=8MHz, WDT enable
—
1.2
1.8
mA
—
2.2
3.3
mA
mA
1.6
2.4
3.3
5.0
mA
—
2.0
3.0
mA
—
4.0
6.0
mA
—
1.2
2.0
mA
—
2.2
3.3
mA
3V No load, fH=12MHz,
5V fL=fH/4, WDT enable
—
1.0
1.5
mA
—
1.8
2.7
mA
5V No load, fH=12MHz,
3V fL=fH/8, WDT enable
—
0.9
1.4
mA
—
1.6
2.4
mA
3V No load, fH =12MHz,
5V fL=fH/16, WDT enable
—
0.8
1.2
mA
—
mA
No load, fH=12MHz, WDT enable
No load, fH=16MHz, WDT enable
3V No load, fH=12MHz,
5V fL=fH/2, WDT enable
1.5
2.3
3V No load, fH=12MHz,
5V fL=fH/32, WDT enable
—
0.8
1.2
mA
—
1.5
2.3
mA
5V No load, fH=12MHz,
3V fL=fH/64, WDT enable
—
0.8
1.2
mA
—
1.5
2.3
mA
3V
—
50
100
A
—
70
150
A
—
0.9
1.4
mA
—
1.4
2.1
mA
IDD3
Operating Current
(LIRC, fSYS=fL=fLIRC, fS=fSUB=fLIRC)
5V
ISTB1
IDLE Mode Standby Current
(HIRC, fSYS=fH, fS=fSUB=fLIRC)
3V No load, system HALT, WDT enable,
5V fSYS=12MHz
Rev. 1.00
Max.
—
5V
Operating Current
(HIRC, fSYS=fL, fS=fSUB=fLIRC)
Typ.
—
5V
3V
IDD2
Min.
No load, WDT enable, LVR enable
13
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
A
ISTB2
IDLE Mode Standby Current
(HIRC, fSYS=off, fS=fSUB=fLIRC)
3V No load, system HALT, WDT enable,
5V fSYS=12MHz, LVR enable
—
40
80
—
50
100
A
ISTB3
IDLE Mode Standby Current
(HIRC, fSYS=fL, fS=fSUB=fLIRC)
3V No load, system HALT, WDT enable,
5V fSYS=12MHz/64
—
0.7
1.1
mA
—
1.4
2.1
mA
ISTB4
IDLE Mode Standby Current
(HIRC, fSYS=off, fS=fSUB=fLIRC)
3V No load, system HALT, WDT enable,
5V fSYS=12MHz/64, LVR enable
—
40
80
A
—
50
100
A
ISTB5
IDLE Mode Standby Current
(LIRC, fSYS=fL=fLIRC, fS=fSUB=fLIRC)
3V No load, system HALT, WDT enable,
5V fSYS=32kHz
—
1.9
4.0
A
—
3.3
7.0
A
ISTB6
IDLE Mode Standby Current
(LIRC, fSYS=off, fS=fSUB=fLIRC)
3V No load, system HALT, WDT enable,
5V fSYS=32kHz, LVR enable
—
40
80
A
—
50
100
A
ISTB7
SLEEP Mode Standby Current
(HIRC, fSYS=off, fS=fSUB=fLIRC)
3V No load, system HALT, WDT enable,
5V fSYS=12MHz, LVR enable
—
40
80
A
—
50
100
A
ISTB8
SLEEP Mode Standby Current
(LIRC, fSYS=off, fS=fSUB=fLIRC)
3V No load, system HALT, WDT enable,
5V fSYS=32kHz
—
1.3
3.0
A
—
2.4
5.0
A
VIL
Input Low Voltage for I/O Ports
or Input Pins
5V
0
—
1.5
V
0
—
0.2VDD
V
VIH
Input High Voltage for I/O Ports
or Input Pins
5V
VLVR
Low Voltage Reset Voltage
(BS83B08A-3/BS83B12A-3/
BS83B16A-3)
—
VLVR
Low Voltage Reset Voltage
(BS83B08A-4/BS83B12A-4/
BS83B16A-4)
ILVR
—
—
3.5
—
5.0
V
0.8VDD
—
VDD
V
LVR enable, 2.55V
-5%
2.55
+5%
V
—
LVR enable, 2.10V
-5%
2.10
+5%
V
Low Voltage Reset Current
—
LVR enable
—
62
90
A
IOL
Sink Current for I/O Port
(BS83B08A-3/BS83B08A-4)
3V
4
8
—
mA
10
20
—
mA
Sink Current for I/O Port
(BS83B12A-3/BS83B12A-4,
BS83B16A-3/BS83B16A-4)
3V
8
16
—
mA
IOL
16
32
—
mA
IOH
Source Current for I/O Port
(BS83B08A-3/BS83B08A-4)
3V
-2
-4
—
mA
-5
-10
—
mA
3V
-3.75
-7.5
—
mA
IOH
Source Current for I/O Port
(BS83B12A-3/BS83B12A-4,
BS83B16A-3/BS83B16A-4)
-7.5
-15
—
mA
RPH
Rev. 1.00
Pull-high Resistance for I/O Ports
—
—
5V
VOL=0.1VDD
VOL=0.1VDD
5V
5V
VOH=0.9VDD
VOH=0.9VDD
5V
3V
—
20
60
100
k
5V
—
10
30
50
k
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May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
A.C. Characteristics
Ta=25°C
Symbol
fSYS
Test Conditions
Parameter
Conditions
VDD
System Clock (HIRC)
3V/5V
Ta=25°C
2.7V~5.5V
fTIMER
Timer Input Pin Frequency
2.7V~5.5V
—
4.5V~5.5V
fLIRC
System Clock (32kHz)
5V
Ta=25°C
Min.
Typ.
Max.
Unit
-2%
8
+2%
MHz
-2%
12
+2%
MHz
-2%
16
+2%
MHz
—
—
8
MHz
—
—
12
MHz
—
—
16
MHz
-3%
32
+3%
kHz
s
tINT
Interrupt Pulse Width
—
—
1
—
—
tLVR
Low Voltage Width to Reset
—
—
60
120
240
s
tEERD
EEPROM Read Time
—
—
1
2
4
tSYS
tEEWR
EEPROM Write Time
—
ms
tSST
System Start-up Timer Period
(Wake-up from HALT)
—
—
1
2
4
fSYS=HIRC
—
15~16
20
fSYS=LIRC
—
1~2
—
tSYS
Note:1.tSYS=1/fSYS
2.TomaintaintheaccuracyoftheinternalHIRCoscillatorfrequency,a0.1 Fdecouplingcapacitorshould
beconnectedbetweenVDDandVSSandlocatedasclosetothedeviceaspossible.
3.16MHzcannotbeusedwhenthesupplyvoltageisbelow3V.
Power-on Reset Characteristics
Symbol
Test Conditions
Parameter
VDD
Conditions
Min. Typ. Max. Unit
VPOR
VDD Start Voltage to eEnsure Power-on Reset
—
—
—
—
100
mV
RRVDD
VDD Raising Rate to Ensure Power-on Reset
—
—
0.035
—
—
V/ms
tPOR
Minimum Time for VDD Stays at VPOR to Ensure
Power-on Reset
—
—
1
—
—
ms
Rev. 1.00
15
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
System Architecture
Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributed
totheirinternalsystemarchitecture.Therangeofdevicestakeadvantageoftheusualfeaturesfound
withinRISCmicrocontrollersprovidingincreasedspeedofoperationandPeriodicperformance.The
pipeliningschemeisimplementedinsuchawaythatinstructionfetchingandinstructionexecution
areoverlapped,henceinstructionsareeffectivelyexecutedinonecycle,withtheexceptionofbranch
orcallinstructions.An8-bitwideALUisusedinpracticallyallinstructionsetoperations,which
carriesoutarithmeticoperations,logicoperations,rotation,increment,decrement,branchdecisions,
etc.TheinternaldatapathissimplifiedbymovingdatathroughtheAccumulatorandtheALU.
CertaininternalregistersareimplementedintheDataMemoryandcanbedirectlyorindirectly
addressed.Thesimpleaddressingmethodsoftheseregistersalongwithadditionalarchitectural
featuresensurethataminimumofexternalcomponentsisrequiredtoprovideafunctionalI/O
controlsystemwithmaximumreliabilityandlexibility.Thismakesthesedevicessuitableforlowcost,high-volumeproductionforcontrollerapplications.
Clocking and Pipelining
Themainsystemclock,derivedfromeitherahighorlowspeedoscillatorissubdividedintofour
internallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincrementedatthe
beginningoftheT1clockduringwhichtimeanewinstructionisfetched.TheremainingT2~T4
clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clockcycleforms
oneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplaceinconsecutive
instruction cycles, the pipelining structure of the microcontroller ensures that instructions are
effectively executed in one instruction cycle.The exception to this are instructions where the
contentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhichcasethe
instructionwilltakeonemoreinstructioncycletoexecute.
System Clock and Pipelining
Rev. 1.00
16
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
For instructionsinvolvingbranches,suchas jumpor callinstructions,two machinecyclesare
requiredtocompleteinstructionexecution.Anextracycleisrequiredastheprogramtakesone
cycletoirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethe
branch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintiming
sensitiveapplications.
Instruction Fetching
Program Counter
During program execution, the Program Counter is used to keep track of the address of the
nextinstructiontobeexecuted.Itisautomaticallyincrementedbyoneeachtimeaninstruction
is executed except for instructions, such as “JMP” or “CALL” that demand a jump to a
non-consecutiveProgramMemoryaddress.Onlythelower8bits,knownastheProgramCounter
LowRegister,aredirectlyaddressablebytheapplicationprogram.
When executing instructions requiring jumps to non-consecutive addresses such as a jump
instruction,asubroutinecall,interruptorreset,etc.,themicrocontrollermanagesprogramcontrol
byloadingtherequiredaddressintotheProgramCounter.Forconditionalskipinstructions,once
theconditionhasbeenmet,thenextinstruction,whichhasalreadybeenfetchedduringthepresent
instructionexecution,isdiscardedandadummycycletakesitsplacewhilethecorrectinstructionis
obtained.
Device
Program Counter
Program CounterHigh Byte
BS83B08A-3/BS83B08A-4
PC10~PC8
BS83B12A-3/BS83B12A-4
PC10~PC8
BS83B16A-3/BS83B16A-4
PC10~PC8
PCL Register
PCL7~PCL0
ThelowerbyteoftheProgramCounter,knownastheProgramCounterLowregisterorPCL,is
availableforprogramcontrolandisareadableandwriteableregister.Bytransferringdatadirectly
intothisregister,ashortprogramjumpcanbeexecuteddirectly,however,asonlythislowbyte
isavailableformanipulation,thejumpsarelimitedtothepresentpageofmemory,thatis256
locations.When such program jumps areexecuteditshould also be noted thatadummy cycle
willbeinserted.ManipulatingthePCLregistermaycauseprogrambranching,soanextracycleis
neededtopre-fetch.
Rev. 1.00
17
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Stack
ThisisaspecialpartofthememorywhichisusedtosavethecontentsoftheProgramCounter
only.Thestackisneitherpartofthedatanorpartoftheprogramspace,andisneitherreadablenor
writeable.TheactivatedlevelisindexedbytheStackPointer,andisneitherreadablenorwriteable.
Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushed
ontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,
RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevice
reset,theStackPointerwillpointtothetopofthestack.
Ifthestackisfullandanenabledinterrupttakesplace,theinterruptrequestlagwillberecorded
buttheacknowledgesignalwillbeinhibited.WhentheStackPointerisdecremented,byRETor
RETI,theinterruptwillbeserviced.Thisfeaturepreventsstackoverlowallowingtheprogrammer
tousethestructuremoreeasily.However,whenthestackisfull,aCALLsubroutineinstructioncan
stillbeexecutedwhichwillresultinastackoverlow.Precautionsshouldbetakentoavoidsuch
caseswhichmightcauseunpredictableprogrambranching.Ifthestackisoverlow,theirstProgram
Countersaveinthestackwillbelost.
Arithmetic and Logic Unit – ALU
Thearithmetic-logicunitorALUisacriticalareaofthemicrocontrollerthatcarriesoutarithmetic
andlogicoperationsoftheinstructionset.Connectedtothemainmicrocontrollerdatabus,theALU
receivesrelatedinstructioncodesandperformstherequiredarithmeticorlogicaloperationsafter
whichtheresultwillbeplacedinthespeciiedregister.AstheseALUcalculationoroperationsmay
resultincarry,borroworotherstatuschanges,thestatusregisterwillbecorrespondinglyupdatedto
relectthesechanges.TheALUsupportsthefollowingfunctions:
• Arithmeticoperations:ADD,ADDM,ADC,ADCM,SUB,SUBM,SBC,SBCM,DAA
• Logicoperations:AND,OR,XOR,ANDM,ORM,XORM,CPL,CPLA
• RotationRRA,RR,RRCA,RRC,RLA,RL,RLCA,RLC
• IncrementandDecrementINCA,INC,DECA,DEC
• Branchdecision,JMP,SZ,SZA,SNZ,SIZ,SDZ,SIZA,SDZA,CALL,RET,RETI
Rev. 1.00
18
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Flash Program Memory
TheProgramMemoryisthelocationwheretheusercodeorprogramisstored.Forthisdevice
seriestheProgramMemoryisFlashtype,whichmeansitcanbeprogrammedandre-programmed
a large number of times, allowing the user the convenience of code modification on the same
device.Byusingtheappropriateprogrammingtools,theseFlashdevicesofferusersthelexibilityto
convenientlydebuganddeveloptheirapplicationswhilealsoofferingameansofieldprogramming
andupdating.
Structure
TheProgramMemoryhasacapacityof2K×16bits.TheProgramMemoryisaddressedbythe
ProgramCounterandalsocontainsdata,tableinformationandinterruptentries.Tabledata,which
canbesetupinanylocationwithintheProgramMemory,isaddressedbyaseparatetablepointer
register.
Special Vectors
WithintheProgramMemory,certainlocationsarereservedfortheresetandinterrupts.Thelocation
000H is reserved for use by the device reset for program initialisation.After a devicereset is
initiated,theprogramwilljumptothislocationandbeginexecution.
Program Memory Structure
Rev. 1.00
19
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Look-up Table
AnylocationwithintheProgramMemorycanbedeinedasalook-uptablewhereprogrammerscan
storeixeddata.Tousethelook-uptable,thetablepointermustirstbesetupbyplacingtheaddress
ofthelookupdatatoberetrievedinthetablepointerregister,TBLPandTBHP.Theseregisters
deinethetotaladdressofthelook-uptable.
After setting up the table pointer, the table data can be retrieved from the Program Memory
usingthe“TABRDC[m]”or“TABRDL[m]”instructions,respectively.Whentheinstructionis
executed, the lower order table byte from the Program Memory will be transferred to the user
deinedDataMemoryregister[m]asspeciiedintheinstruction.Thehigherordertabledatabyte
fromtheProgramMemorywillbetransferredtotheTBLHspecialregister.Anyunusedbitsinthis
transferredhigherorderbytewillbereadas“0”.
Theaccompanyingdiagramillustratestheaddressingdatalowofthelook-uptable.
Instruction
Table Location Bits
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
TABRDC [m]
@10
@9
@8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:b10~b0:Tablelocationbits
@7~@0:Tablepointer(TBLP)bits
@10~@8:Tablepointer(TBHP)bits
Rev. 1.00
20
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Table Program Example
Thefollowingexampleshowshowthetablepointerandtabledataisdeinedandretrievedfromthe
microcontroller.ThisexampleusesrawtabledatalocatedintheProgramMemorywhichisstored
thereusingtheORGstatement.ThevalueatthisORGstatementis“700H”whichreferstothestart
addressofthelastpagewithinthe2KwordsProgramMemoryofthedevice.Thetablepointeris
setupheretohaveaninitialvalueof“06H”.Thiswillensurethattheirstdatareadfromthedata
tablewillbeattheProgramMemoryaddress“706H”or6locationsafterthestartofthelastpage.
Notethatthevalueforthetablepointerisreferencedtotheirstaddressofthepresentpageifthe
“TABRDC[m]”instructionisbeingused.Thehighbyteofthetabledatawhichinthiscaseisequal
tozerowillbetransferredtotheTBLHregisterautomaticallywhenthe“TABRDC[m]”instruction
isexecuted.
BecausetheTBLHregisterisaread-onlyregisterandcannotberestored,careshouldbetaken
to ensure its protection if both the main routine and Interrupt Service Routine use table read
instructions.Ifusingthetablereadinstructions,theInterruptServiceRoutinesmaychangethe
valueoftheTBLHandsubsequentlycauseerrorsifusedagainbythemainroutine.Asaruleitis
recommendedthatsimultaneoususeofthetablereadinstructionsshouldbeavoided.However,in
situationswheresimultaneoususecannotbeavoided,theinterruptsshouldbedisabledpriortothe
executionofanymainroutinetable-readinstructions.Notethatalltablerelatedinstructionsrequire
twoinstructioncyclestocompletetheiroperation.
Table Read Program Example
tempreg1 db ?
tempreg2 db ?
:
:
mov a,06h
mov tblp,a
mov a,07h
mov tbhp,a
:
:
tabrdc tempreg1
dec tblp
tabrdc tempreg2
; temporary register #1
; temporary register #2
; initialise low table pointer - note that this address is referenced
; initialise high table pointer
;
;
;
;
;
;
;
transfers value in table referenced by table pointer data at program
memory address “706H” transferred to tempreg1 and TBLH
reduce value of table pointer by one
transfers value in table referenced by table pointer data at program
memory address “705H” transferred to tempreg2 and TBLH in this
example the data “1AH” is transferred to tempreg1 and data “0FH” to
register tempreg2
:
:
org 700h
; sets initial address of program memory
dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Rev. 1.00
21
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
In Circuit Programming
TheprovisionofFlashtypeProgramMemoryprovidestheuserwithameansofconvenientandeasy
upgradesandmodiicationstotheirprogramsonthesamedevice.Asanadditionalconvenience,
Holtekhasprovidedameansofprogrammingthemicrocontrollerin-circuitusinga4-pininterface.
Thisprovidesmanufacturerswiththepossibilityofmanufacturingtheircircuitboardscompletewith
aprogrammedorun-programmedmicrocontroller,andthenprogrammingorupgradingtheprogram
atalaterstage.Thisenablesproductmanufacturerstoeasilykeeptheirmanufacturedproducts
suppliedwiththelatestprogramreleaseswithoutremovalandre-insertionofthedevice.
TheHoltekFlashMCUtoWriterProgrammingPincorrespondencetableisasfollows:
Holtek Write Pins
MCU Programming Pins
ICPDA
PA0
Serial Address and data -- read/write
Function
ICPCK
PA2
Programming Serial Clock
VDD
VDD
Power Supply (5.0V)
VSS
VSS
Ground
Duringtheprogrammingprocess,theusermusttheretakecaretoensurethatnootheroutputsare
connectedtothesetwopins.
TheProgramMemoryandEEPROMdatamemorycanbothbeprogrammedseriallyin-circuitusing
this4-wireinterface.Dataisdownloadedanduploadedseriallyonasinglepinwithanadditional
linefortheclock.Twoadditionallinesarerequiredforthepowersupply.Thetechnicaldetails
regardingthein-circuitprogrammingofthedevicearebeyondthescopeofthisdocumentandwill
besuppliedinsupplementaryliterature.
During the programming process the PA0 and PA2 I/O pins for data and clock programming
purposes.Theusermusttheretakecaretoensurethatnootheroutputsareconnectedtothesetwo
pins.
Note:*mayberesistororcapacitor.Theresistanceof*mustbegreaterthan1korthecapacitance
of*mustbelessthan1nF.
Rev. 1.00
22
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
RAM Data Memory
TheDataMemoryisavolatileareaof8-bitwideRAMinternalmemoryandisthelocationwhere
temporaryinformationisstored.
Structure
Dividedintotwosections,theirstoftheseisanareaofRAM,knownastheSpecialFunctionData
Memory.Herearelocatedregisterswhicharenecessaryforcorrectoperationofthedevice.Many
oftheseregisterscanbereadfromandwrittentodirectlyunderprogramcontrol,however,some
remainprotectedfromusermanipulation.
ThesecondareaofDataMemoryisknownastheGeneralPurposeDataMemory,whichisreserved
forgeneralpurposeuse.Alllocationswithinthisareaarereadandwriteaccessibleunderprogram
control.
TheoverallDataMemoryissubdividedintotwobanksforthedevices.TheSpecialPurposeData
Memoryregistersareaccessibleinallbanks,withtheexceptionoftheEECregisterataddress40H,
whichisonlyaccessibleinBank1.SwitchingbetweenthedifferentDataMemorybanksisachieved
bysettingtheBankPointertothecorrectvalue.ThestartaddressoftheDataMemoryforalldevices
istheaddress00H.
Device
Capacity
Bank 0
BS83B08A-3/BS83B08A-4
160×8
60H~FFH
Bank 1
—
BS83B12A-3/BS83B12A-4
288×8
60H~FFH
80H~FFH
BS83B16A-3/BS83B16A-4
288×8
60H~FFH
80H~FFH
General Purpose Data Memory
Special Function Register Description
MostoftheSpecialFunctionRegisterdetailswillbedescribedintherelevantfunctionalsection,
howeverseveralregistersrequireaseparatedescriptioninthissection.
Indirect Addressing Registers – IAR0, IAR1
TheIndirectAddressingRegisters,IAR0andIAR1,althoughhavingtheirlocationsinnormalRAM
registerspace,donotactuallyphysicallyexistasnormalregisters.Themethodofindirectaddressing
for RAM datamanipulationuses theseIndirectAddressing Registers and Memory Pointers, in
contrasttodirectmemoryaddressing,wheretheactualmemoryaddressisspeciied.Actionsonthe
IAR0andIAR1registerswillresultinnoactualreadorwriteoperationtotheseregistersbutrather
tothememorylocationspeciiedbytheircorrespondingMemoryPointers,MP0orMP1.Actingasa
pair,IAR0andMP0cantogetheraccessdatafromBank0whiletheIAR1andMP1registerpaircan
accessdatafromanybank.AstheIndirectAddressingRegistersarenotphysicallyimplemented,
readingtheIndirectAddressingRegistersindirectlywillreturnaresultof“00H”andwritingtothe
registersindirectlywillresultinnooperation.
Rev. 1.00
23
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
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Special Purpose Data Memory – BS83B08A-3/BS83B08A-4/BS83B12A-3/BS83B12A-4
Rev. 1.00
24
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
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Special Purpose Data Memory – BS83B16A-3/BS83B16A-4
General Purpose Data Memory
Rev. 1.00
25
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Memory Pointers – MP0, MP1
Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are
physicallyimplementedintheDataMemoryandcanbemanipulatedinthesamewayasnormal
registersprovidingaconvenientwaywithwhichtoaddressandtrackdata.Whenanyoperationto
therelevantIndirectAddressingRegistersiscarriedout,theactualaddressthatthemicrocontroller
isdirectedtoistheaddressspeciiedbytherelatedMemoryPointer.MP0,togetherwithIndirect
AddressingRegister,IAR0,areusedtoaccessdatafromBank0,whileMP1andIAR1areusedto
accessdatafromallbanksaccordingtoBPregister.DirectAddressingcanonlybeusedwithBank0,
allotherBanksmustbeaddressedindirectlyusingMP1andIAR1.
ThefollowingexampleshowshowtoclearasectionoffourDataMemorylocationsalreadydeined
aslocationsadres1toadres4.
Indirect Addressing Program Example
data .section ´data´
adres1 db ?
adres2 db ?
adres3 db ?
adres4 db ?
block
db ?
code .section at 0 ´code´
org00h
start:
mov a,04h
mov block,a
mov a,offset adres1
mov mp0,a
loop:
clr IAR0
inc mp0
sdz block
jmp loop
continue:
; setup size of block
; Accumulator loaded with irst RAM address
; setup memory pointer with irst RAM address
; clear the data at address deined by mp0
; increment memory pointer
; check if last memory location has been cleared
Theimportantpointtonotehereisthatintheexampleshownabove,noreferenceismadetospeciic
DataMemoryaddresses.
Rev. 1.00
26
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Bank Pointer – BP
For this device, the Data Memory is divided into two banks, Bank0 and Bank1. Selecting the
requiredDataMemoryareaisachievedusingtheBankPointer.Bit0oftheBankPointerisusedto
selectDataMemoryBanks0~1.
TheDataMemoryisinitialisedtoBank0afterareset,exceptforaWDTtime-outresetinthePower
DownMode,inwhichcase,theDataMemorybankremainsunaffected.Itshouldbenotedthatthe
SpecialFunctionDataMemoryisnotaffectedbythebankselection,whichmeansthattheSpecial
FunctionRegisterscanbeaccessedfromwithinanybank.DirectlyaddressingtheDataMemory
willalwaysresultinBank0beingaccessedirrespectiveofthevalueoftheBankPointer.Accessing
datafromBank1mustbeimplementedusingIndirectAddressing.
BP Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
—
DMBP0
R/W
—
—
—
—
—
—
—
R/W
POR
—
—
—
—
—
—
—
0
Bit7~1
Unimplemented,readas"0"
Bit0
DMBP0:SelectDataMemoryBanks
0:Bank0
1:Bank1
Accumulator – ACC
TheAccumulator is central to the operation of any microcontroller and is closely related with
operationscarriedoutbytheALU.TheAccumulatoristheplacewhereallintermediateresults
fromtheALUarestored.WithouttheAccumulatoritwouldbenecessarytowritetheresultof
eachcalculationorlogicaloperationsuchasaddition,subtraction,shift,etc.,totheDataMemory
resultinginhigherprogrammingandtimingoverheads.Datatransferoperationsusuallyinvolve
thetemporarystoragefunctionoftheAccumulator;forexample,whentransferringdatabetween
oneuser-definedregisterandanother,itisnecessarytodothisbypassingthedatathroughthe
Accumulatorasnodirecttransferbetweentworegistersispermitted.
Program Counter Low Register – PCL
Toprovideadditionalprogramcontrolfunctions,thelowbyteoftheProgramCounterismade
accessibletoprogrammersbylocatingitwithintheSpecialPurposeareaoftheDataMemory.By
manipulatingthisregister,directjumpstootherprogramlocationsareeasilyimplemented.Loading
avaluedirectlyintothisPCLregisterwillcauseajumptothespeciiedProgramMemorylocation,
however,astheregisterisonly8-bitwide,onlyjumpswithinthecurrentProgramMemorypageare
permitted.Whensuchoperationsareused,notethatadummycyclewillbeinserted.
Look-up Table Registers – TBLP, TBHP, TBLH
Thesethreespecialfunctionregistersareusedtocontroloperationofthelook-uptablewhichis
storedintheProgramMemory.TBLPandTBHParethetablepointersandindicatethelocation
wherethetabledataislocated.Theirvaluemustbesetupbeforeanytablereadcommandsare
executed.Theirvaluecanbechanged,forexampleusingthe“INC”or“DEC”instructions,allowing
foreasytabledatapointingandreading.TBLHisthelocationwherethehighorderbyteofthetable
dataisstoredafteratablereaddatainstructionhasbeenexecuted.Notethatthelowerordertable
databyteistransferredtoauserdeinedlocation.
Rev. 1.00
27
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Status Register – STATUS
This8-bitregistercontainsthezerolag(Z),carrylag(C),auxiliarycarrylag(AC),overlowlag
(OV),powerdownlag(PDF),andwatchdogtime-outlag(TO).Thesearithmetic/logicaloperation
andsystemmanagementlagsareusedtorecordthestatusandoperationofthemicrocontroller.
WiththeexceptionoftheTOandPDFlags,bitsinthestatusregistercanbealteredbyinstructions
likemostotherregisters.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFlag.
Inaddition,operationsrelatedtothestatusregistermaygivedifferentresultsduetothedifferent
instructionoperations.TheTOlagcanbeaffectedonlybyasystempower-up,aWDTtime-outor
byexecutingthe“CLRWDT”or“HALT”instruction.ThePDFlagisaffectedonlybyexecuting
the“HALT”or“CLRWDT”instructionorduringasystempower-up.
TheZ,OV,ACandClagsgenerallyrelectthestatusofthelatestoperations.
• Cissetifanoperationresultsinacarryduringanadditionoperationorifaborrowdoesnottake
placeduringasubtractionoperation;otherwiseCiscleared.Cisalsoaffectedbyarotatethrough
carryinstruction.
• ACissetifanoperationresultsinacarryoutofthelownibblesinaddition,ornoborrowfrom
thehighnibbleintothelownibbleinsubtraction;otherwiseACiscleared.
• Zissetiftheresultofanarithmeticorlogicaloperationiszero;otherwiseZiscleared.
• OVissetifanoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthe
highest-orderbit,orviceversa;otherwiseOViscleared.
• PDFisclearedbyasystempower-uporexecutingthe“CLRWDT”instruction.PDFissetby
executingthe“HALT”instruction.
• TOisclearedbyasystempower-uporexecutingthe“CLRWDT”or“HALT”instruction.TOis
setbyaWDTtime-out.
Inaddition,onenteringaninterruptsequenceorexecutingasubroutinecall,thestatusregisterwill
notbepushedontothestackautomatically.Ifthecontentsofthestatusregistersareimportantandif
thesubroutinecancorruptthestatusregister,precautionsmustbetakentocorrectlysaveit.
Rev. 1.00
28
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
STATUS Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
TO
PDF
OV
Z
AC
C
R/W
—
—
R
R
R/W
R/W
R/W
R/W
POR
—
—
0
0
×
×
×
×
"x" unknown
Rev. 1.00
Bit7~6
Unimplemented,readas"0"
Bit5
TO:WatchdogTime-Outlag
0:Afterpoweruporexecutingthe"CLRWDT"or"HALT"instruction
1:Awatchdogtime-outoccurred.
Bit4
PDF:Powerdownlag
0:Afterpoweruporexecutingthe"CLRWDT"instruction
1:Byexecutingthe"HALT"instruction
Bit3
OV:Overlowlag
0:Nooverlow
1:Anoperationresultsinacarryintothehighest-orderbitbutnotacarryoutofthe
highest-orderbitorviceversa.
Bit2
Z:Zerolag
0:Theresultofanarithmeticorlogicaloperationisnotzero
1:Theresultofanarithmeticorlogicaloperationiszero
Bit1
AC:Auxiliarylag
0:Noauxiliarycarry
1:Anoperationresultsinacarryoutofthelownibblesinaddition,ornoborrow
fromthehighnibbleintothelownibbleinsubtraction
Bit0
C:Carrylag
0:Nocarry-out
1:Anoperationresultsinacarryduringanadditionoperationorifaborrowdoes
nottakeplaceduringasubtractionoperation
Cisalsoaffectedbyarotatethroughcarryinstruction.
29
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
EEPROM Data Memory
OneofthespecialfeaturesinthedeviceisitsinternalEEPROMDataMemory.EEPROM,which
standsforElectricallyErasableProgrammableReadOnlyMemory,isbyitsnatureanon-volatile
formofmemory,withdataretentionevenwhenitspowersupplyisremoved.Byincorporating
thiskindofdatamemory,awholenewhostofapplicationpossibilitiesaremadeavailabletothe
designer.TheavailabilityofEEPROMstorageallowsinformationsuchasproductidentification
numbers,calibrationvalues,speciicuserdata,systemsetupdataorotherproductinformationto
bestoreddirectlywithintheproductmicrocontroller.Theprocessofreadingandwritingdatatothe
EEPROMmemoryhasbeenreducedtoaverytrivialaffair.
EEPROM Data Memory Structure
TheEEPROMDataMemorycapacityisupto64×8bits.UnliketheProgramMemoryandRAM
DataMemory,theEEPROMDataMemoryisnotdirectlymappedandisthereforenotdirectly
accessible in the same way as the other types of memory. Read andWrite operations to the
EEPROMarecarriedoutinsinglebyteoperationsusinganaddressanddataregisterinBank0and
asinglecontrolregisterinBank1.
Device
Capacity
Address
BS83B08A-3/BS83B08A-4
64×8
00H~3FH
BS83B12A-3/BS83B12A-4
64×8
00H~3FH
BS83B16A-3/BS83B16A-4
64×8
00H~3FH
EEPROM Registers
ThreeregisterscontroltheoveralloperationoftheinternalEEPROMDataMemory.Thesearethe
addressregister,EEA,thedataregister,EEDandasinglecontrolregister,EEC.AsboththeEEA
andEEDregistersarelocatedinBank0,theycanbedirectlyaccessedinthesamewayasanyother
SpecialFunctionRegister.TheEECregisterhowever,beinglocatedinBank1,cannotbedirectly
addresseddirectlyandcanonlybereadfromorwrittentoindirectlyusingtheMP1MemoryPointer
andIndirectAddressingRegister,IAR1.BecausetheEECcontrolregisterislocatedataddress40H
inBank1,theMP1MemoryPointermustirstbesettothevalue40HandtheBankPointerregister,
BP,settothevalue,01H,beforeanyoperationsontheEECregisterareexecuted.
EEPROM Control Registers List
Name
Bit
7
6
5
4
3
2
1
0
EEA
—
—
D5
D4
D3
D2
D1
D0
EED
D7
D6
D5
D4
D3
D2
D1
D0
EEC
—
—
—
—
WREN
WR
RDEN
RD
EEA Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
D5
D4
D3
D2
D1
D0
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
×
×
×
×
×
×
“×” unknown
Rev. 1.00
Bit7~6
Unimplemented,readas"0"
Bit5~0
DataEEPROMaddress
DataEEPROMaddressbit5~bit0
30
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
EED Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit7~0
DataEEPROMdata
DataEEPROMdatabit7~bit0
EEC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
WREN
WR
RDEN
RD
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
Bit7~4
Unimplemented,readas"0"
Bit3
WREN:DataEEPROMWriteEnable
0:Disable
1:Enable
This is the Data EEPROMWrite Enable Bit which must be set high before Data
EEPROMwriteoperationsarecarriedout.ClearingthisbittozerowillinhibitData
EEPROMwriteoperations.
Bit2
WR:EEPROMWriteControl
0:Writecyclehasinished
1:Activateawritecycle
ThisistheDataEEPROMWriteControlBitandwhensethighbytheapplication
programwillactivateawritecycle.Thisbitwillbeautomaticallyresettozerobythe
hardwareafterthewritecyclehasinished.Settingthisbithighwillhavenoeffectif
theWRENhasnotirstbeensethigh.
Bit1
RDEN:DataEEPROMReadEnable
0:Disable
1:Enable
This is the Data EEPROM Read Enable Bit which must be set high before Data
EEPROMreadoperationsarecarriedout.ClearingthisbittozerowillinhibitData
EEPROMreadoperations.
Bit0
RD:EEPROMReadControl
0:Readcyclehasinished
1:Activateareadcycle
ThisistheDataEEPROMReadControlBitandwhensethighbytheapplication
programwillactivateareadcycle.Thisbitwillbeautomaticallyresettozerobythe
hardwareafterthereadcyclehasinished.Settingthisbithighwillhavenoeffectif
theRDENhasnotirstbeensethigh.
Note:TheWREN,WR,RDENandRDcannotbesetto“1”atthesametimeinoneinstruction.
TheWRandRDcannotbesetto“1”atthesametime.
Rev. 1.00
31
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Reading Data from the EEPROM
ToreaddatafromtheEEPROM,thereadenablebit,RDEN,intheEECregistermustirstbeset
hightoenablethereadfunction.TheEEPROMaddressofthedatatobereadmustthenbeplaced
intheEEAregister.IftheRDbitintheEECregisterisnowsethigh,areadcyclewillbeinitiated.
SettingtheRDbithighwillnotinitiateareadoperationiftheRDENbithasnotbeenset.When
thereadcycleterminates,theRDbitwillbeautomaticallyclearedtozero,afterwhichthedatacan
bereadfromtheEEDregister.ThedatawillremainintheEEDregisteruntilanotherreadorwrite
operationisexecuted.TheapplicationprogramcanpolltheRDbittodeterminewhenthedatais
validforreading.
Writing Data to the EEPROM
TowritedatatotheEEPROM,thewriteenablebit,WREN,intheEECregistermustirstbeset
hightoenablethewritefunction.TheEEPROMaddressofthedatatobewrittenmustthenbe
placedintheEEAregisterandthedataplacedintheEEDregister.IftheWRbitintheEECregister
isnowsethigh,aninternalwritecyclewillthenbeinitiated.SettingtheWRbithighwillnotinitiate
awritecycleiftheWRENbithasnotbeenset.AstheEEPROMwritecycleiscontrolledusingan
internaltimerwhoseoperationisasynchronoustomicrocontrollersystemclock,acertaintimewill
elapsebeforethedatawillhavebeenwrittenintotheEEPROM.Detectingwhenthewritecycle
hasinishedcanbeimplementedeitherbypollingtheWRbitintheEECregisterorbyusingthe
EEPROMinterrupt.Whenthewritecycleterminates,theWRbitwillbeautomaticallyclearedto
zerobythemicrocontroller,informingtheuserthatthedatahasbeenwrittentotheEEPROM.The
applicationprogramcanthereforepolltheWRbittodeterminewhenthewritecyclehasended.
Write Protection
Protection against inadvertent write operation is provided in several ways.After the device is
powered-on theWrite Enable bit in the control register will be cleared preventing any write
operations.Alsoatpower-ontheBankPointer,BP,willberesettozero,whichmeansthatData
MemoryBank0willbeselected.AstheEEPROMcontrolregisterislocatedinBank1,thisaddsa
furthermeasureofprotectionagainstspuriouswriteoperations.Duringnormalprogramoperation,
ensuringthattheWriteEnablebitinthecontrolregisterisclearedwillsafeguardagainstincorrect
writeoperations.
EEPROM Interrupt
TheEEPROMwriteinterruptisgeneratedwhenanEEPROMwritecyclehasended.TheEEPROM
interruptmustfirstbeenabledbysettingtheDEEbitintherelevantinterruptregister.Whenan
EEPROMwritecycleends,theDEFrequestlagwillbeset.Iftheglobal,EEPROMisenabledand
thestackisnotfull,ajumptotheassociatedInterruptvectorwilltakeplace.Whentheinterruptis
serviced,theEEPROMinterruptlagwillautomaticallyreset.Moredetailscanbeobtainedinthe
Interruptsection.
Rev. 1.00
32
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Programming Considerations
CaremustbetakenthatdataisnotinadvertentlywrittentotheEEPROM.ProtectioncanbePeriodic
byensuringthattheWriteEnablebitisnormallyclearedtozerowhennotwriting.AlsotheBank
PointercouldbenormallyclearedtozeroasthiswouldinhibitaccesstoBank1wheretheEEPROM
control register exist.Although certainly not necessary, consideration might be given in the
applicationprogramtothecheckingofthevalidityofnewwritedatabyasimplereadbackprocess.
WhenwritingdatatheWRbitmustbesethighimmediatelyaftertheWRENbithasbeensethigh,
toensurethewritecycleexecutescorrectly.TheglobalinterruptbitEMIshouldalsobecleared
beforeawritecycleisexecutedandthenre-enabledafterthewritecyclestarts.
Programming Examples
Reading Data from the EEPROM – Polling Method
MOV A, EEPROM_ADRES
MOV EEA, A
MOV A, 040H
MOV MP1, A
MOV A, 01H
MOV BP, A
SET IAR1.1
SET IAR1.0
BACK:
SZ IAR1.0
JMP BACK
CLR IAR1
CLR BP
MOV A, EED
MOV READ_DATA, A
; user deined address
; setup memory pointer MP1
; MP1 points to EEC register
; setup Bank Pointer
; set RDEN bit, enable read operations
; start Read Cycle - set RD bit
; check for read cycle end
; disable EEPROM write
; move read data to register
Writing Data to the EEPROM – Polling Method
CLR EMI
MOV A, EEPROM_ADRES
MOV EEA, A
MOV A, EEPROM_DATA
MOV EED, A
MOV A, 040H
MOV MP1, A
MOV A, 01H
MOV BP, A
SET IAR1.3
SET IAR1.2
SET EMI
BACK:
SZ IAR1.2
JMP BACK
CLR IAR1
CLR BP
Rev. 1.00
; user deined address
; user deined data
; setup memory pointer MP1
; MP1 points to EEC register
; setup Bank Pointer
; set WREN bit, enable write operations
; start Write Cycle - set WR bit
; check for write cycle end
; disable EEPROM write
33
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Oscillator
Various oscillator options offer the user a wide range of functions according to their various
application requirements.The flexible features of the oscillator functions ensure that the best
optimisationcanbeachievedintermsofspeedandpowersaving.Oscillatorselectionsandoperation
areselectedthroughregisters.
Oscillator Overview
Inadditiontobeingthesourceofthemainsystemclocktheoscillatorsalsoprovideclocksources
fortheWatchdogTimerandTimeBaseInterrupts.Fullyintegratedinternaloscillators,requiringno
externalcomponents,areprovidedtoformawiderangeofbothfastandslowsystemoscillators.
Thehigherfrequencyoscillatorsprovidehigherperformancebutcarrywithitthedisadvantageof
higherpowerrequirements,whiletheoppositeisofcoursetrueforthelowerfrequencyoscillators.
Withthecapabilityofdynamicallyswitchingbetweenfastandslowsystemclock,thedevicehasthe
lexibilitytooptimizetheperformance/powerratio,afeatureespeciallyimportantinpowersensitive
portableapplications.
Name
Freq.
Internal High Speed RC
Type
HIRC
8/12/16MHz
Internal Low Speed RC
LIRC
32kHz
Oscillator Types
System Clock Conigurations
Therearetwomethodsofgeneratingthesystemclock,ahighspeedoscillatorandalowspeed
oscillator.Thehighspeedoscillatoristheinternal8MHz,12MHz,16MHzRCoscillator.Thelow
speedoscillatoristheinternal32kHz(LIRC)oscillator.Selectingwhethertheloworhighspeed
oscillatorisusedasthesystemoscillatorisimplementedusingtheHLCLKbitandCKS2~CKS0
bitsintheSMODregisterandasthesystemclockcanbedynamicallyselected.
Theactualsourceclockusedforthehighspeedandthelowspeedoscillatorsischosenviaregisters.
ThefrequencyoftheslowspeedorhighspeedsystemclockisalsodeterminedusingtheHLCLK
bit and CKS2~CKS0 bits in the SMOD register. Note that two oscillator selections must be
madenamelyonehighspeedandonelowspeedsystemoscillators.Itisnotpossibletochoosea
no-oscillatorselectionforeitherthehighorlowspeedoscillator.
High Speed
Oscillator
HIRC
fH
6- stage Prescaler
fH /2
fH /4
fH /8
fH /16
fSYS
fH /32
Low Speed
Oscillator
LIRC
fH /64
fSUB
HLCLK,
CKS2~ CKS0 bits
System Clock Conigurations
Rev. 1.00
34
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Internal RC Oscillator – HIRC
TheinternalRCoscillatorisafullyintegratedsystemoscillatorrequiringnoexternalcomponents.
TheinternalRCoscillatorhasapowerondefaultfrequencyof8MHzbutcanbeselectedtobe
either8MHz,12MHzor16MHzusingtheHIRCS1andHIRCS0bitsintheCTRLregister.Device
trimmingduringthemanufacturingprocessandtheinclusionofinternalfrequencycompensation
circuitsareusedtoensurethattheinluenceofthepowersupplyvoltage,temperatureandprocess
variationsontheoscillationfrequencyareminimised.
Internal 32kHz Oscillator – LIRC
The Internal 32kHz System Oscillator is the low frequency oscillator. It is a fully integrated
RCoscillatorwithatypicalfrequencyof32kHzat5V,requiringnoexternalcomponentsforits
implementation.Devicetrimmingduringthemanufacturingprocessandtheinclusionofinternal
frequencycompensationcircuitsareusedtoensurethattheinluenceofthepowersupplyvoltage,
temperatureandprocessvariationsontheoscillationfrequencyareminimised.Afterpoweronthis
LIRCoscillatorwillbepermanentlyenabled;thereisnoprovisiontodisabletheoscillatorusing.
Operating Modes and System Clocks
Presentdayapplicationsrequirethattheirmicrocontrollershavehighperformancebutoftenstill
demandthattheyconsumeaslittlepoweraspossible,conlictingrequirementsthatareespecially
trueinbatterypoweredportableapplications.Thefastclocksrequiredforhighperformancewill
bytheirnatureincreasecurrentconsumptionandofcoursevice-versa,lowerspeedclocksreduce
current consumption.As Holtek has provided this device with both high and low speed clock
sourcesandthemeanstoswitchbetweenthemdynamically,theusercanoptimisetheoperationof
theirmicrocontrollertoachievethebestperformance/powerratio.
System Clocks
Themainsystemclock,cancomefromeitherahighfrequency,fH,orlowfrequency,fSUB,source,
andisselectedusingtheHLCLKbitandCKS2~CKS0bitsintheSMODregister.Boththehighand
lowspeedsystemclocksaresourcedfrominternalRCoscillators.
Rev. 1.00
35
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
System Clock Conigurations
Note:WhenthesystemclocksourcefSYSisswitchedtofSUBfromfH,thehighspeedoscillationwill
stoptoconservethepower.ThusthereisnofH~fH/64forperipheralcircuittouse.
System Operation Modes
There are five different modes of operation for the microcontroller, each one with its own
special characteristics and which can be chosen according to the specific performance and
power requirementsof the application.Therearetwomodesallowing normal operationof the
microcontroller,theNORMALModeandSLOWMode.Theremainingthreemodes,theSLEEP,
IDLE0andIDLE1ModeareusedwhenthemicrocontrollerCPUisswitchedofftoconservepower.
Operating
Mode
Rev. 1.00
Description
CPU
fSYS
fSUB
fS
NORMAL mode
On
fH~fH/64
On
On
SLOW mode
On
fSUB
On
On
ILDE0 mode
Off
Off
On
On
IDLE1 mode
Off
On
On
On
SLEEP mode
Off
Off
On
On
36
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
NORMAL Mode
Asthenamesuggeststhisisoneofthemainoperatingmodeswherethemicrocontrollerhasallof
itsfunctionsoperationalandwherethesystemclockisprovidedbythehighspeedoscillator.This
modeoperatesallowingthemicrocontrollertooperatenormallywithaclocksourcewillcomefrom
thehighspeedoscillator,HIRC.Thehighspeedoscillatorwillhoweverirstbedividedbyaratio
rangingfrom1to64,theactualratiobeingselectedbytheCKS2~CKS0andHLCLKbitsinthe
SMODregister.Althoughahighspeedoscillatorisused,runningthemicrocontrolleratadivided
clockratioreducestheoperatingcurrent.
SLOW Mode
Thisisalsoamodewherethemicrocontrolleroperatesnormallyalthoughnowwithaslowerspeed
clocksource.TheclocksourceusedwillbefromfSUB.Runningthemicrocontrollerinthismode
allowsittorunwithmuchloweroperatingcurrents.IntheSLOWMode,thefHisoff.
SLEEP Mode
TheSLEEPModeisenteredwhenanHALTinstructionisexecutedandwhentheIDLENbitinthe
SMODregisterislow.IntheSLEEPmodetheCPUwillbestopped.HoweverthefSUBclockswill
continuetoruntheWatchdogTimerwillcontinuetooperate.
IDLE0 Mode
TheIDLE0ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitinthe
SMODregisterishighandtheFSYSONbitintheCTRLregisterislow.IntheIDLE0Modethe
systemoscillatorwillbestopandwillthereforebeinhibitedfromdrivingtheCPU.
IDLE1 Mode
TheIDLE1ModeisenteredwhenaHALTinstructionisexecutedandwhentheIDLENbitin
theSMODregisterishighandtheFSYSONbitintheCTRLregisterishigh.IntheIDLE1Mode
thesystemoscillatorwillbeinhibitedfromdrivingtheCPUbutmaycontinuetoprovideaclock
sourcetokeepsomeperipheralfunctionsoperational.IntheIDLE1Mode,thesystemoscillatorwill
continuetorun,andthissystemoscillatormaybethehighspeedorlowspeedsystemoscillator.
Rev. 1.00
37
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Control Register
TheSMODregisterisusedtocontroltheinternalclockswithinthedevice.
SMOD Register
Bit
7
6
5
4
3
2
1
0
Name
CKS2
CKS1
CKS0
—
LTO
HTO
IDLEN
HLCLK
R/W
R/W
R/W
R/W
—
R
R
R/W
R/W
POR
0
0
0
—
0
0
1
1
Bit7~5
Bit4
Bit3
Bit2
Bit1
Bit0
Rev. 1.00
CKS2~CKS0:ThesystemclockselectionwhenHLCLKis“0”
000:fSUB(fLIRC)
001:fSUB(fLIRC)
010:fH/64
011:fH/32
100:fH/16
101:fH/8
110:fH/4
111:fH/2
Thesethreebitsareusedtoselectwhichclockisusedasthesystemclocksource.In
additiontothesystemclocksource,whichcanbeLIRC,adividedversionofthehigh
speedsystemoscillatorcanalsobechosenasthesystemclocksource.
Unimplemented,readas“0”
LTO:LIRCSystemOSCSSTreadylag
0:Notready
1:Ready
ThisisthelowspeedsystemoscillatorSSTreadylagwhichindicateswhenthelow
speedsystemoscillatorisstableafterpoweronresetorawake-uphasoccurred.The
lagwillchangetoahighlevelafter1~2cycles.
HTO:HIRCSystemOSCSSTreadylag
0:Notready
1:Ready
ThisisthehighspeedsystemoscillatorSSTreadylagwhichindicateswhenthehigh
speedsystemoscillatorisstableafterawake-uphasoccurred.Thislagisclearedto
“0”byhardwarewhenthedeviceispoweredonandthenchangestoahighlevelafter
thehighspeedsystemoscillatorisstable.Thereforethislagwillalwaysbereadas“1”
bytheapplicationprogramafterdevicepower-on.Thelagwillbelowwheninthe
SLEEPorIDLE0Modebutafterpoweronresetorawake-uphasoccurred,thelag
willchangetoahighlevelafter15~16clockcyclesiftheHIRCoscillatorisused.
IDLEN:IDLEModeControl
0:Disable
1:Enable
ThisistheIDLEModeControlbitanddetermineswhathappenswhentheHALT
instructionisexecuted.Ifthisbitishigh,whenaHALTinstructionisexecutedthe
devicewillentertheIDLEMode.IntheIDLE1ModetheCPUwillstoprunning
butthesystemclockwillcontinuetokeeptheperipheralfunctionsoperational,if
FSYSONbitishigh.IfFSYSONbitislow,theCPUandthesystemclockwillallstop
inIDLE0mode.IfthebitislowthedevicewillentertheSLEEPModewhenaHALT
instructionisexecuted.
HLCLK:SystemClockSelection
0:fH/2~fH/64orfSUB
1:fH
This bit is used to select if the fH clock or the fH/2~fH/64 or fSUB clock is used as
thesystemclock.WhenthebitishighthefHclockwillbeselectedandiflowthe
fH/2~fH/64orfSUBclockwillbeselected.WhensystemclockswitchesfromthefHclock
tothefSUBclockandthefHclockwillbeautomaticallyswitchedofftoconservepower.
38
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
CTRL Register
Bit
7
6
5
4
3
2
1
0
Name
FSYSON
—
HIRCS1
HIRCS0
—
R/W
R/W
—
R/W
R/W
—
LVRF
LRF
WRF
R/W
R/W
POR
0
—
0
0
—
R/W
×
0
0
“×” unknow
Bit7
Rev. 1.00
FSYSON:fSYSControlinIDLEMode
0:Disable
1:Enable
Bit6
Unimplemented,readas"0"
Bit5~4
HIRCS1~HIRCS0:Highfrequencyclockselect
00:8MHz
01:16MHz
10:12MHz
11:8MHz
Bit3
Unimplemented,readas"0"
Bit2
LVRF:LVRfunctionresetlag
0:Notoccur
1:Occurred
Thisbitissetto1whenaspeciicLowVoltageResetsituationconditionoccurs.This
bitcanonlybeclearedto0bytheapplicationprogram.
Bit1
LRF:LVRCControlregistersoftwareresetlag
0:Notoccur
1:Occurred
Thisbitissetto1iftheLVRCregistercontainsanynondeinedLVRvoltageregister
values.Thisineffectactslikeasoftwareresetfunction.Thisbitcanonlybeclearedto
0bytheapplicationprogram.
Bit0
WRF:WDTControlregistersoftwareresetlag
0:Notoccur
1:Occurred
Thisbitissetto1bytheWDTControlregistersoftwareresetandclearedbythe
applicationprogram.Notethatthisbitcanonlybeclearedto0bytheapplication
program.
39
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Operating Mode Switching
Thedevicecanswitchbetweenoperatingmodesdynamicallyallowingtheusertoselectthebest
performance/powerratioforthepresenttaskinhand.Inthiswaymicrocontrolleroperationsthat
donotrequirehighperformancecanbeexecutedusingslowerclocksthusrequiringlessoperating
currentandprolongingbatterylifeinportableapplications.
In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed
usingtheHLCLKbitandCKS2~CKS0bitsintheSMODregisterwhileModeSwitchingfromthe
NORMAL/SLOWModestotheSLEEP/IDLEModesisexecutedviatheHALTinstruction.When
aHALTinstructionisexecuted,whetherthedeviceenterstheIDLEModeortheSLEEPModeis
determinedbytheconditionoftheIDLENbitintheSMODregisterandFSYSONintheCTRL
register.
WhentheHLCLKbitswitchestoalowlevel,whichimpliesthatclocksourceisswitchedfromthe
highspeedclocksource,fH,totheclocksource,fH/2~fH/64orfSUB.IftheclockisfromthefSUB,the
highspeedclocksourcewillstoprunningtoconservepower.Whenthishappensitmustbenoted
thatthefH/16andfH/64internalclocksourceswillalsostoprunning.Theaccompanyinglowchart
showswhathappenswhenthedevicemovesbetweenthevariousoperatingmodes.
Rev. 1.00
40
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
NORMAL Mode to SLOW Mode Switching
WhenrunningintheNORMALMode,whichusesthehighspeedsystemoscillator,andtherefore
consumes more power, the system clock can switch to run in the SLOW Mode by setting the
HLCLKbitto“0”andsettingtheCKS2~CKS0bitsto“000”or“001”intheSMODregister.This
willthenusethelowspeedsystemoscillatorwhichwillconsumelesspower.Usersmaydecideto
dothisforcertainoperationswhichdonotrequirehighperformanceandcansubsequentlyreduce
powerconsumption.
TheSLOWModeissourcedfromtheLIRCoscillatorandthereforerequiresthisoscillatortobe
stablebeforefullmodeswitchingoccurs.ThisismonitoredusingtheLTObitintheSMODregister.
SLOW Mode to NORMAL Mode Switching
InSLOWModethesystemusesLIRClowspeedsystemoscillator.ToswitchbacktotheNORMAL
Mode, where the high speed system oscillator is used, the HLCLK bit should be set to “1” or
HLCLKbitis“0”,butCKS2~CKS0issetto“010”,“011”,“100”,“101”,“110”or“111”.Asa
certainamountoftimewillberequiredforthehighfrequencyclocktostabilise,thestatusofthe
HTObitischecked.Theamountoftimerequiredforhighspeedsystemoscillatorstabilization
dependsuponwhichhighspeedsystemoscillatortypeisused.
Entering the SLEEP Mode
ThereisonlyonewayforthedevicetoentertheSLEEPModeandthatistoexecutethe“HALT”
instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“0”.Whenthis
instructionisexecutedundertheconditionsdescribedabove,thefollowingwilloccur:
• ThesystemclockandTimeBaseclockwillbestoppedandtheapplicationprogramwillstopat
the“HALT”instruction,butthefSUBclockwillbeon.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheWDTwillbeclearedandresumecounting.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownlag,PDF,willbesetandtheWatchdogtime-outlag,TO,
willbecleared.
Entering the IDLE0 Mode
ThereisonlyonewayforthedevicetoentertheIDLE0Modeandthatistoexecutethe“HALT”
instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andthe
FSYSONbitinCTRLregisterequalto“0”.Whenthisinstructionisexecutedundertheconditions
describedabove,thefollowingwilloccur:
• The system clock will be stopped and the application program will stop at the “HALT”
instruction,buttheTimeBaseandthelowfrequencyfSUBclockwillbeon.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheWDTwillbeclearedandresumecounting.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownlag,PDF,willbesetandtheWatchdogtime-outlag,TO,
willbecleared.
Rev. 1.00
41
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Entering the IDLE1 Mode
ThereisonlyonewayforthedevicetoentertheIDLE1Modeandthatistoexecutethe“HALT”
instructionintheapplicationprogramwiththeIDLENbitinSMODregisterequalto“1”andthe
FSYSONbitinCTRLregisterequalto“1”.Whenthisinstructionisexecutedundertheconditions
describedabove,thefollowingwilloccur:
• ThesystemclockandthelowfrequencyfSUBwillbeonandtheapplicationprogramwillstopat
the“HALT”instruction.
• TheDataMemorycontentsandregisterswillmaintaintheirpresentcondition.
• TheWDTwillbeclearedandresumecounting.
• TheI/Oportswillmaintaintheirpresentconditions.
• Inthestatusregister,thePowerDownlag,PDF,willbesetandtheWatchdogtime-outlag,TO,
willbecleared.
                       Rev. 1.00
42
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU

                                Standby Current Considerations
AsthemainreasonforenteringtheSLEEPorIDLEModeistokeepthecurrentconsumptionofthe
devicetoaslowavalueaspossible,perhapsonlyintheorderofseveralmicro-ampsexceptinthe
IDLE1Mode,thereareotherconsiderationswhichmustalsobetakenintoaccountbythecircuit
designerifthepowerconsumptionistobeminimised.SpecialattentionmustbemadetotheI/Opins
onthedevice.Allhigh-impedanceinputpinsmustbeconnectedtoeitheraixedhighorlowlevelas
anyloatinginputpinscouldcreateinternaloscillationsandresultinincreasedcurrentconsumption.
Thisalsoappliestodeviceswhichhavedifferentpackagetypes,astheremaybeunbonbedpins.
Thesemusteitherbesetupasoutputsorifsetupasinputsmusthavepull-highresistorsconnected.
Care must also be taken with the loads, which are connected to I/O pins, which are setup as
outputs.Theseshouldbeplacedinaconditioninwhichminimumcurrentisdrawnorconnected
onlytoexternalcircuitsthatdonotdrawcurrent,suchasotherCMOSinputs.IntheIDLE1Mode
thesystemoscillatorison,ifthesystemoscillatorisfromthehighspeedsystemoscillator,the
additionalstandbycurrentwillalsobeperhapsintheorderofseveralhundredmicro-amps.
Rev. 1.00
43
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Wake-up
AfterthesystementerstheSLEEPorIDLEMode,itcanbewokenupfromoneofvarioussources
listedasfollows:
• Anexternalreset
• AnexternalfallingedgeonPortA
• Asysteminterrupt
• AWDToverlow
If the system is woken up by an external reset, the device will experience a full system reset,
however,IfthedeviceiswokenupbyaWDToverlow,aWatchdogTimerresetwillbeinitiated.
Althoughbothofthesewake-upmethodswillinitiatearesetoperation,theactualsourceofthe
wake-upcanbedeterminedbyexaminingtheTOandPDFflags.ThePDFflagisclearedbya
systempower-uporexecutingtheclearWatchdogTimerinstructionsandissetwhenexecutingthe
“HALT”instruction.TheTOlagissetifaWDTtime-outoccurs,andcausesawake-upthatonly
resetstheProgramCounterandStackPointer,theotherlagsremainintheiroriginalstatus.
EachpinonPortAcanbesetupusingthePAWUregistertopermitanegativetransitiononthepin
towake-upthesystem.WhenaPortApinwake-upoccurs,theprogramwillresumeexecutionat
theinstructionfollowingthe“HALT”instruction.Ifthesystemiswokenupbyaninterrupt,then
twopossiblesituationsmayoccur.Theirstiswheretherelatedinterruptisdisabledortheinterrupt
isenabledbutthestackisfull,inwhichcasetheprogramwillresumeexecutionattheinstruction
followingthe“HALT”instruction.Inthissituation,theinterruptwhichwoke-upthedevicewillnot
beimmediatelyserviced,butwillratherbeservicedlaterwhentherelatedinterruptisinallyenabled
orwhenastacklevelbecomesfree.Theothersituationiswheretherelatedinterruptisenabledand
thestackisnotfull,inwhichcasetheregularinterruptresponsetakesplace.Ifaninterruptrequest
flagissethighbeforeenteringtheSLEEPorIDLEMode,thewake-upfunctionoftherelated
interruptwillbedisabled.
System Oscillator
Wake-up Time
(SLEEP Mode)
Wake-up Time
(IDLE0 Mode)
Wake-up Time
(IDLE1 Mode)
HIRC
15~16 HIRC cycles
1~2 HIRC cycles
LIRC
1~2 LIRC cycles
1~2 LIRC cycles
Wake-Up Time
Programming Considerations
ThehighspeedandlowspeedoscillatorsbothusethesameSSTcounter.Forexample,ifthesystem
iswokenupfromtheSLEEPModetheHIRCoscillatorneedstostart-upfromanoffstate.
IfthedeviceiswokenupfromtheSLEEPModetotheNORMALMode,thehighspeedsystem
oscillatorneedsanSSTperiod.ThedevicewillexecutetheirstinstructionafterHTOishigh.
Rev. 1.00
44
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Watchdog Timer
TheWatchdogTimerisprovidedtopreventprogrammalfunctionsorsequencesfromjumpingto
unknownlocations,duetocertainuncontrollableexternaleventssuchaselectricalnoise.
Watchdog Timer Clock Source
TheWatchdogTimerclocksourceisprovidedbytheinternalfSUBclockwhichisinturnsupplied
bytheLIRCoscillator.TheWatchdogTimersourceclockisthensubdividedbyaratioof28to
218togivelongertimeouts,theactualvaluebeingchosenusingtheWS2~WS0bitsintheWDTC
register.TheLIRCinternaloscillatorhasanapproximateperiodof32kHzatasupplyvoltageof5V.
However,itshouldbenotedthatthisspeciiedinternalclockperiodcanvarywithVDD,temperature
andprocessvariations.
Watchdog Timer Control Register
Asingleregister,WDTC,controlstherequiredtimeoutperiodaswellastheenableoperation.The
WDTCregisterisinitiatedto01010011BatanyresetbutkeepsunchangedattheWDTtime-out
occurrenceinapowerdownstate.
WDTC Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
WE4
WE3
WE2
WE1
WE0
WS2
WS1
WS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
1
0
1
0
0
1
1
Bit7~3
WE4 ~ WE0:WDTfunctionsoftwarecontrol
10101B:Enabled
01010B:Enabled(Default)
Othervalues:ResetMCU(Resetwillbeactiveafter2~3LIRCclockfordebouncetime.)
IftheMCUresetcausedbytheWE[4:0]inWDTCsoftwarereset,theWRFlagof
CTRLregisterwillbeset.
Bit2~0
WS2~WS0:WDTTime-outperiodselection
000:28/fSUB
001:210/fSUB
010:212/fSUB
011:214/fSUB
100:215/fSUB
101:216/fSUB
110:217/fSUB
111:218/fSUB
ThesethreebitsdeterminethedivisionratiooftheWatchdogTimersourceclock,
whichinturndeterminesthetimeoutperiod.
45
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
CTRL Register
Bit
7
6
5
4
3
2
1
0
Name
FSYSON
—
HIRCS1
HIRCS0
—
R/W
R/W
—
R/W
R/W
—
LVRF
LRF
WRF
R/W
R/W
POR
0
—
0
0
—
R/W
×
0
0
“×” unknown
Bit7
FSYSON:fSYSControlIDLEMode
Describeelsewhere
Bit6
Unimplemented,readas“0”
Bit5~4
HIRCS1~HIRCS0:Highfrequencyclockselect
Describeelsewhere
Bit3
Unimplemented,readas“0”
Bit2
LVRF:LVRfunctionresetlag
Describeelsewhere
Bit1
LRF:LVRControlregistersoftwareresetlag
Describeelsewhere
Bit0
WRF:WDTControlregistersoftwareresetlag
0:Notoccur
1:Occurred
Thisbitissetto1bytheWDTControlregistersoftwareresetandclearedbythe
applicationprogram.Notethatthisbitcanonlybeclearedto0bytheapplication
program.
Watchdog Timer Operation
InthesedevicestheWatchdogTimersuppliedbythefSUBoscillatorandisthereforealwayson.
TheWatchdogTimeroperatesbyprovidingadeviceresetwhenitstimeroverlows.Thismeans
thatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallyclearthe
WatchdogTimerbeforeitoverlowstopreventtheWatchdogTimerfromexecutingareset.Thisis
doneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumps
toanunknownlocation,orentersanendlessloop,theclearWDTinstructionwillnotbeexecutedin
thecorrectmanner,inwhichcasetheWatchdogTimerwilloverlowandresetthedevice.Thereare
ivebits,WE4~WE0,intheWDTCregistertoenabletheWDTfunction.WhentheWE4~WE0bits
valueisequalto01010Bor10101B,theWDTfunctionisenabled.However,iftheWE4~WE0bits
arechangedtoanyothervaluesexcept01010Band10101B,whichiscausedbytheenvironmental
noise,itwillresetthemicrocontrollerafter2~3LIRCclockcycles.
Undernormalprogramoperation,aWatchdogTimertime-outwillinitialiseadeviceresetandset
thestatusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimer
time-outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStack
Pointerwillbereset.FourmethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.
TheirstisaWDTreset,whichmeansacertainvalueiswrittenintotheWE4~WE0bitiledexcept
01010Band10101B,thesecondisusingtheWatchdogTimersoftwareclearinstructionsandthe
thirdisviaaHALTinstruction.
ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistouse
thesingle“CLRWDT”instructiontocleartheWDT.
Themaximumtime-outperiodiswhenthe218divisionratioisselected.Asanexample,witha
32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround8
secondsforthe218divisionratio,andaminimumtimeoutof7.8msforthe28divisionration.
Rev. 1.00
46
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
   ­
    
€ ‚ € ƒ
 Watchdog Timer
Reset and Initialisation
Aresetfunctionisafundamentalpartofanymicrocontrollerensuringthatthedevicecanbeset
to some predetermined condition irrespective of outside parameters.The mostimportant reset
conditionisafterpowerisirstappliedtothemicrocontroller.Inthiscase,internalcircuitrywill
ensurethatthemicrocontroller,afterashortdelay,willbeinawelldefinedstateandreadyto
executetheirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisters
willbesettodeinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgram
Counter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthe
lowestProgramMemoryaddress.
AnothertypeofresetiswhentheWatchdogTimeroverflowsandresetsthemicrocontroller.All
typesofresetoperationsresultindifferentregisterconditionsbeingsetup.Anotherresetexistsinthe
formofaLowVoltageReset,LVR,whereafullresetisimplementedinsituationswherethepower
supplyvoltagefallsbelowacertainthreshold.
Reset Functions
Thereareivewaysinwhichamicrocontrollerresetcanoccur,througheventsoccurringinternally:
• Power-onReset
Themostfundamentalandunavoidableresetistheonethatoccursafterpowerisirstappliedto
themicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromtheirst
memoryaddress,apower-onresetalsoensuresthatcertainotherregistersarepresettoknown
conditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuring
thatallpinswillbeirstsettoinputs.
VDD
Power-on
Reset
tRSTD
SST Time-out
Power-On Reset Timing Chart
Rev. 1.00
47
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
• LowVoltageReset–LVR
Themicrocontrollercontainsalowvoltageresetcircuitinordertomonitorthesupplyvoltageof
thedevice.TheLVRfunctionisalwaysenabledwithaspeciicLVRvoltage,VLVR.Ifthesupply
voltageofthedevicedropstowithinarangeof0.9V~VLVRsuchasmightoccurwhenchanging
thebattery,theLVRwillautomaticallyresetthedeviceinternallyandtheLVRFbitintheCTRL
registerwillalsobesetto1.ForavalidLVRsignal,alowvoltage,i.e.,avoltageintherange
between0.9V~VLVRmustexistforgreaterthanthevaluetLVRspeciiedintheA.C.characteristics.
Ifthelowvoltagestatedoesnotexceedthisvalue,theLVRwillignorethelowsupplyvoltage
andwillnotperformaresetfunction.TheactualVLVRissetbytheLVRCregister.Whenthis
happens,theLRFbitintheCTRLregisterwillbesetto1.
Low Voltage Reset Timing Chart
LVRC Register – BS83B08A-3/BS83B12A-3/BS83B16A-3
Bit
7
6
5
4
3
2
1
0
Name
LVS7
LVS6
LVS5
LVS4
LVS3
LVS2
LVS1
LVS0
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
POR
0
1
0
1
0
1
0
1
Bit7
LVS7 ~ LVS0:LVRVoltageSelectcontrol
01010101:2.55V(default)
00110011:2.55V
10011001:2.55V
10101010:2.55V
Othervalues:MCUreset(resetwillbeactiveafter2~3LIRCclockfordebouncetime)
Note:S/Wcanwrite00H~FFHtocontrolLVRvoltage,eventoS/WresetMCU.If
theMCUresetcausedLVRCsoftwarereset,theLRFlagofCTRLregisterwill
beset.
LVRC Register – BS83B08A-4/BS83B12A-4/BS83B16A-4
Bit
7
6
5
4
3
2
1
0
Name
LVS7
LVS6
LVS5
LVS4
LVS3
LVS2
LVS1
LVS0
R/W
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
POR
0
1
0
1
0
1
0
1
Bit7
Rev. 1.00
LVS7 ~ LVS0:LVRVoltageSelectcontrol
01010101:2.10V(default)
00110011:2.10V
10011001:2.10V
10101010:2.10V
Othervalues:MCUreset(resetwillbeactiveafter2~3LIRCclockfordebouncetime)
Note:S/Wcanwrite00H~FFHtocontrolLVRvoltage,eventoS/WresetMCU.If
theMCUresetcausedLVRCsoftwarereset,theLRFlagofCTRLregisterwill
beset.
48
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
CTRL Register
Bit
7
6
5
4
3
2
Name
R/W
POR
1
0
FSYSON
—
HIRCS1
HIRCS0
—
R/W
—
R/W
R/W
—
LVRF
LRF
WRF
R/W
R/W
0
—
0
0
—
R/W
×
0
0
“×” unknown
Rev. 1.00
Bit7
FSYSON:fSYSControlIDLEMode
Describeelsewhere
Bit6
Unimplemented,readas“0”
Bit5~4
HIRCS1~HIRCS0:Highfrequencyclockselect
Describeelsewhere
Bit3
Unimplemented,readas“0”
Bit2
LVRF:LVRfunctionresetlag
0:Notoccur
1:Occurred
Thisbitissetto1whenaspeciicLowVoltageResetsituationconditionoccurs.This
bitcanonlybeclearedto0bytheapplicationprogram.
Bit1
LRF:LVRControlregistersoftwareresetlag
0:Notoccur
1:Occurred
Thisbitissetto1iftheLVRCregistercontainsanynondeinedLVRvoltageregister
values.Thisineffectactslikeasoftwareresetfunction.Thisbitcanonlybeclearedto
0bytheapplicationprogram.
Bit0
WRF:WDTControlregistersoftwareresetlag
Describeelsewhere
49
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
• WatchdogTime-outResetduringNormalOperation
TheWatchdogtime-outResetduringnormaloperationisthesameasaLVRresetexceptthatthe
Watchdogtime-outlagTOwillbesetto“1”.
Note:tRSTDispower-ondelay,typicaltime=16.7ms
WDT Time-out Reset during Normal Operation Timing Chart
• WatchdogTime-outResetduringSLEEPorIDLEMode
TheWatchdogtime-outResetduringSLEEPorIDLEModeisalittledifferentfromotherkinds
ofreset.MostoftheconditionsremainunchangedexceptthattheProgramCounterandtheStack
Pointerwillbeclearedto“0”andtheTOlagwillbesetto“1”.RefertotheA.C.Characteristics
fortSSTdetails.
Note:ThetSSTis15~16clockcyclesifthesystemclocksourceisprovidedbytheHIRC.
ThetSSTis1~2clockfortheLIRC.
WDT Time-out Reset during SLEEP or IDLE Timing Chart
Reset Initial Conditions
Thedifferenttypesofresetdescribedaffecttheresetlagsindifferentways.Theselags,known
asPDF andTOarelocatedinthestatusregisterandarecontrolledbyvariousmicrocontroller
operations,suchastheSLEEPorIDLEModefunctionorWatchdogTimer.Theresetflagsare
showninthetable:
TO
PDF
RESET Conditions
0
0
u
u
LVR reset during NORMAL or SLOW Mode operation
1
u
WDT time-out reset during NORMAL or SLOW Mode operation
1
1
WDT time-out reset during IDLE or SLEEP Mode operation
Power-on reset
“u” stands for unchanged
Thefollowingtableindicatesthewayinwhichthevariouscomponentsofthemicrocontrollerare
affectedafterapower-onresetoccurs.
Item
Condition After RESET
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins counting
Timer/Eventer Counter
Timer/Eventer Counter will be turned off
Input/Output Ports
I/O ports will be setup as inputs
Stack Pointer
Stack Pointer will point to the top of the stack
Thedifferentkindsofresetsallaffecttheinternalregistersofthemicrocontrollerindifferentways.
Toensurereliablecontinuationofnormalprogramexecutionafteraresetoccurs,itisimportantto
knowwhatconditionthemicrocontrollerisinafteraparticularresetoccurs.Thefollowingtable
describeshoweachtypeofresetaffectseachofthemicrocontrollerinternalregisters.
Rev. 1.00
50
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
BS83B08A-3/BS83B08A-4 Register
Register
Rev. 1.00
LVR&power on
----
WDT Overlow
(Normal Mode)
IAR0
----
MP0
xxxx xxxx
xxxx xxxx
uuuu uuuu
IAR1
----
----
----
MP1
xxxx xxxx
----
----
----
WDT Overlow
(HALT Mode)
----
xxxx xxxx
----
-------
uuuu uuuu
BP
---- ---0
---- ---0
---- ---u
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
0000 0000
PCL
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
TBHP
---- xxxx
---- uuuu
---- uuuu
STATUS
--00 xxxx
--1u uuuu
- - 11 u u u u
SMOD
0 0 0 0 0 0 11
0 0 0 0 0 0 11
uuuu uuuu
CTRL
0-00 -x00
0-00 -x00
u-uu -uuu
INTEG
---- --00
---- --00
---- --uu
INTC0
-000 0000
-000 0000
-uuu uuuu
INTC1
-000 -000
-000 -000
-uuu -uuu
LVRC
0101 0101
0101 0101
uuuu uuuu
PA
1 - - 1 1111
1 - - 1 1111
u--u uuuu
PAC
1 - - 1 1111
1 - - 1 1111
u--u uuuu
PAPU
0--0 0000
0--0 0000
u--u uuuu
PAWU
0--0 0000
0--0 0000
u--u uuuu
WDTC
0 1 0 1 0 0 11
0 1 0 1 0 0 11
uuuu uuuu
TBC
--00 ----
--00 ----
--uu ----
TMR
0000 0000
0000 0000
uuuu uuuu
TMRC
--00 -000
--00 -000
--uu -uuu
EEA
- - 11 1111
- - 11 1111
--uu uuuu
EED
0000 0000
0000 0000
uuuu uuuu
PB
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
uuuu uuuu
PBPU
0000 0000
0000 0000
uuuu uuuu
I2CTOC
0000 0000
0000 0000
uuuu uuuu
SIMC0
0000 -00-
0000 -00-
uuuu -uu-
SIMC1
0000 -000
0000 -000
uuuu -uuu
SIMD
0000 0000
0000 0000
uuuu uuuu
SIMC2
- - 11 1111
- - 11 1111
--uu uuuu
SIMA
0000 0000
0000 0000
uuuu uuuu
TKTMR
0000 0000
0000 0000
uuuu uuuu
TKC0
-000 0000
-000 0000
-uuu uuuu
TK16DL
0000 0000
0000 0000
uuuu uuuu
TK16DH
0000 0000
0000 0000
uuuu uuuu
TKC1
---- --11
---- --11
---- --uu
TKM016DL
0000 0000
0000 0000
uuuu uuuu
TKM016DH
0000 0000
0000 0000
uuuu uuuu
TKM0ROL
0000 0000
0000 0000
uuuu uuuu
TKM0ROH
---- --00
---- --00
---- --uu
TKM0C0
0000 0000
0000 0000
uuuu uuuu
51
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Register
LVR&power on
WDT Overlow
(Normal Mode)
WDT Overlow
(HALT Mode)
TKM0C1
0-00 0000
0-00 0000
u-uu uuuu
TKM116DL
0000 0000
0000 0000
uuuu uuuu
TKM116DH
0000 0000
0000 0000
uuuu uuuu
TKM1ROL
0000 0000
0000 0000
uuuu uuuu
TKM1ROH
---- --00
---- --00
---- --uu
TKM1C0
0000 0000
0000 0000
uuuu uuuu
TKM1C1
0000 0000
0000 0000
uuuu uuuu
EEC
---- 0000
---- 0000
---- uuuu
WDT Overlow
(Normal Mode)
WDT Overlow
(HALT Mode)
Note:“-”notimplement
“u”standsfor“unchanged”
“x”standsfor“unknown”
BS83B12A-3/BS83B12A-4 Register
Register
Rev. 1.00
LVR&power on
IAR0
----
MP0
xxxx xxxx
----
xxxx xxxx
uuuu uuuu
IAR1
----
----
----
----
----
-------
----
-------
MP1
xxxx xxxx
xxxx xxxx
BP
---- ---0
---- ---0
uuuu uuuu
---- ---u
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
TBHP
---- xxxx
---- uuuu
---- uuuu
STATUS
--00 xxxx
--1u uuuu
- - 11 u u u u
uuuu uuuu
SMOD
0 0 0 0 0 0 11
0 0 0 0 0 0 11
CTRL
0-00 -x00
0-00 -x00
u-uu -uuu
INTEG
---- --00
---- --00
---- --uu
INTC0
-000 0000
-000 0000
-uuu uuuu
INTC1
-000 -000
-000 -000
-uuu -uuu
LVRC
0101 0101
0101 0101
uuuu uuuu
PA
1 - - 1 1111
1 - - 1 1111
u--u uuuu
PAC
1 - - 1 1111
1 - - 1 1111
u--u uuuu
PAPU
0--0 0000
0--0 0000
u--u uuuu
PAWU
0--0 0000
0--0 0000
u--u uuuu
WDTC
0 1 0 1 0 0 11
0 1 0 1 0 0 11
uuuu uuuu
TBC
--00 ----
--00 ----
--uu ----
TMR
0000 0000
0000 0000
uuuu uuuu
TMRC
--00 -000
--00 -000
--uu -uuu
EEA
- - 11 1111
- - 11 1111
--uu uuuu
EED
0000 0000
0000 0000
uuuu uuuu
PB
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
uuuu uuuu
PBPU
0000 0000
0000 0000
uuuu uuuu
I2CTOC
0000 0000
0000 0000
uuuu uuuu
SIMC0
0000 -00-
0000 -00-
uuuu -uu-
52
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Register
LVR&power on
WDT Overlow
(Normal Mode)
WDT Overlow
(HALT Mode)
SIMC1
0000 -000
0000 -000
uuuu -uuu
SIMD
0000 0000
0000 0000
uuuu uuuu
SIMC2
- - 11 1111
- - 11 1111
--uu uuuu
SIMA
0000 0000
0000 0000
uuuu uuuu
PC
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
uuuu uuuu
PCPU
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
TKTMR
0000 0000
0000 0000
TKC0
-000 0000
-000 0000
-uuu uuuu
TK16DL
0000 0000
0000 0000
uuuu uuuu
TK16DH
0000 0000
0000 0000
uuuu uuuu
TKC1
---- --11
---- --11
---- --uu
TKM016DL
0000 0000
0000 0000
uuuu uuuu
TKM016DH
0000 0000
0000 0000
uuuu uuuu
TKM0ROL
0000 0000
0000 0000
uuuu uuuu
TKM0ROH
---- --00
---- --00
---- --uu
TKM0C0
0000 0000
0000 0000
uuuu uuuu
TKM0C1
0-00 0000
0-00 0000
u-uu uuuu
TKM116DL
0000 0000
0000 0000
uuuu uuuu
TKM116DH
0000 0000
0000 0000
uuuu uuuu
TKM1ROL
0000 0000
0000 0000
uuuu uuuu
TKM1ROH
---- --00
---- --00
---- --uu
TKM1C0
0000 0000
0000 0000
uuuu uuuu
TKM1C1
0000 0000
0000 0000
uuuu uuuu
TKM216DL
0000 0000
0000 0000
uuuu uuuu
TKM216DH
0000 0000
0000 0000
uuuu uuuu
TKM2ROL
0000 0000
0000 0000
uuuu uuuu
TKM2ROH
---- --00
---- --00
---- --uu
TKM2C0
0000 0000
0000 0000
uuuu uuuu
TKM2C1
0000 0000
0000 0000
uuuu uuuu
EEC
---- 0000
---- 0000
---- uuuu
Note:“-”notimplement
“u”standsfor“unchanged”
“x”standsfor“unknown”
Rev. 1.00
53
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
BS83B16A-3/BS83B16A-4 Register
Register
Rev. 1.00
LVR&power on
----
WDT Overlow
(Normal Mode)
IAR0
----
MP0
xxxx xxxx
xxxx xxxx
IAR1
----
----
MP1
xxxx xxxx
BP
---- ---0
---- ---0
---- ---u
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
----
----
----
WDT Overlow
(HALT Mode)
----
xxxx xxxx
----
----
uuuu uuuu
----
----
uuuu uuuu
TBHP
---- xxxx
---- uuuu
---- uuuu
STATUS
--00 xxxx
--1u uuuu
- - 11 u u u u
SMOD
0 0 0 0 0 0 11
0 0 0 0 0 0 11
uuuu uuuu
CTRL
0-00 -x00
0-00 -x00
u-uu -uuu
INTEG
---- --00
---- --00
---- --uu
INTC0
-000 0000
-000 0000
-uuu uuuu
INTC1
-000 -000
-000 -000
-uuu -uuu
LVRC
0101 0101
0101 0101
uuuu uuuu
PA
1 - - 1 1111
1 - - 1 1111
u--u uuuu
PAC
1 - - 1 1111
1 - - 1 1111
u--u uuuu
PAPU
0--0 0000
0--0 0000
u--u uuuu
PAWU
0--0 0000
0--0 0000
u--u uuuu
WDTC
0 1 0 1 0 0 11
0 1 0 1 0 0 11
uuuu uuuu
TBC
--00 ----
--00 ----
--uu ----
TMR
0000 0000
0000 0000
uuuu uuuu
TMRC
--00 -000
--00 -000
--uu -uuu
EEA
- - 11 1111
- - 11 1111
--uu uuuu
EED
0000 0000
0000 0000
uuuu uuuu
PB
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
uuuu uuuu
PBPU
0000 0000
0000 0000
uuuu uuuu
I2CTOC
0000 0000
0000 0000
uuuu uuuu
SIMC0
0000 -00-
0000 -00-
uuuu -uu-
SIMC1
0000 -000
0000 -000
uuuu -uuu
SIMD
0000 0000
0000 0000
uuuu uuuu
SIMC2
- - 11 1111
- - 11 1111
--uu uuuu
SIMA
0000 0000
0000 0000
uuuu uuuu
PC
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
uuuu uuuu
PCPU
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
TKTMR
0000 0000
0000 0000
TKC0
-000 0000
-000 0000
-uuu uuuu
TK16DL
0000 0000
0000 0000
uuuu uuuu
TK16DH
0000 0000
0000 0000
uuuu uuuu
TKC1
---- --11
---- --11
---- --uu
TKM016DL
0000 0000
0000 0000
uuuu uuuu
TKM016DH
0000 0000
0000 0000
uuuu uuuu
54
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
LVR&power on
WDT Overlow
(Normal Mode)
WDT Overlow
(HALT Mode)
TKM0ROL
0000 0000
0000 0000
uuuu uuuu
TKM0ROH
---- --00
---- --00
---- --uu
TKM0C0
0000 0000
0000 0000
uuuu uuuu
TKM0C1
0-00 0000
0-00 0000
u-uu uuuu
TKM116DL
0000 0000
0000 0000
uuuu uuuu
TKM116DH
0000 0000
0000 0000
uuuu uuuu
TKM1ROL
0000 0000
0000 0000
uuuu uuuu
TKM1ROH
---- --00
---- --00
---- --uu
TKM1C0
0000 0000
0000 0000
uuuu uuuu
TKM1C1
0000 0000
0000 0000
uuuu uuuu
TKM216DL
0000 0000
0000 0000
uuuu uuuu
TKM216DH
0000 0000
0000 0000
uuuu uuuu
TKM2ROL
0000 0000
0000 0000
uuuu uuuu
TKM2ROH
---- --00
---- --00
---- --uu
TKM2C0
0000 0000
0000 0000
uuuu uuuu
TKM2C1
0000 0000
0000 0000
uuuu uuuu
TKM316DL
0000 0000
0000 0000
uuuu uuuu
TKM316DH
0000 0000
0000 0000
uuuu uuuu
TKM3ROL
0000 0000
0000 0000
uuuu uuuu
TKM3ROH
---- --00
---- --00
---- --uu
TKM3C0
0000 0000
0000 0000
uuuu uuuu
TKM3C1
0000 0000
0000 0000
uuuu uuuu
EEC
---- 0000
---- 0000
---- uuuu
Register
Note:“-”notimplement
“u”standsfor“unchanged”
“x”standsfor“unknown”
Rev. 1.00
55
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Input/Output Ports
HoltekmicrocontrollersofferconsiderablelexibilityontheirI/Oports.Withtheinputoroutput
designationofeverypinfullyunderuserprogramcontrol,pull-highselectionsforallportsand
wake-upselectionsoncertainpins,theuserisprovidedwithanI/Ostructuretomeettheneedsofa
widerangeofapplicationpossibilities.
Thedeviceprovidesbidirectionalinput/outputlineslabeledwithportnamesPA~PC.TheseI/O
portsaremappedtotheRAMDataMemorywithspeciicaddressesasshownintheSpecialPurpose
DataMemorytable.AlloftheseI/Oportscanbeusedforinputandoutputoperations.Forinput
operation,theseportsarenon-latching,whichmeanstheinputsmustbereadyattheT2risingedge
ofinstruction“MOVA,[m]”,wheremdenotestheportaddress.Foroutputoperation,allthedatais
latchedandremainsunchangeduntiltheoutputlatchisrewritten.
I/O Register List
BS83B08A-3/BS83B08A-4
Register
Name
Bit
7
6
5
4
3
2
1
0
PAWU
D7
—
—
D4
D3
D2
D1
D0
PAPU
D7
—
—
D4
D3
D2
D1
D0
PA
D7
—
—
D4
D3
D2
D1
D0
PAC
D7
—
—
D4
D3
D2
D1
D0
PBPU
D7
D6
D5
D4
D3
D2
D1
D0
PB
D7
D6
D5
D4
D3
D2
D1
D0
PBC
D7
D6
D5
D4
D3
D2
D1
D0
6
5
4
3
2
1
0
BS83B12A-3/BS83B12A-4
Register
Name
Rev. 1.00
Bit
7
PAWU
D7
—
—
D4
D3
D2
D1
D0
PAPU
D7
—
—
D4
D3
D2
D1
D0
D0
PA
D7
—
—
D4
D3
D2
D1
PAC
D7
—
—
D4
D3
D2
D1
D0
PBPU
D7
D6
D5
D4
D3
D2
D1
D0
PB
D7
D6
D5
D4
D3
D2
D1
D0
PBC
D7
D6
D5
D4
D3
D2
D1
D0
PCPU
—
—
—
—
D3
D2
D1
D0
PC
—
—
—
—
D3
D2
D1
D0
PCC
—
—
—
—
D3
D2
D1
D0
56
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
BS83B16A-3/BS83B16A-4
Bit
Register
Name
7
6
5
4
3
2
1
0
PAWU
D7
—
—
D4
D3
D2
D1
D0
PAPU
D7
—
—
D4
D3
D2
D1
D0
PA
D7
—
—
D4
D3
D2
D1
D0
PAC
D7
—
—
D4
D3
D2
D1
D0
PBPU
D7
D6
D5
D4
D3
D2
D1
D0
PB
D7
D6
D5
D4
D3
D2
D1
D0
PBC
D7
D6
D5
D4
D3
D2
D1
D0
PCPU
D7
D6
D5
D4
D3
D2
D1
D0
PC
D7
D6
D5
D4
D3
D2
D1
D0
PCC
D7
D6
D5
D4
D3
D2
D1
D0
Pull-high Resistors
Manyproductapplicationsrequirepull-highresistorsfortheirswitchinputsusuallyrequiringthe
useofanexternalresistor.Toeliminatetheneedfortheseexternalresistors,allI/Opins,when
coniguredasaninputhavethecapabilityofbeingconnectedtoaninternalpull-highresistor.These
pull-high resistors are selected using registers PAPU~PCPU, and are implemented using weak
PMOStransistors.
PAPU Register
Bit
7
6
5
4
3
2
1
0
Name
D7
—
—
D4
D3
D2
D1
D0
R/W
R/W
—
—
R/W
R/W
R/W
R/W
R/W
POR
0
—
—
0
0
0
0
0
Bit7
I/OPortAbit7Pull-HighControl
0:Disable
1:Enable
Bit6~5
Unimplemented,readas“0”
Bit4~0
I/OPortAbit4~bit0Pull-HighControl
0:Disable
1:Enable
PBPU Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit7~0
Rev. 1.00
I/OPortBbit7~bit0Pull-HighControl
0:Disable
1:Enable
57
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
PCPU Register – BS83B12A-3/BS83B12A-4
Bit
7
6
5
4
Name
—
—
—
—
D3
D2
D1
D0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
0
0
0
0
3
2
1
0
Bit7~4
Unimplemented,readas“0”
Bit3~0
I/OPortCbit3~bit0Pull-HighControl
0:Disable
1:Enable
3
2
1
0
PCPU Register – BS83B16A-3/BS83B16A-4
Bit
7
6
5
4
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit7~0
I/OPortCbit7~bit0Pull-HighControl
0:Disable
1:Enable
Port A Wake-up
TheHALTinstructionforcesthemicrocontrollerintotheSLEEPorIDLEModewhichpreserves
power,afeaturethatisimportantforbatteryandotherlow-powerapplications.Variousmethods
existtowake-upthemicrocontroller,oneofwhichistochangethelogicconditionononeofthePort
Apinsfromhightolow.Thisfunctionisespeciallysuitableforapplicationsthatcanbewokenup
viaexternalswitches.EachpinonPortAcanbeselectedindividuallytohavethiswake-upfeature
usingthePAWUregister.
PAWU Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
D7
—
—
D4
D3
D2
D1
D0
R/W
R/W
—
—
R/W
R/W
R/W
R/W
R/W
POR
0
—
—
0
0
0
0
0
Bit7
I/OPortAbit7Pull-HighControl
0:Disable
1:Enable
Bit6~5
Unimplemented,readas“0”
Bit4~0
I/OPortAbit4~bit0WakeUpControl
0:Disable
1:Enable
58
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
I/O Port Control Registers
Each I/O port has its own control register known as PAC~PCC, to control the input/output
configuration. With this control register, each CMOS output or input can be reconfigured
dynamicallyundersoftwarecontrol.EachpinoftheI/Oportsisdirectlymappedtoabitinits
associatedportcontrolregister.FortheI/Opintofunctionasaninput,thecorrespondingbitofthe
controlregistermustbewrittenasa“1”.Thiswillthenallowthelogicstateoftheinputpintobe
directlyreadbyinstructions.Whenthecorrespondingbitofthecontrolregisteriswrittenasa“0”,
theI/OpinwillbesetupasaCMOSoutput.Ifthepiniscurrentlysetupasanoutput,instructions
canstillbeusedtoreadtheoutputregister.However,itshouldbenotedthattheprogramwillinfact
onlyreadthestatusoftheoutputdatalatchandnottheactuallogicstatusoftheoutputpin.
PAC Register
Bit
7
6
5
4
3
2
1
0
Name
D7
—
—
D4
D3
D2
D1
D0
R/W
R/W
—
—
R/W
R/W
R/W
R/W
R/W
POR
1
—
—
1
1
1
1
1
3
2
1
0
Bit7
I/OPortAbit7Input/OutputControl
0:Disable
1:Enable
Bit6~5
Unimplemented,readas“0”
Bit4~0
I/OPortAbit4~bit0Input/OutputControl
0:Disable
1:Enable
PBC Register
Bit
7
6
5
4
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
Bit7~0
I/OPortBbit7~bit0Input/OutputControl
0:Output
1:Input
PCC Register – BS83B12A-3/BS83B12A-4
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
D3
D2
D1
D0
R/W
—
—
—
—
R/W
R/W
R/W
R/W
POR
—
—
—
—
1
1
1
1
Bit7~4
Unimplemented,readas“0”
Bit3~0
I/OPortCbit3~bit0Input/OutputControl
0:Disable
1:Enable
59
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
PCC Register – BS83B16A-3/BS83B16A-4
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
1
1
1
1
1
1
1
1
Bit7~0
I/OPortCbit7~bit0Input/OutputControl
0:Disable
1:Enable
I/O Pin Structures
Theaccompanying diagramsillustratetheinternalstructuresofsomegenericI/Opintypes.As
theexactlogicalconstructionoftheI/Opinwilldifferfromthesedrawings,theyaresuppliedasa
guideonlytoassistwiththefunctionalunderstandingoftheI/Opins.Thewiderangeofpin-shared
structuresdoesnotpermitalltypestobeshown.
Generic Input/Output Structure
Programming Considerations
Withintheuserprogram,oneoftheirstthingstoconsiderisportinitialisation.Afterareset,allof
theI/Odataandportcontrolregisterswillbesethigh.ThismeansthatallI/Opinswilldefaultto
aninputstate,thelevelofwhichdependsontheotherconnectedcircuitryandwhetherpull-high
selectionshavebeenchosen.Iftheportcontrolregisters,PAC~PCC,arethenprogrammedtosetup
somepinsasoutputs,theseoutputpinswillhaveaninitialhighoutputvalueunlesstheassociated
portdataregisters,PA~PC,areirstprogrammed.Selectingwhichpinsareinputsandwhichare
outputscanbeachievedbyte-widebyloadingthecorrectvaluesintotheappropriateportcontrol
registerorbyprogrammingindividualbitsintheportcontrolregisterusingthe“SET[m].i”and
“CLR[m].i”instructions.Notethatwhenusingthesebitcontrolinstructions,aread-modify-write
operationtakesplace.Themicrocontrollermustirstreadinthedataontheentireport,modifyitto
therequirednewbitvaluesandthenrewritethisdatabacktotheoutputports.
PortAhas theadditional capability ofproviding wake-up functions.Whenthedeviceisinthe
SLEEPorIDLEMode,variousmethodsareavailabletowakethedeviceup.Oneoftheseisahigh
tolowtransitionofanyofthePortApins.SingleormultiplepinsonPortAcanbesetuptohavethis
function.
Rev. 1.00
60
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Timer/Event Counter
Theprovisionoftimersformanimportantpartofanymicrocontroller,givingthedesignerameans
ofcarryingouttimerelatedfunctions.Thedevicescontainone8-bit.Theprovisionofaninternal
prescalertotheclockcircuitryongivesaddedrangetothetimer.
TherearetwotypesofregistersrelatedtotheTimer/EventCounters.Theirstistheregisterthat
containstheactualvalueofthetimerandintowhichaninitialvaluecanbepreloaded.Readingfrom
thisregisterretrievesthecontentsoftheTimer/EventCounter.Thesecondtypeofassociatedregister
istheTimerControlRegisterwhichdeinesthetimeroptions.
Timer/Event Counter
Coniguring the Timer/Event Counter Input Clock Source
TheTimer/EventCounterclocksourcecanoriginatefromeitherthesystemclockfSYSorthefSUB
oscillator,thechoiceofwhichisdeterminedbytheTSbitintheTMRCregister.Thisinternalclock
sourceisirstdividedbyaprescaler,thedivisionratioofwhichisconditionedbytheTimerControl
RegisterbitsTPSC0~TPSC2.
Timer Register – TMR
ThetimerregisterisaspecialfunctionregisterlocatedintheSpecialPurposeDataMemoryandis
theplacewheretheactualtimervalueisstored,itisknownasTMR.Thevalueinthetimerregister
increasesbyoneeachtimeaninternalclockpulseisreceivedThetimerwillcountfromtheinitial
valueloadedbythepreloadregistertothefullcountofFFHatwhichpointthetimeroverlowsand
aninternalinterruptsignalisgenerated.Thetimervaluewillthenberesetwiththeinitialpreload
registervalueandcontinuecounting.
NotethattoachieveamaximumfullrangecountofFFH,thepreloadregistermustirstbecleared
toallzeros.Itshouldbenotedthatafterpower-on,thepreloadregisterswillbeinanunknown
condition.NotethatiftheTimer/EventCounterisinanOFFconditionanddataiswrittentoits
preload register, this data will be immediately written into the actual counter. However, if the
counterisenabledandcounting,anynewdatawrittenintothepreloaddataregisterduringthis
periodwillremaininthepreloadregisterandwillonlybewrittenintotheactualcounterthenext
timeanoverlowoccurs.
Rev. 1.00
61
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Timer Control Register – TMRC
TheTimerControlRegisterisknownasTMRC.ItistheTimerControlRegistertogetherwiththe
corresponding timer registerthatcontrolthefulloperation oftheTimer/EventCounter. Before
thetimercanbeused,itisessentialthattheTimerControlRegisterisfullyprogrammedwiththe
rightdatatoensureitscorrectoperation,aprocessthatisnormallycarriedoutduringprogram
initialisation.
Thetimer-onbit,whichisbit4oftheTimerControlRegisterandknownasTON,providesthe
basicon/offcontrolofthetimer.Settingthebithighallowsthecountertorun,clearingthebitstops
thecounter.Bits0~2oftheTimerControlRegisterdeterminethedivisionratiooftheinputclock
prescaler.TheTSbitselectstheinternalclocksource.
TMRC Register
Bit
7
6
5
4
3
2
1
0
Name
—
R/W
—
—
TS
TON
—
TPSC2
TPSC1
TPSC0
—
R/W
R/W
—
R/W
R/W
POR
—
R/W
—
0
0
—
0
0
0
Bit7~6
Unimplemented,readas"0"
Bit5
TS:Timer/EventCounterClockSource
0:fSYS
1:fSUB
Bit4
TON:Timer/EventCounterCountingEnable
0:Disable
1:Enable
Bit3
Unimplemented,readas"0"
Bits2~0
TPSC2~TPSC0:Timerprescalerrateselection
Timerinternalclock=
000:fTP
001:fTP/2
010:fTP/4
011:fTP/8
100:fTP/16
101:fTP/32
110:fTP/64
111:fTP/128
Timer Operation
TheTimer/EventCounterisutilisedtomeasureixedtimeintervals,providinganinternalinterrupt
signaleachtimetheTimer/EventCounteroverflows.ThetimerinputclocksourceiseitherfSYS
orfSUB,however,thistimerclocksourceisfurtherdividedbyaprescaler,thevalueofwhichis
determinedbythebitsTPSC2~TPSC0intheTimerControlRegister.Thetimer-onbit,TONmust
be set high to enable the timer to run. Each time an internal clock transition occurs, the timer
incrementsbyone;whenthetimerisfullandoverlows,aninterruptsignalisgeneratedandthe
timerwillreloadthevaluealreadyloadedintothepreloadregisterandcontinuecounting.Atimer
overlowconditionandcorrespondinginternalinterruptisoneofthewake-upsources,however,the
internalinterruptscanbedisabledbyensuringthatthetimerenablebitintheinterruptregisteris
resettozero.
Rev. 1.00
62
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Prescaler
BitsTPSC0~TPSC2oftheTMRCregistercanbeusedtodefineadivisionratiofortheinternal
clocksourceoftheTimer/EventCounterenablinglongertimeoutperiodstobesetup.
Programming Considerations
WhentheTimer/EventCounterisread,orifdataiswrittentothepreloadregister,theclockis
inhibitedtoavoiderrors,howeverasthismayresultinacountingerror,thisshouldbetakeninto
accountbytheprogrammer.Caremustbetakentoensurethatthetimerisproperlyinitialisedbefore
usingitfortheirsttime.Theassociatedtimerenablebitsintheinterruptcontrolregistermustbe
properlysetotherwisetheinternalinterruptassociatedwiththetimerwillremaininactive.Itisalso
importanttoensurethataninitialvalueisirstloadedintothetimerregistersbeforethetimeris
switchedon;thisisbecauseafterpower-ontheinitialvaluesofthetimerregistersareunknown.
Afterthetimerhasbeeninitializedthetimercanbeturnedonandoffbycontrollingtheenablebit
inthetimercontrolregister.WhentheTimer/EventCounteroverlows,itscorrespondinginterrupt
requestflagintheinterruptcontrolregisterwillbeset.IftheTimer/EventCounterinterruptis
enabledthiswillinturngenerateaninterruptsignal.Howeverirrespectiveofwhethertheinterrupts
areenabledornot,aTimer/EventCounteroverlowwillalsogenerateawake-upsignalifthedevice
isinaPower-downcondition.Topreventsuchawake-upfromoccurring,thetimerinterruptrequest
lagshouldirstbesethighbeforeissuingtheHALTinstructiontoentertheIdle/SleepMode.
Touch Key Function
Eachdeviceprovidesmultipletouchkeyfunctions.Thetouchkeyfunctionisfullyintegratedand
requiresnoexternalcomponents,allowingtouchkeyfunctionstobeimplementedbythesimple
manipulationofinternalregisters.
Touch Key Structure
ThetouchkeysarepinsharedwiththePBandPClogicI/Opins,withthedesiredfunctionchosen
viaregisterbits.Keysareorganisedintogroupsoffour,witheachgroupknownasamoduleand
havingamodulenumber,M0toM3.EachmoduleisafullyindependentsetoffourTouchKeys
andeachTouchKeyhasitsownoscillator.Eachmodulecontainsitsowncontrollogiccircuitsand
registerset.Examinationoftheregisternameswillrevealthemodulenumberitisreferringto.
Device
BS83B08A-3/BS83B08A-4
8
BS83B12A-3/BS83B12A-4
12
BS83B16A-3/BS83B16A-4
Rev. 1.00
Keys - n
16
63
Touch Key Module
Touch Key
Shared I/O Pin
M0
K1~K4
PB0~PB3
M1
K5~K8
PB4~PB7
M0
K1~K4
PB0~PB3
M1
K5~K8
PB4~PB7
M2
K9~K12
PC0~PC3
M0
K1~K4
PB0~PB3
M1
K5~K8
PB4~PB7
M2
K9~K12
PC0~PC3
M3
K13~K16
PC4~PC7
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Touch Key Register Deinition
Eachtouchkeymodule,whichcontainsfourtouchkeyfunctions,hasitsownsuiteregisters.The
followingtableshowstheregistersetforeachtouchkeymodule.TheMnwithintheregistername
referstotheTouchKeymodulenumber,BS83B08A-3/BS83B08A-4hasarangeofM0toM1,
BS83B12A-3/BS83B12A-4hasarangeofM0toM2,BS83B16A-3/BS83B16A-4hasarangeof
M0toM3.
Name
Usage
TKTMR
Touch Key 8-bit timer/counter register
TKC0
Counter on-off and clear control/reference clock control/Start bit
TK16DL
Touch key module 16-bit counter low byte contents
TK16DH
Touch key module 16-bit counter high byte contents
TKC1
Touch key OSC frequency select
TKMn16DL
Module n 16-bit counter low byte contents
TKMn16DH
Module n 16-bit counter high byte contents
TKMnROL
Reference OSC internal capacitor select
TKMnROH
Reference OSC internal capacitor select
TKMnC0
Control Register 0
Multiplexer Key Select
TKMnC1
Control Register 1
Key oscillator control/Reference oscillator control/Touch key or I/O select
Register Listing
Bit
Register
Name
7
TKTMR
D7
D6
D5
D4
D3
D2
D1
D0
TKC0
—
TKRCOV
TKST
TKCFOV
TK16OV
TSCS
TK16S1
TK16S0
D0
6
5
4
3
2
1
0
TK16DL
D7
D6
D5
D4
D3
D2
D1
TK16DH
D7
D6
D5
D4
D3
D2
D1
D0
TKC1
—
—
—
—
—
—
TKFS1
TKFS0
TKMn16DL
D7
D6
D5
D4
D3
D2
D1
D0
TKMn16DH
D7
D6
D5
D4
D3
D2
D1
D0
TKMnROL
D7
D6
D5
D4
D3
D2
D1
D0
TKMnROH
—
—
—
—
—
—
D9
D8
TKMnC0
MnMXS1
MnMXS0
MnDFEN
MnFILEN
MnSOFC
MnSOF2
MnSOF1
MnSOF0
TKMnC1
MnTSS
—
MnROEN
MnKOEN
MnK4IO
MnK3IO
MnK2IO
MnK1IO
Touch Key Module (n=0~3)
TKTMR Register
Bit
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit7~0
Rev. 1.00
7
TouchKey8-bittimer/counterregister
Timeslotcounteroverlowset-uptimeis(256-TKTMR[7:0])×32
64
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
TKC0 Register
Bit
7
6
5
4
3
2
1
0
Name
—
TKRCOV
TKST
TKCFOV
TK16OV
TSCS
TK16S1
TK16S0
R/W
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
0
0
0
0
0
0
0
Bit7
Unimplemented,readas"0"
Bit6
TKRCOV:Timeslotcounteroverlowlag
0:Nooverlow
1:Overlow
Ifmodule0orAllmodule(selectbyTSCSbit)timeslotcounterisoverflow,the
TouchKeyInterruptrequestlagwillbeset(TKMF)andallmodulekeyOSCandref
OSCautostop.Allmodule16-bitC/Fcounter,16-bitcounter,5-bittimeslotcounter
and8-bittimeslottimercounterwillbeautomaticallyoff.
Bit5
TKST:StartTouchKeydetectioncontrolbit
0:Stopped
0 1:Started
In all modules the16-bit C/F counter, 16-bit counter, 5-bit time slot counter will
beautomatically clearedwhenthisbitisclearedto“0”(8-bitprogrammabletime
slotcounterwillnotbecleared,whichoverflowtimeissetupbyuser).Whenthis
bitchangesfromlowtohigh,the16-bitC/Fcounter,16-bitcounter,5-bittimeslot
counterand8-bittimeslottimercounterwillbeautomaticallyonandenablekeyOSC
andrefOSCoutputclockinputthesecounter.
Bit4
TKCFOV:Touchkeymodule16-bitC/Fcounteroverlowlag
0:Notoverlow
1:Overlow
Thisbitmustbeclearedbysoftware.
Bit3
TK16OV:Touchkeymodule16-bitcounteroverlowlag
0:Notoverlow
1:Overlow
Thisbitmustbeclearedbysoftware.
Bit2
TSCS:TouchKeytimeslotcounterselect
0:EachModuleuseowntimeslotcounter.
1:AllTouchKeyModuleuseModule0timeslotcounter.
Bit1~0
TK16S1~TK16S0:Thetouchkeymodule16-bitcounterclocksourceselect
00:fSYS
01:fSYS/2
10:fSYS/4
11:fSYS/8
TKC1 Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
TKFS1
TKFS0
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
1
1
Bit7~2
Unimplemented,readas"0"
Bit1~0
TKFS1~TKFS0:TouchkeyOSCfrequencyselect
00:500kHz
01:1000kHz
10:1500kHz
11:2000kHz
65
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
TK16DL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit7~0
Touchkeymodule16-bitcounterlowbytecontents
TK16DH Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit7~0
Touchkeymodule16-bitcounterhighbytecontents
TKMn16DL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit7~0
Modulen16-bitcounterlowbytecontents
TKMn16DH Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R
R
R
R
R
R
R
R
POR
0
0
0
0
0
0
0
0
Bit7~0
Modulen16-bitcounterhighbytecontents
TKMnROL Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit7~0
ReferenceOSCinernalcapacitorselect
OSCinernalcapacitorselect:(TKMnRO[9:0]×50pF)/1024
TKMnROH Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
D9
D8
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit7~2
Unimplemented,readas"0"
Bit1~0
ReferenceOSCinernalcapacitorselect
OSCinernalcapacitorselect:(TKMnRO[9:0]×50pF)/1024
66
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
TKMnC0 Register
Bit
Name
Rev. 1.00
7
6
5
4
3
2
MnMXS1 MnMXS0 MnDFEN MnFILEN MnSOFC MnSOF2
1
0
MnSOF1
MnSOF0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
Bit7~6
MnMXS1~MnMXS0:MultiplexerKeySelect
Bit5
MnDFEN:Multi-frequencycontrol
0:Disable
1:Enable
Bit4
MnFILEN:Filterfunctioncontrol
0:Disable
1:Enable
Bit3
MnSOFC:CtoFOSCfrequencyhoppingfunctioncontrol
0:ThefrequencyhoppingfunctioniscontrolledbyMnSOF2~MnSOF0bits
1:Thefrequencyhoppingfunctioniscontrolledbyhardwareregardlessofwhatis
thestateofMnSOF2~MnSOF0bits
Bit2~0
MnSOF2~ MnSOF0:SelectingkeyOSCandrefOSCfrequencyasCtoFOSCis
controlledbysoftware
000:1380kHz
001:1500kHz
010:1670kHz
011:1830kHz
100:2000kHz
101:2230kHz
110:2460kHz
111:2740kHz
Thefrequencywhichismentionedherewilllbechangedwhentheexternalorinternal
capacitoriswithdifferentvalue.ifthetouchkeyoperatesatafrequencyof2MHz,
userscanadjustthefrequencyinscalewhenselectotherfrequency.
67
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
TKMnC1 Register
Bit
7
6
Name
MnTSS
—
R/W
R/W
—
R/W
R/W
POR
0
—
0
0
4
MnROEN MnKOEN
3
2
1
0
MnK4IO
MnK3IO
MnK2IO
MnK1IO
R/W
R/W
R/W
R/W
0
0
0
0
Bit7
MnTSS:Timerslotcounterclockselect
0:Refoscillator
1:fSYS/4
Bit6
Unimplemented,readas"0"
Bit5
MnROEN:ReferenceOSCcontrol
0:Disable
1:Enable
Bit4
MnKOEN:KeyOSCcontrol
0:Disable
1:Enable
Bit3~0
MnK4IO~MnK1IO:I/Opinortouchkeyfunctionselect
MnK4OEN
M0
M1
M2
M3
PB3/Key4
PB7/Key8
PC3/Key12
PC7/Key16
0
I/O
1
Touch key
MnK3OEN
M0
M1
PB2/Key3
PB6/Key7
M2
M3
PC2/Key11
PC6/Key15
0
I/O
1
Touch key
MnK2OEN
M0
M1
PB1/Key2
PB5/Key6
M2
M3
PC1/Key10
PC5/Key14
0
I/O
1
Touch key
MnK1OEN
Rev. 1.00
5
M0
M1
M2
M3
PB0/Key1
PB4/Key5
PC0/Key9
PC4/Key13
0
I/O
1
Touch key input
68
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Touch Key Operation
Whenaingertouchesorisinproximitytoatouchpad,thecapacitanceofthepadwillincrease.
Byusingthiscapacitancevariationtochangeslightlythefrequencyoftheinternalsenseoscillator,
touchactionscanbesensedbymeasuringthesefrequencychanges.Usinganinternalprogrammable
divider the reference clock is used to generate a fixed time period. By counting a number of
generatedclockcyclesfromthesenseoscillatorduringthisixedtimeperiodtouchkeyactionscan
bedetermined.
During this reference clock fixed interval, the number of clock cycles generated by the sense
oscillatorismeasured,anditisthisvaluethatisusedtodetermineifatouchactionhasbeenmade
ornot.ThesedevicescontainfourtouchkeyinputswhicharesharedwithlogicalI/Opins,withthe
desiredfunctionselectedusingregisterbits.
UsingtheTSCSbitintheTKC0registercanselectthemodule0timeslotcounterasthetimeslot
counterforallmodules.Allmodulesusethesamestartedsignal.The16-bitC/Fcounter,16-bit
counter,5-bittimeslotcounterinallmoduleswillbeautomaticallyclearedwhenthisbitiscleared
to"0",butthe8-bitprogrammabletimeslotcounterwillnotbecleared.Theoverlowtimeissetup
byuser.Whenthisbitchangesfromlowtohigh,the16-bitC/Fcounter,16-bitcounter,5-bittime
slotcounterand8-bittimeslottimercounterwillbeautomaticallyswitchedon.
Thekeyoscillatorandreferenceoscillatorinallmoduleswillbeautomaticallystoppedandthe
16-bitC/Fcounter,16-bitcounter,5-bittimeslotcounterand8-bittimeslottimercounterwillbe
automaticallyswitchedoffwhenthe5-bittimeslotcounteroverlows.Theclocksourceforthetime
slotcounterand8+5bitcounter,issourcedfromthereferenceoscillatororfSYS/4.Thereference
oscillatorandkeyoscillatorwillbeenabledbysettingtheMnROENbitandMnKOENbitsinthe
TKMnC1register.
Whenthetimeslotcounterinallthetouchkeymodulesorinthetouchkeymodule0overlows,
anactualtouchkeyinterruptwilltakeplace.Thetouchkeysmentionedherearethekeyswhichare
enabled.
Eachtouchkeymodule,whichconsistsoffourtouchkeys,Key1~Key4iscontainedinmodule0,
Key5~Key8iscontainedinmodule1,Key9~Key12iscontainedinmodule2andKey13~Key16
iscontainedinthemodule3.Eachtouchkeymodulehasanidenticalstructure.
Rev. 1.00
69
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
KEY 1
KEY
OSC
KEY 2
KEY
OSC
Filter
MUX.
KEY 3
KEY
OSC
KEY 4
KEY
OSC
fSYS,fSYS/2,fSYS/4,fSYS/8
16-bit C/F
counter
Multi-frequency
Overflow
Overflow
16-bit counter
TK16S1~TK16S0
MnTSS
Ref OSC
MUX.
8-bit time slot
timer counter
5-bit time slot
counter
fSYS/4
8-bit time slot timer counter
preload register
Overflow
Overflow
Note:Eachtouchkeymodulecontainsthecontentinthedashline.
Touch Switch Module Block Diagram
Rev. 1.00
70
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Thetouchkeysenseoscilltorandreferenceoscillatortimingdiagramisshowninthefollowing
igure:
TKST
KEY OSC EN
REY OSC EN
.......
KEY OSC CLK
.......
fREF
ENCK
Hardware set to “0”
TSTMR overflow * 32
fTMCK (DFEN=0)
.......
fTMCK (DFEN=1)
.......
Time slot counter
overflow flag
Set Touch Key Interrupt request flag
Touch Key or I/O Function Select
Rev. 1.00
71
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Touch Key Interrupt
Thetouchkeyonlyhassingleinterrupt,whenthetimeslotcounterinallthetouchkeymodulesor
inthetouchkeymodule0overlows,anactualtouchkeyinterruptwilltakeplace.The16-bitC/F
counter,16-bitcounter,5-bittimeslotcounterand8-bittimeslotcounterinallmoduleswillbe
automaticallycleared.
TheTKCFOVflag,whichisthe16-bitC/Fcounteroverflowflagwillgohighwhenanyofthe
TouchKeyModule16-bitC/Fcounteroverlows.Asthislagwillnotbeautomaticallycleared,it
hastobeclearedbytheapplicationprogram.
Module0onlycontainsone16-bitcounter.TheTK16OVlag,whichisthe16-bitcounteroverlow
lagwillgohighwhenthe16-bitcounteroverlows.Asthislagwillnotbeautomaticallycleared,
ithastobeclearedbytheapplicationprogram.Moredetailsregardingthetouchkeyinterruptis
locatedintheinterruptsectionofthedatasheet.
Programming Considerations
Aftertherelevantregistersaresetup,thetouchkeydetectionprocessisinitiatedthechangingthe
TKSTbitfromlowtohigh.Thiswillenableandsynchroniseallrelevantoscillators.TheTKRCOV
lag,whichisthetimeslotcounterlagwillgohighandremainhighuntilthecounteroverlows.
Whenthishappensaninterruptsignalwillbegenerated.
When the external touch key size and layout are defined, their related capacitances will then
determinethesensoroscillatorfrequency.
Serial Interface Module – SIM
ThesedevicescontainaSerialInterfaceModule,whichincludeboththefourlineSPIinterfaceand
thetwolineI2Cinterfacetypes,toallowaneasymethodofcommunicationwithexternalperipheral
hardware.Havingrelativelysimplecommunicationprotocols,theseserialinterfacetypesallowthe
microcontrollertointerfacetoexternalSPIorI2Cbasedhardwaresuchassensors,Flashmemory
orEEPROMmemory,etc.TheSIMinterfacepinsarepin-sharedwithotherI/Opinsandmustbe
selectedusingtheSIMENbitintheSIMC0register.Asbothinterfacetypessharethesamepinsand
registers,thechoiceofwhethertheSPIorI2CtypeisusedismadeusingtheSIMoperatingmode
controlbits,namedSIM2~SIM0,intheSIMC0register.
SPI Interface
TheSPIinterfaceisoftenusedtocommunicatewithexternalperipheraldevicessuchassensors,
Flash or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI
interfaceisasynchronousserialdatainterfacethathasarelativelysimplecommunicationprotocol
simplifyingtheprogrammingrequirementswhencommunicatingwithexternalhardwaredevices.
Thecommunicationisfullduplexandoperatesasaslave/mastertype,wherethedevicecanbe
eithermasterorslave.AlthoughtheSPIinterfacespeciicationcancontrolmultipleslavedevices
fromasinglemaster,butthisdeviceprovidedonlyoneSCSpin.Ifthemasterneedstocontrol
multipleslavedevicesfromasinglemaster,themastercanuseI/Opintoselecttheslavedevices.
Rev. 1.00
72
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
SPI Interface Operation
TheSPIinterfaceisafullduplexsynchronousserialdatalink.Itisafourlineinterfacewithpin
names SDI, SDO, SCK and SCS. Pins SDI and SDO are theSerial Data Input and Serial Data
Outputlines,SCKistheSerialClocklineandSCSistheSlaveSelectline.AstheSPIinterfacepins
arepin-sharedwithnormalI/OpinsandwiththeI2Cfunctionpins,theSPIinterfacemustirstbe
enabledbysettingthecorrectbitsintheSIMC0andSIMC2registers.Communicationbetween
devicesconnectedtotheSPIinterfaceiscarriedoutinaslave/mastermodewithalldatatransfer
initiationsbeingimplementedbythemaster.TheMasteralsocontrolstheclocksignal.Asthedevice
onlycontainsasingleSCSpinonlyoneslavedevicecanbeutilized.TheSCSpiniscontrolledby
software,setCSENbitto"1"toenableSCSpinfunction,setCSENbitto"0"theSCSpinwillbeas
I/Ofunction.
SPI Master/Slave Connection
SPI Block Diagram
TheSPIfunctioninthisdeviceoffersthefollowingfeatures:
• Fullduplexsynchronousdatatransfer
• BothMasterandSlavemodes
• LSBirstorMSBirstdatatransmissionmodes
• Transmissioncompletelag
• Risingorfallingactiveclockedge
ThestatusoftheSPIinterfacepinsisdeterminedbyanumberoffactorssuchaswhetherthedevice
isinthemasterorslavemodeandupontheconditionofcertaincontrolbitssuchasCSENand
SIMEN.
Rev. 1.00
73
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
SPI Registers
TherearethreeinternalregisterswhichcontroltheoveralloperationoftheSPIinterface.Theseare
theSIMDdataregisterandtworegistersSIMC0andSIMC2.NotethattheSIMC1registerisonly
usedbytheI2Cinterface.
Bit
Register
Name
7
6
5
4
3
2
1
0
SIMC0
SIM2
SIM1
SIM0
—
—
—
SIMEN
—
SIMD
D7
D6
D5
D4
D3
D2
D1
D0
SIMC2
—
—
CKPOLB
CKEG
MLS
CSEN
WCOL
TRF
SIM Registers List
TheSIMDregisterisusedtostorethedatabeingtransmittedandreceived.Thesameregisterisused
byboththeSPIandI2Cfunctions.BeforethedevicewritesdatatotheSPIbus,theactualdatato
betransmittedmustbeplacedintheSIMDregister.AfterthedataisreceivedfromtheSPIbus,the
devicecanreaditfromtheSIMDregister.AnytransmissionorreceptionofdatafromtheSPIbus
mustbemadeviatheSIMDregister.
SIMD Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
“x” unknown
TherearealsotwocontrolregistersfortheSPIinterface,SIMC0andSIMC2.NotethattheSIMC2
registeralsohasthenameSIMAwhichisusedbytheI2Cfunction.TheSIMC1registerisnotused
bytheSPIfunction,onlybytheI2Cfunction.RegisterSIMC0isusedtocontroltheenable/disable
functionandtosetthedatatransmissionclockfrequency.AlthoughnotconnectedwiththeSPI
function,theSIMC0registerisalsousedtocontrolthePeripheralClockPrescaler.RegisterSIMC2
isusedforothercontrolfunctionssuchasLSB/MSBselection,writecollisionlagetc.
Rev. 1.00
74
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
SIMC0 Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
SIM2
SIM1
SIM0
—
—
—
SIMEN
—
R/W
R/W
R/W
R/W
—
—
—
R/W
—
POR
1
1
1
—
—
—
0
—
Bit7~5
SIM2~SIM0:SIMOperatingModeControl
000:SPImastermode;SPIclockisfSYS/4
001:SPImastermode;SPIclockisfSYS/16
010:SPImastermode;SPIclockisfSYS/64
011:SPImastermode;SPIclockisfSUB
100:SPImastermode;SPIclockisTMRfrequency/2
101:SPIslavemode
110:I2Cslavemode
111:Unusedmode
ThesebitssetuptheoveralloperatingmodeoftheSIMfunction.Aswellasselecting
iftheI2CorSPIfunction,theyareusedtocontroltheSPIMaster/Slaveselectionand
theSPIMasterclockfrequency.TheSPIclockisafunctionofthesystemclockbut
canalsobechosentobesourcedfromtheTimer/Eventcounter.IftheSPISlaveMode
isselectedthentheclockwillbesuppliedbyanexternalMasterdevice.
Bit4~2
Unimplemented,readas"0"
Bit1
SIMEN:SIMControl
0:Disable
1:Enable
Thebitistheoverallon/offcontrolfortheSIMinterface.WhentheSIMENbitis
clearedtozerotodisabletheSIMinterface,theSDI,SDO,SCKandSCS,orSDA
andSCLlineswillbeasI/OfunctionandtheSIMoperatingcurrentwillbereduced
toaminimumvalue.IftheSIMisconiguredtooperateasanSPIinterfaceviathe
SIM2~SIM0bits,thecontentsoftheSPIcontrolregisterswillremainattheprevious
settingswhentheSIMENbitchangesfromlowtohighandshouldthereforebeirst
initialisedbytheapplicationprogram.IftheSIMisconiguredtooperateasanI2C
interfaceviatheSIM2~SIM0bitsandtheSIMENbitchangesfromlowtohigh,the
contentsoftheI2CcontrolbitssuchasHTXandTXAKwillremainattheprevious
settingsandshouldthereforebeirstinitialisedbytheapplicationprogramwhilethe
relevantI2CflagssuchasHCF,HAAS,HBB,SRWandRXAKwillbesettotheir
defaultstates.
Bit0
Unimplemented,readas"0"
75
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
SIMC2 Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
—
—
CKPOLB
CKEG
MLS
CSEN
WCOL
TRF
R/W
—
—
R/W
R/W
R/W
R/W
R/W
R/W
POR
—
—
0
0
0
0
0
0
Bit7~6
Unimplemented,readas"0"
Bit5
CKPOLB:Determinesthebaseconditionoftheclockline
0:TheSCKlinewillbehighwhentheclockisinactive
1:TheSCKlinewillbelowwhentheclockisinactive
TheCKPOLBbitdeterminesthebaseconditionoftheclockline,ifthebitishigh,
thentheSCKlinewillbelowwhentheclockisinactive.WhentheCKPOLBbitis
low,thentheSCKlinewillbehighwhentheclockisinactive.
Bit4
CKEG:DeterminesSPISCKactiveclockedgetype
CKPOLB=0
0:SCKishighbaselevelanddatacaptureatSCKrisingedge
1:SCKishighbaselevelanddatacaptureatSCKfallingedge
CKPOLB=1
0:SCKislowbaselevelanddatacaptureatSCKfallingedge
1:SCKislowbaselevelanddatacaptureatSCKrisingedge
TheCKEGandCKPOLBbitsareusedtosetupthewaythattheclocksignaloutputs
andinputsdataontheSPIbus.Thesetwobitsmustbeconiguredbeforedatatransfer
isexecutedotherwiseanerroneousclockedgemaybegenerated.TheCKPOLBbit
determinesthebaseconditionoftheclockline,ifthebitishigh,thentheSCKline
willbelowwhentheclockisinactive.WhentheCKPOLBbitislow,thentheSCK
linewillbehighwhentheclockisinactive.
Bit3
MLS:SPIDatashiftorder
Thisisthedatashiftselectbitandisusedtoselecthowthedataistransferred,either
MSBorLSBirst.SettingthebithighwillselectMSBirstandlowforLSBirst.
Bit2
CSEN:SPISCSpinControl
0:Disable
1:Enable
TheCSENbitisusedasanenable/disablefortheSCSpin.Ifthisbitislow,thenthe
SCSpinwillbedisabledandplacedintoaloatingcondition.IfthebitishightheSCS
pinwillbeenabledandusedasaselectpin.
Bit1
WCOL:SPIWriteCollisionlag
0:Nocollision
1:Collision
TheWCOLlagisusedtodetectifadatacollisionhasoccurred.Ifthisbitishighit
meansthatdatahasbeenattemptedtobewrittentotheSIMDregisterduringadata
transferoperation.Thiswritingoperationwillbeignoredifdataisbeingtransferred.
Thebitcanbeclearedbytheapplicationprogram.
Bit0
TRF:SPITransmit/ReceiveCompletelag
0:Dataisbeingtransferred
1:SPIdatatransmissioniscompleted
TheTRFbitistheTransmit/ReceiveCompletelagandisset“1”automaticallywhen
anSPIdatatransmissioniscompleted,butmustsetto“0”bytheapplicationprogram.
Itcanbeusedtogenerateaninterrupt.
76
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
SPI Communication
AftertheSPIinterfaceisenabledbysettingtheSIMENbithigh,thenintheMasterMode,when
dataiswrittentotheSIMDregister,transmission/receptionwillbeginsimultaneously.Whenthe
datatransferiscomplete,theTRFflagwillbesetautomatically, butmustbeclearedusingthe
applicationprogram.IntheSlaveMode,whentheclocksignalfromthemasterhasbeenreceived,
anydataintheSIMDregisterwillbetransmittedandanydataontheSDIpinwillbeshiftedinto
theSIMDregister.ThemastershouldoutputanSCSsignaltoenabletheslavedevicebeforea
clocksignalisprovided.Theslavedatatobetransferredshouldbewellpreparedattheappropriate
momentrelativetotheSCSsignaldependingupontheconigurationsoftheCKPOLBbitandCKEG
bit.TheaccompanyingtimingdiagramshowstherelationshipbetweentheslavedataandSCSsignal
forvariousconigurationsoftheCKPOLBandCKEGbits.
TheSPIwillcontinuetofunctionevenintheIDLEMode.
SPI Master Mode Timing
SPI Slave Mode Timing – CKEG=0
Rev. 1.00
77
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
SPI Slave Mode Timing – CKEG=1
SPI Transfer Control Flowchart
Rev. 1.00
78
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
I2C Interface
The I 2C interface is used to communicate with external peripheral devices such as sensors,
EEPROMmemoryetc.OriginallydevelopedbyPhilips,itisatwolinelowspeedserialinterface
forsynchronousserialdatatransfer.Theadvantageofonlytwolinesforcommunication,relatively
simplecommunicationprotocolandtheabilitytoaccommodatemultipledevicesonthesamebus
hasmadeitanextremelypopularinterfacetypeformanyapplications.
I2C Master/Slave Bus Connection
I2C Interface Operation
TheI2Cserialinterfaceisatwolineinterface,aserialdataline,SDA,andserialclockline,SCL.As
manydevicesmaybeconnectedtogetheronthesamebus,theiroutputsarebothopendraintypes.
Forthisreasonitisnecessarythatexternalpull-highresistorsareconnectedtotheseoutputs.Note
thatnochipselectlineexists,aseachdeviceontheI2Cbusisidentiiedbyauniqueaddresswhich
willbetransmittedandreceivedontheI2Cbus.
WhentwodevicescommunicatewitheachotheronthebidirectionalI2Cbus,oneisknownasthe
masterdeviceandoneastheslavedevice.Bothmasterandslavecantransmitandreceivedata,
however,itisthemasterdevicethathasoverallcontrolofthebus.Forthisdevice,whichonly
operatesinslavemode,therearetwomethodsoftransferringdataontheI2Cbus,theslavetransmit
modeandtheslavereceivemode.
ThedebouncetimeoftheI2Cinterfaceusesthesystemclocktoineffectaddadebouncetimetothe
externalclocktoreducethepossibilityofglitchesontheclocklinecausingerroneousoperation.
Thedebouncetime,is2systemclocks.ToachievetherequiredI2Cdatatransferspeed,thereexists
arelationshipbetweenthesystemclock,fSYS,andtheI2Cdebouncetime.ForeithertheI2CStandard
or Fast mode operation, users must take care of the selected system clock frequency and the
conigureddebouncetimetomatchthecriterionshowninthefollowingtable.
I2C Debounce Time Selection
I2C Standard Mode (100kHz)
I2C Fast Mode (400kHz)
fSYS > 4MHz
fSYS > 10MHz
2 system clock debounce
I2C Minimum fSYS Frequency
Rev. 1.00
79
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
I2C Registers
TherearefourcontrolregistersassociatedwiththeI2Cbus,SIMC0,SIMC1,SIMAandI2CTOC
andonedataregister,SIMD.TheSIMDregister,whichisshownintheaboveSPIsection,isusedto
storethedatabeingtransmittedandreceivedontheI2Cbus.Beforethemicrocontrollerwritesdata
totheI2Cbus,theactualdatatobetransmittedmustbeplacedintheSIMDregister.Afterthedatais
receivedfromtheI2Cbus,themicrocontrollercanreaditfromtheSIMDregister.Anytransmission
orreceptionofdatafromtheI2CbusmustbemadeviatheSIMDregister.TheSIMpinsarepin
sharedwithotherI/OpinsandmustbeselectedusingtheSIMENbitintheSIMC0register.
NotethattheSIMAregisteralsohasthenameSIMC2whichisusedbytheSPIfunction.BitSIMEN
andbitsSIM2~SIM0inregisterSIMC0areusedbytheI2Cinterface.
Bit
Register
Name
7
6
5
4
3
2
1
0
SIMC0
SIM2
SIM1
SIM0
—
—
—
SIMEN
—
SIMC1
HCF
HAAS
HBB
HTX
TXAK
SRW
RNIC
RXAK
SIMD
D7
D6
D5
D4
D3
D2
D1
D0
SIMA
A6
A4
A3
A2
A1
A0
—
I2CTOC I2CTOEN
A5
I2CTOF
I2CTOS5 I2CTOS4 I2CTOS3 I2CTOS2 I2CTOS1 I2CTOS0
I2C Registers List
Rev. 1.00
80
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
SIMC0 Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
Name
SIM2
SIM1
SIM0
—
R/W
R/W
R/W
R/W
—
POR
1
1
1
—
—
0
—
—
SIMEN
—
—
—
R/W
—
—
0
—
Bit7~5
SIM2~SIM0:SIMOperatingModeControl
000:SPImastermode;SPIclockisfSYS/4
001:SPImastermode;SPIclockisfSYS/16
010:SPImastermode;SPIclockisfSYS/64
011:SPImastermode;SPIclockisfSUB
100:SPImastermode;SPIclockisTMRfrequency/2
101:SPIslavemode
110:I2Cslavemode
111:Unusedmode
ThesebitssetuptheoveralloperatingmodeoftheSIMfunction.Aswellasselecting
iftheI2CorSPIfunction,theyareusedtocontroltheSPIMaster/Slaveselectionand
theSPIMasterclockfrequency.TheSPIclockisafunctionofthesystemclockbut
canalsobechosentobesourcedfromtheTM0.IftheSPISlaveModeisselectedthen
theclockwillbesuppliedbyanexternalMasterdevice.
Bit4~2
Unimplemented,readas"0"
Bit1
SIMEN:SIMControl
0:Disable
1:Enable
Thebitistheoverallon/offcontrolfortheSIMinterface.WhentheSIMENbitis
clearedtozerotodisabletheSIMinterface,theSDI,SDO,SCKandSCS,orSDA
andSCLlineswillbeasI/OfunctionandtheSIMoperatingcurrentwillbereduced
toaminimumvalue.IftheSIMisconiguredtooperateasanSPIinterfaceviathe
SIM2~SIM0bits,thecontentsoftheSPIcontrolregisterswillremainattheprevious
settingswhentheSIMENbitchangesfromlowtohighandshouldthereforebeirst
initialisedbytheapplicationprogram.IftheSIMisconiguredtooperateasanI2C
interfaceviatheSIM2~SIM0bitsandtheSIMENbitchangesfromlowtohigh,the
contentsoftheI2CcontrolbitssuchasHTXandTXAKwillremainattheprevious
settingsandshouldthereforebeirstinitialisedbytheapplicationprogramwhilethe
relevantI2CflagssuchasHCF,HAAS,HBB,SRWandRXAKwillbesettotheir
defaultstates.
Bit0
Unimplemented,readas"0"
81
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
SIMC1 Register
Bit
7
6
5
4
3
2
1
0
Name
HCF
HAAS
HBB
HTX
TXAK
SRW
RNIC
RXAK
R/W
R
R
R
R/W
R/W
R
R/W
R
POR
1
0
0
0
0
0
0
1
Bit7
HCF:I2CBusdatatransfercompletionlag
0:Dataisbeingtransferred
1:Completionofan8-bitdatatransfer
The HCF flag is the data transfer flag.This flag will be zero when data is being
transferred.Uponcompletionofan8-bitdatatransfertheflagwillgohighandan
interruptwillbegenerated.
Bit6
HAAS:I2CBusaddressmatchlag
0:Notaddressmatch
1:Addressmatch
TheHASSlagistheaddressmatchlag.Thislagisusedtodetermineiftheslave
deviceaddressisthesameasthemastertransmitaddress.Iftheaddressesmatchthen
thisbitwillbehigh,ifthereisnomatchthenthelagwillbelow.
Bit5
HBB:I2CBusbusylag
0:I2CBusisnotbusy
1:I2CBusisbusy
TheHBBflagistheI2Cbusyflag.Thisflagwillbe“1”whentheI2Cbusisbusy
whichwilloccurwhenaSTARTsignalisdetected.Thelagwillbesetto“0”when
thebusisfreewhichwilloccurwhenaSTOPsignalisdetected.
Bit4
HTX:SelectI2Cslavedeviceistransmitterorreceiver
0:Slavedeviceisthereceiver
1:Slavedeviceisthetransmitter
Bit3
TXAK:I2CBustransmitacknowledgelag
0:Slavesendacknowledgelag
1:Slavedonotsendacknowledgelag
TheTXAKbitisthetransmitacknowledgelag.Aftertheslavedevicereceiptof8-bits
ofdata,thisbitwillbetransmittedtothebusonthe9thclockfromtheslavedevice.
TheslavedevicemustalwayssetTXAKbitto“0”beforefurtherdataisreceived.
Bit2
SRW:I2CSlaveRead/Writelag
0:Slavedeviceshouldbeinreceivemode
1:Slavedeviceshouldbeintransmitmode
The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether
the master device wishes to transmit or receive data from the I2C bus.When the
transmittedaddressandslaveaddressismatch,thatiswhentheHAASlagissethigh,
theslavedevicewillchecktheSRWlagtodeterminewhetheritshouldbeintransmit
modeorreceivemode.IftheSRWlagishigh,themasterisrequestingtoreaddata
fromthebus,sotheslavedeviceshouldbeintransmitmode.WhentheSRWflag
iszero,themasterwillwritedatatothebus,thereforetheslavedeviceshouldbein
receivemodetoreadthisdata.
Bit1
RNIC:I2CrunningusingInternalClockControl
0:I2Crunningusinginternalclock
1:I2CrunningnotusingInternalClock
The I2C module can run without using internal clock, and generate an interrupt
iftheSIMinterruptisenabled,whichcanbeusedinSLEEPMode,IDLEMode,
NORMAL(SLOW)Mode.Ifthisbitissetto“1”andMCUisin“HALT”,slave-receiver
canworkwellbutslave-transmitterdoesn’tworksinceitneedssystemclock.
Rev. 1.00
82
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Bit0
RXAK:I2CBusReceiveacknowledgelag
0:Slavereceiveacknowledgelag
1:Slavedonotreceiveacknowledgelag
TheRXAKflagisthereceiveracknowledgeflag.WhentheRXAKflagis“0”,it
meansthataacknowledgesignalhasbeenreceivedatthe9thclock,after8bitsofdata
havebeentransmitted.Whentheslavedeviceinthetransmitmode,theslavedevice
checkstheRXAKlagtodetermineifthemasterreceiverwishestoreceivethenext
byte.TheslavetransmitterwillthereforecontinuesendingoutdatauntiltheRXAK
lagis“1”.Whenthisoccurs,theslavetransmitterwillreleasetheSDAlinetoallow
themastertosendaSTOPsignaltoreleasetheI2CBus.
I2CTOC Register
Bit
7
6
Name
I2CTOEN
I2CTOF
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
0
0
0
0
0
0
0
0
I2CTOS5 I2CTOS4 I2CTOS3 I2CTOS2 I2CTOS1 I2CTOS0
Bit7
I2CTOEN:I CTime-outCountrol
0:Disable
1:Enable
Bit6
HAAS:Time-outlag
0:Notime-out
1:Time-outoccurred
Bit5~0
I2CTOS5~I2CTOS0:Time-outDeinition
I2Ctime-outclocksourceisfSUB/32
I2Ctime-outtimeisgivenby:([I2CTOS5:I2CTOS0]+1)×(32/fSUB)
2
TheSIMDregisterisusedtostorethedatabeingtransmittedandreceived.Thesameregisterisused
byboththeSPIandI2Cfunctions.BeforethedevicewritesdatatotheI2Cbus,theactualdatato
betransmittedmustbeplacedintheSIMDregister.AfterthedataisreceivedfromtheI2Cbus,the
devicecanreaditfromtheSIMDregister.AnytransmissionorreceptionofdatafromtheI2Cbus
mustbemadeviatheSIMDregister.
Rev. 1.00
83
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
SIMD Register
Bit
7
6
5
4
3
2
1
0
Name
D7
D6
D5
D4
D3
D2
D1
D0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
POR
x
x
x
x
x
x
x
x
“x” unknown
SIMA Register
Bit
7
6
5
4
3
2
1
0
Name
A6
A5
A4
A3
A2
A1
A0
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
POR
x
x
x
x
x
x
x
—
“x” unknown
Bit7~1
A6~A0:I2Cslaveaddress
A6~A0istheI2Cslaveaddressbit6~bit0.
TheSIMAregisterisalsousedbytheSPIinterfacebuthasthenameSIMC2.The
SIMA register is the locationwhere the 7-bitslaveaddress of the slavedeviceis
stored.Bits7~1oftheSIMAregisterdefinethedeviceslaveaddress.Bit0isnot
deined.
Whenamasterdevice,whichisconnectedtotheI2Cbus,sendsoutanaddress,which
matchestheslaveaddressintheSIMAregister,theslavedevicewillbeselected.Note
thattheSIMAregisteristhesameregisteraddressasSIMC2whichisusedbytheSPI
interface.
Bit0
Unimplemented,readas"0"
I2C Block Diagram
Rev. 1.00
84
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
I2C Bus Communication
CommunicationontheI2Cbusrequiresfourseparatesteps,aSTARTsignal,aslavedeviceaddress
transmission,adatatransmissionandfinallyaSTOPsignal.WhenaSTARTsignalisplacedon
theI2Cbus,alldevicesonthebuswillreceivethissignalandbenotiiedoftheimminentarrivalof
dataonthebus.Theirstsevenbitsofthedatawillbetheslaveaddresswiththeirstbitbeingthe
MSB.Iftheaddressoftheslavedevicematchesthatofthetransmittedaddress,theHAASbitinthe
SIMC1registerwillbesetandanI2Cinterruptwillbegenerated.Afterenteringtheinterruptservice
routine,theslavedevicemustirstchecktheconditionoftheHAASbittodeterminewhetherthe
interruptsourceoriginatesfromanaddressmatchorfromthecompletionofan8-bitdatatransfer.
Duringadatatransfer,notethatafterthe7-bitslaveaddresshasbeentransmitted,thefollowingbit,
whichisthe8thbit,istheread/writebitwhosevaluewillbeplacedintheSRWbit.Thisbitwillbe
checkedbytheslavedevicetodeterminewhethertogointotransmitorreceivemode.Beforeany
transferofdatatoorfromtheI2Cbus,themicrocontrollermustinitialisethebus,thefollowingare
stepstoachievethis:
• Step1
SettheSIM2~SIM0andSIMENbitsintheSIMC0registerto“1”toenabletheI2Cbus.
• Step2
WritetheslaveaddressofthedevicetotheI2CbusaddressregisterSIMA.
• Step3
SettheSIMEinterruptenablebitoftheinterruptcontrolregistertoenabletheSIMinterrupt.
I2C Bus Initialisation Flow Chart
Rev. 1.00
85
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
I2C Bus Start Signal
TheSTARTsignalcanonlybegeneratedbythemasterdeviceconnectedtotheI2Cbusandnotby
theslavedevice.ThisSTARTsignalwillbedetectedbyalldevicesconnectedtotheI2Cbus.When
detected,thisindicatesthattheI2CbusisbusyandthereforetheHBBbitwillbeset.ASTART
conditionoccurswhenahightolowtransitionontheSDAlinetakesplacewhentheSCLline
remainshigh.
Slave Address
ThetransmissionofaSTARTsignalbythemasterwillbedetectedbyalldevicesontheI2Cbus.
Todeterminewhichslavedevicethemasterwishestocommunicatewith,theaddressoftheslave
devicewillbesentoutimmediatelyfollowingtheSTARTsignal.Allslavedevices,afterreceiving
this7-bitaddressdata,willcompareitwiththeirown7-bitslaveaddress.Iftheaddresssentoutby
themastermatchestheinternaladdressofthemicrocontrollerslavedevice,thenaninternalI2Cbus
interruptsignalwillbegenerated.Thenextbitfollowingtheaddress,whichisthe8thbit,deines
theread/writestatusandwillbesavedtotheSRWbitoftheSIMC1register.Theslavedevicewill
thentransmitanacknowledgebit,whichisalowlevel,asthe9thbit.Theslavedevicewillalsoset
thestatuslagHAASwhentheaddressesmatch.
As an I 2C bus interrupt can come from two sources, when the program enters the interrupt
subroutine,theHAASbitshouldbeexaminedtoseewhethertheinterruptsourcehascomefrom
amatchingslaveaddressorfromthecompletionofadatabytetransfer.Whenaslaveaddressis
matched,thedevicemustbeplacedineitherthetransmitmodeandthenwritedatatotheSIMD
register,orinthereceivemodewhereitmustimplementadummyreadfromtheSIMDregisterto
releasetheSCLline.
I2C Bus Read/Write Signal
TheSRWbitintheSIMC1registerdeineswhethertheslavedevicewishestoreaddatafromthe
I2CbusorwritedatatotheI2Cbus.Theslavedeviceshouldexaminethisbittodetermineifitisto
beatransmitterorareceiver.IftheSRWlagis“1”thenthisindicatesthatthemasterdevicewishes
toreaddatafromtheI2Cbus,thereforetheslavedevicemustbesetuptosenddatatotheI2Cbusas
atransmitter.IftheSRWlagis“0”thenthisindicatesthatthemasterwishestosenddatatotheI2C
bus,thereforetheslavedevicemustbesetuptoreaddatafromtheI2Cbusasareceiver.
I2C Bus Slave Address Acknowledge Signal
After the master has transmitted a calling address, any slave device on the I 2C bus, whose
own internal address matches the calling address, must generate an acknowledge signal.The
acknowledgesignalwillinformthemasterthataslavedevicehasaccepteditscallingaddress.Ifno
acknowledgesignalisreceivedbythemasterthenaSTOPsignalmustbetransmittedbythemaster
toendthecommunication.WhentheHAASlagishigh,theaddresseshavematchedandtheslave
devicemustchecktheSRWlagtodetermineifitistobeatransmitterorareceiver.IftheSRWlag
ishigh,theslavedeviceshouldbesetuptobeatransmittersotheHTXbitintheSIMC1register
shouldbesetto“1”.IftheSRWlagislow,thenthemicrocontrollerslavedeviceshouldbesetupas
areceiverandtheHTXbitintheSIMC1registershouldbesetto“0”.
Rev. 1.00
86
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
I2C Bus Data and Acknowledge Signal
Thetransmitteddatais8-bitswideandistransmittedaftertheslavedevicehasacknowledgedreceipt
ofitsslaveaddress.TheorderofserialbittransmissionistheMSBfirstandtheLSBlast.After
receiptof8-bitsofdata,thereceivermusttransmitanacknowledgesignal,level“0”,beforeitcan
receivethenextdatabyte.Iftheslavetransmitterdoesnotreceiveanacknowledgebitsignalfrom
themasterreceiver,thentheslavetransmitterwillreleasetheSDAlinetoallowthemastertosend
aSTOPsignaltoreleasetheI2CBus.ThecorrespondingdatawillbestoredintheSIMDregister.
Ifsetupasatransmitter,theslavedevicemustirstwritethedatatobetransmittedintotheSIMD
register.Ifsetupasareceiver,theslavedevicemustreadthetransmitteddatafromtheSIMDregister.
Whentheslavereceiverreceivesthedatabyte,itmustgenerateanacknowledgebit,knownas
TXAK,onthe9thclock.Theslavedevice,whichissetupasatransmitterwillchecktheRXAKbit
intheSIMC1registertodetermineifitistosendanotherdatabyte,ifnotthenitwillreleasethe
SDAlineandawaitthereceiptofaSTOPsignalfromthemaster.
I2C Communication Timing Diagram
Note:*Whenaslaveaddressismatched,thedevicemustbeplacedineitherthetransmitmode
andthenwritedatatotheSIMDregister,orinthereceivemodewhereitmustimplementa
dummyreadfromtheSIMDregistertoreleasetheSCLline.
Rev. 1.00
87
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
I2C Bus ISR Flow Chart
Rev. 1.00
88
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
I2C Time-out Control
InordertoreducetheproblemofI2Clockupduetoreceptionoferroneousclocksources,clock,a
time-outfunctionisprovided.IftheclocksourcetotheI2Cisnotreceivedthenafteraixedtime
period,theI2Ccircuitryandregisterswillbereset.
Thetime-outcounterstartscountingonanI2Cbus“START”and“addressmatch”condition,and
isclearedbyanSCLfallingedge.BeforethenextSCLfallingedgearrives,ifthetimeelapsedis
greaterthanthetime-outsetupbytheI2CTOCregister,thenatime-outconditionwilloccur.The
time-outfunctionwillstopwhenanI2C“STOP”conditionoccurs.
WhenanI2Ctime-outcounteroverlowoccurs,thecounterwillstopandtheI2CTOENbitwillbe
clearedtozeroandtheI2CTOFbitwillbesethightoindicatethatatime-outconditionasoccurred.
Thetime-outconditionwillalsogenerateaninterruptwhichusestheI2Cinterrruptvector.When
anI2Ctime-outoccurs,theI2Cinternalcircuitrywillberesetandtheregisterswillberesetintothe
followingcondition:
Register
After I2C Time-out
SIMD, SIMA, SIMC0
No change
SIMC1
Reset to POR condition
I2C Registers After Time-out
TheI2CTOFlagcanbeclearedbytheapplicationprogram.Thereare64time-outperiodswhich
canbeselectedusingbitsintheI2CTOCregister.Thetime-outtimeisgivenbytheformula:
((1~64)×32)/fSUB
Thisgivesarangeofabout1msto64ms.NotealsothattheLIRCoscillatoriscontinuouslyenabled.
Rev. 1.00
89
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Interrupts
Interrupts are an important part of any microcontroller system.When an external event or an
internalfunctionsuchasaTouchActionorTimer/EventCounteroverlowrequiresmicrocontroller
attention,theircorrespondinginterruptwillenforceatemporarysuspensionofthemainprogram
allowingthemicrocontrollertodirectattentiontotheirrespectiveneeds.Thedevicescontainseveral
externalinterruptandinternalinterruptsfunctions.Theexternalinterruptisgeneratedbytheaction
oftheexternalINTpin,whiletheinternalinterruptsaregeneratedbyvariousinternalfunctionssuch
astheTouchKeys,Timer/EventCounter,TimeBase,SIMetc.
Interrupt Registers
Overall interrupt control, which basically means the setting of request flags when certain
microcontrollerconditionsoccurandthesettingofinterruptenablebitsbytheapplicationprogram,
iscontrolledbyaseriesofregisters,locatedintheSpecialPurposeDataMemory,asshowninthe
accompanyingtable.Thenumberofregistersdependsuponthedevicechosenbutfallintothree
categories.TheirstistheINTC0~INTC1registerswhichsetuptheprimaryinterrupts,thesecondis
theINTEGregisterstosetuptheexternalinterrupttriggeredgetype.
Eachregistercontainsanumberofenablebitstoenableordisableindividualregistersaswellas
interruptflagstoindicatethepresenceofaninterruptrequest.Thenamingconventionofthese
followsaspeciicpattern.Firstislistedanabbreviatedinterrupttype,thenthe(optional)numberof
thatinterruptfollowedbyeitheran“E”forenable/disablebitor“F”forrequestlag.
Enable Bit
Request Flag
Notes
Global
Function
EMI
—
—
INT Pin
INTE
INTF
—
Touch Key Module
TKME
TKMF
—
SIM
SIME
SIMF
—
EEPROM
DEE
DEF
—
Time Base
TBE
TBF
—
TE
TF
—
Timer/Event Counter
Interrupt Register Bit Naming Conventions
Interrupt Register Contents
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
INTEG
—
—
—
—
—
—
INTS1
INTS0
INTC0
—
TF
TKMF
INTF
TE
TKME
INTE
EMI
INTC1
—
DEF
TBF
SIMF
—
DEE
TBE
SIME
INTEG Register
Rev. 1.00
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
—
—
INTS1
INTS0
R/W
—
—
—
—
—
—
R/W
R/W
POR
—
—
—
—
—
—
0
0
Bit7~2
Unimplemented,readas"0"
Bit1~0
INTS1, INTS0:DeinesINTinterruptactiveedge
00:Disabledinterrupt
01:RisingEdgeinterrupt
10:FallingEdgeinterrupt
11:DualEdgeinterrupt
90
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
INTC0 Register
Rev. 1.00
Bit
7
6
5
4
Name
R/W
POR
3
2
1
—
TF
TKMF
—
R/W
R/W
—
0
0
INTF
TE
TKME
INTE
EMI
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
Bit7
Unimplemented,readas"0"
Bit6
TF:Timer/EventCounterinterruptrequestlag
0:Norequest
1:Interruptrequest
Bit5
TKMF:Touchkeymoduleinterruptrequestlag
0:Norequest
1:Interruptrequest
Bit4
INTF:INTpininterruptrequestlag
0:Norequest
1:Interruptrequest
Bit3
TE:Timer/EventCounterinterruptcontrol
0:Disable
1:Enable
Bit2
TKME:Touchkeymoduleinterruptcontrol
0:Disable
1:Enable
Bit1
INTE:INTpininterruptcontrol
0:Disable
1:Enable
Bit0
EMI:GlobalInterruptcontrol
0:Disable
1:Enable
91
0
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
INTC1 Register
Rev. 1.00
Bit
7
6
5
4
Name
—
R/W
—
POR
—
3
2
DEF
TBF
R/W
R/W
0
0
SIMF
—
R/W
—
0
—
Bit7
Unimplemented,readas"0"
Bit6
DEF:DataEEPROMinterruptrequestlag
0:Norequest
1:Interruptrequest
Bit5
TBF:TimeBaseinterruptrequestlag
0:Norequest
1:Interruptrequest
Bit4
SIMF:SIMinterruptrequestlag
0:Norequest
1:Interruptrequest
Bit3
Unimplemented,readas"0"
Bit2
DEE:DataEEPROMcontrol
0:Disable
1:Enable
Bit1
TBE:TimeBaseinterruptcontrol
0:Disable
1:Enable
Bit0
SIME:SIMinterruptcontrol
0:Disable
1:Enable
92
1
0
DEE
TBE
SIME
R/W
R/W
R/W
0
0
0
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Interrupt Operation
When the conditions for an interrupt event occur, such as a Touch Key Counter overflow,
Timer/Event Counteroverflow,etc,therelevantinterruptrequestflagwillbeset.Whetherthe
requestflagactuallygeneratesaprogramjumptotherelevantinterruptvectorisdeterminedby
theconditionoftheinterruptenablebit.Iftheenablebitissethighthentheprogramwilljumpto
itsrelevantvector;iftheenablebitiszerothenalthoughtheinterruptrequestlagissetanactual
interruptwillnotbegeneratedandtheprogramwillnotjumptotherelevantinterruptvector.The
globalinterruptenablebit,ifclearedtozero,willdisableallinterrupts.
Whenaninterruptisgenerated,theProgramCounter,whichstorestheaddressofthenextinstruction
tobeexecuted,willbetransferredontothestack.TheProgramCounterwillthenbeloadedwitha
newaddresswhichwillbethevalueofthecorrespondinginterruptvector.Themicrocontrollerwill
thenfetchitsnextinstructionfromthisinterruptvector.Theinstructionatthisvectorwillusually
bea“JMP”whichwilljumptoanothersectionofprogramwhichisknownastheinterruptservice
routine.Hereislocatedthecodetocontroltheappropriateinterrupt.Theinterruptserviceroutine
mustbeterminated witha“RETI”,whichretrievestheoriginal ProgramCounteraddressfrom
thestackandallowsthemicrocontrollertocontinuewithnormalexecutionatthepointwherethe
interruptoccurred.
Thevariousinterruptenablebits,togetherwiththeirassociated requestflags,areshowninthe
accompanying diagrams with their order of priority. Some interrupt sources have their own
individualvectorwhileotherssharethesamemulti-function interruptvector.Onceaninterrupt
subroutineisserviced,alltheotherinterruptswillbeblocked,astheglobalinterruptenablebit,
EMIbitwillbeclearedautomatically.Thiswillpreventanyfurtherinterruptnestingfromoccurring.
However,ifotherinterruptrequestsoccurduringthisinterval,althoughtheinterruptwillnotbe
immediatelyserviced,therequestlagwillstillberecorded.
Ifaninterruptrequiresimmediateservicingwhiletheprogramisalreadyinanotherinterruptservice
routine,theEMIbitshouldbesetafterenteringtheroutine,toallowinterruptnesting.Ifthestack
isfull,theinterruptrequestwillnotbeacknowledged,eveniftherelatedinterruptisenabled,until
theStackPointerisdecremented.Ifimmediateserviceisdesired,thestackmustbepreventedfrom
becomingfull.Incaseofsimultaneousrequests,theaccompanyingdiagramshowstheprioritythat
isapplied.Alloftheinterruptrequestlagswhensetwillwake-upthedeviceifitisinSLEEPor
IDLEMode,howevertopreventawake-upfromoccurringthecorrespondinglagshouldbeset
beforethedeviceisinSLEEPorIDLEMode.
xxF
Legend
Request Flag, no auto reset in ISR
xxF
Request Flag, auto reset in ISR
xxE
Enable Bits
EMI auto disabled in ISR
Interrupt
Name
External
Request
Flags
INTF
Enable
Bits
INTE
Master
Enable
EMI
Touch Key Module
TKMF
TKME
EMI
08H
Timer/Event Counter
TF
TE
EMI
0CH
SIM
SIMF
SIME
EMI
10H
Time Base
TBF
TBE
EMI
14H
EEPROM
DEF
DEE
EMI
18 H
Vector
04H
Priority
High
Low
Interrupt Structure
Rev. 1.00
93
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
External Interrupt
The external interrupt is controlled by signal transitions on the pin INT.An external interrupt
requestwilltakeplacewhentheexternalinterruptrequestflag,INTF, isset,whichwilloccur
whenatransition,whosetypeischosenbytheedgeselectbits,appearsontheexternalinterrupt
pin.Toallowtheprogramtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterrupt
enablebit,EMI,andrespectiveexternalinterruptenablebit,INTE,mustirstbeset.Additionally
thecorrectinterruptedgetypemustbeselectedusingtheINTEGregistertoenabletheexternal
interruptfunctionandtochoosethetriggeredgetype.Astheexternalinterruptpinispin-shared
withI/Opin,itscanonlybeconiguredasexternalinterruptpinifitsexternalinterruptenablebitin
thecorrespondinginterruptregisterhasbeenset.Thepinmustalsobesetupasaninputbysetting
thecorrespondingbitintheportcontrolregister.Whentheinterruptisenabled,thestackisnotfull
andthecorrecttransitiontypeappearsontheexternalinterruptpin,asubroutinecalltotheexternal
interruptvector,willtakeplace.Whentheinterruptisserviced,theexternalinterruptrequestlag,
INTF,willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableother
interrupts.Notethatanypull-highresistorselectionsontheexternalinterruptpinwillremainvalid
evenifthepinisusedasanexternalinterruptinput.
TheINTEGregisterisusedtoselectthetypeofactiveedgethatwilltriggertheexternalinterrupt.
Achoiceofeitherrisingorfallingorbothedgetypescanbechosentotriggeranexternalinterrupt.
NotethattheINTEGregistercanalsobeusedtodisabletheexternalinterruptfunction.
Time Base Interrupt
ThefunctionoftheTimeBaseInterruptistoprovideregulartimesignalintheformofaninternal
interrupt.Itiscontrolledbytheoverflowsignalfromitstimerfunction.Whenthishappensits
interrupt request flagsTBF will be set.To allow the program to branch to its interrupt vector
address,theglobalinterruptenablebit,EMIandTimeBaseenablebit,TBE,mustirstbeset.When
theinterruptisenabled,thestackisnotfullandtheTimeBaseoverlows,asubroutinecalltoits
vectorlocationwilltakeplace.Whentheinterruptisserviced,theinterruptrequestlag,TBF,will
beautomaticallyresetandtheEMIbitwillbeclearedtodisableotherinterrupts.
ThepurposeoftheTimeBaseInterruptistoprovideaninterruptsignalatixedtimeperiods.Its
clocksourceoriginatefromtheinternalclocksourcefSYSorfSUB.ThisfTPinputclockpassesthrough
adivider,thedivisionratioofwhichisselectedbyprogrammingtheappropriatebitsintheTBC
registertoobtainlongerinterruptperiodswhosevalueranges.TheclocksourcethatgeneratesfTP,
whichinturncontrolstheTimeBaseinterruptperiod,canoriginatefromseveraldifferentsources,
asshownintheSystemOperatingModesection.
Rev. 1.00
94
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
TBC Register
Bit
7
6
5
4
3
2
1
0
Name
—
—
R/W
—
—
TB1
TB0
—
—
—
—
R/W
R/W
—
—
—
POR
—
—
0
—
0
—
—
—
—
Bit7~6
Unimplemented,readas"0"
Bit5~4
TB1~TB0:SelectTimeBaseTime-outPeriod
00:1024/fTP
01:2048/fTP
10:4096/fTP
11:8192/fTP
Bit3~0
Unimplemented,readas"0"
Time Base Structure
Timer/Event Counter Interrupt
For aTimer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and the
corresponding timerinterrupt enablebit,TE,must first be set.An actualTimer/Event Counter
interruptwilltakeplacewhentheTimer/EventCounterrequestlag,TF,isset,asituationthatwill
occurwhentherelevantTimer/EventCounteroverlows.Whentheinterruptisenabled,thestack
isnotfullandaTimer/EventCounternoverflowoccurs,asubroutinecalltotherelevanttimer
interruptvector,willtakeplace.Whentheinterruptisserviced,thetimerinterruptrequestlag,TF,
willbeautomaticallyresetandtheEMIbitwillbeautomaticallyclearedtodisableotherinterrupts.
EEPROM Interrupt
AnEEPROMInterruptrequestwilltakeplacewhentheEEPROMInterruptrequestlag,DEF,isset,
whichoccurswhenanEEPROMWritecycleends.Toallowtheprogramtobranchtoitsrespective
interruptvectoraddress,theglobalinterruptenablebit,EMI,andEEPROMInterruptenablebit,
DEE,mustirstbeset.Whentheinterruptisenabled,thestackisnotfullandanEEPROMWrite
cycleends,asubroutinecalltotherespectiveEEPROMInterruptvector,willtakeplace.Whenthe
EEPROMInterruptisserviced,theDEFlagwillbeautomaticallyclearedandtheEMIbitwillbe
automaticallyclearedtodisableotherinterrupts.
Rev. 1.00
95
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Touch Key Interrupt
ForaTouchKeyinterrupttooccur,theglobalinterruptenablebit,EMI,andthecorresponding
TouchKeyinterruptenableTKMEmustbeirstset.AnactualTouchKeyinterruptwilltakeplace
whentheTouchKeyrequestlag.TKMF,isset,asituationthatwilloccurwhenthetimeslotcounter
overlows.Whentheinterruptisenabled,thestackisnotfullandtheTouchKeytimeslotcounter
overlowoccurs,asubroutinecalltotherelevanttimerinterruptvector,willtakeplace.Whenthe
interruptisserviced,theTouchKeyinterruptrequestlag,TKMF,willbeautomaticallyresetandthe
EMIbitwillbeautomaticallyclearedtodisableotherinterrupts.
TheTKCFOVflag,whichisthe16-bitC/Fcounteroverflowflagwillgohighwhenanyofthe
TouchKeyModule16-bitC/Fcounteroverlows.Asthislagwillnotbeautomaticallycleared,it
hastobeclearedbytheapplicationprogram.
Module0onlycontainsone16-bitcounter.TheTK16OVlag,whichisthe16-bitcounteroverlow
lagwillgohighwhenthe16-bitcounteroverlows.Asthislagwillnotbeautomaticallycleared,it
hastobeclearedbytheapplicationprogram.
SIM Interrupt
ASIMInterruptrequestwilltakeplacewhentheSIMInterruptrequestlag,SIMF,isset,which
occurswhenabyteofdatahasbeenreceivedortransmittedbytheSIMinterface.Toallowthe
programtobranchtoitsrespectiveinterruptvectoraddress,theglobalinterruptenablebit,EMI,
andtheSerialInterfaceInterruptenablebit,SIME,mustirstbeset.Whentheinterruptisenabled,
thestackisnotfullandabyteofdatahasbeentransmittedorreceivedbytheSIMinterface,a
subroutinecalltotherespectiveinterruptvector,willtakeplace.WhentheSerialInterfaceInterrupt
isserviced,theSIMinterruptrequestlag,SIMF,willbeautomaticallyclearedandtheEMIbitwill
beautomaticallyclearedtodisableotherinterrupts.
Interrupt Wake-up Function
Eachoftheinterruptfunctionshasthecapabilityofwakingupthemicrocontrollerwheninthe
SLEEPorIDLEMode.Awake-upisgeneratedwhenaninterruptrequestlagchangesfromlowto
highandisindependentofwhethertheinterruptisenabledornot.Therefore,eventhoughthedevice
isintheSLEEPorIDLEModeanditssystemoscillatorstopped,situationssuchasexternaledge
transitionsontheexternalinterruptpins,alowpowersupplyvoltageorcomparatorinputchange
maycausetheirrespectiveinterruptlagtobesethighandconsequentlygenerateaninterrupt.Care
mustthereforebetakenifspuriouswake-upsituationsaretobeavoided.Ifaninterruptwake-up
functionistobedisabledthenthecorrespondinginterruptrequestlagshouldbesethighbeforethe
deviceenterstheSLEEPorIDLEMode.Theinterruptenablebitshavenoeffectontheinterrupt
wake-upfunction.
Rev. 1.00
96
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Programming Considerations
Bydisablingtherelevantinterruptenablebits,arequestedinterruptcanbepreventedfrombeing
serviced, however, once an interrupt request flag is set, it will remain in this condition in the
interruptregisteruntilthecorrespondinginterruptisservicedoruntiltherequestlagisclearedby
theapplicationprogram.
Itisrecommendedthatprogramsdonotusethe“CALL”instructionwithintheinterruptservice
subroutine.Interruptsoftenoccurinanunpredictablemannerorneedtobeservicedimmediately.
Ifonlyonestackisleftandtheinterruptisnotwellcontrolled,theoriginalcontrolsequencewillbe
damagedonceaCALLsubroutineisexecutedintheinterruptsubroutine.
EveryinterrupthasthecapabilityofwakingupthemicrocontrollerwhenitisinSLEEPorIDLE
Mode,thewakeupbeinggeneratedwhentheinterruptrequestlagchangesfromlowtohigh.Ifitis
requiredtopreventacertaininterruptfromwakingupthemicrocontrollerthenitsrespectiverequest
lagshouldbeirstsethighbeforeenterSLEEPorIDLEMode.
AsonlytheProgramCounterispushedontothestack,thenwhentheinterruptisserviced,ifthe
contentsoftheaccumulator,statusregisterorotherregistersarealteredbytheinterruptservice
program,theircontentsshouldbesavedtothememoryatthebeginningoftheinterruptservice
routine.
Toreturnfromaninterruptsubroutine,eitheraRETorRETIinstructionmaybeexecuted.TheRETI
instructioninadditiontoexecutingareturntothemainprogramalsoautomaticallysetstheEMI
bithightoallowfurtherinterrupts.TheRETinstructionhoweveronlyexecutesareturntothemain
programleavingtheEMIbitinitspresentzerostateandthereforedisablingtheexecutionoffurther
interrupts.
Rev. 1.00
97
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Application Circuits
Note:“*”ItisrecommendedthatthiscomponentisaddedforaddedESDprotection.
“**”Itisrecommendedthatthiscomponentisaddedinenvironmentswherepowerlinenoise
issigniicant.
Rev. 1.00
98
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Instruction Set
Instruction
Centraltothesuccessfuloperationofanymicrocontrollerisitsinstructionset,whichisasetof
programinstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.Inthecase
ofHoltekmicrocontrollers,acomprehensiveandlexiblesetofover60instructionsisprovidedto
enableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.
Foreasierunderstandingofthevariousinstructioncodes,theyhavebeensubdividedintoseveral
functionalgroupings
Instruction Timing
Mostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,
call,ortablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleis
equalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructions
wouldbeimplementedwithin0.5 sandbranchorcallinstructionswouldbeimplementedwithin
1us.Althoughinstructionswhichrequireonemorecycletoimplementaregenerallylimitedto
theJMP,CALL,RET,RETIandtablereadinstructions,itisimportanttorealizethatanyother
instructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotake
onemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwillimplya
directjumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructions
wouldbe“CLRPCL”or“MOVPCL,A”.Forthecaseofskipinstructions,itmustbenotedthatif
theresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifno
skipisinvolvedthenonlyonecycleisrequired.
Moving and Transferring Data
The transfer of data within the microcontroller program is one of the most frequently used
operations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregistersto
theAccumulatorandvice-versaaswellasbeingabletomovespeciicimmediatedatadirectlyinto
theAccumulator.Oneofthemostimportantdatatransferapplicationsistoreceivedatafromthe
inputportsandtransferdatatotheoutputports.
Arithmetic Operations
Theabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureof
mostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeof
addandsubtractinstructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Care
mustbetakentoensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255for
additionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DEC
andDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthe
destinationspeciied.
Rev. 1.00
99
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Logical and Rotate Operations
ThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstruction
withintheHoltekmicrocontrollerinstructionset.Aswiththecaseofmostinstructionsinvolving
data manipulation, data must pass through theAccumulator which may involve additional
programming steps. In all logical data operations, the zero flag may be set if the result of the
operationiszero.Anotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuch
asRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Different
rotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserial
portprogrammingapplicationswheredatacanberotatedfromaninternalregisterintotheCarry
bitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplication
whererotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.
Branches and Control Transfer
ProgrambranchingtakestheformofeitherjumpstospeciiedlocationsusingtheJMPinstructionor
toasubroutineusingtheCALLinstruction.Theydifferinthesensethatinthecaseofasubroutine
call,theprogrammustreturntotheinstructionimmediatelywhenthesubroutinehasbeencarried
out.ThisisdonebyplacingareturninstructionRETinthesubroutinewhichwillcausetheprogram
tojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,the
programsimplyjumpstothedesiredlocation.Thereisnorequirementtojumpbacktotheoriginal
jumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulset
ofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingthe
conditionofacertaindatamemoryorindividualbits.Dependingupontheconditions,theprogram
willcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These
instructionsarethekeytodecisionmakingandbranchingwithintheprogramperhapsdetermined
bytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.
Bit Operations
TheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelylexiblefeatureofall
Holtekmicrocontrollers.Thisfeatureisespeciallyusefulforoutputportbitprogrammingwhere
individualbitsorportpinscanbedirectlysethighorlowusingeitherthe“SET[m].i”or“CLR[m].i”
instructionsrespectively.Thefeatureremovestheneedforprogrammerstoirstreadthe8-bitoutput
port,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwith
thecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebit
operationinstructionsareused.
Table Read Operations
Data storage is normally implemented by using registers. However, when working with large
amountsofixeddata,thevolumeinvolvedoftenmakesitinconvenienttostoretheixeddatain
theDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgram
Memorytobesetupasatablewheredatacanbedirectlystored.Asetofeasytouseinstructions
providesthemeansbywhichthisfixeddatacanbereferencedandretrieved fromtheProgram
Memory.
Other Operations
Inadditiontotheabovefunctionalinstructions,arangeofotherinstructionsalsoexistsuchas
the“HALT”instructionforPower-downoperationsandinstructionstocontroltheoperationof
theWatchdogTimerforreliableprogramoperationsunderextremeelectricorelectromagnetic
environments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.
Rev. 1.00
100
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Instruction Set Summary
Thefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionand
canbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.
Table conventions
x:Bitsimmediatedata
m:DataMemoryaddress
A:Accumulator
i:0~7numberofbits
addr:Programmemoryaddress
Mnemonic
Description
Cycles
Flag Affected
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
1Note
1Note
1Note
1
1
1
1Note
1
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
1
1Note
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
None
None
None
1
1Note
Z
Z
Z
Z
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Rev. 1.00
1
101
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Mnemonic
Description
Cycles
Flag Affected
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifno
skiptakesplaceonlyonecycleisrequired.
2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.
3.Forthe“CLRWDT1”and“CLRWDT2”instructionstheTOandPDFflagsmaybeaffectedbythe
execution status.TheTO and PDF flags are cleared after both “CLRWDT1” and “CLRWDT2”
instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFlagsremainunchanged.
Rev. 1.00
102
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Instruction Deinition
ADC A,[m]
Description
Operation
Affectedlag(s)
AddDataMemorytoACCwithCarry
ThecontentsofthespeciiedDataMemory,Accumulatorandthecarrylagareadded.
TheresultisstoredintheAccumulator.
ACC ACC+[m]+C
OV,Z,AC,C
ADCM A,[m]
Description
Operation
Affectedlag(s)
AddACCtoDataMemorywithCarry
ThecontentsofthespeciiedDataMemory,Accumulatorandthecarrylagareadded.
TheresultisstoredinthespeciiedDataMemory.
[m] ACC+[m]+C
OV,Z,AC,C
AddDataMemorytoACC
ADD A,[m]
Description
ThecontentsofthespeciiedDataMemoryandtheAccumulatorareadded.
TheresultisstoredintheAccumulator.
Operation
Affectedlag(s)
ACC ACC+[m]
OV,Z,AC,C
ADD A,x
Description
Operation
Affectedlag(s)
AddimmediatedatatoACC
ThecontentsoftheAccumulatorandthespeciiedimmediatedataareadded.
TheresultisstoredintheAccumulator.
ACC ACC+x
OV,Z,AC,C
ADDM A,[m]
Description
Operation
Affectedlag(s)
AddACCtoDataMemory
ThecontentsofthespeciiedDataMemoryandtheAccumulatorareadded.
TheresultisstoredinthespeciiedDataMemory.
[m] ACC+[m]
OV,Z,AC,C
AND A,[m]
Description
Operation
Affectedlag(s)
LogicalANDDataMemorytoACC
DataintheAccumulatorandthespeciiedDataMemoryperformabitwiselogicalAND
operation.TheresultisstoredintheAccumulator.
ACC ACC AND [m]
Z
AND A,x
Description
Operation
Affectedlag(s)
LogicalANDimmediatedatatoACC
DataintheAccumulatorandthespeciiedimmediatedataperformabitwiselogicalAND
operation.TheresultisstoredintheAccumulator.
ACC ACC AND x
Z
ANDM A,[m]
Description
Operation
Affectedlag(s)
LogicalANDACCtoDataMemory
DatainthespeciiedDataMemoryandtheAccumulatorperformabitwiselogicalAND
operation.TheresultisstoredintheDataMemory.
[m] ACC AND [m]
Z
Rev. 1.00
103
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
CALL addr
Description
Operation
Affectedlag(s)
Subroutinecall
Unconditionallycallsasubroutineatthespeciiedaddress.TheProgramCounterthen
incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe
stack.Thespeciiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis
newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.
Stack ProgramCounter+1
ProgramCounter addr
None
CLR [m]
Description
Operation
Affectedlag(s)
ClearDataMemory
EachbitofthespeciiedDataMemoryisclearedto0.
[m] 00H
None
CLR [m].i
Description
Operation
Affectedlag(s)
ClearbitofDataMemory
BitiofthespeciiedDataMemoryisclearedto0.
[m].i 0
None
CLR WDT
Description
Operation
Affectedlag(s)
ClearWatchdogTimer
TheTO,PDFlagsandtheWDTareallcleared.
WDTcleared
TO 0
PDF 0
TO,PDF
CLR WDT1
Description
Operation
Affectedlag(s)
Pre-clearWatchdogTimer
TheTO,PDFlagsandtheWDTareallcleared.Notethatthisinstructionworksin
conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave
effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will
havenoeffect.
WDTcleared
TO 0
PDF 0
TO,PDF
CLR WDT2
Description
Operation
Affectedlag(s)
Pre-clearWatchdogTimer
TheTO,PDFlagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction
withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect.
RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno
effect.
WDTcleared
TO 0
PDF 0
TO,PDF
CPL [m]
Description
Operation
Affectedlag(s)
ComplementDataMemory
EachbitofthespeciiedDataMemoryislogicallycomplemented(1 scomplement).Bitswhich
previouslycontaineda1arechangedto0andviceversa.
[m] [m]
Z
Rev. 1.00
104
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
CPLA [m]
Description
Operation
Affectedlag(s)
ComplementDataMemorywithresultinACC
EachbitofthespeciiedDataMemoryislogicallycomplemented(1 scomplement).Bitswhich
previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin
theAccumulatorandthecontentsoftheDataMemoryremainunchanged.
ACC [m]
Z
DAA [m]
Description
Operation
Affectedlag(s)
Decimal-AdjustACCforadditionwithresultinDataMemory
ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value
resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9
orifAClagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble
remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheClagisset,thenavalueof6
willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding
00H,06H,60Hor66HdependingontheAccumulatorandlagconditions.OnlytheClag
maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan
100,itallowsmultipleprecisiondecimaladdition.
[m] ACC+00Hor
[m] ACC+06Hor
[m] ACC+60Hor
[m] ACC+66H
C
DEC [m]
Description
Operation
Affectedlag(s)
DecrementDataMemory
DatainthespeciiedDataMemoryisdecrementedby1.
[m] [m]−1
Z
DECA[m]
Description
Operation
Affectedlag(s)
DecrementDataMemorywithresultinACC
DatainthespeciiedDataMemoryisdecrementedby1.Theresultisstoredinthe
Accumulator.ThecontentsoftheDataMemoryremainunchanged.
ACC [m]−1
Z
HALT
Description
Operation
Affectedlag(s)
Enterpowerdownmode
Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof
theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower
downlagPDFissetandtheWDTtime-outlagTOiscleared.
TO 0
PDF 1
TO,PDF
INC [m]
Description
Operation
Affectedlag(s)
IncrementDataMemory
DatainthespeciiedDataMemoryisincrementedby1.
[m] [m]+1
Z
INCA [m]
Description
Operation
Affectedlag(s)
IncrementDataMemorywithresultinACC
DatainthespeciiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator.
ThecontentsoftheDataMemoryremainunchanged.
ACC [m]+1
Z
Rev. 1.00
105
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
JMP addr
Description
Operation
Affectedlag(s)
Jumpunconditionally
ThecontentsoftheProgramCounterarereplacedwiththespeciiedaddress.Program
executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy
instructionwhilethenewaddressisloaded,itisatwocycleinstruction.
ProgramCounter addr
None
MOV A,[m]
Description
Operation
Affectedlag(s)
MoveDataMemorytoACC
ThecontentsofthespeciiedDataMemoryarecopiedtotheAccumulator.
ACC [m]
None
MOV A,x
Description
Operation
Affectedlag(s)
MoveimmediatedatatoACC
TheimmediatedataspeciiedisloadedintotheAccumulator.
ACC x
None
MOV [m],A
Description
Operation
Affectedlag(s)
MoveACCtoDataMemory
ThecontentsoftheAccumulatorarecopiedtothespeciiedDataMemory.
[m] ACC
None
NOP
Description
Operation
Affectedlag(s)
Nooperation
Nooperationisperformed.Executioncontinueswiththenextinstruction.
Nooperation
None
OR A,[m]
Description
Operation
Affectedlag(s)
LogicalORDataMemorytoACC
DataintheAccumulatorandthespeciiedDataMemoryperformabitwise
logicalORoperation.TheresultisstoredintheAccumulator.
ACC ACC OR [m]
Z
OR A,x
Description
Operation
Affectedlag(s)
LogicalORimmediatedatatoACC
DataintheAccumulatorandthespeciiedimmediatedataperformabitwiselogicalOR
operation.TheresultisstoredintheAccumulator.
ACC ACC OR x
Z
ORM A,[m]
Description
Operation
Affectedlag(s)
LogicalORACCtoDataMemory
DatainthespeciiedDataMemoryandtheAccumulatorperformabitwiselogicalOR
operation.TheresultisstoredintheDataMemory.
[m] ACC OR [m]
Z
RET
Description
Operation
Affectedlag(s)
Returnfromsubroutine
TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored
address.
ProgramCounter Stack
None
Rev. 1.00
106
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
RET A,x
Description
Operation
Affectedlag(s)
ReturnfromsubroutineandloadimmediatedatatoACC
TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespeciied
immediatedata.Programexecutioncontinuesattherestoredaddress.
ProgramCounter Stack
ACC x
None
RETI
Description
Operation
Affectedlag(s)
Returnfrominterrupt
TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe
EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe
RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning
tothemainprogram.
ProgramCounter Stack
EMI 1
None
RL [m]
Description
Operation
Affectedlag(s)
RotateDataMemoryleft
ThecontentsofthespeciiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.
[m].(i+1) [m].i;(i=0~6)
[m].0 [m].7
None
RLA [m]
Description
Operation
Affectedlag(s)
RotateDataMemoryleftwithresultinACC
ThecontentsofthespeciiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.
TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain
unchanged.
ACC.(i+1) [m].i;(i=0~6)
ACC.0 [m].7
None
RLC [m]
Description
Operation
Affectedlag(s)
RotateDataMemoryleftthroughCarry
ThecontentsofthespeciiedDataMemoryandthecarrylagarerotatedleftby1bit.Bit7
replacestheCarrybitandtheoriginalcarrylagisrotatedintobit0.
[m].(i+1) [m].i;(i=0~6)
[m].0 C
C [m].7
C
RLCA [m]
Description
Operation
Affectedlag(s)
RotateDataMemoryleftthroughCarrywithresultinACC
DatainthespeciiedDataMemoryandthecarrylagarerotatedleftby1bit.Bit7replacesthe
Carrybitandtheoriginalcarrylagisrotatedintothebit0.Therotatedresultisstoredinthe
AccumulatorandthecontentsoftheDataMemoryremainunchanged.
ACC.(i+1) [m].i;(i=0~6)
ACC.0 C
C [m].7
C
RR [m]
Description
Operation
Affectedlag(s)
RotateDataMemoryright
ThecontentsofthespeciiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.
[m].i [m].(i+1);(i=0~6)
[m].7 [m].0
None
Rev. 1.00
107
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
RRA [m]
Description
Operation
Affectedlag(s)
RotateDataMemoryrightwithresultinACC
DatainthespeciiedDataMemoryandthecarrylagarerotatedrightby1bitwithbit0
rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe
DataMemoryremainunchanged.
ACC.i [m].(i+1);(i=0~6)
ACC.7 [m].0
None
RRC [m]
Description
Operation
Affectedlag(s)
RotateDataMemoryrightthroughCarry
ThecontentsofthespeciiedDataMemoryandthecarrylagarerotatedrightby1bit.Bit0
replacestheCarrybitandtheoriginalcarrylagisrotatedintobit7.
[m].i [m].(i+1);(i=0~6)
[m].7 C
C [m].0
C
RRCA [m]
Description
Operation
Affectedlag(s)
RotateDataMemoryrightthroughCarrywithresultinACC
DatainthespeciiedDataMemoryandthecarrylagarerotatedrightby1bit.Bit0replaces
theCarrybitandtheoriginalcarrylagisrotatedintobit7.Therotatedresultisstoredinthe
AccumulatorandthecontentsoftheDataMemoryremainunchanged.
ACC.i [m].(i+1);(i=0~6)
ACC.7 C
C [m].0
C
SBC A,[m]
Description
Operation
Affectedlag(s)
SubtractDataMemoryfromACCwithCarry
ThecontentsofthespeciiedDataMemoryandthecomplementofthecarrylagare
subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe
resultofsubtractionisnegative,theClagwillbeclearedto0,otherwiseiftheresultis
positiveorzero,theClagwillbesetto1.
ACC ACC−[m]−C
OV,Z,AC,C
SBCM A,[m]
Description
Operation
Affectedlag(s)
SubtractDataMemoryfromACCwithCarryandresultinDataMemory
ThecontentsofthespeciiedDataMemoryandthecomplementofthecarrylagare
subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe
resultofsubtractionisnegative,theClagwillbeclearedto0,otherwiseiftheresultis
positiveorzero,theClagwillbesetto1.
[m] ACC−[m]−C
OV,Z,AC,C
SDZ [m]
Description
Operation
Affectedlag(s)
SkipifdecrementDataMemoryis0
ThecontentsofthespeciiedDataMemoryareirstdecrementedby1.Iftheresultis0the
followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile
thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram
proceedswiththefollowinginstruction.
[m] [m]−1
Skipif[m]=0
None
Rev. 1.00
108
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
SDZA [m]
Description
Operation
Affectedlag(s)
SkipifdecrementDataMemoryiszerowithresultinACC
ThecontentsofthespeciiedDataMemoryareirstdecrementedby1.Iftheresultis0,the
followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespeciied
DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy
instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0,
theprogramproceedswiththefollowinginstruction.
ACC [m]−1
SkipifACC=0
None
SET [m]
Description
Operation
Affectedlag(s)
SetDataMemory
EachbitofthespeciiedDataMemoryissetto1.
[m] FFH
None
SET [m].i
Description
Operation
Affectedlag(s)
SetbitofDataMemory
BitiofthespeciiedDataMemoryissetto1.
[m].i 1
None
SIZ [m]
Description
Operation
Affectedlag(s)
SkipifincrementDataMemoryis0
ThecontentsofthespeciiedDataMemoryareirstincrementedby1.Iftheresultis0,the
followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile
thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram
proceedswiththefollowinginstruction.
[m] [m]+1
Skipif[m]=0
None
SIZA [m]
Description
Operation
Affectedlag(s)
SkipifincrementDataMemoryiszerowithresultinACC
ThecontentsofthespeciiedDataMemoryareirstincrementedby1.Iftheresultis0,the
followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespeciied
DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy
instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot
0theprogramproceedswiththefollowinginstruction.
ACC [m]+1
SkipifACC=0
None
SNZ [m].i
Description
Operation
Affectedlag(s)
SkipifbitiofDataMemoryisnot0
IfbitiofthespeciiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis
requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo
cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.
Skipif[m].i≠0
None
SUB A,[m]
Description
Operation
Affectedlag(s)
SubtractDataMemoryfromACC
ThespeciiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis
storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theClagwillbe
clearedto0,otherwiseiftheresultispositiveorzero,theClagwillbesetto1.
ACC ACC−[m]
OV,Z,AC,C
Rev. 1.00
109
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BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
SUBM A,[m]
Description
Operation
Affectedlag(s)
SubtractDataMemoryfromACCwithresultinDataMemory
ThespeciiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis
storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theClagwillbe
clearedto0,otherwiseiftheresultispositiveorzero,theClagwillbesetto1.
[m] ACC−[m]
OV,Z,AC,C
SUB A,x
Description
Operation
Affectedlag(s)
SubtractimmediatedatafromACC
TheimmediatedataspeciiedbythecodeissubtractedfromthecontentsoftheAccumulator.
TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC
lagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theClagwillbesetto1.
ACC ACC−x
OV,Z,AC,C
SWAP [m]
Description
Operation
Affectedlag(s)
SwapnibblesofDataMemory
Thelow-orderandhigh-ordernibblesofthespeciiedDataMemoryareinterchanged.
[m].3~[m].0 [m].7~[m].4
None
SWAPA [m]
Description
Operation
Affectedlag(s)
SwapnibblesofDataMemorywithresultinACC
Thelow-orderandhigh-ordernibblesofthespeciiedDataMemoryareinterchanged.The
resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.
ACC.3~ACC.0 [m].7~[m].4
ACC.7~ACC.4 [m].3~[m].0
None
SZ [m]
Description
Operation
Affectedlag(s)
SkipifDataMemoryis0
IfthecontentsofthespeciiedDataMemoryis0,thefollowinginstructionisskipped.Asthis
requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo
cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.
Skipif[m]=0
None
SZA [m]
Description
Operation
Affectedlag(s)
SkipifDataMemoryis0withdatamovementtoACC
ThecontentsofthespeciiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero,
thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction
whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the
programproceedswiththefollowinginstruction.
ACC [m]
Skipif[m]=0
None
SZ [m].i
Description
Operation
Affectedlag(s)
SkipifbitiofDataMemoryis0
IfbitiofthespeciiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires
theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle
instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.
Skipif[m].i=0
None
Rev. 1.00
110
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
TABRDC [m]
Description
Operation
Affectedlag(s)
Readtable(currentpage)toTBLHandDataMemory
Thelowbyteoftheprogramcodeaddressedbythetablepointer(TBLP/TBHP)is
movedtothespeciiedDataMemoryandthehighbytemovedtoTBLH.
[m] programcode(lowbyte)
TBLH programcode(highbyte)
None
TABRDL [m]
Description
Operation
Affectedlag(s)
Readtable(lastpage)toTBLHandDataMemory
Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved
tothespeciiedDataMemoryandthehighbytemovedtoTBLH.
[m] programcode(lowbyte)
TBLH programcode(highbyte)
None
XOR A,[m]
Description
Operation
Affectedlag(s)
LogicalXORDataMemorytoACC
DataintheAccumulatorandthespeciiedDataMemoryperformabitwiselogicalXOR
operation.TheresultisstoredintheAccumulator.
ACC ACC XOR [m]
Z
XORM A,[m]
Description
Operation
Affectedlag(s)
LogicalXORACCtoDataMemory
DatainthespeciiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR
operation.TheresultisstoredintheDataMemory.
[m] ACC XOR [m]
Z
XOR A,x
Description
Operation
Affectedlag(s)
LogicalXORimmediatedatatoACC
DataintheAccumulatorandthespeciiedimmediatedataperformabitwiselogicalXOR
operation.TheresultisstoredintheAccumulator.
ACC ACC XOR x
Z
Rev. 1.00
111
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Package Information
Note that the package information provided here is for consultation purposes only.As this
informationmaybeupdatedatregularintervalsusersareremindedtoconsulttheHoltekwebsitefor
thelatestversionofthepackageinformation.
Additionalsupplementaryinformationwithregardtopackagingislistedbelow.Clickontherelevant
sectiontobetransferredtotherelevantwebsitepage.
• FurtherPackageInformation(includeOutlineDimensions,ProductTapeandReelSpeciications)
• PackingMeterialsInformation
• Cartoninformation
• PBFREEProducts
• GreenPackagesProducts
Rev. 1.00
112
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
16-pin NSOP (150mil) Outline Dimensions
MS-012
Symbol
Min.
Nom.
Max.
A
0.228
—
0.244
—
0.157
—
0.402
0.069
B
0.150
C
0.012
C’
0.386
D
—
—
E
—
0.050
—
F
0.004
—
0.010
0.020
G
0.016
—
0.050
H
0.007
—
0.010
0°
—
8°
Symbol
Rev. 1.00
Dimensions in inch
Dimensions in mm
Min.
Nom.
Max.
A
5.79
—
6.20
B
3.81
—
3.99
C
0.30
C’
9.80
—
10.21
D
—
—
1.75
E
—
1.27
—
F
0.10
—
0.25
0.51
G
0.41
—
1.27
H
0.18
—
0.25
0°
—
8°
113
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
16-pin SSOP(150mil) Outline Dimensions
Symbol
A
Dimensions in inch
Min.
Nom.
Min.
0.228
—
0.244
0.157
B
0.150
—
C
0.008
—
0.012
C’
0.189
—
0.197
D
0.054
—
0.060
E
—
0.025
—
F
0.004
—
0.010
G
0.022
—
0.028
H
0.007
—
0.010
0°
—
8°
Symbol
Dimensions in mm
Min.
Nom.
A
5.79
—
6.20
B
3.81
—
3.99
C
0.20
—
0.30
C’
4.80
—
5.00
D
1.37
—
1.52
E
—
0.64
—
F
0.10
—
0.25
Rev. 1.00
Min.
G
0.56
—
0.71
H
0.18
—
0.25
0°
—
8°
114
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
20-pin SOP (300mil) Outline Dimensions
MS-013
Symbol
A
Nom.
Max.
0.393
—
0.419
—
0.300
—
0.512
0.104
B
0.256
C
0.012
C’
0.496
D
—
—
E
—
0.050
—
F
0.004
—
0.012
G
0.016
—
0.050
H
0.008
—
0.013
0°
—
8°
Symbol
Rev. 1.00
Dimensions in inch
Min.
0.020
Dimensions in mm
Min.
Nom.
Max.
A
9.98
—
10.64
B
6.50
—
7.62
C
0.30
C’
12.60
—
13.00
D
—
—
2.64
E
—
1.27
—
F
0.10
—
0.30
G
0.41
—
1.27
H
0.20
—
0.33
0°
—
8°
0.51
115
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
20-pin SSOP (150mil) Outline Dimensions
Symbol
A
Dimensions in inch
Min.
Nom.
Max.
0.228
—
0.244
—
0.158
—
0.347
0.065
B
0.150
C
0.008
C’
0.335
D
0.049
—
E
—
0.025
—
F
0.004
—
0.010
0.012
G
0.015
—
0.050
H
0.007
—
0.010
0°
—
8°
Symbol
Dimensions in mm
Min.
Nom.
Max.
6.20
A
5.79
—
B
3.81
—
C
0.20
4.01
0.30
C’
8.51
—
8.81
D
1.24
—
1.65
E
—
0.64
—
F
0.10
—
0.25
G
0.38
—
1.27
H
0.18
—
0.25
0°
—
8°
Rev. 1.00
116
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
24-pin SOP (300mil) Outline Dimensions
MS-013
Symbol
A
Nom.
Min.
0.393
—
0.419
B
0.256
—
0.300
C
0.012
—
0.020
C’
0.598
—
0.613
D
—
—
0.104
E
—
0.050
—
F
0.004
—
0.012
G
0.016
—
0.050
H
0.008
—
0.013
0°
—
8°
Symbol
Rev. 1.00
Dimensions in inch
Min.
Dimensions in mm
Min.
Nom.
Min.
10.64
A
9.98
—
B
6.50
—
7.62
C
0.30
—
0.51
C’
15.19
—
15.57
D
—
—
2.64
E
—
1.27
—
F
0.10
—
0.30
G
0.41
—
1.27
H
0.20
—
0.33
0°
—
8°
117
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
24-pin SSOP (150mil) Outline Dimensions
Symbol
A
Dimensions in inch
Min.
Nom.
Min.
0.228
—
0.244
B
0.150
—
0.157
C
0.008
—
0.012
C’
0.335
—
0.346
D
0.054
—
0.060
E
—
0.025
—
F
0.004
—
0.010
G
0.022
—
0.028
H
0.007
—
0.010
0°
—
8°
Symbol
Dimensions in mm
Min.
Nom.
A
5.79
—
6.20
B
3.81
—
3.99
C
0.20
—
0.30
C’
8.51
—
8.79
D
1.37
—
1.52
E
—
0.64
—
F
0.10
—
0.25
Rev. 1.00
Min.
G
0.56
—
0.71
H
0.18
—
0.25
0°
—
8°
118
May 02, 2013
BS83B08A-3/BS83B12A-3/BS83B16A-3
BS83B08A-4/BS83B12A-4/BS83B16A-4
8-Bit Touch Key Flash MCU
Copyright© 2013 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the speciications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notiication. For the most up-to-date information, please
visit our web site at http://www.holtek.com.
Rev. 1.00
119
May 02, 2013