datasheet for ML610Q419 by LAPIS Semiconductor

datasheet for ML610Q419 by LAPIS Semiconductor
FEDL610Q419-3
Issue Date: Jun5, 2012
ML610Q419/ML610Q419C
8-bit Microcontroller with a Built-in LCD driver
GENERAL DESCRIPTION
This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port,
UART, I2C bus interface (master), melody driver, battery level detect circuit, RC oscillation type A/D converter, and LCD
driver, are incorporated around 8-bit CPU nX-U8/100.
The CPU nX-U8/100 is capable of efficient instruction execution in 1-instruction 1-clock mode by 3-stage pipe line architecture
parallel procesing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation
(read operation) equivalent to mask ROM and is most suitable for battery-driven applications.
The on-chip debug function that is installed enables program debugging and programming.
FEATURES
• CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system: 16-bit instructions
− Instruction set:
Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic
shift, and so on
− On-Chip debug function
− Minimum instruction execution time
30.5 μs (@32.768 kHz system clock)
0.24 4μs (@4.096 MHz system clock)
• Internal memory
− Internal 64KByte Flash ROM (32K×16 bits) (including unusable 1KByte TEST area)
− Internal 4KByte Data Flash (2K×16 bits)
− Internal 2KByte Data RAM (2048×8 bits), 240 9bit Display Allocation RAM
• Interrupt controller
− 1 non-maskable interrupt sources (Internal source: 1)
− 21 maskable interrupt sources (Internal sources: 16, External sources: 5)
• Time base counter
− Low-speed time base counter ×1 channel
Frequency compensation (Compensation range: Approx. −488ppm to +488ppm. Compensation accuracy: Approx.
0.48ppm)
− High-speed time base counter ×1 channel
• Watchdog timer
− Non-maskable interrupt and reset
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s)
• Timers
− 8 bits × 4 channels (Timer0-3: 16-bit x 2 configuration available by using Timer0-1 or Timer2-3)
− Clock frequency measurement mode (in one channel of 16-bit configuration using Timer2-3)
1/37
FEDL610Q419-3
ML610Q419/ML610Q419C
• Capture
− Time base capture × 2 channels (4096 Hz to 32 Hz)
• PWM
− Resolution 16 bits × 1 channel
• Synchronous serial port
− Master/slave selectable × 2 channel
− LSB first/MSB first selectable
− 8-bit length/16-bit length selectable
• UART
− TXD/RXD × 1 channel
− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
− Positive logic/negative logic selectable
− Built-in baud rate generator
• I2C bus interface
− Master function only
− Fast mode (400 [email protected] MH ), standard mode (100 [email protected] , [email protected])
• Melody driver
− Scale: 29 types (Melody sound frequency: 508 Hz to 32.768 kHz)
− Tone length: 63 types
− Tempo: 15 types
− Buzzer output mode (4 output modes, 8 frequencies, 16 duty levels)
• RC oscillation type A/D converter
− 24-bit counter
− Time division × 2 channels
• Successive approximation type A/D converter (SA-ADC)
− 12-bit A/D converter
− Input × 4 channels
• General-purpose ports
− Input-only port × 6 channels (including secondary functions)
− Output-only port × 3 channels (including secondary functions)
− Input/output port
ML610Q419 : 18 channels (including secondary functions)
ML610Q419C : 26 channels (including secondary functions)
2/37
FEDL610Q419-3
ML610Q419/ML610Q419C
• LCD driver
− Dot matrix can be supported.
ML610Q419 : 192 dots max. (48 seg × 4 com)
ML610Q419C : 160 dots max. (40 seg × 4 com)
− 1/1 to 1/4 duty
− 1/2, 1/3 bias (built-in bias generation circuit)
− Frame frequency selecable: approx. 64Hz, 73Hz, 85Hz, and 102Hz
− Bias voltage multiplying clock selectable (8 types)
− LCD drive stop mode, LCD display mode, all LCDs on mode, and all LCDs off mode selectable
− Programmable display allocation function
• Reset
− Reset by the RESET_N pin
− Reset by power-on detection
− Reset when oscillation stop of the low-speed clock is detected
− Reset by low level detection (LLD)
The voltage which is released from reset is selectable by the code-option: 1.1V, 1.8V (Max.)
− Reset by the watchdog timer (WDT) 2nd overflow
• Power supply voltage detect function
− Judgment voltages:
One of 16 levels
− Judgment accuracy:
±2% (Typ.)
• Clock
− Low-speed clock: (This LSI can not guarantee the operation withoug low-speed clock)
Crystal oscillation (32.768 kHz)
− High-speed clock:
Built-in RC oscillation (500kHz)
Built-in PLL oscillation (8.192 MHz ±2.5%), crystal/ceramic oscillation (4.096 MHz), external clock
− Selection of high-speed clock mode by software:
Built-in RC oscillation, built-in PLL oscillation, crystal/ceramic oscillation, external clock
• Power management
− HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).
− STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are
stopped.)
− Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation
clock)
− Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals.
• Shipment
− Chip (Die)
ML610Q419-xxxWA (Blank product: ML610Q419-NNNWA)
ML610Q419P-xxxWA (Blank product: ML610Q419P-NNNWA)
ML610Q419C-xxxWA (Blank product: ML610Q419C-NNNWA)
ML610Q419PC-xxxWA (Blank product: ML610Q419PC-NNNWA)
− 100-pin plastic TQFP
ML610Q419-xxxTBZ0AAL (Blank product: ML610Q419-xxxTBZ0AAL)
ML610Q419P-xxxTB0AAL (Blank product: ML610Q419P-xxxTB0AAL)
ML610Q419C-xxxTB0AAL (Blank product: ML610Q419C-xxxTB0AAL)
ML610Q419PCxxxTB0AAL (Blank product: ML610Q419PCxxxTB0AAL)
xxx: ROM code number
• Guaranteed operating range
− Operating temperature: −20°C to 70°C (P version: −40°C to 85°C)
− Operating voltage: VDD = 1.1V to 3.6V
3/37
FEDL610Q419-3
ML610Q419/ML610Q419C
BLOCK DIAGRAM
ML610Q419 Block Diagram
Figure 1 show the block diagram of the ML610Q419.
"*" indicates the secondary function of each port.
CPU (nX-U8/100)
EPSW1 3
GREG
0 15
PSW
Timing
Controller
On-Chip
ICE
Instruction
Decoder
IN0*
CS0*
RS0*
RT0*
CRT0*
RCM*
IN1*
CS1*
RS1*
RT1*
AIN0, AIN1,
AIN2, AIN3
EA
PC
Instruction
Register
Interrupt
Controller
INT
1
OSC
Power
INT
4
RC-ADC
2
INT
4
INT
1
BLD
WDT
Capture
2
INT
1
12bit-ADC
Program
Memory
(Flash)
64Kbyte
+
Data
Flash
4Kbyte
BUS
Controller
INT
2
RAM
2048byte
RESET &
TEST
AVDD
AVSS
VREF
DSR/CSR
Data-bus
LSCLK*
OUTCLK*
VDDL
LR
SP
XT0
XT1
OSC0*
OSC1*
ECSR1 3
ALU
VDD
VSS
RESET_N
TEST0
TEST1_N
ELR1 3
SSIO
2
SCK0*
SIN0*
SOUT0*
SCK1*
SIN1*
SOUT1*
INT
1
UART
RXD0*
TXD0*
I2C
SDA*
SCL*
INT
1
INT
1
PWM
PWM0*
INT
1
Melody
TBC
INT
5
8bit Timer
2
GPIO
MD0*
P00 to P03
P10 to P11
P20 to P22
P30 to P35
P40 to P47
P50 to P53
Display Allocation
RAM
Display
register
192bit
LCD
Driver
COM0 to COM3
LCD
BIAS
VL1, VL2, VL3
SEG0 to SEG47
C1, C2
Figure 1 ML610Q419 Block Diagram
4/37
FEDL610Q419-3
ML610Q419/ML610Q419C
ML610Q419C Block Diagram
Figure 2 show the block diagram of the ML610Q419C.
"*" indicates the secondary function of each port.
CPU (nX-U8/100)
EPSW1 3
GREG
0 15
PSW
Timing
Controller
On-Chip
ICE
Instruction
Decoder
IN0*
CS0*
RS0*
RT0*
CRT0*
RCM*
IN1*
CS1*
RS1*
RT1*
AIN0, AIN1,
AIN2, AIN3
EA
PC
Instruction
Register
Interrupt
Controller
INT
1
OSC
Power
INT
4
RC-ADC
2
INT
4
INT
1
BLD
WDT
Capture
2
INT
1
12bit-ADC
Program
Memory
(Flash)
64Kbyte
+
Data
Flash
4Kbyte
BUS
Controller
INT
2
RAM
2048byte
RESET &
TEST
AVDD
AVSS
VREF
DSR/CSR
Data-bus
LSCLK*
OUTCLK*
VDDL
LR
SP
XT0
XT1
OSC0*
OSC1*
ECSR1 3
ALU
VDD
VSS
RESET_N
TEST0
TEST1_N
ELR1 3
SSIO
2
SCK0*
SIN0*
SOUT0*
SCK1*
SIN1*
SOUT1*
INT
1
UART
RXD0*
TXD0*
I2C
SDA*
SCL*
INT
1
INT
1
PWM
PWM0*
INT
1
Melody
TBC
INT
5
8bit Timer
2
GPIO
Display Allocation
RAM
Display
register
192bit
MD0*
P00 to P03
P10 to P11
P20 to P22
P30 to P35
P40 to P47
P50 to P53
P60 to P67
LCD
Driver
COM0 to COM3
LCD
BIAS
VL1, VL2, VL3
SEG0 to SEG39
C1, C2
Figure 2 ML610Q419C Block Diagram
5/37
ML610Q419 TQFP100 Pin Layout
PIN CONFIGURATION
(NC): No Connection
Figure 3 ML610Q419 TQFP100 Pin Configuration
FEDL610Q419-3
ML610Q419/ML610Q419C
6/37
FEDL610Q419-3
ML610Q419/ML610Q419C
ML610Q419C TQFP100 Pin Layout
(NC): No Connection
Figure 4 ML610Q419C TQFP100 Pin Configuration
7/37
FEDL610Q419-3
ML610Q419/ML610Q419C
ML610Q419 Chip Dimension
Chip size:
PAD count:
Minimum PAD pitch:
PAD aperture:
Chip thickness:
Voltage of the rear side of chip:
2.64 mm × 3.20 mm
100 pins
80 μm
70 μm × 70 μm
350 μm
VSS level
Figure 5 ML610Q419 Chip Dimension
8/37
ML610Q419C Chip Dimension
Chip size:
PAD count:
Minimum PAD pitch:
PAD aperture:
Chip thickness:
Voltage of the rear side of chip:
2.64 mm × 3.20 mm
100 pins
80 μm
70 μm × 70 μm
350 μm
VSS level
Figure 6 ML610Q419C Chip Dimension
FEDL610Q419-3
ML610Q419/ML610Q419C
9/37
FEDL610Q419-3
ML610Q419/ML610Q419C
ML610Q419 Pad Coordinates
Table 1 ML610Q419 Pad Coordinates
Chip Center: X=0,Y=0
PAD
No.
Pad
Name
X
( m)
Y
( m)
PAD
No.
Pad
Name
X
( m)
Y
( m)
PAD
No.
Pad
Name
X
( m)
Y
( m)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Vref
AVSS
VSS
P20
P21
P22
P40
P41
P42
P43
P44
P45
P46
P47
VDD
VSS
VDDL
XT0
XT1
RESET_N
TEST0
TEST1_N
VL1
VL2
VL3
C1
C2
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
-1020.0
-860.0
-780.0
-700.0
-620.0
-540.0
-460.0
-380.0
-280.0
-200.0
-120.0
-40.0
40.0
120.0
204.0
284.0
364.0
452.0
612.0
692.0
772.0
852.0
932.0
1012.0
1092.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1325.0
-1245.0
-1165.0
-1085.0
-1005.0
-925.0
-845.0
-765.0
-685.0
-605.0
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1060.0
980.0
900.0
820.0
740.0
660.0
580.0
500.0
420.0
340.0
260.0
180.0
100.0
20.0
-60.0
-140.0
-220.0
-300.0
-380.0
-460.0
-540.0
-525.0
-445.0
-365.0
-285.0
-205.0
52.0
258.0
464.0
670.0
876.0
1015.0
1095.0
1175.0
1255.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
P01
P00
P11
P10
P50
P51
P52
P53
P02
P03
P30
P31
P34
P32
P33
P35
AIN0
AIN1
AIN02
AIN03
AVDD
-620.0
-730.0
-810.0
-890.0
-970.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
1494.0
1494.0
1494.0
1494.0
1494.0
1380.0
1300.0
1220.0
1140.0
1040.0
850.0
760.0
600.0
476.0
270.0
28.0
-52.0
-132.0
-212.0
-292.0
-372.0
-452.0
-532.0
-612.0
-692.0
-833.0
-913.0
-1085.0
-1165.0
-1291.0
10/37
FEDL610Q419-3
ML610Q419/ML610Q419C
ML610Q419C Pad Coordinates
Table 2 ML610Q419C Pad Coordinates
Chip Center: X=0,Y=0
PAD
No.
Pad
Name
X
( m)
Y
( m)
PAD
No.
Pad
Name
X
( m)
Y
( m)
PAD
No.
Pad
Name
X
( m)
Y
( m)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Vref
AVSS
VSS
P20
P21
P22
P40
P41
P42
P43
P44
P45
P46
P47
VDD
VSS
VDDL
XT0
XT1
RESET_N
TEST0
TEST1_N
VL1
VL2
VL3
C1
C2
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
-1020.0
-860.0
-780.0
-700.0
-620.0
-540.0
-460.0
-380.0
-280.0
-200.0
-120.0
-40.0
40.0
120.0
204.0
284.0
364.0
452.0
612.0
692.0
772.0
852.0
932.0
1012.0
1092.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1494.0
-1325.0
-1245.0
-1165.0
-1085.0
-1005.0
-925.0
-845.0
-765.0
-685.0
-605.0
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1214.0
1060.0
980.0
900.0
820.0
740.0
660.0
580.0
500.0
420.0
340.0
260.0
180.0
100.0
20.0
-60.0
-140.0
-220.0
-300.0
-380.0
-460.0
-540.0
-525.0
-445.0
-365.0
-285.0
-205.0
52.0
258.0
464.0
670.0
876.0
1015.0
1095.0
1175.0
1255.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
1494.0
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SEG39
P60
P61
P62
P63
P64
P65
P66
P67
P01
P00
P11
P10
P50
P51
P52
P53
P02
P03
P30
P31
P34
P32
P33
P35
AIN0
AIN1
AIN02
AIN03
AVDD
-620.0
-730.0
-810.0
-890.0
-970.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
-1214.0
1494.0
1494.0
1494.0
1494.0
1494.0
1380.0
1300.0
1220.0
1140.0
1040.0
850.0
760.0
600.0
476.0
270.0
28.0
-52.0
-132.0
-212.0
-292.0
-372.0
-452.0
-532.0
-612.0
-692.0
-833.0
-913.0
-1085.0
-1165.0
-1291.0
11/37
FEDL610Q419-3
ML610Q419/ML610Q419C
PIN LIST
Primary function
PAD No.
Q419
Q419C
Pin name
Secondary function
Tertiary function
I/O
Function
Pin name
I/O
Function
Pin name
I/O
Function
Negative power
supply pin
Positive power supply
pin
Power supply pin for
internal logic
(internally generated)
Negative power
supply pin for
successive
approximation type
ADC
Positive power supply
pin for successive
approximation type
ADC
Reference power
supply pin for
successive
approximation type
ADC
Successive
approximation type
ADC input
Successive
approximation type
ADC input
Successive
approximation type
ADC input
Successive
approximation type
ADC input
Power supply pin for
LCD bias (internally
generated)
Power supply pin for
LCD bias (internally
generated)
Power supply pin for
LCD bias (internally
generated)
Capacitor connection
pin for LCD bias
generation
Capacitor connection
pin for LCD bias
generation
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
3, 16
3. 16
Vss
⎯
15
15
VDD
⎯
17
17
VDDL
⎯
2
2
AVSS
⎯
100
100
AVDD
⎯
1
1
VREF
⎯
96
96
AIN0
⎯
97
97
AIN1
⎯
98
98
AIN2
⎯
99
99
AIN3
⎯
23
23
VL1
⎯
24
24
VL2
⎯
25
25
VL3
⎯
26
26
C1
⎯
27
27
C2
⎯
21
21
TEST0
I/O
Test pin
⎯
⎯
⎯
⎯
⎯
⎯
22
22
TEST1_N
I
Test pin
⎯
⎯
⎯
⎯
⎯
⎯
20
20
RESET_N
I
⎯
⎯
⎯
⎯
⎯
⎯
18
18
XT0
I
⎯
⎯
⎯
⎯
⎯
⎯
19
19
XT1
O
⎯
⎯
⎯
⎯
⎯
⎯
81
81
P00/EXI0/
CAP0
I
⎯
⎯
⎯
⎯
⎯
⎯
80
80
P01/EXI1/
CAP1
I
⎯
⎯
⎯
⎯
⎯
⎯
88
88
P02/EXI2
/RXD0
I
Reset input pin
Low-speed clock
oscillation pin
Low-speed clock
oscillation pin
Input port,
External interrupt,
Capture 0 input
Input port,
External interrupt,
Capture 1 input
Input port,
External interrupt,
UART0 received data
⎯
⎯
⎯
⎯
⎯
⎯
12/37
FEDL610Q419-3
ML610Q419/ML610Q419C
Primary function
PAD No.
Q419
Q419C
Pin name
I/O
Function
Secondary function
Tertiary function
Pin name
I/O
Function
Pin name
I/O
Function
⎯
⎯
⎯
⎯
⎯
⎯
High-speed
oscillation
High-speed
oscillation
Low-speed clock
output
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
89
89
P03/EXI3
I
Input port,
External interrupt
83
83
P10
I
Input port
OSC0
I
82
82
P11
I
Input port
OSC1
O
4
4
P20/LED0
O
Output port
LSCLK
O
5
5
P21/LED
1
O
Output port
OUTCLK
O
High-speed clock
output
⎯
⎯
⎯
6
6
P22/LED
2
O
Output port
MD0
O
Melody 0 output
⎯
⎯
⎯
90
90
P30
I/O
Input/output port
IN0
I
⎯
⎯
⎯
91
91
P31
I/O
Input/output port
CS0
O
⎯
⎯
⎯
93
93
P32
I/O
Input/output port
RS0
O
⎯
⎯
⎯
94
94
P33
I/O
Input/output port
RT0
O
⎯
⎯
⎯
92
92
P34
I/O
Input/output port
RCT0
O
PWM0
O
95
95
P35
I/O
Input/output port
RCM
O
⎯
⎯
7
7
P40
I/O
Input/output port
SDA
I/O
SIN0
I
8
8
P41
I/O
Input/output port
SCL
I/O
SCK0
I/O
9
9
P42
I/O
Input/output port
RXD0
I
RC type ADC0
oscillation input
pin
RC type ADC0
reference
capacitor
connection pin
RC type ADC0
reference resistor
connection pin
RC type ADC0
measurement
resistor sensor
connection pin
RC type ADC0
resistor/capacitor
sensor connection
pin
RC type ADC
oscillation monitor
I2C data
input/output
I2C clock
input/output
UART data input
10
10
P43
I/O
Input/output port
TXD0
O
UART data output
IN1
I
RC type ADC1
oscillation input
pin
PWM output
⎯
SSIO0 data input
SOUT0
O
SSIO0
synchronous clock
SSIO0 data output
PWM0
O
PWM output
SIN0
I
SSIO0 data input
SCK0
I/O
SSIO0
synchronous clock
SOUT0
O
SSIO0 data output
⎯
⎯
⎯
SIN1
I
SSIO1 data input
11
11
P44/T02P
0CK
I/O
Input/output port,
Timer 0/Timer
2/PWM0 external
clock input
12
12
P45/T13C
K
I/O
Input/output port,
Timer 1/Timer 3
external clock input
CS1
O
13
13
P46
I/O
Input/output port
RS1
O
14
14
P47
I/O
Input/output port
RT1
O
84
84
P50/EXI8
I/O
Input/output port,
External interrupt
MD0
O
85
85
P51/EXI8
I/O
Input/output port,
External interrupt
⎯
⎯
⎯
SCK1
I/O
SSIO1
synchronous clock
input/output
86
86
P52/EXI8
I/O
⎯
⎯
⎯
SOUT1
O
SSIO1 data output
87
87
P53/EXI8
I/O
⎯
⎯
⎯
⎯
⎯
⎯
28
28
COM0
O
Input/output port,
External interrupt
Input/output port,
External interrupt
LCD common pin
⎯
⎯
⎯
⎯
⎯
⎯
29
29
COM1
O
LCD common pin
⎯
⎯
⎯
⎯
⎯
⎯
30
30
COM2
O
LCD common pin
⎯
⎯
⎯
⎯
⎯
⎯
31
31
COM3
O
LCD common pin
⎯
⎯
⎯
⎯
⎯
⎯
RC type ADC1
reference
capacitor
connection pin
RC type ADC1
reference resistor
connection pin
RC type ADC1
resistor sensor
connection pin
Melody 0 output
13/37
FEDL610Q419-3
ML610Q419/ML610Q419C
Primary function
PAD No.
Q419
Q419C
Pin name
I/O
32
32
SEG0
O
33
33
SEG1
O
34
34
SEG2
35
35
36
37
Function
Secondary function
Tertiary function
Pin name
I/O
Function
Pin name
I/O
Function
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
SEG3
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
36
SEG4
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
37
SEG5
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
38
38
SEG6
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
39
39
SEG7
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
40
40
SEG8
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
41
41
SEG9
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
42
42
SEG10
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
43
43
SEG11
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
44
44
SEG12
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
45
45
SEG13
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
46
46
SEG14
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
47
47
SEG15
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
48
48
SEG16
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
49
49
SEG17
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
50
50
SEG18
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
51
51
SEG19
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
52
52
SEG20
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
53
53
SEG21
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
54
54
SEG22
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
55
55
SEG23
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
56
56
SEG24
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
57
57
SEG25
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
58
58
SEG26
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
59
59
SEG27
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
60
60
SEG28
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
61
61
SEG29
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
62
62
SEG30
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
63
63
SEG31
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
64
64
SEG32
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
65
65
SEG33
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
66
66
SEG34
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
67
67
SEG35
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
68
68
SEG36
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
69
69
SEG37
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
70
70
SEG38
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
71
71
SEG39
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
72
⎯
SEG40
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
73
⎯
SEG41
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
74
⎯
SEG42
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
75
⎯
SEG43
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
76
⎯
SEG44
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
77
⎯
SEG45
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
78
⎯
SEG46
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
79
⎯
SEG47
O
LCD segment pin
⎯
⎯
⎯
⎯
⎯
⎯
⎯
72
P60
I/O
Input/output port
⎯
⎯
⎯
⎯
⎯
⎯
⎯
73
P61
I/O
Input/output port
⎯
⎯
⎯
⎯
⎯
⎯
⎯
74
P62
I/O
Input/output port
⎯
⎯
⎯
⎯
⎯
⎯
⎯
75
P63
I/O
Input/output port
⎯
⎯
⎯
⎯
⎯
⎯
⎯
76
P64
I/O
Input/output port
⎯
⎯
⎯
⎯
⎯
⎯
14/37
FEDL610Q419-3
ML610Q419/ML610Q419C
Primary function
PAD No.
Q419
Q419C
Pin name
I/O
⎯
77
P65
I/O
⎯
78
P66
I/O
⎯
79
P67
I/O
Function
Secondary function
Tertiary function
Pin name
I/O
Function
Pin name
I/O
Function
Input/output port
⎯
⎯
⎯
⎯
⎯
⎯
Input/output port
⎯
⎯
⎯
⎯
⎯
⎯
Input/output port
⎯
⎯
⎯
⎯
⎯
⎯
15/37
FEDL610Q419-3
ML610Q419/ML610Q419C
PIN DESCRIPTION
Pin name
I/O
Description
Primary/
Secondary/
Tertiary
Logic
—
Negative
—
—
—
—
Secondary
Secondary
—
—
Secondary
—
Secondary
—
Primary
Positive
Primary
Positive
Primary
Positive
Primary
Positive
Primary
Positive
Primary
Positive
Primary
Positive
System
Reset input pin. When this pin is set to a “L” level, system reset mode is
set and the internal section is initialized. When this pin is set to a “H” level
subsequently, program execution starts. A pull-up resistor is internally
connected.
XT0
I Crystal connection pin for low-speed clock.
XT1
O A 32.768 kHz crystal oscillator (see measuring circuit 1) is connected to
this pin. Capacitors CDL and CGL are connected across this pin and VSS
as required.
OSC0
I Crystal/ceramic connection pin for high-speed clock.
OSC1
O A crystal or ceramic is connected to this pin (4.1 MHz max.). Capacitors
CDH and CGH (see measuring circuit 1) are connected across this pin
and VSS.
This pin is used as the secondary function of the P10 pin(OSC0) and P11
pin(OSC1).
LSCLK
O Low-speed clock output pin. This pin is used as the secondary function of
the P20 pin.
OUTCLK
O High-speed clock output pin. This pin is used as the secondary function of
the P21 pin.
General-purpose input port
RESET_N
I
General-purpose input port.
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
P10-P11
I General-purpose input port.
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
General-purpose output port
P20-P22
O General-purpose output port.
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
General-purpose input/output port
P30-P35
I/O General-purpose input/output port.
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
P40-P47
I/O General-purpose input/output port.
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
P50-P53
I/O General-purpose input/output port.
Since these pins have secondary functions, the pins cannot be used as a
port when the secondary functions are used.
P00-P03
P60-P67
I
I/O General-purpose input/output port.
These pins are for the ML610Q419C, but are not provided in the
ML610Q419.
16/37
FEDL610Q419-3
ML610Q419/ML610Q419C
Pin name
Primary/
Secondary/
Tertiary
Logic
Secondary
Positive
Primary/Se
condary
Positive
Secondary
Positive
Secondary
Positive
I/O Synchronous serial clock input/output pin. This pin is used as the tertiary
function of the P41 or P45 pin.
I Synchronous serial data input pin. This pin is used as the tertiary function
of the P40 or P44 pin.
O Synchronous serial data output pin. This pin is used as the tertiary
function of the P42 or P46 pin.
I/O Synchronous serial clock input/output pin. This pin is used as the tertiary
function of the P51 pin.
I Synchronous serial data input pin. This pin is used as the tertiary function
of the P50 pin.
O Synchronous serial data output pin. This pin is used as the tertiary
function of the P52 pin.
Tertiary
—
Tertiary
Positive
Tertiary
Positive
Tertiary
—
Tertiary
Positive
Tertiary
Positive
PWM0 output pin. This pin is used as the tertiary function of the P43 or
P34 pin.
PWM0 external clock input pin. This pin is used as the primary function of
the P44 pin.
Tertiary
Positive
Primary
—
External maskable interrupt input pins. Interrupt enable and edge
selection can be performed for each bit by software. These pins are used
as the primary functions of the P00-P03 pins.
External maskable interrupt input pins. Interrupt enable and edge
selection can be performed for each bit by software. These pins are used
as the primary functions of the P50-P53 pins.
Primary
Positive/
negative
Primary
Positive/
negative
Capture trigger input pins. The value of the time base counter is captured
in the register synchronously with the interrupt edge selected by software.
These pins are used as the primary functions of the P00 pin(CAP0) and
P01 pin(CAP1).
Primary
I/O
UART
TXD0
O
RXD0
I
Description
UART data output pin. This pin is used as the secondary function of the
P43 pin.
UART data input pin. This pin is used as the secondary function of the
P42 or the primary function of the P02 pin.
2
I C bus interface
2
SDA
I/O I C data input/output pin. This pin is used as the secondary function of the
P40 pin. This pin has an NMOS open drain output. When using this pin as
2
a function of the I C, externally connect a pull-up resistor.
2
SCL
O I C clock output pin. This pin is used as the secondary function of the P41
pin. This pin has an NMOS open drain output. When using this pin as a
2
function of the I C, externally connect a pull-up resistor.
Synchronous serial (SSIO)
SCK0
SIN0
SOUT0
SCK1
SIN1
SOUT1
PWM
PWM0
T0P0CK
O
I
External interrupt
EXI0-3
I
EXI8
I
Capture
CAP0
I
CAP1
I
Primary
—
—
Timer
T0P0CK
I
T1P1CK
I
External clock input pin used for Timer 0. This pin is used as the primary
function of the P44 pin.
External clock input pin used for Timer 1. This pin is used as the primary
function of the P45 pin.
Melody
MD0
O
Melody/buzzer signal output pin. This pin is used as the secondary
function of the P22 pin.
LED drive
LED0-2
O
Nch open drain output pins to drive LED.
Primary
Primary
—
—
Secondary Positive/
negative
Primary
Positive/
negative
17/37
FEDL610Q419-3
ML610Q419/ML610Q419C
Pin name
I/O
Description
RC oscillation type A/D converter
IN0
I Channel 0 oscillation input pin. This pin is used as the secondary function
of the P30 pin.
CS0
O Channel 0 reference capacitor connection pin. This pin is used as the
secondary function of the P31 pin.
RS0
O This pin is used as the secondary function of the P32 pin which is the
reference resistor connection pin of Channel 0.
RT0
O Resistor sensor connection pin of Channel 0 for measurement. This pin is
used as the secondary function of the P34 pin.
CRT0
O Resistor/capacitor sensor connection pin of Channel 0 for measurement.
This pin is used as the secondary function of the P33 pin.
RCM
O RC oscillation monitor pin. This pin is used as the secondary function of
the P35 pin.
IN1
I Oscillation input pin of Channel 1. This pin is used as the secondary
function of the P44 pin.
CS1
O Reference capacitor connection pin of Channel 1. This pin is used as the
secondary function of the P45 pin.
RS1
O Reference resistor connection pin of Channel 1. This pin is used as the
secondary function of the P46 pin.
RT1
O Resistor sensor connection pin for measurement of Channel 1. This pin is
used as the secondary function of the P47 pin.
Successive approximation type A/D converter
AVSS
— Negative power supply pin for successive approximation type A/D
converter.
AVDD
— Positive power supply pin for successive approximation type A/D
converter.
VREF
— Reference power supply pin for successive approximation type A/D
converter.
AIN0
I Channel 0 analog input for successive approximation type A/D converter.
AIN1
I Channel 1 analog input for successive approximation type A/D converter.
AIN2
I Channel 2 analog input for successive approximation type A/D converter.
AIN3
I Channel 3 analog input for successive approximation type A/D converter.
LCD drive signal
COM0-3
O Common output pins.
SEG0-39
O Segment output pins.
SEG40-47
O Segment output pins.
These pins are for the ML610Q419, but are not provided in the
ML610Q419C.
LCD driver power supply
VL1
— Power supply pins for LCD bias (internally generated). Capacitors Ca, Cb,
VL2
— and Cc (see measuring circuit 1) are connected between VSS and VL1, VL2,
VL3
— and VL3 respectively.
Power supply pins for LCD bias (internally generated). Capacitors C12 is
C1
— connected between C1 and C2.
Primary/
Secondary/
Tertiary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Secondary
Logic
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C2
For testing
—
—
—
TEST0
TEST1_N
Power supply
VSS
VDD
VDDL
I/O Input/output pin for testing. A pull-down resistor is internally connected.
I Input/output pin for testing. A pull-up resistor is internally connected.
—
—
—
—
—
—
—
—
—
—
—
—
—
Negative power supply pin.
Positive power supply pin.
Positive power supply pin (internally generated) for internal logic.
Capacitors CL0 and CL1 (see measuring circuit 1) are connected between
this pin and VSS.
18/37
FEDL610Q419-3
ML610Q419/ML610Q419C
TERMINATION OF UNUSED PINS
Table 3 shows methods of terminating the unused pins.
Table 3
Pin
Termination of Unused Pins
Recommended pin termination
AVDD
VSS
AVSS
VSS
VREF
VSS
AIN0, AIN1, AIN2, AIN3
Open
VL1, VL2, VL3
Open
C1, C2
RESET_N
TEST0
TEST1_N
P00 to P03
P10 to P11
P20 to P22
P30 to P35
P40 to P47
P50 to P53
P60 to P67
COM0 to 3
SEG0 to 47
Open
Open
Open
Open
VDD or VSS
VDD
Open
Open
Open
Open
Open
Open
Open
Note:
It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or
the output mode since the supply current may become excessively large if the pins are left open in the high impedance input
setting.
The main difference points of ML610Q419 and ML610Q419C
Table 4
The main difference points of ML610Q419 and ML610Q419C
Function
LCD SEG
ML610Q419
ML610Q419C
SEG47 to SEG0
SEG39 to SEG0
19/37
FEDL610Q419-3
ML610Q419/ML610Q419C
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
(VSS = 0V)
Parameter
Symbol
Condition
Rating
Unit
Power supply voltage 1
VDD
Ta = 25°C
−0.3 to +4.6
V
Power supply voltage 2
AVDD
Ta = 25°C
−0.3 to +4.6
V
Power supply voltage 3
VDDL
Ta = 25°C
−0.3 to +3.6
V
Power supply voltage 4
VL1
Ta = 25°C
−0.3 to +1.75
V
Power supply voltage 5
VL2
Ta = 25°C
−0.3 to +3.5
V
Power supply voltage 6
VL3
Ta = 25°C
−0.3 to +5.25
V
VIN
Ta = 25°C
−0.3 to VDD+0.3
V
Output voltage
VOUT
Ta = 25°C
−0.3 to VDD+0.3
V
Output current 1
IOUT1
Port3–5, Ta = 25°C
−12 to +11
mA
Output current 2
IOUT2
Port2, Ta = 25°C
−12 to +20
mA
Power dissipation
PD
Ta = 25°C
0.9
W
Storage temperature
TSTG
⎯
−55 to +150
°C
Input voltage
RECOMMENDED OPERATING CONDITIONS
(VSS = 0V)
Parameter
Symbol
Operating temperature
TOP
Operating voltage
VDD
Operating frequency (CPU)
Low-speed crystal oscillation
frequency
Low-speed crystal oscillation
external capacitor
High-speed crystal/ceramic
oscillation frequency
High-speed crystal oscillation
external capacitor
Capacitor externally connected to
VDD pin
Capacitor externally connected to
VDDL pin
Capacitors externally connected to
VL1, 2, 3 pins
Capacitors externally connected
across C1 and C2 pins
fOP
Condition
Range
Unit
non - P version
-20
+70
°C
P version
-40
+85
°C
fOP = 30k to 625kHz
1.1
3.6
V
1.8
3.6
V
fOP = 30k to 4.2MHz
VDD = 1.1
VDD = 1.3
VDD = 1.8
3.6V
3.6V
3.6V
30k 36k
30k 650k
30k 4.2M
Hz
32.768k
Hz
fXTL
⎯
CDL
CGL
⎯
⎯
fXTH
⎯
4.0M / 4.096M
Hz
CDH
CGH
⎯
⎯
24
24
pF
CV
⎯
More than 2.2 30%
μF
CL0
CL1
⎯
⎯
2.2
0.1
30%
30%
μF
⎯
0.1
30%
μF
⎯
0.47
30%
μF
Ca
b c
C12
3
3
18
18
pF
20/37
FEDL610Q419-3
ML610Q419/ML610Q419C
OPERATING CONDITIONS OF FLASH ROM
(VSS = 0V)
Parameter
Symbol
Operating temperature
TOP
Operating voltage
VDD
Rewrite counts
CEP
Data retention
YDR
Chip-erase time
Block-erase time
Sector-erase time
1-word (16 bits) write time
tCERASE
tBERASE
tSERASE
tWRITE
Condition
Flash ROM, At write/erase
Data flash memory, At write/erase
At write/erase
Flash ROM
Data flash memory
Flash ROM
Data flash memory,
Ta=85°C, 1000 cycles
⎯
⎯
⎯
⎯
Min.
0
-40
1.8
⎯
⎯
10
Rating
Typ.
⎯
⎯
⎯
⎯
⎯
⎯
10
⎯
85
85
85
18
Max.
+40
+85
3.6
100
10k
Unit
°C
°C
V
cycles
years
100
100
100
40
ms
ms
ms
ms
21/37
FEDL610Q419-3
ML610Q419/ML610Q419C
DC CHARACTERISTICS (1/5)
Parameter
(VDD = 1.1 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C,
Ta = -40 to +85°C for P version, unless otherwise specified)
Measuring
Rating
Condition
Unit
circuit
Min.
Typ.
Max.
Symbol
500kHz RC oscillation frequency
Ta = 25°C
VDD =
1.3 to
3.6V
fRC
5
*
Typ.
−10%
Typ.
−25%
500
500
Typ.
+10%
Typ.
+25%
kHz
kHz
fPLL
LSCLK = 32.768kHz
VDD = 1.8 to 3.6V
-2.5%
8.192
+2.5%
MHz
Low-speed crystal oscillation start
2
time*
TXTL
⎯
⎯
0.3
2
s
500kHz RC oscillation start time
TRC
⎯
⎯
50
500
μs
TXTH
VDD = 1.8 to 3.6V
2
20
TPLL
VDD = 1.8 to 3.6V
1
10
TSTOP
⎯
0.2
3
20
PRST
⎯
200
⎯
⎯
PNRST
⎯
⎯
⎯
0.3
TPOR
⎯
⎯
⎯
10
⎯
⎯
200
⎯
⎯
⎯
⎯
⎯
⎯
⎯
1.1
1.8
⎯
1.1
1.8
PLL oscillation frequency*
4
High-speed crystal oscillation start
3
time*
PLL oscillation start time
Low-speed oscillation stop detect
*1
time
Reset pulse width
Reset noise elimination
pulse width
Power-on reset activation
power rise time
6
Low level reset detection voltage
VLLR
Low level reset detection time
TLLR
Release reset voltage
VRER
COLD0=0*
6
COLD0=1*
⎯
6
COLD0=0*
6
COLD0=1*
ms
1
μs
ms
V
μs
V
*1: When low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is reset to shift to
system reset mode.
*2 : Use 32.768kHz crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=12pF).
*3 : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera).
*4 : 1024 clock average.
*5 : Recommended operating temperature (Ta = -20 to +70°C, Ta = -40 to +85°C for P version)
*6 : The COLD0 bit is the code-option which is set up into the Flash memory.
RESET
VIL1
RESET_N
VIL1
PRST
RESET_N pin reset
0.9xVDD
VDD
0.1xVDD
TPOR
Power on reset
VDD
VRER (COLD0=1)
VLLR (COLD0=1)
VRER (COLD0=0)
Release reset voltage
VLLR (COLD0=0)
TLLR
Low level reset
22/37
FEDL610Q419-3
ML610Q419/ML610Q419C
DC CHARACTERISTICS (2/5)
Parameter
VL1 voltage
Symbol
VL1
(VDD = 1.1 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C,
Ta = -40 to +85°C for P version, unless otherwise specified)
Rating
Measuring
Condition
Unit
circuit
Min.
Min.
Min.
VDD = 3.0V, Tj = 25°C
CN4-0 = 00H
CN4-0 = 01H
CN4-0 = 02H
CN4-0 = 03H
CN4-0 = 04H
CN4-0 = 05H
CN4-0 = 06H
CN4-0 = 07H
CN4-0 = 08H
CN4-0 = 09H
CN4-0 = 0AH
CN4-0 = 0BH
CN4-0 = 0CH
CN4-0 = 0DH
CN4-0 = 0EH
CN4-0 = 0FH
CN4-0 = 10H
CN4-0 = 11H
CN4-0 = 12H
CN4-0 = 13H
1
CN4-0 = 14H*
1
CN4-0 = 15H*
1
CN4-0 = 16H*
1
CN4-0 = 17H*
1
CN4-0 = 18H*
1
CN4-0 = 19H*
1
CN4-0 = 1AH*
1
CN4-0 = 1BH*
1
CN4-0 = 1CH*
1
CN4-0 = 1DH*
1
CN4-0 = 1EH*
1
CN4-0 = 1FH*
0.89
0.91
0.93
0.95
0.97
0.99
1.01
1.03
1.05
1.07
1.09
1.11
1.13
1.15
1.17
1.19
1.21
1.23
1.25
1.27
1.29
1.31
1.33
1.35
1.37
1.39
1.41
1.43
1.45
1.47
1.49
1.51
0.94
0.96
0.98
1.00
1.02
1.04
1.06
1.08
1.10
1.12
1.14
1.16
1.18
1.20
1.22
1.24
1.26
1.28
1.30
1.32
1.34
1.36
1.38
1.40
1.42
1.44
1.46
1.48
1.50
1.52
1.54
1.56
VL1 temperature
deviation
VL1
VDD = 3.0V
-1.5
VL1 voltage
dependency
VL1
VDD = 1.3 to 3.6V
5
VL2 voltage
VL3 voltage
VL2
VL3
1/2bias
VDD = 3.0V,
Tj = 25°C,
300kΩ load
(VL3−VSS)
1/3bias
1/2bias
1/3bias
LCD bias voltage
generation time
TBIAS
0.99
1.01
1.03
1.05
1.07
1.09
1.11
1.13
1.15
1.17
1.19
1.21
1.23
1.25
1.27
1.29
1.31
1.33
1.35
1.37
1.39
1.41
1.43
1.45
1.47
1.49
1.51
1.53
1.55
1.57
1.59
1.61
V
1
mV/°C
20
mV/V
VL1×1
Typ.
×09
Typ.
×09
Typ.
×09
VL1×2
VL1×2
V
VL1×3
100
ms
23/37
FEDL610Q419-3
ML610Q419/ML610Q419C
DC CHARACTERISTICS (3/5)
Parameter
Symbol
(VDD = 1.1 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C,
Ta = -40 to +85°C for P version, unless otherwise specified)
Rating
Measuring
Condition
Unit
circuit
Min.
Typ.
Max.
BLD threshold
voltage
VBLD
VDD = 1.35 to 3.6V
BLD threshold
voltage
temperature
deviation
ΔVBLD
VDD = 1.35 to 3.6V
Supply current 1
Supply current 2
Supply current 3
Supply current 4
IDD1
IDD2
IDD3
IDD4
LD2–0 = 0H
LD2–0 = 1H
LD2–0 = 2H
LD2–0 = 3H
LD2–0 = 4H
LD2–0 = 5H
LD2–0 = 6H
LD2–0 = 7H
LD2–0 = 8H
LD2–0 = 9H
LD2–0 = 0AH
LD2–0 = 0BH
LD2–0 = 0CH
LD2–0 = 0DH
LD2–0 = 0EH
LD2–0 = 0FH
CPU: In STOP state.
Low-speed/high-speed oscillation:
stopped.
CPU: In HALT state (LTBC, RTC:
Operating*3*5).
High-speed oscillation: Stopped.
LCD/BIAS circuits: Stopped.
CPU: In 32.768kHz operating
state.*1*3
High-speed oscillation: Stopped.
LCD/BIAS circuits: Operating.*2
CPU: In 500kHz CR operating state.
LCD/BIAS circuits: Operating.*2*3
Typ.
−2%
1.35
1.4
1.45
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.7
2.9
Typ.
+2%
⎯
0
⎯
Ta = 25°C
⎯
0.4
0.8
*
6
⎯
⎯
8
Ta = 25°C
⎯
0.9
1.8
*
6
⎯
⎯
9
Ta = 25°C
⎯
5
8
*
6
⎯
⎯
15
Ta = 25°C
⎯
80
100
6
⎯
⎯
120
V
1
%/°C
μA
μA
μA
μA
*
CPU: In 4.096MHz operating
Ta = 25°C
⎯
0.9
1.0
state.*2*3
Supply current 5
IDD5
mA
PLL: In oscillating state.
6
LCD/BIAS circuits: Operating. *2
*
⎯
⎯
1.2
VDD = 1.8 to 3.6V
CPU: In 4.096MHz operating state.*2
Ta = 25°C
⎯
1.5
1.6
PLL: In oscillating state. *3*4
IDD6
Supply current 6
mA
A/D: In operating state.
6
LCD/BIAS circuits: Operating. *2
*
⎯
⎯
2.5
VDD = AVDD = 3.0V
1
* : CPU operating rate is 100% (No HALT state).
*2 : All SEGs: off waveform, No LCD panel load, 1/3 bias, 1/3 duty, Frame frequency: Approx. 64 Hz,
Bias voltage multiplying clock: 1/128 LSCLK (256Hz)
*3 : Use 32.768kHz crystal resonator DT-26 (Load capacitance 6pF) (made by KDS:DAISHINKU CORP.) is used (CGL=CDL=6pF).
*4 : Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera).
*5 : Significant bits of BLKCON0~BLKCON4 registers are all “1”.
*6 : Recommended operating temperature (Ta = -20 to +70°C, Ta = -40 to +85°C for P version)
24/37
FEDL610Q419-3
ML610Q419/ML610Q419C
DC CHARACTERISTICS (4/5)
Parameter
Symbol
Output voltage 1
nd
(P20–P22/2
function is
selected)
(P30–P36)
(P40–P47)
(P50–P53)
*1
(P60–P67)
VDD−0.5
VDD−0.3
⎯
⎯
⎯
⎯
IOH1 = -0.03mA, VDD = 1.1 to 3.6V
VDD−0.3
⎯
⎯
IOL1 = +0.5mA, VDD = 1.8 to 3.6V
IOL1 = +0.1mA, VDD = 1.3 to 3.6V
⎯
⎯
⎯
⎯
0.5
0.5
IOL1 = +0.03mA, VDD = 1.1 to 3.6V
⎯
⎯
0.3
VOH2
IOH1 = −0.5mA, VDD = 1.8 to 3.6V
IOH1 = -0.1mA, VDD = 1.3 to 3.6V
IOH1 = -0.03mA, VDD = 1.1 to 3.6V
VDD−0.5
VDD−0.3
VDD−0.3
⎯
⎯
⎯
⎯
⎯
⎯
VOL2
IOL2 = +5mA, VDD = 1.8 to 3.6V
⎯
⎯
0.5
VOL3
IOL3 = +3mA, VDD = 2.0 to 3.6V
2
(when I C mode is selected)
⎯
⎯
0.4
VOH4
IOH4 = −0.05mA, VL1=1.2V
VL3−0.2
⎯
⎯
VOL1
Output voltage 3
(P40–P41)
Output voltage 4
(COM0–3)
(SEG0–39)
*2
(SEG40–47)
IOH1 = −0.5mA, VDD = 1.8 to 3.6V
IOH1 = -0.1mA, VDD = 1.3 to 3.6V
VOH1
Output voltage 2
nd
(P20–P22/2
function is Not
selected)
(VDD = 1.1 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C,
Ta = -40 to +85°C for P version, unless otherwise specified)
Measuring
Rating
Condition
Unit
circuit
Min.
Typ.
Max.
VOML4
IOMH4 = +0.05mA, VL1=1.2V
⎯
⎯
VL2+0.2
VOML4S
IOMH4S = −0.05mA, VL1=1.2V
VL2−0.2
⎯
⎯
VOLM4
IOML4 = +0.05mA, VL1=1.2V
⎯
⎯
VL1+0.2
VOLM4S
IOML4S = −0.05mA, VL1=1.2V
VL1−0.2
⎯
⎯
VOL4
IOL4 = +0.05mA, VL1=1.2V
⎯
⎯
0.2
IOOH
VOH = VDD (in high-impedance state)
⎯
⎯
1
Output leakage
(P20–P22)
(P30–P35)
(P40–P47)
(P50–P53)
*1
(P60–P67)
Input current 1
(RESET_N)
(TEST1_N)
Input current 1
(TEST0)
IOOL
IIH1
IIL1
IIH1
IIL1
Input current 2
(P00–P03)
(P10–P11)
(P30–P35)
(P40–P47)
(P50–P53)
*1
(P60–P67)
IIH2
IIL2
IIH2Z
IIL2Z
VOL = VSS (in high-impedance state)
VIH1 = VDD
VDD = 1.8 to 3.6V
VIL1 = VSS
VDD = 1.3 to 3.6V
VDD = 1.1 to 3.6V
VDD = 1.8 to 3.6V
VIH1 = VDD
VDD = 1.3 to 3.6V
VDD = 1.1 to 3.6V
VIL1 = Vss
VIH2 = VDD
(when pulled-down)
VDD = 1.8 to 3.6V
VDD = 1.3 to 3.6V
VDD = 1.1 to 3.6V
VDD = 1.8 to 3.6V
VIL2 = VSS
VDD = 1.3 to 3.6V
(when pulled-up)
VDD = 1.1 to 3.6V
VIH2 = VDD (in high-impedance state)
VIL2 = VSS (in high-impedance state)
−1
⎯
⎯
0
−600
−600
−600
20
10
2
-1
⎯
−300
−300
−300
300
300
300
⎯
1
−20
-10
-2
600
600
600
⎯
2
30
200
0.2
0.01
−200
−200
−200
⎯
−1
30
30
−30
−30
−30
⎯
⎯
200
200
−2
-0.2
-0.01
1
⎯
V
2
μA
3
μA
4
*1: ML610Q419C only
*2: ML610Q419 only
25/37
FEDL610Q419-3
ML610Q419/ML610Q419C
DC CHARACTERISTICS (5/5)
Parameter
Input voltage 1
(RESET_N)
(TEST1_N)
(TEST0)
(P00–P03)
(P10–P11)
(P31–P35)
(P40–P43)
(P45–P47)
(P50–P53)
*1
(P60–P67)
Input voltage 2
(P30, P44)
Symbol
(VDD = 1.1 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C,
Ta = -40 to +85°C for P version, unless otherwise specified)
Rating
Measuring
Condition
Unit
circuit
Min.
Typ.
Max.
VDD = 1.3 to 3.6V
0.7
×VDD
⎯
VDD
VDD = 1.1 to 3.6V
0.7
×VDD
⎯
VDD
VDD = 1.3 to 3.6V
0
⎯
0.3
×VDD
VDD = 1.1 to 3.6V
0
⎯
0.2
×VDD
VIH2
⎯
0.7
×VDD
⎯
VDD
VIL2
⎯
0
⎯
0.3
×VDD
f = 10kHz
Vrms = 50mV
Ta = 25°C
⎯
⎯
5
VIH1
VIL1
Input pin
capacitance
(P00–P03)
(P10–P11)
CIN
(P30–P35)
(P40–P47)
(P50–P53)
*1
(P60–P67)
*1: ML610Q419C only
V
5
pF
⎯
26/37
FEDL610Q419-3
ML610Q419/ML610Q419C
MEASURING CIRCUITS
MEASURING CIRCUIT 1
CGL
XT0
CDL
XT1
C2
32.768kHz
crystal
CGH
C12
C1
P10/OSC0
CDH
P11/OSC1
4.096MHz
crystal
VDD AVDD VREF VDDL
VL1 VL2 VL3
VSS AVSS
A
CV
CL1 CL0
Ca Cb Cc
CV
CL0
CL1
Ca,Cb,Cc
C12
CGL,CDL
CGH,CDH
: >2.2μF
: 2.2μF
: 0.1μF
: 0.1μF
: 0.47μF
: 6pF
: 24pF
32.768kHz crystal resonator
DT-26 (Load capacitance 6pF)
(Made by KDS:DAISHINKU CORP.)
4.096MHz crystal:
HC49SFWB (Kyocera)
MEASURING CIRCUIT 2
(*2)
VIL
Input pins
(*1)
Output pins
VIH
VDD VDDL VL1
VL2
VL3
V
AVDD VREF VSS AVSS
(*1) Input logic circuit to determine the specified measuring conditions.
(*2) Measured at the specified output pins.
27/37
FEDL610Q419-3
ML610Q419/ML610Q419C
MEASURING CIRCUIT 3
(*2)
(*1)
VIL
Output pins
Input pins
VIH
VDD VDDL VL1
VL2
VL3
A
AVDD VREF VSS AVSS
*1: Input logic circuit to determine the specified measuring conditions.
*2: Measured at the specified output pins.
MEASURING CIRCUIT 4
Input pins
Output pins
(*3)
A
VDD VDDL VL1
VL2
VL3
AVDD VREF VSS AVSS
*3: Measured at the specified output pins.
MEASURING CIRCUIT 5
VDD VDDL VL1
VL2
VL3
Waveform monitoring
VIL
Output pins
(*1)
Input pins
VIH
AVDD VREF VSS AVSS
*1: Input logic circuit to determine the specified measuring conditions.
28/37
FEDL610Q419-3
ML610Q419/ML610Q419C
AC CHARACTERISTICS (External Interrupt)
(VDD = 1.1 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C,
Ta = -40 to +85°C for P version, unless otherwise specified)
Rating
Symbol
Condition
Unit
Min.
Typ.
Max.
Parameter
External interrupt disable period
TNUL
Interrupt: Enabled (MIE = 1),
CPU: NOP operation
System clock: 32.768kHz
⎯
76.8
106.8
μs
P00–P03
(Rising-edge interrupt)
tNUL
P00–P03
(Falling-edge interrupt)
tNUL
P00–P03
(Both-edge interrupt)
tNUL
AC CHARACTERISTICS (UART)
Parameter
Transmit baud rate
(VDD = 1.3 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C,
Ta = -40 to +85°C for P version, unless otherwise specified)
Rating
Symbol
Condition
Unit
Min.
Typ.
Max.
tTBRT
⎯
⎯
1
BRT*
1
⎯
s
1
BRT*
BRT*
1
BRT*
s
−3%
+3%
*1: Baud rate period (including the error of the clock frequency selected) set with the UART baud rate register (UA0BRTL,H)
and the UART mode register 0 (UA0MOD0).
Receive baud rate
tRBRT
⎯
tTBRT
TXD0*
tRBRT
RXD0*
*: Indicates the secondary function of the port.
29/37
FEDL610Q419-3
ML610Q419/ML610Q419C
AC CHARACTERISTICS (Synchronous Serial Port)
Parameter
Symbol
(VDD = 1.3 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C,
Ta = -40 to +85°C for P version, unless otherwise specified)
Rating
Condition
Unit
Min.
Typ.
Max.
When high-speed oscillation is
10
⎯
⎯
μs
2
not active* (VDD = 1.3 to 3.6V)
When high-speed oscillation is
1
⎯
⎯
μs
3
active* (VDD = 1.8 to 3.6V)
SCLKn input cycle
(slave mode)
tSCYC
SCLKn output cycle
(master mode)
tSCYC
⎯
SCLKn input pulse width
(slave mode)
tSW
When high-speed oscillation is
2
not active* (VDD = 1.3 to 3.6V)
When high-speed oscillation is
3
active* (VDD = 1.8 to 3.6V)
SCLKn output pulse width
(master mode)
tSW
⎯
SCLKn*
⎯
s
4
⎯
⎯
μs
0.4
⎯
⎯
μs
1
1
SOUTn output delay time
(slave mode)
tSD
SOUTn output delay time
(master mode)
tSD
SINn input setup time
(slave mode)
tSS
SINn input setup time
(master mode)
tSS
SINn input hold time
tSH
1
1
⎯
SCLKn*
×0.4
SCLKn*
×0.5
SCLKn*
×0.6
When high-speed oscillation is
2
not active* (VDD = 1.3 to 3.6V)
When high-speed oscillation is
3
active* (VDD = 1.8 to 3.6V)
When high-speed oscillation is
2
not active* (VDD = 1.3 to 3.6V)
When high-speed oscillation is
3
active* (VDD = 1.8 to 3.6V)
⎯
⎯
500
⎯
⎯
240
⎯
⎯
500
⎯
⎯
240
⎯
80
⎯
⎯
500
⎯
⎯
240
⎯
⎯
300
⎯
⎯
80
⎯
⎯
When high-speed oscillation is
2
not active* (VDD = 1.3 to 3.6V)
When high-speed oscillation is
3
active* (VDD = 1.8 to 3.6V)
When high-speed oscillation is
2
not active* (VDD = 1.3 to 3.6V)
When high-speed oscillation is
3
active* (VDD = 1.8 to 3.6V)
s
ns
ns
ns
ns
ns
n= 0,1
*1: Clock period selected with SnCK3–0 of the serial port n mode register (SIOnMOD1)
2
* : When RC oscillation is selected with OSCM1–0 of the frequency control register (FCON0)
3
* : When Crystal/ceramic oscillation, built-in PLL oscillation, or external clock input is selected with OSCM1–0 of the frequency
control register (FCON0)
tSCYC
tSW
tSW
SCLKn*
tSD
tSD
SOUTn*
tSS
tSH
SINn*
*: Indicates the secondary function of the port.
30/37
FEDL610Q419-3
ML610Q419/ML610Q419C
AC CHARACTERISTICS (I2C Bus Interface: Standard Mode 100kHz)
(VDD = 1.8 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C,
Ta = -40 to +85°C for P version, unless otherwise specified)
Rating
Symbol
Condition
Unit
Min.
Typ.
Max.
fSCL
⎯
0
⎯
100
kHz
Parameter
SCL clock frequency
SCL hold time
(start/restart condition)
SCL ”L” level time
SCL ”H” level time
SCL setup time
(restart condition)
SDA hold time
SDA setup time
SDA setup time
(stop condition)
Bus-free time
tHD:STA
⎯
4.0
⎯
⎯
μs
tLOW
tHIGH
⎯
⎯
4.7
4.0
⎯
⎯
⎯
⎯
μs
μs
tSU:STA
⎯
4.7
⎯
⎯
μs
tHD:DAT
tSU:DAT
⎯
⎯
0
0.25
⎯
⎯
3.45
⎯
μs
μs
tSU:STO
⎯
4.0
⎯
⎯
μs
tBUF
⎯
4.7
⎯
⎯
μs
AC CHARACTERISTICS (I2C Bus Interface: Fast Mode 400kHz)
(VDD = 1.8 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C,
Ta = -40 to +85°C for P version, unless otherwise specified)
Rating
Symbol
Condition
Unit
Min.
Typ.
Max.
fSCL
⎯
0
⎯
400
kHz
Parameter
SCL clock frequency
SCL hold time
(start/restart condition)
SCL ”L” level time
SCL ”H” level time
SCL setup time
(restart condition)
SDA hold time
SDA setup time
SDA setup time
(stop condition)
Bus-free time
tHD:STA
⎯
0.6
⎯
⎯
μs
tLOW
tHIGH
⎯
⎯
1.3
0.6
⎯
⎯
⎯
⎯
μs
μs
tSU:STA
⎯
0.6
⎯
⎯
μs
tHD:DAT
tSU:DAT
⎯
⎯
0
0.1
⎯
⎯
0.9
⎯
μs
μs
tSU:STO
⎯
0.6
⎯
⎯
μs
tBUF
⎯
1.3
⎯
⎯
μs
Start
condition
Restart
condition
Stop
condition
P40/SDA
P41/SCL
tHD:STA
tLOW
tHIGH
tSU:STA tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tBUF
31/37
FEDL610Q419-3
ML610Q419/ML610Q419C
AC CHARACTERISTICS (RC Oscillation A/D Converter)
Condition for VDD=1.8 to 3.6V
Parameter
Oscillation resistor
Oscillation frequency
VDD = 3.0V
RS to RT oscillation
*1
frequency ratio
VDD = 3.0V
(VDD=1.8 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C,
Ta = -40 to +85°C for P version, unless otherwise specified)
Rating
Condition
Unit
Min.
Typ.
Max.
Symbol
RS0,RS1,RT0,
RT0-1,RT1
fOSC1
fOSC2
fOSC3
Kf1
Kf2
Kf3
CS0, CT0, CS1≥740pF
1
Resistor for oscillation=1kΩ
Resistor for oscillation=10kΩ
Resistor for oscillation=100kΩ
RT0, RT0-1, RT1=1kΩ
RT0, RT0-1, RT1=10kΩ
RT0, RT0-1, RT1=100kΩ
457.3
53.48
5.43
7.972
0.981
0.099
kΩ
525.2
58.18
5.89
9.028
1
0.101
575.1
62.43
6.32
9.782
1.019
0.104
kHz
kHz
kHz
⎯
⎯
⎯
*1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the
same conditions.
fOSCX(RT0-1-CS0 oscillation)
fOSCX(RS0-CS0 oscillation)
IN0 CS0 RCT0
RT0
RS0
RS0 RT0
VIL
RCM
VDD
CV
VDDL
RT0, RT0-1, RT1: 1k /10k
RS0, RS1: 10k
CS0, CT0, CS1: 560pF
CVR0, CVR1: 820pF
/100k
IN1 CS1 RS1 RT1
Input pin
VIH
CVR1
RT0-1
CT0
CS0
CVR0
fOSCX(RT1-CS1 oscillation)
fOSCX(RS1-CS1 oscillation)
,
RT1
,
RS1
fOSCX(RT0-CS0 oscillation)
fOSCX(RS0-CS0 oscillation)
( x = 1, 2, 3 )
CS1
Kfx =
Frequency measurement (fOSCX)
VSS
CL
*1: Input logic circuit to determine the
specified measuring conditions.
32/37
FEDL610Q419-3
ML610Q419/ML610Q419C
Condition for VDD=1.25 to 3.6V
Parameter
Oscillation resistor
Oscillation frequency
VDD = 1.5V
RS to RT oscillation
*1
frequency ratio
VDD = 1.5V
Oscillation frequency
VDD = 3.0V
RS to RT oscillation
*1
frequency ratio
VDD = 3.0V
(VDD=1.25 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C,
Ta = -40 to +85°C for P version, unless otherwise specified)
Rating
Symbol
Condition
Unit
Min.
Typ.
Max.
RS0,RS1,RT0,
1
CS0, CT0, CS1≥740pF
kΩ
RT0-1,RT1
fOSC1
81.93
93.16
101.2
kHz
Resistor for oscillation=6kΩ
fOSC2
35.32
38.75
41.48
kHz
Resistor for oscillation=15kΩ
fOSC3
5.22
5.65
6.03
kHz
Resistor for oscillation=105kΩ
Kf1
2.139
2.381
2.632
RT0, RT0-1, RT1=1kΩ
⎯
Kf2
0.973
1
1.028
RT0, RT0-1, RT1=10kΩ
⎯
Kf3
0.142
0.147
0.152
RT0, RT0-1, RT1=100kΩ
⎯
fOSC1
85.28
94.58
103.3
kHz
Resistor for oscillation=6kΩ
fOSC2
35.72
38.87
41.78
kHz
Resistor for oscillation=15kΩ
fOSC3
5.189
5.622
6.012
kHz
Resistor for oscillation=105kΩ
Kf1
2.227
2.432
2.626
RT0, RT0-1, RT1=1kΩ
⎯
Kf2
0.982
1
1.018
RT0, RT0-1, RT1=10kΩ
⎯
Kf3
0.141
0.145
0.149
RT0, RT0-1, RT1=100kΩ
⎯
*1: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the
same conditions.
fOSCX(RT0-1-CS0 oscillation)
fOSCX(RS0-CS0 oscillation)
,
IN0 CS0 RCT0
VIH
,
fOSCX(RT1-CS1 oscillation)
fOSCX(RS1-CS1 oscillation)
RS0 RT0
RT1
RT0
RS0
RA0
RA1
CVR1
RT0-1 RA0-1
CT0
CS0
CVR0
RS1
fOSCX(RT0-CS0 oscillation)
fOSCX(RS0-CS0 oscillation)
( x = 1, 2, 3 )
CS1
Kfx =
RT0, RT0-1, RT1: 1k /10k
RA0, RA0-1, RA1: 5k
RS0, RS1: 15k
CS0, CT0, CS1: 560pF
CVR0, CVR1: 820pF
/100k
IN1 CS1 RS1 RT1
Frequency measurement (fOSCX)
Input pin
RCM
VIL
VDD
CV
VDDL
VSS
CL
*1: Input logic circuit to determine the
specified measuring conditions.
Note:
- Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors
and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1 and RS0/RS1. The coupling
capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise
around the node.
- When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to
the signal.
- Please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. Wiring to reserved
components may affect to the A/D conversion operation by noise the components itself may have.
33/37
FEDL610Q419-3
ML610Q419/ML610Q419C
Electrical Characteristics of Successive Approximation Type A/D Converter
(VDD = 1.8 to 3.6V, AVDD =2.2 to 3.6V, VSS = AVSS = 0V, Ta = -20 to +70°C,
Ta = -40 to +85°C for P version, unless otherwise specified)
Rating
Symbol
Condition
Unit
Min.
Typ.
Max.
n
⎯
⎯
⎯
12
bit
2.7V ≤ VREF ≤ 3.6V
−4
⎯
+4
IDL
2.2V ≤ VREF ≤ 2.7V
−6
⎯
+6
2.7V ≤ VREF ≤ 3.6V
−3
⎯
+3
LSB
DNL
2.2V ≤ VREF ≤ 2.7V
−5
⎯
+5
VOFF
⎯
−6
⎯
+6
FSE
⎯
−6
⎯
+6
VREF
⎯
2.2
⎯
AVDD
V
SACK = 0
⎯
25
⎯
(HSCLK = 375kHz to 625kHz)
φ/CH
tCONV
SACK = 1
⎯
112
⎯
(HSCLK = 1.5MHz to 4.2MHz)
Parameter
Resolution
Integral non-linearity error
Differential non-linearity error
Zero-scale error
Full-scale error
Reference voltage
Conversion time
φ: Period of high-speed clock (HSCLK)
AVDD
Reference
voltage
VDD
VDDL
VREF
1μF
1μF
A
0.1μF
−
1μF
RI≤5kΩ
+
Analog input
0.1μF
VDDX
AIN0,
AIN1,
AIN2,
AIN3
0.1μF
VSS
AVSS
34/37
FEDL610Q419-3
ML610Q419/ML610Q419C
Package Dimensions
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore,
before you perform reflow mounting, contact our responsible sales person for the product name, package name, pin number,
package code and desired mounting conditions (reflow method, temperature and times).
35/37
FEDL610Q419-3
ML610Q419/ML610Q419C
Revision History
Document No.
FEDL610Q419-1
FEDL610Q419-2
FEDL610Q419-3
Date
Dec.26.2011
Jan.11.2012
Jun.5.2012
Page
Previous Current
Edition
Edition
–
35
3
–
35
3
Description
Formally edition 1.0
Changed figure of package dimensions.
Changed part number of TQFP.
36/37
FEDL610Q419-3
ML610Q419/ML610Q419C
NOTES
No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co.,
Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter "Products"). If you
wish to use any such Product, please be sure to refer to the specifications, which can be obtained from LAPIS Semiconductor
upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and
operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any
damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall bear no responsibility for such
damage.
The technical information specified herein is intended only to show the typical functions of and examples of application circuits
for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual
property or other rights held by LAPIS Semiconductor and other parties. LAPIS Semiconductor shall bear no responsibility
whatsoever for any dispute arising from the use of such technical information.
The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio
visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a Product may fail or
malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical
injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and
fail-safe designs. LAPIS Semiconductor shall bear no responsibility whatsoever for your use of any Product outside of the
prescribed scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely
high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human
injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller
or other safety device). LAPIS Semiconductor shall bear no responsibility in any way for use of any of the Products for the
above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales
representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign
Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Copyright
2011 LAPIS Semiconductor Co., Ltd.
37/37
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement