Stratix IV

Stratix IV
Section II. I/O Interfaces
This section provides information on Stratix® IV device I/O features, external
memory interfaces, and high-speed differential interfaces with DPA. This section
includes the following chapters:
■
Chapter 6, I/O Features in Stratix IV Devices
■
Chapter 7, External Memory Interfaces in Stratix IV Devices
■
Chapter 8, High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Revision History
Refer to each chapter for its own specific revision history. For information on when
each chapter was updated, refer to the Chapter Revision Dates section, which appears
in the full handbook.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
II–2
Stratix IV Device Handbook Volume 1
Section II: I/O Interfaces
Revision History
February 2011
Altera Corporation
6. I/O Features in Stratix IV Devices
February 2011
SIV51006-3.2
SIV51006-3.2
This chapter describes how Stratix® IV devices provide I/O capabilities that allow
you to work in compliance with current and emerging I/O standards and
requirements. With these device features, you can reduce board design interface costs
and increase development flexibility.
Altera® Stratix IV FPGAs deliver a breakthrough level of system bandwidth and
power efficiency for high-end applications, allowing you to innovate without
compromise. Stratix IV I/Os are specifically designed for ease-of-use and rapid
system integration while simultaneously providing the high bandwidth required to
maximize internal logic capabilities and produce system-level performance.
Stratix IV device I/O capability far exceeds the I/O bandwidth available from
previous generation FPGAs. Independent modular I/O banks with a common bank
structure for vertical migration lend efficiency and flexibility to the high-speed I/O.
Package and die enhancements with dynamic termination and output control provide
best-in-class signal integrity. Numerous I/O features assist high-speed data transfer
into and out of the device, including:
■
Up to 32 full-duplex clock data recovery (CDR)-based transceivers supporting
data rates between 600 Mbps and 8.5 Gbps
■
Dedicated circuitry to support physical layer functionality for popular serial
protocols, such as PCI Express® (PIPE) (PCIe) Gen1 and Gen2, Gigabit Ethernet
(GbE), Serial RapidIO® , SONET/SDH, XAUI/HiGig, (OIF) CEI-6G,
SD/HD/3G-SDI, Fibre Channel, SFI-5, and Interlaken
■
Complete PCIe protocol solution with embedded PCIe hard IP blocks that
implement PHY-MAC layer, data link layer, and transaction layer functionality
■
Single-ended, non-voltage-referenced, and voltage-referenced I/O standards
■
Low-voltage differential signaling (LVDS), reduced swing differential signaling
(RSDS), mini-LVDS, high-speed transceiver logic (HSTL), and SSTL
■
Single data rate (SDR) and half data rate (HDR—half frequency and twice data
width of SDR) input and output options
■
Up to 132 full duplex 1.6 Gbps true LVDS channels (132 Tx + 132 Rx) on the row
I/O banks
■
Hard dynamic phase alignment (DPA) block with serializer/deserializer
(SERDES)
■
Deskew, read and write leveling, and clock-domain crossing functionality
■
Programmable output current strength
■
Programmable slew rate
■
Programmable delay
■
Programmable bus-hold circuit
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
Stratix IV Device Handbook Volume 1
February 2011
Subscribe
6–2
Chapter 6: I/O Features in Stratix IV Devices
I/O Standards Support
■
Programmable pull-up resistor
■
Open-drain output
■
Serial, parallel, and dynamic on-chip termination (OCT)
■
Differential OCT
■
Programmable pre-emphasis
■
Programmable equalization
■
Programmable differential output voltage (VOD )
This chapter contains the following sections:
■
“I/O Standards Support”
■
“I/O Banks” on page 6–5
■
“I/O Structure” on page 6–17
■
“On-Chip Termination Support and I/O Termination Schemes” on page 6–24
■
“OCT Calibration” on page 6–32
■
“Termination Schemes for I/O Standards” on page 6–38
■
“Design Considerations” on page 6–46
I/O Standards Support
Stratix IV devices support a wide range of industry I/O standards. Table 6–1 lists the
I/O standards Stratix IV devices support, as well as the typical applications. These
devices support V CCIO voltage levels of 3.0, 2.5, 1.8, 1.5, and 1.2 V.
Table 6–1. I/O Standards and Applications for Stratix IV Devices (Part 1 of 2)
I/O Standard
Application
3.3-V LVTTL/LVCMOS (1), (2)
General purpose
2.5-V LVCMOS
General purpose
1.8-V LVCMOS
General purpose
1.5-V LVCMOS
General purpose
1.2-V LVCMOS
General purpose
3.0-V PCI/PCI-X
PC and embedded system
SSTL-2 Class I and II
DDR SDRAM
SSTL-18 Class I and II
DDR2 SDRAM
SSTL-15 Class I and II
DDR3 SDRAM
HSTL-18 Class I and II
QDRII/RLDRAM II
HSTL-15 Class I and II
QDRII/QDRII+/RLDRAM II
HSTL-12 Class I and II
General purpose
Differential SSTL-2 Class I and II
DDR SDRAM
Differential SSTL-18 Class I and II
DDR2 SDRAM
Differential SSTL-15 Class I and II
DDR3 SDRAM
Differential HSTL-18 Class I and II
Clock interfaces
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Standards Support
6–3
Table 6–1. I/O Standards and Applications for Stratix IV Devices (Part 2 of 2)
I/O Standard
Application
Differential HSTL-15 Class I and II
Clock interfaces
Differential HSTL-12 Class I and II
Clock interfaces
LVDS
High-speed communications
RSDS
Flat panel display
mini-LVDS
Flat panel display
LVPECL
Video graphics and clock distribution
Notes to Table 6–1:
(1) The 3.3-V LVTTL/LVCMOS standard is supported using VCCIO at 3.0 V.
(2) For more information about the 3.3-V LVTTL/LVCMOS standard supported in Stratix IV devices, refer to “3.3-V I/O
Interface” on page 6–19.
f For more information about transceiver supported I/O standards, refer to the
Transceiver Architecture in Stratix IV Devices chapter.
I/O Standards and Voltage Levels
Stratix IV devices support a wide range of industry I/O standards, including
single-ended, voltage-referenced single-ended, and differential I/O standards.
Table 6–2 lists the supported I/O standards and typical values for input and output
VCCIO , VCCPD , VREF, and board VTT.
Table 6–2. I/O Standards and Voltage Levels for Stratix IV Devices (Note 1) (Part 1 of 3)
VCCIO (V)
I/O Standard
Standard
Support
Input Operation
Column
Row
I/O Banks I/O Banks
Output Operation
Column
I/O Banks
Row
I/O Banks
VTT (V)
VREF (V)
VCCPD (V)
(Board
(Pre-Driver (Input Ref
Termination
Voltage)
Voltage)
Voltage)
3.3-V LVTTL
JESD8-B
3.0/2.5
3.0/2.5
3.0
3.0
3.0
—
—
3.3-V LVCMOS (3)
JESD8-B
3.0/2.5
3.0/2.5
3.0
3.0
3.0
—
—
2.5-V LVCMOS
JESD8-5
3.0/2.5
3.0/2.5
2.5
2.5
2.5
—
—
1.8-V LVCMOS
JESD8-7
1.8/1.5
1.8/1.5
1.8
1.8
2.5
—
—
1.5-V LVCMOS
JESD8-11
1.8/1.5
1.8/1.5
1.5
1.5
2.5
—
—
1.2-V LVCMOS
JESD8-12
1.2
1.2
1.2
1.2
2.5
—
—
3.0-V PCI
PCI
Rev 2.1
3.0
3.0
3.0
3.0
3.0
—
—
3.0-V PCI-X
PCI-X
Rev 1.0
3.0
3.0
3.0
3.0
3.0
—
—
SSTL-2 Class I
JESD8-9B
(2)
(2)
2.5
2.5
2.5
1.25
1.25
SSTL-2 Class II
JESD8-9B
(2)
(2)
2.5
2.5
2.5
1.25
1.25
SSTL-18 Class I
JESD8-15
(2)
(2)
1.8
1.8
2.5
0.90
0.90
SSTL-18 Class II
JESD8-15
(2)
(2)
1.8
1.8
2.5
0.90
0.90
SSTL-15 Class I
—
(2)
(2)
1.5
1.5
2.5
0.75
0.75
SSTL-15 Class II
—
(2)
(2)
1.5
—
2.5
0.75
0.75
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
6–4
Chapter 6: I/O Features in Stratix IV Devices
I/O Standards Support
Table 6–2. I/O Standards and Voltage Levels for Stratix IV Devices (Note 1) (Part 2 of 3)
VCCIO (V)
I/O Standard
Standard
Support
Input Operation
Column
Row
I/O Banks I/O Banks
Output Operation
Column
I/O Banks
Row
I/O Banks
VTT (V)
VREF (V)
VCCPD (V)
(Board
(Pre-Driver (Input Ref
Termination
Voltage)
Voltage)
Voltage)
HSTL-18 Class I
JESD8-6
(2)
(2)
1.8
1.8
2.5
0.90
0.90
HSTL-18 Class II
JESD8-6
(2)
(2)
1.8
1.8
2.5
0.90
0.90
HSTL-15 Class I
JESD8-6
(2)
(2)
1.5
1.5
2.5
0.75
0.75
HSTL-15 Class II
JESD8-6
(2)
(2)
1.5
—
2.5
0.75
0.75
HSTL-12 Class I
JESD8-16A
(2)
(2)
1.2
1.2
2.5
0.6
0.6
HSTL-12 Class II
JESD8-16A
(2)
(2)
1.2
—
2.5
0.6
0.6
Differential SSTL-2
Class I
JESD8-9B
(2)
(2)
2.5
2.5
2.5
—
1.25
Differential SSTL-2
Class II
JESD8-9B
(2)
(2)
2.5
2.5
2.5
—
1.25
Differential
SSTL-18 Class I
JESD8-15
(2)
(2)
1.8
1.8
2.5
—
0.90
Differential
SSTL-18 Class II
JESD8-15
(2)
(2)
1.8
1.8
2.5
—
0.90
Differential
SSTL-15 Class I
—
(2)
(2)
1.5
1.5
2.5
—
0.75
Differential
SSTL-15 Class II
—
(2)
(2)
1.5
—
2.5
—
0.75
Differential
HSTL-18 Class I
JESD8-6
(2)
(2)
1.8
1.8
2.5
—
0.90
Differential
HSTL-18 Class II
JESD8-6
(2)
(2)
1.8
1.8
2.5
—
0.90
Differential
HSTL-15 Class I
JESD8-6
(2)
(2)
1.5
1.5
2.5
—
0.75
Differential
HSTL-15 Class II
JESD8-6
(2)
(2)
1.5
—
2.5
—
0.75
Differential
HSTL-12 Class I
JESD8-16A
(2)
(2)
1.2
1.2
2.5
—
0.60
Differential
HSTL-12 Class II
JESD8-16A
(2)
(2)
1.2
—
2.5
—
0.60
ANSI/TIA/
EIA-644
(2)
(2)
2.5
2.5
2.5
—
—
RSDS (6), (7),
(8)
—
(2)
(2)
2.5
2.5
2.5
—
—
mini-LVDS (6),
(7), (8)
—
(2)
(2)
2.5
2.5
2.5
—
—
LVDS (4), (5), (8)
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
6–5
Table 6–2. I/O Standards and Voltage Levels for Stratix IV Devices (Note 1) (Part 3 of 3)
VCCIO (V)
I/O Standard
Standard
Support
Input Operation
Column
Row
I/O Banks I/O Banks
LVPECL
—
(4)
2.5
Output Operation
Column
I/O Banks
Row
I/O Banks
—
—
VTT (V)
VREF (V)
VCCPD (V)
(Board
(Pre-Driver (Input Ref
Termination
Voltage)
Voltage)
Voltage)
2.5
—
—
Notes to Table 6–2:
(1) VCCPD is either 2.5 or 3.0 V. For V CCIO = 3.0 V, VCCPD = 3.0 V. For V CCIO = 2.5 V or less, VCCPD = 2.5 V.
(2) Single-ended HSTL/SSTL, differential SSTL/HSTL, and LVDS input buffers are powered by VCCPD. Row I/O banks support both true differential
input buffers and true differential output buffers. Column I/O banks support true differential input buffers, but not true differential output buffers.
I/O pins are organized in pairs to support differential standards. Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers
without on-chip RD support.
(3) For more information about the 3.3-V LVTTL/LVCMOS standard supported in Stratix IV devices, refer to “3.3-V I/O Interface” on page 6–19.
(4) Column I/O banks support LVPECL I/O standards for input clock operation. Clock inputs on column I/Os are powered by VCCCLKIN when configured
as differential clock inputs. They are powered by V CCIO when configured as single-ended clock inputs. Differential clock inputs in row I/Os are
powered by VCCPD.
(5) Column and row I/O banks support LVDS outputs using two single-ended output buffers, an external one-resistor (LVDS_E_1R), and a
three-resistor (LVDS_E_3R) network.
(6) Row I/O banks support RSDS and mini-LVDS I/O standards using a true LVDS output buffer without a resistor network.
(7) Column and row I/O banks support RSDS and mini-LVDS I/O standards using two single-ended output buffers with one-resistor (RSDS_E_1R
and mini-LVDS_E_1R) and three-resistor (RSDS_E_3R and mini-LVDS_E_3R) networks.
(8) The emulated differential output standard that supports the tri-state feature includes: LVDS_E_1R, LVDS_E_3R, RSDS_E_1R, RSDS_E_3R,
Mini_LVDS_E_1R, and Mini_LVDS_E_3R. For more information, refer to the I/O Buffer (ALTIOBUF) Megafunction User Guide.
f For more information about electrical characteristics of each I/O standard, refer to the
DC and Switching Characteristics for Stratix IV Devices chapter.
I/O Banks
Stratix IV devices contain up to 24 I/O banks, as shown in Figure 6–1 and Figure 6–2.
The row I/O banks contain true differential input and output buffers and dedicated
circuitry to support differential standards at speeds up to 1.6 Gbps.
Each I/O bank in Stratix IV devices can support high-performance external memory
interfaces with dedicated circuitry. The I/O pins are organized in pairs to support
differential standards. Each I/O pin pair can support both differential input and
output buffers. The only exceptions are the clk[1,3,8,10], PLL_L[1,4]_clk, and
PLL_R[1,4]_clk pins, which support differential input operations only.
f For the number of channels available for the LVDS I/O standard, refer to the
High-Speed Differential I/O Interface and DPA in Stratix IV Devices chapter. For more
information about transceiver-bank-related features, refer to the Transceiver
Architecture in Stratix IV Devices chapter.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
6–6
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
Figure 6–1. Stratix IV E Devices I/0 Banks (Note 1), (2), (3), (4), (5), (6), (7), (8)
Bank 8B
Bank 8C
Bank 7A
I/O banks 7A, 7B, and 7C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
Bank 1B
Bank 6B
I/O banks 8A, 8B, and 8C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
Bank 7B
Bank 7C
Bank 6A
Bank 1A
Bank 8A
Bank 6C
Bank 1C
Row I/O banks support LVTTL, LVCMOS, 2.5-V, 1.8-V,
1.5-V, 1.2-V, SSTL-2 Class I & II, SSTL-18 Class I & II,
SSTL-15 Class I, HSTL-18 Class I & II, HSTL-15 Class I,
HSTL-12 Class I, LVDS, RSDS, mini-LVDS, differential
SSTL-2 Class I & II, differential SSTL-18 Class I & II,
differential SSTL-15 Class I, differential HSTL-18 Class I &
II, differential HSTL-15 Class I, and differential HSTL-12
Class I standards for input and output operations.
Bank 5C
Bank 2C
LVPECL I/O standard for input operation on dedicated
clock input pins.
Bank 2A
Bank 3A
Bank 3B
Bank 3C
Bank 5B
I/O banks 4A, 4B, and 4C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
I/O banks 3A, 3B, and 3C support all
single-ended and differential input
and output operations except LVPECL,
which is supported on clk input pins only.
Bank 4C
Bank 4B
Bank 5A
Bank 2B
SSTL-15 Class II, HSTL-15 Class II, HSTL-12 Class II,
differential SSTL-15 Class II, differential HSTL-15
Class II, differential HSTL-12 Class II standards are
only supported for input operations.
Bank 4A
Notes to Figure 6–1:
(1) Differential HSTL and SSTL outputs are not true differential outputs. They use two single-ended outputs with the second output programmed as
inverted.
(2) Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers without differential OCT support.
(3) Column I/O supports LVDS outputs using single-ended buffers and external resistor networks.
(4) Column I/O supports PCI/PCI-X with on-chip clamp diode. Row I/O supports PCI/PCI-X with external clamp diode.
(5) Clock inputs on column I/Os are powered by VCCCLKIN when configured as differential clock inputs. They are powered by VCCIO when configured as
single-ended clock inputs. All outputs use the corresponding bank VCCIO.
(6) Row I/O supports the true LVDS output buffer.
(7) Column and row I/O banks support LVPECL standards for input clock operation.
(8) Figure 6–1 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
6–7
Figure 6–2. Stratix IV GX Devices I/O Banks (Note 1), (2), (3), (4), (5), (6), (7), (8)
Bank 3A
Bank 3B
Bank 3C
Bank 4C
Bank 4B
Transceiver Bank
GXBR3
Transceiver Bank
GXBR2
Transceiver Bank
GXBR1
Bank 6C
Bank5C
I/O banks 4A, 4B & 4C support all
single-ended and differential input
and output operation.
I/O banks 3A, 3B & 3C support all
single-ended and differential input
and output operation.
Bank 5A
Bank 2B
Bank 5B
Bank 2C
Bank 1C
Row I/O banks support LVTTL, LVCMOS, 2.5-V, 1.8V, 1.5-V, 1.2-V, SSTL-2 Class I & II, SSTL-18 Class I
& II, SSTL-15 Class I, HSTL-18 Class I & II, HSTL-15
Class I, HSTL-12 Class I, LVDS, RSDS, mini-LVDS,
differential SSTL-2 Class I & II, differential SSTL-18
Class I & II, differential SSTL-15 Class I, differential
HSTL-18 Class I & II, differential HSTL-15 Class I and
differential HSTL-12 Class I standards for input and
output operation.
SSTL-15 class II, HSTL-15 Class II, HSTL-12 Class II,
differential SSTL-15 Class II, differential HSTL-15
Class II, differential HSTL-12 Class II standards are
only supported for input operations
Transceiver Bank
GXBR0
Bank 6B
Bank 1B
I/O banks 7A, 7B & 7C support all
single-ended and differential input
and output operation.
Bank 6A
Bank 1A
Bank 7A
Bank 7B
Bank 7C
I/O banks 8A, 8B & 8C support all
single-ended and differential input
and output operation.
Bank 2A
Transceiver Bank
GXBL3
Transceiver Bank
GXBL2
Transceiver Bank
GXBL1
Transceiver Bank
GXBL0
Bank 8C
Bank 8B
Bank 8A
Bank 4A
Notes to Figure 6–2:
(1) Differential HSTL and SSTL outputs are not true differential outputs. They use two single-ended outputs with the second output programmed as
inverted.
(2) Column I/O differential HSTL and SSTL inputs use LVDS differential input buffers without differential OCT support.
(3) Column I/O supports LVDS outputs using single-ended buffers and external resistor networks.
(4) Column I/O supports PCI/PCI-X with an on-chip clamp diode. Row I/O supports PCI/PCI-X with an external clamp diode.
(5) Clock inputs on column I/Os are powered by VCCCLKIN when configured as differential clock inputs. They are powered by VCCIO when configured as
single-ended clock inputs. All outputs use the corresponding bank VCCIO.
(6) Row I/O supports the true LVDS output buffer.
(7) Column and row I/O banks support LVPECL standards for input clock operation.
(8) Figure 6–2 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
6–8
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
Modular I/O Banks
The I/O pins in Stratix IV devices are arranged in groups called modular I/O banks.
Depending on device densities, the number of Stratix IV device I/O banks range from
16 to 24. The number of I/O pins on each bank is 24, 32, 36, 40, or 48. Figure 6–4
through Figure 6–16 show the number of I/O pins available in each I/O bank.
In Stratix IV devices, the maximum number of I/O banks per side is either four or six,
depending on the device density. When migrating between devices with a different
number of I/O banks per side, it is the middle or “B” bank that is removed or
inserted. For example, when moving from a 24-bank device to a 16-bank device, the
banks that are dropped are “B” banks, namely: 1B, 2B, 3B, 4B, 5B, 6B, 7B, and 8B.
Similarly, when moving from a 16-bank device to a 24-bank device, the banks that are
added are the same “B” banks.
After migration from a smaller device to a larger device, the bank size increases or
remains the same, but never decreases. For example, the number of I/O pins to a bank
may increase from 24 to 26, 32, 36, 40, 42, or 48, but will never decrease. This is shown
in Figure 6–3.
Figure 6–3. Bank Migration Path with Increasing Device Size
24
Stratix IV Device Handbook Volume 1
26
32
36
40
42
48
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
6–9
Figure 6–4 through Figure 6–16 show the number of I/O pins and packaging
information for different sets of available devices. They show the top view of the
silicon die that corresponds to a reverse view for flip chip packages. They are
graphical representations only.
1
For Figure 6–4 through Figure 6–16, the pin count includes all general purpose I/Os,
dedicated clock pins, and dual purpose configuration pins. Transceiver pins and
dedicated configuration pins are not included in the pin count.
40
Bank 2C
Bank 5C
26
Bank 2A
Bank 5A
32
40
Bank 4A
Bank
Name
Number
of I/Os
40
32
Bank 7A
26
Bank 4C
26
24
Bank 6C
EP4SE230
EP4SE360
24
Bank 1C
Bank 7C
32
Bank 3C
26
24
Bank 6A
24
Bank 1A
Bank 3A
32
Bank 8C
Bank
Name
40
Number
of I/Os
Bank 8A
Figure 6–4. Number of I/Os in Each Bank in EP4SE230 and EP4SE360 Devices in the 780-Pin FineLine BGA Package
24
32
32
24
40
Bank 8B
Bank 8C
Bank 7C
Bank 7B
Altera Corporation
Bank 7A
Bank 4A
40
40
February 2011
Bank 4B
Bank 2A
24
48
Bank 4C
Bank 2C
32
42
EP4SE360
EP4SE530
EP4SE820
Bank 3C
Bank 1C
32
42
Bank 3B
Bank 1A
Bank 3A
48
24
Bank
Name
40
Number
of I/Os
Bank 8A
Figure 6–5. Number of I/Os in Each Bank in EP4SE360, EP4SE530, and EP4SE820 Devices in the 1152-Pin FineLine BGA
Package
Bank 6A
48
Bank 6C
42
Bank 5C
42
Bank 5A
48
Bank
Name
Number
of I/Os
Stratix IV Device Handbook Volume 1
6–10
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
48
32
32
48
48
Bank 8B
Bank 8C
Bank 7C
Bank 7B
Bank 7A
Bank
Name
48
Number
of I/Os
Bank 8A
Figure 6–6. Number of I/Os in Each Bank in EP4SE530 and EP4SE820 Devices in the 1517-Pin FineLine BGA Package
50
Bank 1A
Bank 6A
50
24
Bank 1B
Bank 6B
24
42
Bank 1C
Bank 6C
42
42
Bank 2C
Bank 5C
42
24
Bank 2B
Bank 5B
24
50
Bank 2A
Bank 5A
50
48 Bank 4A
48 Bank 4B
32 Bank 4C
32 Bank 3C
48 Bank 3B
48 Bank 3A
EP4SE530
EP4SE820
Bank
Name
Number
of I/Os
48
48
48
48
48
Bank 8B
Bank 8C
Bank 7C
Bank 7B
Bank 7A
Bank
Name
48
Number
of I/Os
Bank 8A
Figure 6–7. Number of I/Os in Each Bank in EP4SE530 and EP4SE820 Devices in the 1760-Pin Fineline BGA Package
50
Bank 1A
Bank 6A
50
36
Bank 1B
Bank 6B
36
50
Bank 1C
Bank 6C
50
50
Bank 2C
Bank 5C
50
36
Bank 2B
Bank 5B
36
50
Bank 2A
Bank 5A
50
Stratix IV Device Handbook Volume 1
48 Bank 4A
48 Bank 4B
48 Bank 4C
48 Bank 3C
48 Bank 3B
48 Bank 3A
EP4SE530
EP4SE820
Bank
Name
Number
of I/Os
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
6–11
40
Bank
GXBR1
Bank 2A
24
24
40
Bank 7C
Bank 7A
Number of
Transceiver
Channels
4
Bank
GXBR0
32
Bank 4A
Bank 2C
40
26
EP4SGX70
EP4SGX110
EP4SGX180
EP4SGX230
Bank 4C
Bank 1C
24
26
Bank 3C
Bank 1A
Bank 3A
32
24
Bank
Name
Bank 8A
40
Number
of I/Os
Bank 8C
Figure 6–8. Number of I/Os in Each Bank in EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230 Devices in the 780-Pin
FineLine BGA Package
4
Bank
Name
Number
of I/Os
Altera Corporation
32
40
Bank 7C
Bank 7A
Bank 4C
Bank 4A
32
40
Bank
GXBL0
Bank 3C
4
Number of
Transceiver
Channels
Bank
GXBR1
4
Bank
GXBR0
4
EP4SGX290
EP4SGX360
32
Bank
GXBL1
Bank 3A
4
Number of
Transceiver
Channels
February 2011
32
Bank
1C
40
1
Bank 8C
Bank
Name
40
Number
of I/Os
Bank 8A
Figure 6–9. Number of I/Os in Each Bank in EP4SGX290 and EP4SGX360 Devices in the 780-Pin FineLine BGA Package
Bank
Name
Number
of I/Os
Stratix IV Device Handbook Volume 1
6–12
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
Bank
GXBL0
24
24
40
Bank 7C
Bank 7A
40
*Number of
Transceiver
Channels
Bank 4A
4*
Bank 6A
32
Bank 6C
26
Bank
GXBR1
4*
Bank
GXBR0
4*
Bank
Name
Number
of I/Os
40
Bank
GXBL1
Bank 4C
4*
EP4SGX70
EP4SGX110
24
Bank 1C
Bank 3C
26
24
Bank 1A
Bank 3A
32
Bank 8C
Bank
Name
40
Number
of I/Os
Bank 8A
Figure 6–10. Number of I/Os in Each Bank in EP4SGX70 and EP4SGX110 Devices in the 1152-Pin FineLine BGA Package
32
32
24
40
Bank 8C
Bank 7C
Bank 7B
Bank 7A
24
Bank 8B
Bank 4B
Bank 4A
40
40
24
Bank
GXBL0
Bank 4C
4 (2)
32
4 (2)
Bank
GXBL1
Bank 3C
Bank 1C
32
42
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530
Bank 3B
Bank 1A
Bank 3A
48
24
Bank
Name
40
Number
of I/Os
Bank 8A
Figure 6–11. Number of I/Os in Each Bank in EP4SGX180, EP4SGX230, EP4SGX290, EP4SGX360, and EP4SGX530 Devices
in the 1152-Pin FineLine BGA Package (Note 1), (2)
Bank 6A
48
Bank 6C
42
Bank
GXBR1
4 (2)
Bank
GXBR0
4 (2)
Bank
Name
Number
of I/Os
Notes to Figure 6–11:
(1) Except for the EP4SGX530 device, all listed devices have two variants in the F1152 package option—one with no PMA-only transceiver channels
and the other with two PMA-only transceiver channels for each transceiver bank. The EP4SGX530 device is only offered with two PMA-only
transceiver channels for each transceiver bank in the F1152 package option.
(2) There are two additional PMA-only transceiver channels in each transceiver bank for devices with the PMA-only transceiver package option.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
6–13
24
32
32
24
40
Bank 8B
Bank 8C
Bank 7C
Bank 7B
Bank 7A
Bank
Name
40
Number
of I/Os
Bank 8A
Figure 6–12. Number of I/Os in Each Bank in EP4SGX180, EP4SGX230, EP4SGX290, EP4SGX360, and EP4SGX530 Devices
in the 1517-Pin FineLine BGA Package (Note 1)
48
Bank 1A
Bank 6A
48
42
Bank 1C
Bank 6C
42
42
Bank 2C
Bank 5C
42
48
Bank 2A
Bank 5A
48
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530
Bank
GXBR1
4 (1)
4 (1)
Bank
GXBL0
Bank
GXBR0
4 (1)
40
24
32
32
24
40
Bank 4A
Bank
GXBL1
Bank 4B
4 (1)
Bank 4C
4 (1)
Bank 3C
Bank
GXBR2
Bank 3B
Bank
GXBL2
Bank 3A
4 (1)
Bank
Name
Number
of I/Os
Note to Figure 6–12:
(1) There are two additional PMA-only transceiver channels in each transceiver bank.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
6–14
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
48
32
32
48
48
Bank 8B
Bank 8C
Bank 7C
Bank 7B
Bank 7A
Bank
Name
48
Number
of I/Os
Bank 8A
Figure 6–13. Number of I/Os in Each Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1932-Pin FineLine
BGA Package (Note 1)
50
Bank 1A
Bank 6A
50
42
Bank 1C
Bank 6C
42
42
Bank 2C
Bank 5C
42
20
Bank 2B
Bank 5B
20
50
Bank 2A
Bank 5A
50
4 (1)
Bank
GXBL3
Bank
GXBR3
4 (1)
4 (1)
Bank
GXBL2
Bank
GXBR2
4 (1)
4 (1)
Bank
GXBL1
4 (1)
4 (1)
Bank
GXBL0
Bank
GXBR1
Bank
GXBR0
48 Bank 4A
48 Bank 4B
32 Bank 4C
32 Bank 3C
48 Bank 3B
48 Bank 3A
EP4SGX530
EP4SGX290
EP4SGX360
4 (1)
Bank
Name
Number
of I/Os
Note to Figure 6–13:
(1) There are two additional PMA-only transceiver channels in each transceiver bank.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
6–15
48
32
32
48
48
Bank 8B
Bank 8C
Bank 7C
Bank 7B
Bank 7A
Bank
Name
48
Number
of I/Os
Bank 8A
Figure 6–14. Number of I/Os in Each Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1760-Pin FineLine
BGA Package (Note 1)
50
Bank 1A
Bank 6A
50
42
Bank 1C
Bank 6C
42
42
Bank 2C
Bank 5C
42
Bank 5A
50
50
EP4SGX290
EP4SGX360
EP4SGX530
Bank 2A
Bank
GXBR1
4 (1)
4 (1)
Bank
GXBL0
Bank
GXBR0
4 (1)
48
48
32
32
48
48
Bank 4A
Bank
GXBL1
Bank 4B
4 (1)
Bank 4C
4 (1)
Bank 3C
Bank
GXBR2
Bank 3B
Bank
GXBL2
Bank 3A
4 (1)
Bank
Name
Number
of I/Os
Note to Figure 6–14:
(1) There are two additional PMA-only transceiver channels in each transceiver bank.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
6–16
Chapter 6: I/O Features in Stratix IV Devices
I/O Banks
1
The information in Figure 6–15 and Figure 6–16 applies to Stratix IV GX and GT
devices.
48
32
32
48
48
Bank 8B
Bank 8C
Bank 7C
Bank 7B
Bank 7A
Bank
Name
48
Number
of I/Os
Bank 8A
Figure 6–15. Number of I/Os in Each Bank in EP4S100G3, EP4S100G4, and EP4S100G5 Devices in the 1932-Pin FineLine
BGA Package (Note 1)
40
Bank 1A
Bank 6A
38
21
Bank 1C
Bank 6C
22
21
Bank 2C
Bank 5C
19
13
Bank 2B
Bank 5B
12
41
Bank 2A
Bank 5A
42
4 (1)
Bank
GXBL2
Bank
GXBR2
4 (1)
4 (1)
Bank
GXBL1
Bank
GXBR1
4 (1)
4 (1)
Bank
GXBL0
Bank
GXBR0
4 (1)
Bank 4A
48
Bank 4B
48
Bank 4C
32
Bank 3C
32
Bank 3B
48
48
Bank 3A
EP4S100G3
EP4S100G4
EP4S100G5
Bank
Name
Number
of I/Os
Note to Figure 6–15:
(1) There are two additional PMA-only transceiver channels in each transceiver bank.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
6–17
24
32
32
24
40
Bank 8B
Bank 8C
Bank 7C
Bank 7B
Bank 7A
Bank
Name
40
Number
of I/Os
Bank 8A
Figure 6–16. Number of I/Os in Each Bank in EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices in the 1517-Pin
FineLine BGA Package (Note 1)
43
Bank 1A
Bank 6A
44
22
Bank 1C
Bank 6C
23
23
Bank 2C
Bank 5C
23
46
Bank 2A
Bank 5A
46
EP4S40G2
EP4S40G5
EP4S100G2
EP4S100G5
Bank
GXBR1
4 (1)
4 (1)
Bank
GXBL0
Bank
GXBR0
4 (1)
40
24
32
32
24
40
Bank 4A
Bank
GXBL1
Bank 4B
4 (1)
Bank 4C
4 (1)
Bank 3C
Bank
GXBR2
Bank 3B
Bank
GXBL2
Bank 3A
4 (1)
Bank
Name
Number
of I/Os
Note to Figure 6–16:
(1) There are two additional PMA-only transceiver channels in each transceiver bank.
I/O Structure
The I/O element (IOE) in Stratix IV devices contain a bidirectional I/O buffer and I/O
registers to support a complete embedded bidirectional single data rate or DDR
transfer. The IOEs are located in I/O blocks around the periphery of the Stratix IV
device. There are up to four IOEs per row I/O block and four IOEs per column I/O
block. The row IOEs drive row, column, or direct link interconnects. The column IOEs
drive column interconnects.
The Stratix IV bidirectional IOE also supports the following features:
February 2011
■
Programmable input delay
■
Programmable output-current strength
■
Programmable slew rate
■
Programmable output delay
■
Programmable bus-hold
■
Programmable pull-up resistor
■
Open-drain output
■
On-chip series termination with calibration
Altera Corporation
Stratix IV Device Handbook Volume 1
6–18
Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
■
On-chip series termination without calibration
■
On-chip parallel termination with calibration
■
On-chip differential termination
■
PCI clamping diode
I/O registers are composed of the input path for handling data from the pin to the
core, the output path for handling data from the core to the pin, and the output-enable
(OE) path for handling the OE signal to the output buffer. These registers allow faster
source-synchronous register-to-register transfers and resynchronization. The input
path consists of the DDR input registers, alignment and synchronization registers,
and HDR. You can bypass each block of the input path.
The output and OE paths are divided into output or OE registers, alignment registers,
and HDR blocks. You can bypass each block of the output and OE paths.
Figure 6–17 shows the Stratix IV IOE structure.
Figure 6–17. IOE Structure in Stratix IV Devices (Note 1), (2), (3)
Firm Core
DQS Logic Block
OE Register
D
OE
from
Core
2
Half Data
Rate Block
D6_OCT
D5_OCT
PRN
Q
Dynamic OCT Control (2)
Alignment
Registers
OE Register
D
VCCIO
D5, D6
Delay
PRN
Q
VCCIO
PCI Clamp
Programmable
Pull-Up Resistor
Programmable
Current
Strength and
Slew Rate
Control
Output Register
Write
Data
from
Core
Half Data
Rate Block
4
Alignment
Registers
PRN
D
Q
From OCT
Calibration
Block
Output Buffer
D5, D6
Delay
On-Chip
Termination
Output Register
D
Open Drain
PRN
Q
D2 Delay
Input Buffer
D3_0
Delay
clkout
To
Core
D3_1
Delay
To
Core
Read
Data
to
Core
4
Half Data
Rate Block
Alignment and
Synchronization
Registers
D1
Delay
Bus-Hold
Circuit
Input Register
PRN
D
Q
Input Register
Input Register
PRN
D
DQS
CQn
PRN
Q
D
Q
D4 Delay
clkin
Notes to Figure 6–17:
(1) The D3_0 and D3_1 delays have the same available settings in the Quartus® II software.
(2) One dynamic OCT control is available per DQ/DQS group.
(3) Column I/O supports PCI/PCI-X with an on-chip clamp diode. Row I/O supports PCI/PCI-X with an external clamp diode.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
6–19
f For more information about I/O registers and how they are used for memory
applications, refer to the External Memory Interfaces in Stratix IV Devices chapter.
3.3-V I/O Interface
Stratix IV I/O buffers support 3.3-V I/O standards. You can use them as transmitters
or receivers in your system. The output high voltage (VOH), output low voltage (V OL ),
input high voltage (VIH), and input low voltage (VIL) levels meet the 3.3-V I/O
standards specifications defined by EIA/JEDEC Standard JESD8-B with margin when
the Stratix IV VCCIO voltage is powered by 3.0 V.
To ensure device reliability and proper operation, when interfacing with a 3.3-V I/O
system using Stratix IV devices, ensure that you do not violate the absolute maximum
ratings of the devices. Altera recommends performing IBIS simulation to determine
that the overshoot and undershoot voltages are within the guidelines.
When using the Stratix IV device as a transmitter, you can use slow slew rate and
series termination to limit overshoot and undershoot at the I/O pins, but they are not
required. Transmission line effects that cause large voltage deviations at the receiver
are associated with an impedance mismatch between the driver and the transmission
lines. By matching the impedance of the driver to the characteristic impedance of the
transmission line, you can significantly reduce overshoot voltage. You can use a series
termination resistor placed physically close to the driver to match the total driver
impedance to the transmission line impedance. Stratix IV devices support series OCT
for all LVTTL and LVCMOS I/O standards in all I/O banks.
When using the Stratix IV device as a receiver, you can use a clamping diode (on-chip
or off-chip) to limit overshoot, though this is not required. Stratix IV devices provide
an optional on-chip PCI-clamping diode for column I/O pins. You can use this diode
to protect the I/O pins against overshoot voltage.
The 3.3-V I/O standard is supported using bank supply voltage (VCCIO ) at 3.0 V. In
this method, the clamping diode (on-chip or off-chip), when enabled, can sufficiently
clamp overshoot voltage to within the DC and AC input voltage specifications. The
clamped voltage can be expressed as the sum of the supply voltage (V CCIO) and the
diode forward voltage.
f For more information about the absolute maximum rating and maximum allowed
overshoot during transitions, refer to the DC and Switching Characteristics for Stratix IV
Devices chapter.
External Memory Interfaces
In addition to the I/O registers in each IOE, Stratix IV devices also have dedicated
registers and phase-shift circuitry on all I/O banks for interfacing with external
memory interfaces.
f For more information about external memory interfaces, refer to the External Memory
Interfaces in Stratix IV Devices chapter.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
6–20
Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
High-Speed Differential I/O with DPA Support
Stratix IV devices have the following dedicated circuitry for high-speed differential
I/O support:
■
Differential I/O buffer
■
Transmitter serializer
■
Receiver deserializer
■
Data realignment
■
Dynamic phase aligner (DPA)
■
Synchronizer (FIFO buffer)
■
Phase-locked loops (PLLs)
f For more information about DPA support, refer to the High-Speed Differential I/O
Interfaces and DPA in Stratix IV Devices chapter.
Programmable Current Strength
The output buffer for each Stratix IV device I/O pin has a programmable current
strength control for certain I/O standards. Use programmable current strength to
mitigate the effects of high signal attenuation due to a long transmission line or a
legacy backplane. The LVTTL, LVCMOS, SSTL, and HSTL standards have several
levels of current strength that you can control. Table 6–3 lists the programmable
current strength for Stratix IV devices.
Table 6–3. Programmable Current Strength (Part 1 of 2) (Note 1), (2)
IOH / I OL Current Strength
Setting (mA) for
Column I/O Pins
IOH / IOL Current Strength
Setting (mA) for
Row I/O Pins
3.3-V LVTTL
16, 12, 8, 4
12, 8, 4
3.3-V LVCMOS
16, 12, 8, 4
8, 4
I/O Standard
2.5-V LVCMOS
16, 12, 8, 4
12, 8, 4
1.8-V LVCMOS
12, 10, 8, 6, 4, 2
8, 6, 4, 2
1.5-V LVCMOS
12, 10, 8, 6, 4, 2
8, 6, 4, 2
1.2-V LVCMOS
8, 6, 4, 2
4, 2
SSTL-2 Class I
12, 10, 8
12, 8
SSTL-2 Class II
16
16
SSTL-18 Class I
12, 10, 8, 6, 4
12, 10, 8, 6, 4
SSTL-18 Class II
16, 8
16, 8
SSTL-15 Class I
12, 10, 8, 6, 4
8, 6, 4
SSTL-15 Class II
16, 8
—
HSTL-18 Class I
12, 10, 8, 6, 4
12, 10, 8, 6, 4
HSTL-18 Class II
16
16
HSTL-15 Class I
12, 10, 8, 6, 4
8, 6, 4
HSTL-15 Class II
16
—
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
6–21
Table 6–3. Programmable Current Strength (Part 2 of 2) (Note 1), (2)
IOH / I OL Current Strength
Setting (mA) for
Column I/O Pins
IOH / IOL Current Strength
Setting (mA) for
Row I/O Pins
HSTL-12 Class I
12, 10, 8, 6, 4
8, 6, 4
HSTL-12 Class II
16
—
I/O Standard
Notes to Table 6–3:
(1) The default setting in the Quartus II software is 50- Ω OCT RS without calibration for all non-voltage reference and
HSTL and SSTL Class I I/O standards. The default setting is 25-Ω OCT RS without calibration for HSTL and SSTL
Class II I/O standards.
(2) The 3.3-V LVTTL and 3.3-V LVCMOS are supported using VCCIO and VCCPD at 3.0 V.
1
Altera recommends performing IBIS or SPICE simulations to determine the best
current strength setting for your specific application.
Programmable Slew Rate Control
The output buffer for each Stratix IV device regular- and dual-function I/O pin has a
programmable output slew-rate control that you can configure for low-noise or
high-speed performance. A faster slew rate provides high-speed transitions for
high-performance systems. A slower slew rate can help reduce system noise, but adds
a nominal delay to the rising and falling edges. Each I/O pin has an individual
slew-rate control, allowing you to specify the slew rate on a pin-by-pin basis.
1
You cannot use the programmable slew rate feature when using OCT RS.
The Quartus II software allows four settings for programmable slew rate control—0,
1, 2, and 3—where 0 is slow slew rate and 3 is fast slew rate. Figure 6–4 lists the
default slew rate settings from the Quartus II software.
Table 6–4. Default Slew Rate Settings
I/O Standard
Slew Rate Option
Default Slew Rate
1.2-V, 1.5-V, 1.8-V, 2.5-V LVCMOS, and 3.3-V LVTTL/LVCMOS
0, 1, 2, 3
3
SSTL-2, SSTL-18, SSTL-15, HSTL-18, HSTL-15, and HSTL-12
0, 1, 2, 3
3
3.0-V PCI/PCI-X
0, 1, 2, 3
3
LVDS_E_1R, mini-LVDS_E_1R, and RSDS_E_1R
0, 1, 2, 3
3
LVDS_E_3R, mini-LVDS_E_3R, and RSDS_E_3R
0, 1, 2, 3
3
You can use faster slew rates to improve the available timing margin in
memory-interface applications or when the output pin has high-capacitive loading.
1
February 2011
Altera recommends performing IBIS or SPICE simulations to determine the best slew
rate setting for your specific application.
Altera Corporation
Stratix IV Device Handbook Volume 1
6–22
Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
Programmable I/O Delay
The following sections describe programmable IOE delay and programmable output
buffer delay.
Programmable IOE Delay
The Stratix IV device IOE includes programmable delays, shown in Figure 6–17 on
page 6–18, that you can activate to ensure zero hold times, minimize setup times, or
increase clock-to-output times. Each pin can have a different input delay from
pin-to-input register or a delay from output register-to-output pin values to ensure
that the bus has the same delay going into or out of the device. This feature helps read
and time margins because it minimizes the uncertainties between signals in the bus.
f For more information about programmable IOE delay specifications, refer to the DC
and Switching Characteristics for Stratix IV Devices chapter.
Programmable Output Buffer Delay
Stratix IV devices support delay chains built inside the single-ended output buffer, as
shown in Figure 6–17 on page 6–18. The delay chains can independently control the
rising and falling edge delays of the output buffer, providing the ability to adjust the
output-buffer duty cycle, compensate channel-to-channel skew, reduce simultaneous
switching output (SSO) noise by deliberately introducing channel-to-channel skew,
and improve high-speed memory-interface timing margins. Stratix IV devices
support four levels of output buffer delay settings. The default setting is No Delay.
f For more information about programmable output buffer delay specifications, refer to
the DC and Switching Characteristics for Stratix IV Devices chapter.
Open-Drain Output
Stratix IV devices provide an optional open-drain output (equivalent to an open
collector output) for each I/O pin. When configured as open drain, the logic value of
the output is either high-Z or 0. Typically, an external pull-up resistor is required to
provide logic high.
Bus Hold
Each Stratix IV device I/O pin provides an optional bus-hold feature. Bus-hold
circuitry can weakly hold the signal on an I/O pin at its last-driven state. Because the
bus-hold feature holds the last-driven state of the pin until the next input signal is
present, you do not need an external pull-up or pull-down resistor to hold a signal
level when the bus is tri-stated.
Bus-hold circuitry also pulls non-driven pins away from the input threshold voltage
where noise can cause unintended high-frequency switching. You can select this
feature individually for each I/O pin. The bus-hold output drives no higher than
VCCIO to prevent over-driving signals. If you enable the bus-hold feature, you cannot
use the programmable pull-up option. Disable the bus-hold feature if the I/O pin is
configured for differential signals.
Bus-hold circuitry uses a resistor with a nominal resistance (R BH ) of approximately
7 kΩ to weakly pull the signal level to the last-driven state.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
I/O Structure
6–23
f For more information about the specific sustaining current driven through this
resistor and the overdrive current used to identify the next-driven input level, refer to
the DC and Switching Characteristics for Stratix IV Devices chapter.
Bus-hold circuitry is active only after configuration. When going into user mode, the
bus-hold circuit captures the value on the pin present at the end of configuration.
Programmable Pull-Up Resistor
Each Stratix IV device I/O pin provides an optional programmable pull-up resistor
during user mode. If you enable this feature for an I/O pin, the pull-up resistor
(typically 25 K ) weakly holds the I/O to the VCCIO level.
Programmable pull-up resistors are only supported on user I/O pins and are not
supported on dedicated configuration pins, JTAG pins, or dedicated clock pins. If you
enable the programmable pull-up option, you cannot use the bus-hold feature.
1
When the optional DEV_OE signal drives low, all the I/O pins remain tri-stated even
with the programmable pull-up option enabled.
Programmable Pre-Emphasis
Stratix IV LVDS transmitters support programmable pre-emphasis to compensate for
the frequency dependent attenuation of the transmission line. The Quartus II software
allows four settings for programmable pre-emphasis.
f For more information about programmable pre-emphasis, refer to the High-Speed
Differential I/O Interfaces and DPA in Stratix IV Devices chapter.
Programmable Differential Output Voltage
Stratix IV LVDS transmitters support programmable V OD . The programmable V OD
settings allow you to adjust output eye height to optimize trace length and power
consumption. A higher VOD swing improves voltage margins at the receiver end; a
smaller VOD swing reduces power consumption. The Quartus II software allows four
settings for programmable VOD .
f For more information about programmable VOD , refer to the High-Speed Differential I/O
Interfaces and DPA in Stratix IV Devices chapter.
MultiVolt I/O Interface
The Stratix IV architecture supports the MultiVolt I/O interface feature that allows the
Stratix IV devices in all packages to interface with systems of different supply
voltages.
You can connect the VCCIO pins to a 1.2-, 1.5-, 1.8-, 2.5-, or 3.0-V power supply,
depending on the output requirements. The output levels are compatible with
systems of the same voltage as the power supply. (For example, when VCCIO pins are
connected to a 1.5-V power supply, the output levels are compatible with 1.5-V
systems.)
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
6–24
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
f For more information about pin connection guidelines, refer to the Stratix IV GX and
Stratix IV E Device Family Pin Connection Guidelines.
The Stratix IV VCCPD power pins must be connected to a 2.5- or 3.0-V power supply.
Using these power pins to supply the pre-driver power to the output buffers increases
the performance of the output pins. Table 6–5 lists Stratix IV MultiVolt I/O support.
Table 6–5. Stratix IV MultiVolt I/O Support
(Note 1)
Input Signal (V)
VCCIO (V) (3)
1.2
Output Signal (V)
1.2
1.5
1.8
2.5
3.0
3.3
1.2
1.5
1.8
2.5
3.0
3.3
v
—
—
—
—
—
v
—
—
—
—
—
1.5
—
v
v
—
—
—
—
v
—
—
—
—
1.8
—
v
v
—
—
—
—
—
v
—
—
—
2.5
—
—
—
v
v (2)
v (2)
—
—
—
v
—
—
3.0
—
—
—
v
v
v
—
—
—
—
v
—
Notes to Table 6–5:
(1) The pin current may be slightly higher than the default value. You must verify that the driving device’s VOL maximum and VOH minimum voltages
do not violate the applicable Stratix IV VIL maximum and VIH minimum voltage specifications.
(2) Altera recommends that you use an external clamping diode on the I/O pins when the input signal is 3.0 V or 3.3 V. You have the option to use
an internal clamping diode for column I/O pins.
(3) Each I/O bank of a Stratix IV device has its own VCCIO pins and supports only one VCCIO, either 1.2, 1.5, 1.8, or 3.0 V. The LVDS I/O standard
is not supported when VCCIO is 3.0 V. The LVDS input operations are supported when VCCIO is 1.2 V, 1.5 V, 1.8 V, or 2.5 V. The LVDS output
operations are only supported when VCCIO is 2.5 V.
On-Chip Termination Support and I/O Termination Schemes
Stratix IV devices feature dynamic series and parallel OCT to provide I/O impedance
matching and termination capabilities. OCT maintains signal quality, saves board
space, and reduces external component costs.
Stratix IV devices support:
■
On-chip series termination (RS) with calibration
■
On-chip series termination (RS) without calibration
■
On-chip Parallel termination (RT) with calibration
■
Dynamic series termination for single-ended I/O standards
■
Dynamic Parallel termination for single-ended I/O standards
■
On-chip differential termination (R D ) for differential LVDS I/O standards
Stratix IV devices support OCT in all I/O banks by selecting one of the OCT I/O
standards.
These devices also support OCT RS and RT in the same I/O bank for different I/O
standards if they use the same VCCIO supply voltage. You can independently configure
each I/O in an I/O bank to support OCT R S, programmable current strength, or OCT
RT.
1
You cannot configure both OCT R S and programmable current strength for the same
I/O buffer.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
6–25
A pair of RUP and RDN pins are available in a given I/O bank and are shared for
series- and parallel-calibrated termination. The RUP and RDN pins share the same VCCIO
and GND, respectively, with the I/O bank where they are located. The RUP and RDN
pins are dual-purpose I/Os and function as regular I/Os if you do not use the
calibration circuit.
For calibration, the connections are as follows:
■
The RUP pin is connected to VCCIO through an external 25-Ω ±1% or 50-Ω ±1%
resistor for an on-chip series termination value of 25-Ω or 50-Ω, respectively.
■
The RDN pin is connected to GND through an external 25- Ω ±1% or 50-Ω ±1%
resistor for an on-chip series termination value of 25-Ω or 50-Ω, respectively.
For on-chip parallel termination, the connections are as follows:
■
The RUP pin is connected to VCCIO through an external 50-Ω ±1% resistor.
■
The RDN pin is connected to GND through an external 50- Ω ±1% resistor.
On-Chip Series (RS) Termination Without Calibration
Stratix IV devices support driver-impedance matching to provide the I/O driver with
controlled output impedance that closely matches the impedance of the transmission
line. As a result, you can significantly reduce reflections. Stratix IV devices support
on-chip series termination for single-ended I/O standards (Figure 6–18).
The R S shown in Figure 6–18 is the intrinsic impedance of the output transistors.
Typical RS values are 25 Ω and 50 Ω. When you select matching impedance, current
strength is no longer selectable.
Figure 6–18. On-Chip Series Termination Without Calibration
Stratix IV Driver
Series Termination
Receiving
Device
VCCIO
RS
ZO = 50 Ω
RS
GND
To use on-chip termination for the SSTL Class I standard, you must select the 50-Ω
on-chip series termination setting, thus eliminating the external 25-Ω R S (to match
the 50-Ω transmission line). For the SSTL Class II standard, you must select the 25-Ω
on-chip series termination setting (to match the 50-Ω transmission line and the
near-end external 50-Ω pull-up to VTT ).
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
6–26
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
On-Chip Series Termination with Calibration
Stratix IV devices support on-chip series termination with calibration in all banks. The
on-chip series termination calibration circuit compares the total impedance of the I/O
buffer to the external 25-Ω ±1% or 50-Ω ±1% resistors connected to the RUP and RDN
pins and dynamically enables or disables the transistors until they match.
The R S shown in Figure 6–19 is the intrinsic impedance of the transistors. Calibration
occurs at the end of device configuration. When the calibration circuit finds the
correct impedance, it powers down and stops changing the characteristics of the
drivers.
Figure 6–19. On-Chip Series Termination with Calibration
Stratix IV Driver
Series Termination
Receiving
Device
VCCIO
RS
ZO = 50 Ω
RS
GND
Table 6–6 lists the I/O standards that support on-chip series termination with and
without calibration.
Table 6–6. Selectable I/O Standards for On-Chip Series Termination with and Without Calibration
(Part 1 of 2)
On-Chip Series Termination Setting
I/O Standard
3.3-V LVTTL/LVCMOS
2.5-V LVCMOS
1.8-V LVCMOS
Row I/O (Ω)
Column I/O (Ω)
50
50
25
25
50
50
25
25
50
50
25
25
50
1.5-V LVCMOS
50
1.2-V LVCMOS
50
SSTL-2 Class I
50
50
SSTL-2 Class II
25
25
SSTL-18 Class I
50
50
SSTL-18 Class II
25
25
Stratix IV Device Handbook Volume 1
25
50
25
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
6–27
Table 6–6. Selectable I/O Standards for On-Chip Series Termination with and Without Calibration
(Part 2 of 2)
On-Chip Series Termination Setting
I/O Standard
Row I/O (Ω)
Column I/O (Ω)
SSTL-15 Class I
50
50
SSTL-15 Class II
—
25
HSTL-18 Class I
50
50
HSTL-18 Class II
25
25
HSTL-15 Class I
50
50
HSTL-15 Class II
—
25
HSTL-12 Class I
50
50
HSTL-12 Class II
—
25
Left-Shift Series Termination Control
Stratix IV devices support left-shift series termination control. You can use left-shift
series termination control to get the calibrated OCT R S with half of the impedance
value of the external reference resistors connected to the RUP and RDN pins. This feature
is useful in applications that require both 25-Ω and 50-Ω calibrated OCT RS at the same
VCCIO . For example, if your application requires 25-Ω and 50-Ω calibrated OCT R S for
SSTL-2 Class I and Class II I/O standards, you only need one OCT calibration block
with 50-Ω external reference resistors.
You can enable the left-shift series termination control feature in the ALTIOBUF
megafunction in the Quartus II software. The Quartus II software only allows
left-shift series termination control for 25-Ω calibrated OCT R S with 50-Ω external
reference resistors connected to the RUP and RDN pins. You can only use left-shift series
termination control for the I/O standards that support 25-Ω calibrated OCT RS .
1
This feature is automatically enabled if you are using a bidirectional I/O with 25-Ω
calibrated OCT RS and 50-Ω parallel OCT.
f For more information about how to enable the left-shift series termination feature in
the ALTIOBUF megafunction, refer to the I/O Buffer (ALTIOBUF) Megafunction User
Guide.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
6–28
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
On-Chip Parallel Termination with Calibration
Stratix IV devices support on-chip parallel termination with calibration in all banks.
On-chip parallel termination with calibration is only supported for input
configuration of input and bidirectional pins. Output pin configurations do not
support on-chip parallel termination with calibration. Figure 6–20 shows on-chip
parallel termination with calibration. When you use parallel OCT, the VCCIO of the
bank must match the I/O standard of the pin where the parallel OCT is enabled.
Figure 6–20. On-Chip Parallel Termination with Calibration
Stratix IV OCT
VCCIO
100 Ω
ZO = 50 Ω
VREF
100 Ω
GND
Transmitter
Receiver
The on-chip parallel termination calibration circuit compares the total impedance of
the I/O buffer to the external 50-Ω ±1% resistors connected to the RUP and RDN pins
and dynamically enables or disables the transistors until they match. Calibration
occurs at the end of device configuration. When the calibration circuit finds the
correct impedance, it powers down and stops changing the characteristics of the
drivers. Table 6–7 lists the I/O standards that support on-chip parallel termination
with calibration.
Table 6–7. Selectable I/O Standards with On-Chip Parallel Termination with Calibration
On-Chip Parallel
Termination Setting
(Column I/O) (Ω)
On-Chip Parallel
Termination Setting
(Row I/O) (Ω)
SSTL-2 Class I, II
50
50
SSTL-18 Class I, II
50
50
SSTL-15 Class I, II
50
50
HSTL-18 Class I, II
50
50
HSTL-15 Class I, II
50
50
HSTL-12 Class I, II
50
50
Differential SSTL-2 Class I, II
50
50
Differential SSTL-18 Class I, II
50
50
Differential SSTL-15 Class I, II
50
50
Differential HSTL-18 Class I, II
50
50
Differential HSTL-15 Class I, II
50
50
Differential HSTL-12 Class I, II
50
50
I/O Standard
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
6–29
Expanded On-Chip Series Termination with Calibration
OCT calibration circuits always adjust OCT R S to match the external resistors
connected to the RUP and RDN pin; however, it is possible to achieve OCT R S values
other than the 25-Ω and 50-Ω resistors. Theoretically, if you need a different OCT RS
value, you can change the resistance connected to the RUP and RDN pins accordingly.
Practically, the OCT RS range that Stratix IV devices support is limited because of
output buffer size and granularity limitations.
The Quartus II software only allows discrete OCT RS calibration settings of 25, 40, 50,
and 60 Ω . You can select the closest discrete value of OCT RS with calibration settings
in the Quartus II software to your system to achieve the closest timing. For example, if
you are using 20-Ω OCT RS with calibration in your system, you can select the 25-Ω
OCT RS with calibration setting in the Quartus II software to achieve the closest
timing.
Table 6–8 lists expanded OCT R S with calibration supported in Stratix IV devices. Use
expanded on-chip series termination with calibration of SSTL and HSTL for
impedance matching to improve signal integrity but do not use it to meet the JEDEC
standard.
Table 6–8. Selectable I/O Standards with Expanded On-Chip Series Termination with Calibration
Range
Expanded OCT RS Range
I/O Standard
Row I/O (Ω)
Column I/O (Ω)
3.3-V LVTTL/LVCMOS
20–60
20–60
2.5-V LVTTL/LVCMOS
20–60
20–60
1.8-V LVTTL/LVCMOS
20–60
20–60
1.5-V LVTTL/LVCMOS
40–60
20–60
1.2-V LVTTL/LVCMOS
40–60
20–60
SSTL-2
20–60
20–60
SSTL-18
20–60
20–60
SSTL-15
40–60
20–60
HSTL-18
20–60
20–60
HSTL-15
40–60
20–60
HSTL-12
40–60
20–60
Dynamic On-Chip Termination
Stratix IV devices support on and off dynamic termination, both series and parallel,
for a bidirectional I/O in all I/O banks. Figure 6–21 shows the termination schemes
supported in Stratix IV devices. Dynamic parallel termination is enabled only when
the bidirectional I/O acts as a receiver and is disabled when it acts as a driver.
Similarly, dynamic series termination is enabled only when the bidirectional I/O acts
as a driver and is disabled when it acts as a receiver. This feature is useful for
terminating any high-performance bidirectional path because signal integrity is
optimized depending on the direction of the data.
Using dynamic OCT helps save power because device termination is internal instead
of external. Termination only switches on during input operation, thus drawing less
static power.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
6–30
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
1
When using calibrated input parallel and calibrated output series termination on
bidirectional pins, they must use the same termination value because each I/O pin
can only reference one OCT calibration block. The only exception is when using 50 Ω
parallel OCT and 25 Ω series OCT using the left shift series termination control. For
example, you cannot use calibrated 50 Ω parallel OCT on the input buffer of a
bidirectional pin and calibrated 40 Ω series OCT on the output buffer because these
would require two separate calibration blocks with different RUP and RDN resistor
values.
Figure 6–21. Dynamic Parallel OCT in Stratix IV Devices
VCCIO
VCCIO
Transmitter
Receiver
100 Ω
100 Ω
50 Ω
ZO = 50 Ω
100 Ω
100 Ω
50 Ω
GND
GND
Stratix IV OCT
Stratix IV OCT
VCCIO
VCCIO
100 Ω
100 Ω
50 Ω
ZO = 50 Ω
100 Ω
100 Ω
50 Ω
GND
GND
Transmitter
Receiver
Stratix IV OCT
Stratix IV OCT
f For more information about tolerance specifications for OCT with calibration, refer to
the DC and Switching Characteristics for Stratix IV Devices chapter.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
6–31
LVDS Input OCT (RD)
Stratix IV devices support OCT for differential LVDS input buffers with a nominal
resistance value of 100 Ω, as shown in Figure 6–22. Differential OCT RD can be enabled
in row I/O banks when both the V CCIO and VCCPD is set to 2.5 V. Column I/O banks
do not support OCT RD. Dedicated clock input pairs CLK[1,3,8,10][p,n],
PLL_L[1,4]_CLK[p,n], and PLL_R[1,4]_CLK[p,n] on the row I/O banks of Stratix IV
devices do not support RD termination.
Figure 6–22. Differential Input OCT
Transmitter
Receiver
ZO = 50 Ω
100 Ω
ZO = 50 Ω
f For more information about differential on-chip termination, refer to the High Speed
Differential I/O Interfaces and DPA in Stratix IV Devices chapter.
Summary of OCT Assignments
Table 6–9 lists the OCT assignments for the Quartus II software version 9.1 and later.
Table 6–9. Summary of OCT Assignments in the Quartus II Software
Assignment Name
Value
Applies To
Parallel 50 Ω with calibration
Input buffers for single-ended and
differential HSTL/SSTL standards
Differential
Input buffers for LVDS receivers on
row I/O banks (1)
Input Termination
Series 25 Ω without calibration
Series 50 Ω without calibration
Output Termination
Series 25 Ω with calibration
Series 40 Ω with calibration
Series 50 Ω with calibration
Output buffers for single-ended
LVTTL/LVCMOS and HSTL/SSTL
standards as well as differential
HSTL/SSTL standards
Series 60 Ω with calibration
Note to Table 6–9:
(1) You can enable differential OCT RD in row I/O banks when both VCCIO and VCCPD are set to 2.5 V.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
6–32
Chapter 6: I/O Features in Stratix IV Devices
OCT Calibration
OCT Calibration
Stratix IV devices support calibrated on-chip series termination (RS ) and calibrated
on-chip parallel termination (RT) on all I/O pins. You can calibrate the device’s I/O
bank with any of the OCT calibration blocks available in the device provided the
VCCIO of the I/O bank with the pins using calibrated OCT matches the V CCIO of the
I/O bank with the calibration block and its associated RUP and RDN pins.
OCT Calibration Block Location
Table 6–10 and Table 6–11 list the location of OCT calibration blocks in Stratix IV
devices. For both tables, the following legend applies:
1
■
“v” indicates I/O banks with OCT calibration block
■
”X” indicates I/O banks without OCT calibration block
■
“—” indicates I/O banks that are not available in the device
Table 6–10 and Table 6–11 do not show transceiver banks and transceiver calibration
blocks.
Table 6–10 lists the OCT calibration blocks in Banks 1A through 4C.
Table 6–10. OCT Calibration Block Counts and Placement in Stratix IV Devices (1A through 4C) (Part 1 of 2)
Device
EP4SE230
EP4SE360
EP4SE530
EP4SE820
EP4SGX70
EP4SGX110
EP4SGX180
EP4SGX230
Bank
Number of
OCT Blocks
1A
1B
1C
2A
2B
2C
3A
3B
3C
4A
4B
4C
780
8
v
—
X
v
—
X
v
—
X
v
—
X
Pin
780
8
v
—
X
v
—
X
v
—
X
v
—
X
1152
8
v
—
X
v
—
X
v
X
X
v
X
X
1152
8
v
—
X
v
—
X
v
X
X
v
X
X
1517
10
v
X
X
v
X
X
v
X
v
v
X
X
1760
10
v
X
X
v
X
X
v
X
v
v
X
X
1152
8
v
—
X
v
—
X
v
X
X
v
X
X
1517
10
v
X
X
v
X
X
v
X
v
v
X
X
1760
10
v
X
X
v
X
X
v
X
v
v
X
X
780
8
v
—
X
v
—
X
v
—
X
v
—
X
780
8
v
—
X
v
—
X
v
—
X
v
—
X
1152
8
v
—
X
—
—
—
v
—
X
v
—
X
780
8
v
—
X
v
—
X
v
—
X
v
—
X
1152
8
v
—
X
—
—
—
v
X
X
v
X
X
1517
8
v
—
X
v
—
X
v
X
X
v
X
X
780
8
v
—
X
v
—
X
v
—
X
v
—
X
1152
8
v
—
X
—
—
—
v
X
X
v
X
X
1517
8
v
—
X
v
—
X
v
X
X
v
X
X
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
OCT Calibration
6–33
Table 6–10. OCT Calibration Block Counts and Placement in Stratix IV Devices (1A through 4C) (Part 2 of 2)
Bank
Number of
OCT Blocks
1A
1B
1C
2A
2B
2C
3A
3B
3C
4A
4B
4C
780
8
—
—
—
—
—
—
v
—
X
v
—
X
1152
8
v
—
X
—
—
—
v
X
X
v
X
X
1517
8
v
—
X
v
—
X
v
X
X
v
X
X
1760
8
v
—
X
v
—
X
v
X
X
v
X
X
1932
10
v
X
X
v
—
X
v
X
v
v
X
X
780
8
—
—
—
—
—
—
v
—
X
v
—
X
1152
8
v
—
X
—
—
—
v
X
X
v
X
X
1517
8
v
—
X
v
—
X
v
X
X
v
X
X
1760
8
v
—
X
v
—
X
v
X
X
v
X
X
1932
10
v
X
X
v
—
X
v
X
v
v
X
X
1152
8
v
—
X
—
—
—
v
X
v
v
X
X
1517
10
v
—
X
v
—
X
v
X
v
v
X
X
1760
10
v
—
X
v
—
X
v
X
v
v
X
X
1932
10
v
—
X
v
X
X
v
X
v
v
X
X
EP4S40G2
1517
8
v
—
X
v
—
X
v
X
X
v
X
X
EP4S40G5
1517
10
v
—
X
v
—
X
v
X
v
v
X
X
EP4S100G2
1517
8
v
—
X
v
—
X
v
X
X
v
X
X
EP4S100G3
1932
10
v
—
X
v
X
X
v
X
v
v
X
X
EP4S100G4
1932
10
v
—
X
v
X
X
v
X
v
v
X
X
1517
10
v
—
X
v
—
X
v
X
v
v
X
X
1932
10
v
—
X
v
X
X
v
X
v
v
X
X
Device
EP4SGX290
EP4SGX360
EP4SGX530
EP4S100G5
Pin
Table 6–11 lists the OCT calibration blocks in Banks 5A through 8C.
Table 6–11. OCT Calibration Block Counts and Placement in Stratix IV Devices (5A through 8C) (Part 1 of 2)
Device
EP4SE230
EP4SE360
EP4SE530
EP4SE820
EP4SGX70
February 2011
Bank
Number of
OCT Blocks
5A
5B
5C
6A
6B
6C
7A
7B
7C
8A
8B
8C
780
8
v
—
X
v
—
X
v
—
X
v
—
X
780
8
v
—
X
v
—
X
v
—
X
v
—
X
1152
8
v
—
X
v
—
X
v
X
X
v
X
X
1152
8
v
—
X
v
—
X
v
X
X
v
X
X
1517
10
v
X
X
v
X
X
v
X
X
v
X
v
1760
10
v
X
X
v
X
X
v
X
X
v
X
v
1152
8
v
—
X
v
—
X
v
X
X
v
X
X
1517
10
v
X
X
v
X
X
v
X
X
v
X
v
1760
10
v
X
X
v
X
X
v
X
X
v
X
v
780
8
—
—
—
—
—
—
v
—
X
v
—
X
Pin
Altera Corporation
Stratix IV Device Handbook Volume 1
6–34
Chapter 6: I/O Features in Stratix IV Devices
OCT Calibration
Table 6–11. OCT Calibration Block Counts and Placement in Stratix IV Devices (5A through 8C) (Part 2 of 2)
Device
EP4SGX110
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
Bank
Number of
OCT Blocks
5A
5B
5C
6A
6B
6C
7A
7B
7C
8A
8B
8C
780
8
—
—
—
—
—
—
v
—
X
v
—
X
1152
8
—
—
—
v
—
X
v
—
X
v
—
X
Pin
780
8
—
—
—
—
—
—
v
—
X
v
—
X
1152
8
—
—
—
v
—
X
v
X
X
v
v
X
1517
8
v
—
X
v
—
X
v
X
X
v
X
X
780
8
—
—
—
—
—
—
v
—
X
v
—
X
1152
8
—
—
—
v
—
X
v
X
X
v
v
X
1517
8
v
—
X
v
—
X
v
X
X
v
X
X
780
8
—
—
—
—
—
—
v
—
X
v
—
X
1152
8
—
—
—
v
—
X
v
X
X
v
X
X
1517
8
v
—
X
v
—
X
v
X
X
v
X
X
1760
8
v
—
X
v
—
X
v
X
X
v
X
X
1932
10
v
—
X
v
X
X
v
X
X
v
X
v
780
8
—
—
—
—
—
—
v
—
X
v
—
X
1152
8
—
—
—
v
—
X
v
X
X
v
X
X
1517
8
v
—
X
v
—
X
v
X
X
v
X
X
1760
8
v
—
X
v
—
X
v
X
X
v
X
X
1932
10
v
—
X
v
X
X
v
X
X
v
X
v
1152
8
—
—
—
v
—
X
v
X
X
v
X
v
1517
10
v
—
X
v
—
X
v
X
X
v
X
v
1760
10
v
—
X
v
—
X
v
X
X
v
X
v
1932
10
v
X
X
v
—
X
v
X
X
v
X
v
EP4S40G2
1517
8
v
—
X
v
—
X
v
X
X
v
X
X
EP4S40G5
1517
10
v
—
X
v
—
X
v
X
X
v
X
v
EP4S100G2
1517
8
v
—
X
v
—
X
v
X
X
v
X
X
EP4S100G3
1932
10
v
X
X
v
—
X
v
X
X
v
X
v
EP4S100G4
1932
10
v
X
X
v
—
X
v
X
X
v
X
v
1517
10
v
—
X
v
—
X
v
X
X
v
X
v
1932
10
v
X
X
v
—
X
v
X
X
v
X
v
EP4SGX530
EP4S100G5
Sharing an OCT Calibration Block on Multiple I/O Banks
An OCT calibration block has the same VCCIO as the I/O bank that contains the block.
OCT RS calibration is supported on all I/O banks with different V CCIO voltage
standards, up to the number of available OCT calibration blocks. You can configure
the I/O banks to receive calibration codes from any OCT calibration block with the
same VCCIO . All I/O banks with the same VCCIO can share one OCT calibration block,
even if that particular I/O bank has an OCT calibration block.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
OCT Calibration
6–35
For example, Figure 6–23 shows a group of I/O banks that has the same VCCIO
voltage. If a group of I/O banks has the same VCCIO voltage, you can use one OCT
calibration block to calibrate the group of I/O banks placed around the periphery.
Because 3B, 4C, 6C, and 7B have the same V CCIO as bank 7A, you can calibrate all four
I/O banks (3B, 4C, 6C, and 7B) with the OCT calibration block (CB7) located in bank
7A. You can enable this by serially shifting out OCT RS calibration codes from the
OCT calibration block located in bank 7A to the I/O banks located around the
periphery.
1
I/O banks that do not contain calibration blocks share calibration blocks with I/O
banks that do contain calibration blocks.
Figure 6–23 is a top view of the silicon die that corresponds to a reverse view for flip
chip packages. It is a graphical representation only. This figure does not show
transceiver banks and transceiver calibration blocks.
Bank 7A
Bank 7B
Bank 7C
Bank 8C
Bank 8B
Bank 8A
CB 7
Figure 6–23. Example of Calibrating Multiple I/O Banks with One Shared OCT Calibration Block
Bank 1A
Bank 6A
Bank 1B
Bank 6B
Bank 1C
Bank 6C
I/O bank with the same VCCIO
Bank 2C
Bank 5C
I/O bank with different VCCIO
Bank 2B
Bank 5B
Bank 2A
Bank 5A
Bank 4A
Bank 4B
Bank 4C
Bank 3C
Bank 3B
Bank 3A
Stratix IV
OCT Calibration Block Modes of Operation
Stratix IV devices support OCT R S and OCT RT on all I/O banks. The calibration can
occur in either power-up or user mode.
Power-Up Mode
In power-up mode, OCT calibration is automatically performed at power up.
Calibration codes are shifted to selected I/O buffers before transitioning to user
mode.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
6–36
Chapter 6: I/O Features in Stratix IV Devices
OCT Calibration
User Mode
In user mode, the OCTUSRCLK, ENAOCT, nCLRUSR, and ENASER[9..0] signals are used to
calibrate and serially transfer calibration codes from each OCT calibration block to
any I/O. Table 6–12 lists the user-controlled calibration block signal names and their
descriptions.
Table 6–12. OCT Calibration Block Ports for User Control
Signal Name
Description
OCTUSRCLK
Clock for OCT block.
ENAOCT
Enable OCT Termination (Generated by user IP).
When ENOCT = 0, each signal enables the OCT serializer for the
corresponding OCT calibration block.
ENASER[9..0]
When ENAOCT = 1, each signal enables OCT calibration for the
corresponding OCT calibration block.
S2PENA_<bank#>
Serial-to-parallel load enable per I/O bank.
nCLRUSR
Clear user.
Figure 6–24 shows the flow of the user signal. When ENAOCT is 1, all OCT calibration
blocks are in calibration mode; when ENAOCT is 0, all OCT calibration blocks are in
serial data transfer mode. The OCTUSRCLK clock frequency must be 20 MHz or less.
1
You must generate all user signals on the rising edge of OCTUSRCLK.
Figure 6–24 does not show transceiver banks and transceiver calibration blocks.
CB9
Bank 1A
CB7
CB8
CB0
CB6
ENAOCT, nCLRUSR,
Bank 1B
Bank 1C
S2PENA_1C
Stratix IV
Core
Bank 2C
Bank 6C
S2PENA_6C
Bank 5C
OCTUSRCLK,
ENASER[N]
Bank 5B
CB1
CB5
CB3
Bank 4B
Bank 4C
Bank 3C
Bank 3B
Bank 3A
Bank 5A
Bank 4A
CB4
CB2
Stratix IV Device Handbook Volume 1
Bank 6A
Bank 6B
S2PENA_4C
Bank 2B
Bank 2A
Bank 7A
Bank 7B
Bank 7C
Bank 8C
Bank 8B
Bank 8A
Figure 6–24. Signals Used for User Mode Calibration
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
OCT Calibration
6–37
OCT Calibration
Figure 6–25 shows user mode signal-timing waveforms. To calibrate OCT block[N]
(where N is a calibration block number), you must assert ENAOCT one cycle before
asserting ENASER[N]. Also, nCLRUSR must be set to low for one OCTUSRCLK cycle before
the ENASER[N] signal is asserted. Assert the ENASER[N] signals for 1000 OCTUSRCLK
cycles to perform OCTRS and OCTRT calibration. You can de-assert ENAOCT one clock
cycle after the last ENASER is de-asserted.
Serial Data Transfer
After you complete calibration, you must serially shift out the 28-bit OCT calibration
codes (14-bit OCT RS and 14-bit OCT RT ) from each OCT calibration block to the
corresponding I/O buffers. Only one OCT calibration block can send out the codes at
any time by asserting only one ENASER[N] signal at a time. After you de-assert ENAOCT,
wait at least one OCTUSRCLK cycle to enable any ENASER[N] signal to begin serial
transfer. To shift the 28-bit code from the OCT calibration block[N], you must assert
ENASER[N] for exactly 28 OCTUSRCLK cycles. Between two consecutive asserted ENASER
signals, there must be at least one OCTUSRCLK cycle gap. (Figure 6–25).
Figure 6–25. OCT User Mode Signal—Timing Waveform for One OCT Block
OCTUSRCLK
ENAOCT
Calibration Phase
nCLRUSR
ENASER0
1000 OCTUSRCLK Cycles
28
OCTUSRCLK
Cycles
ts2p (1)
S2PENA_1A
Note to Figure 6–25:
(1) ts2p ≥ 25 ns.
After calibrated codes are shifted in serially to each I/O bank, the calibrated codes
must be converted from serial to parallel format before being used in the I/O buffers.
Figure 6–25 shows the S2PENA signals that can be asserted at any time to update the
calibration codes in each I/O bank. All I/O banks that received the codes from the
same OCT calibration block can have S2PENA asserted at the same time, or at a
different time, even while another OCT calibration block is calibrating and serially
shifting codes. The S2PENA signal is asserted one OCTUSRCLK cycle after ENASER is
de-asserted for at least 25 ns. You cannot use I/Os for transmitting or receiving data
when their S2PENA is asserted for parallel codes transfer.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
6–38
Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
Example of Using Multiple OCT Calibration Blocks
Figure 6–26 shows a signal timing waveform for two OCT calibration blocks doing R S
and RT calibration. Calibration blocks can start calibrating at different times by
asserting the ENASER signals at different times. ENAOCT must remain asserted while any
calibration is ongoing. You must set nCLRUSR low for one OCTUSRCLK cycle before each
ENASER[N] signal is asserted. In Figure 6–26, when you set nCLRUSR to 0 for the second
time to initialize OCT calibration block 0, this does not affect OCT calibration block 1,
whose calibration is already in progress.
Figure 6–26. OCT User-Mode Signal Timing Waveform for Two OCT Blocks
OCTUSRCLK
Calibration Phase
ENAOCT
nCLRUSR
1000 OCTUSRCLK
28 OCTUSRCLK
CY CLE S
CY CLE S
ENASER0
ENASER1
1000 OCTUSRCLK
28 OCTUSRCLK
CY CLE S
CY CLE S
ts2p (1)
S2PENA_1A (2)
ts2p (1)
S2PENA_2A (3)
Notes to Figure 6–26:
(1) ts2p ≥ 25 ns.
(2) S2PENA_1A is asserted in Bank 1A for calibration block 0.
(3) S2PENA_2A is asserted in Bank 2A for calibration block 1.
RS Calibration
If only RS calibration is used for an OCT calibration block, its corresponding ENASER
signal only requires to be asserted for 240 OCTUSRCLK cycles.
1
You must assert the ENASER signal for 28 OCTUSRCLK cycles for serial transfer.
Termination Schemes for I/O Standards
The following sections describe the different termination schemes for the I/O
standards used in Stratix IV devices.
Single-Ended I/O Standards Termination
Voltage-referenced I/O standards require both an input reference voltage, VREF, and a
termination voltage, VTT. The reference voltage of the receiving device tracks the
termination voltage of the transmitting device.
Figure 6–27 and Figure 6–28 show the details of SSTL and HSTL I/O termination on
Stratix IV devices.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
1
6–39
In Stratix IV devices, you cannot use series and parallel OCT simultaneously. For
more information, refer to “Dynamic On-Chip Termination” on page 6–29.
Figure 6–27. SSTL I/O Standard Termination
Termination
SSTL Class I
SSTL Class II
External
On-Board
Termination
25 Ω
50 Ω
25 Ω
50 Ω
50 Ω
50 Ω
VREF
Receiver
Transmitter
OCT
Transmit
VTT
50 Ω
Receiver
Transmitter
Stratix IV
Series OCT 25 Ω
VTT
VTT
50 Ω 50 Ω
50 Ω
50 Ω
8
VREF
VREF
Transmitter
Receiver
VCCIO
25 Ω
OCT
Receive
Receiver
Transmitter
Stratix IV
Parallel OCT
VTT
100 Ω
25 Ω
50 Ω
VREF
Transmitter
Receiver
VCCIO
Series OCT
50 Ω
100 Ω
Series OCT
25 Ω
100 Ω
100 Ω
Receiver
VCCIO
100 Ω
50 Ω
100 Ω
100 Ω
50 8
Transmitter
VCCIO
VCCIO
Stratix IV
Parallel OCT
VCCIO
50 Ω
VREF
100 Ω
OCT
in BiDirectional
Pins
50 Ω
VREF
Stratix IV
Series OCT 50 Ω
VTT
VTT
VTT
100 Ω
50 Ω
100 Ω
100 Ω
100 Ω
Series
OCT 50 Ω
Stratix IV
February 2011
Altera Corporation
Stratix IV
Series
OCT 25 Ω
Stratix IV
Stratix IV
Stratix IV Device Handbook Volume 1
6–40
Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
Figure 6–28. HSTL I/O Standard Termination
Termination
HSTL Class II
HSTL Class I
VTT
VTT
VTT
50 Ω 50 Ω
50 Ω
External
On-Board
Termination
50 Ω
50 Ω
VREF
VREF
Transmitter
Receiver
VTT
Stratix IV
Series OCT 50 Ω
Receiver
VTT
Stratix IV
Series OCT 25 Ω
50 Ω
50 Ω
VREF
Receiver
Transmitter
VCCIO
100 Ω
50 Ω
VREF
OCT
Receive
VTT
100 Ω
Stratix IV
Stratix IV Device Handbook Volume 1
100 Ω
Series OCT
25 Ω
Stratix IV
Parallel OCT
100 Ω
Transmitter
Receiver
VCCIO
VCCIO
100 Ω
50 Ω
100 Ω
VCCIO
50 Ω
100 Ω
VCCIO
100 Ω
Receiver
Stratix IV
Parallel OCT
Receiver
VCCIO
Transmitter
50 Ω
VREF
Transmitter
Series OCT
50 Ω
VTT
50 Ω 50 Ω
50 Ω
VREF
OCT
Transmit
OCT
in BiDirectional
Pins
Transmitter
100 Ω
50 8
100 Ω
Series
OCT 50 Ω
Stratix IV
100 Ω
Stratix IV
100 Ω
Series
OCT 25 Ω
Stratix IV
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
6–41
Differential I/O Standards Termination
Stratix IV devices support differential SSTL-18 and SSTL-2, differential HSTL-18,
HSTL-15, HSTL-12, LVDS, LVPECL, RSDS, and mini-LVDS. Figure 6–29 through
Figure 6–35 show the details of various differential I/O terminations on these devices.
1
Differential HSTL and SSTL outputs are not true differential outputs. They use two
single-ended outputs with the second output programmed as inverted.
Figure 6–29. Differential SSTL I/O Standard Termination
Termination
Differential SSTL Class II
Differential SSTL Class I
VTT VTT
50 Ω
External
On-Board
Termination
25 Ω
25 Ω
VTT VTT
25 Ω
50 Ω
Receiver
Differential SSTL Class I
Z0= 50 Ω
VTT
VCCIO
50 Ω
100 Ω
Z0= 50 Ω
100 Ω
VTT
VCCIO
GND
100 Ω
50 Ω
Z0= 50 Ω
100 Ω
GND
Altera Corporation
Receiver
Transmitter
Series OCT 25 Ω
VCCIO
Z0= 50 Ω
February 2011
50 Ω
Differential SSTL Class II
Series OCT 50 Ω
Transmitter
50 Ω
50 Ω
50 Ω
25 Ω
50 Ω
Transmitter
OCT
50 Ω
50 Ω
50 Ω
VTT VTT
Receiver
100 Ω
100 Ω
VCCIO
GND
100 Ω
100 Ω
GND
Transmitter
Receiver
Stratix IV Device Handbook Volume 1
6–42
Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
Figure 6–30. Differential HSTL I/O Standard Termination
Termination
Differential HSTL Class II
Differential HSTL Class I
VTT VTT
50 Ω
External
On-Board
Termination
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
Receiver
50 Ω
Receiver
Transmitter
Differential HSTL Class II
Differential HSTL Class I
Series OCT 50 Ω
Series OCT 25 Ω
VCCIO
Z0= 50 Ω
OCT
Z0= 50 Ω
VTT
VCCIO
50 Ω
100 Ω
Z0= 50 Ω
100 Ω
VCCIO
GND
100 Ω
VTT
50 Ω
Z0= 50 Ω
100 Ω
Receiver
100 Ω
100 Ω
VCCIO
GND
100 Ω
100 Ω
GND
GND
Stratix IV Device Handbook Volume 1
50 Ω 50 Ω
50 Ω
Transmitter
Transmitter
VTT VTT
VTT VTT
Transmitter
Receiver
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
6–43
LVDS
The LVDS I/O standard is a differential high-speed, low-voltage swing, low-power,
general-purpose I/O interface standard. In Stratix IV devices, the LVDS I/O standard
requires a 2.5-V VCCIO level. The LVDS input buffer requires 2.5-V VCCPD . Use this
standard in applications requiring high-bandwidth data transfer, such as backplane
drivers and clock distribution. LVDS requires a 100-Ω termination resistor between the
two signals at the input buffer. Stratix IV devices provide an optional 100-Ω
differential termination resistor in the device using on-chip differential termination.
Figure 6–31 shows LVDS termination. The on-chip differential resistor is only
available in the row I/O banks.
Figure 6–31. LVDS I/O Standard Termination (Note 1)
Termination
LVDS
Differential Outputs
Differential Inputs
External On-Board
Termination
50 Ω
100 Ω
50 Ω
Differential Inputs
Differential Outputs
50 Ω
OCT Receive
(True LVDS
Output)
(2)
100 Ω
50 Ω
Stratix IV OCT
OCT Receive
(Single-Ended
LVDS Output
with One-Resistor
Network,
LVDS_E_1R)
(3)
Differential Inputs
Single-Ended Outputs
≤ 1 inch
50 Ω
100 Ω
Rp
50 Ω
External Resistor
Stratix IV OCT
Single-Ended Outputs
OCT Receive
(Single-Ended
LVDS Output
with Three-Resistor
Network,
LVDS_E_3R)
(3)
Differential Inputs
≤ 1 inch
50 Ω
Rs
100 Ω
Rp
Rs
50 Ω
External Resistor
Stratix IV OCT
Notes to Figure 6–31:
(1) For LVDS output with a three-resistor network, the R S and RP values are 120 and 170 Ω, respectively. For LVDS output with a one-resistor network, the
RP value is 120 Ω.
(2) Side I/O banks support true LVDS output buffers.
(3) Column and side I/O banks support LVDS_E_1R and LVDS_E_3R I/O standards using two single-ended output buffers.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
6–44
Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
Differential LVPECL
In Stratix IV devices, the LVPECL I/O standard is supported on input clock pins on
column and row I/O banks. LVPECL output operation is not supported in Stratix IV
devices. LVDS input buffers are used to support LVPECL input operation. AC
coupling is required when the LVPECL common-mode voltage of the output buffer is
higher than the LVPECL input common-mode voltage. Figure 6–32 shows the
AC-coupled termination scheme. The 50-Ω resistors used at the receiver end are
external to the device.
Figure 6–32. LVPECL AC-Coupled Termination (Note 1)
Altera FPGA
LVPECL Output Buffer
0.1 μF
0.1 μF
Stratix IV LVPECL
Input Buffer
ZO = 50 Ω
50 Ω
VICM
50 Ω
ZO = 50 Ω
Note to Figure 6–32:
(1) The LVPECL AC-coupled termination is applicable only when you use an Altera FPGA LVPECL transmitter.
DC-coupled LVPECL is supported if the LVPECL output common mode voltage is
within the Stratix IV LVPECL input buffer specification (Figure 6–33).
Figure 6–33. LVPECL DC-Coupled Termination (Note 1)
Altera FPGA
LVPECL Output Buffer
Stratix IV LVPECL
Input Buffer
ZO = 50 Ω
ZO = 50 Ω
100 Ω
Note to Figure 6–33:
(1) The LVPECL DC-coupled termination is applicable only when you use an Altera FPGA LVPECL transmitter.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
Termination Schemes for I/O Standards
6–45
RSDS
Stratix IV devices support the RSDS output standard with data rates up to 230 Mbps
using LVDS output buffer types. For transmitters, use two single-ended output
buffers with the external one- or three-resistor networks in the column I/O bank, as
shown in Figure 6–34. The one-resistor topology is for data rates up to 200 Mbps. The
three-resistor topology is for data rates above 200 Mbps. The row I/O banks support
RSDS output using true LVDS output buffers without an external resistor network.
Figure 6–34. RSDS I/O Standard Termination (Note 1)
One-Resistor Network (RSDS_E_1R)
Termination
Three-Resistor Network (RSDS_E_3R)
≤1 inch
External
On-Board
Termination
RP
≤1 inch
50 Ω
50 Ω
RS
100 Ω
RP
50 Ω
50 Ω
100 Ω
RS
Receiver
Transmitter
Stratix IV OCT
≤1 inch
RP
OCT
Transmitter
50 Ω
50 Ω
Transmitter
Receiver
≤ 1 inch
RS
RP
100 Ω
RS
Receiver
Transmitter
Stratix IV OCT
50 Ω
50 Ω
100 Ω
Receiver
Note to Figure 6–34:
(1) The RS and RP values are pending characterization.
A resistor network is required to attenuate the LVDS output-voltage swing to meet
RSDS specifications. You can modify the three-resistor network values to reduce
power or improve noise margin. The resistor values chosen must satisfy Equation 6–1.
Equation 6–1.
R
R s × ------p2
--------------------- = 50Ω
Rp
R s + ------2
1
Altera recommends performing additional simulations using IBIS models to validate
that custom resistor values meet the RSDS requirements.
f For more information about the RSDS I/O standard, refer to the RSDS Specification
from the National Semiconductor website at www.national.com.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
6–46
Chapter 6: I/O Features in Stratix IV Devices
Design Considerations
Mini-LVDS
Stratix IV devices support the mini-LVDS output standard with data rates up to
340 Mbps using LVDS output buffer types. For transmitters, use two single-ended
output buffers with external one- or three-resistor networks, as shown in Figure 6–35.
The one-resistor topology is for data rates up to 200 Mbps. The three-resistor topology
is for data rates above 200 Mbps. The row I/O banks support mini-LVDS output using
true LVDS output buffers without an external resistor network.
Figure 6–35. Mini-LVDS I/O Standard Termination (Note 1)
One-Resistor Network (mini-LVDS_E_1R)
Termination
Three-Resistor Network (mini-LVDS_E_3R)
≤1 inch
External
On-Board
Termination
R
P
50 Ω
50 Ω
≤1 inch
RS
100 Ω
R
P
RS
Transmitter
Receiver
R
50 Ω
R
P
100 Ω
RS
Receiver
Stratix IV OCT
≤ 1 inch
OCT
Transmitter
100 Ω
Receiver
RS
50 Ω
P
50 Ω
Transmitter
Stratix IV OCT
≤1 inch
50 Ω
50 Ω
50 Ω
100 Ω
Transmitter
Receiver
Note to Figure 6–35:
(1) The RS and RP values are pending characterization.
A resistor network is required to attenuate the LVDS output voltage swing to meet the
mini-LVDS specifications. You can modify the three-resistor network values to reduce
power or improve noise margin. The resistor values chosen must satisfy Equation 6–1
on page 6–45.
1
Altera recommends that you perform additional simulations using IBIS models to
validate that custom resistor values meet the RSDS requirements.
f For more information about the mini-LVDS I/O standard, see the mini-LVDS
Specification from the Texas Instruments website at www.ti.com.
Design Considerations
Although Stratix IV devices feature various I/O capabilities for high-performance
and high-speed system designs, there are several other design considerations that
require your attention to ensure the success of your designs.
I/O Bank Restrictions
Each I/O bank can simultaneously support multiple I/O standards. The following
sections provide guidelines for mixing non-voltage-referenced and voltage-referenced
I/O standards in Stratix IV devices.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 6: I/O Features in Stratix IV Devices
Design Considerations
6–47
Non-Voltage-Referenced Standards
Each I/O bank of a Stratix IV device has its own VCCIO pins and supports only one
VCCIO , either 1.2, 1.5, 1.8, 2.5, or 3.0 V. An I/O bank can simultaneously support any
number of input signals with different I/O standard assignments if it meets the V CCIO
and VCCPD requirement, as shown in Table 6–2 on page 6–3.
For output signals, a single I/O bank supports non-voltage-referenced output signals
that are driving at the same voltage as VCCIO . Because an I/O bank can only have one
VCCIO value, it can only drive out that one value for non-voltage-referenced signals.
For example, an I/O bank with a 2.5-V VCCIO setting can support 2.5-V standard
inputs and outputs as well as 3.0-V LVCMOS inputs (but not output or bidirectional
pins).
Voltage-Referenced Standards
To accommodate voltage-referenced I/O standards, each Stratix IV device’s I/O bank
supports multiple VREF pins feeding a common VREF bus. The number of available
VREF pins increases as device density increases. If these pins are not used as VREF pins,
they cannot be used as generic I/O pins and must be tied to VCCIO or GND. Each bank
can only have a single VCCIO voltage level and a single VREF voltage level at a given
time.
An I/O bank featuring single-ended or differential standards can support
voltage-referenced standards if all voltage-referenced standards use the same VREF
setting.
For performance reasons, voltage-referenced input standards use their own V CCPD
level as the power source. This feature allows you to place voltage-referenced input
signals in an I/O bank with a V CCIO of 2.5 V or below. For example, you can place
HSTL-15 input pins in an I/O bank with 2.5-V VCCIO . However, the voltage-referenced
input with parallel OCT enabled requires the VCCIO of the I/O bank to match the
voltage of the input standard.
Voltage-referenced bidirectional and output signals must be the same as the I/O
bank’s VCCIO voltage. For example, you can only place SSTL-2 output pins in an I/O
bank with a 2.5-V VCCIO .
Mixing Voltage-Referenced and Non-Voltage-Referenced Standards
An I/O bank can support both voltage-referenced and non-voltage-referenced pins by
applying each of the rule sets individually. For example, an I/O bank can support
SSTL-18 inputs and 1.8-V inputs and outputs with a 1.8-V V CCIO and a 0.9-V VREF.
Similarly, an I/O bank can support 1.5-V standards, 1.8-V inputs (but not outputs),
and HSTL and HSTL-15 I/O standards with a 1.5-V VCCIO and 0.75-V VREF.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
6–48
Chapter 6: I/O Features in Stratix IV Devices
Document Revision History
Document Revision History
Table 6–13 lists the revision history for this chapter.
Table 6–13. Document Revision History
Date
February 2011
March 2010
November 2009
June 2009
April 2009
March 2009
November 2008
May 2008
Version
3.2
3.1
3.0
2.3
2.2
Changes
■
Updated the “Modular I/O Banks”, “On-Chip Termination Support and I/O Termination
Schemes”, “Dynamic On-Chip Termination”, and “Programmable Pull-Up Resistor”
sections.
■
Updated Figure 6–17, Figure 6–32 and Figure 6–33.
■
Applied new template.
■
Minor text edits.
■
Updated Table 6–2 and Table 6–5.
■
Updated Figure 6–18, Figure 6–19, Figure 6–27, Figure 6–28, and Figure 6–31.
■
Added the “Summary of OCT Assignments” section.
■
Added a note to the “Sharing an OCT Calibration Block on Multiple I/O Banks” section.
■
Updated the “OCT Calibration” section.
■
Minor text edits.
■
Updated Table 6–2, Table 6–4, Table 6–6, Table 6–9, and Table 6–10.
■
Updated Figure 6–1, Figure 6–2, Figure 6–4, Figure 6–5, Figure 6–6, Figure 6–8,
Figure 6–9, Figure 6–10, Figure 6–11, Figure 6–12, Figure 6–13, and Figure 6–31.
■
Added Table 6–8.
■
Added Figure 6–7, Figure 6–14, Figure 6–15, and Figure 6–16.
■
Added “Left-Shift Series Termination Control” and “Expanded On-Chip Series Termination
with Calibration” sections.
■
Updated “MultiVolt I/O Interface”, “RSDS”, “Mini-LVDS”, and “Non-Voltage-Referenced
Standards” sections.
■
Deleted Figure 6-5: Number of I/Os in Each Bank in EP4SE290 and EP4SE360 in the
1517-Pin FineLine BGA Package.
■
Minor text edits.
■
Added introductory sentences to improve search ability.
■
Removed the Conclusion section.
■
Updated Figure 6–2.
■
Updated Table 6–8 and Table 6–9.
■
Deleted Figure 6-14.
■
Updated Table 6–1, Table 6–2,Table 6–3, Table 6–4, Table 6–6, Table 6–8, and Table 6–9.
■
Updated Figure 6–2, Figure 6–7, Figure 6–8, Figure 6–9, Figure 6–10, Figure 6–11, and
Figure 6–12.
■
Added Figure 6–14.
■
Removed Equation 6–2 and “Referenced Documents” section.
■
Updated “Modular I/O Banks” on page 6–7.
■
Updated Figure 6–3 and Figure 6–21.
■
Made minor editorial changes.
2.1
2.0
1.0
Stratix IV Device Handbook Volume 1
Initial release.
February 2011
Altera Corporation
7. External Memory Interfaces in
Stratix IV Devices
February 2011
SIV51007-3.2
SIV51007-3.2
This chapter describes external memory interfaces available with the Stratix ® IV
device family and that family’s silicon capability to support external memory
interfaces. To support the level of system bandwidth achievable with Altera ®
Stratix IV FPGAs, the devices provide an efficient architecture to quickly and easily fit
wide external memory interfaces within their small modular I/O bank structure. The
I/Os are designed to provide high-performance support for existing and emerging
external double data rate (DDR) memory standards, such as DDR3, DDR2, DDR
SDRAM, QDR II+, QDR II SRAM, and RLDRAM II.
Stratix IV I/O elements provide easy-to-use built-in functionality required for a rapid
and robust implementation with features such as dynamic calibrated on-chip
termination (OCT), trace mismatch compensation, read- and write-leveling circuit for
DDR3 SDRAM interfaces, half data rate (HDR) blocks, and 4- to 36-bit programmable
DQ group widths.
The high-performance memory interface solution is backed-up by a self-calibrating
megafunction (ALTMEMPHY), optimized to take advantage of the Stratix IV I/O
structure and the TimeQuest Timing Analyzer, which completes the picture by
providing the total solution for the highest reliable frequency of operation across
process, voltage, and temperature (PVT) variations.
This chapter contains the following sections:
■
“Memory Interfaces Pin Support” on page 7–3
■
“Stratix IV External Memory Interface Features” on page 7–29
f For more information about external memory system performance specifications,
board design guidelines, timing analysis, simulation, and debugging information,
refer to the External Memory Interface Handbook.
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
Stratix IV Device Handbook Volume 1
February 2011
Subscribe
7–2
Chapter 7: External Memory Interfaces in Stratix IV Devices
Figure 7–1 shows an overview of the memory interface data path that uses all the
Stratix IV I/O element (IOE) features.
Figure 7–1. External Memory Interface Data Path Overview (Note 1), (2)
Memory
Stratix IV FPGA
Postamble Enable
Postamble Clock
4n
DPRAM
(2)
DLL
DQS Logic
Block
Postamble
Control
Circuit
DQS Enable
Circuit
2n
2n
Alignment &
Synchronization
Registers
Half Data Rate
Input Registers
DQS (Read) (3)
DDR Input
Registers
n
DQ (Read) (3)
Resynchronization Clock
n
2n
4n
Half-Rate
Resynchronization
Clock
Clock Management & Reset
DQ Write Clock
Half-Rate Clock
4
2n
Alignment
Registers
Half Data Rate
Output Registers
2
2
Half Data Rate
Output Registers
Alignment
Registers
DQ (Write) (3)
DDR Output
and Output
Enable
Registers
DQS (Write) (3)
DDR Output
and Output
Enable
Registers
Alignment Clock
DQS Write Clock
Notes to Figure 7–1:
(1) You can bypass each register block.
(2) The blocks used for each memory interface may differ slightly. The shaded blocks are part of the Stratix IV IOE.
(3) These signals may be bidirectional or unidirectional, depending on the memory standard. When bidirectional, the signal is active during both read
and write operations.
Memory interfaces use Stratix IV device features such as delay-locked loops (DLLs),
dynamic OCT control, read- and write-leveling circuitry, and I/O features such as
OCT, programmable input delay chains, programmable output delay, slew rate
adjustment, and programmable drive strength.
f For more information about I/O features, refer to the I/O Features in Stratix IV Devices
chapter.
The ALTMEMPHY megafunction instantiates a phase-locked loop (PLL) and PLL
reconfiguration logic to adjust the phase shift based on VT variation.
f For more information about the Stratix IV PLL, refer to the Clock Networks and PLLs in
Stratix IV Devices chapter. For more information about the ALTMEMPHY
megafunction, refer to the External Memory PHY Interface (ALTMEMPHY) (nonAFI)
Megafunction User Guide.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–3
Memory Interfaces Pin Support
A typical memory interface requires data (D, Q, or DQ), data strobe (DQS/CQ and
DQSn/CQn), address, command, and clock pins. Some memory interfaces use data
mask (DM, BWSn, or NWSn) pins to enable write masking and QVLD pins to indicate
that the read data is ready to be captured. This section describes how Stratix IV
devices support all these different pins.
1
If you have more than one clock pair, you must place them in the same DQ group. For
example, if you have two clock pairs, you must place both of them in the same ×4
DQS group.
f For more information about pin connections, refer to the Stratix IV GX and Stratix IV E
Device Family Pin Connection Guidelines.
f For more information about pin planning and pin connections between a Stratix IV
device and an external memory device, refer to the External Memory Interface
Handbook.
DDR3, DDR2, DDR SDRAM, and RLDRAM II devices use the CK and CK# signals to
capture the address and command signals. Generate these signals to mimic the
write-data strobe using Stratix IV DDR I/O registers (DDIOs) to ensure that the
timing relationships between the CK/CK# and DQS signals (tDQSS, tDSS, and tDSH in
DDR3, DDR2, and DDR SDRAM devices or tCKDK in RLDRAM II devices) are met.
QDR II+ and QDR II SRAM devices use the same clock (K/K#) to capture write data,
address, and command signals.
Memory clock pins in Stratix IV devices are generated using a DDIO register going to
differential output pins (refer to Figure 7–2), marked in the pin table with DIFFOUT,
DIFFIO_TX, or DIFFIO_RX prefixes.
f For more information about which pins to use for memory clock pins, refer to the
External Memory Interface Handbook.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–4
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–2. Memory Clock Generation
FPGA LEs
I/O Elements
VCC
D
Q
1
D
Q
mem_clk (2)
0
mem_clk_n (2)
System Clock (3)
Notes to Figure 7–2:
(1) For pin location requirements,refer to the External Memory Interface Handbook.
(2) The mem_clk[0] and mem_clk_n[0] pins for DDR3, DDR2, and DDR SDRAM interfaces use the I/O input buffer for feedback required by
the ALTMEMPHY megafunction for tracking; therefore, use bidirectional I/O buffers for these pins. For memory interfaces using a differential DQS
input, the input feedback buffer is configured as differential input. For memory interfaces using a single-ended DQS input, the input buffer is
configured as a single-ended input. Using a single-ended input feedback buffer requires that I/O standard’s VREF voltage is provided to that I/O
bank’s VREF pins.
(3) To minimize jitter, regional clock networks are required for memory output clock generation.
Stratix IV devices offer differential input buffers for differential read-data strobe and
clock operations. In addition, Stratix IV devices also provide an independent DQS
logic block for each CQn pin for complementary read-data strobe and clock
operations. In the Stratix IV pin tables, the differential DQS pin pairs are denoted as
DQS and DQSn pins, while the complementary CQ signals are denoted as CQ and
CQn pins. DQSn and CQn pins are marked separately in the pin table. Each CQn pin
connects to a DQS logic block and the shifted CQn signals go to the negative-edge
input registers in the DQ IOE registers.
1
Use differential DQS signaling for DDR2 SDRAM interfaces running at or above
333 MHz.
DQ pins can be bidirectional signals, as in DDR3, DDR2, and DDR SDRAM, and
RLDRAM II common I/O (CIO) interfaces, or unidirectional signals, as in QDR II+,
QDR II SRAM, and RLDRAM II separate I/O (SIO) devices. Connect the
unidirectional read-data signals to Stratix IV DQ pins and the unidirectional
write-data signals to a different DQS/DQ group than the read DQS/DQ group.
Furthermore, the write clocks must be assigned to the DQS/DQSn pins associated to
this write DQS/DQ group. Do not use the CQ/CQn pin-pair for write clocks.
1
Using a DQS/DQ group for the write-data signals minimizes output skew, allows
access to the write-leveling circuitry (for DDR3 SDRAM interfaces), and allows
vertical migration. These pins also have access to deskewing circuitry (using
programmable delay chains) that can compensate for delay mismatch between signals
on the bus.
The DQS and DQ pin locations are fixed in the pin table. Memory interface circuitry is
available in every Stratix IV I/O bank that does not support transceivers. All the
memory interface pins support the I/O standards required to support DDR3, DDR2,
DDR SDRAM, QDR II+, QDR II SRAM, and RLDRAM II devices.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–5
The Stratix IV device family supports DQS and DQ signals with DQ bus modes of ×4,
×8/×9, ×16/×18, or ×32/×36, although not all devices support DQS bus mode
×32/×36. When any of these pins are not used for memory interfacing, you can use
them as user I/Os. In addition, you can use any DQSn or CQn pins not used for
clocking as DQ (data) pins. Table 7–1 lists pin support per DQS/DQ bus mode,
including the DQS/CQ and DQSn/CQn pin pair.
Table 7–1. Stratix IV DQS/DQ Bus Mode Pins
Maximum
Number of
Data Pins
per Group
(2)
DQSn Support
CQn Support
Parity or DM
(Optional)
QVLD
(Optional) (1)
Typical
Number of
Data Pins
per Group
×4
Yes
No
No (6)
No
4
5
×8/×9 (3)
Yes
Yes
Yes
Yes
8 or 9
11
×16/×18 (4)
Yes
Yes
Yes
Yes
16 or 18
23
×32/×36 (5)
Yes
Yes
Yes
Yes
32 or 36
47
×32/×36 (7)
Yes
Yes
No (8)
Yes
32 or 36
39
Mode
Notes to Table 7–1:
(1) The QVLD pin is not used in the ALTMEMPHY megafunction.
(2) This represents the maximum number of DQ pins (including parity, data mask, and QVLD pins) connected to the DQS bus network with
single-ended DQS signaling. When you use differential or complementary DQS signaling, the maximum number of data per group decreases
by one. This number may vary per DQS/DQ group in a particular device. Check the pin table for the exact number per group. For DDR3, DDR2,
and DDR interfaces, the number of pins is further reduced for an interface larger than ×8 due to the need of one DQS pin for each ×8/×9 group
that is used to form the x16/×18 and ×32/×36 groups.
(3) Two ×4 DQS/DQ groups are stitched to make a ×8/×9 group so there are a total of 12 pins in this group.
(4) Four ×4 DQS/DQ groups are stitched to make a ×16/×18 group.
(5) Eight ×4 DQS/DQ groups are stitched to make a ×32/×36 group.
(6) The DM pin can be supported if differential DQS is not used and the group does not have additional signals.
(7) These ×32/×36 DQS/DQ groups are available in EP4SGX290, EP4SGX360, and EP4SGX530 devices in 1152- and 1517-pin FineLine BGA
packages. There are 40 pins in each of these DQS/DQ groups.
(8) There are 40 pins in each of these DQS/DQ groups. The BWSn pins cannot be placed within the same DQS/DQ group as the write data pins
because of insufficient pins available.
Table 7–2 lists the number of DQS/DQ groups available per side in each Stratix IV
device. For a more detailed listing of the number of DQS/DQ groups available per
bank in each Stratix IV device, see Figure 7–3 through Figure 7–19. These figures
represent the die-top view of the Stratix IV device.
Table 7–2. Number of DQS/DQ Groups in Stratix IV Devices per Side (Part 1 of 3) (Note 1)
Device
Package
EP4SGX70
EP4SGX110
EP4SGX180
EP4SGX230
780-pin
FineLine BGA
EP4SGX290
EP4SGX360
780-pin
FineLine BGA
EP4SE230
EP4SE360
780-pin
FineLine BGA
February 2011
Altera Corporation
Side
×4 (2)
×8/×9
×16/×18
×32/×36 (3)
Left
14
6
2
0
Top/Bottom
17
8
2
0
Right
0
0
0
0
Left/Right
0
0
0
0
Top/Bottom
18
8
2
0
Left/Right
14
6
2
0
Top/Bottom
17
8
2
0
Refer to:
Figure 7–3
Figure 7–5
Figure 7–4
Stratix IV Device Handbook Volume 1
7–6
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Table 7–2. Number of DQS/DQ Groups in Stratix IV Devices per Side (Part 2 of 3) (Note 1)
Device
Package
Side
×4 (2)
×8/×9
×16/×18
×32/×36 (3)
EP4SGX110
1152-pin
FineLine BGA
(with 16
transceivers)
EP4SGX70
EP4SGX110
1152-pin
FineLine BGA
(with 24
transceivers)
EP4SGX180
EP4SGX230
1152-pin
FineLine BGA
EP4SGX290
EP4SGX360
EP4SGX530
1152-pin
FineLine BGA
EP4SE360
EP4SE530
EP4SE820
Right/Left
7
3
1
0
Top/Bottom
17
8
2
0
Right/Left
14
6
2
0
Top/Bottom
17
8
2
0
Right/Left
13
6
2
0
Top/Bottom
26
12
4
0
Right/Left
13
6
2
0
Top/Bottom
26
12
4
2 (4)
1152-pin
FineLine BGA
All sides
26
12
4
0
Figure 7–10
EP4SGX180
EP4SGX230
1517-pin
FineLine BGA
All sides
26
12
4
0
Figure 7–11
EP4SGX290
EP4SGX360
EP4SGX530
1517-pin
FineLine BGA
Right/Left
26
12
4
0
Top/Bottom
26
12
4
2 (4)
EP4SE530
EP4SE820
1517-pin
FineLine BGA
Right/Left
34
16
6
0
Top/Bottom
38
18
8
4
EP4S40G2
EP4S40G5
EP4S100G2
EP4S100G5
Left
12
3
1
0
1517-pin
FineLine BGA
Top/Bottom
26
12
4
0
Right
11
4
1
0
EP4SGX290
EP4SGX360
EP4SGX530
1760-pin
FineLine BGA
Right/Left
26
12
4
0
Top/Bottom
38
18
8
4
EP4SE530
1760-pin
FineLine BGA
Right/Left
34
16
6
0
Top/Bottom
38
18
8
4
EP4SE820
1760-pin
FineLine BGA
Right/Left
40
18
6
0
Top/Bottom
44
22
10
4
EP4SGX290
EP4SGX360
EP4SGX530
1932-pin
FineLine BGA
Right/Left
29
13
4
0
Top/Bottom
38
18
8
4
Stratix IV Device Handbook Volume 1
February 2011
Refer to:
Figure 7–6
Figure 7–7
Figure 7–8
Figure 7–9
Figure 7–12
Figure 7–13
Figure 7–14
Figure 7–15
Figure 7–16
Figure 7–17
Figure 7–18
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–7
Table 7–2. Number of DQS/DQ Groups in Stratix IV Devices per Side (Part 3 of 3) (Note 1)
Device
Package
EP4S100G3
EP4S100G4
EP4S100G5
1932-pin
FineLine BGA
Side
×4 (2)
×8/×9
×16/×18
×32/×36 (3)
Left
8
2
0
0
Top/Bottom
38
18
8
4
Right
7
1
0
0
Refer to:
Figure 7–19
Notes to Table 7–2:
(1) These numbers are preliminary until the devices are available.
(2) Some of the ×4 groups may use RUP and RDN pins. You cannot use these groups if you use the Stratix IV calibrated OCT feature.
(3) To interface with a ×36 QDR II+/QDR II SRAM device in a Stratix IV FPGA that does not support the ×32/×36 DQS/DQ group, refer to “Combining
×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(4) These ×32/×36 DQS/DQ groups have 40 pins instead of 48 pins per group. BWSn pins cannot be placed within the same DQS/DQ group as the
write data pins because of insufficient pins available.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–8
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–3. Number of DQS/DQ Groups per Bank in EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230 Devices in the
780-Pin FineLine BGA Package (Note 1), (2), (3), (4). (5)
DLL0
I/O Bank 8A
I/O Bank 8C
I/O Bank 7C
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=2
x8/x9=1
x16/x18=0
24 User I/Os
x4=3
x8/x9=1
x16/x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL3
I/O Bank 1A
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 1C
26 User I/Os
x4=3
x8/x9=1
x16/x18=0
EP4SGX70, EP4SGX110, EP4SGX180, and
EP4SGX230 Devices in the
780-Pin FineLine BGA
I/O Bank 2C
26 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 2A
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
DLL1
I/O Bank 3A
I/O Bank 3C
I/O Bank 4C
I/O Bank 4A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=2
x8/x9=1
x16/x18=0
24 User I/Os
x4=3
x8/x9=1
x16/x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–3:
(1) These numbers are preliminary until the devices are available.
(2) EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM
device, refer to “Combining ×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
(5) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–9
Figure 7–4. Number of DQS/DQ Groups per Bank in EP4SE230 and EP4SE360 Devices in the 780-Pin FineLine BGA
Package (Note 1), (2), (3), (4), (5)
DLL0
I/O Bank 8A
I/O Bank 8C
I/O Bank 7C
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=2
x8/x9=1
x16/x18=0
24 User I/Os
x4=3
x8/x9=1
x16/x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL3
I/O Bank 1A
I/O Bank 6A
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 1C
I/O Bank 6C
26 User I/Os
x4=3
x8/x9=1
x16/x18=0
26 User I/Os
x4=3
x8/x9=1
x16/x18=0
EP4SE230 and EP4SE360 Devices in the
780-Pin FineLine BGA
I/O Bank 2C
I/O Bank 5C
26 User I/Os
x4=3
x8/x9=1
x16/x18=0
26 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 2A
I/O Bank 5A
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
DLL1
I/O Bank 3A
I/O Bank 3C
I/O Bank 4C
I/O Bank 4A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=2
x8/x9=1
x16/x18=0
24 User I/Os
x4=3
x8/x9=1
x16/x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–4:
(1) These numbers are preliminary until the devices are available.
(2) EP4SE230 and EP4SE360 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to “Combining
×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
(5) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–10
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–5. Number of DQS/DQ Groups per Bank in EP4SGX290 and EP4SGX360 Devices in the 780-Pin FineLine BGA
Package (Note 1), (2)
DLL0
I/O Bank 8A
I/O Bank 8C
I/O Bank 7C
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16//x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL3
EP4SGX290 and EP4SGX360 Devices
in the 780-Pin FineLine BGA
DLL1
I/O Bank 3A
I/O Bank 3C
I/O Bank 4C
I/O Bank 4A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–5:
(1) These numbers are preliminary until the devices are available.
(2) EP4SGX290 and EP4SGX360 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to “Combining
×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–11
Figure 7–6. Number of DQS/DQ Groups per Bank in EP4SGX110 Devices with 16 Transceivers in the 1152-Pin FineLine
BGA Package (Note 1), (2), (3), (4), (5)
DLL0
I/O Bank 8A
I/O Bank 8C
I/O Bank 7C
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=2
x8/x9=1
x16/x18=0
24 User I/Os
x4=3
x8/x9=1
x16/x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL3
I/O Bank 1A
I/O Bank 6A
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
EP4SGX110 Devices
in the 1152-Pin FineLine BGA
(with 16 Transceivers)
I/O Bank 1C
26 User I/Os
x4=3
x8/x9=1
x16/x18=0
DLL1
I/O Bank 6C
26 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 3A
I/O Bank 3C
I/O Bank 4C
I/O Bank 4A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=2
x8/x9=1
x16/x18=0
24 User I/Os
x4=3
x8/x9=1
x16/x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–6:
(1) These numbers are preliminary until the devices are available.
(2) EP4SGX110 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to “Combining ×16/×18 DQS/DQ
Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
(5) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–12
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–7. Number of DQS/DQ Groups per Bank in EP4SGX70 and EP4SGX110 Devices with 24 Transceivers in the
1152-Pin FineLine BGA Package (Note 1), (2), (3), (4), (5)
DLL0
I/O Bank 8A (3)
I/O Bank 8C
I/O Bank 7C
I/O Bank 7A (3)
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=2
x8/x9=1
x16/x18=0
24 User I/Os
x4=3
x8/x9=1
x16/x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
I/O Bank 1A (3)
DLL3
I/O Bank 6A (3)
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 1C (4)
26 User I/Os (5)
x4=3
x8/x9=1
x16/x18=0
I/O Bank 6C
26 User I/Os (5)
x4=3
x8/x9=1
x16/x18=0
EP4SGX70 and EP4SGX110 Devices
in the 1152-Pin FineLine BGA
(with 24 Transceivers)
I/O Bank 6A (3)
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 1C (4)
26 User I/Os (5)
x4=3
x8/x9=1
x16/x18=0
I/O Bank 6C
26 User I/Os (5)
x4=3
x8/x9=1
x16/x18=0
I/O Bank 3A (3)
DLL1
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
I/O Bank 3C
24 User I/Os
x4=2
x8/x9=1
x16/x18=0
I/O Bank 4C
I/O Bank 4A (3)
24 User I/Os
x4=3
x8/x9=1
x16/x18=0
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–7:
(1) These numbers are preliminary until the devices are available.
(2) EP4SGX70 and EP4SGX110 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to “Combining
×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(5) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–13
Figure 7–8. Number of DQS/DQ Groups per Bank in EP4SGX180 and EP4SGX230 Devices in the 1152-Pin FineLine BGA
Package (Note 1), (2), (3), (4), (5)
DLL0
I/O Bank 8A
I/O Bank 8B
I/O Bank 8C
I/O Bank 7C
I/O Bank 7B
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16//x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL3
I/O Bank 1A
I/O Bank 6A
48 User I/Os
x4=7
x8/x9=3
x16/x18=1
48 User I/Os
x4=7
x8/x9=3
x6/x18=1
EP4SGX180 and EP4SGX230 Devices
in the 1152-Pin FineLine BGA
I/O Bank 1C
I/O Bank 6C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL1
I/O Bank 3A
I/O Bank 3B
I/O Bank 3C
I/O Bank 4C
I/O Bank 4B
I/O Bank 4A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–8:
(1) These numbers are preliminary until the devices are available.
(2) EP4SGX180 and EP4SGX230 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to “Combining
×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(5) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–14
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–9. Number of DQS/DQ Groups per Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1152-Pin
FineLine BGA Package (Note 1), (3), (4), (5)
DLL0
I/O Bank 8A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=1 (2)
I/O Bank 8B
I/O Bank 8C
I/O Bank 7C
I/O Bank 7B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16//x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=1 (2)
DLL3
I/O Bank 1A
I/O Bank 6A
48 User I/Os
x4=7
x8/x9=3
x16/x18=1
48 User I/Os
x4=7
x8/x9=3
x6/x18=1
EP4SGX290, EP4SGX360, and EP4SGX530 Devices
in the 1152-Pin FineLine BGA
I/O Bank 1C
I/O Bank 6C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL1
I/O Bank 3A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=1 (2)
I/O Bank 3B
I/O Bank 3C
I/O Bank 4C
I/O Bank 4B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 4A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=1 (2)
DLL2
Notes to Figure 7–9:
(1) These numbers are preliminary until the devices are available.
(2) These ×32/×36 DQS/DQ groups have 40 pins instead of 48 pins per group.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group; however, there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(5) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–15
Figure 7–10. Number of DQS/DQ Groups per Bank in EP4SE360, EP4SE530, and EP4SE820 Devices in the 1152-Pin
FineLine BGA Package (Note 1), (2), (3), (4), (5)
DLL0
I/O Bank 8A
I/O Bank 8B
I/O Bank 8C
I/O Bank 7C
I/O Bank 7B
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16//x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL3
I/O Bank 1A
I/O Bank 6A
48 User I/Os
x4=7
x8/x9=3
x16/x18=1
48 User I/Os
x4=7
x8/x9=3
x6/x18=1
I/O Bank 1C
I/O Bank 6C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
EP4SE360, EP4SE530
and EP4SE820 Devices
in the 1152-Pin FineLine BGA
I/O Bank 2C
I/O Bank 5C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
I/O Bank 2A
I/O Bank 5A
48 User I/Os
x4=7
x8/x9=3
x16/x18=1
48 User I/Os
x4=7
x8/x9=3
x6/x18=1
DLL1
I/O Bank 3A
I/O Bank 3B
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 3C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 4C
I/O Bank 4B
I/O Bank 4A
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–10:
(1) These numbers are preliminary until the devices are available.
(2) EP4SE360, EP4SE530, and EP4SE820 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to
“Combining ×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
(5) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–16
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–11. Number of DQS/DQ Groups per Bank in EP4SGX180 and EP4SGX230 Devices in the 1517-Pin FineLine BGA
Package (Note 1), (2), (3), (4), (5)
DLL0
I/O Bank 8A
I/O Bank 8B
I/O Bank 8C
I/O Bank 7C
I/O Bank 7B
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16//x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL3
I/O Bank 1A
I/O Bank 6A
48 User I/Os
x4=7
x8/x9=3
x16/x18=1
48 User I/Os
x4=7
x8/x9=3
x6/x18=1
I/O Bank 1C
I/O Bank 6C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
EP4SGX180 and EP4SGX230 Devices
in the 1517-Pin FineLine BGA
I/O Bank 2C
I/O Bank 5C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
I/O Bank 2A
I/O Bank 5A
48 User I/Os
x4=7
x8/x9=3
x16/x18=1
48 User I/Os
x4=7
x8/x9=3
x6/x18=1
DLL1
I/O Bank 3A
I/O Bank 3B
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 3C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 4C
I/O Bank 4B
I/O Bank 4A
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–11:
(1) These numbers are preliminary until the devices are available.
(2) EP4SGX180 and EP4SGX230 devices do not support ×32/×36 mode. To interface with a ×36 QDR II+/QDR II SRAM device, refer to “Combining
×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(5) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–17
Figure 7–12. Number of DQS/DQ Groups per Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1517-Pin
FineLine BGA Package (Note 1), (3), (4), (5)
DLL0
I/O Bank 8A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=1 (2)
I/O Bank 8B
I/O Bank 8C
I/O Bank 7C
I/O Bank 7B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16//x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=1 (2)
DLL3
I/O Bank 1A
I/O Bank 6A
48 User I/Os
x4=7
x8/x9=3
x16/x18=1
48 User I/Os
x4=7
x8/x9=3
x6/x18=1
I/O Bank 1C
I/O Bank 6C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
EP4SGX290, EP4SGX360, and EP4SGX530 Devices
in the 1517-Pin FineLine BGA
I/O Bank 2C
I/O Bank 5C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
I/O Bank 2A
I/O Bank 5A
48 User I/Os
x4=7
x8/x9=3
x16/x18=1
48 User I/Os
x4=7
x8/x9=3
x6/x18=1
DLL1
I/O Bank 3A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=1 (2)
I/O Bank 3B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 3C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 4C
I/O Bank 4B
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 4A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=1 (2)
DLL2
Notes to Figure 7–12:
(1) These numbers are preliminary until the devices are available.
(2) These ×32/×36 DQS/DQ groups have 40 pins instead of 48 pins per group.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(5) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–18
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–13. Number of DQS/DQ Groups per Bank in EP4SE530 and EP4SE820 Devices in the 1517-pin FineLine BGA
Package (Note 1), (2), (3), (4)
DLL0
I/O Bank 8A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 7A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 1A
DLL3
I/O Bank 6A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 1B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
x32/x36=0
I/O Bank 6B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
x32/x36=0
I/O Bank 1C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 6C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
EP4SE530 and EP4SE820 Devices
in the 1517-Pin FineLine BGA
I/O Bank 2C
I/O Bank 5C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 2B
I/O Bank 5B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
x32/x36=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
x32/x36=0
I/O Bank 2A
I/O Bank 5A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
DLL1
I/O Bank 3A
I/O Bank 3B
I/O Bank 3C
I/O Bank 4C
I/O Bank 4B
I/O Bank 4A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL2
Notes to Figure 7–13:
(1) These numbers are preliminary until the devices are available.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(3) All I/O pin counts include dedicated clock inputs and dedicated corner PLL clock inputs that you can use for data inputs.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–19
Figure 7–14. Number of DQS/DQ Groups per Bank in EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices in the
1517-Pin FineLine BGA Package (Note 1), (2), (3), (4), (5)
DLL0
I/O Bank 8A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
I/O Bank 8B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 8C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 7C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
I/O Bank 7B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
I/O Bank 7A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL3
I/O Bank 1A
I/O Bank 6A
43 User I/Os
x4=5
x8/x9=1
x16/x18=0
44 User I/Os
x4=5
x8/x9=1
x16/x18=0
I/O Bank 1C
20 User I/Os
x4=0
x8/x9=0
x16/x18=0
I/O Bank 6C
21 User I/Os
x4=0
x8/x9=0
x16/x18=0
EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices
in the 1517-Pin FineLine BGA
I/O Bank 2C
21 User I/Os
x4=1
x8/x9=0
x16/x18=0
I/O Bank 5C
21 User I/Os
x4=0
x8/x9=0
x16/x18=0
I/O Bank 2A
I/O Bank 5A
46 User I/Os
x4=6
x8/x9=2
x16/x18=1
46 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL1
I/O Bank 3A
I/O Bank 3B
I/O Bank 3C
I/O Bank 4C
I/O Bank 4B
I/O Bank 4A
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
40 User I/Os
x4=6
x8/x9=3
x16/x18=1
DLL2
Notes to Figure 7–14:
(1) These numbers are preliminary until the devices are available.
(2) EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 devices do not support × 32/× 36 mode. To interface with a × 36 QDR II+/QDR II SRAM
device, refer to “Combining ×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page 7–26.
(3) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(4) All I/O pin counts include dedicated clock inputs that you can use for data inputs.
(5) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a × 4 DQS/DQ group with any of its pin members
used for configuration purposes. Make sure that the DQS/DQ groups that you have chosen are not used for configuration as you may lose up to
four × 4 DQS/DQ groups, depending on your configuration scheme.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–20
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–15. Number of DQS/DQ Groups per Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1760-Pin
FineLine BGA Package (Note 1), (2), (3), (4)
DLL0
I/O Bank 8A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7C
32 User I/Os
x4=3
x8/x9=1
x16//x18=0
x32/x36=0
I/O Bank 7B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 7A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL3
I/O Bank 1A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 6A
50 User I/Os
x4=7
x8/x9=3
x6/x18=1
x32/x36=0
I/O Bank 1C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 6C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
EP4SGX290, EP4SGX360, and EP4SGX530 Devices
in the 1760-Pin FineLine BGA
I/O Bank 2C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 5C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 5A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 2A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
DLL1
I/O Bank 3A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 3B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 3C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 4C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 4B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 4A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL2
Notes to Figure 7–15:
(1) These numbers are preliminary until the devices are available.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(3) All I/O pin counts include dedicated clock inputs and dedicated corner PLL clock inputs that you can use for data inputs.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–21
Figure 7–16. Number of DQS/DQ Groups per Bank in EP4SE530 Devices in the 1760-Pin FineLine BGA Package (Note 1),
(2), (3), (4)
DLL0
I/O Bank 8A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 7A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL3
I/O Bank 1A
I/O Bank 6A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 1B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
x32/x36=0
I/O Bank 6B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
x32/x36=0
I/O Bank 1C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 6C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
EP4SE530 Devices
in the 1760-Pin FineLine BGA
I/O Bank 2C
I/O Bank 5C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 2B
I/O Bank 5B
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
x32/x36=0
24 User I/Os
x4=4
x8/x9=2
x16/x18=1
x32/x36=0
I/O Bank 2A
I/O Bank 5A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
DLL1
I/O Bank 3A
I/O Bank 3B
I/O Bank 3C
I/O Bank 4C
I/O Bank 4B
I/O Bank 4A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL2
Notes to Figure 7–16:
(1) These numbers are preliminary until the devices are available.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(3) All I/O pin counts include dedicated clock inputs and dedicated corner PLL clock inputs that you can use for data inputs.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–22
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–17. Number of DQS/DQ Groups per Bank in EP4SE820 Devices in the 1760-pin FineLine BGA Package (Note 1),
(2), (3), (4)
DLL0
I/O Bank 8A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8C
48 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 7C
48 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 7B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 7A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL3
I/O Bank 1A
I/O Bank 6A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 6B
36 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 1B
36 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 1C
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 6C
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
EP4SE820 Devices
in the 1760-Pin FineLine BGA
I/O Bank 2C
I/O Bank 5C
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 2B
I/O Bank 5B
36 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
36 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 2A
I/O Bank 5A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
DLL1
I/O Bank 3A
I/O Bank 3B
I/O Bank 3C
I/O Bank 4C
I/O Bank 4B
I/O Bank 4A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
48 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL2
Notes to Figure 7–17:
(1) These numbers are preliminary until the devices are available.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(3) All I/O pin counts include dedicated clock inputs and dedicated corner PLL clock inputs that you can use for data inputs.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–23
Figure 7–18. Number of DQS/DQ Groups per Bank in EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1932-Pin
FineLine BGA Package (Note 1), (2), (3), (4)
DLL0
I/O Bank 8A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 7A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 1A
DLL3
I/O Bank 6A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 1C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 6C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
I/O Bank 2C
I/O Bank 5C
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
42 User I/Os
x4=6
x8/x9=3
x16/x18=1
x32/x36=0
EP4SGX290, EP4SGX360, and EP4SGX530 Devices
in the 1932-Pin FineLine BGA
I/O Bank 2B
I/O Bank 5B
20 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
20 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 2A
I/O Bank 5A
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
50 User I/Os
x4=7
x8/x9=3
x16/x18=1
x32/x36=0
DLL1
I/O Bank 3A
I/O Bank 3B
I/O Bank 3C
I/O Bank 4C
I/O Bank 4B
I/O Bank 4A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL2
Notes to Figure 7–18:
(1) These numbers are preliminary until the devices are available.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(3) All I/O pin counts include dedicated clock inputs and dedicated corner PLL clock inputs that you can use for data inputs.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–24
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Figure 7–19. Number of DQS/DQ Groups per Bank in EP4S100G3, EP4S100G4, and EP4S100G5 Devices in the 1932-Pin
FineLine BGA Package (Note 1), (2), (3), (4)
DLL0
I/O Bank 8A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 8C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7C
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 7B
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
I/O Bank 7A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL3
I/O Bank 6A
I/O Bank 1A
38 User I/Os
x4=3
x8/x9=0
x16/x18=0
x32/x36=0
40 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
I/O Bank 6C
20 User I/Os
x4=0
x8/x9=0
x16/x18=0
x32/x36=0
I/O Bank 1C
19 User I/Os
x4=0
x8/x9=0
x16/x18=0
x32/x36=0
I/O Bank 2C
I/O Bank 5C
19 User I/Os
x4=0
x8/x9=0
x16/x18=0
x32/x36=0
17 User I/Os
x4=0
x8/x9=0
x16/x18=0
x32/x36=0
EP4S100G3, EP4S100G4, and EP4S100G5 Devices
in the 1932-Pin FineLine BGA
I/O Bank 2B
I/O Bank 5B
13 User I/Os
x4=1
x8/x9=0
x16/x18=0
x32/x36=0
12 User I/Os
x4=0
x8/x9=0
x16/x18=0
x32/x36=0
I/O Bank 2A
I/O Bank 5A
39 User I/Os
x4=4
x8/x9=1
x16/x18=0
x32/x36=0
40 User I/Os
x4=4
x8/x9=1
x16/x18=0
x32/x36=0
DLL1
I/O Bank 3A
I/O Bank 3B
I/O Bank 3C
I/O Bank 4C
I/O Bank 4B
I/O Bank 4A
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
32 User I/Os
x4=3
x8/x9=1
x16/x18=0
x32/x36=0
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
48 User I/Os
x4=8
x8/x9=4
x16/x18=2
x32/x36=1
DLL2
Notes to Figure 7–19:
(1) These numbers are preliminary until the devices are available.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as R UP and RDN pins, but you cannot use a ×4 group for memory interfaces if two pins
of the ×4 group are used as RUP and RDN pins for OCT calibration. If two pins of a ×4 group are used as RUP and R DN pins for OCT calibration, you
can use the ×16/×18 or ×32/×36 groups that include that ×4 group, however there are restrictions on using ×8/×9 groups that include that ×4
group.
(3) All I/O pin counts include dedicated clock inputs and dedicated corner PLL clock inputs that you can use for data inputs.
(4) You can also use some of the DQS/DQ pins in I/O Bank 1C as configuration pins. You cannot use a ×4 DQS/DQ group with any of its pin members
used for configuration purposes. Ensure that the DQS/DQ groups that you have chosen are not also used for configuration because you may lose
up to four ×4 DQS/DQ groups, depending on your configuration scheme.
The DQS and DQSn pins are listed in the Stratix IV pin tables as DQSXY and DQSnXY,
respectively, where X indicates the DQS/DQ grouping number and Y indicates
whether the group is located on the top (T), bottom (B), left (L), or right (R) side of the
device. The DQS/DQ pin numbering is based on ×4 mode.
The corresponding DQ pins are marked as DQXY, where X indicates which DQS group
the pins belong to and Y indicates whether the group is located on the top (T), bottom
(B), left (L), or right (R) side of the device. For example, DQS1L indicates a DQS pin
located on the left side of the device. The DQ pins belonging to that group are shown
as DQ1L in the pin table. For more information, refer to Figure 7–20.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
1
7–25
The parity, DM, BWSn, NWSn, ECC, and QVLD pins are shown as DQ pins in the pin
table.
The numbering scheme starts from the top-left corner of the device going
counter-clockwise in a die-top view. Figure 7–20 shows how the DQS/DQ groups are
numbered in a die-top view of the device. The top and bottom sides of the device can
contain up to 38 ×4 DQS/DQ groups. The left and right sides of the device can contain
up to 34 ×4 DQS/DQ groups.
Figure 7–20. DQS Pins in Stratix IV I/O Banks
DQS20T
DQS38T
DQS19T
DQS1T
DLL0
DLL3
PLL_T1
PLL_T2
PLL_R1
PLL_L1
8A
8B
8C
7C
7B
7A
DQS1L
DQS34R
1A
6A
1B
6B
1C
6C
DQS17L
DQS18R
PLL_R2
PLL_L2
Stratix IV Device
PLL_R3
PLL_L3
DQS18L
DQS17R
2C
5C
2B
5B
2A
5A
DQS34L
DQS1R
3A
3B
3C
4C
4B
4A
PLL_R4
PLL_L4
PLL_B1
PLL_B2
DLL2
DLL1
DQS1B
February 2011
Altera Corporation
DQS19B
DQS20B
DQS38B
Stratix IV Device Handbook Volume 1
7–26
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Using the RUP and RDN Pins in a DQS/DQ Group Used for Memory Interfaces
You can use the DQS/DQSn pins in some of the ×4 groups as R UP and R DN pins (listed
in the pin table). You cannot use a ×4 DQS/DQ group for memory interfaces if any of
its pin members are used as RUP and RDN pins for OCT calibration. You may be able to
use the ×8/×9 group that includes this ×4 DQS/DQ group, if either of the following
applies:
■
You are not using DM pins with your differential DQS pins
■
You are not using complementary or differential DQS pins
You can use the ×8/×9 group because a DQS/DQ ×8/×9 group actually comprises 12
pins, as the groups are formed by stitching two DQS/DQ groups in ×4 mode with six
pins each (refer to Table 7–1 on page 7–5). A typical ×8 memory interface consists of
one DQS, one DM, and eight DQ pins that add up to 10 pins. If you choose your pin
assignment carefully, you can use the two extra pins for RUP and RDN . In a DDR3
SDRAM interface, you must use differential DQS, which means that you only have
one extra pin. In this case, pick different pin locations for the RUP and R DN pins (for
example, in the bank that contains the address and command pins).
You cannot use the RUP and RDN pins shared with DQS/DQ group pins when using
×9 QDR II+/QDR II SRAM devices, as the R UP and R DN pins are dual purpose with
the CQn pins. In this case, pick different pin locations for R UP and RDN pins to avoid
conflict with memory interface pin placement. In this case, you have the choice of
placing the RUP and RDN pins in the data-write group or in the same bank as the
address and command pins.
There is no restriction on using ×16/×18 or ×32/×36 DQS/DQ groups that include the
×4 groups whose pins are being used as RUP and RDN pins, because there are enough
extra pins that can be used as DQS pins.
1
For ×8, ×16/×18, or ×32/×36 DQS/DQ groups whose members are used for R UP and
RDN , you must assign DQS and DQ pins manually. The Quartus ® II software might
not be able to place DQS and DQ pins without manual pin assignments, resulting in a
“no-fit”.
Combining ×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface
This implementation combines ×16/×18 DQS/DQ groups to interface with a ×36
QDR II+/QDR II SRAM device. The ×36 read data bus uses two ×16/×18 groups
while the ×36 write data uses another two ×16/×18 or four ×8/×9 groups. The
CQ/CQn signal traces are split on the board trace to connect to two pairs of CQ/CQn
pins in the FPGA. This is the only connection on the board that you need to change for
this implementation. Other QDR II+/QDR II SRAM interface rules for Stratix IV
devices also apply for this implementation.
1
The ALTMEMPHY megafunction and UniPHY-based external memory interface IPs
do not use the QVLD signal, so you can leave the QVLD signal unconnected as in any
QDR II+/QDR II SRAM interface.
f For more information about the ALTMEMPHY megafunction or UniPHY-based IPs,
refer to the External Memory Interface Handbook.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
7–27
Rules to Combine Groups
In 780-, 1152-, and some 1517-pin package devices, there is at most one ×16/×18 group
per I/O sub-bank. You can combine two ×16/×18 groups from a single side of the
device for a ×36 interface.
For devices that do not have four ×16/×18 groups in a single side of the device to
form two ×36 groups for read and write data, you can form one ×36 group on one side
of the device and another ×36 group on the other side of the device.
For vertical migration with the ×36 emulation implementation, check if migration is
possible by enabling device migration in the Quartus II project. The Quartus II
software supports the use of four ×8/×9 DQ groups for write data pins and migration
of these groups across device density. Table 7–3 lists the possible combinations to use
two ×16/×18 DQS/DQ groups to form a ×32/×36 group on Stratix IV devices lacking
a native ×32/×36 DQS/DQ group.
Table 7–3. Possible Group Combinations in Stratix IV Devices (Part 1 of 2)
Package
780-Pin
FineLine BGA
1152-Pin
FineLine BGA
February 2011
Altera Corporation
Device Density
■
EP4SGX70
■
EP4SGX110
■
EP4SGX180
■
EP4SGX230
■
EP4SGX290
■
EP4SGX360
■
EP4SE230
■
EP4SE360
■
EP4SGX70
■
EP4SGX110
■
EP4SGX180
■
EP4SGX230
■
EP4SGX290 (2)
■
EP4SGX360 (2)
■
EP4SGX530 (2)
■
EP4SE360
■
EP4SE530
■
EP4SE820
I/O Sub-Bank Combinations
3A and 4A, 7A and 8A (bottom and top I/O banks) (1)
1A and 2A, 5A and 6A (left and right I/O banks)
3A and 4A, 7A and 8A (bottom and top I/O banks) (1)
3A and 4A, 7A and 8A (bottom and top I/O banks) (1)
1A and 1C, 6A and 6C (left and right I/O banks)
3A and 3B, 4A and 4B (bottom I/O banks)
7A and 7B, 8A and 8B (top I/O banks)
1A and 1C, 2A and 2C (left I/O banks)
3A and 3B, 4A and 4B (bottom I/O banks)
5A and 5C, 6A and 6C (right I/O banks)
7A and 7B, 8A and 8B (top I/O banks)
Stratix IV Device Handbook Volume 1
7–28
Chapter 7: External Memory Interfaces in Stratix IV Devices
Memory Interfaces Pin Support
Table 7–3. Possible Group Combinations in Stratix IV Devices (Part 2 of 2)
Package
1517-Pin
FineLine BGA
1760-Pin
FineLine BGA
1932-Pin
FineLine BGA
Device Density
■
EP4SGX180
■
EP4SGX230
■
EP4SGX290 (2)
■
EP4SGX360 (2)
■
EP4SGX530 (2)
■
EP4SE530 (2)
■
EP4SE820 (2)
■
EP4S40G2
■
EP4S40G5
■
EP4S100G2
■
EP4S100G5
■
EP4SGX290
■
EP4SGX360
■
EP4SGX530
■
EP4SE530 (2)
■
EP4SE820 (2)
■
EP4SGX290 (2)
■
EP4SGX360 (2)
■
EP4SGX530 (2)
I/O Sub-Bank Combinations
1A and 1C, 2A and 2C (left I/O banks)
3A and 3B, 4A and 4B (bottom I/O banks)
5A and 5C, 6A and 6C (right I/O banks)
7A and 7B, 8A and 8B (top I/O banks)
1A and 1B, 2A and 2B or 1B and 1C, 2B and 2C (left I/O
banks) (3)
5A and 5B, 6A and 6B or 5B and 5C, 6B and 6C (right I/O
banks) (3)
3A and 3B, 4A and 4B (bottom I/O banks)
7A and 7B, 8A and 8B (top I/O banks)
1A and 1C, 2A and 2C (left I/O banks)
3A and 3B, 4A and 4B (bottom I/O banks)
5A and 5C, 6A and 6C (right I/O banks)
7A and 7B, 8A and 8B (top I/O banks)
1A and 1B, 2A and 2B or 1B and 1C, 2B and 2C (left I/O
banks) (3)
5A and 5B, 6A and 6B or 5B and 5C, 6B and 6C (right I/O
banks) (3)
1A and 1C, 2A and 2C (left I/O banks)
5A and 5C, 6A and 6C (right I/O banks)
Notes to Table 7–3:
(1) Each side of the device in these packages has four remaining ×8/×9 groups. You can combine them for the write
side (only) if you want to keep the ×36 QDR II+/QDR II SRAM interface on one side of the device. You must change
the Memory Interface Data Group default assignment from the default 18 to 9 in this case.
(2) This device supports ×36 DQS/DQ groups on the top and bottom I/O banks natively.
(3) Although it is possible to combine the ×16/×18 DQS/DQ groups from I/O banks 1A and 1C, 2A and 2C, 5A and 5C,
and 6A and 6C, Altera does not recommend this due to the size of the package. Similarly, crossing a bank number
(for example, combining groups from I/O banks 6C and 5C) is not supported in this package.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–29
Stratix IV External Memory Interface Features
Stratix IV devices are rich with features that allow robust high-performance external
memory interfacing. The ALTMEMPHY megafunction allows you to use these
external memory interface features and helps set up the physical interface (PHY) best
suited for your system. This section describes each Stratix IV device feature that is
used in external memory interfaces from the DQS phase-shift circuitry, DQS logic
block, leveling multiplexers, and dynamic OCT control block.
1
The ALTMEMPHY megafunction and the Altera memory controller MegaCore®
functions can run at half the frequency of the I/O interface of the memory devices to
allow better timing management in high-speed memory interfaces. Stratix IV devices
have built-in registers in the IOE to convert data from full-rate (the I/O frequency) to
half-rate (the controller frequency) and vice versa. You can bypass these registers if
your memory controller is not running at half the rate of the I/O frequency. When
using the Altera memory controller MegaCore functions, the ALTMEMPHY
megafunction is instantiated for you.
f For more information about the ALTMEMPHY megafunction, refer to the External
Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide.
DQS Phase-Shift Circuitry
Stratix IV phase-shift circuitry provides phase shift to the DQS/CQ and CQn pins on
read transactions when the DQS/CQ and CQn pins are acting as input clocks or
strobes to the FPGA. The DQS phase-shift circuitry consists of DLLs that are shared
between multiple DQS pins and the phase-offset module to further fine-tune the DQS
phase shift for different sides of the device.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–30
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Figure 7–21 shows how the DQS phase-shift circuitry is connected to the DQS/CQ
and CQn pins in the device where memory interfaces are supported on all sides of the
Stratix IV device.
Figure 7–21. DQS/CQ and CQn Pins and DQS Phase-Shift Circuitry (Note 1), (2)
DQS/CQ
Pin
CQn
Pin
DLL
Reference
Clock
DQS/CQ
Pin
CQn
Pin
DLL
Reference
Clock
DQS Logic
Blocks
DQS
Phase-Shift
Circuitry
Δt
Δt
Δt
Δt
to IOE
to IOE
to IOE
to IOE
DQS
Phase-Shift
Circuitry
DQS Logic
Blocks
DQS/CQ
Pin
CQn
Pin
DQS/CQ
Pin
CQn
Pin
Δt
to
IOE
Δt
to
IOE
Δt
to
IOE
Δt
to
IOE
DQS
Phase-Shift
Circuitry
to IOE
to IOE
to IOE
to IOE
Δt
Δt
Δt
Δt
to
IOE
Δt
CQn
Pin
to
IOE
Δt
DQS/CQ
Pin
to
IOE
Δt
CQn
Pin
to
IOE
Δt
DQS/CQ
Pin
DQS
Phase-Shift
Circuitry
DLL
Reference
Clock
DLL
Reference
Clock
CQn
Pin
DQS/CQ
Pin
CQn
Pin
DQS/CQ
Pin
Notes to Figure 7–21:
(1) For possible reference input clock pins for each DLL, refer to “DLL” on page 7–31.
(2) You can configure each DQS/CQ and CQn pin with a phase shift based on one of two possible DLL output settings.
DQS phase-shift circuitry is connected to the DQS logic blocks that control each
DQS/CQ or CQn pin. The DQS logic blocks allow the DQS delay settings to be
updated concurrently at every DQS/CQ or CQn pin.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–31
DLL
DQS phase-shift circuitry uses a DLL to dynamically control the clock delay needed
by the DQS/CQ and CQn pin. The DLL, in turn, uses a frequency reference to
dynamically generate control signals for the delay chains in each of the DQS/CQ and
CQn pins, allowing it to compensate for PVT variations. The DQS delay settings are
Gray-coded to reduce jitter when the DLL updates the settings. The phase-shift
circuitry needs 1,280 clock cycles to lock and calculate the correct input clock period
when the DLL is in low jitter mode. Otherwise, only 256 clock cycles are needed. Do
not send data during these clock cycles because there is no guarantee that it will be
captured properly. As the settings from the DLL may not be stable until this lock
period has elapsed, be aware that anything using these settings (including the
leveling delay system) may be unstable during this period.
1
You can still use the DQS phase-shift circuitry for any memory interfaces that are less
than 100 MHz. However, the DQS signal may not shift over 2.5 ns. Even if the DQS
signal is not shifted exactly to the middle of the DQ valid window, the I/O element
should still be able to capture the data in low-frequency applications in which a large
amount of timing margin is available.
There are a maximum of four DLLs in a Stratix IV device, located in each corner of the
device. These four DLLs support a maximum of four unique frequencies, with each
DLL running at one frequency. Each DLL can have two outputs with different phase
offsets, which allows one Stratix IV device to have eight different DLL phase shift
settings.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–32
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Figure 7–22 shows the DLL and I/O bank locations in Stratix IV devices from a
die-top view if all sides of the device support external memory interfaces.
Figure 7–22. Stratix IV DLL and I/O Bank Locations (Die-Top View)
PLL_L1
8A
8B
8C
PLL_T1
PLL_T2
7C
7B
PLL_R1
7A
6
6
DLL0
DLL3
6
6
1A
6A
1B
6B
1C
6C
PLL_R2
PLL_L2
Stratix IV FPGA
PLL_L3
PLL_R3
2C
5C
2B
5B
5A
2A
6
6
DLL1
6
DLL2
6
PLL_L4
3A
3B
3C
PLL_B1
PLL_B2
4C
4B
4A
PLL_R4
The DLL can access the two adjacent sides from its location within the device. For
example, DLL0 on the top left of the device can access the top side (I/O banks 7A, 7B,
7C, 8A, 8B, and 8C) and the left side of the device (I/O banks 1A, 1B, 1C, 2A, 2B, and
2C). This means that each I/O bank is accessible by two DLLs, giving more flexibility
to create multiple frequencies and multiple-type interfaces. You can have two
different interfaces with the same frequency on the two sides adjacent to a DLL, where
the DLL controls the DQS delay settings for both interfaces.
Each bank can use settings from either or both DLLs the bank is adjacent to. For
example, DQS1L can get its phase-shift settings from DLL0, while DQS2L can get its
phase-shift settings from DLL1. Table 7–4 lists the DLL location and supported I/O
banks for Stratix IV devices.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
1
7–33
You can only have one memory interface in each I/O sub-bank (such as I/O
sub-banks 1A, 1B, and 1C) when you use leveling delay chains. This is because there
is only one leveling delay chain per I/O sub-bank.
Table 7–4. DLL Location and Supported I/O Banks
DLL
Location
Accessible I/O Banks (1)
DLL0
Top-left corner
1A, 1B, 1C, 2A, 2B, 2C, 7A, 7B, 7C, 8A, 8B, 8C
DLL1
Bottom-left corner
1A, 1B, 1C, 2A, 2B, 2C, 3A, 3B, 3C, 4A, 4B, 4C
DLL2
Bottom-right corner
3A, 3B, 3C, 4A, 4B, 4C, 5A, 5B, 5C, 6A, 6B, 6C
DLL3
Top-right corner
5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 8A, 8B, 8C
Note to Table 7–4:
(1) The DLL can access these I/O banks if they are available for memory interfacing.
The reference clock for each DLL may come from PLL output clocks or any of the two
dedicated clock input pins located in either side of the DLL. Table 7–5 through
Table 7–17 lists the available DLL reference clock input resources for the Stratix IV
device family.
1
When you have a dedicated PLL that only generates the DLL input reference clock, set
the PLL mode to No Compensation to achieve better performance or the Quartus II
software changes it automatically. Because the PLL does not use any other outputs, it
does not need to compensate for any clock paths.
Table 7–5. DLL Reference Clock Input for EP4SGX70, EP4SGX110, EP4SGX180, and EP4SGX230 Devices in the 780-Pin
FineLine BGA Package
DLL
DLL0
DLL1
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
CLK12P
CLK0P
CLK13P
CLK1P
CLK14P
CLK2P
PLL_T1
PLL_L2
—
CLK15P
CLK3P
CLK4P
CLK0P
CLK5P
CLK1P
CLK6P
CLK2P
PLL_B1
—
—
CLK7P
CLK3P
—
PLL_B1
—
—
—
PLL_T1
—
—
CLK4P
DLL2
CLK5P
CLK6P
CLK7P
CLK12P
DLL3
CLK13P
CLK14P
CLK15P
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–34
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Table 7–6. DLL Reference Clock Input for EP4SE230 and EP4SE360 Devices in the 780-Pin FineLine BGA Package
DLL
DLL0
DLL1
DLL2
DLL3
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
CLK12P
CLK0P
CLK13P
CLK1P
CLK14P
CLK2P
CLK15P
CLK3P
CLK4P
CLK0P
CLK5P
CLK1P
CLK6P
CLK2P
CLK7P
CLK3P
CLK4P
CLK8P
CLK5P
CLK9P
CLK6P
CLK10P
CLK7P
CLK11P
CLK12P
CLK8P
CLK13P
CLK9P
CLK14P
CLK10P
CLK15P
CLK11P
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
PLL_T1
PLL_L2
—
PLL_B1
PLL_L2
—
PLL_B1
PLL_R2
—
PLL_T1
PLL_R2
—
Table 7–7. DLL Reference Clock Input for EP4SGX290 and EP4SGX360 Devices in the 780-Pin FineLine BGA Package
DLL
CLKIN (Top/Bottom)
CLKIN
(Left/Right)
PLL (Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
—
PLL_T1
—
—
—
PLL_B1
—
—
—
PLL_B2
—
—
—
PLL_T2
—
—
CLK12P
DLL0
CLK13P
CLK14P
CLK15P
CLK4P
DLL1
CLK5P
CLK6P
CLK7P
CLK4P
DLL2
CLK5P
CLK6P
CLK7P
CLK12P
DLL3
CLK13P
CLK14P
CLK15P
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–35
Table 7–8. DLL Reference Clock Input for EP4SGX70 and EP4SGX110 Devices in the 1152-Pin FineLine BGA Package
(with 24 Transceivers)
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
DLL0
CLK12P
CLK13P
CLK14P
CLK15P
CLK0P
CLK1P
CLK2P
CLK3P
PLL_T1
PLL_L2
—
DLL1
CLK4P
CLK5P
CLK6P
CLK7P
CLK0P
CLK1P
CLK2P
CLK3P
PLL_B1
PLL_L2
—
DLL2
CLK4P
CLK5P
CLK6P
CLK7P
CLK8P
CLK9P
CLK10P
CLK11P
PLL_B1
PLL_R2
—
DLL3
CLK12P
CLK13P
CLK14P
CLK15P
CLK8P
CLK9P
CLK10P
CLK11P
PLL_T1
PLL_R2
—
DLL
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–36
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Table 7–9. DLL Reference Clock Input for EP4SGX110 Devices in the 1152-Pin FineLine BGA Package (with 16
Transceivers)
DLL
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
PLL_T1
PLL_L2
—
PLL_B1
—
—
PLL_B1
—
—
PLL_T1
PLL_R2
—
CLK12P
DLL0
CLK13P
CLK0P
CLK14P
CLK1P
CLK15P
CLK4P
DLL1
CLK5P
CLK0P
CLK6P
CLK1P
CLK7P
CLK4P
DLL2
CLK5P
CLK10P
CLK6P
CLK11P
CLK7P
CLK12P
DLL3
CLK13P
CLK10P
CLK14P
CLK11P
CLK15P
Table 7–10. DLL Reference Clock Input for EP4SGX180, EP4SGX230, EP4SGX290, EP4SGX360, and EP4SGX530 Devices
in the 1152-Pin FineLine BGA Package
DLL
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
PLL_T1
PLL_L2
—
PLL_B1
—
—
PLL_B2
—
—
PLL_T2
PLL_R2
—
CLK12P
DLL0
CLK13P
CLK0P
CLK14P
CLK1P
CLK15P
CLK4P
DLL1
CLK5P
CLK0P
CLK6P
CLK1P
CLK7P
CLK4P
DLL2
CLK5P
CLK10P
CLK6P
CLK11P
CLK7P
CLK12P
DLL3
CLK13P
CLK10P
CLK14P
CLK11P
CLK15P
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–37
Table 7–11. DLL Reference Clock Input for EP4SE360, EP4SE530, and EP4SE820 Devices in the 1152-Pin FineLine BGA
Packages
DLL
DLL0
DLL1
DLL2
DLL3
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
CLK12P
CLK0P
CLK13P
CLK1P
CLK14P
CLK2P
CLK15P
CLK3P
CLK4P
CLK0P
CLK5P
CLK1P
CLK6P
CLK2P
CLK7P
CLK3P
CLK4P
CLK8P
CLK5P
CLK9P
CLK6P
CLK10P
CLK7P
CLK11P
CLK12P
CLK8P
CLK13P
CLK9P
CLK14P
CLK10P
CLK15P
CLK11P
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
PLL_T1
PLL_L2
—
PLL_B1
PLL_L3
—
PLL_B2
PLL_R3
—
PLL_T2
PLL_R2
—
Table 7–12. DLL Reference Clock Input for EP4SE530 and EP4SE820 Devices in the 1517- and 1760-Pin FineLine BGA
Packages
DLL
DLL0
DLL1
DLL2
DLL3
February 2011
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
CLK12P
CLK0P
CLK13P
CLK1P
CLK14P
CLK2P
CLK15P
CLK3P
CLK4P
CLK0P
CLK5P
CLK1P
CLK6P
CLK2P
CLK7P
CLK3P
CLK4P
CLK8P
CLK5P
CLK9P
CLK6P
CLK10P
CLK7P
CLK11P
CLK12P
CLK8P
CLK13P
CLK9P
CLK14P
CLK10P
CLK15P
CLK11P
Altera Corporation
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
PLL_T1
PLL_L2
PLL_L1
PLL_B1
PLL_L3
PLL_L4
PLL_B2
PLL_R3
PLL_R4
PLL_T2
PLL_R2
PLL_R1
Stratix IV Device Handbook Volume 1
7–38
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Table 7–13. DLL Reference Clock Input for EP4SGX180, EP4SGX230, EP4SGX290, EP4SGX360, and EP4SGX530 Devices
in the 1517-Pin FineLine BGA Package
DLL
DLL0
DLL1
DLL2
DLL3
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
CLK12P
CLK0P
CLK13P
CLK1P
CLK14P
CLK2P
CLK15P
CLK3P
CLK4P
CLK0P
CLK5P
CLK1P
CLK6P
CLK2P
CLK7P
CLK3P
CLK4P
CLK8P
CLK5P
CLK9P
CLK6P
CLK10P
CLK7P
CLK11P
CLK12P
CLK8P
CLK13P
CLK9P
CLK14P
CLK10P
CLK15P
CLK11P
Stratix IV Device Handbook Volume 1
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
PLL_T1
PLL_L2
—
PLL_B1
PLL_L3
—
PLL_B2
PLL_R3
—
PLL_T2
PLL_R2
—
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–39
Table 7–14. DLL Reference Clock Input for EP4S40G2, EP4S40G5, EP4S100G2, and EP4S100G5 Devices in the 1517-Pin
FineLine BGA Package
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
DLL0
CLK12P
CLK13P
CLK14P
CLK15P
CLK1P
CLK3P
PLL_T1
PLL_L2
—
DLL1
CLK4P
CLK5P
CLK6P
CLK7P
CLK1P
CLK3P
PLL_B1
PLL_L3
—
DLL2
CLK4P
CLK5P
CLK6P
CLK7P
CLK8P
CLK10P
PLL_B2
PLL_R3
—
DLL3
CLK12P
CLK13P
CLK14P
CLK15P
CLK8P
CLK10P
PLL_T2
PLL_R2
—
DLL
Table 7–15. DLL Reference Clock Input for EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1760-Pin FineLine
BGA Package
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
DLL0
CLK12P
CLK13P
CLK14P
CLK15P
CLK0P
CLK1P
CLK2P
CLK3P
PLL_T1
PLL_L2
—
DLL1
CLK4P
CLK5P
CLK6P
CLK7P
CLK0P
CLK1P
CLK2P
CLK3P
PLL_B1
PLL_L3
—
DLL2
CLK4P
CLK5P
CLK6P
CLK7P
CLK8P
CLK9P
CLK10P
CLK11P
PLL_B2
PLL_R3
—
DLL3
CLK12P
CLK13P
CLK14P
CLK15P
CLK8P
CLK9P
CLK10P
CLK11P
PLL_T2
PLL_R2
—
DLL
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
7–40
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Table 7–16. DLL Reference Clock Input for EP4SGX290, EP4SGX360, and EP4SGX530 Devices in the 1932-Pin FineLine
BGA Package
DLL
DLL0
DLL1
DLL2
DLL3
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
CLK12P
CLK0P
CLK13P
CLK1P
CLK14P
CLK2P
CLK15P
CLK3P
CLK4P
CLK0P
CLK5P
CLK1P
CLK6P
CLK2P
CLK7P
CLK3P
CLK4P
CLK8P
CLK5P
CLK9P
CLK6P
CLK10P
CLK7P
CLK11P
CLK12P
CLK8P
CLK13P
CLK9P
CLK14P
CLK10P
CLK15P
CLK11P
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
PLL_T1
PLL_L2
PLL_L1
PLL_B1
PLL_L3
PLL_L4
PLL_B2
PLL_R3
PLL_R4
PLL_T2
PLL_R2
PLL_R1
Table 7–17. DLL Reference Clock Input for EP4S100G3, EP4S100G4, and EP4S100G5 Devices in the 1932-Pin FineLine
BGA Package
CLKIN
(Top/Bottom)
CLKIN
(Left/Right)
PLL
(Top/Bottom)
PLL
(Left/Right)
PLL
(Corner)
DLL0
CLK12P
CLK13P
CLK14P
CLK15P
—
PLL_T1
PLL_L2
PLL_L1
DLL1
CLK4P
CLK5P
CLK6P
CLK7P
—
PLL_B1
PLL_L3
PLL_L4
DLL2
CLK4P
CLK5P
CLK6P
CLK7P
CLK9P
CLK11P
PLL_B2
PLL_R3
PLL_R4
DLL3
CLK12P
CLK13P
CLK14P
CLK15P
CLK9P
CLK11P
PLL_T2
PLL_R2
PLL_R1
DLL
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–41
Figure 7–23 shows a simple block diagram of the DLL. The input reference clock goes
into the DLL to a chain of up to 16 delay elements. The phase comparator compares
the signal coming out of the end of the delay chain block to the input reference clock.
The phase comparator then issues the upndn signal to the Gray-code counter. This
signal increments or decrements a six-bit delay setting (DQS delay settings) that
increases or decreases the delay through the delay element chain to bring the input
reference clock and the signals coming out of the delay element chain in phase.
Figure 7–23. Simplified Diagram of the DQS Phase-Shift Circuitry (Note 1)
addnsub
Phase offset settings
from the logic array
( offset [5:0] )
6
offsetdelayctrlin [5:0]
DLL
aload
Input Reference
Clock (2)
offsetdelayctrlout [5:0]
Phase
Comparator
upndninclkena
6
Phase
Offset
Control
B
offsetdelayctrlout [5:0]
offsetdelayctrlin [5:0]
6
delayctrlout [5:0]
6
6
Phase offset
settings to DQS pins
on top or bottom edge (3)
( offsetctrlout [5:0] )
addnsub
Phase offset settings
from the logic array ( offset [5:0] )
Up/Down
Counter
Delay Chains
6
(dll_offset_ctrl_a)
upndnin
clk
Phase
Offset
Control
A
6
(dll_offset_ctrl_b)
Phase offset
settings to DQS pin
on left or right edge (3)
( offsetctrlout [5:0] )
DQS Delay
Settings (4)
dqsupdate
Notes to Figure 7–23:
(1) All features of the DQS phase-shift circuitry are accessible from the ALTMEMPHY megafunction in the Quartus II software.
(2) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. For more information, refer
to Table 7–5 on page 7–33 through Table 7–17 on page 7–40.
(3) Phase offset settings can only go to the DQS logic blocks.
(4) DQS delay settings can go to the logic array, DQS logic block, and leveling circuitry.
1
In the Quartus II assignment, phase offset control block ‘A’ is designated as
DLLOFFSETCTRL_<coordinate x>_<coordinate y>_N1 and phase offset control block
‘B’ is designated as DLLOFFSETCTRL_<coordinate x>_<coordinate y>_N2.
You can reset the DLL from either the logic array or a user I/O pin. Each time the DLL
is reset, you must wait for 1,280 clock cycles for the DLL to lock before you can
capture the data properly.
Depending on the DLL frequency mode, the DLL can shift the incoming DQS signals
by 0°, 22.5°, 30°, 36°, 45°, 60°, 67.5°, 72°, 90°, 108°, 120°, 135°, 144°, 180°, or 240°. The
shifted DQS signal is then used as the clock for the DQ IOE input registers.
All DQS/CQ and CQn pins, referenced to the same DLL, can have their input signal
phase shifted by a different degree amount but all must be referenced at one
particular frequency. For example, you can have a 90° phase shift on DQS1T and a 60°
phase shift on DQS2T, referenced from a 200-MHz clock. Not all phase-shift
combinations are supported. The phase shifts on the DQS pins referenced by the same
DLL must all be a multiple of 22.5° (up to 90°), 30° (up to 120°), 36° (up to 144°), 45°
(up to 180°), or 60° (up to 240°).
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Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
There are eight different frequency modes for the Stratix IV DLL, as listed in
Table 7–18. Each frequency mode provides different phase shift selections. In
frequency mode 0, 1, 2, and 3, the 6-bit DQS delay settings vary with PVT to
implement the phase-shift delay. In frequency modes 4, 5, 6, and 7, only 5 bits of the
DQS delay settings vary with PVT to implement the phase-shift delay; the most
significant bit of the DQS delay setting is set to 0.
Table 7–18. Stratix IV DLL Frequency Modes
Frequency Mode
Available Phase Shift
Number of Delay Chains
0
22.5, 45, 67.5, 90
16
1
30, 60, 90, 120
12
2
36, 72, 108, 144
10
3
45, 90, 135, 180
8
4
30, 60, 90, 120
12
5
36, 72, 108, 144
10
6
45, 90, 135, 180
8
7
60, 120, 180, 240
6
f For the frequency range of each mode, refer to the DC and Switching Characteristics for
Stratix IV Devices chapter.
For 0° shift, the DQS/CQ signal bypasses both the DLL and DQS logic blocks. The
Quartus II software automatically sets the DQ input delay chains so that the skew
between the DQ and DQS/CQ pin at the DQ IOE registers is negligible when 0° shift
is implemented. You can feed the DQS delay settings to the DQS logic block and logic
array.
The shifted DQS/CQ signal goes to the DQS bus to clock the IOE input registers of the
DQ pins. The signal can also go into the logic array for resynchronization if you are
not using IOE resynchronization registers. The shifted CQn signal can only go to the
negative-edge input register in the DQ IOE and is only used for QDR II+ and QDR II
SRAM interfaces.
Phase Offset Control
Each DLL has two phase-offset modules and can provide two separate DQS delay
settings with independent offsets, one for the top and bottom I/O bank and one for
the left and right I/O bank, so you can fine-tune the DQS phase-shift settings between
two different sides of the device. Even though you have independent phase offset
control, the frequency of the interface using the same DLL must be the same. Use the
phase offset control module for making small shifts to the input signal and use the
DQS phase-shift circuitry for larger signal shifts. For example, if the DLL only offers a
multiple of 30° phase shift, but your interface needs a 67.5° phase shift on the DQS
signal, you can use two delay chains in the DQS logic blocks to give you 60° phase
shift and use the phase offset control feature to implement the extra 7.5° phase shift.
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Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–43
You can use either a static phase offset or a dynamic phase offset to implement the
additional phase shift. The available additional phase shift is implemented in 2’s:
complement in Gray-code between settings –64 to +63 for frequency mode 0, 1, 2, and
3, and between settings –32 to +31 for frequency modes 4, 5, 6, and 7. An additional bit
indicates whether the setting has a positive or negative value. The settings are linear,
each phase offset setting adds a delay amount specified in the DC and Switching
Characteristics for Stratix IV Devices chapter. The DQS phase shift is the sum of the DLL
delay settings and the user-selected phase offset settings whose top setting is 64 for
frequency modes 0, 1, 2, and 3; and 32 for frequency modes 4, 5, 6, and 7, so the actual
physical offset setting range is 64 or 32 subtracted by the DQS delay settings from the
DLL.
1
When using this feature, you need to monitor the DQS delay settings to know how
many offsets you can add and subtract in the system. Note that the DQS delay settings
output by the DLL are also Gray coded.
For example, if the DLL determines that DQS delay settings of 28 is needed to achieve
a 30° phase shift in DLL frequency mode 1, you can subtract up to 28 phase offset
settings and you can add up to 35 phase offset settings to achieve the optimal delay
that you need. However, if the same DQS delay settings of 28 is needed to achieve 30°
phase shift in DLL frequency mode 4, you can still subtract up to 28 phase offset
settings, but you can only add up to 3 phase offset settings before the DQS delay
settings reach their maximum settings because DLL frequency mode 4 only uses 5-bit
DLL delay settings.
f For more information about the value for each step, refer to the DC and Switching
Characteristics for Stratix IV Devices chapter.
When using static phase offset, you can specify the phase offset amount in the
ALTMEMPHY megafunction as a positive number for addition or a negative number
for subtraction. You can also have a dynamic phase offset that is always added to,
subtracted from, or both added to and subtracted from the DLL phase shift. When
you always add or subtract, you can dynamically input the phase offset amount into
the dll_offset[5..0] port. When you want to both add and subtract dynamically,
you control the addnsub signal in addition to the dll_offset[5..0] signals.
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Stratix IV Device Handbook Volume 1
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Stratix IV Device Handbook Volume 1
DQS Logic Block
Each DQS/CQ and CQn pin is connected to a separate DQS logic block, which consists of the DQS delay chains, update enable
circuitry, and DQS postamble circuitry, as shown in Figure 7–24.
Figure 7–24. Stratix IV DQS Logic Block
DQS Delay Chain
DQS Enable
dqsenable (2)
1xx
000 dqsbusout
001
010
011
Bypass
dqsin
DQS bus
6
6
DQS Enable Control
0
1
0
1
6
D
Input Reference
Clock (1)
Q
dqsupdateen
Update
Enable
Circuitry
phasectrlin
6
<dqs_ctrl_latches_enable>
6
delayctrlin
Resynchronization
Clock
clk
4
phaseinvertctrl
0111
0110
0101
0100
0011
0010
0001
0000
Postamble
Enable
0
1
<level_dqs_enable>
postamble control clock
0
0 dqsenableout
0 1
1
1
dqsenablein
enaphasetransferreg
<delay_dqs_enable_by_half_cycle>
February 2011
Notes to Figure 7–24:
(1) The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. For more information, refer to Table 7–5 on page 7–33 through Table 7–17 on page 7–40.
(2) The dqsenable signal can also come from the Stratix IV FPGA fabric.
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
6
offsetctrlin [5:0]
6
Phase offset
1
D Q
settings from the
0
DQS phase-shift
circuitry
<dqs_offsetctrl_enable>
6
DQS delay
settings from the delayctrlin [5:0]
DQS phase-shift
circuitry
dqsbusout
phasectrlin[2:0]
dqsin
DQS/CQ or
CQn Pin
6
PRE
Q D
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Stratix IV External Memory Interface Features
7–45
DQS Delay Chain
DQS delay chains consist of a set of variable delay elements to allow the input
DQS/CQ and CQn signals to be shifted by the amount specified by the DQS
phase-shift circuitry or the logic array. There are four delay elements in the DQS delay
chain; the first delay chain closest to the DQS/CQ pin can be shifted either by the
DQS delay settings or by the sum of the DQS delay setting and the phase-offset
setting. The number of delay chains required is transparent because the
ALTMEMPHY megafunction automatically sets it when you choose the operating
frequency. The DQS delay settings can come from the DQS phase-shift circuitry on
either end of the I/O banks or from the logic array.
The delay elements in the DQS logic block have the same characteristics as the delay
elements in the DLL. When the DLL is not used to control the DQS delay chains, you
can input your own Gray-coded 6-bit or 5-bit settings using the
dqs_delayctrlin[5..0] signals available in the ALTMEMPHY megafunction. These
settings control 1, 2, 3, or all 4 delay elements in the DQS delay chains. The
ALTMEMPHY megafunction can also dynamically choose the number of DQS delay
chains needed for the system. The amount of delay is equal to the sum of the delay
element’s intrinsic delay and the product of the number of delay steps and the value
of the delay steps.
You can also bypass the DQS delay chain to achieve a 0° phase shift.
Update Enable Circuitry
Both the DQS delay settings and the phase-offset settings pass through a register
before going into the DQS delay chains. The registers are controlled by the update
enable circuitry to allow enough time for any changes in the DQS delay setting bits to
arrive at all the delay elements. This allows them to be adjusted at the same time. The
update enable circuitry enables the registers to allow enough time for the DQS delay
settings to travel from the DQS phase-shift circuitry or core logic to all the DQS logic
blocks before the next change. It uses the input reference clock or a user clock from the
core to generate the update enable output. The ALTMEMPHY megafunction uses this
circuit by default. Figure 7–25 shows an example waveform of the update enable
circuitry output.
Figure 7–25. DQS Update Enable Waveform
DLL Counter Update
(Every 8 cycles)
DLL Counter Update
(Every 8 cycles)
System Clock
DQS Delay Settings
(Updated every 8 cycles)
6 bit
Update Enable
Circuitry Output
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Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
DQS Postamble Circuitry
For external memory interfaces that use a bidirectional read strobe such as in DDR3,
DDR2, and DDR SDRAM, the DQS signal is low before going to or coming from a
high-impedance state. The state in which DQS is low, just after a high-impedance
state, is called the preamble; the state in which DQS is low, just before it returns to a
high-impedance state, is called the postamble. There are preamble and postamble
specifications for both read and write operations in DDR3, DDR2, and DDR SDRAM.
The DQS postamble circuitry ensures that data is not lost if there is noise on the DQS
line during the end of a read operation that occurs while DQS is in a postamble state.
Stratix IV devices have dedicated postamble registers that you can control to ground
the shifted DQS signal used to clock the DQ input registers at the end of a read
operation. This ensures that any glitches on the DQS input signals during the end of a
read operation that occurs while DQS is in a postamble state do not affect the DQ IOE
registers.
In addition to the dedicated postamble register, Stratix IV devices also have an HDR
block inside the postamble enable circuitry. Use these registers if the controller is
running at half the frequency of the I/Os.
Using the HDR block as the first stage capture register in the postamble enable
circuitry block is optional. The HDR block is clocked by the half-rate
resynchronization clock, which is the output of the I/O clock divider circuit (shown in
Figure 7–31 on page 7–50). There is an AND gate after the postamble register outputs
that is used to avoid postamble glitches from a previous read burst on a
non-consecutive read burst. This scheme allows a half-a-clock cycle latency for
dqsenable assertion and zero latency for dqsenable de-assertion, as shown in
Figure 7–26.
Figure 7–26. Avoiding Glitch on a Non-Consecutive Read Burst Waveform
Postamble glitch
Postamble
Preamble
DQS
Postamble Enable
dqsenable
Delayed by
1/2T logic
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Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–47
Leveling Circuitry
DDR3 SDRAM unbuffered modules use a fly-by clock distribution topology for better
signal integrity. This means that the CK/CK# signals arrive at each DDR3 SDRAM
device in the module at different times. The difference in arrival time between the first
DDR3 SDRAM device and the last device on the module can be as long as 1.6 ns.
Figure 7–27 shows the clock topology in DDR3 SDRAM unbuffered modules.
Figure 7–27. DDR3 SDRAM Unbuffered Module Clock Topology
DQS/DQ
DQS/DQ
DQS/DQ
DQS/DQ CK/CK# DQS/DQ
DQS/DQ
DQS/DQ
DQS/DQ
Stratix IV Device
Because the data and read strobe signals are still point-to-point, take special care to
ensure that the timing relationship between the CK/CK# and DQS signals (tDQSS,
tDSS, and tDSH) during a write is met at every device on the modules. Furthermore,
read data coming back into the FPGA from the memory is also staggered in a similar
way.
Stratix IV FPGAs have leveling circuitry to address these two situations. There is one
leveling circuitry per I/O sub-bank (for example, I/O sub-bank 1A, 1B, and 1C each
has one leveling circuitry). These delay chains are PVT-compensated by the same DQS
delay settings as the DLL and DQS delay chains.
For frequencies equal to and above 400 MHz, the DLL uses eight delay chains, such
that each delay chain generates a 45° delay. The generated clock phases are
distributed to every DQS logic block that is available in the I/O sub-bank. The delay
chain taps then feeds a multiplexer controlled by the ALTMEMPHY megafunction to
select which clock phases are to be used for that ×4 or × 8 DQS group. Each group can
use a different tap output from the read-leveling and write-leveling delay chains to
compensate for the different CK/CK# delay going into each device on the module.
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Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Figure 7–28 and Figure 7–29 show the Stratix IV write- and read-leveling circuitry.
Figure 7–28. Stratix IV Write-Leveling Delay Chains and Multiplexers (Note 1)
Write clk
(-900)
Write-Leveled DQS Clock
Write-Leveled DQ Clock
Note to Figure 7–28:
(1) There is one leveling delay chain per I/O sub-bank (for example, I/O sub-banks 1A, 1B, and 1C). You can only have
one memory interface in each I/O sub-bank when you use the leveling delay chain.
Figure 7–29. Stratix IV Read-Leveling Delay Chains and Multiplexers (Note 1)
I/O Clock Divider (2)
use_masterin
slaveout
masterin
DQS
delayctrlin
1
0
Half-Rate
Resynchronization Clock
DFF
1
0
clkout
Half-Rate Source
Synchronous Clock
phaseselect
phasectrlin
6
4
phaseinvertctrl
Resynchronization Clock
(resync_clk_2x)
0111
0110
0101
0100
0011
0010
0001
0000
0
1
Read-Leveled Resynchronization Clock
Notes to Figure 7–29:
(1) There is one leveling delay chain per I/O sub-bank (for example, I/O sub-banks 1A, 1B, and 1C). You can only have one memory interface in each
I/O sub-bank when you use the leveling delay chain.
(2) Each divider feeds up to six pins (from a × 4 DQS group) in the device. To feed wider DQS groups, you must chain multiple clock dividers together
by feeding the slaveout output of one divider to the masterin input of the neighboring pins’ divider.
The –90° write clock of the ALTMEMPHY megafunction feeds the write-leveling
circuitry to produce the clock to generate the DQS and DQ signals. During
initialization, the ALTMEMPHY megafunction picks the correct write-leveled clock
for the DQS and DQ clocks for each DQS/DQ group after sweeping all the available
clocks in the write calibration process. The DQ clock output is –90° phase-shifted
compared to the DQS clock output.
Similarly, the resynchronization clock feeds the read-leveling circuitry to produce the
optimal resynchronization and postamble clock for each DQS/DQ group in the
calibration process. The resynchronization and postamble clocks can use different
clock outputs from the leveling circuitry. The output from the read-leveling circuitry
can also generate the half-rate resynchronization clock that goes to the FPGA fabric.
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Stratix IV External Memory Interface Features
1
7–49
The ALTMEMPHY megafunction dynamically calibrates the alignment for read- and
write-leveling during the initialization process.
f For more information about the ALTMEMPHY megafunction, refer to the External
Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide.
Dynamic On-Chip Termination Control
Figure 7–30 shows the dynamic OCT control block. The block includes all the registers
needed to dynamically turn on OCT RT during a read and turn OCT RT off during a
write.
f For more information about dynamic on-chip termination control, refer to the I/O
Features in Stratix IV Devices chapter.
Figure 7–30. Stratix IV Dynamic OCT Control Block
OCT Control
OCT Enable
2
DFF
OCT HalfRate Clock
HDR
Block
DFF
Resynchronization
Registers
Write
Clock (1)
OCT Control Path
Note to Figure 7–30:
(1) The write clock comes from either the PLL or the write-leveling delay chain.
February 2011
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Stratix IV Device Handbook Volume 1
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Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
I/O Element Registers
The IOE registers are expanded to allow source-synchronous systems to have faster
register-to-register transfers and resynchronization. Both top and bottom and left and
right IOEs have the same capability. Left and right IOEs have extra features to support
LVDS data transfer.
Figure 7–31 shows the registers available in the Stratix IV input path. The input path
consists of the DDR input registers, resynchronization registers, and HDR block. You
can bypass each block of the input path.
Figure 7–31. Stratix IV IOE Input Registers (Note 1)
DQ
Double Data Rate Input Registers
D
Q
DFF
Input Reg AI
D
DQS/CQ (3), (9)
Differential
Input
Buffer
DQSn (9)
CQn (4)
Q
neg_reg_out
DFF
Input Reg BI
0
1
D
Q
Half Data Rate Registers
DFF
Input Reg C I
directin
Alignment & Synchronization Registers
D
Q
D
0
1
Q
datain [0]
D
Q
dataout
D
DFF
DFF
0
D
0
1
1
Q
To Core
dataout [0]
(7)
DFF
Q
DFF
DFF
D
enaphasetransferreg
enainputcycledelay
<bypass_output_register>(10)
D
Q
1
D
DFF
Q
0
1
DFF
dataout
D
DFF
Resynchronization Clock
(resync_clk_2x) (5)
DFF
1
Q
DFF
D
Q
DFF
I/O Clock
Divider (6)
DFF
Q
(2)
dataoutbypass
(8)
Q
0
D
0
Q
D
DFF
datain [1]
D
Q
To Core
dataout[2]
(7)
D
To Core
dataout [1]
(7)
To Core
dataout [3]
(7)
Q
DFF
Half-Rate Resynchronization Clock (resync_clk_1x)
to core (7)
Notes to Figure 7–31:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
You can bypass each register block in this path.
This is the 0-phase resynchronization clock (from the read-leveling delay chain).
The input clock can be from the DQS logic block (whether the postamble circuitry is bypassed or not) or from a global clock line.
This input clock comes from the CQn logic block.
This resynchronization clock comes from a PLL through the clock network (resync_ck_2x).
The I/O clock divider resides adjacent to the DQS logic block. In addition to the PLL and read-leveled resync clock, the I/O clock divider can also
be fed by the DQS bus or CQn bus.
The half-rate data and clock signals feed into a dual-port RAM in the FPGA core.
You can dynamically change the dataoutbypass signal after configuration to select either the directin input or the output from the half data
rate register to feed dataout.
The DQS and DQSn signals must be inverted for DDR, DDR2, and DDR3 interfaces. When using Altera’s memory interface IPs, the DQS and DQSn
signals are automatically inverted.
The bypass_output_register option allows you to select either the output from the second mux or the output of the fourth alignment/
synchronization register to feed dataout.
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Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–51
There are three registers in the DDR input registers block. Two registers capture data
on the positive and negative edges of the clock, while the third register aligns the
captured data. You can choose to use the same clock for the positive edge and
negative edge registers, or two complementary clocks (DQS/CQ for the positive-edge
register and DQSn/CQn for the negative-edge register). The third register that aligns
the captured data uses the same clock as the positive edge registers.
The resynchronization registers consist of up to three levels of registers to
resynchronize the data to the system clock domain. These registers are clocked by the
resynchronization clock that is either generated by the PLL or the read-leveling delay
chain. The outputs of the resynchronization registers can go straight to the core or to
the HDR blocks, which are clocked by the divided-down resynchronization clock.
For more information about the read-leveling delay chain, refer to “Leveling
Circuitry” on page 7–47.
Figure 7–32 shows the registers available in the Stratix IV output and output-enable
paths. The path is divided into the HDR block, resynchronization registers, and
output and output-enable registers. The device can bypass each block of the output
and output-enable path.
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Stratix IV Device Handbook Volume 1
7–52
Stratix IV Device Handbook Volume 1
Figure 7–32. Stratix IV IOE Output and Output-Enable Path Registers (Note 1)
Half Data Rate to Single Data Rate Output-Enable Registers
From Core (2)
Alignment Registers (4)
D
Q
Double Data Rate Output-Enable Registers
DFF
DFF
From Core (2)
0
1
D
Q
D
DFF
D
Q
D
D
D
Q
Q
Q
DFF
Q
OE Reg A OE
DFF
OR2
1
DFF
DFF
0
DFF
D
Half Data Rate to Single Data Rate Output Registers
Q
Alignment Registers (4)
OE Reg B OE
From Core
(wdata2) (2)
D
Q
Double Data Rate Output Registers
DFF
DFF
0
D
Q
D
Q
D
1
From Core
(wdata0) (2)
D
DFF
D
Q
D
Q
Q
Q
TRI
DFF
Output Reg Ao
DFF
DFF
D
Output Reg Bo
0
1
D
Q
DFF
D
Q
Q
DFF
Q
DFF
From Core
(wdata1) (2)
D
Q
D
D
Q
Q
DFF
DFF
DFF
Half-Rate Clock (3)
February 2011
Alignment
Clock (3)
Write
Clock (5)
Notes to Figure 7–32:
Altera Corporation
(1)
(2)
(3)
(4)
(5)
You can bypass each register block of the output and output-enable paths.
Data coming from the FPGA core are at half the frequency of the memory interface clock frequency in half-rate mode.
The half-rate clock comes from the PLL, while the alignment clock comes from the write-leveling delay chains.
These registers are only used in DDR3 SDRAM interfaces for write-leveling purposes.
The write clock can come from either the PLL or from the write-leveling delay chain. The DQ write clock and DQS write clock have a 90° offset between them.
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
D
DQ or DQS
DFF
DFF
From Core
(wdata3) (2)
1
0
Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–53
The output path is designed to route combinatorial or registered SDR outputs and
full-rate or half-rate DDR outputs from the FPGA core. Half-rate data is converted to
full-rate using the HDR block, clocked by the half-rate clock from the PLL. The
resynchronization registers are also clocked by the same 0° system clock, except in the
DDR3 SDRAM interface. In DDR3 SDRAM interfaces, the leveling registers are
clocked by the write-leveling clock.
For more information about the write-leveling delay chain, refer to “Leveling
Circuitry” on page 7–47.
The output-enable path has a structure similar to the output path. You can have a
combinatorial or registered output in SDR applications and you can use half-rate or
full-rate operation in DDR applications. Also, the ouput-enable path’s
resynchronization registers have a structure similar to the output path registers,
ensuring that the output-enable path goes through the same delay and latency as the
output path.
Delay Chain
Stratix IV devices have run-time adjustable delay chains in the I/O blocks and the
DQS logic blocks. You can control the delay chain setting through the I/O or the DQS
configuration block output. Figure 7–33 shows the delay chain ports.
Figure 7–33. Delay Chain
delayctrlin [3..0]
<use finedelayctrlin>
finedelayctrlin
datain
Δt
0
dataout
Δt
1
Every I/O block contains the following:
February 2011
■
Two delay chains in a series between the output registers and the output buffer
■
One delay chain between the input buffer and the input register
■
Two delay chains between the output enable and the output buffer
■
Two delay chains between the OCT RT enable control register and the output
buffer
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Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
Figure 7–34 shows the delay chains in an I/O block.
Figure 7–34. Delay Chains in an I/O Block
rtena
oe
octdelaysetting1 (only)
D5 OCT
Delay
Chain
D5 OutputEnable Delay
Chain
octdelaysetting2 (only)
D6 OCT
Delay
Chain
D6 OutputEnable Delay
Chain
(outputdelaysetting1 +
outputfinedelaysetting1)
(outputdelaysetting2 +
outputfinedelaysetting2)
D5 Delay
Delay
Chain
D6 Delay
Delay
Chain
0
1
(outputdelaysetting2 + outputfinedelaysetting2) or
(outputonlydelaysetting2 + outputonlyfinedelaysetting2)
D1 Delay
Delay Chain
(padtoinputregisterdelaysetting +
padtoinputregisterfinedelaysetting)
Each DQS logic block contains a delay chain after the dqsbusout output and another
delay chain before the dqsenable input. Figure 7–35 shows the delay chains in the
DQS input path.
Figure 7–35. Delay Chains in the DQS Input Path
(dqsbusoutdelaysetting +
dqsbusoutfinedelaysetting)
DQS
DQS
Delay
Chain
DQS
Enable
D4 Delay
Chain
dqsin
dqsbusout
dqsenable
(dqsenabledelaysetting +
dqsenablefinedelaysetting)
T11 Delay
Chain
DQS
Enable
Control
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Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
7–55
I/O Configuration Block and DQS Configuration Block
The I/O configuration block and the DQS configuration block are shift registers that
you can use to dynamically change the settings of various device configuration bits.
The shift registers power-up low. Every I/O pin contains one I/O configuration
register, while every DQS pin contains one DQS configuration block in addition to the
I/O configuration register. Figure 7–36 shows the I/O configuration block and the
DQS configuration block circuitry.
Figure 7–36. I/O Configuration Block and DQS Configuration Block
bit 0
bit 1
MSB
bit 2
datain
update
ena
clk
Table 7–19 lists the I/O configuration block bit sequence.
Table 7–19. I/O Configuration Block Bit Sequence
Bit
Bit Name
0..3
outputdelaysetting1[0..3]
4..6
outputdelaysetting2[0..2]
7..10
padtoinputregisterdelaysetting[0..3]
Table 7–20 lists the DQS configuration block bit sequence.
Table 7–20. DQS Configuration Block Bit Sequence (Part 1 of 2)
February 2011
Altera Corporation
Bit
Bit Name
0..3
dqsbusoutdelaysetting[0..3]
4..6
dqsinputphasesetting[0..2]
7..10
dqsenablectrlphasesetting[0..3]
11..14
dqsoutputphasesetting[0..3]
15..18
dqoutputphasesetting[0..3]
19..22
resyncinputphasesetting[0..3]
23
dividerphasesetting
24
enaoctcycledelaysetting
25
enainputcycledelaysetting
26
enaoutputcycledelaysetting
27..29
dqsenabledelaysetting[0..2]
30..33
octdelaysetting1[0..3]
Stratix IV Device Handbook Volume 1
7–56
Chapter 7: External Memory Interfaces in Stratix IV Devices
Document Revision History
Table 7–20. DQS Configuration Block Bit Sequence (Part 2 of 2)
Bit
Bit Name
34..36
octdelaysetting2[0..2]
37
enadataoutbypass
38
enadqsenablephasetransferreg
39
enaoctphasetransferreg
40
enaoutputphasetransferreg
41
enainputphasetransferreg
42
resyncinputphaseinvert
43
dqsenablectrlphaseinvert
44
dqoutputphaseinvert
45
dqsoutputphaseinvert
Document Revision History
Table 7–21 lists the revision history for this chapter.
Table 7–21. Document Revision History (Part 1 of 2)
Date
February 2011
March 2010
Version
3.2
3.1
Stratix IV Device Handbook Volume 1
Changes
■
Updated Table 7–5, Table 7–6, Table 7–11, Table 7–19, and Table 7–20.
■
Added Table 7–12.
■
Updated Figure 7–36.
■
Removed Table 7-1 and Table 7-6.
■
Applied new template.
■
Minor text edits.
■
Updated Figure 7–8, Figure 7–11, Figure 7–23, Figure 7–24, Figure 7–29, Figure 7–31,
and Figure 7–36.
■
Added Figure 7–9 and Figure 7–12.
■
Added Table 7–7.
■
Updated Table 7–1, Table 7–2, Table 7–3, Table 7–4, Table 7–6, Table 7–8 and Table 7–19.
■
Added note to the “Memory Interfaces Pin Support” section.
■
Changed “DLL1 through DLL4” to “DLL0 through DLL3” throughout.
■
Added frequency mode 7 throughout.
■
Minor text edits.
February 2011
Altera Corporation
Chapter 7: External Memory Interfaces in Stratix IV Devices
Document Revision History
7–57
Table 7–21. Document Revision History (Part 2 of 2)
Date
Version
November 2009
June 2009
2.3
April 2009
2.2
March 2009
2.1
November 2008
May 2008
February 2011
3.0
2.0
1.0
Altera Corporation
Changes
■
Updated the “Memory Interfaces Pin Support” and “Combining ×16/×18 DQS/DQ Groups
for a ×36 QDR II+/QDR II SRAM Interface” sections.
■
Updated Table 7–1, Table 7–2, Table 7–7, and Table 7–12.
■
Updated Figure 7–3, Figure 7–4, Figure 7–5, Figure 7–6, Figure 7–7, Figure 7–8,
Figure 7–9, Figure 7–10, Figure 7–11, Figure 7–13, Figure 7–14, Figure 7–15, and
Figure 7–16.
■
Added Figure 7–12 and Figure 7–17.
■
Added Table 7–14, Table 7–17, Table 7–19, and Table 7–20.
■
Added “Delay Chain” and “I/O Configuration Block and DQS Configuration Block”
sections.
■
Removed Figure 7-8 and Figure 7-12.
■
Removed Table 7-1, Table 7-2, and Table 7-24.
■
Minor text edits.
■
Updated “Overview” and “Leveling Circuitry”.
■
Updated Figure 7–26 and Figure 7–27.
■
Updated Table 7–3.
■
Added introductory sentences to improve search ability.
■
Removed the Conclusion section.
■
Updated Table 7–5, Table 7–6, Table 7–15, and Table 7–17
■
Removed Figure 7-12, Figure 7-13, and Figure 7-20
■
Updated Table 7–1, Table 7–5, Table 7–8, Table 7–12, Table 7–13, Table 7–14,
Table 7–15, and Table 7–17.
■
Replaced Table 7–6.
■
Added Table 7–11 and Table 7–16.
■
Updated Figure 7–3, Figure 7–6, Figure 7–8, Figure 7–9, and Figure 7–11.
■
Added Figure 7–7, Figure 7–11, Figure 7–12, Figure 7–13, and Figure 7–20.
■
Updated “Combining ×16/×18 DQS/DQ Groups for ×36 QDR II+/QDR II SRAM Interface”.
■
Updated “Rules to Combine Groups”.
■
Removed “Referenced Documents” section.
■
Updated Table 7–1, Table 7–2, Table 7–3, Table 7–4, Table 7–5, and Table 7–6.
■
Added Table 7–7.
■
Updated Figure 7–1 and Figure 7–19.
■
Updated “Combining ×16/×18 DQS/DQ groups for ×36 QDR II+/QDR II SRAM Interface”
on page 7–26.
■
Updated “Rules to Combine Groups” on page 7–27.
■
Updated “DQS Phase-Shift Circuitry” on page 7–29.
■
Updated Table 7–9, Table 7–10, Table 7–11, Table 7–13, Table 7–13, Table 7–14,
Table 7–15, Table 7–15, Table 7–16, and Table 7–18.
■
Updated Figure 7–30 and Figure 7–31.
■
Made minor editorial changes.
Initial release.
Stratix IV Device Handbook Volume 1
7–58
Stratix IV Device Handbook Volume 1
Chapter 7: External Memory Interfaces in Stratix IV Devices
Document Revision History
February 2011
Altera Corporation
8. High-Speed Differential I/O Interfaces
and DPA in Stratix IV Devices
February 2011
SIV51008-3.2
SIV51008-3.2
This chapter describes the significant advantages of the high-speed differential I/O
interfaces and the dynamic phase aligner (DPA) over single-ended I/Os and their
contribution to the overall system bandwidth achievable with Stratix® IV FPGAs. All
references to Stratix IV devices in this chapter apply to Stratix IV E, GT, and GX
devices.
The Stratix IV device family consists of the Stratix IV E (Enhanced) devices without
high-speed clock data recovery (CDR) based transceivers, Stratix IV GT devices with
up to 48 CDR-based transceivers running up to 11.3 Gbps, and Stratix IV GX devices
with up to 48 CDR-based transceivers running up to 8.5 Gbps.
The following sections describe the Stratix IV high-speed differential I/O interfaces
and DPA:
■
“Locations of the I/O Banks” on page 8–3
■
“LVDS Channels” on page 8–4
■
“LVDS SERDES” on page 8–8
■
“ALTLVDS Port List” on page 8–9
■
“Differential Transmitter” on page 8–11
■
“Differential Receiver” on page 8–17
■
“LVDS Interface with the Use External PLL Option Enabled” on page 8–26
■
“Left and Right PLLs (PLL_Lx and PLL_Rx)” on page 8–29
■
“Stratix IV Clocking” on page 8–30
■
“Source-Synchronous Timing Budget” on page 8–31
■
“Differential Pin Placement Guidelines” on page 8–38
Overview
All Stratix IV E, GX, and GT devices have built-in serializer/deserializer (SERDES)
circuitry that supports high-speed LVDS interfaces at data rates of up to 1.6 Gbps.
SERDES circuitry is configurable to support source-synchronous communication
protocols such as Utopia, Rapid I/O, XSBI, small form factor interface (SFI), serial
peripheral interface (SPI), and asynchronous protocols such as SGMII and Gigabit
Ethernet.
The Stratix IV device family has the following dedicated circuitry for high-speed
differential I/O support:
■
Differential I/O buffer
■
Transmitter serializer
■
Receiver deserializer
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off.
and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but
reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
Stratix IV Device Handbook Volume 1
February 2011
Subscribe
8–2
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Overview
■
Data realignment
■
DPA
■
Synchronizer (FIFO buffer)
■
Phase-locked loops (PLLs) (located on left and right sides of the device)
For high-speed differential interfaces, the Stratix IV device family supports the
following differential I/O standards:
■
LVDS
■
Mini-LVDS
■
Reduced swing differential signaling (RSDS)
In the Stratix IV device family, I/Os are divided into row and column I/Os. Figure 8–1
shows I/O bank support for the Stratix IV device family. The row I/Os provide
dedicated SERDES circuitry.
Figure 8–1. I/O Bank Support in the Stratix IV Device Family (Note 1), (2), (3), (4)
LVDS I/Os
Row I/Os with
Dedicated
SERDES Circuitry (3), (4)
LVDS Interface
with 'Use External PLL'
Option Enabled
Column I/Os (1), (2)
LVDS Interface
with 'Use External PLL'
Option Disabled
Notes to Figure 8–1:
(1) Column input buffers are true LVDS buffers, but do not support 100-Ω differential on-chip termination.
(2) Column output buffers are single ended and need external termination schemes to support LVDS, mini-LVDS, and RSDS standards. For more
information, refer to the I/O Features in Stratix IV Devices chapter.
(3) Row input buffers are true LVDS buffers and support 100-Ω differential on-chip termination.
(4) Row output buffers are true LVDS buffers.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Locations of the I/O Banks
8–3
The ALTLVDS transmitter and receiver requires various clock and load enable signals
from a left or right PLL. The Quartus ® II software provides the following two choices
when configuring the LVDS SERDES circuitry when using the PLL:
1
■
LVDS interface with the Use External PLL option enabled—You control the PLL
settings, such as dynamically reconfiguring the PLL to support different data
rates, dynamic phase shift, and so on. You must enable the Use External PLL
option in the ALTLVDS megafunction, using the ALTLVDS MegaWizard™ Plug-in
Manager software. You also must instantiate an ALTPLL megafunction to generate
the various clocks and load enable signals. For more information, refer to “LVDS
Interface with the Use External PLL Option Enabled” on page 8–26.
■
LVDS interface with the Use External PLL option disabled—The Quartus II
software configures the PLL settings automatically. The software is also
responsible for generating the various clock and load enable signals based on the
input reference clock and data rate selected.
Both choices target the same physical PLL; the only difference is the additional
flexibility provided when an LVDS interface has the Use External PLL option
enabled.
Locations of the I/O Banks
Stratix IV I/Os are divided into 16 to 24 I/O banks. The dedicated circuitry that
supports high-speed differential I/Os is located in banks in the right and left side of
the device. Figure 8–2 shows a high-level chip overview of the Stratix IV E device.
Figure 8–2. High-Speed Differential I/Os with DPA Locations in Stratix IV E Devices
General Purpose
I/O and Memory
Interface
PLL
PLL
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
PLL
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
PLL
General Purpose
I/O and Memory
Interface
February 2011
Altera Corporation
PLL
PLL
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
PLL
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
PLL
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
PLL
General Purpose
I/O and Memory
Interface
PLL
PLL
PLL
General Purpose
I/O and Memory
Interface
Stratix IV Device Handbook Volume 1
8–4
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
LVDS Channels
Figure 8–3 shows a high-level chip overview of the Stratix IV GT and GX devices.
Figure 8–3. High-Speed Differential I/Os with DPA Locations in Stratix IV GT and GX Devices
PLL
PLL
General Purpose
I/O and Memory
Interface
PLL
PCI Express
Hard IP Block
PLL
PLL
PLL
PCI Express
Hard IP Block
PLL
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
PLL
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
PLL
General Purpose
I/O and
High-Speed
LVDS I/O with
DPA and Soft CDR
PCI Express
Hard IP Block
PLL
General Purpose
I/O and Memory
Interface
Transceiver Transceiver Transceiver Transceiver
Block
Block
Block
Block
PLL
PLL
PCI Express
Hard IP Block
Transceiver Transceiver Transceiver Transceiver
Block
Block
Block
Block
General Purpose
I/O and Memory
Interface
General Purpose
I/O and Memory
Interface
LVDS Channels
The Stratix IV device family supports LVDS on both row and column I/O banks. Row
I/Os support true LVDS input with 100-Ω differential input termination (OCT RD ),
and true LVDS output buffers. Column I/Os supports true LVDS input buffers
without OCT R D. Alternately, you can configure the row and column LVDS pins as
emulated LVDS output buffers that use two single-ended output buffers with an
external resistor network to support LVDS, mini-LVDS, and RSDS standards.
Stratix IV devices offer single-ended I/O refclk support for the LVDS.
Dedicated SERDES and DPA circuitries are implemented on the row I/O banks to
further enhance LVDS interface performance in the device. For column I/O banks,
SERDES is implemented in the core logic because there is no dedicated SERDES
circuitry on column I/O banks.
1
Emulated differential output buffers support tri-state capability starting with the
Quartus II software version 9.1.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
LVDS Channels
8–5
Table 8–1 and Table 8–2 list the maximum number of row and column LVDS I/Os
supported in Stratix IV E devices. You can design the LVDS I/Os as true LVDS buffers
or emulated LVDS buffers, as long as the combination of the two do not exceed the
maximum count.
For example, there are a total of 112 LVDS pairs on row I/Os in the 780-pin EP4SE230
device (refer to Table 8–1). You can design up to a maximum of 56 true LVDS input
buffers and 56 true LVDS output buffers, or up to a maximum of 112 emulated LVDS
output buffers. For the 780-pin EP4SE230 device (refer to Table 8–2), there are a total
of 128 LVDS pairs on column I/Os. You can design up to a maximum of 64 true LVDS
input buffers and 64 emulated LVDS output buffers, or up to a maximum of 128
emulated LVDS output buffers.
Table 8–1. LVDS Channels Supported in Stratix IV E Device Row I/O Banks (Note 1), (2), (3)
Device
780-Pin FineLine BGA
1152-Pin FineLine BGA
1517-Pin FineLine BGA
1760- Pin FineLine BGA
EP4SE230
56 Rx or eTx + 56 Tx
or eTx
—
—
—
EP4SE360
56 Rx or eTx + 56 Tx
or eTx (4)
88 Rx or eTx + 88 Tx
or eTx
—
—
EP4SE530
—
88 Rx or eTx + 88 Tx
or eTx (5)
112 Rx or eTx + 112 Tx
or eTx (6)
112 Rx or eTx + 112 Tx
or eTx
EP4SE820
—
88 Rx or eTx + 88 Tx
or eTx
112 Rx or eTx + 112 Tx
or eTx
132 Rx or eTx + 132 Tx
or eTx
Notes to Table 8–1:
(1) Receiver (Rx) = true LVDS input buffers with OCT RD, Transmitter (Tx) = true LVDS output buffers, eTx = emulated LVDS output buffers (either
LVDS_E_1R or LVDS_E_3R).
(2) The LVDS Rx and Tx channels are equally divided between the left and right sides of the device.
(3) The LVDS channel count does not include dedicated clock input pins.
(4) EP4SE360 devices are offered in the H780 package instead of the F780 package.
(5) EP4SE530 devices are offered in the H1152 package instead of the F1152 package.
(6) EP4SE530 devices are offered in the H1517 package instead of the F1517 package.
Table 8–2. LVDS Channels Supported in Stratix IV E Device Column I/O Banks (Note 1), (2), (3)
Device
780-Pin FineLine BGA
1152-Pin FineLine BGA
1517-Pin FineLine BGA
1760-Pin FineLine BGA
EP4SE230
64 Rx or eTx + 64 eTx
—
—
—
EP4SE360
64 Rx or eTx + 64 eTx
(4)
96 Rx or eTx + 96 eTx
—
—
EP4SE530
—
96 Rx or eTx + 96 eTx
(5)
128 Rx or eTx + 128 eTx
(6)
128 Rx or eTx + 128 eTx
EP4SE820
—
96 Rx or eTx + 96 eTx
128 Rx or eTx + 128 eTx 144 Rx or eTx + 144 eTx
Notes to Table 8–2:
(1)
(2)
(3)
(4)
(5)
(6)
Rx = true LVDS input buffers without OCT RD, eTx = emulated LVDS output buffers (either LVDS_E_1R or LVDS_E_3R).
The LVDS Rx and Tx channels are equally divided between the top and bottom sides of the device.
The LVDS channel count does not include dedicated clock input pins.
EP4SE360 devices are offered in the H780 package instead of the F780 package.
EP4SE530 devices are offered in the H1152 package instead of the F1152 package.
EP4SE530 devices are offered in the H1517 package instead of the F1517 package.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
8–6
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
LVDS Channels
Table 8–3 and Table 8–4 list the maximum number of row and column LVDS I/Os
supported in Stratix IV GT devices.
Table 8–3. LVDS Channels Supported in Stratix IV GT Device Row I/O Banks (Note 1), (2)
Device
1517-pin FineLine BGA
1932-pin FineLine BGA
EP4S40G2
46 Rx or eTx + 73 Tx or eTx
—
EP4S40G5
46 Rx or eTx + 73 Tx or eTx
—
EP4S100G2
46 Rx or eTx + 73 Tx or eTx
—
EP4S100G3
—
47 Rx or eTx + 56 Tx or eTx
EP4S100G4
—
47 Rx or eTx + 56 Tx or eTx
EP4S100G5
46 Rx or eTx + 73 Tx or eTx
47 Rx or eTx + 56 Tx or eTx
Notes to Table 8–3:
(1) Rx = true LVDS input buffers with OCT RD, eTx = emulated LVDS output buffers (either LVDS_E_1R or
LVDS_E_3R).
(2) The LVDS Rx and Tx channel count does not include dedicated clock input pins.
Table 8–4. LVDS Channels Supported in Stratix IV GT Device Column I/O Banks (Note 1), (2)
Device
1517-pin FineLine BGA
1932-pin FineLine BGA
EP4S40G2
96 Rx or eTx + 96 eTx
—
EP4S40G5
96 Rx or eTx + 96 eTx
—
EP4S100G2
96 Rx or eTx + 96 eTx
—
EP4S100G3
—
128 Rx or eTx + 128 eTx
EP4S100G4
—
128 Rx or eTx + 128 eTx
EP4S100G5
96 Rx or eTx + 96 eTx
128 Rx or eTx + 128 eTx
Notes to Table 8–4:
(1) Rx = true LVDS input buffers without OCT RD, eTx = emulated LVDS output buffers (either LVDS_E_1R or
LVDS_E_3R).
(2) The LVDS Rx and Tx channel count does not include dedicated clock input pins.
Table 8–5 and Table 8–6 list the maximum number of row and column LVDS I/Os
supported in Stratix IV GX devices.
Table 8–5. LVDS Channels Supported in Stratix IV GX Device Row I/O Banks (Note 1), (2), (3) (Part 1 of 2)
780-Pin
FineLine BGA
1152-Pin
FineLine BGA
1152-Pin
FineLine BGA
(4)
1517-Pin
FineLine BGA
1760-Pin
FineLine BGA
1932-Pin
FineLine BGA
EP4SGX70
28 Rx or eTx +
28 Tx or eTx
—
56 Rx or eTx +
56 Tx or eTx
—
—
—
EP4SGX110
28 Rx or eTx +
28 Tx or eTx
28 Rx or eTx +
28 Tx or eTx
56 Rx or eTx +
56 Tx or eTx
—
—
—
EP4SGX180
28 Rx or eTx +
28 Tx or eTx
44 Rx or eTx +
44 Tx or eTx
44 Rx or eTx +
44 Tx or eTx
88 Rx or eTx +
88 Tx or eTx
—
—
EP4SGX230
28 Rx or eTx +
28 Tx or eTx
44 Rx or eTx +
44 Tx or eTx
44 Rx or eTx +
44 Tx or eTx
88 Rx or eTx +
88 Tx or eTx
—
—
EP4SGX290
— (5)
44 Rx or eTx +
44 Tx or eTx
44 Rx or eTx +
44 Tx or eTx
88 Rx or eTx +
88 Tx or eTx
88 Rx or eTx +
88 Tx or eTx
98 Rx or eTx +
98 Tx or eTx
Device
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
LVDS Channels
8–7
Table 8–5. LVDS Channels Supported in Stratix IV GX Device Row I/O Banks (Note 1), (2), (3) (Part 2 of 2)
Device
780-Pin
FineLine BGA
1152-Pin
FineLine BGA
1152-Pin
FineLine BGA
(4)
1517-Pin
FineLine BGA
1760-Pin
FineLine BGA
1932-Pin
FineLine BGA
EP4SGX360
— (5)
44 Rx or eTx +
44 Tx or eTx
44 Rx or eTx +
44 Tx or eTx
88 Rx or eTx +
88 Tx or eTx
88 Rx or eTx +
88 Tx or eTx
98 Rx or eTx +
98 Tx or eTx
EP4SGX530
—
—
44 Rx or eTx +
44 Tx or eTx
(6)
88 Rx or eTx +
88 Tx or eTx
(7)
88 Rx or eTx +
88 Tx or eTx
98 Rx or eTx +
98 Tx or eTx
Notes to Table 8–5:
(1) Rx = true LVDS input buffers with OCT RD, Tx = true LVDS output buffers, eTx = emulated LVDS output buffers (either LVDS_E_1R or
LVDS_E_3R).
(2) The LVDS Rx and Tx channels are equally divided between the left and right sides of the device, except for the devices in the 780-pin Fineline
BGA. These devices have the LVDS Rx and Tx located on the left side of the device.
(3) The LVDS channel count does not include dedicated clock input pins.
(4) This package supports PMA-only transceiver channels.
(5) EP4SGX290 and EP4SGX360 devices are offered in the H780 package instead of the F780 package.
(6) EP4SGX530 devices are offered in the H1152 package instead of the F1152 package.
(7) EP4SGX530 devices are offered in the H1517 package instead of the F1517 package.
Table 8–6. LVDS Channels Supported in Stratix IV GX Device Column I/O Banks (Note 1), (2), (3)
Device
780-Pin
FineLine BGA
1152-Pin
FineLine BGA
1152-Pin
FineLine BGA
(4)
1517-Pin
FineLine BGA
1760-Pin
FineLine BGA
1932-Pin
FineLine BGA
EP4SGX70
64 Rx or eTx +
64 eTx
—
64 Rx or eTx +
64 eTx
—
—
—
EP4SGX110
64 Rx or eTx +
64 eTx
64 Rx or eTx +
64 eTx
64 Rx or eTx +
64 eTx
—
—
—
EP4SGX180
64 Rx or eTx +
64 eTx
96 Rx or eTx +
96 eTx
96 Rx or eTx +
96 eTx
96 Rx or eTx +
96 eTx
—
—
EP4SGX230
64 Rx or eTx +
64 eTx
96 Rx or eTx +
96 eTx
96 Rx or eTx +
96 eTx
96 Rx or eTx +
96 eTx
—
—
EP4SGX290
72 Rx or eTx +
72 eTx (5)
96 Rx or eTx +
96 eTx
96 Rx or eTx +
96 eTx
96 Rx or eTx +
96 eTx
128 Rx or eTx +
128 eTx
128 Rx or eTx +
128 eTx (8)
EP4SGX360
72 Rx or eTx +
72 eTx (5)
96 Rx or eTx +
96 eTx
96 Rx or eTx +
96 eTx
96 Rx or eTx +
96 eTx
128 Rx or eTx +
128 eTx
128 Rx or eTx +
128 eTx (8)
EP4SGX530
—
—
96 Rx or eTx +
96 eTx (6)
96 Rx or eTx +
96 eTx (7)
128 Rx or eTx +
128 eTx
128 Rx or eTx +
128 eTx
Notes to Table 8–6:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Rx = true LVDS input buffers without OCT RD, eTx = emulated LVDS output buffers (either LVDS_E_1R or LVDS_E_3R).
The LVDS Rx and Tx channels are equally divided between the left and right sides of the device.
The LVDS channel count does not include dedicated clock input pins.
This package supports PMA-only transceiver channels.
EP4SGX290 and EP4SGX360 devices are offered in the H780 package instead of the F780 package.
EP4SGX530 devices are offered in the H1152 package instead of the F1152 package.
EP4SGX530 devices are offered in the H1517 package instead of the F1517 package.
The Quartus II software version 9.0 does not support EP4SGX290 and EP4SGX360 devices in the 1932-Pin FineLine BGA package. These
devices will be supported in a future release of the Quartus II software.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
8–8
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
LVDS SERDES
LVDS SERDES
Figure 8–4 shows a transmitter and receiver block diagram for the LVDS SERDES
circuitry in the left and right banks. This diagram shows the interface signals of the
transmitter and receiver data path. For more information, refer to “Differential
Transmitter” on page 8–11 and “Differential Receiver” on page 8–17.
Figure 8–4. LVDS SERDES (Note 1), (2), (3)
Serializer
tx_in
2
IOE Supports SDR, DDR, or
Non-Registered Datapath
IOE
tx_out
+
-
10
DIN DOUT
LVDS Transmitter
tx_coreclock
3
(LVDS_LOAD_EN, diffioclk,
tx_coreclock)
IOE Supports SDR, DDR, or
Non-Registered Datapath
10
2
LVDS Receiver
+
-
IOE
rx_out
rx_in
Synchronizer
FPGA
Fabric
Deserializer
Bit Slip
DOUT DIN
DOUT DIN
DPA Circuitry
Retimed
Data
DOUT DIN
DIN
diffioclk
2
(LOAD_EN, diffioclk)
Clock MUX
DPA_diffioclk
LVDS_diffioclk
DPA Clock
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
rx_divfwdclk
rx_outclock
3
(LVDS_LOAD_EN,
LVDS_diffioclk,
rx_outclock
LVDS Clock Domain
DPA Clock Domain
8 Serial LVDS
Clock Phases
Left/Right PLL
rx_inclock/tx_inclock
Notes to Figure 8–4:
(1) This diagram shows a shared PLL between the transmitter and receiver. If the transmitter and receiver are not sharing the same PLL, the two left
and right PLLs are required.
(2) In SDR and DDR modes, the data width is 1 and 2 bits, respectively.
(3) The tx_in and rx_out ports have a maximum data width of 10 bits.
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
ALTLVDS Port List
8–9
ALTLVDS Port List
Table 8–7 lists the interface signals for an LVDS transmitter and receiver.
Table 8–7. Port List of the LVDS Interface (ALTLVDS) (Note 1), (2) (Part 1 of 3)
Port Name
Input /
Output
Description
PLL Signals
pll_areset
Input
Asynchronous reset to the LVDS transmitter and receiver PLL. The
minimum pulse width requirement for this signal is 10 ns.
Input
The data bus width per channel is the same as the serialization factor (SF).
Input data must be synchronous to the tx_coreclock signal.
LVDS Transmitter Interface Signals
tx_in[ ]
Reference clock input for the transmitter PLL.
Input
tx_inclock
The ALTLVDS MegaWizard Plug-In Manager software automatically selects
the appropriate PLL multiplication factor based on the data rate and
reference clock frequency selection.
For more information about the allowed frequency range for this reference
clock, refer to the “High-Speed I/O Specification” section in the DC and
Switching Characteristics for Stratix IV Devices chapter.
tx_enable (3)
Input
This port is instantiated only when you select the Use External PLL option
in the MegaWizard Plug-In Manager software. This input port must be
driven by the PLL instantiated though the ALTPLL MegaWizard Plug-In
Manager software.
tx_out
Output
LVDS transmitter serial data output port. tx_out is clocked by a serial clock
generated by the left and right PLL.
tx_outclock
Output
The frequency of this clock is programmable to be the same as the data
rate, half the data rate, or one-fourth the data rate. The phase offset of this
clock, with respect to the serial data, is programmable in increments of 45°.
FPGA fabric-transmitter interface clock. The parallel transmitter data
generated in the FPGA fabric must be clocked with this clock.
tx_coreclock (3)
Output
tx_locked
Output
February 2011
Altera Corporation
This port is not available when you select the Use External PLL option in the
MegaWizard Plug-In Manager software. The FPGA fabric-transmitter
interface clock must be driven by the PLL instantiated through the ALTPLL
MegaWizard Plug-In Manager software.
When high, this signal indicates that the transmitter PLL is locked to the
input reference clock.
Stratix IV Device Handbook Volume 1
8–10
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
ALTLVDS Port List
Table 8–7. Port List of the LVDS Interface (ALTLVDS) (Note 1), (2) (Part 2 of 3)
Port Name
Input /
Output
Description
LVDS Receiver Interface Signals
rx_in
Input
LVDS receiver serial data input port.
Reference clock input for the receiver PLL.
rx_inclock
Input
The ALTLVDS MegaWizard Plug-In Manager software automatically selects
the appropriate PLL multiplication factor based on the data rate and
reference clock frequency selection.
For more information about the allowed frequency range for this reference
clock, refer to the “High-Speed I/O Specification” section in the DC and
Switching Characteristics in Stratix IV Devices chapter.
Input
Edge-sensitive bit-slip control signal. Each rising edge on this signal causes
the data re-alignment circuitry to shift the word boundary by one bit. The
minimum pulse width requirement is one parallel clock cycle. There is no
maximum pulse width requirement.
Input
When low, the DPA tracks any dynamic phase variations between the clock
and data. When high, the DPA holds the last locked phase and does not
track any dynamic phase variations between the clock and data. This port is
not available in non-DPA mode.
Input
This port is instantiated only when you select the Use External PLL option
in the MegaWizard Plug-In Manager software. This input port must be
driven by the PLL instantiated though the ALTPLL MegaWizard Plug-In
Manager software.
Output
Receiver parallel data output. The data bus width per channel is the same as
the deserialization factor (DF). The output data is synchronous to the
rx_outclock signal in non-DPA and DPA modes. It is synchronous to the
rx_divfwdclk signal in soft-CDR mode.
rx_outclock
Output
Parallel output clock from the receiver PLL. The parallel data output from
the receiver is synchronous to this clock in non-DPA and DPA modes. This
port is not available when you select the Use External PLL option in the
MegaWizard Plug-In Manager software. The FPGA fabric-receiver interface
clock must be driven by the PLL instantiated through the ALTPLL
MegaWizard Plug-In Manager software.
rx_locked
Output
When high, this signal indicates that the receiver PLL is locked to
rx_inclock.
rx dpa locked
Output
This signal only indicates an initial DPA lock condition to the optimum
phase after power up or reset. This signal is not de-asserted if the DPA
selects a new phase out of the eight clock phases to sample the received
data. You must not use the rx_dpa_locked signal to determine a DPA
loss-of-lock condition.
rx_cda_max
Output
Data re-alignment (bit slip) roll-over signal. When high for one parallel clock
cycle, this signal indicates that the user-programmed number of bits for the
word boundary to roll-over have been slipped.
rx_divfwdclk
Output
Parallel DPA clock to the FPGA fabric logic array. The parallel receiver
output data to the FPGA fabric logic array is synchronous to this clock in
soft-CDR mode. This signal is not available in non-DPA and DPA modes.
dpa_pll_recal
Input
Enable PLL calibration dynamically without resetting the DPA circuitry or
the PLL.
rx_channel_data_align
rx_dpll_hold
rx_enable (3)
rx_out[ ]
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February 2011
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Transmitter
8–11
Table 8–7. Port List of the LVDS Interface (ALTLVDS) (Note 1), (2) (Part 3 of 3)
Input /
Output
Port Name
Description
Output
Busy signal that is asserted high when the PLL calibration occurs.
Input
Asynchronous reset to the DPA circuitry and FIFO. The minimum pulse
width requirement for this reset is one parallel clock cycle. This signal
resets DPA and FIFO blocks.
rx_fifo_reset
Input
Asynchronous reset to the FIFO between the DPA and the data realignment
circuits. The synchronizer block must be reset after a DPA loses lock
condition and the data checker shows corrupted received data. The
minimum pulse width requirement for this reset is one parallel clock cycle.
This signal resets the FIFO block.
rx_cda_reset
Input
Asynchronous reset to the data realignment circuitry. The minimum pulse
width requirement for this reset is one parallel clock cycle. This signal
resets the data realignment block.
dpa_pll_cal_busy
Reset Signals
rx_reset
Notes to Table 8–7:
(1) Unless stated, signals are valid in all three modes (non-DPA, DPA, and soft-CDR) for a single channel.
(2) All reset and control signals are active high.
(3) For more information, refer to “LVDS Interface with the Use External PLL Option Enabled” on page 8–26.
f For more information about the LVDS transmitter and receiver settings using
ALTLVDS, refer to the ALTLVDS Megafunction User Guide.
Differential Transmitter
The Stratix IV transmitter has a dedicated circuitry to provide support for LVDS
signaling. The dedicated circuitry consists of a differential buffer, a serializer, and left
and right PLLs that can be shared between the transmitter and receiver. The
differential buffer can drive out LVDS, mini-LVDS, and RSDS signaling levels. The
serializer takes up to 10 bits wide parallel data from the FPGA fabric, clocks it into the
load registers, and serializes it using shift registers clocked by the left and right PLL
before sending the data to the differential buffer. The MSB of the parallel data is
transmitted first.
1
February 2011
When using emulated LVDS I/O standards at the differential transmitter, the
SERDES circuitry must be implemented in logic cells but not hard SERDES.
Altera Corporation
Stratix IV Device Handbook Volume 1
8–12
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Transmitter
The load enable (LVDS_LOAD_EN) signal and the diffioclk signal (the clock running at
serial data rate) generated from PLL_Lx (left PLL) or PLL_Rx (right PLL) clocks the load
and shift registers. You can statically set the serialization factor to ×3, ×4, ×6, ×7, ×8, or
×10 using the Quartus II software. The load enable signal is derived from the
serialization factor setting. Figure 8–5 shows a block diagram of the Stratix IV
transmitter.
Figure 8–5. Stratix IV Transmitter (Note 1), (2)
Serializer
tx_in 10
DIN
2
IOE
IOE supports SDR, DDR, or
Non-Registered Datapath
+
-
DOUT
tx_out
FPGA
Fabric
LVDS Transmitter
tx_coreclock
3 (LVDS_LOAD_EN, diffioclk, tx_coreclock)
Left/Right PLL
tx_inclock
LVDS Clock Domain
Notes to Figure 8–5:
(1) In SDR and DDR modes, the data width is 1 and 2 bits, respectively.
(2) The tx_in port has a maximum data width of 10 bits.
You can configure any Stratix IV transmitter data channel to generate a
source-synchronous transmitter clock output. This flexibility allows the placement of
the output clock near the data outputs to simplify board layout and reduce
clock-to-data skew. Different applications often require specific clock-to-data
alignments or specific data-rate-to-clock-rate factors. The transmitter can output a
clock signal at the same rate as the data with a maximum frequency of 800 MHz. The
output clock can also be divided by a factor of 1, 2, 4, 6, 8, or 10, depending on the
serialization factor. You can set the phase of the clock in relation to the data at 0° or
180° (edge or center aligned). The left and right PLLs (PLL_Lx and PLL_Rx) provide
additional support for other phase shifts in 45° increments. These settings are made
statically in the Quartus II MegaWizard Plug-In Manager software.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Transmitter
8–13
Figure 8–6 shows the Stratix IV transmitter in clock output mode. In clock output
mode, you can use an LVDS channel as a clock output channel.
Figure 8–6. Stratix IV Transmitter in Clock Output Mode
Transmitter Circuit
Parallel
Series
Txclkout+
Txclkout–
FPGA
Fabric
Left/Right
PLL
diffioclk
LVDS_LOAD_EN
You can bypass the Stratix IV serializer to support DDR (×2) and SDR (×1) operations
to achieve a serialization factor of 2 and 1, respectively. The I/O element (IOE)
contains two data output registers that can each operate in either DDR or SDR mode.
Figure 8–7 shows the serializer bypass path.
Figure 8–7. Serializer Bypass in Stratix IV Devices (Note 1), (2), (3)
Serializer
tx_in 2
DIN
2
IOE
IOE supports SDR, DDR, or
Non-Registered Datapath
+
-
DOUT
tx_out
FPGA
Fabric
LVDS Transmitter
tx_coreclock
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
3
Left/Right PLL
Notes to Figure 8–7:
(1) All disabled blocks and signals are grayed out.
(2) In DDR mode, tx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE.
(3) In SDR and DDR modes, the data width to the IOE is 1 and 2 bits, respectively.
February 2011
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Stratix IV Device Handbook Volume 1
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Transmitter
Programmable VOD and Programmable Pre-Emphasis
Stratix IV LVDS transmitters support programmable pre-emphasis and
programmable V OD. Pre-emphasis increases the amplitude of the high-frequency
component of the output signal, and thus helps to compensate for the
frequency-dependent attenuation along the transmission line. Figure 8–8 shows the
differential LVDS output.
Figure 8–8. Differential VOD
Single-Ended Waveform
Positive Channel (p)
VOD
Negative Channel (n)
VCM
Ground
VOD (diff peak - peak) = 2 x VOD(single-ended)
Differential Waveform
VOD
p - n = 0V
VOD
Figure 8–9 shows the LVDS output with pre-emphasis.
Figure 8–9. Programmable Pre-Emphasis (Note 1)
OUT
VP
VOD
OUT
VP
Note to Figure 8–9:
(1) VP— voltage boost from pre-emphasis. VOD— Differential output voltage (peak-peak).
Stratix IV Device Handbook Volume 1
February 2011
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Transmitter
8–15
Pre-emphasis is an important feature for high-speed transmission. Without
pre-emphasis, the output current is limited by the VOD setting and the output
impedance of the driver. At high frequency, the slew rate may not be fast enough to
reach full VOD before the next edge, producing pattern-dependent jitter.
With pre-emphasis, the output current is boosted momentarily during switching to
increase the output slew rate. The overshoot introduced by the extra current happens
only during switching and does not ring, unlike the overshoot caused by signal
reflection. The amount of pre-emphasis needed depends on the attenuation of the
high-frequency component along the transmission line. The Quartus II software
allows four settings for programmable pre-emphasis—zero (0), low (1), medium (2),
and high (3). The default setting is low.
The VOD is also programmable with four settings: low (0), medium low (1), medium
high (2), and high (3). The default setting is medium low.
Programmable VOD
You can statically assign the VOD settings from the Assignment Editor. Table 8–8 lists
the assignment name for programmable VOD and its possible values in the Quartus II
software Assignment Editor.
Table 8–8. Quartus II Software Assignment Editor
To
tx_out
Assignment name
Programmable Differential Output Voltage (VOD)
Allowed values
0, 1, 2, 3
Figure 8–10 shows the assignment of programmable V OD for a transmit data output
from the Quartus II software Assignment Editor.
Figure 8–10. Quartus II Software Assignment Editor—Programmable VOD
February 2011
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Stratix IV Device Handbook Volume 1
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Transmitter
Programmable Pre-Emphasis
Four different settings are allowed for pre-emphasis from the Assignment Editor for
each LVDS output channel. Table 8–9 lists the assignment name and its possible
values for programmable pre-emphasis in the Quartus II software Assignment Editor.
Table 8–9. Quartus II Software Assignment Editor
To
tx_out
Assignment name
Programmable Pre-emphasis
Allowed values
0, 1, 2, 3
Figure 8–11 shows the assignment of programmable pre-emphasis for a transmit data
output port from the Quartus II software Assignment Editor.
Figure 8–11. Quartus II Software Assignment Editor – Programmable Pre-Emphasis
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Receiver
8–17
Differential Receiver
The Stratix IV device family has a dedicated circuitry to receive high-speed
differential signals in row I/Os. Figure 8–12 shows the hardware blocks of the
Stratix IV receiver. The receiver has a differential buffer and left and right PLLs that
can be shared between the transmitter and receiver, a DPA block, a synchronizer, a
data realignment block, and a deserializer. The differential buffer can receive LVDS,
mini-LVDS, and RSDS signal levels, which are statically set in the Quartus II software
Assignment Editor.
The left and right PLL receives the external clock input and generates different phases
of the same clock. The DPA block chooses one of the clocks from the left and right PLL
and aligns the incoming data on each channel. The synchronizer circuit is a 1 bit wide
by 6 bit deep FIFO buffer that compensates for any phase difference between the DPA
clock and the data realignment block. If necessary, the user-controlled data
realignment circuitry inserts a single bit of latency in the serial bit stream to align to
the word boundary. The deserializer includes shift registers and parallel load
registers, and sends a maximum of 10 bits to the internal logic.
The Stratix IV device family supports three different receiver modes:
■
“Non-DPA Mode” on page 8–22
■
“DPA Mode” on page 8–24
■
“Soft-CDR Mode” on page 8–25
The physical medium connecting the transmitter and receiver LVDS channels may
introduce skew between the serial data and the source-synchronous clock. The
instantaneous skew between each LVDS channel and the clock also varies with the
jitter on the data and clock signals as seen by the receiver. The three different modes—
non-DPA, DPA, and soft-CDR—provide different options to overcome skew between
the source synchronous clock (non-DPA, DPA) /reference clock (soft-CDR) and the
serial data.
1
Only non-DPA mode requires manual skew adjustment.
Non-DPA mode allows you to statically select the optimal phase between the source
synchronous clock and the received serial data to compensate skew. In DPA mode,
the DPA circuitry automatically chooses the best phase to compensate for the skew
between the source synchronous clock and the received serial data. Soft-CDR mode
provides opportunities for synchronous and asynchronous applications for
chip-to-chip and short reach board-to-board applications for SGMII protocols.
February 2011
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Stratix IV Device Handbook Volume 1
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Receiver
Figure 8–12. Receiver Block Diagram (Note 1), (2)
LVDS Receiver
IOE Supports SDR, DDR, or Non-Registered Datapath
2
rx_out
+
IOE
10
rx_in
Synchronizer
Deserializer
Bit Slip
DOUT DIN
DOUT DIN
DPA Circuitry
Retimed
Data
DOUT DIN
DIN
FPGA
Fabric
2
DPA Clock
LVDS_diffiioclk
Clock Mux
rx_divfwdclk
DPA_diffioclk
diffioclk
(LOAD_EN, diffioclk)
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
rx_outclock
3
(LVDS_LOAD_EN,
LVDS_diffioclk,
rx_outclk)
LVDS Clock Domain
DPA Clock Domain
8 Serial LVDS
Clock Phases
Left/Right PLL
rx_inclock
Notes to Figure 8–12:
(1) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(2) The rx_out port has a maximum data width of 10 bits.
Differential I/O Termination
The Stratix IV device family provides a 100-Ω, on-chip differential termination option
on each differential receiver channel for LVDS standards. On-chip termination saves
board space by eliminating the need to add external resistors on the board. You can
enable on-chip termination in the Quartus II software Assignment Editor.
On-chip differential termination is supported on all row I/O pins and dedicated clock
input pins (CLK[0,2,9,11]). It is not supported for column I/O pins, dedicated clock
input pins (CLK[1,3,8,10]), or the corner PLL clock inputs.
Figure 8–13 shows device on-chip termination.
Figure 8–13. On-Chip Differential I/O Termination
Stratix IV Differential
Receiver with On-Chip
100 Ω Termination
LVDS
Transmitter
Z0 = 50 Ω
RD
Z0 = 50 Ω
Stratix IV Device Handbook Volume 1
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Receiver
8–19
Receiver Hardware Blocks
The differential receiver has the following hardware blocks:
■
“DPA Block” on page 8–19
■
“Synchronizer” on page 8–20
■
“Data Realignment Block (Bit Slip)” on page 8–20
■
“Deserializer” on page 8–22
DPA Block
The DPA block takes in high-speed serial data from the differential input buffer and
selects one of the eight phases generated by the left and right PLL to sample the data.
The DPA chooses a phase closest to the phase of the serial data. The maximum phase
offset between the received data and the selected phase is 1/8 UI, which is the
maximum quantization error of the DPA. The eight phases of the clock are equally
divided, offering a 45° resolution.
Figure 8–14 shows the possible phase relationships between the DPA clocks and the
incoming serial data.
Figure 8–14. DPA Clock Phase to Serial Data Timing Relationship (Note 1)
rx_in
D0
D1
D2
D3
D4
Dn
0˚
45˚
90˚
135˚
180˚
225˚
270˚
315˚
Tvco
0.125Tvco
Note to Figure 8–14:
(1) TVCO is defined as the PLL serial clock period.
The DPA block continuously monitors the phase of the incoming serial data and
selects a new clock phase if needed. You can prevent the DPA from selecting a new
clock phase by asserting the optional RX_DPLL_HOLD port, which is available for each
channel.
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Stratix IV Device Handbook Volume 1
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Receiver
DPA circuitry does not require a fixed training pattern to lock to the optimum phase
out of the eight phases. After reset or power up, DPA circuitry requires transitions on
the received data to lock to the optimum phase. An optional output port,
RX_DPA_LOCKED, is available to indicate an initial DPA lock condition to the optimum
phase after power up or reset. This signal is not de-asserted if the DPA selects a new
phase out of the eight clock phases to sample the received data. Do not use the
rx_dpa_locked signal to determine a DPA loss-of-lock condition. Use data checkers
such as a cyclic redundancy check (CRC) or diagonal interleaved parity (DIP-4) to
validate the data.
An independent reset port, RX_RESET, is available to reset the DPA circuitry. DPA
circuitry must be retrained after reset.
1
The DPA block is bypassed in non-DPA mode.
Synchronizer
The synchronizer is a 1 bit wide and 6 bit deep FIFO buffer that compensates for the
phase difference between DPA_diffioclk, which is the optimal clock selected by the
DPA block, and LVDS_diffioclk, which is produced by the left and right PLL. The
synchronizer can only compensate for phase differences, not frequency differences
between the data and the receiver’s input reference clock.
An optional port, RX_FIFO_RESET, is available to the internal logic to reset the
synchronizer. The synchronizer is automatically reset when the DPA first locks to the
incoming data. Altera recommends using RX_FIFO_RESET to reset the synchronizer
when the DPA signals a loss-of-lock condition and the data checker indicates
corrupted received data.
1
The synchronizer circuit is bypassed in non-DPA and soft-CDR mode.
Data Realignment Block (Bit Slip)
Skew in the transmitted data along with skew added by the link causes
channel-to-channel skew on the received serial data streams. If the DPA is enabled,
the received data is captured with different clock phases on each channel. This may
cause the received data to be misaligned from channel to channel. To compensate for
this channel-to-channel skew and establish the correct received word boundary at
each channel, each receiver channel has a dedicated data realignment circuit that
realigns the data by inserting bit latencies into the serial stream.
An optional RX_CHANNEL_DATA_ALIGN port controls the bit insertion of each receiver
independently controlled from the internal logic. The data slips one bit on the rising
edge of RX_CHANNEL_DATA_ALIGN. The requirements for the RX_CHANNEL_DATA_ALIGN
signal include:
■
The minimum pulse width is one period of the parallel clock in the logic array.
■
The minimum low time between pulses is one period of the parallel clock.
■
This is an edge-triggered signal.
■
Valid data is available two parallel clock cycles after the rising edge of
RX_CHANNEL_DATA_ALIGN.
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Receiver
8–21
Figure 8–15 shows receiver output (RX_OUT) after one bit slip pulse with the
deserialization factor set to 4.
Figure 8–15. Data Realignment Timing
rx_inclock
rx_in
3
2
1
0
3
2
1
0
3
2
1
0
rx_outclock
rx_channel_data_align
rx_out
3210
321x
xx21
0321
The data realignment circuit can have up to 11 bit-times of insertion before a rollover
occurs. The programmable bit rollover point can be from 1 to 11 bit-times,
independent of the deserialization factor. The programmable bit rollover point must
be set equal to or greater than the deserialization factor, allowing enough depth in the
word alignment circuit to slip through a full word. You can set the value of the bit
rollover point using the MegaWizard Plug-In Manager software. An optional status
port, RX_CDA_MAX, is available to the FPGA fabric from each channel to indicate when
the preset rollover point is reached.
Figure 8–16 shows a preset value of four bit-times before rollover occurs. The
rx_cda_max signal pulses for one rx_outclock cycle to indicate that rollover has
occurred.
Figure 8–16. Receiver Data Re-alignment Rollover
rx_inclock
rx_channel_data_align
rx_outclock
rx_cda_max
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Receiver
Deserializer
You can statically set the deserialization factor to 3, 4, 6, 7, 8, or 10 by using the
Quartus II software. You can bypass the Stratix IV deserializer in the Quartus II
MegaWizard Plug-In Manager software to support DDR (×2) or SDR (×1) operations,
as shown Figure 8–17. The DPA and data realignment circuit cannot be used when the
deserializer is bypassed. The IOE contains two data input registers that can operate in
DDR or SDR mode.
Figure 8–17. Deserializer Bypass in Stratix IV Devices (Note 1), (2), (3)
LVDS Receiver
IOE Supports SDR, DDR, or Non-Registered Datapath
2
rx_out
+
IOE
2
rx_in
Synchronizer
Deserializer
Bit Slip
DOUT DIN
DOUT DIN
DPA Circuitry
Retimed
Data
DOUT DIN
DIN
FPGA
Fabric
2
DPA Clock
rx_divfwdclk
DPA_diffioclk
Clock Mux
LVDS_diffiioclk
diffioclk
(LOAD_EN, diffioclk)
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
rx_outclock
3
(LVDS_LOAD_EN,
LVDS_diffioclk,
rx_outclk)
8 Serial LVDS
Clock Phases
Left/Right PLL
Notes to Figure 8–17:
(1) All disabled blocks and signals are grayed out.
(2) In DDR mode, rx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE.
(3) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
Receiver Data Path Modes
The Stratix IV device family supports three receiver datapath modes—non-DPA
mode, DPA mode, and soft-CDR mode.
Non-DPA Mode
Figure 8–18 shows the non-DPA datapath block diagram. In non-DPA mode, the DPA
and synchronizer blocks are disabled. Input serial data is registered at the rising or
falling edge of the serial LVDS_diffioclk clock produced by the left and right PLL.
You can select the rising/falling edge option using the ALTLDVS MegaWizard
Plug-In Manager software. Both data realignment and deserializer blocks are clocked
by the LVDS_diffioclk clock, which is generated by the left and right PLL.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Receiver
1
8–23
When using non-DPA receivers, you must drive the PLL from a dedicated and
compensated clock input pin. Compensated clock inputs are dedicated clock pins in
the same I/O bank as the PLL.
f For more information about dedicated and compensated clock inputs, refer to the
Clock Networks and PLLs in Stratix IV Devices chapter.
Figure 8–18. Receiver Data Path in Non-DPA Mode (Note 1), (2)
LVDS Receiver
IOE Supports SDR, DDR, or Non-Registered Datapath
2
rx_out
+
IOE
10
rx_in
Synchronizer
Deserializer
Bit Slip
DOUT DIN
DOUT DIN
DPA
P Circuitr y
Retimed
Data
DOUT DIN
N
DIN
FPGA
Fabric
2
DPA
P Clock
L
LVDS_diffiioclk
Clock Mux
rx_divfwdclk
DPA_diffioclk
P
diffioclk
(LOAD_EN, diffioclk)
3
(DPA_LO
P
AD_EN,
DPA_diffioclk,
P
rx_divfwdclk)
rx_outclock
3
(LVDS_LOAD_EN,
LVDS_diffioclk,
rx_outclk)
8 Serial LVDS
L
Clock Phases
Left/Right PLL
rx_inclock
LVDS Clock Domain
Notes to Figure 8–18:
(1) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(2) The rx_out port has a maximum data width of 10 bits.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
8–24
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Receiver
DPA Mode
Figure 8–19 shows the DPA mode datapath, where all the hardware blocks mentioned
in “Receiver Hardware Blocks” on page 8–19 are active. The DPA block chooses the
best possible clock (DPA_diffioclk) from the eight fast clocks sent by the left and right
PLL. This serial DPA_diffioclk clock is used for writing the serial data into the
synchronizer. A serial LVDS_diffioclk clock is used for reading the serial data from
the synchronizer. The same LVDS_diffioclk clock is used in data realignment and
deserializer blocks.
Figure 8–19. Receiver Datapath in DPA Mode (Note 1), (2), (3)
LVDS Receiver
IOE Supports SDR, DDR, or Non-Registered Datapath
2
rx_out
+
IOE
10
rx_in
Synchronizer
Deserializer
Bit Slip
DOUT DIN
DOUT DIN
DPA Circuitry
Retimed
Data
DOUT DIN
DIN
FPGA
Fabric
2
DPA Clock
LVDS_diffiioclk
Clock Mux
rx_divfwdclk
DPA_diffioclk
diffioclk
(LOAD_EN, diffioclk)
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
rx_outclock
3
(LVDS_LOAD_EN,
LVDS_diffioclk,
rx_outclk)
LVDS Clock Domain
DPA Clock Domain
8 Serial LVDS
Clock Phases
Left/Right PLL
rx_inclock
Notes to Figure 8–19:
(1) All disabled blocks and signals are grayed out.
(2) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(3) The rx_out port has a maximum data width of 10 bits.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Receiver
8–25
Soft-CDR Mode
The Stratix IV LVDS channel offers soft-CDR mode to support the Gigabit Ethernet
and SGMII protocols. A receiver PLL uses the local clock source for reference.
Figure 8–20 shows the soft-CDR mode datapath.
Figure 8–20. Receiver Datapath in Soft-CDR Mode (Note 1), (2), (3)
LVDS Receiver
IOE Supports SDR, DDR, or Non-Registered Datapath
2
rx_out
+
IOE
10
rx_in
Synchronizer
Deserializer
Bit Slip
DOUT DIN
DOUT DIN
DPA Circuitry
Retimed
Data
DOUT DIN
DIN
FPGA
Fabric
2
DPA Clock
LVDS_diffiioclk
Clock Mux
rx_divfwdclk
DPA_diffioclk
diffioclk
(LOAD_EN, diffioclk)
3
(DPA_LOAD_EN,
DPA_diffioclk,
rx_divfwdclk)
rx_outclock
3
(LVDS_LOAD_EN,
LVDS_diffioclk,
rx_outclk)
8 Serial LVDS
Clock Phases
LVDS Clock Domain
DPA Clock Domain
Left/Right PLL
rx_inclock
Notes to Figure 8–20:
(1) All disabled blocks and signals are grayed out.
(2) In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
(3) The rx_out port has a maximum data width of 10 bits.
In soft-CDR mode, the synchronizer block is inactive. The DPA circuitry selects an
optimal DPA clock phase to sample the data. Use the selected DPA clock for bit-slip
operation and deserialization. The DPA block also forwards the selected DPA clock,
divided by the deserialization factor called rx_divfwdclk, to the FPGA fabric, along
with the deserialized data. This clock signal is put on the periphery clock (PCLK)
network. When using soft-CDR mode, the rx_reset port must not be asserted after
the rx_dpa_lock is asserted because the DPA will continuously choose new phase
taps from the PLL to track parts per million (PPM) differences between the reference
clock and incoming data.
f For more information about periphery clock networks, refer to the Clock Networks and
PLLs in Stratix IV Devices chapter.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
8–26
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
LVDS Interface with the Use External PLL Option Enabled
You can use every LVDS channel in soft-CDR mode and can drive the FPGA fabric
using the periphery clock network in the Stratix IV device family. The rx_dpa_locked
signal is not valid in soft-CDR mode because the DPA continuously changes its phase
to track PPM differences between the upstream transmitter and the local receiver
input reference clocks. The parallel clock rx_outclock, generated by the left and right
PLL, is also forwarded to the FPGA fabric.
LVDS Interface with the Use External PLL Option Enabled
The ALTLVDS MegaWizard Plug-In Manager software provides an option for
implementing the LVDS interface with the Use External PLL option. With this option
enabled you can control the PLL settings, such as dynamically reconfiguring the PLL
to support different data rates, dynamic phase shift, and other settings. You also must
instantiate an ALTPLL megafunction to generate the various clock and load enable
signals.
When you enable the Use External PLL option with the ALTLVDS transmitter and
receiver, the following signals are required from the ALTPLL megafunction:
1
■
Serial clock input to the SERDES of the ALTLVDS transmitter and receiver
■
Load enable to the SERDES of the ALTLVDS transmitter and receiver
■
Parallel clock used to clock the transmitter FPGA fabric logic and parallel clock
used for the receiver rx_syncclock port and receiver FPGA fabric logic
■
Asynchronous PLL reset port of the ALTLVDS receiver
As an example, Table 8–10 describes the serial clock output, load enable output, and
parallel clock output generated on ports c0, c1, and c2, respectively, along with the
locked signal of the ALTPLL instance. You can choose any of the PLL output clock
ports to generate the interface clocks.
f With soft SERDES, a different clocking requirement is needed. For more information,
refer to the LVDS SERDES Transmitter/Receiver (ALTLVDS_RX/TX) Megafunction User
Guide.
1
The high-speed clock generated from the PLL is intended to clock the LVDS SERDES
circuitry only. Do not use the high-speed clock to drive other logic because the
allowed frequency to drive the core logic is restricted by the PLL FOUT specification.
For more information about the FOUT specification, refer to the DC and Switching
Characteristics for Stratix IV Devices chapter.
Table 8–10 lists the signal interface between the output ports of the ALTPLL
megafunction and the input ports of the ALTLVDS transmitter and receiver.
Table 8–10. Signal Interface Between ALTPLL and ALTLVDS Megafunctions (Part 1 of 2)
From the ALTPLL
Megafunction
To the ALTLVDS Transmitter
To the ALTLVDS Receiver
Serial clock output (c0) (1)
tx_inclock (serial clock input to the
transmitter)
rx_inclock (serial clock input)
Load enable output (c1)
tx_enable (load enable to the transmitter)
rx_enable (load enable for the
deserializer)
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
LVDS Interface with the Use External PLL Option Enabled
8–27
Table 8–10. Signal Interface Between ALTPLL and ALTLVDS Megafunctions (Part 2 of 2)
From the ALTPLL
Megafunction
Parallel clock output (c2)
To the ALTLVDS Transmitter
To the ALTLVDS Receiver
Parallel clock used inside the transmitter core
logic in the FPGA fabric
rx_syncclock (parallel clock input) and
parallel clock used inside the receiver
core logic in the FPGA fabric
~(locked)
pll_areset (asynchronous PLL reset
port) (2)
—
Notes to Table 8–10:
(1) The serial clock output (c0) can only drive tx_inclock on the ALTLVDS transmitter and rx_inclock on the ALTLVDS receiver. This clock
cannot drive the core logic.
(2) The pll_areset signal is automatically enabled for the LVDS receiver in external PLL mode. This signal does not exist for LVDS transmitter
instantiation when the external PLL option is enabled.
1
The rx_syncclock port is automatically enabled in an LVDS receiver in external PLL
mode. The Quartus II compiler errors out if this port is not connected, as shown in
Figure 8–21.
When generating the ALTPLL megafunction, the Left/Right PLL option is configured
to set up the PLL in LVDS mode. Figure 8–21 shows the connection between the
ALTPLL and ALTLVDS megafunctions.
Figure 8–21. LVDS Interface with the ALTPLL Megafunction (Note 1)
FPGA Fabric
LVDS Transmitter
(ALTLVDS)
tx_inclock
Transmitter Core Logic
tx_in
tx_enable
tx_coreclk
c0
c1
c2
rx_coreclk
Receiver Core Logic
LVDS Receiver
(ALTLVDS)
rx_inclock
rx_out
ALTPLL
inclk0
pll_areset
locked
rx_enable
rx_syncclock
pll_areset
Note to Figure 8–21:
(1) Instantiation of pll_areset is optional for the ALTPLL instantiation.
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
8–28
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
LVDS Interface with the Use External PLL Option Enabled
Example 8–1 shows how to generate three output clocks using an ALTPLL
megafunction.
Example 8–1. Generating Three Output Clocks Using an ALTPLL Megafunction
LVDS data rate = 1 Gbps; serialization factor = 10; input reference clock = 100 MHz
The following settings are used when generating the three output clocks using an ALTPLL megafunction.
The serial clock must be 1000 MHz and the parallel clock must be 100 MHz (serial clock divided by the
serialization factor):
■
■
■
c0
■
Frequency = 1000 MHz (multiplication factor = 10 and division factor = 1)
■
Phase shift = –180° with respect to the voltage-controlled oscillator (VCO) clock
■
Duty cycle = 50%
c1
■
Frequency = (1000/10) = 100 MHz (multiplication factor = 1 and division factor = 1)
■
Phase shift = (10 - 2) × 360/10 = 288° [(deserialization factor - 2)/deserialization factor] × 360°
■
Duty cycle = (100/10) = 10% (100 divided by the serialization factor)
c2
■
Frequency = (1000/10) = 100 MHz (multiplication factor = 1 and division factor = 1)
■
Phase shift = (–180/10) = –18° (c0 phase shift divided by the serialization factor)
■
Duty cycle = 50%
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Left and Right PLLs (PLL_Lx and PLL_Rx)
8–29
The Equation 8–1 calculations for phase shift assume that the input clock and serial
data are edge aligned. Introducing a phase shift of –180° to sampling clock (c0)
ensures that the input data is center-aligned with respect to the c0, as shown in
Figure 8–22.
Figure 8–22. Phase Relationship for External PLL Interface Signals
inclk0
VCO clk
(internal PLL clk)
c0 (-180
phase shift)
c1 (288
phase shift)
c2 (-18
phase shift)
Serial data
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
Left and Right PLLs (PLL_Lx and PLL_Rx)
The Stratix IV device family contains up to eight left and right PLLs with up to four
PLLs located on the left side and four on the right side of the device. The left PLLs can
support high-speed differential I/O banks on the left side; the right PLLs can support
high-speed differential I/O banks on the right side of the device. The high-speed
differential I/O receiver and transmitter channels use these left and right PLLs to
generate the parallel clocks (rx_outclock and tx_outclock) and high-speed clocks
(diffioclk).
Figure 8–2 on page 8–3 and Figure 8–3 on page 8–4 show the locations of the left and
right PLLs for Stratix IV E, GT, and GX devices. The PLL VCO operates at the clock
frequency of the data rate. Clock switchover and dynamic reconfiguration are allowed
using the left and right PLL in high-speed differential I/O support mode.
f For more information, refer to the Clock Network and PLLs in Stratix IV Devices chapter.
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8–30
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Stratix IV Clocking
Stratix IV Clocking
The left and right PLLs feed into the differential transmitter and receive channels
through the LVDS and DPA clock network. The center left and right PLLs can clock
the transmitter and receive channels above and below them. The corner left and right
PLLs can drive I/Os in the banks adjacent to them.
Figure 8–23 shows center PLL clocking in the Stratix IV device family. For more
information about PLL clocking restrictions, refer to “Differential Pin Placement
Guidelines” on page 8–38.
Figure 8–23. LVDS/DPA Clocks in the Stratix IV Device Family with Center PLLs
4
DPA
Clock
LVDS
Clock
Quadrant
Quadrant
DPA
Clock
LVDS
4
Clock
4
4
2
Center
PLL_L2
Center
PLL_R2
Center
PLL_L3
Center
PLL_R3
2
2
2
4
4
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
DPA
Clock
LVDS
4
Clock
Figure 8–24 shows center and corner PLL clocking in the Stratix IV device family. For
more information about PLL clocking restrictions, refer to “Differential Pin Placement
Guidelines” on page 8–38.
Figure 8–24. LVDS/DPA Clocks in the Stratix IV Device Family with Center and Corner PLLs
Corner
PLL_R1
Corner
PLL_L1
2
2
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
DPA
Clock
LVDS
4
Clock
4
4
2
2
Center
PLL_L2
Center
PLL_R2
Center
PLL_L3
Center
PLL_R3
2
2
4
4
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
DPA
Clock
LVDS 4
Clock
2
2
Corner
PLL_L4
Stratix IV Device Handbook Volume 1
Corner
PLL_R4
February 2011
Altera Corporation
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Source-Synchronous Timing Budget
8–31
Source-Synchronous Timing Budget
This section describes the timing budget, waveforms, and specifications for
source-synchronous signaling in the Stratix IV device family. LVDS I/O standards
enable high-speed data transmission. This high data transmission rate results in better
overall system performance. To take advantage of fast system performance, it is
important to understand how to analyze timing for these high-speed signals. Timing
analysis for the differential block is different from traditional synchronous timing
analysis techniques.
Instead of focusing on clock-to-output and setup times, source synchronous timing
analysis is based on the skew between the data and the clock signals. High-speed
differential data transmission requires the use of timing parameters provided by IC
vendors and is strongly influenced by board skew, cable skew, and clock jitter. This
section defines the source-synchronous differential data orientation timing
parameters, the timing budget definitions for the Stratix IV device family, and how to
use these timing parameters to determine a design’s maximum performance.
Differential Data Orientation
There is a set relationship between an external clock and the incoming data. For
operations at 1 Gbps and a serialization factor of 10, the external clock is multiplied by
10. You can set phase-alignment in the PLL to coincide with the sampling window of
each data bit. The data is sampled on the falling edge of the multiplied clock.
Figure 8–25 shows the data bit orientation of the ×10 mode.
Figure 8–25. Bit Orientation in the Quartus II Software
inclock/outclock
10 LVDS Bits
MSB
data in
9
8
7
6
5
4
3
LSB
2
1
0
Differential I/O Bit Position
Data synchronization is necessary for successful data transmission at high
frequencies. Figure 8–26 shows the data bit orientation for a channel operation. This
figure is based on the following:
February 2011
■
Serialization factor equals the clock multiplication factor
■
Edge alignment is selected for phase alignment
■
Implemented in hard SERDES
Altera Corporation
Stratix IV Device Handbook Volume 1
8–32
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Source-Synchronous Timing Budget
For other serialization factors, use the Quartus II software tools to find the bit position
within the word. Table 8–11 lists the bit positions after deserialization.
Figure 8–26. Bit-Order and Word Boundary for One Differential Channel (Note 1)
Transmitter Channel
Operation (x8 Mode)
tx_outclock
tx_out
X
Current Cycle
Next Cycle
Previous Cycle
X X X X X X X 7 6 5 4 3 2 1 0 X X X X X X X X
MSB
LSB
Receiver Channel
Operation (x8 Mode)
rx_inclock
rx_in
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
rx_outclock
rx_out [7..0]
XXXXXXXX
XXXXXXXX
XXXX7654
3210XXXX
Note to Figure 8–26:
(1) These are only functional waveforms and are not intended to convey timing information.
Table 8–11 lists the conventions for differential bit naming for 18 differential channels.
The MSB and LSB positions increase with the number of channels used in a system.
Table 8–11. Differential Bit Naming
Internal 8-Bit Parallel Data
Receiver Channel Data Number
Stratix IV Device Handbook Volume 1
MSB Position
LSB Position
1
7
0
2
15
8
3
23
16
4
31
24
5
39
32
6
47
40
7
55
48
8
63
56
9
71
64
10
79
72
11
87
80
12
95
88
13
103
96
14
111
104
15
119
112
16
127
120
17
135
128
18
143
136
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Source-Synchronous Timing Budget
8–33
Transmitter Channel-to-Channel Skew
Transmitter channel-to-channel skew (TCCS) is an important parameter based on the
Stratix IV transmitter in a source synchronous differential interface. This parameter is
used in receiver skew margin calculation. For more information, refer to “Receiver
Skew Margin for Non-DPA Mode” on page 8–33.
TCCS is the difference between the fastest and slowest data output transitions,
including the TCO variation and clock skew. For LVDS transmitters, the TimeQuest
Timing Analyzer provides a TCCS report, which shows TCCS values for serial output
ports.
f You can get the TCCS value from the TCCS report (report_TCCS) in the Quartus II
compilation report under the TimeQuest Timing Analyzer, or from the DC and
Switching Characteristics for Stratix IV Devices chapter.
Receiver Skew Margin for Non-DPA Mode
Changes in system environment, such as temperature, media (cable, connector, or
PCB), and loading effect the receiver ’s setup and hold times; internal skew affects the
sampling ability of the receiver.
Different modes of LVDS receivers use different specifications that can help in
deciding the ability to sample the received serial data correctly. In DPA mode, you
must use DPA jitter tolerance instead of receiver input skew margin (RSKM).
In non-DPA mode, use TCCS, RSKM, and sampling window (SW) specifications for
high-speed source-synchronous differential signals in the receiver data path. The
relationship between RSKM, TCCS, and SW is expressed by the RSKM equation
shown in Equation 8–1.
Equation 8–1. RSKM
– SW – TCCSRSKM = TUI
--------------------------------------------2
Conventions used for the equation:
February 2011
■
Time unit interval (TUI)—Time period of the serial data.
■
RSKM—The timing margin between the receiver ’s clock input and the data input
sampling window.
■
SW—The period of time that the input data must be stable to ensure that data is
successfully sampled by the LVDS receiver. The SW is a device property and
varies with device speed grade.
■
TCCS—The timing difference between the fastest and the slowest output edges,
including tCO variation and clock skew, across channels driven by the same PLL.
The clock is included in the TCCS measurement.
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Source-Synchronous Timing Budget
Figure 8–27 shows the relationship between the RSKM, TCCS, and the receiver’s SW.
You must calculate the RSKM value to decide whether or not data can be sampled
properly by the LVDS receiver with the given data rate and device. A positive RSKM
value indicates that the LVDS receiver can sample the data properly, whereas a
negative RSKM indicates that it cannot.
Figure 8–27. Differential High-Speed Timing Diagram and Timing Budget for Non-DPA Mode
Timing Diagram
External
Input Clock
Time Unit Interval (TUI)
Internal
Clock
TCCS
TCCS
Receiver
Input Data
RSKM
SW
RSKM
Internal
Clock
Falling Edge
Timing Budget
TUI
External
Clock
Clock Placement
Internal
Clock
Synchronization
Transmitter
Output Data
RSKM
RSKM
TCCS
TCCS
2
Receiver
Input Data
SW
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Source-Synchronous Timing Budget
8–35
For LVDS receivers, the Quartus II software provides an RSKM report showing the
SW, TUI, and RSKM values for non-DPA mode. You can generate the RSKM report by
executing the report_RSKM command in the TimeQuest Timing Analyzer. You can
find the RSKM report in the Quartus II compilation report under the TimeQuest
Timing Analyzer section.
1
In order to obtain the RSKM value, you must assign an appropriate input delay to the
LVDS receiver through the TimeQuest Timing Analyzer constraints menu.
For assigning input delay, follow these steps:
1. The Quartus II TimeQuest Timing Analyzer GUI has many options for setting the
constraints and analyzing the design. Figure 8–28 shows various commands on
the Constraints menu. For setting input delay, you must select the Set Input Delay
option.
Figure 8–28. Selection of Constraint Menu in TimeQuest Timing Analyzer
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Source-Synchronous Timing Budget
2. Figure 8–29 shows the setting parameters for the Set Input Delay option. The
clock name must reference the source synchronous clock that feeds the LVDS
receiver. Select the desired clock using the pull-down menu.
Figure 8–29. Input Time Delay Assignment Through TimeQuest Timing Analyzer
3. Figure 8–30 shows the Targets option. You can view a list of all available ports
using the List option in the Name Finder window.
Figure 8–30. Name Finder Window in Set Input Delay Option
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Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Source-Synchronous Timing Budget
8–37
4. Select the LVDS receiver serial input ports (from the list) according to the input
delay you set. Click OK.
5. In the Set Input Delay window, set the appropriate values in the Input Delay
Options section and Delay value.
6. Click Run to incorporate these values in the TimeQuest Timing Analyzer.
7. Assign the appropriate delay for all the LVDS receiver input ports following these
steps. If you have already assigned Input Delay and you need to add more delay
to that input port, use the Add Delay option in the Set Input Delay window.
1
If no input delay is set in the TimeQuest Timing Analyzer, the receiver
channel-to-channel skew (RCCS) defaults to zero. You can also directly set the input
delay in a Synopsys Design Constraint file (.sdc) using the set_input_delay
command.
f For more information about .sdc commands and the TimeQuest Timing Analyzer,
refer to the Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II
Development Software Handbook.
Example 8–2 shows the RSKM calculation.
Example 8–2. RSKM
Data Rate: 1 Gbps, Board channel-to-channel skew = 200 ps
For Stratix IV devices:
TCCS = 100 ps (pending characterization)
SW = 300 ps (pending characterization)
TUI = 1000 ps
Total RCCS = TCCS + Board channel-to-channel skew= 100 ps + 200 ps
= 300 ps
RSKM= TUI - SW - RCCS
= 1000 ps - 300 ps - 300 ps
= 400 ps > 0
Because the RSKM > 0 ps, receiver non-DPA mode must work correctly.
1
February 2011
You can also calculate RSKM using the steps described in “Guidelines for DPAEnabled Differential Channels” on page 8–38.
Altera Corporation
Stratix IV Device Handbook Volume 1
8–38
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Pin Placement Guidelines
Differential Pin Placement Guidelines
To ensure proper high-speed operation, differential pin placement guidelines have
been established. The Quartus II compiler automatically checks that these guidelines
are followed and issues an error message if they are not met.
This section is divided into pin placement guidelines with and without DPA usage
because DPA usage adds some constraints on the placement of high-speed differential
channels.
1
DPA-enabled differential channels refer to DPA mode or soft-CDR mode; DPA
disabled channels refer to non-DPA mode.
Guidelines for DPA-Enabled Differential Channels
The Stratix IV device family has differential receivers and transmitters in I/O banks
on the left and right sides of the device. Each receiver has a dedicated DPA circuit to
align the phase of the clock to the data phase of its associated channel. When you use
DPA-enabled channels in differential banks, you must adhere to the guidelines listed
in the following sections.
DPA-Enabled Channels and Single-Ended I/Os
When you enable a DPA channel in a bank, both single-ended I/Os and differential
I/O standards are allowed in the bank.
■
Single-ended I/Os are allowed in the same I/O bank, as long as the single-ended
I/O standard uses the same VCCIO as the DPA-enabled differential I/O bank.
■
Single-ended inputs can be in the same logic array block (LAB) row as a
differential channel using the SERDES circuitry.
■
DDIO can be placed within the same LAB row as a SERDES differential channel
but half rate DDIO (single data rate) output pins cannot be placed within the same
LAB row as a receiver SERDES differential channel. The input register must be
implemented within the FPGA fabric logic.
DPA-Enabled Channel Driving Distance
If the number of DPA channels driven by each left and right PLL exceeds 25 LAB
rows, Altera recommends implementing data realignment (bit slip) circuitry for all
the DPA channels.
Using Corner and Center Left and Right PLLs
If a differential bank is being driven by two left and right PLLs, where the corner left
and right PLL is driving one group and the center left and right PLL is driving
another group, there must be at least one row of separation between the two groups
of DPA-enabled channels (refer to Figure 8–31). The two groups can operate at
independent frequencies.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Pin Placement Guidelines
8–39
You do not need a separation if a single left and right PLL is driving the DPA-enabled
channels as well as DPA-disabled channels.
Figure 8–31. Corner and Center Left and Right PLLs Driving DPA-Enabled Differential I/Os in the
Same Bank
Corner
Left /Right PLL
Reference
CLK
DPA -enabled
Diff I/O
DPA - enabled
Diff I/O
DPA - enabled
Diff I/O
Channels
driven by
Corner
Left/Right
PLL
DPA - enabled
Diff I/O
DPA - enabled
Diff I/O
Diff I/O
One Unused
Channel for Buffer
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA -enabled
Diff I/O
Channels
driven by
Center
Left/Right
PLL
DPA- enabled
Diff I/O
Reference
CLK
Center
Left /Right PLL
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
8–40
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Pin Placement Guidelines
Using Both Center Left and Right PLLs
You can use both center left and right PLLs to drive DPA-enabled channels
simultaneously, as long as they drive these channels in their adjacent banks only, as
shown in Figure 8–32.
If one of the center left and right PLLs drives the top and bottom banks, you cannot
use the other center left and right PLL to drive differential channels, as shown in
Figure 8–32.
If the top PLL_L2 and PLL_R2 drives DPA-enabled channels in the lower differential
bank, the PLL_L3 and PLL_R3 cannot drive DPA-enabled channels in the upper
differential banks and vice versa. In other words, the center left and right PLLs cannot
drive cross-banks simultaneously, as shown in Figure 8–33.
Figure 8–32. Center Left and Right PLLs Driving DPA-Enabled Differential I/Os
Stratix IV Device Handbook Volume 1
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
Reference
CLK
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
Reference
CLK
Center
Left/Right PLL
(PLL_L2/PLL_R2)
Center
Left/Right PLL
(PLL_L2/PLL_R2)
Center
Left/Right PLL
(PLL_L3/PLL_R3)
Center
Left/Right PLL
(PLL_L3/PLL_R3)
Reference
CLK
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
Reference
CLK
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
February 2011
Unused
PLL
Altera Corporation
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Pin Placement Guidelines
8–41
Figure 8–33. Invalid Placement of DPA-Enabled Differential I/Os Driven by Both Center Left and
Right PLLs
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
Reference
CLK
Center Left /Right
PLL
Center Left /Right
PLL
Reference
CLK
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
DPA-enabled
Diff I/O
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
8–42
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Pin Placement Guidelines
Guidelines for DPA-Disabled Differential Channels
When you use DPA-disabled channels in the left and right banks of a Stratix IV
device, you must adhere to the guidelines in the following sections.
1
When using non-DPA receivers, you must drive the PLL from a dedicated and
compensated clock input pin. Compensated clock inputs are dedicated clock pins in
the same I/O bank as the PLL.
f For more information about dedicated and compensated clock inputs, refer to the
Clock Networks and PLLs in Stratix IV Devices chapter.
DPA-Disabled Channels and Single-Ended I/Os
The placement rules for DPA-disabled channels and single-ended I/Os are the same
as those for DPA-enabled channels and single-ended I/Os. For more information,
refer to “DPA-Enabled Channels and Single-Ended I/Os” on page 8–38.
DPA-Disabled Channel Driving Distance
Each left and right PLL can drive all the DPA-disabled channels in the entire bank.
Using Corner and Center Left and Right PLLs
You can use a corner left and right PLL to drive all transmitter channels and a center
left and right PLL to drive all DPA-disabled receiver channels within the same
differential bank. In other words, a transmitter channel and a receiver channel in the
same LAB row can be driven by two different PLLs, as shown in Figure 8–34.
A corner left and right PLL and a center left and right PLL can drive duplex channels
in the same differential bank, as long as the channels driven by each PLL are not
interleaved. Separation is not necessary between the group of channels driven by the
corner and center left and right PLLs, as shown in Figure 8–34 and Figure 8–35.
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Pin Placement Guidelines
8–43
Figure 8–34. Corner and Center Left and Right PLLs Driving DPA-Disabled Differential I/Os in the
Same Bank
Corner Left/Right
Corner Left/ Right
PLL
PLL
Reference
CLK
Diff RX
Diff TX
Diff RX
Diff TX
Diff RX
Diff TX
Diff RX
Diff TX
Diff RX
Diff TX
Diff RX
Diff TX
Diff RX
Diff TX
Diff RX
Diff TX
Diff RX
Diff TX
DPA-disabled
Diff I/O
Diff RX
Diff TX
DPA -disabled
Diff I /O
Reference
CLK
Center Left/Right
PLL
February 2011
Altera Corporation
Reference
CLK
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
Channels
driven by
Corner
Left/Right
PLL
No
separation
buffer
needed
Channels
driven by
Center
Left/Right
PLL
Reference
CLK
Center Left/Right
PLL
Stratix IV Device Handbook Volume 1
8–44
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Pin Placement Guidelines
Figure 8–35. Invalid Placement of DPA-Disabled Differential I/Os Due to Interleaving of Channels
Driven by the Corner and Center Left and Right PLLs
Corner Left/Right
PLL
Reference CLK
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
Reference CLK
Center Left/Right
PLL
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Differential Pin Placement Guidelines
8–45
Using Both Center Left and Right PLLs
You can use both center left and right PLLs simultaneously to drive DPA-disabled
channels on upper and lower differential banks. Unlike DPA-enabled channels, the
center left and right PLLs can drive cross-banks. For example, the upper-center left
and right PLL can drive the lower differential bank at the same time the lower center
left and right PLL is driving the upper differential bank, and vice versa, as shown in
Figure 8–36.
Figure 8–36. Both Center Left and Right PLLs Driving Cross-Bank DPA-Disabled Channels
Simultaneously
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
Reference
CLK
Center
Left/Right PLL
Center
Left/Right PLL
Reference
CLK
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
DPA-disabled
Diff I/O
February 2011
Altera Corporation
Stratix IV Device Handbook Volume 1
8–46
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Document Revision History
Document Revision History
Table 8–12 lists the revision history for this chapter.
Table 8–12. Document Revision History (Part 1 of 2)
Date
February 2011
March 2010
November 2009
June 2009
April 2009
March 2009
Version
Changes
■
Updated Table 8–10.
■
Updated the “Differential Transmitter”, “Non-DPA Mode”, “LVDS Interface with the Use
External PLL Option Enabled”, “Deserializer”, and “Guidelines for DPA-Disabled
Differential Channels” sections.
■
Applied new template.
■
Minor text edits.
■
Removed note 7 from Table 8–1 and Table 8–2.
■
Updated Figure 8–5.
■
Updated the “LVDS Channels” section.
■
Updated Table 8–7.
■
Added a note to the “LVDS Interface with the Use External PLL Option Enabled” and
“ALTLVDS Port List” sections.
■
Minor text edits.
■
Changed “dedicated LVDS” to “true LVDS”.
■
Removed EP4SE110, EP4SE290, and EP4SE680 devices.
■
Added EP4SE820 and Stratix IV GT devices.
■
Updated “LVDS Channels”, “Differential Transmitter”, “Soft-CDR Mode”, and “DPAEnabled Channels and Single-Ended I/Os” sections.
■
Updated Table 8–1, Table 8–2, Table 8–5, and Table 8–6.
■
Added Table 8–3 and Table 8–4.
■
Updated Example 8–1.
■
Updated Figure 8–22.
■
Minor text edits.
■
Added an introductory paragraph to increase search ability.
■
Minor text edits.
■
Updated “Introduction”.
■
Updated Figure 8–3.
■
Removed Table 8-5 and Table 8-6.
■
Updated “Introduction”, “Stratix IV LVDS Channels”, “Stratix IV Differential Transmitter”,
“Differential I/O Termination”, and “Dynamic Phase Alignment (DPA) Block” sections.
■
Updated Table 8–1, Table 8–2, Table 8–3, Table 8–4, and Table 8–7.
■
Added Table 8–5 and Table 8–6.
■
Updated Figure 8–2.
■
Removed “Referenced Documents” section.
3.2
3.1
3.0
2.3
2.2
2.1
Stratix IV Device Handbook Volume 1
February 2011
Altera Corporation
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Document Revision History
8–47
Table 8–12. Document Revision History (Part 2 of 2)
Date
Version
November 2008
May 2008
February 2011
2.0
1.0
Altera Corporation
Changes
■
Updated Figure 8–2, Figure 8–3, Figure 8–21, Figure 8–34.
■
Removed Figure 8–31.
■
Updated Table 8–1, Table 8–10.
■
Updated “Differential Pin Placement Guidelines” section.
Initial release.
Stratix IV Device Handbook Volume 1
8–48
Stratix IV Device Handbook Volume 1
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Document Revision History
February 2011
Altera Corporation
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