Intel 82547GI(EI), 82541(PI/GI/EI), 82541ER Gigabit Ethernet Controller Application Note
The 82547GI(EI)/82541(PI/GI/EI) family of Gigabit Ethernet Controllers requires an external EEPROM that details the LOM (LAN on Motherboard) configuration data. These EEPROM images include configuration information to optimize the device performance as it relates to the specific design. For these controllers, performance is enhanced if the EEPROM includes information on the system design, for example if a combination magnetic-jack is used, or if a discrete magnetic component is used.
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82547GI(EI)/82541(PI/GI/EI)/
82541ER EEPROM Map/
Programming Information Guide
Application Note (AP-446)
Revision Number 2.5
June 2008
82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
Information in this document is provided in connection with Intel
® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
The Intel product(s) described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.
This document and the software described in it are furnished under license and may only be used or copied in accordance with the terms of the license. The information in this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Intel Corporation. Intel Corporation assumes no responsibility or liability for any errors or inaccuracies that may appear in this document or any software that may be provided in association with this document. Except as permitted by such license, no part of this document may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without the express written consent of Intel Corporation.
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Application Note (AP-446)
82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
Revision History
Date
June 2008
May 2006
Apr 2005
Feb 2005
Nov 2004
Oct 2004
Apr 2004
Dec 2003
Aug 2003
Oct 2002
Revision
2.5
2.4
2.3
2.2
2.1
2.0
1.61
1.6
1.5
1.0
Description
Updated Word 21h bit definitions (changed word value to
93A7h).
Added lead-free version device ID for the 82541PI C0 to Table
7 and under “Component Identification Via Programming
Interface”.
Updated Word 0Ah bit assignments (Table 6, bits 10 and 3) to match EEPROM image.
• Updated bit assignments for Words 0Fh and 21h.
• Updated EEPROM bit assignments to match EEPROM images.
• Added “Only if instructed to do so” to section 1.2.9.
• Removed section 1.2.11.
• Changed Word 0A bits 3 and 10 settings from 0 to 1 to match example images.
• Added 82541PI stepping information.
• Added new EEPROM images.
Changed Section 1.0; added OEM Configuration and
EEPROM Image Version Sections.
Changed value of word 0x1f from “3649” to “0000”
Updated detail
Combined data from DOC 13401
Structure and grammar corrections
Initial release
Application Note (AP-446)
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Contents
EEPROM Image Version Fields (Word 05h)............................................................ 7
Subsystem ID (Word 0Bh) ....................................................................... 9
Subsystem Vendor ID (Word 0Ch) .......................................................... 9
Vendor ID (Word 0Eh) ............................................................................. 9
PHY Register Address Data (Words 10h, 11h, and 13h-1Eh) ............................... 10
1.2.23 Boot Agent Configuration Customization Options (Word 31h)............................... 19
1.2.24 Boot Agent Configuration Customization Options (Word 32h)............................... 20
Application Note (AP-446)
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Application Note (AP-446)
1.0
82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
Introduction
The 82547GI(EI)/82541(PI/GI/EI) family of Gigabit Ethernet Controllers requires an external
EEPROM that details the LOM (LAN on Motherboard) configuration data. These EEPROM images include configuration information to optimize the device performance as it relates to the specific design. For these controllers, performance is enhanced if the EEPROM includes information on the system design, for example if a combination magnetic-jack is used, or if a discrete magnetic component is used.
The 82547GI(EI)/82541(PI/GI/EI) family can use either a Microwire* or an SPI* EEPROM. The
EEPROM mode is selected on the EE_MODE input (Ball J4). This pin should be pulled low for
Microwire through a 1K Ohm resistor. For SPI mode, the pin can be left as a No Connect. The
82547GI(EI)/82541(PI/GI/EI) automatically reads several words after power-up to retrieve configuration information. The remainder of the EEPROM space is available to software for storing the MAC address, serial numbers, and additional information.
Intel has provided several reference EEPROM images located in Appendix A of this guide that can
be used to generate an initial EEPROM image for a particular system, including:
•
Systems with no management capability (integrated or discrete magnetics)
— These EEPROM images include no system management support, and the motherboard design uses an integrated magnetic and board connector for the LAN connection.
•
Systems that support ASF V1.0
•
Systems that support ASF V2.0
These EEPROM images include ASF V1.0 or ASF V2.0 system management support.
•
Systems that support basic (TCO Basic) and advanced (TCO Advanced) pass through mode.
— These EEPROM images include TCO Basic or TCO Advanced.
The 82541ER controller EEPROM map and image are explained in Appendix B
.
Any one of these images may be used to generate the system manufacturer’s custom EEPROM image. The hardware system manufacture will review this document and update the EEPROM image for their particular implementation. Any text editor may be used to update the EEPROM image file. Once the image is finalized, EEUPDATE.EXE may be used to program the image.
Comments in the file are acceptable as long as they are delimited with a semi-colon; a single semicolon is all that is required. EEUPDATE.EXE will update all of the checksums within the device during the programming process.
The EEPROM access algorithm programmed into the controllers are compatible with most, but not all, commercially available 3.3V Microwire* interface serial EEPROM devices, with 64 x 16 (or
256 x 16) organization and a 2 MHz speed rating. The controller’s EEPROM access algorithms drives extra pulses on the shift clock at the beginning and end of read and write cycles. The extra pulses may violate the timing specifications of some EEPROM devices. In selecting a serial
EEPROM, choose a device that specifies “don't care” shift clock states between accesses.
Application Note (AP-446)
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EEPROM Size
For non-manageability applications, a 64 register by 16-bit Microwire serial or SPI EEPROM. For
ASF 2.0 applications, the larger SPI EEPROM is required. For AoL/ASF 1.0, use at least a 4K SPI serial EEPROM. See table below for reference:
Management
No
ASF 1.0
ASF 2.0
TCO Basic
TCO Advanced
Microwire*
x
SPI
x x x x x
Notes
at least 1kbit at least 4kbit at least 8kbit at least 4kbit at least 64kbit
Microwire EEPROMs that have been found to work satisfactorily with the 82547GI(EI)/82541(PI/
GI/EI)/82541ER Gigabit Ethernet Controller for non-manageability applications are listed in
Table 1. Microwire 64 x 16 Serial EEPROMs (no management)
Manufacturer
Atmel
Catalyst
Manufacturer Part Number
AT93C46
CAT93C46
SPI EEPROMs that have been found to work satisfactorily with the 82547GI(EI)/82541(PI/GI/EI)
device for manageability applications are listed in Table 2 :
Table 2. Serial EEPROMs for the 82547GI(EI)/82541(PI/GI/EI) Controller (Management
Applications)
Size (Kbit) Manufacturer Part Number
Catalyst
Atmel
CAT9366S-TE13
AT93C66-10SI-2.7
STMicroElectronics 95010W6
Catalyst CAT25010S
Atmel AT25010N-10SI-2.7
SPI
STMicroElectronics 95040W6 SPI
Catalyst
Atmel
CAT25040S
AT25040N-10SI-2.7
SPI
SPI uWire uWire
SPI
SPI
STMicroElectronics 95080W6
Catalyst CAT250C80S
SPI
SPI
Atmel AT25080N-10SI-2.7
SPI
STMicroElectronics 95160W6 SPI
Catalyst CAT25C160S SPI
Interface
4
4
1
4
1
1
4
4
8
8
8
16
16
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82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
Table 2. Serial EEPROMs for the 82547GI(EI)/82541(PI/GI/EI) Controller (Management
Applications)
Size (Kbit) Manufacturer Part Number
Atmel AT25160N-10SI-2.7
SPI
STMicroElectronics 95320W6
Catalyst CAT25C320S
SPI
SPI
Atmel AT25320N-10SI-2.7
SPI
STMicroElectronics 95640W6 SPI
Catalyst
Atmel
25C640S
AT25640N-10SI-2.7
SPI
SPI
Interface
32
64
64
64
16
32
32
Nomenclature
•
Numbers without a suffix are decimal (base 10).
•
Numbers with a suffix of “h” are hexadecimal (base 16).
•
Numbers with a suffix of “b” are binary (base 2).
Component Identification Via Programming Interface
The 82547 controller stepping will be identified by the following register contents:
Stepping
82547EI - A0
82547EI - A1
82547EI - B0
82547EI - B0
82547GI - B1
8086h
8086h
8086h
8086h
8086h
Vendor ID Device ID
1019h
1019h
1019h
101Ah (mobile)
1075h
These devices also provide identification data through the Test Access Port (TAP).
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1.1
The 82541 controller stepping will be identified by the following register contents: a.
Stepping
82541EI - A0
82541EI - A1
82541EI - B0
82541EI - B0
82541GI - B1
82541GI - B1
82541PI - C0
82541PI - C0
Vendor ID
8086h
8086h
8086h
8086h
8086h
8086h
8086h
8086h
Device ID
1013h
1013h
1013h
1018h
1076h
1077h (mobile)
1076h
107Ch a
Lead-free version. See
Table 7 for default device ID values.
Note:
The 82541PI stepping is differentiated from the 82541GI stepping by revision ID and not by device
ID.
The 82541ER controller stepping is identified by the following register content:
Stepping
82541ER
Vendor ID
8086h
Device ID
1078h
This device also provides identification data through the Test Access Port (TAP).
EEPROM Map Information
Table 3 summarizes the full EEPROM map for the 82547GI(EI)/82541(PI/GI/EI) Gigabit Ethernet
Controller.
Table 3. 82547GI(EI)/82541(PI/GI/EI) EEPROM Memory Layout
HW/SW Reserved Area
00h
...
3Fh
40h
...
FFh
ASF 1.0
Legacy Manageability
100h
...
19F
Manageability Packet Filter data
1A0
...
EEPROM END
Loadable Manageability Firmware Code
NOTE:This map supports full ASF 2.0 manageability.
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82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
1.2
EEPROM Address Map
The following table is a more detailed EEPROM address map for the 82547GI(EI)/82541(PI/GI/
EI) Gigabit Ethernet Controllers. Each of the data words is described in the following subsections.
Note that these maps extend only through the address range for legacy manageability.
28
29
2A
2B
2C
24
25
26
27
10 - 11
12
13-1E
1F
20
21
22
23
E
F
C
D
A
B
8
9
3
4
5
6-7
0
1
2
Table 4. 82547GI(EI)/82541(PI/GI/EI) EEPROM Address Map (Sheet 1 of 2)
Word Description: High Byte Description: Low Byte
IA Byte 2
IA Byte 4
IA Byte 6
IA Byte 1
IA Byte 3
IA Byte 5
Compatibility High Byte Compatibility Low Byte
SW/HW Reserved
EEPROM Image Version
HW Reserved
PBA, Byte 1
PBA, Byte 3
Initial Control 1, High Byte
Subsystem ID, High Byte
PBA, Byte 2
PBA, Byte 4
Initial Control 1, Low Byte
Subsystem ID, Low Byte
Subsystem Vendor ID, High Byte Subsystem Vendor ID, Low Byte
Device ID, High Byte Device ID, Low Byte
Vendor ID, High Byte
Initial Control 2, High Byte
Vendor ID, Low Byte
Initial Control 2, Low Byte
PHY Registers
EEPROM Size
PHY Registers
IDDQ Configuration/CSA Port Config 1
Software Defined Pins Control Software Defined Pins Control
HW Reserved/CSA Port Config 2
D0 Power
Management Control
D3 Power
Management Control
Initial Control 3
IPv4 Address Byte 2
IPv4 Address Byte 4
IPv6 Address Byte 2
IPv6 Address Byte 4
IPv6 Address Byte 6
IPv6 Address Byte 8
IPv6 Address Byte 10
IPv6 Address Byte 12
SMB Address
IPv4 Address Byte 1
IPv4 Address Byte 3
IPv6 Address Byte 1
IPv6 Address Byte 3
IPv6 Address Byte 5
IPv6 Address Byte 7
IPv6 Address Byte 9
IPv6 Address Byte 11
Hardware
Access
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
Yes
No
No
No
No
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Table 4. 82547GI(EI)/82541(PI/GI/EI) EEPROM Address Map (Sheet 2 of 2)
Word
2D
2E
2F
30 - 3E
3F
40 - F7
F8 - FF
Description: High Byte Description: Low Byte
IPv6 Address Byte 14 IPv6 Address Byte 13
IPv6 Address Byte 16 IPv6 Address Byte 15
LED Configuration Defaults
Checksum, High Byte
PXE Configuration
Checksum, Low Byte
Configured by ASF software
Reserved for software use
Hardware
Access
Yes
Yes
Yes
No
No
Yes
Yes
NOTE: Values listed in the EEPROM map table are hexadecimal.
1.2.1
Ethernet Address (Words 00h - 02h)
The Ethernet Individual Address (IA) is a 6-byte field that must be unique for each Ethernet port
(and for each copy of the EEPROM image). The first three bytes are vendor specific. The value from this field is loaded into the Receive Address Register 0 (RAL0/RAH0). For a MAC address of
12-34-56-78-90-AB, words 0-2 should be loaded as follows:
•
Word 0 = 3412
•
Word 1 = 7856
•
Word 2 = AB90
Note:
These values are byte-swapped
1.2.2
Compatibility Fields (Word 03h)
Word 03h in the EEPROM image is reserved for compatibility information to be used by software drivers.
Table 5. Compatibility Fields (Word 03h)
a.
Bit
15:12
11
10
9
8
7:5
4
3
2
1:0
Name
Reserved
LOM Design 0 = No 1 = Yes (default)
Server Design 0 = No (Default) 1 = Yes
Client Design 0 = No 1 = Yes (Default)
OEM Design 0 = Intel Adapter 1 = OEM Adapter
Reserved
SMBus routed to Chipset a
0 = No 1 = Yes
Reserved
PCI Bridge Device Present 0 = No 1 = Yes
Reserved
The default is dependent upon whether system management is supported or not
Value
0000
1
0
1
1
000
1
0
0
00
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1.2.3
1.2.4
OEM Configuration Fields (Word 04h)
Word 04h in the EEPROM image is reserved for OEM configuration.
EEPROM Image Version Fields (Word 05h)
Word 05h in the EEPROM image is EEPROM image version.
15:12
11:8
7:0
Bit Name
EEPROM major version
EEPROM minor version
EEPROM fix
0000
0000
00000000
Value
1.2.5
PBA Number (Words 08h - 09h)
A nine-digit printed board assembly (PBA) number used for Intel manufactured adapter cards is stored in a four-byte field. Other hardware manufacturers may use these fields for other purposes.
The network driver should not rely on this field to identify the product or its capabilities.
1.2.6
Initialization Control Word 1 (Word 0Ah)
This is the first word read by the controller that contains initialization values to:
Set default values for some internal registers
Enable and disable specific features
Determine which PCI configuration space values will be loaded from the EEPROM
Table 6. Initialization Control Word 1 (Word 0Ah)
Bit
15:14
13
8
7
12
11
10
9
Name
Signature
64/32 BAR
Reserved
Reserved
Reserved
Reserved
Reserved
Internal
VREG
Power down
Control
Description
The Signature field contains a signature of 01b indicating a valid EEPROM. If this field contains a value other than 01b, the EEPROM is invalid and the values in the
EEPROM are not read. Therefore, default values are used for the configuration space IDs.
This bit indicates whether the device is using 32-bit or 64-bit memory mapping.
0 = 64-bit memory mapping (default)
1 = 32-bit memory mapping
82547GI Reserved. Default setting = 1
Reserved. Set to 0
Reserved. Set to 0
Reserved. Set to 1
Reserved. Set to 0
Reserved. Set to 0
This bit is used to define usage of internal 1.2V and 1.8V regulators to supply power
0 = Yes (Default)
1 = No (external regulators are being used)
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Table 6. Initialization Control Word 1 (Word 0Ah)
2
1
6:4
3
Bit
0
Name
Reserved
Reserved
Reserved
Subsystem and
Subsystem
Vendor ID
PCI Device and Vendor
ID
Description
Reserved. Set to 0
Reserved. Set to 1
Reserved. Set to 0
This bit indicates whether or not to load the Subsystem ID and Subsystem Vendor
ID from the EEPROM.
0 = Do not load the Subsystem and subsystem vendor ID from the EEPROM
1 = Load the Subsystem and subsystem vendor ID from the EEPROM (Default)
This bit indicates whether or not to load the Vendor ID and Device ID from the
EEPROM
0 = Do not load the Vendor ID from the EEPROM
1 = Load the Vendor ID from the EEPROM (Default
1.2.7
Identification Words (Words 0Bh - 0Eh)
These words contain the Subsystem ID, Subsystem Vendor ID, Device ID, and Vendor ID.
lists examples of the different identification word settings.
Table 7. Identification Words
Vendor ID
8086
Device ID
1013
Subsystem
Vendor ID
8086
Subsystem ID
1013
Comments
8086
8086
8086
8086
8086h
8086
8086
8086
8086
1018
1076
1077
1076
107C
1019
101A
1075
1078
8086
8086
8086
8086
8086
8086
8086
8086
8086
1018
1076
1077
1076
107C
1019
101A
1075
1078
82541EI LOM. Default value if
EEPROM not present.
82541EI. Mobile applications.
82541GI LOM. Default value if EEPROM not present.
82541GI. Mobile applications.
82541PI LOM. Default value if
EEPROM not present.
82541PI LF LOM. Default
Device ID and Subsystem ID values are 1076 if EEPROM is not present.
82547EI LOM. Default value if
EEPROM not present
82547EI. Mobile applications.
82547GI LOM. Default value if EEPROM not present.
82541ER LOM. Default value if EEPROM not present.
NOTE: The values in this table are in hexadecimal.
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1.2.7.1
Subsystem ID (Word 0Bh)
If the Signature bits (15:14) and Load Subsystem IDs bit (1) in word 0Ah are valid, this word will be read in to initialize the Subsystem ID.
1.2.7.2
Subsystem Vendor ID (Word 0Ch)
If the Signature bits (15:14) and Load Subsystem IDs bit (1) of word 0Ah are valid, this word will be read in to initialize the Subsystem Vendor ID.
1.2.7.3
Device ID (Word 0Dh)
If the Signature bits (15:14) and Load Vendor/Device IDs bit (0) of EEPROM word 0Ah are valid, this word will be read in to initialize the Device ID.
1.2.7.4
Vendor ID (Word 0Eh)
If the Signature bits (15:14) and Load Vendor/Device IDs bit (0) of EEPROM word 0Ah are valid, this word will be read in to initialize the Device ID.
1.2.8
Initialization Control Word 2 (Word 0Fh)
This is the second word read by the controller and contains additional initialization values to:
•
Set defaults for some internal registers
•
Enable and disable specific features
Table 8. Initialization Control Word 2 (Word 0Fh)
Bit
15
14
13:11
10:9
8
7
6:3
Name
APM PME# Enable
ASDE
Reserved
Flash Size
MAC Clock Speed
(82541PI/GI)
Reserved (82547GI/EI)
Reserved
Reserved
Description
This bit is the initial value of the Assert PME on APM Wake Up bit in the Wake Up Control Register (WUC.APMPME). It is typically set to 1 for Intel LAN adapters.
This bit reflects the initial value of the Auto-Speed Detection
Enable bit of the Device Control Register (CTRL). The hardware default value is 0 (the PHY tells MAC the speed).
Reserved. Set to 0.
This field indicates the Flash size:
00 = 64 Kbytes (hardware default)
01 = 128 Kbytes
10 = 256 Kbytes
11 = 512 Kbytes
These bits impact the requested memory space for the Flash and
Expansion ROM BARs in the PCI configuration space.
When programmed to 0, MAC runs at full speed.
When set as 1, MAC runs at 1/4 speed on any drop from
1000 mb/s.
Reserved. Set to 0
Reserved. Set to 0
Reserved. Set to 0
Application Note (AP-446)
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Table 8. Initialization Control Word 2 (Word 0Fh)
Bit
2
1
0
Name
Reserved
Reserved
Reserved (82547GI/EI)
8254EI
Reserved. Set to 0
Reserved. Set to 0
Reserved. Set to 0
Set to 0.
NOTE: The values in this table are hexadecimal.
Description
1.2.9
PHY Register Address Data (Words 10h, 11h, and 13h-1Eh)
These settings are specific to individual platform configurations and should not be altered from the reference designs unless you are instructed to do so. Refer to Appendix for reference settings specific to a particular platform design. Future Intel devices may use this space differently.
1.2.10
EEPROM size (word 12h)
This word is only applicable to SPI EEPROMS which are typically need for manageability applications. Unused bits are reserved and should be programmed to 0. Bits 15:13 and 8:0 are reserved. See the table below:.
Table 9. SPI EEPROM Size
Bits 12:10
000
001
010
011
100
101
110
111
Bit 9
1
1
1
1
0
1
1
1
EEPROM Size
(Bits)
1Kbit
4Kbit
8Kbit
16Kbit
32Kbit
64Kbit
128Kbit
Reserved
EEPROM Size (Bytes)
128byte
512byte
1Kbyte
2Kbyte
4Kbyte
8Kbyte
16Kbyte
Reserved
10
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82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
1.2.11
CSA Port Configuration 1 (Word 1Fh) (82547GI(EI) Only)
For the 82547GI(EI), this word controls the CSA hublink port configuration and must be programmed to 0000h for regular operation. Note that this word should maintain constant values.
Do not change any values unless you are instructed to do so.
Table 10. CSA Port Configuration 1
Bit
15
14:12
8:11
7
6:4
3:0
Name
Hub interface mode
CSA N-Comp Buffer Strength (MSBs)
CSA N-Comp buffer Strength (LSBs)
CSA R-Comp Not overridden
CSA P-Comp buffer strength (MSBs)
CSA P-Comp buffer (LSBs)
Description
4 bit =1 8 bit =0 (Default =0)
Default setting 0
Default setting 0
Default 0
Default 0
Default 0
1.2.12
Software Defined Pins Control (Word 20h)
Table 11. Software Defined Pins Control (Word 20h)
Bit
15
14
Name
SDPDIR[3]
SDPDIR[2]
13:10 Reserved
9 SDPDIR[1]
8
7
6
5:4
3
SDPDIR[0]
SDPVAL[3]
SDPVAL[2]
Reserved
EN_PHY_PWR_MGMT
Description
SDP3 Pin - Initial Direction. This bit configures the initial HW value of the SDP3_IODIR bit in the Extended Device Control
Register (CTRL_EXT) following powerup.
0 = In; 1 = Out
SDP2 Pin - Initial Direction. This bit configures the initial HW value of the SDP2_IODIR bit in the Extended Device Control
Register (CTRL_EXT) following powerup.
0 = In; 1 = Out
Reserved. Set to 0
SDP1 Pin - Initial Direction. This bit configures the initial HW value of the SDP1_IODIR bit in the Device Control Register
(CTRL) following powerup.
0 = In; 1 = Out
SDP0 Pin - Initial Direction. This bit configures the initial HW value of the SDP0_IODIR bit in the Device Control Register
(CTRL) following powerup.
0 = In; 1 = Out
SDP3 Pin - Initial Output Value. This bit configures the initial power-on value output on SDP3 (when configured as an output) by configuring the initial HW value of the SDP3_DATA bit in the
Extended Device Control Register (CTRL_EXT) after powerup.
SDP2 Pin - Initial Output Value. This bit configures the initial power-on value output on SDP2 (when configured as an output) by configuring the initial HW value of the SDP2_DATA bit in the
Extended Device Control Register (CTRL_EXT) after powerup.
Reserved. Set to 0
Configures the initial HW default value of this bit in the Device
Control Register (CTRL) following powerup.
Application Note (AP-446)
11
82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
Bit
2
1
0
Name Description
D3_COLD_WAKEUP_ADV_EN Configures the initial HW default value of the ADVD3WUC bit in the Device Control Register (CTRL) following powerup.
SDPVAL[1] SDP1 Pin - Initial Output Value. This bit configures the initial power-on value output on SDP1 (when configured as an output) by configuring the initial HW value of the SDP1_DATA bit in the
Device Control Register (CTRL) after powerup.
SDPVAL[0] SDP0 Pin - Initial Output Value. This bit configures the initial power-on value output on SDP0 (when configured as an output) by configuring the initial HW value of the SDP0_DATA bit in the
Device Control Register (CTRL) after powerup.
12
Application Note (AP-446)
82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
1.2.13
1.2.14
1.2.15
CSA Port Configuration 2 (word 21h) (82547EI/GI only)
This word controls the CSA port configuration and must be programmed to 93A7h for regular operation.
Table 12. CSA Port Configuration 2
Bit #
15:13
12
11:2
1
0
Description
Reserved
Reserved
Reserved
Dock/
Undock polarity
Reserved
Default
Set to 100
Set to 1
Set to 0011101001
1 (Indicates docked)
1
D0 Power (word 22h high byte)
If the signature bits are valid and Power Management is not disabled, then the value in this field is used in the PCI Power Management Data Register when the Data_Select field of the Power
Management Control/Status Register (PMCSR) is set to 0 or 4. It indicates the power usage and heat dissipation of the networking function (including the Ethernet controller and any other devices controlled by the chip in tenths of a watt. Example:
If Word 22 = 290E, POWER CONSUMPTION (in 1/10W, hex), then: bits 15:8 = 29h Power in D0a, 29h = 4.1W
bits 7:0 = 0Eh Power in D3h, 0Eh = 1.4W
D3 Power (word 22h low byte)
If the signature bits are valid and Power Management is not disabled, then the value in this field is used in the PCI Power Management Data Register when the Data_Select field of the Power
Management Control/Status Register (PMCSR) is set to 3 or 7. It indicates the power usage and heat dissipation of the networking function (including the Ethernet controller and any other devices controlled by the chip in tenths of a watt (see the example above:
).
Application Note (AP-446)
13
82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
1.2.16
Management Control (word 23h)
This word contains initial settings for the Management Control Register as well as valid bits for the
IPv4 Address and IPv6 Address.
Table 13. Management Control (word 23h)
Bit
15
14
13
12:10
9
8
7
6
5
1
0
4:3
2
Name
Reserved
Neighbor Discovery
Packets
Enable ARP Filtering
Reserved
Enable RMCP 0298h filtering
Enable RMCP 026F filtering
IPv6 Address Valid
IPv4 Address Valid
Flex Filter Enable
Reserved
Reset on ForceTCO
ASF Mode
SMBus Enable
Description
Reserved. Set to 0.
Initial value of MANC.NEIGHBOR_EN bit.
1 = IPv6 Neighbor Discovery packets are Management packets for delivery to external TCO controller (82559 mode).
0 = IPv6 Neighbor Discovery packets go to host memory. If SMBus is disabled, then program this bit to 0.
This bit controls the initial value of the MANC.ARP_EN bit.
1=Send ARP Request packets to SMBus (in 82559 mode after a
Receive Enable SMBus command enabling packet filtering) or automatically generate ARP Reply packets (in ASF mode)
0=Send ARP Request packets to host memory
Note: Refer to the ARP Support section of the Total Cost of Ownership
(TCO) System Management Bus Interface Application Note (AP-430) for the 82541xx controllers. This document provides information regarding the usage of flexible filters for handling ARP Request packets.
Reserved. Set to 0
This bit controls the initial value of the MANC.0298_EN bit, which permits sending UDP packets of port 0298h to the SMBus or ASF controller.
1 = Allow; 0 = Don’t allow
This bit controls the initial value of the MANC.RMCP_EN bit, which permits sending UDP packets of port 026Fh to the SMBus or ASF controller.
1 = Allow; 0 = Don’t allow
IPv6 Address in the IP Address EEPROM register is valid. This is written to bit 16 of the IP Address Valid (IPAV[16]) register.
IPv4 Address in the IP Address EEPROM register is valid. This is written to bit 0 of the IP Address Valid (IPAV[0]) register.
This bit enables the flexible filter loaded from the EEPROM.
0 = Disable, 1 = Enable
Reserved. Set to 0.
Reset the 82547EI on a ForceTCO SMBus Command with the “Force” bit set to 1 in 82559 mode, or on various conditions in ASF mode.
Program to 0 if SMBus is not used.
1=ASF mode, 0=82559 compatible mode
Enables SMBus functionality.
1 = Enable; 0 = Disable
14
Application Note (AP-446)
82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
1.2.17
Initialization Control 3 (Word 24h)
The word controls general initialization values.
82541PI(GI) / 82547PI(GI)
Bit
15:13
12
11
10
9:8
7:0
Name
Reserved
PCI Interrupt
Enable/Disable FLASH
Logic
Enable/Disable APM
Reserved
Reserved
Description
See configuration options in Appendix A
See configuration options in Appendix A
Set by IBA
See configuration options in Appendix A
See configuration options in Appendix A
See configuration options in Appendix A
82541EI / 82547EI
Bit
15:4
3
2
Name
Reserved
Enable/Disable FLASH
Logic
APM Enable
1:0 Reserved
Description
See configuration options in Appendix A
A value of 1 disables the FLASH logic. The expansion ROM and secondary FLASH access BARs in the PCI config space are disabled.
Initial value of Advanced Power Management Wake Up Enable in the
Wake Up Control Register (WUC.APME).
See configuration options in Appendix A
1.2.18
SMBus Slave Address (word 24h low byte)
Bit
7:1
0
Name
SMBus Slave Address
Reserved
Description
Contains the SMBus slave address for 82559 compatible SMBus mode. This must be 1100 100(b) for ASF mode.
Reserved. Set to 0
1.2.19
Note:
Note: This byte must be C8h for ASF mode.
IPv4 Address (words 25h-26h)
Not used – should be FFFFh
1.2.20
IPv6 Address (words 27h-2Eh)
Not used – should be FFFFh
Application Note (AP-446)
15
82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
1.2.21
LED Configuration Defaults (Word 2Fh)
This EEPROM word specifies the hardware defaults for the LED Control Register (LEDCTL) fields controlling the LED0 (LINK_UP) and LED2 (LINK_100) output behaviors.
A value of 0602h configures the LED behavior to be equivalent to a LAN port based on the legacy
82544EI/GC controller.
Table 14. LED Configuration (Word 0Fh)
Bit
15
14
13:12
11:8
7
6
5:4
3:0
Name Description
LED2 Blink This bit reflects the initial value of the LED2 blink field in the LED control register:
0 = Non-blinking
1 = Blinking
LED2 Invert This bit reflects the initial value of the LED2 invert field in the LED control register:
0 = Do not invert output (active low)
1 = Invert output
Reserved Reserved. Set to 0.
LED2 Mode This bit reflects the initial value of the LED2 mode field in the LED control register.
It specifies which event, state, or pattern will be displayed on LED2 (LINK_100) output. For example, a value of 0111 indicates 1000 Mbps link operation.
LED0 Blink This bit reflects the initial value of the LED0 blink field in the LED control register:
0 = Non-blinking
1 = Blinking
LED0 Invert This bit reflects the initial value of the LED0 invert field in the LED control register:
0 = Do not invert output (active low)
1 = Invert output
Reserved Reserved. Set to 0
LED0 Mode This bit reflects the initial value of the LED0 mode field in the LED control register.
It specifies which event, state, or pattern will be displayed on LED0 (LINK_UP) output. For example, a value of 0010 indicates activity.
1.2.22
Boot Agent Main Setup Options (Word 30h)
The boot agent software configuration is controlled by the EEPROM with the main setup options stored in word 30h. These options are those that can be changed by using the Control-S setup menu or by using the IBA Intel Boot Agent utility. Note that these settings only apply to Boot Agent software.
16
Application Note (AP-446)
82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
Table 15. Boot Agent Main Setup Options
Bit Name
15
14
PPB
EPB
Description
PXE Presence.
Setting this bit to 0b Indicates that the image in the FLASH contains a
PXE image.
Setting this bit to 1b indicates that no PXE image is contained.
The default for this bit is 0b in order to be backwards compatible with existing systems already in the field.
If this bit is set to 0b, EEPROM word 32h (PXE Version) is valid. When
EPB is set to 1 and this bit is set to 0, indicates that both images are present in the FLASH.
EFI Presence.
Setting this bit to 1b Indicates that the image in the FLASH contains an
EFI image.
Setting this bit to 0b indicates that no EFI image is contained.
The default for this bit is 0 in order to be backwards compatible with existing systems already in the field.
If this bit is set to 1b, EEPROM word 33h (EFI Version) is valid. When
PPB is set to 0b and this bit is set to 1b, indicates that both images
(PXE and EFI) are present in the FLASH.
13
12
11:10
9
8
Reserved
FDP
FSP
LWS
DSM
Reserved for future use. Set this bit to 0b.
Force Full Duplex.
a
Set this bit to 0b for half duplex; set to 1b for full duplex.
Note that this bit is a don’t care unless bits 10 and 11 are set.
Force Speed.
b
These bits determine speed. 01b = 10Mbs, 10b = 100Mbs, 11b = Not allowed.
All zeros indicate Auto-negotiate (the current bit state).
Note that bit 12 is a don’t care unless these bits are set.
Legacy OS Wakeup Support (for 82559-based adapters only).
If set to 1b, the agent enables PME in the adapter's PCI configuration space during initialization. This allows remote wakeup under legacy operating systems that don't normally support it. Note that enabling this bit makes the network controller technically non-compliant with the
ACPI specification.
0b = Disabled (Default Value)
1b = Enabled
Display Setup Message.
If this bit is set to 1b, the "Press Control-S" message appears after the title message.
The default for this bit is 1b.
Application Note (AP-446)
17
82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
Table 15. Boot Agent Main Setup Options
Bit Name
7:6
5
PT
LBS
Description
Prompt Time. These bits control how long the "Press Control-S" setup prompt message appears, if enabled by DIM.
00b = 2 seconds (default)
01b = 3 seconds
10b = 5 seconds
11b = 0 seconds
Note that the Ctrl-S message does not appear if 0 seconds prompt time is selected.
Local Boot Selection (OBSOLETE). In previous versions of the agent, this bit enables or disables local boot, if the DBS bit selects it.
The default for this bit is 1b; enable local booting. The boot agent, at runtime, no longer uses this bit.
4:3
2
DBS
BBS
Default Boot Selection. These bits select which device is the default boot device. These bits are only used if the agent detects that the BIOS does not support boot order selection or if the MODE field of word 31h is set to MODE_LEGACY.
00b = Network boot, then local boot
01b = Local boot, then network boot
10b = Network boot only
11b = Local boot only
BIOS Boot Specification (OBSOLETE). In previous versions of the agent, this bit enables or disables use of the BBS to determine boot order. If set to 1, the BIOS boot order is used, and the DBS bits are ignored. The boot agent at runtime no longer uses this bit. The runtime checks for BBS/PnP and the setting in the MODE field of word 31h are used instead.
a.
b.
1:0 PS
Protocol Select. These bits select the boot protocol.
00b = PXE (default value)
01b = RPL protocol
Other values are undefined.
This setting only applies to the Boot Agent software.
This setting only applies to the Boot Agent software.
18
Application Note (AP-446)
82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
1.2.23
Boot Agent Configuration Customization Options (Word 31h)
Word 31h contains settings that can be programmed by an OEM or network administrator to customize the operation of the software. These settings cannot be changed from within the Control-
S setup menu or the IBA Intel Boot Agent utility. The lower byte contains settings that would typically be configured by a network administrator using the Intel Boot Agent utility; these settings generally control which setup menu options are changeable. The upper byte are generally settings that would be used by an OEM to control the operation of the agent in a LOM environment, although there is nothing in the agent to prevent their use on a NIC implementation.
Table 16. Boot Agent Configuration Customization Options (Word 31h)
Bit Name Description
15:14
13:11
SIG
Reserved
Signature. These bits must be set to 1b to indicate that this word has been programmed by the agent or other configuration software.
Reserved for future use. Set these bits to 0b.
10:8
7:6
5
4
MODE
Reserved
DFU
DLWS
Selects the agent's boot order setup mode. This field changes the agent's default behavior in order to make it compatible with systems that do not completely support the BBS and PnP Expansion ROM standards. Valid values and their meanings are:
000b - Normal behavior. The agent attempts to detect BBS and PnP
Expansion ROM support as it normally does.
001b - Force Legacy mode. The agent does not attempt to detect BBS or PnP Expansion ROM supports in the BIOS and assumes the BIOS is not compliant. The BIOS boot order can be changed in the Setup
Menu.
010b - Force BBS mode. The agent assumes the BIOS is BBScompliant, even though it may not be detected as such by the agent's detection code. The BIOS boot order CANNOT be changed in the
Setup Menu.
011b - Force PnP Int18 mode. The agent assumes the BIOS allows boot order setup for PnP Expansion ROMs and hooks interrupt 18h (to inform the BIOS that the agent is a bootable device) in addition to registering as a BBS IPL device. The BIOS boot order CANNOT be changed in the Setup Menu.
100b - Force PnP Int19 mode. The agent assumes the BIOS allows boot order setup for PnP Expansion ROMs and hooks interrupt 19h (to inform the BIOS that the agent is a bootable device) in addition to registering as a BBS IPL device. The BIOS boot order CANNOT be changed in the Setup Menu.
101b - Reserved for future use. If specified, treated as value 000b.
110b - Reserved for future use. If specified, treated as value 000b.
111b - Reserved for future use. If specified, treated as value 000b.
Reserved for future use. Set these bits to 0b.
Disable FLASH Update.
If set to 1b, no updates to the FLASH image using PROSet is allowed.
The default for this bit is 0b; allow FLASH image updates using
PROSet.
Disable Legacy Wakeup Support.
If set to 1b, no changes to the Legacy OS Wakeup Support menu option is allowed.
The default for this bit is 0b; allow Legacy OS Wakeup Support menu option changes.
Application Note (AP-446)
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82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
Table 16. Boot Agent Configuration Customization Options (Word 31h)
Bit Name Description
3
2
1
0
DBS
DPS
DTM
DSM
Disable Boot Selection.
If set to 1b, no changes to the boot order menu option is allowed.
The default for this bit 0; allow boot order menu option changes.
Disable Protocol Select.
If set to 1b, no changes to the boot protocol is allowed.
The default for this bit is 0b; allow changes to the boot protocol.
Disable Title Message.
If set to 1b, the title message displaying the version of the boot agent is suppressed; the Control-S message is also suppressed. This is for
OEMs who do not wish the boot agent to display any messages at system boot.
The default for this bit is 0b; allow the title message that displays the version of the boot agent and the Control-S message.
Disable Setup Menu.
If set to 1b, no invoking the setup menu by pressing Control-S is allowed. In this case, the EEPROM can only be changed via an external program.
The default for this bit is 0b; allow invoking the setup menu by pressing
Control-S.
1.2.24
Boot Agent Configuration Customization Options (Word 32h)
Word 32h is used to store the version of the boot agent that is stored in the FLASH image. When the Boot Agent loads, it can check this value to determine if any first-time configuration needs to be performed. The agent then updates this word with its version. Some diagnostic tools to report the version of the Boot Agent in the FLASH also read this word. This word is only valid if the PPB is set to 0. Otherwise the contents may be undefined.
Table 17. Boot Agent Configuration Customization Options (Word 32h)
Bit Name Description
15:12
11:8
7:0
MAJOR
MINOR
BUILD
PXE boot agent major version. The default for these bits is 0b.
PXE boot agent minor version. The default for these bits is 0b.
PXE boot agent build number. The default for these bits is 0b.
20
Application Note (AP-446)
82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
1.2.25
IBA Capabilities (Word 33h)
Word 33h is used to enumerate the boot technologies that have been programmed into the FLASH.
It is updated by IBA configuration tools and is not updated or read by IBA.
Table 18. IBA Capabilities
Bit Name Description
15:14
13:5
4
3
2
1
0
SIG
Reserved
SAN
EFI
RPL
UNDI
BC
Signature. These bits must be set to 1b to indicate that this word has been programmed by the agent or other configuration software.
Reserved for future use. Set these bits to 0b.
SAN capability is present in FLASH.
0b = The SAN capability is not present (default).
1b = The SAN capability is present.
EFI UNDI capability is present in FLASH.
0b = The RPL code is not present (default).
1b = The RPL code is present.
RPL capability is present in FLASH.
1b = The RPL code is present (default).
0b = The RPL code is not present.
PXE/UNDI capability is present in FLASH.
1b = The PXE base code is present (default).
0b = The PXE base code is not present.
PXE base code is present in FLASH.
0b = The PXE base code is present (default).
1b = The PXE base code is not present.
1.2.26
1.2.27
1.2.28
Intel Boot Agent (Word 34h - 3Eh)
Reserved.
Checksum Word Calculation (Word 3Fh)
The Checksum word (3Fh) is calculated by adding all EEPROM words (00h - 3Fh), including the
Checksum word itself. The sum should equal BABAh. The initial value in the 16-bit summing register should be 0000h, and the carry bit should be ignored after each addition. This checksum is not accessed by the controller device. If CRC checking is required, it must be performed by software.
Word 40h - F7h
These words are configured by ASF software.
Application Note (AP-446)
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82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
1.2.29
ASF 2.0 Configuration Area Pointer (Word F8h)
This value holds a pointer (offset in 16 bit words from address 0) to the start of the ASF 2.0 configuration area [in the EEPROM]. If this pointer equals 0, the EEPROM will not contain an
ASF 2.0 configuration area. If the EEPROM contains an ASF 2.0 configuration area, this pointer will contain this area’s address.
Note:
A CRC field does not protect this pointer.
1.2.30
Code Upgrade Ara Pointer (Word F9h)
This value holds a pointer (offset in 16 bit words from address 0) to the start of the ASF 2.0 code upgrade area. If this pointer equals 0, the EEPROM will not contain a Code Upgrade area. If the
EEPROM contains a Code Upgrade area, this pointer will contain this area’s address.
Note:
A CRC field does not protect this pointer
22
Application Note (AP-446)
82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
Appendix A Sample Starter EEPROM Images
A.1
A.2
82541(PI/GI/EI) No Management and No Integrated
Magnetics
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
FFFF FFFF FFFF 0210 FFFF 1000 FFFF FFFF
FFFF FFFF 640B 1076 8086 1076 8086 B284
20DD 2222 0000 2F90 2380 0012 1E20 0012
1E20 0012 1E20 0012 1E20 0009 0200 0000
000C 93A6 280B 0000 0400 FFFF FFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF 0602
0100 4000 1210 4007 FFFF FFFF FFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
82547GI(EI) No Management and No Integrated Magnetics
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
FFFF FFFF FFFF 0B10 FFFF 2066 FFFF FFFF
FFFF FFFF 640B 1075 8086 1075 8086 B204
20DD 2222 0000 2F90 2380 0012 1E20 0012
1E20 0012 1E20 0012 1E20 0009 0200 0000
000C 93A7 290E 0000 0400 FFFF FFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF 0602
0100 4000 1210 4007 FFFF FFFF FFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
Application Note (AP-446)
23
82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
Appendix B 82541ER Programmers’ Supplement
The following table is a more detailed EEPROM address map for the 82541ER Gigabit Ethernet
Controller. Each of the data words is described in the following subsections.
29
2A
2B
2C
25
26
27
28
21
22
23
24
12
13-1E
1F
20
D
E
F
10 - 11
B
C
9
A
4
5
6-7
8
2
3
0
1
Table 19. 82541ER EEPROM Address Map
Word Description: High Byte Description: Low Byte
IA Byte 2
IA Byte 4
IA Byte 6
Compatibility High Byte
IA Byte 1
IA Byte 3
IA Byte 5
Compatibility Low Byte
HW Reserved
EEPROM Image Version
HW Reserved
PBA, Byte 1
PBA, Byte 3
Initial Control 1, High Byte
PBA, Byte 2
PBA, Byte 4
Initial Control 1, Low Byte
Subsystem ID, High Byte Subsystem ID, Low Byte
Subsystem Vendor ID, High Byte Subsystem Vendor ID, Low Byte
Device ID, High Byte
Vendor ID, High Byte
Initial Control 2, High Byte
Device ID, Low Byte
Vendor ID, Low Byte
Initial Control 2, Low Byte
Reserved
Reserved
Reserved
Reserved
Software Defined Pins Control Software Defined Pins Control
D0 Power
Reserved
Initial Control 3
HW Reserved/CSA Port Config 2
D3 Power
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Hardware
Access
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
No
No
No
No
Yes
Yes
Yes
No
24
Application Note (AP-446)
82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
Table 19. 82541ER EEPROM Address Map
Word Description: High Byte Description: Low Byte
2D
2E
2F
Reserved
Reserved
LED Configuration Defaults
30 - 3E Reserved
3F Checksum, High Byte
Reserved
Reserved
Checksum, Low Byte
NOTE: Values listed in the EEPROM map table are hexadecimal.
Hardware
Access
Yes
Yes
Yes
No
No
B.3
Ethernet Address (Words 00h - 02h)
The Ethernet Individual Address (IA) is a 6-byte field that must be unique for each Ethernet port
(and for each copy of the EEPROM image). The first three bytes are vendor specific. The value from this field is loaded into the Receive Address Register 0 (RAL0/RAH0). For a MAC address of
12-34-56-78-90-AB, words 0-2 should be loaded as follows:
•
Word 0 = 3412
•
Word 1 = 7856
•
Word 2 = AB90
Note:
These values are byte-swapped
B.4
Compatibility Fields (Word 03h)
Word 03h in the EEPROM image is reserved for compatibility information to be used by software drivers.
Table 20. Compatibility Fields (Word 03h)
Bit
15:12
11
10
9
8
7:5
4
3
2
1:0
Name
Reserved
LOM Design 0 = No 1 = Yes (default)
Server Design 0 = No (Default) 1 = Yes
Client Design 0 = No 1 = Yes (Default)
OEM Design 0 = Intel Adapter 1 = OEM Adapter
Reserved
Reserved
Reserved
PCI Bridge Device Present 0 = No 1 = Yes
Reserved
Value
1
000
0
0
0000
1
0
1
0
00
Application Note (AP-446)
25
82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
B.5
PBA Number (Words 08h - 09h)
A nine-digit printed board assembly (PBA) number used for Intel manufactured adapter cards is stored in a four-byte field. Other hardware manufacturers may use these fields for other purposes.
The network driver should not rely on this field to identify the product or its capabilities.
B.6
Initialization Control Word 1 (Word 0Ah)
This is the first word read by the controller that contains initialization values to:
Set default values for some internal registers
Enable and disable specific features
Determine which PCI configuration space values will be loaded from the EEPROM
Table 21. Initialization Control Word 1 (Word 0Ah)
Bit
15:14
13
Name
Signature
64/32 BAR
Description
The Signature field contains a signature of 01b indicating a valid EEPROM. If this field contains a value other than 01b, the EEPROM is invalid and the values in the
EEPROM are not read. Therefore, default values are used for the configuration space IDs.
This bit indicates whether the device is using 32-bit or 64-bit memory mapping.
0 = 64-bit memory mapping (default)
1 = 32-bit memory mapping
2
1
6:4
3
9
8
7
12
11
10
0
Reserved
Reserved
Reserved
Reserved
Reserved
Internal
VREG
Power down
Control
Reserved
Reserved
Reserved
Subsystem and
Subsystem
Vendor ID
PCI Device and Vendor
ID
Reserved. Set to 0
Reserved. Set to 0
Reserved. Set to 1
Reserved. Set to 0
Reserved. Set to 0
This bit is used to define usage of internal 1.2V and 1.8V regulators to supply power
0 = Yes (Default)
1 = No (external regulators are being used)
Reserved. Set to 0
Reserved. Set to 1
Reserved. Set to 0
This bit indicates whether or not to load the Subsystem ID and Subsystem Vendor
ID from the EEPROM.
0 = Do not load the Subsystem and subsystem vendor ID from the EEPROM
1 = Load the Subsystem and subsystem vendor ID from the EEPROM (Default)
This bit indicates whether or not to load the Vendor ID and Device ID from the
EEPROM
0 = Do not load the Vendor ID from the EEPROM
1 = Load the Vendor ID from the EEPROM (Default
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82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
B.7
Identification Words (Words 0Bh - 0Eh)
These words contain the Subsystem ID, Subsystem Vendor ID, Device ID, and Vendor ID. The table below is an example of settings for the 82541ER..
Table 22. Identification Words
Vendor ID
8086
Device ID
1078
Subsystem
Vendor ID
8086
Subsystem ID
1078
Comments
82541ER LOM. Default value if EEPROM not present
NOTE: The values in this table are hexadecimal.
B.7.1
B.7.2
B.7.3
B.7.4
Subsystem ID (Word 0Bh)
If the Signature bits (15:14) and Load Subsystem IDs bit (1) in word 0Ah are valid, this word will be read in to initialize the Subsystem ID.
Subsystem Vendor ID (Word 0Ch)
If the Signature bits (15:14) and Load Subsystem IDs bit (1) of word 0Ah are valid, this word will be read in to initialize the Subsystem Vendor ID.
Device ID (Word 0Dh)
If the Signature bits (15:14) and Load Vendor/Device IDs bit (0) of EEPROM word 0Ah are valid, this word will be read in to initialize the Device ID.
Vendor ID (Word 0Eh)
If the Signature bits (15:14) and Load Vendor/Device IDs bit (0) of EEPROM word 0Ah are valid, this word will be read in to initialize the Device ID.
B.8
Initialization Control Word 2 (Word 0Fh)
This is the second word read by the controller and contains additional initialization values to:
•
Set defaults for some internal registers
•
Enable and disable specific features
Application Note (AP-446)
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82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
Table 23. Initialization Control Word 2 (Word 0Fh)
Bit
15
14
13:12
11
10:9
8
2
1
7
6:3
0
Name Description
APM PME# Enable
ASDE
Pause Capability
This bit is the initial value of the Assert PME on APM Wake Up bit in the Wake Up Control Register (WUC.APMPME). It is typically set to 1 for Intel LAN adapters.
This bit reflects the initial value of the Auto-Speed Detection
Enable bit of the Device Control Register (CTRL). The hardware default value is 0 (the PHY tells MAC the speed).
This bit reflects the pause capability for the advertised configuration base page and is mapped to TXCW[8:7].
Reserved
Flash Size
Reserved. Set to 0
This field indicates the Flash size:
00 = 64 Kbytes (hardware default)
01 = 128 Kbytes
10 = 256 Kbytes
11 = 512 Kbytes
These bits impact the requested memory space for the Flash and
Expansion ROM BARs in the PCI configuration space.
MAC Clock Speed (82541EI) When programmed to 0, MAC runs at full speed.
When set as 1, MAC runs at 1/4 speed on any drop from
1000 mb/s.
Reserved
Reserved
Reserved
Force CSR Read Split
Reserved
Reserved. Set to 1.
Reserved. Set to 0.
Reserved. Set to 1.
Used to force all device control/status register-reads to be split when operating in a PCI-X environment. When set to 0 (default), certain critical registers are decoded for non-split access.
Set to 0.
NOTE: Values in this table are hexadecimal
B.9
EEPROM Size (word 12h)
This word is only applicable to SPI EEPROMS which are typically need for manageability applications. Unused bits are reserved and should be programmed to 0. Bits 8:0 are reserved. See the table below:.
Table 24. SPI EEPROM Size
Bits 12:10
000
001
010
011
100
Bit 9
0
1
1
1
1
EEPROM Size
(Bits)
1Kbit
4Kbit
8Kbit
16Kbit
32Kbit
EEPROM Size (Bytes)
128byte
512byte
1Kbyte
2Kbyte
4Kbyte
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82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
Table 24. SPI EEPROM Size
Bits 12:10
101
110
111
Bit 9
1
1
1
EEPROM Size
(Bits)
64Kbit
128Kbit
Reserved
EEPROM Size (Bytes)
8Kbyte
16Kbyte
Reserved
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82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
B.10
Software Defined Pins Control (word 20h)
Bit Name Description
15
14
13:10
9
8
7
6
5:4
3
2
1
0
SDPDIR[3]
SDPDIR[2]
Reserved
SDPDIR[1]
SDP3 Pin - Initial Direction. This bit configures the initial HW value of the SDP3_IODIR bit in the Extended Device Control
Register (CTRL_EXT) following powerup.
0 = In; 1 = Out
SDP2 Pin - Initial Direction. This bit configures the initial HW value of the SDP2_IODIR bit in the Extended Device Control
Register (CTRL_EXT) following powerup.
0 = In; 1 = Out
Reserved. Set to 0
SDP1 Pin - Initial Direction. This bit configures the initial HW value of the SDP1_IODIR bit in the Device Control Register
(CTRL) following powerup.
0 = In; 1 = Out
SDPDIR[0]
SDPVAL[3]
SDPVAL[2]
SDP0 Pin - Initial Direction. This bit configures the initial HW value of the SDP0_IODIR bit in the Device Control Register
(CTRL) following powerup.
0 = In; 1 = Out
SDP3 Pin - Initial Output Value. This bit configures the initial power-on value output on SDP3 (when configured as an output) by configuring the initial HW value of the SDP3_DATA bit in the
Extended Device Control Register (CTRL_EXT) after powerup.
SDP2 Pin - Initial Output Value. This bit configures the initial power-on value output on SDP2 (when configured as an output) by configuring the initial HW value of the SDP2_DATA bit in the
Extended Device Control Register (CTRL_EXT) after powerup.
Reserved. Set to 0 Reserved
EN_PHY_PWR_MGMT Configures the initial HW default value of this bit in the Device
Control Register (CTRL) following powerup.
D3_COLD_WAKEUP_ADV_EN Configures the initial HW default value of the ADVD3WUC bit in the Device Control Register (CTRL) following powerup.
SDPVAL[1] SDP1 Pin - Initial Output Value. This bit configures the initial power-on value output on SDP1 (when configured as an output) by configuring the initial HW value of the SDP1_DATA bit in the
Device Control Register (CTRL) after powerup.
SDPVAL[0] SDP0 Pin - Initial Output Value. This bit configures the initial power-on value output on SDP0 (when configured as an output) by configuring the initial HW value of the SDP0_DATA bit in the
Device Control Register (CTRL) after powerup.
B.11
D0 Power (word 22h high byte)
If the signature bits are valid and Power Management is not disabled, then the value in this field is used in the PCI Power Management Data Register when the Data_Select field of the Power
Management Control/Status Register (PMCSR) is set to 0 or 4. It indicates the power usage and heat dissipation of the networking function (including the Ethernet controller and any other devices controlled by the chip in tenths of a watt. Example:
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Application Note (AP-446)
82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
B.12
B.13
If Word 22 = 290E, POWER CONSUMPTION (in 1/10W, hex), then: bits 15:8 = 29h Power in D0a, 29h = 4.1W
bits 7:0 = 0Eh Power in D3h, 0Eh = 1.4W
D3 Power (word 22h low byte)
If the signature bits are valid and Power Management is not disabled, then the value in this field is used in the PCI Power Management Data Register when the Data_Select field of the Power
Management Control/Status Register (PMCSR) is set to 3 or 7. Its indicates the power usage and heat dissipation of the networking function (including the Ethernet controller and any other devices
controlled by the chip in tenths of a watt (see Section B.11
).
Initialization Control 3 (Word 24h)
The word controls general initialization values.
82541ER
Bit
15:13
12
11
10
9:8
7:0
Name
Reserved
PCI Interrupt
Enable/Disable FLASH
Logic
Enable/Disable APM
Reserved
Reserved
Description
See configuration options in
See configuration options in
Set by IBA
See configuration options in
See configuration options in
See configuration options in
B.14
LED Configuration Defaults (Word 2Fh)
This EEPROM word specifies the hardware defaults for the LED Control Register (LEDCTL) fields controlling the LED0 (LINK_UP) and LED2 (LINK_100) output behaviors.
A value of 0602h configures the LED behavior to be equivalent to a LAN port based on the legacy
82544EI/GC controller.
Table 25. LED Configuration (Word 0Fh)
Bit
15
14
13:12
Name Description
LED2 Blink This bit reflects the initial value of the LED2 blink field in the LED control register:
0 = Non-blinking
1 = Blinking
LED2 Invert This bit reflects the initial value of the LED2 invert field in the LED control register:
0 = Do not invert output (active low)
1 = Invert output
Reserved Reserved. Set to 0.
Application Note (AP-446)
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82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
Table 25. LED Configuration (Word 0Fh)
Bit
11:8
7
6
5:4
3:0
Name Description
LED2 Mode This bit reflects the initial value of the LED2 mode field in the LED control register.
It specifies which event, state, or pattern will be displayed on LED2 (LINK_100) output. For example, a value of 0111 indicates 1000 Mbps link operation.
LED0 Blink This bit reflects the initial value of the LED0 blink field in the LED control register:
0 = Non-blinking
1 = Blinking
LED0 Invert This bit reflects the initial value of the LED0 invert field in the LED control register:
0 = Do not invert output (active low)
1 = Invert output
Reserved Reserved. Set to 0
LED0 Mode This bit reflects the initial value of the LED0 mode field in the LED control register.
It specifies which event, state, or pattern will be displayed on LED0 (LINK_UP) output. For example, a value of 0010 indicates activity.
B.15
Checksum Word Calculation (Word 3Fh)
The Checksum word (3Fh) is calculated by adding all EEPROM words (00h - 3Fh), including the
Checksum word itself. The sum should equal BABAh. The initial value in the 16-bit summing register should be 0000h, and the carry bit should be ignored after each addition. This checksum is not accessed by the controller device. If CRC checking is required, it must be performed by software.
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82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
B.16
82541ER No Management and No Integrated Magnetics
0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F
FFFF FFFF FFFF 0300 FFFF 1000 FFFF FFFF
FFFF FFFF 640B 1078 8086 1078 8086 3284
20DD 5555 0000 2F90 3200 0012 1E20 0012
1E20 0012 1E20 0012 1E20 0009 0200 0000
000C 93A6 280B 0000 0800 FFFF FFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF 0602
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
FFFF FFFF FFFF FFFF FFFF FFFF FFFF FFFF
Application Note (AP-446)
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82547GI(EI)/82541(PI/GI/EI)/82541ER EEPROM Map/Programming Information Guide
Note:
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34
Application Note (AP-446)
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Key features
- Microwire or SPI EEPROM support
- EEPROM image optimization for performance
- Reference EEPROM image for various configurations
- Supports manageability and non-manageability applications
- Legacy manageability support (82559 compatible mode)
- ASF 2.0 manageability support
- TCO Basic and TCO Advanced pass through mode