UPD78070A Data Sheet

To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

st

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both companies.

Therefore, although the old company name remains in this document, it is a valid

Renesas

Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

st

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.

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(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries.

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DATA SHEET

MOS INTEGRATED CIRCUIT

m

PD78070A

8-BIT SINGLE-CHIP MICROCONTROLLER

DESCRIPTION

The m

PD78070A is a limited-function product from which the internal ROM of the m

PD78078 subseries has been removed. Through interchangeable external ROM, program maintenance can be performed easily. Besides a highspeed, high-performance CPU, this microcontroller has an internal RAM, I/O ports, 8-bit resolution A/D converter, 8-bit resolution D/A converter, timer, serial interface, real-time output port, interrupt control, and various other peripheral hardware.

Detailed information about product features and specifications can be found in the following documents. Be sure to read the following documents before starting design.

m

PD78070A, 78070AY User’s Manual: U10200E

78K/0 Series User’s Manual – Instructions: IEU-1372

FEATURES

Internal high-capacity RAM

Internal high-speed RAM : 1024 bytes

Buffer RAM: 32 bytes

Two packages

100-pin plastic QFP (fine pitch) (14 x 14 mm)

100-pin plastic QFP (14 x 20 mm)

External memory expansion space : 64 Kbytes

Instruction execution time can be varied from high-speed (0.4 m s) to ultra-low-speed (122 m s)

APPLICATIONS

I/O ports: 61 (N-ch open-drain : 8)

8-bit resolution A/D converter : 8 channels

8-bit resolution D/A converter : 2 channels

Serial interface : 3 channels

• 3-wire/SBI/2-wire mode : 1 channel

• 3-wire mode : 1 channel

• 3-wire/UART mode : 1 channel

Timer : 7 channels

Power supply voltage : V

DD

= 2.7 to 5.5 V

CD-ROM driver, printer, PPC, etc.

ORDERING INFORMATION

Part Number m

PD78070AGC-7EA m

PD78070AGF-3BA

Package

100-pin plastic QFP (Fine pitch) (14

¥

14 mm, Resin thickness 1.45 mm)

100-pin plastic QFP (14

¥

20 mm, Resin thickness 2.7 mm)

Document No.

U10326EJ1V0DS00 (1st edition)

Date Published April 1996 P

Printed in Japan

The information in this document is subject to change without notice.

The mark

shows major revised points.

©

2

m

PD78070A

78K/0 Series Development

The following shows the 78K/0 series products development. Subseries names are shown inside frames.

78K/0 series

Products in mass production

Products under development

Y subseries products are compatible with I

2

C bus.

100-pin

100-pin

80-pin

80-pin

64-pin

64-pin

64-pin

64-pin

42/44pin

Control

µ

PD78078

µ

PD78070A

µ

PD78058F

µ

PD78054

µ

PD78018F

µ

PD78014

µ

PD780001

µ

PD78002

µ

PD78083

100-pin

80-pin

64-pin

FIP

TM drive

µ

PD780208

µ

PD78044A

µ

PD78024

µ

PD78078Y

µ

PD78070AY

µ

PD78058FY

µ

PD78054Y

µ

PD78018FY

µ

PD78014Y

µ

PD78002Y

100-pin

100-pin

100-pin

LCD drive

µ

PD780308

µ

PD78064B

µ

PD78064

µ

µ

PD780308Y

PD78064Y

Basic subseries for control

On-chip UART, capable of operating at a low voltage (1.8 V)

Basic subseries for driving FIP, Display output total: 26

Basic subseries for driving LCDs, On-chip UART

80-pin

IEBus

TM

supported

µ

PD78098

64-pin

LV

µ

PD78P0914 PWM output, LV digital code decoder, and on-chip Hsync counter

m

PD78070A

The following table lists the main functional differences between subseries products.

Function ROM

Subseries name capacity

Control

FIP driving

LCD driving

IEBus

Timer

8-bit m

PD78078 32 K-60 K m

PD78070A –

4ch m

PD78058F 48 K-60 K 2ch m

PD78054 16 K-60 K m

PD78018F 8 K-60 K m

PD78014 8 K-32 K m

PD780001 8 K m

PD78002 m

PD78083

8 K-16 K m

PD780208 32 K-60 K 2ch m

PD78044A 16 K-40 K m

PD78024 24 K-32 K m

PD780308 48 K-60 K 2ch m

PD78064B 32 K m

PD78064 16 K-32 K m

PD78098 32 K-60 K 2ch supported

LV m

PD78P0914 32 K 6ch

8-bit 8-bit Serial Interface I/O V

DD

16-bit Watch WDT A/D D/A

External

MIN. Value Expansion

1ch 1ch 1ch 8ch 2ch 3ch (UART: 1ch) 88

61

69

1.8 V

2.7 V

Available

– 2ch 53

2.0 V

1.8 V

2.7 V

1ch

1ch

1ch –

– 8ch

1ch 1ch 8ch –

1ch 1ch 8ch –

1ch 39

53

1ch (UART: 1ch) 33

2ch 74

68

54

3ch (UART: 1ch) 57

2ch (UART: 1ch)

1.8 V

2.7 V

1.8 V

2.0 V

Available

1ch

1ch

1ch

1ch

8ch

8ch

2ch

3ch (UART: 1ch) 69

2ch 54

2.7 V

4.5 V

Available

Available

3

4

m

PD78070A

FUNCTION DESCRIPTION

Item

Internal memory ROM

Function

Not provided

Internal high-speed 1024 bytes

RAM

Memory space

General registers

Instruction cycle

Instruction set

I/O ports

A/D converter

D/A converter

Serial interface

Buffer RAM 32 bytes

On-chip instruction execution time setting function

When main system 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (@ 5.0 MHz) clock is selected

64 Kbytes

8 bits

¥

32 registers (8 bits

¥

8 registers

¥

4 banks)

When subsystem 122 m s (@ 32.768 kHz) clock is selected

• 16-bit operation

• Multiply/divide (8 bits

¥

8 bits, 16 bits

Þ

8 bits)

• Bit manipulation (set, reset, test, Boolean operation)

• BCD adjust, etc.

Total

• CMOS input

• CMOS I/O

: 61

: 2

: 51

• N-ch open-drain I/O

• 8-bit resolution

¥

8 channels

• 8-bit resolution

¥

2 channels

: 8

• 3-wire/SBI/2-wire bus mode selectable: 1 channel

Timer

• 3-wire mode (on-chip max. 32-byte automatic data transmit/receive function):

1 channel

• 3-wire/UART mode selectable: 1 channel

• 16-bit timer/event counter: 1 channel

• 8-bit timer/event counter: 4 channels

• Watch timer: 1 channel

• Watchdog timer: 1 channel

5 (14-bit PWM output

¥

1, 8-bit PWM output

¥

2)

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz

Timer output

Clock output

Buzzer output

Vectored interrupts

Maskable interrupts

(@ 5.0-MHz operation with main system clock)

32.768 kHz (@ 32.768-kHz operation with subsystem clock)

1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@ 5.0-MHz operation with main system clock)

Internal : 15, external : 7

Non-maskable interInternal : 1 rupts

Software interrupts Internal : 1

Test input

Power supply voltage

Internal : 1

Package

V

DD

= 2.7 to 5.5 V

• 100-pin plastic QFP (Fine pitch) (14

¥

14 mm, Resin thickness 1.45 mm)

• 100-pin plastic QFP (14

¥

20 mm, Resin thickness 2.7 mm)

m

CONTENTS

1.

PIN CONFIGURATION (TOP VIEW) ... 7

2.

BLOCK DIAGRAM ... 10

3.

PIN FUNCTIONS ... 11

3.1 Port Pins ... 11

3.2 Non-port Pins ... 13

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ... 15

4.

MEMORY SPACE ... 19

5.

PERIPHERAL HARDWARE FUNCTIONS ... 20

5.1 Ports ... 20

5.2 Clock Generator ... 21

5.3 Timer/Event Counter ... 22

5.4 Clock Output Control Circuit ... 24

5.5 Buzzer Output Control Circuit ... 25

5.6 A/D Converter ... 25

5.7 D/A Converter ... 25

5.8 Serial Interfaces ... 26

5.9 Real-Time Output Port ... 28

6.

INTERRUPT FUNCTIONS AND TEST FUNCTION ... 29

6.1 Interrupt Functions ... 29

6.2 Test Function ... 33

7.

EXTERNAL DEVICE EXPANSION FUNCTIONS ... 34

8.

STANDBY FUNCTION ... 34

9.

RESET FUNCTION ... 34

10. INSTRUCTION SET ... 35

11. ELECTRICAL SPECIFICATIONS... 38

12. PACKAGE DRAWINGS ... 63

13. RECOMMENDED SOLDERING CONDITIONS ... 65

m m

PD78070A

5

6

APPENDIX A. DEVELOPMENT TOOLS ... 67

APPENDIX B. RELATED DOCUMENTS ... 69

m

PD78070A

m

PD78070A

1.

PIN CONFIGURATION (Top View)

• 100-pin plastic QFP (Fine pitch) (14

¥

14 mm) m

PD78070AGC-7EA

P14/ANI4

P15/ANI5

P16/ANI6

P17/ANI7

AV

SS

P130/ANO0

P131/ANO1

AV

REF1

P70/SI2/R

X

D

P71/SO2/T

X

D

P72/SCK2/ASCK

V

SS

P20/SI1

P21/SO1

P22/SCK1

P23/STB

P24/BUSY

P25/SI0/SB0

P26/SO0/SB1

P27/SCK0

A0

A1

A2

A3

A4

7

8

9

3

4

5

6

100 99 98979695 94 93 92 9190 89 88 87 86 85 8483 8281 80 79 7877 76

1

2

75

74

73

72

71

70

69

68

67

18

19

20

21

22

10

11

12

13

14

15

16

17

23

24

53

52

25 51

26 27 28293031 32 3334 35 36 37 38 39 40 41 4243 4445 46 47 4849 50

58

57

56

55

54

66

65

64

63

62

61

60

59

P122/RTP2

P121/RTP1

P120/RTP0

P96

P95

P94

P93

P92

P91

P90

P37

P36/BUZ

P35/PCL

P34/TI2

P33/TI1

P32/TO2

P31/TO1

P30/TO0

P103

P102

P101/TI6/TO6

P100/TI5/TO5

ASTB

P66/WAIT

WR

Cautions 1. Connect IC (Internally Connected) pin directly to V

SS

.

2. Connect AV

DD

pin to V

DD

.

3. Connect AV

SS

pin to V

SS

.

7

m

PD78070A

• 100-pin plastic QFP (14

¥

20 mm) m

PD78070AGF-3BA

P120/RTP0

P121/RTP1

P122/RTP2

P123/RTP3

P124/RTP4

P125/RTP5

P126/RTP6

P127/RTP7

XT1/P07

RESET

P00/INTP0/TI00

P01/INTP1/TI01

P02/INTP2

P03/INTP3

P04/INTP4

P05/INTP5

IC

X2

X1

V

DD

XT2

P06/INTP6

AV

DD

AV

REF0

P10/ANI0

P11/ANI1

P12/ANI2

P13/ANI3

P14/ANI4

P15/ANI5

5

6

7

8

2

3

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

1 80

4

79

78

77

76

75

74

73

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29 52

30 51

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

56

55

54

53

60

59

58

57

67

66

65

64

63

62

61

72

71

70

69

68

A10

A9

A8

AD7

AD6

AD5

AD4

AD3

A14

V

SS

A13

A12

A11

AD2

AD1

AD0

A7

A6

A5

A4

A3

A2

P66/WAIT

WR

RD

P63

P62

P61

P60

A15

8

Cautions 1. Connect IC (Internally Connected) pin directly to V

SS

.

2. Connect AV

DD

pin to V

DD

.

3. Connect AV

SS

pin to V

SS

.

m

PD78070A

P00-P07

P10-P17

P20-P27

P30-P37

P60-P63, P66

P70-P72

P90-P96

P100-P103

P120-P127

P130, P131

: Port0

: Port1

: Port2

: Port3

: Port6

: Port7

: Port9

: Port10

: Port12

: Port13

RTP0-RTP7

INTP0-INTP6

TI00, TI01

: Real-time Output Port

: Interrupt from Peripherals

: Timer Input

TI1, TI2, TI5, TI6 : Timer Input

TO0-TO2, TO5, TO6 : Timer Output

SB0, SB1 : Serial Bus

SI0-SI2

SO0-SO2

SCK0-SCK2

RxD

TxD

ASCK

: Serial Input

: Serial Output

: Serial Clock

: Receive Data

: Transmit Data

: Asynchronous Serial Clock

PCL

BUZ

STB

BUSY

AD0-AD7

A0-A15

RD

WR

WAIT

ASTB

: Programmable Clock

: Buzzer Clock

: Strobe

: Busy

: Address/Data Bus

: Address Bus

: Read Strobe

: Write Strobe

: Wait

: Address Strobe

X1, X2

XT1, XT2

RESET

ANI0-ANI7

ANO0, ANO1

AV

DD

: Crystal (Main System Clock)

: Crystal (Subsystem Clock)

: Reset

: Analog Input

: Analog Output

: Analog Power Supply

AV

SS

: Analog Ground

AV

REF0,

AV

REF1

: Analog Reference Voltage

V

DD

: Power Supply

V

SS

IC

: Ground

: Internally Connected

9

2.

BLOCK DIAGRAM

TO0/P30

TI00/INTP0/P00

TI01/INTP1/P01

TO1/P31

TI1/P33

TO2/P32

TI2/P34

TI5/TO5/P100

TI6/TO6/P101

16-bit TIMER/

EVENT COUNTER

8-bit TIMER/

EVENT COUNTER 1

8-bit TIMER/

EVENT COUNTER 2

8-bit TIMER/

EVENT COUNTER 5

8-bit TIMER/

EVENT COUNTER 6

WATCHDOG TIMER

WATCH TIMER

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27

SI1/P20

SO1/P21

SCK1/P22

STB/P23

BUSY/P24

SI2/RxD/P70

SO2/TxD/P71

SCK2/ASCK/P72

ANI0/P10-

ANI7/P17

AV

DD

AV

SS

AV

REF0

ANO0/P130,

ANO1/P131

AV

SS

AV

REF1

INTP0/P00-

INTP6/P06

BUZ/P36

PCL/P35

SERIAL

INTERFACE 0

SERIAL

INTERFACE 1

SERIAL

INTERFACE 2

A/D CONVERTER

D/A CONVERTER

INTERRUPT

CONTROL

BUZZER OUTPUT

CLOCK OUTPUT

CONTROL

10

78K/0

CPU CORE

RAM

V

DD

V

SS

IC m

PD78070A

PORT 0

PORT 1

PORT 2

P00

P01-P06

P07

P10-P17

P20-P27

P30-P37

PORT 3

PORT 6

PORT 7

P60-P63, P66

P70-P72

P90-P96

PORT 9

PORT 10

PORT 12

P100-P103

P120-P127

PORT 13

P130, P131

REAL-TIME

OUTPUT PORT

EXTERNAL

ACCESS

RTP0/P120-

RTP7/P127

AD0-AD7

A0-A15

RD

WR

WAIT/P66

SYSTEM

CONTROL

RESET

X1

X2

XT1/P07

XT2

m

PD78070A

P34

P35

P36

P37

P30

P31

P32

P33

P24

P25

P26

P27

P20

P21

P22

P23

3.

PIN FUNCTIONS

3.1

Port Pins (1/2)

P03

P04

P05

P06

Pin Name

P00

P01

P02

P07

Note1

P10-P17

Input/Output

Input

Input/output

Input

Input/output

Input/output

Input/output

Function

Port 0 Input only.

After Reset

Input

8-bit input/output port.

Input/output can be specified Input

Alternate Function

INTP0/TI00

INTP1/TI01 bit-wise. When used as an input port, on-chip pull-up resistor can be used by software.

INTP2

INTP3

INTP4

INTP5

Input only.

Input

Input

INTP6

XT1

ANI0-ANI7 Port 1

8-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Note2

Port 2

8-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Input SI1

SO1

SCK1

STB

BUSY

SI0/SB0

SO0/SB1

SCK0

Port 3

8-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Input TO0

TO1

TO2

TI1

TI2

PCL

BUZ

Notes 1. When using the P07/XT1 pin as an input port, set bit 6 (FRC) of the processor clock control register (PCC) to

1. Do not use the on-chip feedback resistor of the subsystem clock oscillator.

2. When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog inputs, their on-chip pull-up resistors are automatically disconnected.

11

m

PD78070A

3.1

Port Pins (2/2)

Pin Name

P60

P61

P62

P63

P66

Input/Output

Input/output

P70

P71

P72

P90

P91

P92

P93

P94

P95

P96

P100

Input/output

Input/output

Input/output

P101

P102, P103

P120-P127 Input/output

P130, P131 Input/output

Function

Port 6 N-ch open-drain input/output

5-bit input/output port.

port.

Input/output can be specified bit-wise.

LED can be driven directly.

When used as an input port, on-chip pull-up resistor can be used by software.

Port 7

3-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

After Reset Alternate Function

Input —

Input

WAIT

SI2/RxD

SO2/TxD

SCK2/ASCK

— Port 9 N-ch open-drain input/output

7-bit input/output port.

port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Port 10

4-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Input

Input TI5/TO5

TI6/TO6

Input

RTP0-RTP7 Port 12

8-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Port 13

2-bit input/output port.

Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be used by software.

Input ANO0, ANO1

12

m

PD78070A

TI00

TI01

TI1

TI2

TI5

TI6

TO0

TO1

SCK0

SCK1

SCK2

STB

BUSY

RxD

TxD

ASCK

TO2

TO5

TO6

PCL

SI0

SI1

SI2

SO0

SO1

SO2

SB0

SB1

Pin Name

INTP0

INTP1

INTP2

INTP3

INTP4

INTP5

INTP6

3.2

Non-port Pins (1/2)

Input/Output Function

Input

After Reset

External interrupt input by which the active edge (rising edge, Input

Alternate Function

P00/TI00 falling edge, or both rising and falling edges) can be specified.

P01/TI01

P02

P03

P04

P05

P06

Input Serial interface serial data input.

Input

Output

Input/Output

Serial interface serial data output.

Serial interface serial data input/output.

Input

Input

P25/SB0

P20

P70/RxD

P26/SB1

P21

P71/TxD

P25/SI0

P26/SO0

Input/Output Serial interface serial clock input/output.

Input

Output

Input

Input

Output

Input

Input

Output

Output

Serial interface automatic transmit/receive strobe output.

Serial interface automatic transmit/receive busy input.

Asynchronous serial interface serial data input.

Asynchronous serial interface serial data output.

Asynchronous serial interface serial clock input.

External count clock input to 16-bit timer (TM0).

Capture trigger signal input to capture register (CR00).

External count clock input to 8-bit timer (TM1).

External count clock input to 8-bit timer (TM2).

External count clock input to 8-bit timer (TM5).

External count clock input to 8-bit timer (TM6).

16-bit timer output (also used for 14-bit PWM output).

8-bit timer output.

8-bit timer output (also used for 8-bit PWM output).

Clock output (for main system clock, subsystem clock trimming).

Input

Input

Input

Input

Input

Input

Input

Input

P27

P22

P72/ASCK

P23

P24

P70/SI2

P71/SO2

P72/SCK2

P00/INTP0

P01/INTP1

P33

P34

P100/TO5

P101/TO6

P30

P31

P32

P100/TI5

P101/TI6

P35

13

m

PD78070A

3.2

Non-port Pins (2/2)

X2

XT1

XT2

V

DD

V

SS

IC

Pin Name

BUZ

RTP0-RTP7

AD0-AD7

A0-A15

RD

WR

WAIT

ANI0-ANI7

ANO0, ANO1 Output

AV

REF0

Input

AV

REF1

Input

AV

DD

AV

SS

RESET

X1

Input

Input

Input/Output Function

Output

Output

Buzzer output.

Real-time output port by which data is output in synchronization with a trigger.

Input/Output Data bus for external memory.

Output Address bus for external memory.

Output External memory read operation strobe signal output.

Input

Input

External memory write operation strobe signal output.

Wait insertion at external memory access.

A/D converter analog input.

D/A converter analog output.

A/D converter reference voltage input.

D/A converter reference voltage input.

A/D converter analog power supply. Connected to V

DD

.

A/D converter ground potential. Connected to V

SS

.

System reset input.

Main system clock oscillation crystal connection.

Input

Subsystem clock oscillation crystal connection.

Positive power supply.

Ground potential.

Internal connection. Connected directly to V

SS

.

Input

Input

Input

Input

Input

Input

Input

After Reset Alternate Function

Input

Input

P36

P120-P127

P07

P66

P10-P17

P130, P131

14

m

PD78070A

3.3

Pin I/O Circuits and Recommended Connection of Unused Pins

The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.

For the input/output circuit configuration of each type, see Figure 3-1.

Table 3-1. Types of Pin Input/Output Circuits (1/2)

Pin Name

P30/TO0

P31/TO1

P32/TO2

P33/TI1

P34/TI2

P35/PCL

P36/BUZ

P37

P60-P63

P66/WAIT

P00/INTP0/TI00

P01/INTP1/TI01

P02/INTP2

P03/INTP3

P04/INTP4

P05/INTP5

P06/INTP6

P07/XT1

P10/ANI0-P17/ANI7

P20/SI1

P21/SO1

P22/SCK1

P23/STB

P24/BUSY

P25/SI0/SB0

P26/SO0/SB1

P27/SCK0

Input/Output

Circuit Type

2

8-A

16

11

8-A

5-A

8-A

5-A

8-A

10-A

5-A

8-A

5-A

13-C

5-A

Input/Output

Input

Input/Output

Recommended Connection of Unused Pins

Connect to V

SS

.

Independently connect to V

SS

via a resistor.

Input

Input/Output

Input/Output

Input/Output

Connect to V

DD

.

Independently connect to V

DD

or V

SS

via a resistor.

Independently connect to V

DD

via a resistor.

Independently connect to V

DD

or V

SS

via a resistor.

15

16

m

PD78070A

Table 3-1. Types of Pin Input/Output Circuits (2/2)

Pin Name

P70/SI2/RxD

P71/SO2/TxD

P72/SCK2/ASCK

P90-P93

RESET

XT2

AV

REF0

AV

REF1

AV

DD

AV

SS

IC

P94-P96

P100/TI5/TO5

P101/TI6/TO6

P102, P103

5-A

8-A

5-A

P120/RTP0-P127/RTP7

P130/ANO0, P131/ANO1 12-A

AD0-AD7

A0-A15

RD

WR

ASTB

5-E

5-A

2

16

Input/Output

Circuit Type

8-A

5-A

8-A

13-C

Input/Output

Input/Output

Input/Output

Input/Output

Input/Output

Input/Output

Output

Input

Recommended Connection of Unused Pins

Independently connect to V

DD

or V

SS

via a resistor.

Independently connect to V

DD

via a resistor.

Independently connect to V

DD

or V

SS

via a resistor.

Independently connect to V

SS

via a resistor.

Independently connect to V

DD

via a resistor.

Leave open.

Leave open.

Connect to V

Connect to V

Connect to V

SS

DD

SS

.

.

.

Connect directly to V

SS

.

Type 5-A pullup enable data output disable input enable

Type 5-E pullup enable data output disable m

PD78070A

Type 2

IN

Figure 3-1. Pin Input/Output Circuits (1/2)

Type 8-A pullup enable

Schmitt-Triggered Input with Hysteresis Characteristic data output disable

V

DD

V

DD

P-ch

P-ch

IN/OUT

N-ch

V

DD

Type 10-A pullup enable

V

DD

P-ch

P-ch

IN/OUT

N-ch data open drain output disable

V

DD

V

DD

P-ch

P-ch

IN/OUT

N-ch

V

DD

V

DD

P-ch

P-ch

IN/OUT

N-ch

V

DD

Type 11 pullup enable data

V

DD

P-ch

P-ch

IN/OUT output disable

N-ch

P-ch

Comparator

+

N-ch

V

REF

(threshold voltage) input enable

17

18

Figure 3-1. Pin Input/Output Circuits (2/2)

Type 12-A pullup enable

V

DD data output disable input enable

Analog Output

Voltage

P-ch

N-ch

Type 13-C

N-ch

V

DD

P-ch

P-ch

IN/OUT

Type 16

XT1 feedback cut-off

P-ch

XT2

IN/OUT data output disable

N-ch m

PD78070A

m

PD78070A

4.

MEMORY SPACE

The memory map of the m

PD78070A is shown in Figure 4-1.

Figure 4-1. Memory Map

Data

Memory

Space

FB00H

FAFFH

FAE0H

FADFH

FAC0H

FABFH

FA80H

FA7FH

FFFFH

Special Function Registers

(SFR) 256

×

8 bits

FF00H

FEFFH

FEE0H

FEDFH

General Registers

32

×

8 bits

Internal High-Speed RAM

1024

×

8 bits

Use Prohibited

Buffer RAM 32

×

8 bits

Use Prohibited

Program

Memory

Space

0000H

External Memory

64128

×

8 bits

0FFFH

0800H

07FFH

0080H

007FH

0040H

003FH

0000H

CALLF Entry Area

Program Area

CALLT Table Area

Vector Table Area

19

m

PD78070A

5.

PERIPHERAL HARDWARE FUNCTIONS

5.1

Ports

Input/output ports are classified into three types.

• CMOS inputs (P00, P07)

• CMOS input/outputs (P01-P06, Port 1-3, P66, Port 7, P94-P96, Port 10,

Port 12, Port 13)

• N-ch open-drain input/outputs (P60-P63, P90-P93)

Total

: 2

: 51

: 8

: 61

Port Name

Port 0

Pin Name

P00, P07

P01-P06

Port 1

Port 2

Port 3

Port 6

Port 7

Port 9

Port 10

Port 12

Port 13

P10-P17

P20-P27

P30-P37

P60-P63

P66

P70-P72

P90-P93

P94-P96

P100-P103

P120-P127

P130, P131

Table 5-1. Functions of Ports

Function

Input only.

Input/output port. Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be connected by software.

Input/output port. Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be connected by software.

Input/output port. Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be connected by software.

Input/output port. Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be connected by software.

N-ch open-drain input/output port. Input/output can be specified bit-wise.

LED can be driven directly.

Input/output port. Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be connected by software.

Input/output port. Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be connected by software.

N-ch open-drain input/output port. Input/output can be specified bit-wise.

Input/output port. Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be connected by software.

Input/output port. Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be connected by software.

Input/output port. Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be connected by software.

Input/output port. Input/output can be specified bit-wise.

When used as an input port, on-chip pull-up resistor can be connected by software.

20

m

PD78070A

5.2

Clock Generator

There are two kinds of clock generators: main system and subsystem clock generators. It is possible to change the instruction execution time.

• 0.4 m s/0.8 m s/1.6 m s/3.2 m s/6.4 m s/12.8 m s (at main system clock frequency of 5.0 MHz)

• 122 m s (at subsystem clock frequency of 32.768 kHz)

Figure 5-1. Clock Generator Block Diagram

XT1/P07

XT2

Subsystem

Clock

Oscillator f

XT

X1

X2

Main System

Clock

Oscillator f

X

Division

Circuit f

X

2

STOP

Prescaler f

XX f

XX

2 f

XX

2

2 f

XX

2

3 f

XX

2

4 f

XT

2

1

2

Prescaler

Watch Timer, Clock

Output Function

Clock to Peripheral

Hardware

Standby

Control

Circuit

Wait

Control

Circuit

CPU Clock

(f

CPU

)

To INTP0

Sampling Clock

21

m

PD78070A

5.3

Timer/Event Counter

There are the following seven timer/event counter channels:

• 16-bit timer/event counter : 1 channel

• 8-bit timer/event counter : 4 channels

• Watch timer

• Watchdog timer

: 1 channel

: 1 channel

Table 5-2. Types and Functions of Timer/Event Counters

Type

Function

Interval timer

External event counter

Timer output

PWM output

16-bit Timer/

Event Counter

1 channel

1 channel

1 output

1 output

Pulse width measurement 2 inputs

Square wave output 1 output

One-shot pulse output

Interrupt request

Test input

1 output

2

2

8-bit Timer/ 8-bit Timer/

Event Counter 1, 2 Event Counter 5, 6

Watch Timer

2 channels

2 channels

2 channels

2 channels

1 channel

2 outputs

2 outputs

2 outputs

2 outputs

2 outputs

2

1

1

1

Watchdog

Timer

1 channel

Figure 5-2. 16-Bit Timer/Event Counter Block Diagram

Internal Bus

INTP1

TI01/P01/

INTP1

Watch Timer

Output

2f

XX f

XX f

XX

/2 f

XX

/2

2

TI00/P00/

INTP0

Edge

Detector

16-Bit Capture/

Compare Register

(CR00)

Match

PWM Pulse

Output

Control

Circuit

16-Bit Timer

Register (TM0)

Clear

Match

Selector

INTTM00

Output

Control Circuit

TO0/P30

INTTM01

INTP0

16-Bit Capture/

Compare Register

(CR01)

Internal Bus

22

- f

XX

/2

9 f

XX

/2

11

TI1/P33

- f

XX

/2

9

11

TI2/P34

2f

XX

- f

XX

/2

9 f

XX

/2

11

TI5/P100/TO5,

TI6/P101/TO6 m

PD78070A

Figure 5-3. 8-Bit Timer/Event Counter 1, 2 Block Diagram

Internal Bus

INTTM1

8-Bit Compare

Register (CR10)

Match

8-Bit Compare

Register (CR20)

Match

Output

Control

Circuit

TO2/P32

INTTM2

8-Bit Timer

Register 1 (TM1)

Clear

Selector

8-Bit Timer

Register 2 (TM2)

Clear

Internal Bus

Figure 5-4. 8-Bit Timer/Event Counter 5, 6 Block Diagram

Internal Bus

Output

Control

Circuit

TO1/P31

8-Bit Compare Register

(CRn0)

Match

8-Bit Timer Register n

(TMn)

OVF

Clear

Internal Bus

Output Control

Circuit

INTTMn

TO5/P100/TI5,

TO6/P101/TI6 n = 5, 6

23

m

PD78070A

2

7

Figure 5-5. Watch Timer Block Diagram

5-Bit Counter

2 14

Prescaler

2

4

2

5

2

6

2

7

2

8

2

9

2 13

INTWT

INTTM3

To 16-Bit Timer/

Event Counter

Figure 5-6. Watchdog Timer Block Diagram

2

3

Prescaler

2

4

2

5

2

6

2

7

2

8

2

9

2

11

8-Bit Counter

INTWDT

Maskable

Interrupt Request

RESET

INTWDT

Non-maskable

Interrupt Request

5.4

Clock Output Control Circuit

This circuit can output clocks of the following frequencies:

• 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (at main system clock frequency of 5.0 MHz)

• 32.768 kHz (at subsystem clock frequency of 32.768 kHz)

Figure 5-7. Clock Output Control Circuit Block Diagram

f

XX f

XX

/2 f

XX

/2

2 f

XX

/2

3 f

XX

/2

4 f

XX

/2

5 f

XX

/2

6 f

XX

/2

7 f

XT

Synchronization

Circuit

Output Control

Circuit

PCL/P35

24

m

PD78070A

5.5

Buzzer Output Control Circuit

This circuit can output clocks of the following frequencies that can be used for driving buzzers:

• 1.2 kHz/2.4 kHz/4.9 kHz/9.8 kHz (at main system clock frequency of 5.0 MHz)

Figure 5-8. Buzzer Output Control Circuit Block Diagram

f

XX

/2

9 f

XX

/2

10 f

XX

/2

11

Output Control

Circuit

BUZ/P36

5.6

A/D Converter

The A/D converter consists of eight 8-bit resolution channels.

A/D conversion can be started by the following two methods:

• Hardware starting

• Software starting

Figure 5-9. A/D Converter Block Diagram

ANI0/P10

ANI1/P11

ANI2/P12

ANI3/P13

ANI4/P14

ANI5/P15

ANI6/P16

ANI7/P17

Sample & Hold Circuit

Voltage Comparator

Series Resistor String

AV

DD

AV

REF0

Successive Approximation

Register (SAR)

AV

SS

INTP3/P03

Edge

Detector

Control

Circuit

INTAD

INTP3

A/D Conversion Result

Register (ADCR)

Internal Bus

5.7

D/A Converter

The D/A converter consists of two 8-bit resolution channels.

The conversion method is the R-2R resistor ladder method.

25

m

PD78070A

AV

REF1

Figure 5-10. D/A Converter Block Diagram

ANOn

Selector

AV

SS

DACSn

Write

INTTM

X

D/A Conversion Value Set Register n

(DACSn)

DAMm

D/A Converter

Mode Register

Internal Bus n = 0, 1 m = 4, 5 x = 1, 2

5.8

Serial Interfaces

There are the following three on-chip serial interface channels synchronous with the clock:

• Serial interface channel 0

• Serial interface channel 1

• Serial interface channel 2

Function

3-wire serial I/O mode

3-wire serial I/O mode with automatic data transmit/receive function

2-wire serial I/O mode

Serial bus interface (SBI) mode

Asynchronous serial interface

(UART) mode

Table 5-3.

Types and Functions of Serial Interfaces

Serial Interface Channel 0

MSB/LSB first bit switching possible)

Serial Interface Channel 1

(MSB/LSB first bit switching possible)

(MSB/LSB first bit switching possible)

(MSB first)

(MSB first)

Serial Interface Channel 2

(MSB/LSB first bit switching possible)

(On-chip dedicated baud rate generator)

26

SI0/SB0/P25

SO0/SB1/P26

SCK0/P27 m

PD78070A

Figure 5-11. Serial Interface Channel 0 Block Diagram

Internal Bus

Serial I/O Shift Register 0

(SIO0)

Bus Release/

Command/

Acknowledge detector

Serial Clock Counter

Output

Latch

Interrupt

Request Signal

Generator

Busy/Acknowledge

Output Circuit

INTCSI0

Serial Clock

Control Circuit f

XX

/2–f

XX

/2 8

TO2

SI1/P20

SO1/P21

STB/P23

BUSY/P24

SCK1/P22

Figure 5-12. Serial Interface Channel 1 Block Diagram

Internal Bus

Automatic Data Transmit/

Receive Address

Pointer (ADTP)

Buffer RAM

Serial I/O Shift

Register 1 (SIO1)

Match

Automatic Data

Transmit/Receive

Interval Specification

Register (ADTI)

Handshake

Control

Circuit

Serial Clock Counter

5-Bit Counter

Serial Clock

Control Circuit

Interrupt Request

Signal Generator

INTCSI1 f

XX

/2–f

XX

/2 8

TO2

27

m

PD78070A

Figure 5-13. Serial Interface Channel 2 Block Diagram

Internal Bus

R

X

D/SI2/P70

T

X

D/SO2/P71

ASCK/SCK2/P72

Receive Buffer

Register (RXB/SIO2)

Direction Control

Circuit

Receive Shift

Register (RXS)

Receive Control

Circuit

Direction Control

Circuit

Transmit Shift

Register (TXS/SIO2)

Transmit Control

Circuit

INTSER

INTSR/INTCSI2

SCK Output

Control Circuit

INTST

Baud Rate

Generator f

XX

–f

XX

/2 10

5.9

Real-Time Output Port

Data set previously in the real-time output buffer is transferred to the output latch by hardware concurrently with timer interrupt or external interrupt generation in order to output to off-chip. This is a real-time output function. Pins used to output to off-chip are called real-time output ports.

By using a real-time output port, a signal which has no jitter can be output. This is most applicable to control of stepping motors, etc.

Figure 5-14. Real-Time Output Port Block Diagram

Internal Bus

28

INTP2

INTTM1

INTTM2

Output Trigger

Control Circuit

Real-Time Output

Buffer Register

Higher 4 Bits

(RTBH)

Real-Time Output

Buffer Register

Lower 4 Bits

(RTBL)

Output Latch

P127 P120

Real-Time Output Port Mode

Register (RTPM)

6.

INTERRUPT FUNCTIONS AND TEST FUNCTION

6.1 Interrupt Functions

A total of 24 interrupt functions are provided, divided into the following three types.

• Non-maskable interrupt : 1

• Maskable interrupts : 22

• Software interrupt : 1 m

PD78070A

29

m

PD78070A

Table 6-1. List of Interrupt Sources

Interrupt

Type

Nonmaskable

Maskable

Software

7

8

5

6

3

4

1

2

9

10

Default

Note1

Priority

0

11

12

13

14

15

16

17

18

19

20

Interrupt Source

Name Trigger

INTWDT Overflow of watchdog timer (When the watchdog timer mode 1 is selected)

INTWDT Overflow of watchdog timer (When the interval timer mode is selected)

INTP0

INTP1

Pin input edge detection

INTP2

INTP3

INTP4

INTP5

INTP6

INTCSI0 Completion of serial interface channel 0 transfer

INTCSI1 Completion of serial interface channel 1 transfer

INTSER Occurrence of serial interface channel 2 UART reception

INTSR error

Completion of serial interface channel 2 UART reception

INTCSI2 Completion of serial interface channel 2 3-wire transfer

INTST Completion of serial interface channel 2 UART transmission

INTTM3 Reference time interval signal from watch timer

INTTM00 Generation of matching signal of 16-bit timer register and capture/compare register (CR00)

INTTM01 Generation of matching signal of 16-bit timer register and capture/compare register (CR01)

INTTM1 Generation of matching signal of 8-bit timer/event counter 1

INTTM2 Generation of matching signal of 8-bit timer/event

INTAD counter 2

Completion of A/D conversion

INTTM5 Generation of matching signal of 8-bit timer/event counter 5

INTTM6 Generation of matching signal of 8-bit timer/event

BRK counter 6

Execution of BRK instruction

Internal/ Vector

External Table

Internal

Basic

Structure

Address Type Note2

0004H (A)

External 0006H

0008H

000AH

000CH

Internal

000EH

0010H

0012H

0014H

0016H

0018H

Internal

001AH

001CH

001EH

0020H

0022H

0024H

0026H

0028H

002AH

002CH

003EH

(B)

(C)

(D)

(B)

(E)

Notes 1.

Default priority is the priority order when several maskable interrupts are generated at the same time. 0 is the highest priority and 20 is the lowest priority.

2.

Basic structure types (A) to (E) correspond to (A) to (E) in Figure 6-1.

30

m

PD78070A

Figure 6-1. Basic Configuration of Interrupt Function (1/2)

(A) Internal non-maskable interrupt

Internal Bus

Interrupt

Request

Priority

Control

Circuit

Vector Table

Address

Generator

Standby Release

Signal

(B) Internal maskable interrupt

Interrupt

Request

IF

MK

Internal Bus

IE PR ISP

Priority

Control

Circuit

Vector Table

Address

Generator

Standby Release

Signal

(C) External maskable interrupt (INTP0)

Sampling Clock

Select Register

(SCS)

External Interrupt

Mode Register

(INTM0)

Internal Bus

MK IE PR ISP

Interrupt

Request

Sampling

Clock

Edge

Detector

IF

Priority

Control

Circuit

Vector Table

Address

Generator

Standby

Release

Signal

31

m

PD78070A

Figure 6-1. Basic Configuration of Interrupt Function (2/2)

(D) External maskable interrupt (except INTP0)

Internal Bus

External Interrupt

Mode Register

(INTM0, INTM1)

MK IE PR ISP

Interrupt

Request

Edge

Detector

IF

Priority Control

Circuit

Vector Table

Address

Generator

Standby

Release

Signal

(E) Software interrupt

Internal Bus

Interrupt

Request

IF : Interrupt request flag

IE : Interrupt enable flag

ISP : In-service priority flag

MK : Interrupt mask flag

PR : Priority specification flag

Priority

Control

Circuit

Vector Table

Address

Generator

32

6.2

Test Function

Table 6-2 shows the test function available.

Table 6-2. Test Input Source

Test Input Source

Name Trigger

INTWT Overflow of watch timer

Internal/

External

Internal

Figure 6-2. Basic Configuration of Test Function

Internal Bus

MK

Standby Release

Signal

Test Input

Signal

IF

IF : Test input flag

MK : Test mask flag m

PD78070A

33

m

PD78070A

7.

EXTERNAL DEVICE EXPANSION FUNCTIONS

The external device expansion functions connect external devices to areas other than the RAM and SFR.

The m

PD78070A is a ROM-less product, and therefore requires the connection of external ROM.

Connect external devices using an independent address bus and data bus.

8.

STANDBY FUNCTION

The standby function is designed to reduce current consumption.

It has the following two modes:

HALT mode : In this mode, the CPU operation clock is stopped. The average current consumption can be reduced by intermittent operation by combining this mode with the normal operation mode.

STOP mode : In this mode, oscillation of the main system clock is stopped. All the operations performed on the main system clock are suspended, and only the subsystem clock is used for extremely small power consumption.

Figure 8-1. Standby Function

CSS = 1

Main system clock operation

Subsystem clock operation

Note

STOP instruction

Interrupt request

STOP mode

(Oscillation of the main system clock is stopped.)

Interrupt request

CSS = 0

HALT instruction

HALT mode

(Supply of clock to CPU is stopped although clock is generated.)

Interrupt request

HALT instruction

HALT mode

Note

(Supply of clock to CPU is stopped although clock is generated.)

Note

Current consumption is reduced by shutting off the main system clock. If the CPU is operating on the subsystem clock, shut off the main system clock by setting bit 7 (MCC) of the processor clock control register (PCC).

You cannot use a STOP instruction.

Caution When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock.

9.

RESET FUNCTION

There are the following two reset methods.

• External reset input by RESET pin

• Internal reset by watchdog timer runaway time detection

34

m

PD78070A

10. INSTRUCTION SET

(1) 8-bit instructions

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC,

ROR4, ROL4, PUSH, POP, DBNZ r

2nd Operand

1st Operand

A

#byte

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

A

MOV MOV

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP r

Note

sfr

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

MOV

XCH saddr !addr16 PSW

MOV

XCH

XOR

CMP

MOV

XCH

ADD ADD

ADDC ADDC

SUB SUB

SUBC SUBC

AND

OR

AND

OR

XOR

CMP

MOV

[DE]

MOV

XCH

[HL]

[HL + byte] $addr16

[HL + B]

MOV

XCH

ADD

[HL + C]

MOV

XCH

ADD

ADDC ADDC

SUB SUB

SUBC SUBC

AND

OR

XOR

CMP

AND

OR

XOR

CMP

1

ROR

ROL

RORC

ROLC

None

INC

DEC

B, C sfr saddr

DBNZ

DBNZ INC

DEC

!addr16

PSW

MOV

MOV

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

MOV

MOV

MOV

MOV

MOV PUSH

POP

[DE]

Note Except r = A

MOV

35

36

m

PD78070A

2nd Operand

#byte A

1st Operand

[HL]

[HL + byte]

[HL + B]

[HL + C]

X

C

MOV

MOV r sfr saddr !addr16 PSW [DE] [HL]

[HL + byte] $addr16

[HL + B]

[HL + C]

1

2nd Operand

1st Operand

AX rp

(2) 16-bit instructions

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW

#word AX rp

Note

sfrp saddrp

ADDW

SUBW

CMPW

MOVW MOVW

Note

MOVW

XCHW

MOVW MOVW sfrp saddrp

!addr16

SP

MOVW

MOVW

MOVW

MOVW

MOVW

MOVW MOVW

Note Only when rp = BC, DE, HL

None

!addr16

MOVW

SP

MOVW

None

ROR4

ROL4

MULU

DIVUW

INCW, DECW

PUSH, POP

m

PD78070A

(3) Bit manipulation instructions

MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR

2nd Operand

1st Operand

A.bit

A.bit

sfr.bit

saddr.bit

PSW.bit

[HL].bit

sfr.bit

saddr.bit

PSW.bit

[HL].bit

CY MOV1

AND1

OR1

XOR1

MOV1

AND1

OR1

XOR1

MOV1

AND1

OR1

XOR1

MOV1

AND1

OR1

XOR1

MOV1

AND1

OR1

XOR1

CY

MOV1

MOV1

MOV1

MOV1

MOV1

$addr16

BT

BF

BTCLR

BT

BF

BTCLR

BT

BF

BTCLR

BT

BF

BTCLR

BT

BF

BTCLR

SET1

CLR1

SET1

CLR1

SET1

CLR1

NOT1

None

SET1

CLR1

SET1

CLR1

SET1

CLR1

(4) Call instructions/Branch instructions

CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ

2nd Operand AX !addr16

!addr11

[addr5] $addr16

1st Operand

Basic instruction BR

Compound instruction

CALL

BR

CALLF CALLT BR

BC

BNC

BZ

BNZ

BT

BF

BTCLR

DBNZ

(5) Other instructions

ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP

37

54

(iii) UART mode (Dedicated baud rate generator output)

Parameter

Transfer rate

Symbol Test Conditions

V

DD

= 4.5 to 5.5 V

(iv) UART mode (External clock input)

Parameter

ASCK cycle time

Symbol Test Conditions t

KCY13

V

DD

= 4.5 to 5.5 V

ASCK high-/low-level width t

KH13

, t

KL13

Transfer rate

V

DD

= 4.5 to 5.5 V

V

DD

= 4.5 to 5.5 V

ASCK rise, fall time t

R13

, t

F13 m

PD78070A

MIN.

TYP.

MAX.

78125

39063

Unit bps bps

MIN.

800

1600

400

800

TYP.

MAX.

39063

19531

160 ns bps bps ns

Unit ns ns ns

m

PD78070A

11. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

A

= 25 °C)

Parameter

Supply voltage

Input voltage

Output voltage

Analog input voltage

Output current, high

Output current, low

Operating ambient temperature

Storage temperature

I

V

I2

V

O

V

AN

I

OH

Symbol Test Conditions

V

DD

AV

DD

AV

REF0

AV

REF1

AV

SS

V

I1

P00-P07, P10-P17, P20-P27, P30-P37, P66,

P70-P72, P94-P96, P100-P103, P120-P127,

P130, P131, AD0-AD7, X1, X2, XT2, RESET

P60-P63, P90-P93 N-ch open-drain

P10-P17

Per pin

Analog input pins

Total for P30-P37, P60-P63, P66, P90-P96,

P100-P103, P120-P127, A14, A15, RD,

OL

Note

WR, ASTB

Total for P01-P06, P10-P17, P20-P27, P70-P72, –15

P130, P131, AD0-AD7, A0-A13

Per pin Peak value 30 r.m.s. value

15

Total for A8-A13

Total for P60-P63, A14, A15

Peak value 50 r.m.s. value

20

Peak value 100 r.m.s. value

70

Ratings

–0.3 to +7.0

–0.3 to V

DD

+0.3

–0.3 to V

DD

+0.3

–0.3 to V

DD

+0.3

–0.3 to +0.3

–0.3 to V

DD

+0.3

–0.3 to V

DD

+0.3

–0.3 to V

DD

+0.3

V

V

AV

SS

– 0.3 to AV

REF0

+ 0.3

V

–10 mA

–15 mA mA

V

V

V

V

V

Unit

V mA mA mA mA mA mA mA mA

T

T

A stg

Total for P30-P37, P66, P90-P96, Peak value 50

P100-P103, P120-P127, RD, r.m.s. value

20

WR, ASTB

Total for P20-P27, AD0-AD7,

A0-A7

Total for P01-P06, P10-P17,

P70-P72, P130, P131

Peak value 50 r.m.s. value

20

Peak value 50 r.m.s. value

20

–40 to +85

–65 to +150 mA mA mA mA

°C

°C

Note The r.m.s. value should be calculated as follows: [r.m.s. value] = [Peak value]

¥

Duty

Caution Exposure to Absolute Maximum Ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. The device should be operated within the limits specified under DC and AC Characteristics.

Remark

Unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics.

38

m

PD78070A

Capacitance (T

A

= 25 °C, V

DD

= V

SS

= 0 V)

Parameter

Input capacitance

Symbol Test Conditions

C

IN f = 1 MHz, Unmeasured pins returned to 0 V.

Output capacitance C

OUT

I/O capacitance C

IO

MIN.

TYP.

MAX.

15

15

15

Unit pF pF pF

Main System Clock Oscillator Characteristics (T

A

= –40 to +85 °C, V

DD

= 2.7 to 5.5 V)

MIN.

TYP.

Resonator

Ceramic resonator

Crystal resonator

External clock

Recommended

Circuit

IC

R1

X2 X1

C2 C1

IC

R1

X2

C2 C1

X1

X2

µ

PD74HCU04

Parameter Test Conditions

X1

Oscillation frequency

(f

X

)

Note1

Oscillation stabilization time

Note2

Oscillation frequency

(f

X

)

Note1

Oscillation stabilization time

Note2

X1 input frequency

(f

X

)

Note1

X1 input high- and low-level widths (t

XH

, t

XL

)

V

DD

= Oscillation voltage range

After V

DD

came to MIN.

of oscillation voltage range

V

DD

= 4.5 to 5.5 V

1.0

1.0

1.0

85

MAX.

Unit

5.0

4

5.0

10

30

5.0

500

MHz ms

MHz ms

MHz ns

Notes 1. Only the oscillator characteristics are shown. For the instruction execution time, refer to AC Characteristics.

2. Time required for oscillation to stabilize after a reset or the STOP mode has been released.

Cautions 1.

When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted lines in the figures as follows to avoid adverse influences on the wiring capacitance:

• Keep the wiring length as short as possible.

• Do not cross the wiring over other signal lines.

• Do not route the wiring in the vicinity of lines through which a high fluctuating current flows.

• Always keep the ground point of the capacitor of the oscillation circuit at the same potential as

V

SS

.

• Do not connect the power source to a ground pattern through which a high current flows.

• Do not extract signals from the oscillation circuit.

2.

When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock.

39

m

PD78070A

Subsystem Clock Oscillator Characteristics (T

A

= –40 to +85 °C, V

DD

= 2.7 to 5.5 V)

MIN.

TYP.

Resonator

Crystal resonator

External clock

Recommended

Circuit

IC XT2

R2

XT1

C4

C3

XT2

µ

PD74HCU04

Parameter Test Conditions

XT1

Oscillation frequency

(f

XT

) Note1

Oscillation stabilization time Note2

XT1 input frequency

(f

XT

) Note1

XT1 input high-, low-level widths (t

XTH

, t

XTL

)

V

DD

= 4.5 to 5.5 V

32

32

5

MAX.

32.768

35

1.2

2

10

100

15

Unit kHz s kHz m s

Notes 1. Only the oscillator characteristics are shown. For the instruction execution time, refer to AC Characteristics.

2. Time required for oscillation to stabilize after V

DD

reaches the minimum value of the oscillation voltage range.

Cautions 1.

When using the oscillation circuit of the subsystem clock, wire the portion enclosed in dotted lines in the figures as follows to avoid adverse influences on the wiring capacitance:

• Keep the wiring length as short as possible.

• Do not cross the wiring over other signal lines.

• Do not route the wiring in the vicinity of lines through which a high fluctuating current flows.

• Always keep the ground point of the capacitor of the oscillation circuit at the same potential as

V

SS

.

• Do not connect the power source pattern through which a high current flows.

• Do not extract signals from the oscillation circuit.

2.

The amplification factor of the subsystem clock oscillator is designed to be low to reduce the current consumption and therefore, the subsystem clock oscillator is influenced by noise more easily than the main system clock oscillator. When using the subsystem clock, therefore, exercise utmost care in wiring the circuit.

40

m

PD78070A

DC Characteristics (T

A

= –40 to +85 °C, V

DD

= 2.7 to 5.5 V)

Parameter

Input voltage, high

Input voltage, low

Output voltage, high

Output voltage, low

Symbol Test Conditions

V

IH1

P10-P17, P21, P23, P30-P32, P35-P37, P66,

P71, P94-P96, P102, P103, P120-P127, P130,

P131, AD0-AD7

V

IH2

V

V

V

IH3

IH4

IH5

P00-P06, P20, P22, P24-P27, P33, P34, P70,

P72, P100, P101, RESET

P60-P63, P90-P93 (N-ch open-drain)

X1, X2

XT1/P07, XT2 V

DD

= 4.5 to 5.5 V

V

V

V

V

V

V

V

V

V

IL1

IL2

IL3

IL4

IL5

OH

OL1

OL2

OL3

MIN.

0.7V

0.8V

DD

DD

TYP.

0.7V

DD

V

DD

–0.5

0.8V

DD

0.9V

DD

0 P10-P17, P21, P23, P30-P32, P35-P37, P66,

P71, P94-P96, P102, P103, P120-P127, P130,

P131, AD0-AD7

P00-P06, P20, P22, P24-P27, P33, P34, P70,

P72, P100, P101, RESET

P60-P63, P90-P93

(N-ch open-drain)

X1, X2

XT1/P07, XT2

V

V

DD

DD

= 4.5 to 5.5 V

= 4.5 to 5.5 V

V

DD

= 4.5 to 5.5 V, I

OH

= –1 mA

I

OH

= –100 m

A

P60-P63 V

DD

= 4.5 to 5.5 V,

P01-P06, P10-P17,

P20-P27, P30-P37, P66,

I

OL

= 15 mA

V

DD

= 4.5 to 5.5 V,

I

OL

= 1.6 mA

P70-P72, P90-P96,

P100-P103, P120-P127,

P130, P131, AD0-AD7,

A0-A15, RD, WR, ASTB

SB0, SB1, SCK0 V

DD

= 4.5 to 5.5 V,

Open-drain, pulled up

(R = 1 ký)

I

OL

= 400 m

A

0

0

0

0

0

0

V

DD

–1.0

V

DD

–0.5

0.4

MAX.

V

DD

Unit

V

V

DD

V

DD

V

DD

V

DD

V

DD

0.3V

DD

V

V

V

V

V

0.2V

DD

V

0.3V

DD

V

0.2V

DD

V

0.4

V

0.2V

DD

V

0.1V

DD

V

V

2.0

V

V

0.4

0.5

V

V

0.2V

DD

V

V

Remark

Unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics.

41

m

PD78070A

DC Characteristics (T

A

= –40 to +85 °C, V

DD

= 2.7 to 5.5 V)

Parameter

Input leakage current, high

Input leakage current, low

I

LIL2

Output leakage current, high I

LOH

Output leakage current, low I

LOL

Software pull-up resistor R

I

I

Symbol Test Conditions

I

LIH1

LIH2

LIL1

V

V

IN

IN

= V

DD

= 0 V

P00-P06, P10-P17,

P20-P27, P30-P37,

P60-P63, P66,

P70-P72, P90-P96,

P100-P103, P120-

P127, P130, P131,

AD0-AD7, RESET

X1, X2, XT1/P07, XT2

P00-P06, P10-P17,

P20-P27, P30-P37,

P60-P63, P66,

P70-P72, P90-P96,

P100-P103, P120-

P127, P130, P131,

AD0-AD7, RESET

X1, X2, XT1/P07, XT2

V

OUT

= V

DD

V

OUT

= 0 V

V

IN

= 0 V, P01-P06, P10V

DD

= 4.5 to 5.5 V

P17, P20-P27, P30-P37,

P66, P70-P72, P94-P96,

P100-P103, P120-P127,

P130, P131

MIN.

15

20

TYP.

MAX.

3

Unit m

A

40

20

–3

–20

3

–3

90

500 m

A m

A m

A m

A m

A k ý k ý

Remark

Unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics.

42

m

PD78070A

DC Characteristics (T

A

= –40 to +85 °C, V

DD

= 2.7 to 5.5 V)

Parameter

Supply current

Note1

I

I

I

I

I

Symbol Test Conditions

I

DD1

5.0-MHz crystal oscillation operating mode

(f

XX

= 2.5 MHz)

Note2

V

DD

= 5.0 V ± 10%

Note5

V

DD

= 3.0 V ± 10%

Note6

DD2

5.0-MHz crystal oscillation V

DD

= 5.0 V ± 10%

Note5

operating mode V

DD

= 3.0 V ± 10%

Note6

(f

XX

= 5.0 MHz)

Note3

5.0-MHz crystal oscillation V

DD

= 5.0 V ± 10%

Note5

HALT mode V

DD

= 3.0 V ± 10%

Note6

(f

XX

= 2.5 MHz)

Note2

DD3

DD4

DD5

DD6

5.0-MHz crystal oscillation V

DD

= 5.0 V ± 10%

Note5

HALT mode V

DD

= 3.0 V ± 10%

Note6

(f

XX

= 5.0 MHz)

Note3

32.768-kHz crystal oscillaV

DD

= 5.0 V ± 10% tion operating mode

Note4

V

DD

= 3.0 V ± 10%

32.768-kHz crystal oscillaV

DD

= 5.0 V ± 10% tion operating mode

Note4

V

DD

= 3.0 V ± 10%

XT1 = V

DD

STOP mode

V

V

DD

DD

= 5.0 V ± 10%

= 3.0 V ± 10%

Feedback resistor used

XT1 = V

DD

STOP mode

Feedback resistor not used

V

V

DD

DD

= 5.0 V ± 10%

= 3.0 V ± 10%

MIN.

TYP.

4.5

0.7

MAX.

13.5

2.1

Unit mA mA

8.0

0.9

1.4

0.5

1.6

0.65

60

32

25

5

1

0.5

0.1

0.05

24.0

2.7

4.2

1.5

4.8

1.95

120

64

55

15

30

10

30

10 mA mA mA mA mA mA m

A m

A m

A m

A m

A m

A m

A m

A

Notes 1. Not including AV

REF0

, AV

REF1

and AV

DD

currents or port currents (including current flowing into on-chip pullup resistors).

2. f xx

= f x

/2 operation (when oscillation mode selection register (OSMS) is set to 00H).

3. f xx

= f x

operation (when OSMS is set to 01H).

4. When the main system clock is stopped.

5. High-speed mode operation (when processor clock control register (PCC) is set to 00H).

6. Low-speed mode operation (when PCC is set to 04H).

Remark

f xx

: Main system clock frequency (f x

or f x

/2) f x

: Main system clock oscillation frequency

43

m

PD78070A

AC Characteristics

(1)

Basic Operation (T

A

= –40 to +85 °C, V

DD

= 2.7 to 5.5 V)

Parameter

Cycle time

(minimum instruction execution time)

TI00 input high-/low-level widths

TI01 input high-/low-level widths

TI1, TI2, TI5, TI6 input frequency f

TI1

TI1, TI2, TI5, TI6 input high-/ t

TIH1

, low-level widths t

TIL1

Interrupt input high-/ low-level widths t t t t

Symbol Test Conditions

T

CY

Operating on f

XX

= f

X

/2

Note1

main system f

XX

= f

X

Note2

MIN.

0.8

V

DD

= 3.5 to 5.5 V 0.4

TIH00 t

TIL00

TIH01 t

TIL01

,

, clock

Operating on subsystem clock

V

DD

= 3.5 to 5.5 V

0.8

40

2/f sam

+0.1

Note3

2/f sam

+0.2

Note3

10

V

DD

= 4.5 to 5.5 V

INTH

INTL

,

V

DD

= 4.5 to 5.5 V

INTP0

0

0

100

1.8

V

DD

= 3.5 to 5.5 V

2/f sam

+0.1

Note3

RESET low-level width t

RSL

INTP1-INTP6

2/f sam

+0.2

Note3

10

10

TYP.

122

4

275

MAX.

64

32

32

125

Unit m s m s m s m s m s m s m s

MHz kHz ns m s m s m s m s m s

Notes 1. When oscillation mode selection register (OSMS) is set to 00H.

2. When OSMS is set to 01H.

3. f sam

can be selected as f xx

/2 N , f xx

/32, f xx

/64 or f xx

/128 (N = 0-4) by bits 0 and 1 (SCS0, SCS1) of the sampling clock selection register.

Remark

f xx

: Main system clock frequency (f x

or f x

/2) f x

: Main system clock oscillation frequency

44

T

CY

vs V

DD

(Main System Clock f xx

= f x

/2 Operation)

60 m

PD78070A

T

CY

vs V

DD

(Main System Clock f xx

= f x

Operation)

60

10

Operation

Guaranteed

Range

2.0

1.0

0.5

0.4

0

1 2 3 4 5 6

Power Supply Voltage V

DD

[V]

10

Operation

Guaranteed

Range

2.0

1.0

0.5

0.4

0

1 2 3 4 5 6

Power Supply Voltage V

DD

[V]

45

m

PD78070A

(2) Read/Write Operation

(a)

When MCS = 1, PCC2 to PCC0 = 000B (T

A

= –40 to +85 °C, V

DD

= 4.5 to 5.5 V)

MAX.

Parameter

ASTB high-level width

Address setup time

Address hold time

Address

Æ

Data input time

RD

Ø Æ

Data input time

Read data hold time

RD low-level width

RD

Ø Æ

WAIT

Ø

input time

WR

Ø Æ

WAIT

Ø

input time

WAIT low-level width t

RDWT2 t

WRWT t

WTL

Write data setup time t

WDS

Write data hold time t

WDH

WR low-level width t

WRL

ASTB

Ø Æ

RD

Ø

delay time t

ASTRD

ASTB

Ø Æ

WR

Ø

delay time t

ASTWR

In external fetch RD

 Æ

ASTB



delay time

In external fetch RD

 Æ t t

RDAST

RDADH address hold time

RD

 Æ

write data output time t

RDWD

WR

Ø Æ

write data output time t

WRWD

WR

 Æ

address hold time

WAIT

 Æ

RD



delay time

WAIT

 Æ

WR



delay time t t t

WRADH

WTRD

WTWR t

RDD1 t

RDD2 t

RDH t

RDL1 t

RDL2 t

RDWT1

Symbol Test Conditions t

ASTH t

ADS t

ADH t

ADD1 t

ADD2

MIN.

0.85t

CY

– 50

0.85t

CY

– 50

50

0

(2 + 2n) t

CY

– 60

(2.85 + 2n) t

CY

– 60

(1.15 + 2n) t

CY

(2.85 + 2n) t

CY

– 100

20

(2.85 + 2n) t

CY

– 60

25

0.85t

CY

+ 20

0.85t

CY

– 10

0.85t

CY

– 50

40

0

0.85t

CY

1.15t

CY

+ 40

1.15t

CY

+ 30

(2.85 + 2n) t

CY

– 80

(4 + 2n) t

CY

– 100

(2 + 2n) t

CY

– 100

(2.85 + 2n) t

CY

– 100

0.85t

CY

– 50

2t

CY

– 60

2t

CY

– 60

(2 + 2n) t

CY

1.15t

CY

+ 20

1.15t

CY

+ 50

50

1.15t

CY

+ 40

3.15t

CY

+ 40

3.15t

CY

+ 30

Remarks 1.

MCS: Bit 0 of the oscillation mode selection register (OSMS)

2.

PCC2-PCC0: Bit 2 to bit 0 of the processor clock control register (PCC)

3.

t

CY

= T

CY

/4

4.

n indicates the number of waits.

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Unit ns ns

46

m

PD78070A

(b) Except When MCS = 1, PCC2 to PCC0 = 000B (T

A

= –40 to +85 °C, V

DD

= 2.7 to 5.5 V)

MAX.

Parameter

ASTB high-level width

Address setup time

Address hold time

Address

Æ

Data input time

RD

Ø Æ

Data input time

Read data hold time

RD low-level width t

RDH t

RDL1

RD

Ø Æ

WAIT

Ø

input time t t

RDL2

RDWT1

WR

Ø Æ

WAIT

Ø

input time

WAIT low-level width

Write data setup time

Write data hold time t t t

RDWT2

WRWT t

WTL

WDS t

WDH

WR low-level width t

WRL

ASTB

Ø Æ

RD

Ø

delay time t

ASTRD

ASTB

Ø Æ

WR

Ø

delay time t

ASTWR

In external fetch RD

 Æ

ASTB



delay time

In external fetch RD

 Æ t t

RDAST

RDADH address hold time

RD

 Æ

write data output time t

RDWD

WR

Ø Æ

write data output time t

WRWD

WR

 Æ

address hold time

WAIT

 Æ

RD



delay time

WAIT

 Æ

WR



delay time t t t

WRADH

WTRD

WTWR

Symbol Test Conditions t

ASTH t

ADS t

ADH t

ADD1 t

ADD2 t

RDD1 t

RDD2

MIN.

t

CY

– 80 t

CY

– 80

0.4t

CY

– 10

0

(1.4 + 2n) t

CY

– 20

(2.4 + 2n) t

CY

– 20

(1 + 2n) t

CY

(2.4 + 2n) t

CY

– 60

20

(2.4 + 2n) t

CY

– 20

0.4t

CY

– 30

1.4t

CY

– 30 t

CY

– 10 t

CY

– 50

0.4t

CY

– 20

0 t

CY

0.6t

CY

+ 180

0.6t

CY

+ 120

(3 + 2n) t

CY

– 160

(4 + 2n) t

CY

– 200

(1.4 + 2n) t

CY

– 70

(2.4 + 2n) t

CY

– 70 t

CY

– 100

2t

CY

– 100

2t

CY

– 100

(2 + 2n) t

CY t

CY

+ 20 t

CY

+ 50

60 t

CY

+ 60

2.6t

CY

+ 180

2.6t

CY

+ 120

Remarks 1.

MCS: Bit 0 of the oscillation mode selection register (OSMS)

2.

PCC2-PCC0: Bit 2 to bit 0 of the processor clock control register (PCC)

3.

t

CY

= T

CY

/4

4.

n indicates the number of waits.

ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

Unit ns ns ns

47

m

PD78070A

(3)

Serial Interface (T

A

= –40 to +85 °C, V

DD

= 2.7 to 5.5 V)

(a) Serial Interface Channel 0

(i) 3-wire serial I/O mode (SCK0 ··· internal clock output)

Parameter

SCK0 cycle time

Symbol Test Conditions t

KCY1

V

DD

= 4.5 to 5.5 V

SCK0 high-/low-level width t

KH1

, t

KL1 t

SIK1

V

DD

= 4.5 to 5.5 V

SI0 setup time

(to SCK0



)

SI0 hold time

(from SCK0



)

SCK0

Ø Æ

SO0 output delay time t

KSI1 t

KSO1

V

DD

= 4.5 to 5.5 V

C = 100 pF Note

Note C is the SCK0, SO0 output line load capacitance.

(ii) 3-wire serial I/O mode (SCK0 ··· external clock input)

Parameter

SCK0 cycle time

Symbol Test Conditions t

KCY2

V

DD

= 4.5 to 5.5 V

SCK0 high-/low-level width t

KH2

, t

KL2 t

SIK2

V

DD

= 4.5 to 5.5 V

SI0 setup time

(to SCK0



)

SI0 hold time

(from SCK0



)

SCK0

Ø Æ

SO0 output delay time

SCK0 rise, fall time t

KSI2 t

KSO2

C = 100 pF Note t

R2

, t

F2

Note C is the SO0 output line load capacitance.

MIN.

800

1600 t

KCY1

/2–50 t

KCY1

/2–100

100

150

400

TYP.

MAX.

300 ns ns ns ns

Unit ns ns ns ns

MIN.

800

1600

400

800

100

400

TYP.

MAX.

300

160 ns ns

Unit ns ns ns ns ns ns

48

m

PD78070A

(iii) SBI mode (SCK0 ··· internal clock output)

Parameter

SCK0 cycle time

Symbol Test Conditions t

KCY3

V

DD

= 4.5 to 5.5 V

SCK0 high-/low-level width t

KH3

, t

KL3

V

DD

= 4.5 to 5.5 V

SB0, SB1 setup time

(to SCK0



)

SB0, SB1 hold time

(from SCK0



)

SCK0

Ø Æ

SB0, SB1 output delay time

SCK0

 Æ

SB0, SB1

Ø

SB0, SB1

Ø Æ

SCK0

Ø

SB0, SB1 high-level width

SB0, SB1 low-level width t

SIK3 t

KSI3 t

KSO4 t

KSB t

SBK t

SBH t

SBL

V

DD

= 4.5 to 5.5 V

R = 1 k

W

,

C = 100 pF Note

V

DD

= 4.5 to 5.5 V 0

0 t

KCY3 t

KCY3 t

KCY3 t

KCY3

MIN.

800

3200 t

KCY3

/2–50 t

KCY3

/2–150

100

300 t

KCY3

/2

TYP.

Note R and C are the SCK0, SB0, SB1 output line load resistance and load capacitance.

(iv) SBI mode (SCK0 ··· external clock input)

Parameter

SCK0 cycle time

Symbol Test Conditions t

KCY4

V

DD

= 4.5 to 5.5 V

TYP.

SCK0 high-/low-level width t

KH4

, t

KL4

V

DD

= 4.5 to 5.5 V

SB0, SB1 setup time

(to SCK0



)

SB0, SB1 hold time

(from SCK0



)

SCK0

Ø Æ

SB0, SB1 output delay time

SCK0

 Æ

SB0, SB1

Ø

SB0, SB1

Ø Æ

SCK0

Ø

SB0, SB1 high-level width

SB0, SB1 low-level width

SCK0 rise, fall time t

SIK4

V

DD

= 4.5 to 5.5 V t

KSI4 t

KSO4

R = 1 k

W

,

C = 100 pF

Note t

KSB t

SBK t

SBH t

SBL t

R4

, t

F4

V

DD

= 4.5 to 5.5 V 0

0 t

KCY4 t

KCY4 t

KCY4 t

KCY4

MIN.

800

3200

400

1600

100

300 t

KCY4

/2

Note R and C are the SB0, SB1 output line load resistance and load capacitance.

MAX.

250

1000 ns ns ns ns ns ns ns ns ns ns

Unit ns ns ns

MAX.

300

1000

160 ns ns ns ns ns ns ns ns ns ns ns

Unit ns ns ns

49

m

PD78070A

(v) 2-wire serial I/O mode (SCK0 ··· internal clock output)

Parameter

SCK0 cycle time

SCK0 high-level width

SCK0 low-level width

SB0, SB1 setup time

(to SCK0



)

SB0, SB1 hold time

(from SCK0



)

SCK0

Ø Æ

SB0, SB1 output delay time t

Symbol Test Conditions

KCY5

R = 1 k

W

, t

KH5

C = 100 pF Note t

KL5 t

SIK5 t

KSI5 t

KSO5

MIN.

1600 t

KCY5

/2–160

V

DD

= 4.5 to 5.5 V t

KCY5

/2–50

TYP.

t

KCY5

/2–100

V

DD

= 4.5 to 5.5 V 300

350

600

0

Note R and C are the SCK0, SB0, SB1 output line load resistance and load capacitance.

(vi) 2-wire serial I/O mode (SCK0 ··· external clock input)

Parameter

SCK0 cycle time

SCK0 high-level width

SCK0 low-level width

SB0, SB1 setup time

(to SCK0



)

SB0, SB1 hold time

(from SCK0



)

SCK0

Ø Æ

SB0, SB1 output delay time

SCK0 rise, fall time

Symbol Test Conditions t

KCY6 t

KH6 t

KL6 t

SIK6 t

KSI6 t

KSO6 t

R6

, t

F6

R = 1 k

W

,

C = 100 pF Note

MIN.

1600

650

800

100 t

KCY6

/2

V

DD

= 4.5 to 5.5 V 0

0

Note R and C are the SB0, SB1 output line load resistance and load capacitance.

TYP.

MAX.

300 ns ns ns ns

Unit ns ns ns ns

MAX.

300

500

160 ns ns ns

Unit ns ns ns ns ns

50

m

PD78070A

(b) Serial Interface Channel 1

(i) 3-wire serial I/O mode (SCK1 ··· internal clock output)

Parameter

SCK1 cycle time

Symbol Test Conditions t

KCY7

V

DD

= 4.5 to 5.5 V

SCK1 high-/low-level width t

KH7

, t

KL7 t

SIK7

SI1 setup time

(to SCK1



)

SI1 hold time

(from SCK1



)

SCK1

Ø Æ

SO1 output delay time t t

KSI7

KSO7

V

DD

= 4.5 to 5.5 V

V

DD

= 4.5 to 5.5 V

C = 100 pF

Note

Note C is the SCK1, SO1 output line load capacitance.

(ii) 3-wire serial I/O mode (SCK1 ··· external clock input)

Parameter

SCK1 cycle time

Symbol Test Conditions t

KCY8

V

DD

= 4.5 to 5.5 V

SCK1 high-/low-level width t

KH8

, t

KL8

V

DD

= 4.5 to 5.5 V

SI1 setup time

(to SCK1



)

SI1 hold time

(from SCK1



)

SCK1

Ø Æ

SO1 output delay time

SCK1 rise, fall time t t t t

SIK8

KSI8

KSO8

R8

, t

F8

C = 100 pF

Note

Note C is the SO1 output line load capacitance.

MIN.

800

1600 t

KCY7

/2–50 t

KCY7

/2–100

100

150

400

TYP.

MAX.

300 ns ns ns

Unit ns ns ns ns ns

MIN.

800

1600

400

800

100

400

TYP.

MAX.

300

160 ns ns

Unit ns ns ns ns ns ns

51

m

PD78070A

(iii) 3-wire serial I/O mode with automatic transmission/reception function (SCK1 ··· internal clock output)

Parameter

SCK1 cycle time

Symbol Test Conditions t

KCY9

V

DD

= 4.5 to 5.5 V

SCK1 high-/low-level width

SI1 setup time

(to SCK1



)

SI1 hold time

(from SCK1



)

SCK1

Ø Æ

SO1 output delay time

SCK1

 Æ

STB



Strobe signal high-level width

Busy signal setup time

(to busy signal detection timing)

Busy signal hold time

(from busy signal detection

timing)

Busy inactive

Æ

SCK1

Ø t

KH9

, t

KL9 t

SIK9 t

KSI9 t

KSO9 t

SBD t

SBW t

BYS t

BYH t

SPS

V

DD

= 4.5 to 5.5 V

V

DD

= 4.5 to 5.5 V

C = 100 pF Note

V

DD

= 4.5 to 5.5 V

MIN.

800

1600 t

KCY9

/2–50 t

KCY9

/2–100

100

150

400

TYP.

t

KCY9

/2–100 t

KCY9

–30

100

100

150

MAX.

300 ns t

KCY9

/2+100 ns t

KCY9

+30 ns

2t

KCY9 ns ns ns ns ns ns ns ns

Unit ns ns ns

Note C is the SCK1, SO1 output line load capacitance.

(iv) 3-wire serial I/O mode with automatic transmission/reception function (SCK1 ··· external clock input)

Parameter

SCK1 cycle time

SCK1 high-/low-level width

SI1 setup time

(to SCK1



)

SI1 hold time

(from SCK1



)

SCK1

Ø Æ

SO1 output delay time

SCK1 rise, fall time

Symbol Test Conditions t

KCY10

V

DD

= 4.5 to 5.5 V t

KH10

, t

KL10 t

SIK10 t

KSI10 t

KSO10 t

R10

, t

F10

V

DD

= 4.5 to 5.5 V

C = 100 pF

Note

MIN.

800

1600

400

800

100

400

TYP.

MAX.

300

160

Unit ns ns ns ns ns ns ns ns

Note C is the SO1 output line load capacitance.

52

m

PD78070A

(c) Serial Interface Channel 2

(i) 3-wire serial I/O mode (SCK2 ··· internal clock output)

Parameter

SCK2 cycle time

Symbol Test Conditions t

KCY11

V

DD

= 4.5 to 5.5 V

SCK2 high-/low-level width t

KH11

, t

KL11 t

SIK11

SI2 setup time

(to SCK2



)

SI2 hold time

(from SCK2



)

SCK2

Ø Æ

SO2 output delay time t t

KSI11

KSO11

V

V

DD

DD

= 4.5 to 5.5 V

= 4.5 to 5.5 V

C = 100 pF Note

Note C is the SCK2, SO2 output line load capacitance.

(ii) 3-wire serial I/O mode (SCK2 ··· external clock input)

Parameter

SCK2 cycle time

Symbol Test Conditions t

KCY12

V

DD

= 4.5 to 5.5 V

SCK2 high-/low-level width t

KH12

, t

KL12 t

SIK12

SI2 setup time

(to SCK2



)

SI2 hold time

(from SCK2



)

SCK2

Ø Æ

SO2 output delay time

SCK2 rise, fall time t t t

KSI12

KSO12

R12 t

F12

,

V

DD

= 4.5 to 5.5 V

C = 100 pF Note

Note C is the SO2 output line load capacitance.

MIN.

800

1600 t

KCY11

/2–50 t

KCY11

/2–100

100

150

400

TYP.

MAX.

300 ns ns ns ns

Unit ns ns ns ns

MIN.

800

1600

400

800

100

400

TYP.

MAX.

300

160 ns ns

Unit ns ns ns ns ns ns

53

54

(iii) UART mode (Dedicated baud rate generator output)

Parameter

Transfer rate

Symbol Test Conditions

V

DD

= 4.5 to 5.5 V

(iv) UART mode (External clock input)

Parameter

ASCK cycle time

Symbol Test Conditions t

KCY13

V

DD

= 4.5 to 5.5 V

ASCK high-/low-level width t

KH13

, t

KL13

Transfer rate

V

DD

= 4.5 to 5.5 V

V

DD

= 4.5 to 5.5 V

ASCK rise, fall time t

R13

, t

F13 m

PD78070A

MIN.

TYP.

MAX.

78125

39063

Unit bps bps

MIN.

800

1600

400

800

TYP.

MAX.

39063

19531

160 ns bps bps ns

Unit ns ns ns

AC Timing Test Point (Excluding X1, XT1 Input)

0.8 V

DD

0.2 V

DD

Test Points

Clock Timing

1/f x t

XL t

XH

0.8 V

DD

0.2 V

DD

X1 Input

V

DD

– 0.5 V

0.4 V t

XTL

1/f

XT t

XTH

XT1 Input

V

DD

– 0.5 V

0.4 V

TI Timing

t

TIL00 , t

TIL01 t

TIH00, t

TIH01

TI00, TI01 t

TIL1

1/f

TI1 t

TIH1

TI1, TI2,

TI5, TI6 m

PD78070A

55

Read/Write Operation

External fetch (no wait):

A0-A15

AD0-AD7

Address t

ADS t

ASTH t

ADD1

Low-order

8-bit address

Hi-Z t

ADH

Instruction code t

RDD1 t

RDADH t

RDAST

ASTB

RD t

ASTRD t

RDL1 t

RDH

External fetch (wait insertion):

A0-A15

AD0-AD7 t

ADS t

ASTH

ASTB

Low-order

8-bit address t

ADH

RD

WAIT t

ASTRD t

RDWT1 t

ADD1

Hi-Z t

RDD1

Address

Instruction code t

RDADH t

RDAST t

WTL t

RDL1 t

WTRD t

RDH m

PD78070A

56

External data access (no wait):

A0-A15

AD0-AD7 t

ADS t

ASTH

Low-order

8-bit address t

ADD2

Hi-Z t

ADH

Read Data t

RDD2 t

RDH

Address

Hi-Z

ASTB

RD

WR t

ASTRD t t

RDL2

ASTWR

Write Data t

RDWD t

WRWD t

WDS t

WRL

Hi-Z t

WDH t

WRADH

External data access (wait insertion):

A0-A15

AD0-AD7

ASTB t

ADS t

ASTH

Low-order

8-bit address t

ADH t

ADD2

Hi-Z t

RDD2 t

ASTRD

RD t

RDL2

Address

Hi-Z

Read Data t

RDH

WR

WAIT t

RDWT2 t

WTL t

ASTWR t

WTRD

Write Data

Hi-Z t

RDWD t

WRWD t

WDS t

WRL t

WRWT t

WTL t

WTWR t

WDH t

WRADH m

PD78070A

57

Serial Transfer Timing

3-wire serial I/O mode:

t

KLm t

Rn t

KCYm t

KHm t

Fn

SCK0-SCK2 t

SIKm t

KSIm

Input Data

SI0-SI2 t

KSOm

SO0-SO2

Output Data

Remark

m = 1, 2, 7, 8, 11, 12 n = 2, 8, 12

SBI mode (bus release signal transfer):

t

KL3,4 t

R4 t

KCY3,4 t

KH3,4 t

F4

SCK0 t

KSB t t t t

SBH t

SBK

SB0, SB1 t

KSO3,4

SBI mode (command signal transfer):

SCK0 t

KSB t

SBK t

KL3,4 t

R4 t

KCY3,4 t

KH3,4 t

F4 t

SIK3,4 t

KSI3,4

SB0, SB1 t

KSO3,4 t

SIK3,4 t

KSI3,4 m

PD78070A

58

m

PD78070A

2-wire serial I/O mode:

t

KL5, 6 t

R6 t

KCY5, 6 t

KH5, 6 t

F6

SCK0 t

KSO5, 6 t

SIK5, 6 t

KSI5, 6

SB0, SB1

3-wire serial I/O mode with automatic transmission/reception function:

SO1

D2 D1 D0

SI1

D2 t

SIK9, 10 t

KSO9, 10

SCK1

D1 D0 t

KSI9, 10 t

KH9, 10 t

F10 t

KL9, 10 t

KCY9, 10 t

R10 t

SBD t

SBW

STB

D7

D7

3-wire serial I/O mode with automatic transmission/reception function (busy processing):

SCK1

7 8 9

Note

10

Note

t

BYS

10+n

Note

t

BYH t

SPS

BUSY

(Active high)

Note

The signal is not actually low here, but is represented in this way to show the timing.

UART mode (external clock input):

t

KL13 t

R13 t

KCY13 t

KH13 t

F13

ASCK

1

59

m

PD78070A

A/D Converter Characteristics (T

A

= –40 to +85 °C, AV

DD

= V

DD

= 2.7 to 5.5 V, AV

SS

= V

SS

= 0 V)

Parameter

Resolution

Total error

Note

Conversion time

Sampling time

Analog input voltage

Reference voltage

AV

REF0

-AV

SS resistance

Symbol Test Conditions t

CONV t

SAMP

V

IAN

AV

REF0

R

AIREF0

2.7 V - AV

REF0

- AV

DD

MIN.

8

19.1

12/f xx

AV

SS

2.7

4

TYP.

8

14

MAX.

8

0.6

200

AV

REF0

AV

DD

Unit bit

% m s m s

V

V k

W

Note Excluding quantization error (±1/2 LSB). Shown as a percentage of the full scale value.

Remark

f xx

: Main system clock frequency (f x

or f x

/2) f x

: Main system clock oscillation frequency

D/A Converter Characteristics (T

A

= –40 to +85 °C, V

DD

= 2.7 to 5.5 V, AV

SS

= V

SS

= 0 V)

Symbol Test Conditions MIN.

TYP.

Parameter

Resolution

Total error

Settling time

Output resistor

Analog reference voltage

AV

REF1

–AV

SS

resistance

R = 2 M

W

Note1

R = 4 M

W

Note1

R = 10 M

W

Note1

C = 30 pF

Note1

4.5 V - AV

REF1

- 5.5 V

2.7 V - AV

REF1

< 4.5 V

R

O

AV

REF1

Note2

R

AIREF1

DACS0, DACS1 = 55H

Note2

2.7

4

10

8

MAX.

8

1.2

0.8

0.6

10

15

V

DD

Notes 1. R and C are the D/A converter output pin load resistance and load capacitance.

2. Value for one D/A converter channel.

Remark

DACS0, DACS1: D/A conversion value setting registers 0, 1.

Unit bit

%

%

% m s m s k

W

V k

W

60

m

PD78070A

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T

A

= –40 to +85 °C)

Parameter Symbol Test Conditions

Data retention supply voltage V

DDDR

Data retention supply current I

DDDR

V

DDDR

= 1.8 V

When subsystem clock stopped and feedback resistor disconnected

Release signal setup time t

SREL

Oscillation stabilization wait t

WAIT time

Release by RESET

Release by interrupt

MIN.

1.8

0

TYP.

0.1

2 17 /f x

Note

MAX.

5.5

10

Unit

V m

A m s ms ms

Note 2

12

/f xx

or 2

14

/f xx

-2

17

/f xx

can be selected by bit 0-bit 2 (OSTS0-OSTS2) of oscillation stabilization time selection register

(OSTS).

Remark

f xx

: Main system clock frequency (f x

or f x

/2) f x

: Main system clock oscillation frequency

Data Retention Timing (STOP mode released by RESET)

STOP mode

Data retention mode

Internal reset operation

HALT mode

Operating mode

V

DD

V

DDDR t

SREL

STOP instruction execution

RESET t

WAIT

Data Retention Timing (Standby release signal: STOP mode released by interrupt signal)

HALT mode

Operating mode

STOP mode

Data retention mode

V

DD

V

DDDR

STOP instruction execution

Standby release signal

(interrupt request) t

SREL t

WAIT

61

Interrupt Input Timing

RESET Input Timing

INTP0-INTP6

RESET t

INTL t

RSL t

INTH m

PD78070A

62

m

PD78070A

12. PACKAGE DRAWINGS

100 PIN PLASTIC QFP (FINE PITCH) ( 14)

A

B

75

76

51

50 detail of lead end

100

1

26

25

G

H

I

M J

K

N

L

NOTE

Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.

L

M

N

P

Q

R

S

ITEM MILLIMETERS

A 16.0±0.2

B 14.0±0.2

INCHES

0.630±0.008

C

D

F

G

H

I

J

K

14.0±0.2

16.0±0.2

1.0

1.0

0.22

+0.05

–0.04

0.10

0.5 (T.P.)

1.0±0.2

0.630±0.008

0.039

0.039

0.009±0.002

0.004

0.020 (T.P.)

0.5±0.2

0.17

+0.03

–0.07

0.007

+0.001

–0.003

0.10

1.45

0.004

0.057

0.125±0.075

0.005±0.003

5°±5°

1.7 MAX.

5°±5°

0.067 MAX.

P100GC-50-7EA-2

63

64

m

PD78070A

100 PIN PLASTIC QFP (14

×

20)

A

B

80

81

51

50 detail of lead end

100

1

31

30

G

H I M

J

K

N

NOTE

Each lead centerline is located within 0.15

mm (0.006 inch) of its true position (T.P.) at maximum material condition.

L

M

N

P

Q

I

J

K

G

H

D

F

ITEM

A

B

C

S

L

MILLIMETERS

23.6±0.4

20.0±0.2

14.0±0.2

17.6±0.4

0.8

0.6

0.30±0.10

0.15

0.65 (T.P.)

1.8±0.2

0.8±0.2

0.15

+0.10

–0.05

0.10

2.7

0.1±0.1

3.0 MAX.

P100GF-65-3BA1-2

INCHES

0.929±0.016

0.795

+0.009

–0.008

0.551

+0.009

–0.008

0.693±0.016

0.031

0.024

0.012

+0.004

–0.005

0.006

0.026 (T.P.)

0.071

+0.008

–0.009

0.031

+0.009

–0.008

0.006

+0.004

–0.003

0.004

0.106

0.004±0.004

0.119 MAX.

m

PD78070A

13. RECOMMENDED SOLDERING CONDITIONS

It is recommended that the m

PD78070A be soldered under the following conditions.

For details on the recommended soldering conditions, refer to information document "Semiconductor Device Mounting

Technology Manual" (C10535E).

For soldering methods and conditions other than those recommended, please contact your NEC sales representative.

Table 13-1. Soldering Conditions for Surface Mount Devices (1/2)

(1)

m

PD78070AGC-7EA: 100-pin plastic QFP (Fine pitch) (14

¥

14 mm, resin thickness 1.45 mm)

Soldering Method

Infrared ray reflow

VPS

Partial heating

Soldering Conditions Symbol

Package peak temperature: 235 °C, Reflow time: 30 seconds or less (at 210 °C IR35-107-2 or higher), Number of reflow processes: 2 or less, Exposure limit: 7 days

Note

(10 hours pre-baking is required at 125 °C afterwards)

< Cautions >

(1) Wait for the device temperature to return to normal after the first reflow before starting the second reflow.

(2) Do not perform flux cleaning with water after the first reflow.

Package peak temperature: 215 °C, Reflow time: 40 seconds or less (at 200 °C VP15-107-2 or higher), Number of reflow processes: 2 or less, Exposure limit: 7 days

Note

(10 hours pre-baking is required at 125 °C afterwards)

< Cautions >

(1) Wait for the device temperature to return to normal after the first reflow before starting the second reflow.

(2) Do not perform flux cleaning with water after the first reflow.

Pin temperature: 300°C or below, Flow time: 3 seconds or less (per device side) —

Note Exposure limit before soldering after the dry pack package is opened. Storage conditions: 25 °C and relative humidity at 65% or less.

Caution Do not use different soldering methods together (except for partial heating method).

65

m

PD78070A

Table 13-1. Soldering Conditions for Surface Mount Devices (2/2)

(2)

m

PD78070AGF-3BA: 100-pin plastic QFP (14

¥

20 mm, resin thickness 2.7 mm)

Soldering Method

Infrared ray reflow

VPS

Wave soldering

Partial heating

Soldering Conditions

Package peak temperature: 235 °C, Reflow time: 30 seconds or less

(at 210 °C or higher), Number of reflow processes: 2 or less

< Cautions >

(1) Wait for the device temperature to return to normal after the first reflow before starting the second reflow.

(2) Do not perform flux cleaning with water after the first reflow.

Package peak temperature: 215 °C, Reflow time: 40 seconds or less

Symbol

IR35-00-2

VP15-00-2

(at 200 °C or higher), Number of reflow processes: 2 or less

< Cautions >

(1) Wait for the device temperature to return to normal after the first reflow before starting the second reflow.

(2) Do not perform flux cleaning with water after the first reflow.

Solder temperature: 260 °C or below, Flow time: 10 seconds or less,

Number of flow processes: 1, Preheating temperature: 120°C max.

(package surface temperature)

WS60-00-1

Pin temperature: 300°C or below, Flow time: 3 seconds or less (per device side) —

Caution Do not use different soldering methods together (except for partial heating method).

66

m

PD78070A

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available to support development of systems using the m

PD78070AY.

Language Processing Software

RA78K/0

Note 1, 2, 3, 4

CC78K/0 Note 1, 2, 3, 4

DF78078

Note 1, 2, 3, 4

CC78K/0–L

Note 1, 2, 3, 4

Debugging Tools

Assembler package common to the 78K/0 series

C compiler package common to the 78K/0 series

Device file common to the m

PD78078 subseries

C compiler library source file common to the 78K/0 series

IE-78000-R

IE-78000-R-A

Note8

IE-78000-R-BK

IE-78078-R-EM

EP-78064GC-R

EP-78064GF-R

EV-9500GC-100

EV-9200GF-100

SM78K0 Note 5, 6, 7

ID78K0 Note 4, 5, 6, 7, 8

SD78K/0

Note 1, 2

DF78078 Note 1, 2, 5, 6, 7

Real-Time OS

In-circuit emulator common to the 78K/0 series

In-circuit emulator common to the 78K/0 series (for the integrated debugger)

Break board common to the 78K/0 series

Emulation board common to the m

PD78078 subseries

Emulation probe common to the m

PD78064 subseries

Adapter mounted on the user system board prepared for 100-pin plastic QFP

Socket mounted on the user system board prepared for 100-pin plastic QFP

System simulator common to the 78K/0 series

Integrated debugger for the IE-78000-R-A

Screen debugger for the IE-78000-R

Device file common to the m

PD78078 subseries

RX78K/0 Note 1, 2, 3, 4

MX78K0 Note 1, 2, 3, 4

Real-time OS used for the 78K/0 series

OS used for the 78K/0 series

Notes 1. Based on PC-9800 series (MS-DOS TM )

2. Based on IBM PC/AT TM and its compatibles (PC DOS TM /IBM DOS TM /MS-DOS TM )

3. Based on HP9000 series 300 TM (HP-UX TM )

4. Based on HP9000 series 700 TM (HP-UX), SPARCstation TM (SunOS TM ), and EWS-4800 series (EWS-UX/V)

5. Based on PC-9800 series (MS-DOS + Windows TM )

6. Based on IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS + Windows)

7. Based on NEWS TM (NEWS-OS TM )

8. Under development

Remarks 1.

Please refer to the 78K/0 Series Selection Guide (IF-1185) for information on third party development tools.

2.

Use the RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0 and RX78K/0 in combination with the DF78078.

67

m

PD78070A

Fuzzy Inference Development Support System

FE9000

Note1

/FE9200

Note2

FT9080

Note1

/FT9085

Note3

FI78K0

Note 1, 3

FD78K0

Note 1, 3

Fuzzy knowledge data creation tool

Translator

Fuzzy inference module

Fuzzy inference debugger

Notes 1. Based on PC-9800 series (MS-DOS)

2. Based on IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS + Windows)

3. Based on IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS)

Remark

Please refer to the 78K/0 Series Selection Guide (IF-1185) for information on third party development tools.

68

m

PD78070A

APPENDIX B. RELATED DOCUMENTS

Documents Related to Devices

Document Name m

PD78070A, 78070AY User’s Manual

78K/0 Series User’s Manual—Instructions

78K/0 Series Instruction Table

78K/0 Series Instruction Set m

PD78070AY Special Function Register Table

Documents Related to Development Tools

Document No.

Japanese

IEU-907

IEU-849

U10903J

U10904J

U10133J

English

U10200E

IEU-1372

Document Name

RA78K Series Assembler Package

RA78K Series Structured Assembler Preprocessor

CC78K Series C Compiler

CC78K/0 C Compiler Application Note know-how

CC78K Series Library Source File

IE-78000-R

IE-78000-R-A

IE-78000-R-BK

IE-78078-R-EM

EP-78064

SM78K0 System Simulator

SM78K Series System Simulator

SD78K/0 Screen Debugger

PC-9800 Series (MS-DOS) Based

SD78K/0 Screen Debugger

IBM PC/AT (PC DOS) Based

Operation

Language

Operation

Language

Programming

Document No.

Japanese

EEU-809

EEU-815

EEU-817

EEU-656

EEU-655

EEA-618

English

EEU-1399

EEU-1404

EEU-1402

EEU-1280

EEU-1284

EEA-1208

EEU-777

EEU-810

U10057J

EEU-867

U10775J

EEU-934

Reference EEU-5002

External parts user U10092J open interface specification

Introduction EEU-852

Reference

Introduction

Reference

U10952J

EEU-5024

EEU-993

EEU-1398

U10057E

EEU-1427

EEU-1504

EEU-1522

U10181E

U10092E

EEU-1414

EEU-1413

Caution The contents of the documents listed above are subject to change without prior notice. Make sure to use the latest edition when starting design.

69

m

PD78070A

Documents Related to Embedded Software (User’s Manual)

Document Name

78K/0 Series Real-time OS Basic

Installation

Technical

Basic 78K/0 Series OS MX78K0

Fuzzy Knowledge Data Creation Tool

78K/0, 78K/II, and 87AD Series Fuzzy Inference Development Support System Translator

78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module

78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger

Document No.

Japanese

EEU-912

EEU-911

EEU-913

EEU-5010

EEU-829

EEU-862

EEU-858

EEU-921

English

EEU-1438

EEU-1444

EEU-1441

EEU-1458

Other Documents

Document Name

Package Manual

Semiconductor Device Mounting Technology Manual

NEC Semiconductor Device Quality Grades

NEC Semiconductor Device Reliability/Quality Control System

Electrostatic Discharge (ESD) Test

Semiconductor Device Quality Assurance Guide

Microcontroller-Related Product Guide – Third Party Products –

Document No.

Japanese

IEI-635

C10535J

IEI-620

IEM-5068

MEM-539

MEI-603

MEI-604

English

IEI-1213

C10535E

IEI-1209

MEI-1202

Caution The contents of the documents listed above are subject to change without prior notice. Be sure to use the latest edition when starting design.

70

[MEMO]

m

PD78070A

71

m

PD78070A

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded.

The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V

DD

or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

72

FIP and IEBus are trademarks of NEC Corporation.

MS-DOS and Windows are trademarks of Microsoft Corporation.

IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.

HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

SunOS is a trademark of Sun Microsystems, Inc.

NEWS and NEWS-OS are trademarks of Sony Corporation.

m

PD78070A

The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.

No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:

“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc.

The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance.

Anti-radioactive design is not implemented in this product.

M4 94.11

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