Renesas 78K/0S µPD789014, µPD789026, µPD789046, µPD789104, µPD789114, µPD789124, µPD789134, µPD789146, µPD789156, µPD789167, µPD789177, µPD789197AY, µPD789217AY, µPD789407A, µPD789417A, µPD789800, µPD789842 microcontroller User manual

To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

st

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both companies.

Therefore, although the old company name remains in this document, it is a valid

Renesas

Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

st

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry.

Notice

1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website.

2. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document.

No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others.

3. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.

4. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information.

5. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas

Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.

6. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein.

7. Renesas Electronics products are classified according to the following three quality grades: “Standard”, “High Quality”, and

“Specific”. The recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as “Specific” without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as “Specific” or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is “Standard” unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc.

“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots.

“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support.

“Specific”: Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life.

8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges.

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10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS

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11. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas

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12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries.

(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries.

(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.

User’s Manual

78K/0S Series

8-Bit Single-Chip Microcontroller

Instructions

Common to 78K/0S Series

Document No.

U11047EJ3V0UMJ1 (3rd edition)

Date Published November 2000 N CP(K)

©

Printed in Japan

1996

[MEMO]

2

User’s Manual U11047EJ3V0UM00

NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V

DD

or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

EEPROM is a trademark of NEC Corporation.

The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.

The following products are manufactured and sold based on a license contract with CP8 Transac regarding the EEPROM microcontroller patent.

These products cannot be used for an IC card (SMART CARD).

Applicable products:

µ

PD789146, 789156, 789197AY, 789217AY Subseries

User’s Manual U11047EJ3V0UM00

3

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•

•

•

•

•

•

The information in this document is current as of March, 1999. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information.

No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.

NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information.

While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features.

NEC semiconductor products are classified into the following three quality grades:

"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below.

Customers must check the quality grade of each semiconductor product before using it in a particular application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc.

The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application.

(Note)

(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.

(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

M8E 00. 4

4

User’s Manual U11047EJ3V0UM00

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:

•

Device availability

•

Ordering information

•

Product release schedule

•

Availability of related technical literature

•

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

•

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

Fax: 408-588-6130

800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 02

Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

Fax: 01908-670-290

NEC Electronics Italiana s.r.l.

Milano, Italy

Tel: 02-66 75 41

Fax: 02-66 75 42 99

NEC Electronics (Germany) GmbH

Benelux Office

Eindhoven, The Netherlands

Tel: 040-2445845

Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France

Tel: 01-30-67 58 00

Fax: 01-30-67 58 99

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

NEC Electronics (France) S.A.

Madrid Office

Madrid, Spain

Tel: 91-504-2787

Fax: 91-504-2860

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore

Tel: 65-253-8311

Fax: 65-250-3583

NEC Electronics (Germany) GmbH

Scandinavia Office

Taeby, Sweden

Tel: 08-63 80 820

Fax: 08-63 80 388

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-2719-2377

Fax: 02-2719-5951

NEC do Brasil S.A.

Electron Devices Division

Guarulhos-SP Brasil

Tel: 55-11-6462-6810

Fax: 55-11-6462-6829

J00.7

User’s Manual U11047EJ3V0UM00

5

Throughout

Page p. 52 p. 52 p. 54 p. 54

MAJOR REVISIONS IN THIS EDITION

Contents

• Addition of the following target products

µ

PD789046, 789104, 789114, 789124, 789134, 789146, 789156, 789167, 789177, 789197AY,

789217AY, 789407A, 789417A, and 789842 Subseries

• Deletion of the following target products

µ

PD789407, 789417, and 789806Y Subseries

Modification of MOV PSW, #byte instruction code

Modification of MOVW rp, AX instruction code

Modification of XOR A, r instruction code

Modification of CMP A, r instruction code

The mark shows major revised points.

6

User’s Manual U11047EJ3V0UM00

INTRODUCTION

Readers

Purpose

This manual is intended for users who wish to understand the functions of 78K/0S

Series products and to design and develop its application systems and programs.

78K/0S Series products

• µ

PD789014 Subseries:

• µ

PD789026 Subseries:

µ

µ

PD789011, 789012, 78P9014

PD789022, 789024, 789025, 789026, 78F9026

• µ

PD789046 Subseries

Note

:

µ

PD789046, 78F9046

• µ

PD789104 Subseries:

• µ

PD789114 Subseries:

µ

PD789101, 789102, 789104

µ

PD789111, 789112, 789114, 78F9116

• µ

PD789124 Subseries

Note

:

µ

PD789121, 789122, 789124

• µ

PD789134 Subseries

Note

:

µ

PD789131, 789132, 789134, 78F9136

• µ

PD789146 Subseries

Note

:

µ

PD789144, 789146

•

µ

PD789156 Subseries

Note

:

µ

PD789154, 789156, 78F9156

•

µ

PD789167 Subseries

Note

:

µ

PD789166, 789167

•

µ

PD789177 Subseries

Note

:

µ

PD789176, 789177, 78F9177

•

µ

PD789197AY Subseries

Note

:

µ

PD789196AY, 789197AY, 78F9197AY

•

µ

PD789217AY Subseries

Note

:

µ

PD789216AY, 789217AY, 78F9217AY

• µ

PD789407A Subseries:

• µ

PD789417A Subseries:

µ

PD789405A, 789406A, 789407A

µ

PD789415A, 789416A, 789417A, 78F9418A

• µ

PD789800 Subseries:

µ

PD789800, 78F9801

• µ

PD789842 Subseries

Note

:

µ

PD789841, 789842, 78F9842

Note Under development

This manual is intended for users to understand the instruction functions of 78K/0S

Series products.

Organization

The contents of this manual are broadly divided into the following.

•

CPU functions

•

Instruction set

•

Explanation of instructions

How to read this manual

It is assumed that the reader of this manual has general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers.

•

To check the details of the functions of an instruction whose mnemonic is known:

→

See APPENDICES A and B INSTRUCTION INDEX.

•

To check an instruction whose mnemonic is not known but whose general function is known:

→

Check the mnemonic in CHAPTER 4 INSTRUCTION SET, then the functions in

CHAPTER 5 EXPLANATION OF INSTRUCTIONS.

•

To understand the overall functions of the 78K/0S Series products instructions in general:

→

Read this manual in the order of the CONTENTS.

User’s Manual U11047EJ3V0UM00

7

Conventions

•

To learn the hardware functions of the 78K/0S Series products:

→

Refer to the user's manual for each product (see Related documents).

Data significance:

Note:

Caution:

Remark:

Numeral representation:

Higher digits on the left and lower digits on the right

Footnote for item marked with Note in the text

Information requiring particular attention

Supplementary information

Binary...............

××××

or

××××

B

Decimal ............

××××

Hexadecimal ....

××××

H

Related Documents

The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.

Document common to 78K/0S Series

Document Name

User's Manual Instructions

Document Number

English

This manual

Japanese

U11047J

Individual documents

•••• µµµµ

PD789014 Subseries

µ

PD789011, 789012 Data Sheet

µ

PD78P9014 Data Sheet

µ

PD789014 Subseries User's Manual

•••• µµµµ

PD789026 Subseries

Document Name

Document Name

Document Number

English Japanese

U11095E

U10912E

U11187E

U11095J

U10912J

U11187J

µ

PD789022, 789024, 789025, 789026 Data Sheet

µ

PD78F9026 Data Sheet

µ

PD789026 Subseries User's Manual

•••• µµµµ

PD789046 Subseries

Document Name

Document Number

English Japanese

U11715E

U11858E

U11919E

U11715J

U11858J

U11919J

µ

PD789046 Preliminary Product Information

µ

PD78F9046 Preliminary Product Information

µ

PD789046 Subseries User’s Manual

Document Number

English

U13380E

U13546E

U13600E

Japanese

U13380J

U13546J

U13600J

8

User’s Manual U11047EJ3V0UM00

•••• µµµµ

PD789104 Subseries

Document Name

µ

PD789101, 789102, 789104 Data Sheet

µ

PD789134 Subseries User’s Manual

•••• µµµµ

PD789114 Subseries

Document Name

µ

PD789111, 789112, 789114 Preliminary Product Information

µ

PD78F9116 Preliminary Product Information

µ

PD789134 Subseries User’s Manual

•••• µµµµ

PD789124 Subseries

Document Name

µ

PD789121, 789122, 789124 Preliminary Product Information

µ

PD789134 Subseries User’s Manual

•••• µµµµ

PD789134 Subseries

Document Name

µ

PD789131, 789132, 789134 Preliminary Product Information

µ

PD78F9136 Preliminary Product Information

µ

PD789134 Subseries User’s Manual

•••• µµµµ

PD789146, 789156 Subseries

Document Name

µ

PD789144, 789146, 789154, 789156 Preliminary Product Information

µ

PD78F9156 Preliminary Product Information

µ

PD789146, 789156 Subseries User’s Manual

•••• µµµµ

PD789167, 789177 Subseries

Document Name

µ

PD789166, 789167, 789176, 789177 Preliminary Product Information

µ

PD78F9177 Preliminary Product Information

µ

PD789177 Subseries User’s Manual

User’s Manual U11047EJ3V0UM00

Document Number

English Japanese

To be prepared U12815J

U13045E U13045J

Document Number

English Japanese

U13013E

U13037E

U13045E

U13013J

U13037J

U13045J

Document Number

English Japanese

U13025E

U13045E

U13025J

U13045J

Document Number

English

U13015E

U13036E

U13045E

Japanese

U13015J

U13036J

U13045J

Document Number

English Japanese

U13478E U13478J

To be prepared U13756J

U13651E U13651J

Document Number

English Japanese

To be prepared U14017J

To be prepared U14022J

To be prepared To be prepared

9

•••• µµµµ

PD789197AY Subseries

Document Name

µ

PD789196AY, 789197AY Preliminary Product Information

µ

PD78F9197Y Preliminary Product Information

µ

PD789217Y Subseries User’s Manual

•••• µµµµ

PD789217AY Subseries

Document Name

Document Number

English

U13853E

U13224E

U13186E

Japanese

U13853J

U13224J

U13186J

µ

PD789216Y, 789217Y Preliminary Product Information

µ

PD78F9217Y Preliminary Product Information

µ

PD789217Y Subseries User’s Manual

•••• µµµµ

PD789407A, 789417A Subseries

Document Name

Document Number

English Japanese

U13196E

U13205E

U13186E

U13196J

U13205J

U13186J

µ

PD789405A, 789406A, 789407A, 789415A, 789416A, 789417A Data Sheet

µ

PD78F9418A Data Sheet

µ

PD789407A, 789417A Subseries User's Manual

•••• µµµµ

PD789800 Subseries

Document Name

Document Number

English Japanese

To be prepared U14024J

To be prepared To be prepared

To be prepared U13952J

µ

PD789800 Data Sheet

µ

PD78F9801 Preliminary Product Information

µ

PD789800 Subseries User's Manual

•••• µµµµ

PD789842 Subseries

Document Name

Document Number

English

U12627E

U12626E

U12978E

Japanese

U12627J

U12626J

U12978J

µ

PD789841, 789842 Preliminary Product Information

µ

PD78F9842 Preliminary Product Information

µ

PD789842 Subseries User's Manual

Document Number

English Japanese

U13790E

U13901E

U13776E

U13790J

U13901J

U13776J

Caution The above documents are subject to change without prior notice. Be sure to use the latest version document when starting design.

10

User’s Manual U11047EJ3V0UM00

CONTENTS

CHAPTER 1 MEMORY SPACE................................................................................................................ 15

1.1

Memory Space........................................................................................................................................... 15

1.2

Internal Program Memory (Internal ROM) Space ................................................................................... 15

1.3

Vector Table Area ..................................................................................................................................... 17

1.4

CALLT Instruction Table Area ................................................................................................................. 20

1.5

Internal Data Memory Space .................................................................................................................... 20

1.6

Special Function Register (SFR) Area .................................................................................................... 22

CHAPTER 2 REGISTERS ........................................................................................................................ 23

2.1

Control Registers...................................................................................................................................... 23

2.1.1

Program counter (PC)................................................................................................................... 23

2.1.2

Program status word (PSW) ......................................................................................................... 23

2.1.3

Stack pointer (SP)......................................................................................................................... 24

2.2

General-Purpose Registers...................................................................................................................... 25

2.3

Special Function Registers (SFRs) ......................................................................................................... 27

CHAPTER 3 ADDRESSING ..................................................................................................................... 29

3.1

Addressing of Instruction Address ......................................................................................................... 29

3.1.1

Relative addressing ...................................................................................................................... 29

3.1.2

Immediate addressing .................................................................................................................. 30

3.1.3

Table indirect addressing.............................................................................................................. 31

3.1.4

Register addressing...................................................................................................................... 32

3.2

Addressing of Operand Address............................................................................................................. 33

3.2.1

Direct addressing.......................................................................................................................... 33

3.2.2

Short direct addressing................................................................................................................. 34

3.2.3

Special function register (SFR) addressing .................................................................................. 35

3.2.4

Register addressing...................................................................................................................... 36

3.2.5

Register indirect addressing ......................................................................................................... 37

3.2.6

Based addressing ......................................................................................................................... 38

3.2.7

Stack addressing .......................................................................................................................... 38

CHAPTER 4 INSTRUCTION SET ............................................................................................................. 39

4.1

Operation ................................................................................................................................................... 40

4.1.1

Operand representation and description formats ......................................................................... 40

4.1.2

Description of operation column ................................................................................................... 41

4.1.3

Description of flag column ............................................................................................................ 41

4.1.4

Description of clock column .......................................................................................................... 42

4.1.5

Operation list................................................................................................................................. 43

4.1.6

Instruction list by addressing ........................................................................................................ 48

4.2

Instruction Codes ..................................................................................................................................... 51

4.2.1

Description of instruction code table............................................................................................. 51

4.2.2

Instruction code list ....................................................................................................................... 52

User’s Manual U11047EJ3V0UM00

11

CHAPTER 5 EXPLANATION OF INSTRUCTIONS.................................................................................. 57

5.1

8-Bit Data Transfer Instructions .............................................................................................................. 59

5.2

16-Bit Data Transfer Instructions ............................................................................................................ 62

5.3

8-Bit Operation Instructions .................................................................................................................... 65

5.4

16-Bit Operation Instructions .................................................................................................................. 74

5.5

Increment/Decrement Instructions.......................................................................................................... 78

5.6

Rotate Instructions ................................................................................................................................... 83

5.7

Bit Manipulation Instructions .................................................................................................................. 88

5.8

CALL/RETURN Instructions ..................................................................................................................... 92

5.9

Stack Manipulation Instructions.............................................................................................................. 97

5.10

Unconditional Branch Instruction ......................................................................................................... 101

5.11

Conditional Branch Instructions ........................................................................................................... 103

5.12

CPU Control Instructions ....................................................................................................................... 111

APPENDIX A INSTRUCTION INDEX (MNEMONIC: BY FUNCTION) .................................................. 117

APPENDIX B INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER) ............................ 119

APPENDIX C REVISION HISTORY ........................................................................................................ 121

12

User’s Manual U11047EJ3V0UM00

LIST OF FIGURES

Figure No.

Title Page

2-1.

Format of Program Counter..............................................................................................................................23

2-2.

Format of Program Status Word.......................................................................................................................23

2-3.

Format of Stack Pointer....................................................................................................................................24

2-4.

Data to Be Saved to Stack Memory .................................................................................................................25

2-5.

Data to Be Restored from Stack Memory .........................................................................................................25

2-6.

General-Purpose Register Configuration .........................................................................................................26

LIST OF TABLES

Table No.

Title Page

1-1.

Internal ROM Space of 78K/0S Series Products ..............................................................................................15

1-2.

Vector Table (0000H to 0013H) (

µ

PD789014 Subseries) ................................................................................17

1-3.

Vector Table (0000H to 002BH) (

µ

PD789026 Subseries) ................................................................................17

1-4.

Vector Table (0000H to 0019H) (

µ

PD789046 Subseries) ................................................................................17

1-5.

Vector Table (0000H to 0015H) (

µ

PD789104, 789114, 789124, 789134 Subseries) ......................................17

1-6.

Vector Table (0000H to 0019H) (

µ

PD789146, 789156 Subseries) ..................................................................18

1-7.

Vector Table (0000H to 0023H) (

µ

PD789167, 789177 Subseries) ..................................................................18

1-8.

Vector Table (0000H to 0027H) (

µ

PD789197AY, 789217AY Subseries).........................................................18

1-9.

Vector Table (0000H to 0023H) (

µ

PD789407A and

µ

PD789417A Subseries).................................................19

1-10. Vector Table (0000H to 0019H) (

µ

PD789800 Subseries) ................................................................................19

1-11. Vector Table (0000H to 0023H) (

µ

PD789842 Subseries) ................................................................................19

1-12. Internal Data Memory Space of 78K/0S Series Products.................................................................................20

4-1.

Operand Representation and Description Formats ..........................................................................................40

User’s Manual U11047EJ3V0UM00

13

[MEMO]

14

User’s Manual U11047EJ3V0UM00

CHAPTER 1 MEMORY SPACE

1.1 Memory Space

The 78K/0S Series product program memory map varies depending on the internal memory capacity. For details of the memory mapped address area, refer to the User's Manual of each product.

1.2 Internal Program Memory (Internal ROM) Space

The 78K/0S Series product has internal ROM in the address space shown below. Program and table data, etc.

are stored in ROM. This memory space is usually addressed by the program counter (PC).

Table 1-1. Internal ROM Space of 78K/0S Series Products (1/2)

Capacity 2 Kbytes 4 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes 24 Kbytes

Address

Space

Subseries Name

µ

PD789014

Subseries

µ

PD789026

Subseries

µ

PD789046

Subseries

µ

PD789104

Subseries

µ

PD789114

Subseries

µ

PD789124

Subseries

µ

PD789134

Subseries

µ

PD789146

Subseries

µ

PD789156

Subseries

µ

PD789167

Subseries

µ

PD789177

Subseries

µ

PD789197AY

Subseries

0000H to

07FFH

0000H to

0FFFH

µ

PD789022

µ

PD789024

µ

PD789025

µ

PD789026

µ

PD78F9026

µ

PD789046

µ

PD78F9046

µ

PD789101

µ

PD789102

µ

PD789104

µ

µ

0000H to

1FFFH

µ

PD789011

µ

PD789012

µ

PD78P9014

µ

PD789111

µ

PD789112

µ

PD789114

µ

PD789121

µ

PD789122

µ

PD789124

µ

PD789131

µ

PD789132

µ

PD789134

PD789144

PD789154

0000H to

2FFFH

µ

µ

µ

µ

µ

µ

µ

0000H to

3FFFH

PD78F9116

PD78F9136

PD789146

PD789156

PD78F9156

PD789166

PD789176

µ

0000H to

5FFFH

PD789167

µ

PD789177

µ

PD78F9177

µ

PD789196AY

µ

PD789197AY

µ

PD78F9197AY

32 Kbytes

0000H to

7FFFH

User’s Manual U11047EJ3V0UM00

15

CHAPTER 1 MEMORY SPACE

Table 1-1. Internal ROM Space of 78K/0S Series Products (2/2)

Capacity

Address

Space

Subseries Name

µ

PD789217AY

Subseries

µ

PD789407A

Subseries

µ

PD789417A

Subseries

µ

PD789800

Subseries

µ

PD789842

Subseries

2 Kbytes

0000H to

07FFH

4 Kbytes

0000H to

0FFFH

8 Kbytes

0000H to

1FFFH

12 Kbytes

0000H to

2FFFH

16 Kbytes

0000H to

3FFFH

24 Kbytes

0000H to

5FFFH

32 Kbytes

0000H to

7FFFH

µ

PD789216AY

µ

PD789217AY

µ

PD78F9217AY

µ

PD789405A

µ

PD789406A

µ

PD789407A

µ

PD789800

µ

PD789415A

µ

PD789416A

µ

PD789417A

µ

PD78F9418A

µ

PD78F9801

µ

PD789841

µ

PD789842

µ

PD78F9842

16

User’s Manual U11047EJ3V0UM00

CHAPTER 1 MEMORY SPACE

1.3 Vector Table Area

The vector table area stores program start addresses to which execution branches when the RESET signal is input or when an interrupt request is generated. Of the 16-bit address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd address.

Table 1-2. Vector Table (0000H to 0013H) (

µµµµ

PD789014 Subseries)

Vector Table Address

0000H

0004H

0006H

0008H

000AH

Interrupt Request

RESET input

INTWDT

INTP0

INTP1

INTP2

Vector Table Address

000CH

000EH

0010H

0012H

Interrupt Request

INTSR/INTCSI0

INTST

INTTM0

INTTM1

Vector Table Address

0000H

0004H

0006H

0008H

000AH

Table 1-3. Vector Table (0000H to 002BH) (

µµµµ

PD789026 Subseries)

Interrupt Request

RESET input

INTWDT

INTP0

INTP1

INTP2

Vector Table Address

000CH

000EH

0010H

0014H

002AH

Interrupt Request

INTSR/INTCSI0

INTST

INTTM0

INTTM2

INTKR

Vector Table Address

0000H

0004H

0006H

0008H

000AH

000CH

Table 1-4. Vector Table (0000H to 0019H) (

µµµµ

PD789046 Subseries)

Interrupt Request

RESET input

INTWDT

INTP0

INTP1

INTP2

INTSR20/INTCSI20

Vector Table Address

000EH

0010H

0012H

0014H

0016H

0018H

Interrupt Request

INTST20

INTWT

INTWTI

INTTM80

INTTM90

INTKR00

Table 1-5. Vector Table (0000H to 0015H) (

µµµµ

PD789104, 789114, 789124, 789134 Subseries)

Vector Table Address

0000H

0004H

0006H

0008H

000AH

Interrupt Request

RESET input

INTWDT

INTP0

INTP1

INTP2

Vector Table Address

000CH

000EH

0010H

0012H

0014H

Interrupt Request

INTSR20/INTCSI20

INTST20

INTTM80

INTTM20

INTAD0

User’s Manual U11047EJ3V0UM00

17

CHAPTER 1 MEMORY SPACE

Table 1-6. Vector Table (0000H to 0019H) (

µµµµ

PD789146, 789156 Subseries)

Vector Table Address

0000H

0004H

0006H

0008H

000AH

000CH

Interrupt Request

RESET input

INTWDT

INTP0

INTP1

INTP2

INTSR20/INTCSI20

Vector Table Address

000EH

0010H

0012H

0014H

0016H

0018H

Interrupt Request

INTST20

INTTM80

INTTM20

INTAD0

INTLVI0

INTEE1

Table 1-7. Vector Table (0000H to 0023H) (

µµµµ

PD789167, 789177 Subseries)

Vector Table Address

0000H

0004H

0006H

0008H

000AH

000CH

000EH

0010H

Interrupt Request

RESET input

INTWDT

INTP0

INTP1

INTP2

INTP3

INTSR20/INTCSI20

INTST20

Vector Table Address

0012H

0014H

0016H

0018H

001AH

001CH

0022H

Interrupt Request

INTWT

INTWTI

INTTM80

INTTM81

INTTM82

INTTM90

INTAD0

Table 1-8. Vector Table (0000H to 0027H) (

µµµµ

PD789197AY, 789217AY Subseries)

Vector Table Address

0000H

0004H

0006H

0008H

000AH

000CH

000EH

0010H

0012H

0014H

Interrupt Request

RESET input

INTWDT

INTP0

INTP1

INTP2

INTP3

INTSR20/INTCSI20

INTST20

INTWT

INTWTI

Vector Table Address

0016H

0018H

001AH

001CH

001EH

0020H

0022H

0024H

0026H

Interrupt Request

INTTM80

INTTM81

INTTM82

INTTM90

INTSMB0

INTSMBOV0

INTAD0

INTLVI0

INTEE1

18

User’s Manual U11047EJ3V0UM00

CHAPTER 1 MEMORY SPACE

Table 1-9. Vector Table (0000H to 0023H) (

µµµµ

PD789407A and

µµµµ

PD789417A Subseries)

Vector Table Address

0000H

0004H

0006H

0008H

000AH

000CH

000EH

0010H

0012H

Interrupt Request

RESET input

INTWDT

INTP0

INTP1

INTP2

INTP3

INTSR00/INTCSI00

INTST00

INTWT

Vector Table Address

0014H

0016H

0018H

001AH

001CH

001EH

0020H

0022H

Interrupt Request

INTWTI

INTTM00

INTTM01

INTTM02

INTTM50

INTKR00

INTAD0

INTCMP0

Vector Table Address

0000H

0004H

0006H

0008H

000AH

000CH

Table 1-10. Vector Table (0000H to 0019H) (

µµµµ

PD789800 Subseries)

Interrupt Request

RESET input

INTWDT

INTUSBTM

INTUSBRT

INTUSBRD

INTUSBST

Vector Table Address

000EH

0010H

0012H

0014H

0016H

0018H

Interrupt Request

INTUSBRE

INTP0

INTCSI10

INTTM00

INTTM01

INTKR00

Vector Table Address

0000H

0004H

0006H

0008H

000AH

000CH

000EH

Table 1-11. Vector Table (0000H to 0023H) (

µµµµ

PD789842 Subseries)

Interrupt Request

RESET input

INTWDT

INTP0

INTP1

INTTM7

INTSER00

INTSR00

Vector Table Address

0016H

0018H

001AH

001CH

001EH

0020H

0022H

Interrupt Request

INTST00

INTWT

INTWTI

INTTM80

INTTM81

INTTM82

INTAD

User’s Manual U11047EJ3V0UM00

19

CHAPTER 1 MEMORY SPACE

1.4 CALLT Instruction Table Area

In a 64-byte address area 0040H to 007FH, the subroutine entry address of a 1-byte call instruction (CALLT) can be stored.

1.5 Internal Data Memory Space

The 78K/0S Series products incorporate the following data memory:

(1) Internal high-speed RAM

The 78K/0S Series products incorporate internal high-speed RAM in the address space shown in Table 1-12.

The internal high-speed RAM is also used as a stack memory.

(2) LCD display RAM (

µµµµ

PD789407A and

µµµµ

PD789417A Subseries)

LCD display RAM is allocated in the area between FA00H and FA1BH.

The LCD display RAM can also be used as ordinary RAM.

(3) EEPROM

TM

(

µµµµ

PD789146, 789156, 789197AY, 789217AY Subseries)

Electrically erasable PROM (EEPROM) is allocated in the address space shown in Table 1-12.

Unlike ordinary RAM, EEPROM retains the data it contains even when the power is turned off. Also, unlike

EPROM, the contents of EEPROM can be erased electrically, without the need to expose the chip to ultraviolet light.

Table 1-12. Internal Data Memory Space of 78K/0S Series Products (1/2)

Subseries Name

µ

PD789014

Subseries

µ

PD789026

Subseries

µ

PD789046

Subseries

µ

PD789104

Subseries

µ

PD789114

Subseries

Product Name

µ

PD789011

µ

PD789012

µ

PD78P9014

µ

PD789022

µ

PD789024

µ

PD789025

µ

PD789026

µ

PD78F9026

µ

PD789046

µ

PD78F9046

µ

PD789101

µ

PD789102

µ

PD789104

µ

PD789111

µ

PD789112

µ

PD789114

µ

PD78F9116

High-Speed RAM

FE80H to FEFFH

(128 bytes)

FE00H to FEFFH

(256 bytes)

FE00H to FEFFH

(256 bytes)

FD00H to FEFFH

(512 bytes)

FD00H to FEFFH

(512 bytes)

FE00H to FEFFH

(256 bytes)

FE00H to FEFFH

(256 bytes)

LCD Display RAM











EEPROM











20

User’s Manual U11047EJ3V0UM00

CHAPTER 1 MEMORY SPACE

Subseries Name

µ

PD789124

Subseries

µ

PD789134

Subseries

µ

PD789146

Subseries

µ

PD789156

Subseries

µ

PD789167

Subseries

µ

PD789177

Subseries

µ

PD789197AY

Subseries

µ

PD789217AY

Subseries

µ

PD789407A

Subseries

µ

PD789417A

Subseries

µ

PD789800

Subseries

µ

PD789842

Subseries

Table 1-12. Internal Data Memory Space of 78K/0S Series Products (2/2)

Product Name

µ

PD78F9177

µ

PD789196AY

µ

PD789197AY

µ

PD78F9197AY

µ

PD789216AY

µ

PD789217AY

µ

PD78F9217AY

µ

PD789405A

µ

PD789406A

µ

PD789407A

µ

PD789415A

µ

PD789416A

µ

PD789417A

µ

PD78F9418A

µ

PD789800

µ

PD78F9801

µ

PD789841

µ

PD789842

µ

PD789121

µ

PD789122

µ

PD789124

µ

PD789131

µ

PD789132

µ

PD789134

µ

PD78F9136

µ

PD789144

µ

PD789146

µ

PD789154

µ

PD789156

µ

PD78F9156

µ

PD789166

µ

PD789167

µ

PD789176

µ

PD789177

µ

PD78F9842

High-Speed RAM

FE00H to FEFFH

(256 bytes)

FE00H to FEFFH

(256 bytes)

FE00H to FEFFH

(256 bytes)

FE00H to FEFFH

(256 bytes)

FD00H to FEFFH

(512 bytes)

FD00H to FEFFH

(512 bytes)

FD00H to FEFFH

(512 bytes)

FD00H to FEFFH

(512 bytes)

FD00H to FEFFH

(512 bytes)

FD00H to FEFFH

(512 bytes)

FE00H to FEFFH

(256 bytes)

FE00H to FEFFH

(256 bytes)

LCD Display RAM

















FA00H to FA1BH

(28 bytes)

FA00H to FA1BH

(28 bytes)





EEPROM





F800H to F8FFH

(256 bytes)

F800H to F8FFH

(256 bytes)





F800H to F87FH

(128 bytes)

F800H to F87FH

(128 bytes)









User’s Manual U11047EJ3V0UM00

21

CHAPTER 1 MEMORY SPACE

1.6 Special Function Register (SFR) Area

Special-function registers (SFRs) of on-chip peripheral hardware are allocated to the area FF00H to FFFFH

(refer to the User's Manual of each product).

22

User’s Manual U11047EJ3V0UM00

CHAPTER 2 REGISTERS

2.1 Control Registers

The control registers have dedicated functions such as controlling the program sequence, statuses, and stack memory. The control registers include a program counter, program status word, and stack pointer.

2.1.1 Program counter (PC)

The program counter is a 16-bit register that holds the address information of the next program to be executed.

In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set.

______________

When the RESET signal is input, the program counter is set to the value of the reset vector table, which are located at addresses 0000H and 0001H.

Figure 2-1. Format of Program Counter

PC

15 0

PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

2.1.2 Program status word (PSW)

Program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.

The contents of program status word are automatically stacked when an interrupt request is generated or when the PUSH PSW instruction is executed and, are automatically reset when the RETI and POP PSW instruction are executed.

______________

RESET input sets PSW to 02H.

Figure 2-2. Format of Program Status Word

7

IE Z 0 AC 0 0 1

0

CY

User’s Manual U11047EJ3V0UM00

23

CHAPTER 2 REGISTERS

(1) Interrupt enable flag (IE)

This flag controls interrupt request acknowledge operations of the CPU.

When IE = 0, all interrupts except non-maskable interrupts are disabled (DI status).

When IE = 1, interrupts are enabled (EI status). At this time, acknowledgment of interrupt requests is controlled by the interrupt mask flag for each interrupt source.

The IE flag is reset (0) when the DI instruction execution is executed or when an interrupt is acknowledged, and set (1) when the EI instruction is executed.

(2) Zero flag (Z)

When the operation result is zero, this flag is set (1); otherwise, it is reset (0).

(3) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow to bit 3, this flag is set (1); otherwise, it is reset (0).

(4) Carry flag (CY)

This flag records an overflow or underflow upon add/subtract instruction execution. It also records the shiftout value upon rotate instruction execution, and functions as a bit accumulator during bit operation instruction execution.

2.1.3 Stack pointer (SP)

This is a 16-bit register that holds the first address of the stack area in the memory. Only the internal high-speed

RAM area can be set as the stack area.

Figure 2-3. Format of Stack Pointer

SP

15 0

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The SP is decremented ahead of write (save) to the stack memory, and is incremented after read (reset) from the stack memory.

The data saved/restored as a result of each stack operation are as shown in Figures 2-4 and 2-5.

Caution Since

______

RESET input makes the SP contents undefined, be sure to initialize the SP before executing an instruction.

24

User’s Manual U11047EJ3V0UM00

CHAPTER 2 REGISTERS

SP SP

−

2

SP

−

2

SP

−

1

SP

PUSH rp instruction

Figure 2-4. Data to Be Saved to Stack Memory

CALL, CALLT instructions

Lower byte in register pair

Upper byte in register pair

SP SP

−

2

SP

−

2

SP

−

1

SP

PC7 to PC0

PC15 to PC8

SP SP

−

3

SP

−

3

SP

−

2

SP

−

1

SP

Interrupt

PC7 to PC0

PC15 to PC8

PSW

Figure 2-5. Data to Be Restored from Stack Memory

POP rp instruction

RET instruction RETI instruction

SP

SP + 1

SP SP + 2

Lower byte in register pair

Upper byte in register pair

SP

SP + 1

SP SP + 2

PC7 to PC0

PC15 to PC8

SP

SP + 1

SP + 2

SP SP + 3

PC7 to PC0

PC15 to PC8

PSW

2.2 General-Purpose Registers

The general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H).

Each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a 16-bit register (AX,

BC, DE, and HL).

Registers can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3).

User’s Manual U11047EJ3V0UM00

25

CHAPTER 2 REGISTERS

15

Figure 2-6. General-Purpose Register Configuration

(a) Absolute name

16-bit processing

RP3

RP2

RP1

RP0

8-bit processing

R7

R6

R5

R4

R3

R2

R1

R0

0 7 0

15

16-bit processing

(b) Functional name

HL

DE

BC

AX

8-bit processing

H

L

D

E

B

C

A

X

0 7 0

26

User’s Manual U11047EJ3V0UM00

CHAPTER 2 REGISTERS

2.3 Special Function Registers (SFRs)

Unlike general-purpose registers, special function registers have their own functions and are allocated to the 256byte area FF00H to FFFFH.

A special function register can be manipulated, like a general-purpose register, by using operation, transfer, and bit manipulation instructions. The bit units in which one register is to be manipulated (1, 8, and 16) differ depending on the special function register type.

The bit unit for manipulation is specified as follows.

•

1-bit manipulation

Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address.

•

8-bit manipulation

Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address.

•

16-bit manipulation

Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When addressing an address, describe an even address.

For details of the special function registers, refer to the User's Manual of each product.

User’s Manual U11047EJ3V0UM00

27

[MEMO]

28

User’s Manual U11047EJ3V0UM00

CHAPTER 3 ADDRESSING

3.1 Addressing of Instruction Address

An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 per byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed. When a branch instruction is executed, the branch destination information is set in the PC and branched by the following addressing (For details of each instruction, see CHAPTER 5 EXPLANATION

OF INSTRUCTIONS).

3.1.1 Relative addressing

[Function]

The value obtained by adding the 8-bit immediate data (displacement value: jdisp8) of an instruction code to the first address of the following instruction is transferred to the program counter (PC) and program branches.

The displacement value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes a sign bit.

Thus, relative addressing causes a branch to an address within the range of –128 to +127, relative to the first address of the next instruction.

This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.

[Illustration]

15

15

α

PC

+

8 7 6

S

0

... PC holds the first address

of instruction next to

BR instruction.

0 jdisp8

PC

15

When S = 0, all bits of

α

are 0.

When S = 1, all bits of

α

are 1.

0

User’s Manual U11047EJ3V0UM00

29

CHAPTER 3 ADDRESSING

3.1.2 Immediate addressing

[Function]

Immediate data in the instruction word is transferred to the program counter (PC) and program branches.

This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed.

The CALL !addr16 and BR !addr16 instructions can be used to branch to any address within the memory spaces.

[Illustration]

In case of CALL !addr16 or BR !addr16 instruction

7 0

CALL or BR

Low addr.

High addr.

PC

15 8 7 0

30

User’s Manual U11047EJ3V0UM00

CHAPTER 3 ADDRESSING

3.1.3 Table indirect addressing

[Function]

Table contents (branch destination address) of a particular location, addressed by the immediate data of bits 1 to 5 of an instruction code are transferred to the program counter (PC), and program branches.

Table indirect addressing is performed when the CALLT [addr5] instruction is executed. This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to the entire memory space.

[Illustration]

Instruction code

7 6

0 1

5 ta

4 to 0

1 0

1

Effective address

15

0

8 7

0 0 0 0 0 0 0 0

6 5

1

1 0

0

Effective address + 1

7 Memory (table)

Low addr.

High addr.

0

PC

15 8 7 0

User’s Manual U11047EJ3V0UM00

31

CHAPTER 3 ADDRESSING

3.1.4 Register addressing

[Function]

Register pair (AX) contents specified with an instruction word are transferred to the program counter (PC) and program branches.

This function is carried out when the BR AX instruction is executed.

[Illustration]

7 0 7 0 rp A X

PC

15 8 7 0

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CHAPTER 3 ADDRESSING

3.2 Addressing of Operand Address

The following methods are available to specify the register and memory (addressing) which undergo manipulation during instruction execution.

3.2.1 Direct addressing

[Function]

This addressing directly addresses a memory to be manipulated with immediate data in an instruction word.

[Operand format]

Operand addr16 Label or 16-bit immediate data

Description

[Description example]

MOV A, !FE00H; When setting !addr16 to FE00H

Instruction code 0 0 1 0 1 0 0 1 OP code

0 0 0 0 0 0 0 0 00H

1 1 1 1 1 1 1 0 FEH

[Illustration]

7 0

OP code addr16 (lower) addr16 (higher)

Memory

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CHAPTER 3 ADDRESSING

3.2.2 Short direct addressing

[Function]

This addressing directly addresses memory to be manipulated in the fixed space with the 8-bit data in an instruction word.

This addressing is applied to the 256-byte fixed space of FE20H to FF1FH. An internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.

The SFR area (FF00H-FF1FH) to which short direct addressing is applied constitutes only part of the overall

SFR area. In this area, ports that are frequently accessed in a program and a compare register of the timer/event counter are mapped, and these SFRs can be manipulated with a small number of bytes and clocks.

When 8-bit immediate data is 20H to FFH, bit 8 of an effective address is set to 0. When it is 00H to 1FH, bit 8 is set to 1. See Illustration below.

[Operand format]

Operand saddr saddrp

Description

Label or FE20H to FF1FH immediate data

Label or FE20H to FF1FH immediate data (even address only)

[Description example]

MOV FE30H, #50H; When setting saddr to FE30H and the immediate data to 50H

Instruction code 1 1 1 1 0 1 0 1 OP code

0 0 1 1 0 0 0 0 30H (saddr-offset)

0 1 0 1 0 0 0 0 50H (immediate data)

[Illustration]

7 0

OP code saddr-offset

Short direct memory

Effective address

15

1 1 1 1 1 1 1

8

α

When 8-bit immediate data is 20H to FFH,

α

= 0.

When 8-bit immediate data is 00H to 1FH,

α

= 1.

0

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CHAPTER 3 ADDRESSING

3.2.3 Special function register (SFR) addressing

[Function]

This addressing is to address special function registers (SFRs) mapped to the memory with the 8-bit immediate data in an instruction word.

This addressing is applied to the 240-byte spaces of FF00H to FFCFH and FFE0H to FFFFH. However, the

SFRs mapped at FF00H to FF1FH can also be accessed by means of short direct addressing.

[Operand format]

sfr

Operand

Special function register name

Description

[Description example]

MOV PM0, A; When selecting PM0 for sfr

Instruction code 1 1 1 0 0 1 1 1

0 0 1 0 0 0 0 0

[Illustration]

7 0

OP code sfr-offset

SFR

Effective address

15

1 1 1 1 1 1 1 1

8 7

0

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CHAPTER 3 ADDRESSING

3.2.4 Register addressing

[Function]

This addressing is to access a general-purpose register by specifying it as an operand. The general-purpose register to be accessed is specified with a register specification code in an instruction code or function name.

Register addressing is carried out when an instruction with the following operand format is executed. When an

8-bit register is specified, one of the eight registers is specified with 3 bits (register specification code) in the instruction code.

[Operand format]

r rp

Operand

X, A, C, B, E, D, L, H

AX, BC, DE, HL

Description

'r' and 'rp' can be described with absolute names (R0 to R7 and RP0 to RP3) as well as functional names (X, A,

C, B, E, D, L, H, AX, BC, DE, and HL).

[Description example]

MOV A, C; When selecting the C register for r

Instruction code 0 0 0 0 1 0 1 0

0 0 1 0 0 1 0 1

Register specification code

INCW DE; When selecting the DE register pair for rp

Instruction code 1 0 0 0 1 0 0 0

Register specification code

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3.2.5 Register indirect addressing

[Function]

This addressing is to address memory using the contents of the special register pair as an operand. The register pair to be accessed is specified with the register pair specification code in an instruction code. This addressing can be carried out for the entire memory space.

[Operand format]

Operand



[DE], [HL]

[Description example]

MOV A, [DE]; When selecting register pair [DE]

Description

Instruction code 0 0 1 0 1 0 1 1

[Illustration]

DE

15 8 7

D

The contents of the specified memory address are transferred.

7 0

A

7

E

0

0

Memory address specified with register pair DE

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CHAPTER 3 ADDRESSING

3.2.6 Based addressing

[Function]

This addressing is to address the memory by using the result of adding 8-bit immediate data to the contents of the base register, i.e., the HL register pair. The addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for the entire memory space.

[Operand format]

Operand



[HL + byte]

[Description example]

MOV A, [HL+10H]; When setting “byte” to 10H

Description

Instruction code 0 0 1 0 1 1 0 1

0 0 0 1 0 0 0 0

3.2.7 Stack addressing

[Function]

This addressing is to indirectly address the stack area with the stack pointer (SP) contents.

This addressing method is automatically employed when the PUSH, POP, subroutine call, or RETURN instructions is executed or when the register is saved/restored upon generation of an interrupt request.

Stack addressing can address the internal high-speed RAM area only.

[Description example]

In the case of PUSH DE

Instruction code 1 0 1 0 1 0 1 0

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CHAPTER 4 INSTRUCTION SET

This chapter lists the instruction set of the 78K/0S Series. The instructions are common to all 78K/0S Series products.

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CHAPTER 4 INSTRUCTION SET

4.1 Operation

4.1.1 Operand representation and description formats

In the operand column of each instruction, an operand is described according to the description format for operand representation of that instruction (for details, refer to the assembler specifications). When there are two or more description methods, select one of them. Uppercase characters, #, !, $ and [ ] are keywords and must be described as is. Each symbol has the following meaning.

•

# : Immediate data

•

!

: Absolute address

•

$ : Relative address

•

[ ] : Indirect address

In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe #, !, $, or [ ].

For operand register description formats, r and rp, either functional names (X, A, C, etc.) or absolute names

(names in parentheses in the table below, R0, R1, R2, etc.) can be described.

Table 4-1. Operand Representation and Description Formats

Operand Description Format r rp sfr saddr saddrp addr16 addr5 word byte bit

X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)

AX (RP0), BC (RP1), DE (RP2), HL (RP3)

Special function register symbol

FE20H to FF1FH Immediate data or labels

FE20H to FF1FH Immediate data or labels (even addresses only)

0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)

0040H to 007FH Immediate data or labels (even addresses only)

16-bit immediate data or label

8-bit immediate data or label

3-bit immediate data or label

Remark

Refer to the User's Manual of each product for symbols of special function registers.

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4.1.2 Description of operation column

D:

E:

H:

L:

A:

X:

B:

C:

AX:

BC:

DE:

HL:

A register; 8-bit accumulator

X register

B register

C register

D register

E register

H register

L register

AX register pair; 16-bit accumulator

BC register pair

DE register pair

HL register pair

PC:

SP:

Program counter

Stack pointer

PSW: Program status word

CY: Carry flag

AC:

Z:

Auxiliary carry flag

Zero flag

IE: Interrupt request enable flag

NMIS: Non-maskable interrupt servicing flag

( ): Memory contents indicated by address or register contents in parentheses

X

H

, X

L

: Higher 8 bits and lower 8 bits of 16-bit register

∧

:

∨

:

∨

:

Logical product (AND)

Logical sum (OR)

Exclusive logical sum (exclusive OR)

: Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value)

4.1.3 Description of flag column

(Blank): Not affected

0: Cleared to 0

1:

×

:

R:

Set to 1

Set/cleared according to the result

Previously saved value is restored

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CHAPTER 4 INSTRUCTION SET

4.1.4 Description of clock column

The number of clock cycles during instruction execution is outlined as follows.

One instruction clock cycle is equal to one CPU clock cycle (f

CPU

) selected by the processor clock control register

(PCC).

The operation list is shown below.

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4.1.5 Operation list

Mnemonic Operand Byte Clock Operation Flag

Z AC CY

MOV

XCH

A, [HL]

[HL], A

A, [HL + byte]

[HL + byte], A

A, X

A, r

A, saddr

A, sfr

A, [DE]

A, [HL]

A, [HL + byte] r, #byte saddr, #byte sfr, #byte

A, r r, A

A, saddr saddr, A

A, sfr sfr, A

A, !addr16

!addr16, A

PSW, #byte

A, PSW

PSW, A

A, [DE]

[DE], A

Notes 1. Except r = A.

2. Except r = A, X.

Note 1

Note 1

Note 2

2

2

1

2

2

2

1

1

1

1

2

1

1

2

2

3

3

2

3

2

2

2

2

3

2

3

3

6 r

←

byte

6 (saddr)

←

byte

6 sfr

←

byte

4 A

←

r

4 r

←

A

4 A

←

(saddr)

4 (saddr)

←

A

4 A

←

sfr

4 sfr

←

A

8 A

←

(addr16)

8 (addr16)

←

A

6 PSW

←

byte

4 A

←

PSW

4 PSW

←

A

6 A

←

(DE)

6 (DE)

←

A

6 A

←

(HL)

6 (HL)

←

A

6 A

←

(HL + byte)

6 (HL + byte)

←

A

4 A

↔

X

6 A

↔

r

6 A

↔

(saddr)

6 A

↔

sfr

8 A

↔

(DE)

8 A

↔

(HL)

8 A

↔

(HL + byte)

× × ×

× × ×

Remark

One instruction clock cycle is equal to one CPU clock (f

CPU

) cycle selected by the processor clock control register (PCC).

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CHAPTER 4 INSTRUCTION SET

Mnemonic Operand Byte Clock Operation Flag

Z AC CY

MOVW

XCHW

ADD

ADDC rp, #word

AX, saddrp saddrp, AX

AX, rp rp, AX

AX, rp

A, #byte saddr, #byte

A, r

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

A, #byte saddr, #byte

A, r

A, saddr

A, !addr16

Note

Note

Note

SUB

A, [HL]

A, [HL + byte]

A, #byte saddr, #byte

A, r

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

Note Only when rp = BC, DE, or HL.

3

2

2

2

2

3

3

1

2

2

2

3

1

1

2

1

3

2

3

1

2

2

2

2

3

1

2

6 rp

←

word

6 AX

←

(saddrp)

8 (saddrp)

←

AX

4 AX

←

rp

4 rp

←

AX

8 AX

↔

rp

4 A, CY

←

A + byte

6 (saddr), CY

←

(saddr) + byte

4 A, CY

←

A + r

4 A, CY

←

A + (saddr)

8 A, CY

←

A + (addr16)

6 A, CY

←

A + (HL)

6 A, CY

←

A + (HL + byte)

4 A, CY

←

A + byte + CY

6 (saddr), CY

←

(saddr) + byte + CY

4 A, CY

←

A + r + CY

4 A, CY

←

A + (saddr) + CY

8 A, CY

←

A + (addr16) + CY

6 A, CY

←

A + (HL) + CY

6 A, CY

←

A + (HL + byte) + CY

4 A, CY

←

A – byte

6 (saddr), CY

←

(saddr) – byte

4 A, CY

←

A – r

4 A, CY

←

A – (saddr)

8 A, CY

←

A – (addr16)

6 A, CY

←

A – (HL)

6 A, CY

←

A – (HL + byte)

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

Remark

One instruction clock cycle is equal to one CPU clock (f

CPU

) cycle selected by the processor clock control register (PCC).

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CHAPTER 4 INSTRUCTION SET

Mnemonic Operand Byte Clock Operation Flag

SUBC

AND

OR

XOR

CMP

A, #byte saddr, #byte

A, r

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

A, #byte saddr, #byte

A, r

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

A, #byte saddr, #byte

A, r

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

A, #byte saddr, #byte

A, r

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

A, #byte saddr, #byte

A, r

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

2

3

2

2

3

1

2

2

3

2

2

3

1

2

2

3

2

2

3

1

2

2

3

2

2

3

1

2

2

3

2

2

3

1

2

4 A, CY

←

A – byte – CY

6 (saddr), CY

←

(saddr) – byte – CY

4 A, CY

←

A – r – CY

4 A, CY

←

A – (saddr) – CY

8 A, CY

←

A – (addr16) – CY

6 A, CY

←

A – (HL) – CY

6 A, CY

←

A – (HL + byte) – CY

4 A

←

A

∧ byte

6 (saddr)

←

(saddr)

∧ byte

4 A

←

A

∧ r

4 A

←

A

∧

(saddr)

8 A

←

A

∧

(addr16)

6 A

←

A

∧

(HL)

6 A

←

A

∧

(HL + byte)

4 A

←

A

∨ byte

6 (saddr)

←

(saddr)

∨ byte

4 A

←

A

∨ r

4 A

←

A

∨

(saddr)

8 A

←

A

∨

(addr16)

6 A

←

A

∨

(HL)

6 A

←

A

∨

(HL + byte)

4 A

←

A

∨ byte

6 (saddr)

←

(saddr)

∨ byte

4 A

←

A

∨ r

4 A

←

A

∨

(saddr)

8 A

←

A

∨

(addr16)

6 A

←

A

∨

(HL)

6 A

←

A

∨

(HL + byte)

4 A – byte

6 (saddr) – byte

4 A – r

4 A – (saddr)

8 A – (addr16)

6 A – (HL)

6 A – (HL + byte)

Z AC CY

×

×

×

×

×

×

×

×

×

×

×

×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

×

×

×

×

×

×

×

×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

× × ×

×

Remark

One instruction clock cycle is equal to one CPU clock (f

CPU

) cycle selected by the processor clock control register (PCC).

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CHAPTER 4 INSTRUCTION SET

Mnemonic Operand Byte Clock Operation Flag

ADDW

SUBW

CMPW

INC

DEC

INCW

DECW

ROR

ROL

RORC

ROLC

SET1

CLR1

SET1

CLR1

NOT1

CALL

CALLT r r

AX, #word

AX, #word

AX, #word saddr saddr rp rp

A, 1

A, 1

A, 1

A, 1 saddr.bit

sfr.bit

A.bit

PSW.bit

[HL].bit

saddr.bit

sfr.bit

A.bit

PSW.bit

[HL].bit

CY

CY

CY

!addr16

[addr5]

3

3

3

2

2

2

2

1

1

1

1

1

1

3

3

2

3

2

3

3

2

3

2

1

1

1

3

1

6 AX, CY

←

AX + word

6 AX, CY

←

AX – word

6 AX – word

4 r

←

r + 1

4 (saddr)

←

(saddr) + 1

4 r

←

r – 1

4 (saddr)

←

(saddr) – 1

4 rp

←

rp + 1

4 rp

←

rp – 1

2 (CY, A

7

←

A

0

, A m–1

←

A m

)

×

1

2 (CY, A

0

←

A

7

, A m+1

←

A m

)

×

1

2 (CY

←

A

0

, A

7

←

CY, A m–1

←

A m

)

×

1

2 (CY

←

A

7

, A

0

←

CY, A m+1

←

A m

)

×

1

6 (saddr.bit)

←

1

6 sfr.bit

←

1

4 A.bit

←

1

6 PSW.bit

←

1

10 (HL).bit

←

1

6 (saddr.bit)

←

0

6 sfr.bit

←

0

4 A.bit

←

0

6 PSW.bit

←

0

10 (HL).bit

←

0

2 CY

←

1

2 CY

←

0

2

CY

←

_____

CY

6 (SP – 1)

←

(PC + 3)

H

, (SP – 2)

←

(PC + 3)

L

,

PC

←

addr16, SP

←

SP – 2

8 (SP – 1)

←

(PC + 1)

H

, (SP – 2)

←

(PC + 1)

L

,

PC

H

←

(00000000, addr5 + 1),

PC

L

←

(00000000, addr5), SP

←

SP – 2

Z AC CY

× × ×

× × ×

× × ×

× ×

× ×

× ×

× ×

×

×

×

×

× × ×

× × ×

1

0

×

Remark

One instruction clock cycle is equal to one CPU clock (f

CPU

) cycle selected by the processor clock control register (PCC).

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CHAPTER 4 INSTRUCTION SET

Mnemonic Operand Byte Clock Operation Flag

Z AC CY

RET

RETI

PUSH

POP

MOVW

BR

BC

BNC

BZ

BNZ

BT

BF

DBNZ

NOP

EI

DI

HALT

STOP

PSW rp

PSW rp

SP,AX

AX,SP

!addr16

$addr16

AX

$addr16

$addr16

$addr16

$addr16 saddr.bit, $addr16 sfr.bit, $addr16

A.bit, $addr16

PSW.bit, $addr16 saddr.bit, $addr16 sfr.bit, $addr16

A.bit, $addr16

PSW.bit, $addr16

B, $addr16

C, $addr16 saddr, $addr16

4

3

2

4

2

2

1

2

3

2

2

2

1

1

1

1

2

3

4

2

4

3

4

4

3

1

1

3

1

1

1

6 PC

H

←

(SP + 1), PC

L

←

(SP), SP

←

SP + 2

8 PC

H

←

(SP + 1), PC

L

←

(SP),

PSW

←

(SP + 2), SP

←

SP + 3, NMIS

←

0

2 (SP – 1)

←

PSW, SP

←

SP – 1

4 (SP – 1)

←

rp

H

, (SP – 2)

←

rp

L

, SP

←

SP – 2

4 PSW

←

(SP), SP

←

SP + 1

6 rp

H

←

(SP + 1), rp

L

←

(SP), SP

←

SP + 2

8 SP

←

AX

6 AX

←

SP

6 PC

←

addr16

6 PC

←

PC + 2 + jdisp8

6 PC

H

←

A, PC

L

←

X

6 PC

←

PC + 2 + jdisp8 if CY = 1

6 PC

←

PC + 2 + jdisp8 if CY = 0

6 PC

←

PC + 2 + jdisp8 if Z = 1

6 PC

←

PC + 2 + jdisp8 if Z = 0

10 PC

←

PC + 4 + jdisp8 if (saddr.bit) = 1

10 PC

←

PC + 4 + jdisp8 if sfr.bit = 1

8 PC

←

PC + 3 + jdisp8 if A.bit = 1

10 PC

←

PC + 4 + jdisp8 if PSW.bit = 1

10 PC

←

PC + 4 + jdisp8 if (saddr.bit) = 0

10 PC

←

PC + 4 + jdisp8 if sfr.bit = 0

8 PC

←

PC + 3 + jdisp8 if A.bit = 0

10 PC

←

PC + 4 + jdisp8 if PSW.bit = 0

6 B

←

B – 1, then PC

←

PC + 2 + jdisp8 if B

≠

0

6 C

←

C – 1, then PC

←

PC + 2 + jdisp8 if C

≠

0

8 (saddr)

←

(saddr) – 1, then

PC

←

PC + 3 + jdisp8 if (saddr)

≠

0

2 No Operation

6 IE

←

1 (Enable Interrupt)

6 IE

←

0 (Disable Interrupt)

2 Set HALT Mode

2 Set STOP Mode

R R R

R R R

Remark

One instruction clock cycle is equal to one CPU clock (f

CPU

) cycle selected by the processor clock control register (PCC).

User’s Manual U11047EJ3V0UM00

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CHAPTER 4 INSTRUCTION SET

4.1.6 Instruction list by addressing

(1) 8-bit instructions

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,

POP, DBNZ

2nd operand

#byte

1st operand

A ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP r

A r sfr saddr !addr16

PSW [DE] [HL]

[HL + byte]

$addr16

MOV MOV

Note

MOV

Note

XCH

Note

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

MOV

XCH

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

MOV

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

MOV MOV

XCH

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

1

ROR

ROL

RORC

ROLC

None

INC

DEC

B, C sfr saddr

DBNZ

DBNZ INC

DEC

!addr16

PSW

MOV MOV

MOV

ADD

ADDC

SUB

SUBC

AND

OR

XOR

CMP

MOV

MOV

MOV MOV PUSH

POP

[DE]

[HL]

MOV

MOV

[HL + byte] MOV

Note Except r = A.

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CHAPTER 4 INSTRUCTION SET

(2) 16-bit instructions

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW

AX rp

Note

saddrp 2nd operand

1st operand

AX rp

#word

ADDW

SUBW

CMPW

MOVW MOVW

Note

MOVW

XCHW

MOVW MOVW

SP None

INCW

DECW

PUSH

POP saddrp

SP

MOVW

MOVW

Note Only when rp = BC, DE, HL.

(3) Bit manipulation instructions

SET1, CLR1, NOT1, BT, BF

2nd operand

1st operand

A.bit

sfr.bit

saddr.bit

PSW.bit

BT

BF

BT

BF

BT

BF

BT

BF

[HL].bit

$saddr

CY

SET1

CLR1

SET1

CLR1

SET1

CLR1

SET1

CLR1

SET1

CLR1

SET1

CLR1

NOT1

None

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CHAPTER 4 INSTRUCTION SET

(4) Call instructions/branch instructions

CALL, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, DBNZ

!addr16

2nd operand

1st operand

Basic instructions BR

AX

CALL

BR

[addr5]

CALLT

Compound instructions

$addr16

BR

BC

BNC

BZ

BNZ

DBNZ

(5) Other instructions

RET, RETI, NOP, EI, DI, HALT, STOP

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CHAPTER 4 INSTRUCTION SET

4.2 Instruction Codes

4.2.1 Description of instruction code table

r

R

2

1

1

1

1

0

0

0

0

R

1

1

1

0

0

1

1

0

0

R

0

0

1

0

1

0

1

0

1

R4

R5

R6

R7

R0

R1

R2

R3 reg

L

H

E

D

C

B

X

A rp

P

1

1

1

0

0

P

0

0

1

0

1 reg-pair

RP0 AX

RP1 BC

RP2 DE

RP3 HL

Bn:

Data:

Immediate data corresponding to “bit”

8-bit immediate data corresponding to “byte”

Low/High byte: 16-bit immediate data corresponding to “word”

Saddr-offset: 16-bit address lower 8-bit offset data corresponding to “saddr”

Sfr-offset: sfr 16-bit address lower 8-bit offset data

Low/High addr: 16-bit immediate data corresponding to “addr16” jdisp: Signed two's complement data (8 bits) of relative address distance between the start and branch addresses of the next instruction ta

4 to 0

: 5 bits of immediate data corresponding to “addr5”

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CHAPTER 4 INSTRUCTION SET

4.2.2 Instruction code list

Mnemonic Operand Instruction Code

B1 B2

MOV

XCH

MOVW r, #byte saddr, #byte sfr, #byte

A, r r, A

A, saddr saddr, A

A, sfr sfr, A

A, !addr16

!addr16, A

PSW, #byte

A, PSW

PSW, A

A, [DE]

[DE], A

Note 1

Note 1

A, [HL]

[HL], A

A, [HL + byte]

[HL + byte], A

A, X

A, r

A, saddr

A, sfr

Note 2

A, [DE]

A, [HL]

A, [HL + byte] rp, #word

AX, saddrp saddrp, AX

AX, rp rp, AX

AX, rp

Note 3

Note 3

Note 3

0 0 0 0 1 0 1 0 1 1 1 1 R

2

R

1

R

0

1

1 1 1 1 0 1 0 1 Saddr-offset

1 1 1 1 0 1 1 1 Sfr-offset

0 0 0 0 1 0 1 0 0 0 1 0 R

2

R

1

R

0

1

0 0 0 0 1 0 1 0 1 1 1 0 R

2

R

1

R

0

1

0 0 1 0 0 1 0 1 Saddr-offset

1 1 1 0 0 1 0 1

0 0 1 0 0 1 1 1

Saddr-offset

Sfr-offset

1 1 1 0 0 1 1 1

0 0 1 0 1 0 0 1

Sfr-offset

Low addr

1 1 1 0 1 0 0 1 Low addr

1 1 1 1 0 1 0 1 0 0 0 1 1 1 1 0

0 0 1 0 0 1 0 1 0 0 0 1 1 1 1 0

1 1 1 0 0 1 0 1 0 0 0 1 1 1 1 0

0 0 1 0 1 0 1 1

1 1 1 0 1 0 1 1

0 0 1 0 1 1 1 1

1 1 1 0 1 1 1 1

0 0 1 0 1 1 0 1

1 1 1 0 1 1 0 1

Data

Data

1 1 0 0 0 0 0 0

0 0 0 0 1 0 1 0 0 0 0 0 R

2

R

1

R

0

1

0 0 0 0 0 1 0 1

0 0 0 0 0 1 1 1

0 0 0 0 1 0 1 1

0 0 0 0 1 1 1 1

Saddr-offset

Sfr-offset

0 0 0 0 1 1 0 1

1 1 1 1 P

1

P

0

0 0

1 1 0 1 0 1 1 0

1 1 1 0 0 1 1 0

1 1 0 1 P

1

P

0

0 0

1 1 1 0 P

1

P

0

0 0

1 1 0 0 P

1

P

0

0 0

Data

Low byte

Saddr-offset

Saddr-offset

XCHW

Notes 1. Except r = A.

2. Except r = A, X.

3. Only when rp = BC, DE, or HL.

B3

Data

Data

Data

High addr

High addr

Data

High byte

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CHAPTER 4 INSTRUCTION SET

Mnemonic Operand

ADD

ADDC

SUB

SUBC

AND

A, !addr16

A, [HL]

A, [HL + byte]

A, #byte saddr, #byte

A, r

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

A, #byte saddr, #byte

A, r

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

A, #byte saddr, #byte

A, r

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

A, #byte saddr, #byte

A, r

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

A, #byte saddr, #byte

A, r

A, saddr

Instruction Code

B1 B2

1 0 0 0 0 0 1 1

1 0 0 0 0 0 0 1

1 0 0 0 1 0 0 1

1 0 0 0 1 1 1 1

Data

Saddr-offset

0 0 0 0 1 0 1 0 1 0 0 0 R

2

R

1

R

0

1

1 0 0 0 0 1 0 1 Saddr-offset

Low addr

1 0 0 0 1 1 0 1

1 0 1 0 0 0 1 1

Data

Data

1 0 1 0 0 0 0 1 Saddr-offset

0 0 0 0 1 0 1 0 1 0 1 0 R

2

R

1

R

0

1

1 0 1 0 0 1 0 1

1 0 1 0 1 0 0 1

Saddr-offset

Low addr

1 0 1 0 1 1 1 1

1 0 1 0 1 1 0 1

1 0 0 1 0 0 1 1

1 0 0 1 0 0 0 1

Data

Data

Saddr-offset

0 0 0 0 1 0 1 0 1 0 0 1 R

2

R

1

R

0

1

1 0 0 1 0 1 0 1 Saddr-offset

1 0 0 1 1 0 0 1

1 0 0 1 1 1 1 1

1 0 0 1 1 1 0 1

1 0 1 1 0 0 1 1

Low addr

Data

Data

1 0 1 1 0 0 0 1 Saddr-offset

0 0 0 0 1 0 1 0 1 0 1 1 R

2

R

1

R

0

1

1 0 1 1 0 1 0 1

1 0 1 1 1 0 0 1

Saddr-offset

Low addr

1 0 1 1 1 1 1 1

1 0 1 1 1 1 0 1

0 1 1 0 0 0 1 1

0 1 1 0 0 0 0 1

Data

Data

Saddr-offset

0 0 0 0 1 0 1 0 0 1 1 0 R

2

R

1

R

0

1

0 1 1 0 0 1 0 1

0 1 1 0 1 0 0 1

0 1 1 0 1 1 1 1

0 1 1 0 1 1 0 1

Saddr-offset

Low addr

Data

B3

Data

High addr

Data

High addr

Data

High addr

Data

High addr

Data

High addr

B4

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CHAPTER 4 INSTRUCTION SET

Mnemonic Operand

INCW

DECW

ROR

ROL

RORC

ROLC

OR

XOR

CMP

ADDW

SUBW

CMPW

INC

DEC

A, 1

A, 1

A, 1

A, 1 r saddr rp rp

A, !addr16

A, [HL]

A, [HL + byte]

AX, #word

AX, #word

AX, #word r saddr

A, #byte saddr, #byte

A, r

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

A, #byte saddr, #byte

A, r

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

A, #byte saddr, #byte

A, r

A, saddr

Instruction Code

B1 B2

0 1 1 1 0 0 1 1

0 1 1 1 0 0 0 1

0 1 1 1 1 0 0 1

0 1 1 1 1 1 1 1

Data

Saddr-offset

0 0 0 0 1 0 1 0 0 1 1 1 R

2

R

1

R

0

1

0 1 1 1 0 1 0 1 Saddr-offset

Low addr

0 1 1 1 1 1 0 1

0 1 0 0 0 0 1 1

Data

Data

0 1 0 0 0 0 0 1 Saddr-offset

0 0 0 0 1 0 1 0 0 1 0 0 R

2

R

1

R

0

1

0 1 0 0 0 1 0 1

0 1 0 0 1 0 0 1

Saddr-offset

Low addr

0 1 0 0 1 1 1 1

0 1 0 0 1 1 0 1

0 0 0 1 0 0 1 1

0 0 0 1 0 0 0 1

Data

Data

Saddr-offset

0 0 0 0 1 0 1 0 0 0 0 1 R

2

R

1

R

0

1

0 0 0 1 0 1 0 1 Saddr-offset

B3

Data

High addr

Data

High addr

Data

0 0 0 1 1 0 0 1

0 0 0 1 1 1 1 1

0 0 0 1 1 1 0 1

1 1 0 1 0 0 1 0

1 1 0 0 0 0 1 0

1 1 1 0 0 0 1 0

Low addr

Data

Low byte

Low byte

Low byte

0 0 0 0 1 0 1 0 1 1 0 0 R

2

R

1

R

0

1

1 1 0 0 0 1 0 1 Saddr-offset

0 0 0 0 1 0 1 0 1 1 0 1 R

2

R

1

R

0

1

1 1 0 1 0 1 0 1 Saddr-offset

1 0 0 0 P

1

P

0

0 0

1 0 0 1 P

1

P

0

0 0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 0

0 0 0 0 0 0 1 0

0 0 0 1 0 0 1 0

High addr

High byte

High byte

High byte

B4

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CHAPTER 4 INSTRUCTION SET

Mnemonic Operand

SET1

CLR1

BC

BNC

BZ

BNZ

BT

SET1

CLR1

NOT1

CALL

CALLT

RET

RETI

PUSH

POP

MOVW

BR

PSW rp

PSW rp

SP, AX

AX, SP

!addr16

$addr16

AX

$addr16

$addr16

$addr16

$addr16 saddr.bit, $addr16 sfr.bit, $addr16

A.bit, $addr16

PSW.bit, $addr16

PSW.bit

[HL].bit

CY

CY

CY

!addr16

[addr5] saddr.bit

sfr.bit

A.bit

PSW.bit

[HL].bit

saddr.bit

sfr.bit

A.bit

Instruction Code

B1 B2 B3

0 0 0 0 1 0 1 0 0 B

2

B

1

B

0

1 0 1 0

0 0 0 0 1 0 1 0 0 B

2

B

1

B

0

0 1 1 0

Saddr-offset

Sfr-offset

0 0 0 0 1 0 1 0 0 B

2

B

1

B

0

0 0 1 0

0 0 0 0 1 0 1 0 0 B

2

B

1

B

0

1 0 1 0 0 0 0 1 1 1 1 0

0 0 0 0 1 0 1 0 0 B

2

B

1

B

0

1 1 1 0

0 0 0 0 1 0 1 0 1 B

2

B

1

B

0

1 0 1 0

0 0 0 0 1 0 1 0 1 B

2

B

1

B

0

0 1 1 0

0 0 0 0 1 0 1 0 1 B

2

B

1

B

0

0 0 1 0

Saddr-offset

Sfr-offset

0 0 0 0 1 0 1 0 1 B

2

B

1

B

0

1 0 1 0 0 0 0 1 1 1 1 0

0 0 0 0 1 0 1 0 1 B

2

B

1

B

0

1 1 1 0

0 0 0 1 0 1 0 0

0 0 0 0 0 1 0 0

0 0 0 0 0 1 1 0

0 0 1 0 0 0 1 0

0 1 ta

4 to 0

0

0 0 1 0 0 0 0 0

0 0 1 0 0 1 0 0

0 0 1 0 1 1 1 0

Low addr High addr

1 0 1 0 P

1

P

0

1 0

0 0 1 0 1 1 0 0

1 0 1 0 P

1

P

0

0 0

1 1 1 0 0 1 1 0 0 0 0 1 1 1 0 0

1 1 0 1 0 1 1 0 0 0 0 1 1 1 0 0

1 0 1 1 0 0 1 0 Low addr

0 0 1 1 0 0 0 0

1 0 1 1 0 0 0 0 jdisp

High addr

0 0 1 1 1 0 0 0

0 0 1 1 1 0 1 0

0 0 1 1 1 1 0 0

0 0 1 1 1 1 1 0 jdisp jdisp jdisp jdisp

0 0 0 0 1 0 1 0 1 B

2

B

1

B

0

1 0 0 0

0 0 0 0 1 0 1 0 1 B

2

B

1

B

0

0 1 0 0

Saddr-offset

Sfr-offset

0 0 0 0 1 0 1 0 1 B

2

B

1

B

0

0 0 0 0 jdisp

0 0 0 0 1 0 1 0 1 B

2

B

1

B

0

1 0 0 0 0 0 0 1 1 1 1 0

B4 jdisp jdisp jdisp

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CHAPTER 4 INSTRUCTION SET

NOP

EI

DI

HALT

STOP

Mnemonic

BF

DBNZ

Operand saddr.bit, $addr16 sfr.bit, $addr16

A.bit, $addr16

PSW.bit, $addr16

B, $addr16

C, $addr16 saddr, $addr16

Instruction Code

B1 B2 B3

0 0 0 0 1 0 1 0 0 B

2

B

1

B

0

1 0 0 0

0 0 0 0 1 0 1 0 0 B

2

B

1

B

0

0 1 0 0

Saddr-offset

Sfr-offset

0 0 0 0 1 0 1 0 0 B

2

B

1

B

0

0 0 0 0 jdisp

0 0 0 0 1 0 1 0 0 B

2

B

1

B

0

1 0 0 0 0 0 0 1 1 1 1 0

0 0 1 1 0 1 1 0

0 0 1 1 0 1 0 0

0 0 1 1 0 0 1 0

0 0 0 0 1 0 0 0 jdisp jdisp

Saddr-offset jdisp

0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0

0 0 0 0 1 0 1 0 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0

0 0 0 0 1 1 0 0

0 0 0 0 1 1 1 0

B4 jdisp jdisp jdisp

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

This chapter explains the instructions of 78K/0S Series. Each instruction is described in the unit of mnemonic, including description of multiple operands.

The basic configuration of instruction descriptions is shown on the next page.

For the number of instruction bytes and operation codes, refer to CHAPTER 4 INSTRUCTION SET.

All the instructions are common to 78K/0S Series products.

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

MOV

Mnemonic

[Instruction format]

[Operation]

[Operand]

DESCRIPTION EXAMPLE

Full name

Move

Byte Data Transfer

Meaning of instruction

MOV dst, src: Indicates the basic description format of the instruction.

dst

←

src: Indicates instruction operation using symbols.

Indicates operands that can be specified with this instruction. Refer to 4.1 Operation for a description of each operand symbol.

Mnemonic

MOV

Operand (dst, src) r, #byte

A, saddr saddr, A

PSW, #byte

Mnemonic

MOV

Operand (dst, src)

A, PSW

[HL], A

A, [HL + byte]

[HL + C], A

[Flag]

Z AC

Indicates the operation of the flag that changes by instruction execution.

Each flag operation symbol is shown in the legend.

CY

Symbol

Blank

0

1

×

R

Legend

Description

Unchanged

Cleared to 0

Set to 1

Set or cleared according to the result

Previously saved value is restored

[Description] Describes the instruction operation in detail.

•

The contents of the source operand (src) specified by the 2nd operand are transferred to the destination operand (dst) specified by the 1st operand.

[Description example]

MOV A, #4DH; 4DH is transferred to A register.

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5.1 8-Bit Data Transfer Instructions

The following instructions are 8-bit data transfer instructions.

MOV ... 60

XCH ... 61

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

MOV

Move

Byte Data Transfer

[Instruction format]

[Operation]

[Operand]

MOV dst, src dst

←

src

Mnemonic Operand (dst, src)

MOV r, #byte saddr, #byte sfr, #byte

A, r r, A

Note

Except r = A

A, saddr saddr, A

A, sfr sfr, A

A, !addr16

Note

Note

[Flag]

PSW, #byte and PSW, A operands

All other operand combinations

Mnemonic

MOV

Operand (dst, src)

!addr16, A

PSW, #byte

A, PSW

PSW, A

A, [DE]

[DE], A

A, [HL]

[HL], A

A, [HL + byte]

[HL + byte], A

Z

×

AC

×

CY

×

Z AC CY

[Description]

•

The contents of the source operand (src) specified by the 2nd operand are transferred to the destination operand (dst) specified by the 1st operand.

•

No interrupts are acknowledged between the “MOV PSW, #byte” instruction or the “MOV PSW, A” instruction and the subsequent instruction.

[Description example]

MOV A, #4DH; 4DH is transferred to A register.

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XCH

[Instruction format]

[Operation]

[Operand]

XCH dst, src dst

↔

src

Mnemonic Operand (dst, src)

XCH A, X

A, r

A, saddr

A, sfr

A, [DE]

A, [HL]

A, [HL + byte]

Note

Except r = A, X

Note

[Flag]

Z AC CY

Exchange

Byte Data Exchange

[Description]

•

The 1st and 2nd operand contents are exchanged.

[Description example]

XCH A, 0FEBCH; The A register contents and address FEBCH contents are exchanged.

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

5.2 16-Bit Data Transfer Instructions

The following instructions are 16-bit data transfer instructions.

MOVW ... 63

XCHW ... 64

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MOVW

[Instruction format]

[Operation]

[Operand]

MOVW dst, src dst

←

src

Mnemonic Operand (dst, src)

MOVW rp, #word

AX, saddrp saddrp, AX

AX, rp rp, AX

Note

Only when rp = BC, DE or HL

Note

Note

[Flag]

Z AC CY

Move Word

Word Data Transfer

[Description]

•

The contents of the source operand (src) specified by the 2nd operand are transferred to the destination operand (dst) specified by the 1st operand.

[Description example]

MOVW AX, HL; The HL register contents are transferred to the AX register.

[Caution]

Only an even address can be specified to saddrp. An odd address cannot be specified.

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

XCHW

[Instruction format]

[Operation]

[Operand]

XCHW dst, src dst

↔

src

Mnemonic Operand (dst, src)

XCHW

AX, rp

Note

Only when rp = BC, DE or HL

Note

[Flag]

Z AC CY

Exchange Word

Word Data Exchange

[Description]

•

The 1st and 2nd operand contents are exchanged.

[Description example]

XCHW AX, BC; The memory contents of AX register are exchanged with those of the BC register.

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5.3 8-Bit Operation Instructions

The following are 8-bit operation instructions.

ADD ... 66

ADDC ... 67

SUB ... 68

SUBC ... 69

AND ... 70

OR ... 71

XOR ... 72

CMP ... 73

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

ADD

Add

Byte Data Addition

[Instruction format]

[Operation]

[Operand]

ADD dst, src dst, CY

←

dst + src

Mnemonic

ADD

Operand (dst, src)

A, #byte saddr, #byte

A, r

A, saddr

Mnemonic

ADD

Operand (dst, src)

A, !addr16

A, [HL]

A, [HL + byte]

[Flag]

Z

×

AC

×

CY

×

[Description]

•

The destination operand (dst) specified with the 1st operand is added to the source operand (src) specified with the 2nd operand and the result is stored in the CY flag and the destination operand (dst).

•

If the addition result shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).

•

If the addition generates a carry from bit 7, the CY flag is set (1). In all other cases, the CY flag is cleared (0).

•

If the addition generates a carry from bit 3 to bit 4, the AC flag is set (1). In all other cases, the AC flag is cleared (0).

[Description example]

ADD CR10, #56H; 56H is added to the CR10 register and the result is stored in the CR10 register.

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ADDC

Add with Carry

Addition of Byte Data with Carry

[Instruction format]

[Operation]

[Operand]

ADDC dst, src dst, CY

←

dst + src + CY

Mnemonic

ADDC

Operand (dst, src)

A, #byte saddr, #byte

A, r

A, saddr

Mnemonic

ADDC

Operand (dst, src)

A, !addr16

A, [HL]

A, [HL + byte]

[Flag]

Z

×

AC

×

CY

×

[Description]

•

The destination operand (dst) specified with the 1st operand, the source operand (src) specified with the 2nd operand, and the CY flag are added and the result is stored in the destination operand (dst) and the CY flag.

The CY flag is added to the least significant bit. This instruction is mainly used to add two or more bytes.

•

If the addition result shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).

•

If the addition generates a carry from bit 7, the CY flag is set (1). In all other cases, the CY flag is cleared (0).

•

If the addition generates a carry from bit 3 to bit 4, the AC flag is set (1). In all other cases, the AC flag is cleared (0).

[Description example]

ADDC A, [HL]; The A register contents, the contents at address (HL register), and the CY flag are added and the result is stored in the A register.

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

SUB

Subtract

Byte Data Subtraction

[Instruction format]

[Operation]

[Operand]

SUB dst, src dst, CY

←

dst – src

Mnemonic

SUB

Operand (dst, src)

A, #byte saddr, #byte

A, r

A, saddr

Mnemonic

SUB

Operand (dst, src)

A, !addr16

A, [HL]

A, [HL + byte]

[Flag]

Z

×

AC

×

CY

×

[Description]

•

The source operand (src) specified with the 2nd operand is subtracted from the destination operand (dst) specified with the 1st operand and the result is stored in the destination operand (dst) and the CY flag.

The destination operand can be cleared to 0 by equalizing the source operand (src) and the destination operand (dst).

•

If the subtraction shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).

•

If the subtraction generates a borrow at bit 7, the CY flag is set (1). In all other cases, the CY flag is cleared

(0).

•

If the subtraction generates a borrow from bit 4 to bit 3, the AC flag is set (1). In all other cases, the AC flag is cleared (0).

[Description example]

SUB A, D; The D register is subtracted from the A register and the result is stored in the A register.

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SUBC

Subtract with Carry

Subtraction of Byte Data with Carry

[Instruction format]

[Operation]

[Operand]

SUBC dst, src dst, CY

←

dst – src – CY

Mnemonic

SUBC

Operand (dst, src)

A, #byte saddr, #byte

A, r

A, saddr

Mnemonic

SUBC

Operand (dst, src)

A, !addr16

A, [HL]

A, [HL + byte]

[Flag]

Z

×

AC

×

CY

×

[Description]

•

The source operand (src) specified with the 2nd operand and the CY flag are subtracted from the destination operand (dst) specified with the 1st operand and the result is stored in the destination operand (dst).

The CY flag is subtracted from the least significant bit. This instruction is mainly used for subtraction of two or more bytes.

•

If the subtraction shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).

•

If the subtraction generates a borrow at bit 7, the CY flag is set (1). In all other cases, the CY flag is cleared

(0).

•

If the subtraction generates a borrow from bit 4 to bit 3, the AC flag is set (1). In all other cases, the AC flag is cleared (0).

[Description example]

SUBC A, [HL]; The (HL register) address contents and the CY flag are subtracted from the A register and the result is stored in the A register.

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AND

And

Logical Product of Byte Data

[Instruction format]

[Operation]

[Operand]

AND dst, src dst

←

dst

∧

src

Mnemonic

AND

Operand (dst, src)

A, #byte saddr, #byte

A, r

A, saddr

Mnemonic

AND

Operand (dst, src)

A, !addr16

A, [HL]

A, [HL + byte]

[Flag]

Z

×

AC CY

[Description]

•

The destination operand (dst) specified with the 1st operand and the source operand (src) specified with the

2nd operand are ANDed bit wise, and the result is stored in the destination operand (dst).

•

If the logical product shows that all bits are 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).

[Description example]

AND 0FEBAH, #11011100B; The FEBAH contents and 11011100B are ANDed bit wise and the result is stored at FEBAH.

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OR

Or

Logical Sum of Byte Data

[Instruction format]

[Operation]

[Operand]

OR dst, src dst

←

dst

∨

src

Mnemonic

OR

Operand (dst, src)

A, #byte saddr, #byte

A, r

A, saddr

Mnemonic

OR

Operand (dst, src)

A, !addr16

A, [HL]

A, [HL + byte]

[Flag]

Z

×

AC CY

[Description]

•

The destination operand (dst) specified with the 1st operand and the source operand (src) specified with the

2nd operand are ORed bit wise, and the result is stored in the destination operand (dst).

•

If the logical sum shows that all bits are 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).

[Description example]

OR A, 0FE98H; The A register and FE98H are ORed bit wise and the result is stored in the A register.

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XOR

Exclusive Or

Exclusive Logical Sum of Byte Data

[Instruction format]

[Operation]

[Operand]

XOR dst, src dst

←

dst

∨

src

Mnemonic

XOR

Operand (dst, src)

A, #byte saddr, #byte

A, r

A, saddr

Mnemonic

XOR

Operand (dst, src)

A, !addr16

A, [HL]

A, [HL + byte]

[Flag]

Z

×

AC CY

[Description]

•

The destination operand (dst) specified with the 1st operand and the source operand (src) specified with the

2nd operand are XORed bit wise, and the result is stored in the destination operand (dst).

Logical negation of all bits of the destination operand (dst) is possible with this instruction by selecting #0FFH for the source operand (src).

•

If the exclusive logical sum shows that all bits are 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).

[Description example]

XOR A, L; The A and L registers are XORed bit wise and the result is stored in the A register.

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CMP

Compare

Byte Data Comparison

[Instruction format]

[Operation]

[Operand]

CMP dst, src dst – src

Mnemonic

CMP

Operand (dst, src)

A, #byte saddr, #byte

A, r

A, saddr

Mnemonic

CMP

Operand (dst, src)

A, !addr16

A, [HL]

A, [HL + byte]

[Flag]

Z

×

AC

×

CY

×

[Description]

•

The source operand (src) specified with the 2nd operand is subtracted from the destination operand (dst) specified with the 1st operand.

The subtraction result is not stored anywhere and only the Z, AC, and CY flags are changed.

•

If the subtraction result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).

•

If the subtraction generates a borrow at bit 7, the CY flag is set (1). In all other cases, the CY flag is cleared

(0).

•

If the subtraction generates a borrow from bit 4 to bit 3, the AC flag is set (1). In all other cases, the AC flag is cleared (0).

[Description example]

CMP 0FE38H, #38H; 38H is subtracted from the contents at address FE38H and only the Z, AC, and CY flags are changed (comparison of contents at address FE38H and the immediate data).

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5.4 16-Bit Operation Instructions

The following are 16-bit operation instructions.

ADDW ... 75

SUBW ... 76

CMPW ... 77

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ADDW

Add Word

Word Data Addition

[Instruction format]

[Operation]

[Operand]

ADDW dst, src dst, CY

←

dst + src

Mnemonic

ADDW

Operand (dst, src)

AX, #word

[Flag]

Z

×

AC

×

CY

×

[Description]

•

The destination operand (dst) specified with the 1st operand is added to the source operand (src) specified with the 2nd operand and the result is stored in the destination operand (dst).

•

If the addition result shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).

•

If the addition generates a carry from bit 15, the CY flag is set (1). In all other cases, the CY flag is cleared

(0).

•

As a result of addition, the AC flag becomes undefined.

[Description example]

ADDW AX, #0ABCDH; ABCDH is added to the AX register and the result is stored in the AX register.

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SUBW

Subtract Word

Word Data Subtraction

[Instruction format]

[Operation]

[Operand]

SUBW dst, src dst, CY

←

dst – src

Mnemonic

SUBW

Operand (dst, src)

AX, #word

[Flag]

Z

×

AC

×

CY

×

[Description]

•

The source operand (src) specified with the 2nd operand is subtracted from the destination operand (dst) specified with the 1st operand and the result is stored in the destination operand (dst) and the CY flag.

The destination operand can be cleared to 0 by equalizing the source operand (src) and the destination operand (dst).

•

If the subtraction shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).

•

If the subtraction generates a borrow at bit 15, the CY flag is set (1). In all other cases, the CY flag is cleared

(0).

•

As a result of subtraction, the AC flag becomes undefined.

[Description example]

SUBW AX, #0ABCDH; ABCDH is subtracted from the AX register contents and the result is stored in the AX register.

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CMPW

Compare Word

Word Data Comparison

[Instruction format]

[Operation]

[Operand]

CMPW dst, src dst – src

Mnemonic

CMPW

Operand (dst, src)

AX, #word

[Flag]

Z

×

AC

×

CY

×

[Description]

•

The source operand (src) specified with the 2nd operand is subtracted from the destination operand (dst) specified with the 1st operand.

The subtraction result is not stored anywhere and only the Z, AC, and CY flags are changed.

•

If the subtraction result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).

•

If the subtraction generates a borrow at bit 15, the CY flag is set (1). In all other cases, the CY flag is cleared

(0).

•

As a result of subtraction, the AC flag becomes undefined.

[Description example]

CMPW AX, #0ABCDH; ABCDH is subtracted from the AX register and only the Z, AC, and CY flags are changed (comparison of the AX register and the immediate data).

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5.5 Increment/Decrement Instructions

The following are increment/decrement instructions.

INC ... 79

DEC ... 80

INCW ... 81

DECW ... 82

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INC

Increment

Byte Data Increment

[Instruction format]

[Operation]

[Operand]

INC dst dst

←

dst + 1

Mnemonic

INC r saddr

Operand (dst)

[Flag]

Z

×

AC

×

CY

[Description]

•

The destination operand (dst) contents are incremented by only one.

•

If the increment result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).

•

If the increment generates a carry from bit 3 to bit 4, the AC flag is set (1). In all other cases, the AC flag is cleared (0).

•

Because this instruction is frequently used for a counter for repeated operations, the CY flag contents are not changed (to hold the CY flag contents in multiple-byte operation).

[Description example]

INC B; The B register is incremented.

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DEC

Decrement

Byte Data Decrement

[Instruction format]

[Operation]

[Operand]

DEC dst dst

←

dst – 1

Mnemonic

DEC r saddr

Operand (dst)

[Flag]

Z

×

AC

×

CY

[Description]

•

•

•

The destination operand (dst) contents are decremented by only one.

If the decrement result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).

If the decrement generates a carry from bit 4 to bit 3, the AC flag is set (1). In all other cases, the AC flag is cleared (0).

•

Because this instruction is frequently used for a counter for repeated operations, the CY flag contents are not changed (to hold the CY flag contents in multiple-byte operation).

•

If dst is the B or C register or saddr, and it is not desired to change the AC and CY flag contents, the DBNZ instruction can be used.

[Description example]

DEC 0FE92H ; The contents at address FE92H are decremented.

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INCW

[Instruction format]

[Operation]

[Operand]

INCW dst dst

←

dst + 1

Mnemonic

INCW rp

Operand (dst)

[Flag]

Z AC CY

Increment Word

Word Data Increment

[Description]

•

The destination operand (dst) contents are incremented by only one.

•

Because this instruction is frequently used for increment of a register (pointer) used for addressing, the Z, AC, and CY flag contents are not changed.

[Description example]

INCW HL ; The HL register is incremented.

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DECW

[Instruction format]

[Operation]

[Operand]

DECW dst dst

←

dst – 1

Mnemonic

DECW rp

Operand (dst)

[Flag]

Z AC CY

Decrement Word

Word Data Decrement

[Description]

•

The destination operand (dst) contents are decremented by only one.

•

Because this instruction is frequently used for decrement of a register (pointer) used for addressing, the Z,

AC, and CY flag contents are not changed.

[Description example]

DECW DE ; The DE register is decremented.

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5.6 Rotate Instructions

The following are rotate instructions.

ROR ... 84

ROL ... 85

RORC ... 86

ROLC ... 87

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ROR

Rotate Right

Byte Data Rotation to the Right

[Instruction format]

[Operation]

[Operand]

ROR dst, cnt

(CY, dst

7

←

dst

Mnemonic

ROR A, 1

Operand (dst, cnt)

0

, dst m–1

←

dst m

)

×

one time

[Flag]

Z AC CY

×

[Description]

•

The destination operand (dst) contents specified with the 1st operand are rotated to the right just once.

•

The LSB (bit 0) contents are simultaneously rotated to MSB (bit 7) and transferred to the CY flag.

CY 7 0

[Description example]

ROR A, 1; The A register contents are rotated one bit to the right.

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ROL

Rotate Left

Byte Data Rotation to the Left

[Instruction format]

[Operation]

[Operand]

ROL dst, cnt

(CY, dst

0

←

0dst

Mnemonic

ROL A, 1

Operand (dst, cnt)

7

, dst m+1

←

dst m

)

×

one time

[Flag]

Z AC CY

×

[Description]

•

The destination operand (dst) contents specified with the 1st operand are rotated to the left just once.

•

The MSB (bit 7) contents are simultaneously rotated to LSB (bit 0) and transferred to the CY flag.

CY 7 0

[Description example]

ROL A, 1; The A register contents are rotated to the left by one bit.

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RORC

Rotate Right with Carry

Byte Data Rotation to the Right with Carry

[Instruction format]

[Operation]

[Operand]

RORC dst, cnt

(CY

←

dst

0

, dst

Mnemonic

RORC A, 1

Operand (dst, cnt)

7

←

CY, dst m–1

←

dst m

)

×

one time

[Flag]

Z AC CY

×

[Description]

•

The destination operand (dst) contents specified with the 1st operand are rotated just once to the right including the CY flag.

CY 7 0

[Description example]

RORC A, 1; The A register contents are rotated to the right by one bit including the CY flag.

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ROLC

Rotate Left with Carry

Byte Data Rotation to the Left with Carry

[Instruction format]

[Operation]

[Operand]

ROLC dst, cnt

(CY

←

dst

7

, dst

Mnemonic

ROLC A, 1

Operand (dst, cnt)

0

←

CY, dst m+1

←

dst m

)

×

one time

[Flag]

Z AC CY

×

[Description]

•

The destination operand (dst) contents specified with the 1st operand are rotated just once to the left including the CY flag.

CY 7 0

[Description example]

ROLC A, 1; The A register contents are rotated to the left by one bit including the CY flag.

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5.7 Bit Manipulation Instructions

The following are bit manipulation instructions.

SET1 ... 89

CLR1 ... 90

NOT1 ... 91

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SET1

Set Single Bit (Carry Flag)

1 Bit Data Set

[Instruction format]

[Operation]

[Operand]

SET1 dst dst

←

1

Mnemonic

SET1 saddr.bit

sfr.bit

A.bit

PSW.bit

[HL].bit

CY

Operand (dst)

[Flag]

dst = PSW.bit

Z

×

AC

×

CY

× dst = CY

Z AC CY

1

In all other cases

Z

[Description]

•

The destination operand (dst) is set (1).

•

When the destination operand (dst) is CY or PSW.bit, only the corresponding flag is set (1).

[Description example]

SET1 0FE55H.1; Bit 1 of FE55H is set (1).

AC CY

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CLR1

Clear Single Bit (Carry Flag)

1 Bit Data Clear

[Instruction format]

[Operation]

[Operand]

CLR1 dst dst

←

0

Mnemonic

CLR1 saddr.bit

sfr.bit

A.bit

PSW.bit

[HL].bit

CY

Operand (dst)

[Flag]

dst = PSW.bit

Z

×

AC

×

CY

× dst = CY

Z AC CY

0

In all other cases

Z

[Description]

•

The destination operand (dst) is cleared (0).

•

When the destination operand (dst) is CY or PSW.bit, only the corresponding flag is cleared (0).

[Description example]

CLR1 P3.7; Bit 7 of port 3 is cleared (0).

AC CY

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NOT1

[Instruction format]

[Operation]

[Operand]

NOT1 dst dst

←

_______ dst

Mnemonic

NOT1 CY

Operand (dst)

[Flag]

Z AC CY

×

[Description]

•

The CY flag is inverted.

[Description example]

NOT1 CY; The CY flag is inverted.

Not Single Bit (Carry Flag)

1 Bit Data Logical Negation

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5.8 CALL/RETURN Instructions

The following are call/return instructions.

CALL ... 93

CALLT ... 94

RET ... 95

RETI ... 96

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Call

Subroutine Call (16 Bit Direct)

CALL

[Instruction format]

[Operation]

CALL target

(SP – 1)

←

(PC + 3)

H

,

(SP – 2)

←

(PC + 3)

L

,

SP

PC

←

SP – 2,

←

target

[Operand]

Mnemonic

CALL

Operand (target)

!addr16

[Flag]

Z AC CY

[Description]

•

This is a subroutine call with a 16-bit absolute address or a register indirect address.

•

The next instruction’s start address (PC + 3) is saved in the stack and is branched to the address specified with the target operand (target).

[Description example]

CALL !3059H; Subroutine call to 3059H

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Call Table

Subroutine Call (Call Table Reference)

CALLT

[Instruction format]

[Operation]

CALLT [addr5]

(SP – 1)

←

(PC + 1)

H

,

(SP – 2)

←

(PC + 1)

L

,

SP

←

SP – 2,

PC

H

←

(00000000,addr5 + 1)

PC

L

←

(00000000,addr5)

[Operand]

Mnemonic

CALLT [addr5]

Operand ([addr5])

[Flag]

Z AC CY

[Description]

•

This is a subroutine call for call table reference.

•

The next instruction’s start address (PC + 1) is saved in the stack and is branched to the address indicated with the word data of a call table (the higher 8 bits of address are fixed to 00000000B and the following 5 bits are specified with addr5).

[Description example]

CALLT [40H]; Subroutine call to the addresses indicated by word data of 0040H and 0041H.

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RET

[Instruction format]

[Operation]

RET

PC

L

←

(SP),

PC

H

←

(SP + 1),

SP

←

SP + 2

[Operand]

None

[Flag]

Z AC CY

Return

Return from Subroutine

[Description]

•

This is a return instruction from the subroutine call made with the CALL and CALLT instructions.

•

The word data saved in the stack returns to the PC, and the program returns from the subroutine.

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RETI

Return from Interrupt

Return from Hardware Vectored Interrupt

[Instruction format]

[Operation]

RETI

PC

L

←

(SP),

PC

H

←

(SP + 1),

PSW

←

(SP + 2),

SP

←

SP + 3,

NMIS

←

0

[Operand]

None

[Flag]

Z

R

AC

R

CY

R

[Description]

•

This is a return instruction from the vectored interrupt.

•

The data saved in the stack returns to the PC and PSW, and the program returns from the interrupt service routine.

•

None of interrupts are acknowledged between this instruction and the next instruction to be executed.

•

The NMIS flag is set to 1 by acknowledgment of a non-maskable interrupt, and cleared to 0 by the RETI instruction.

[Caution]

When the return from non-maskable interrupt servicing is performed by an instruction other than the RETI instruction, the NMIS flag is not cleared to 0, and therefore no interrupts (including non-maskable interrupts) can be acknowledged.

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5.9 Stack Manipulation Instructions

The following are stack manipulation instructions.

PUSH ... 98

POP ... 99

MOVW SP, AX ... 100

MOVW AX, SP ... 100

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PUSH

[Instruction format]

[Operation]

PUSH src

When src = rp

(SP – 1)

←

src

H

,

(SP – 2)

←

src

L

,

SP

←

SP

−

2

[Operand]

Mnemonic

PUSH PSW rp

Operand (src)

[Flag]

Z AC CY

When src = PSW

(SP – 1)

←

src

SP

←

SP

−

1

[Description]

•

The data of the register specified with the source operand (src) is saved in the stack.

[Description example]

PUSH AX; AX register contents are saved in the stack.

Push

Push

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POP

[Instruction format]

[Operation]

POP dst

When dst = rp dst

L

←

(SP), dst

H

←

(SP + 1),

SP

←

SP + 2

[Operand]

Mnemonic

POP PSW rp

Operand (dst)

When dst = PSW dst

←

(SP)

SP

←

SP + 1

[Flag]

dst = rp

Z AC CY

PSW

Z

R

AC

R

CY

R

[Description]

•

Data is returned from the stack to the register specified with the destination operand (dst).

•

When the operand is PSW, each flag is replaced with stack data.

•

No interrupts are acknowledged between the POP PSW instruction and the subsequent instruction.

[Description example]

POP AX; The stack data is returned to the AX register.

Pop

Pop

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MOVW SP, AX

MOVW AX, SP

[Instruction format]

MOVW dst, src dst

←

src

[Operation]

[Operand]

Mnemonic

MOVW

Operand (dst, src)

SP, AX

AX, SP

[Flag]

Z AC CY

CHAPTER 5 EXPLANATION OF INSTRUCTIONS

Move Word

Word Data Transfer with Stack Pointer

[Description]

•

This is an instruction to manipulate the stack pointer contents.

•

The source operand (src) specified with the 2nd operand is stored in the destination operand (dst) specified with the 1st operand.

[Description example]

MOVW SP, AX; AX register contents are stored in the stack pointer.

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5.10 Unconditional Branch Instruction

The following is an unconditional branch instruction.

BR ... 102

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BR

[Instruction format]

[Operation]

[Operand]

BR target

PC

←

target

Mnemonic

BR

Operand (target)

!addr16

AX

$addr16

[Flag]

Z AC CY

Branch

Unconditional Branch

[Description]

•

This is an instruction to branch unconditionally.

•

The word data of the target address operand (target) is transferred to PC and program branches.

[Description example]

BR AX; The AX register contents are regarded as an address to which the program branches.

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

5.11 Conditional Branch Instructions

The following are conditional branch instructions.

BC ... 104

BNC ... 105

BZ ... 106

BNZ ... 107

BT ... 108

BF ... 109

DBNZ ... 110

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

BC

[Instruction format]

[Operation]

[Operand]

BC $addr16

PC

←

PC + 2 + jdisp8 if CY = 1

Mnemonic

BC

Operand ($addr16)

$addr16

[Flag]

Z AC CY

Branch if Carry

Conditional Branch with Carry Flag (CY = 1)

[Description]

•

When CY = 1, program branches to the address specified with the operand.

When CY = 0, no processing is carried out and the subsequent instruction is executed.

[Description example]

BC $300H; When CY = 1, program branches to 0300H (with the start of this instruction set in the range of addresses 027FH to 037EH).

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

BNC

[Instruction format]

[Operation]

[Operand]

BNC $addr16

PC

←

PC + 2 + jdisp8 if CY = 0

Mnemonic

BNC

Operand ($addr16)

$addr16

[Flag]

Z AC CY

Branch if Not Carry

Conditional Branch with Carry Flag (CY = 0)

[Description]

•

When CY = 0, program branches to the address specified with the operand.

When CY = 1, no processing is carried out and the subsequent instruction is executed.

[Description example]

BNC $300H; When CY = 0, program branches to 0300H (with the start of this instruction set in the range of addresses 027FH to 037EH).

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

Branch if Zero

Conditional Branch with Zero Flag (Z = 1)

BZ

[Instruction format]

[Operation]

[Operand]

BZ $addr16

PC

←

PC + 2 + jdisp8 if Z = 1

Mnemonic

BZ

Operand ($addr16)

$addr16

[Flag]

Z AC CY

[Description]

•

When Z = 1, program branches to the address specified with the operand.

When Z = 0, no processing is carried out and the subsequent instruction is executed.

[Description example]

DEC B

BZ $3C5H; When the B register is 0, program branches to 03C5H (with the start of this instruction set in the range of addresses 0344H to 0443H).

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

Branch if Not Zero

Conditional Branch with Zero Flag (Z = 0)

BNZ

[Instruction format]

[Operation]

[Operand]

BNZ $addr16

PC

←

PC + 2 + jdisp8 if Z = 0

Mnemonic

BNZ

Operand ($addr16)

$addr16

[Flag]

Z AC CY

[Description]

•

When Z = 0, program branches to the address specified with the operand.

When Z = 1, no processing is carried out and the subsequent instruction is executed.

[Description example]

CMP A, #55H

BNZ $0A39H; If the A register is not 0055H, program branches to 0A39H (with the start of this instruction set in the range of addresses 09B8H to 0AB7H).

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

BT

Branch if True

Conditional Branch by Bit Test (Byte Data Bit = 1)

[Instruction format]

[Operation]

[Operand]

BT bit, $addr16

PC

←

PC + b + jdisp8 if bit = 1

Mnemonic

BT

Operand (bit, $addr16) saddr.bit, $addr16 sfr.bit, $addr16

A.bit, $addr16

PSW.bit, $addr16 b (Number of bytes)

3

4

4

4

[Flag]

Z AC CY

[Description]

•

If the 1st operand (bit) contents have been set (1), program branches to the address specified with the 2nd operand ($addr16).

If the 1st operand (bit) contents have not been set (1), no processing is carried out and the subsequent instruction is executed.

[Description example]

BT 0FE47H.3, $55CH; When bit 3 at address FE47H is 1, program branches to 055CH (with the start of this instruction set in the range of addresses 04DAH to 05D9H).

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

BF

Branch if False

Conditional Branch by Bit Test (Byte Data Bit = 0)

[Instruction format]

[Operation]

[Operand]

BF bit, $addr16

PC

←

PC + b + jdisp8 if bit = 0

Mnemonic

BF

Operand (bit, $addr16) saddr.bit, $addr16 sfr.bit, $addr16

A.bit, $addr16

PSW.bit, $addr16 b (Number of bytes)

3

4

4

4

[Flag]

Z AC CY

[Description]

•

If the 1st operand (bit) contents have been cleared (0), program branches to the address specified with the

2nd operand ($addr16).

If the 1st operand (bit) contents have not been cleared (0), no processing is carried out and the subsequent instruction is executed.

[Description example]

BF P2.2, $1549H; When bit 2 of port 2 is 0, program branches to address 1549H (with the start of this instruction set in the range of addresses 14C6H to 15C5H).

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

DBNZ

[Instruction format]

[Operation]

DBNZ dst, $addr16 dst

←

dst – 1, then PC

←

PC + b + jdisp16 if dst R1

≠

0

[Operand]

Mnemonic

DBNZ

Operand (dst, $addr16)

B, $addr16

C, $addr16 saddr, $addr16 b (Number of bytes)

2

2

3

[Flag]

Z AC CY

Decrement and Branch if Not Zero

Conditional Loop (R1

≠≠≠≠

0)

[Description]

•

One is subtracted from the destination operand (dst) contents specified with the 1st operand and the subtraction result is stored in the destination operand (dst).

•

If the subtraction result is not 0, program branches to the address indicated with the 2nd operand ($addr16).

When the subtraction result is 0, no processing is carried out and the subsequent instruction is executed.

•

The flag remains unchanged.

[Description example]

DBNZ B, $1215H; The B register contents are decremented. If the result is not 0, program branches to 1215H

(with the start of this instruction set in the range of addresses 1194H to 1293H).

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

5.12 CPU Control Instructions

The following are CPU control instructions.

NOP ... 112

EI ... 113

DI ... 114

HALT ... 115

STOP ... 116

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

NOP

[Instruction format]

[Operation]

[Operand]

None

[Flag]

Z AC

NOP no operation

CY

[Description]

•

No processing is performed and only time is consumed.

No Operation

No Operation

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

EI

[Instruction format]

[Operation]

[Operand]

None

[Flag]

Z AC

EI

IE

←

1

CY

Enable Interrupt

Interrupt Enabled

[Description]

•

The maskable interrupt acknowledge-enable status is set (by setting the interrupt enable flag (IE) (1)).

•

Interrupts are acknowledged immediately after this instruction is executed.

•

If this instruction is executed, vectored interrupt acknowledgment with another source can be disabled. For details, refer to "Interrupt Functions" in the User's Manual of each product.

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

DI

[Instruction format]

[Operation]

[Operand]

None

[Flag]

Z AC

DI

IE

←

0

CY

Disable Interrupt

Interrupt Disabled

[Description]

•

Maskable interrupt acknowledgment with vectored interrupt is disabled (with the interrupt enable flag (IE) cleared (0)).

•

No interrupts are acknowledged between this instruction and the subsequent instruction.

•

For details of interrupt servicing, refer to "Interrupt Functions" in the User's Manual of each product.

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

HALT

[Instruction format]

[Operation]

[Operand]

None

[Flag]

Z AC

HALT

Set HALT Mode

CY

Halt

HALT Mode Set

[Description]

•

This instruction is used to set the HALT mode to stop the CPU operation clock. Total power consumption of the system can be reduced with intermittent operations through combination with the normal operation mode.

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CHAPTER 5 EXPLANATION OF INSTRUCTIONS

STOP

[Instruction format]

[Operation]

[Operand]

None

[Flag]

Z AC

STOP

Set STOP Mode

CY

Stop

Stop Mode Set

[Description]

•

This instruction is used to set the STOP mode to stop the main system clock oscillator and to stop the whole system. Power dissipation can be minimized to an ultra-low leakage current level only.

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APPENDIX A INSTRUCTION INDEX (MNEMONIC: BY FUNCTION)

[8-bit data transfer instructions]

MOV ... 60

XCH ... 61

[16-bit data transfer instructions]

MOVW ... 63

XCHW ... 64

[8-bit operation instructions]

ADD ... 66

ADDC ... 67

SUB ... 68

SUBC ... 69

AND ... 70

OR ... 71

XOR ... 72

CMP ... 73

[16-bit operation instructions]

ADDW ... 75

SUBW ... 76

CMPW ... 77

[Increment/decrement instructions]

INC ... 79

DEC ... 80

INCW ... 81

DECW ... 82

[Rotate instructions]

ROR ... 84

ROL ... 85

RORC ... 86

ROLC ... 87

[Bit manipulation instructions]

SET1 ... 89

CLR1 ... 90

NOT1 ... 91

[Call/return instructions]

CALL ... 93

CALLT ... 94

RET ... 95

RETI ... 96

[Stack manipulation instructions]

PUSH ... 98

POP ... 99

MOVW SP, AX ... 100

MOVW AX, SP ... 100

[Unconditional branch instruction]

BR ... 102

[Conditional branch instructions]

BC ... 104

BNC ... 105

BZ ... 106

BNZ ... 107

BT ... 108

BF ... 109

DBNZ ... 110

[CPU control instructions]

NOP ... 112

EI ... 113

DI ... 114

HALT ... 115

STOP ... 116

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[MEMO]

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APPENDIX B INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER)

[C]

CALL ... 93

CALLT ... 94

CLR1 ... 90

CMP ... 73

CMPW ... 77

[D]

DBNZ ... 110

DEC ... 80

DECW ... 82

DI ... 114

[E]

EI ... 113

[A]

ADD ... 66

ADDC ... 67

ADDW ... 75

AND ... 70

[B]

BC ... 104

BF ... 109

BNC ... 105

BNZ ... 107

BR ... 102

BT ... 108

BZ ... 106

[H]

HALT ... 115

[I]

INC ... 79

INCW ... 81

[S]

SET1 ... 89

STOP ... 116

SUB ... 68

SUBC ... 69

SUBW ... 76

[X]

XCH ... 61

XCHW ... 64

XOR ... 72

[M]

MOV ... 60

MOVW ... 63

MOVW AX, SP ... 100

MOVW SP, AX ... 100

[N]

NOP ... 112

NOT1 ... 91

[O]

OR ... 71

[P]

POP ... 99

PUSH ... 98

[R]

RET ... 95

RETI ... 96

ROL ... 85

ROLC ... 87

ROR ... 84

RORC ... 86

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[MEMO]

120

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APPENDIX C REVISION HISTORY

A history of the revisions up to this edition is shown below. “Applied to:” indicates the chapters to which the revision was applied.

2nd

Edition

3rd

Contents

Addition of the following target products

µ

PD789026, 789407, 789417, 789800, and 789806Y Subseries

Modification of the format of the table of the internal data memory space of the

78K/0S Series products

Addition of the following target products

µ

PD789046, 789104, 789114, 789124, 789134, 789146, 789156, 789167,

789177, 789197AY, 789217AY, 789407A, 789417A, and 789842 Subseries

Deletion of the following target products

µ

PD789407, 789417, and 789806Y Subseries

Modification of MOV PSW, #byte instruction code

Modification of MOVW rp, AX instruction code

Modification of XOR A, r instruction code

Modification of CMP A, r instruction code

Applied to:

Throughout

CHAPTER 1 MEMORY

SPACE

Throughout

CHAPTER 4 INSTRUCTION

SET

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[MEMO]

122

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