AOZ8005 Ultra-Low Capacitance TVS Diode Array General Description

AOZ8005 Ultra-Low Capacitance TVS Diode Array  General Description

AOZ8005

Ultra-Low Capacitance TVS Diode Array

General Description

The AOZ8005 is a transient voltage suppressor array designed to protect high speed data lines such as HDMI and Gigabit Ethernet from damaging ESD events.

This device incorporates eight surge rated, low capacitance steering diodes and a TVS in a single package.

During transient conditions, the steering diodes direct the transient to either the positive side of the power supply line or to ground.

The AOZ8005 provides a typical line to line capacitance of 0.47pF and low insertion loss up to 2GHz providing greater signal integrity making it ideally suited for HDMI

1.3 applications, such as Digital TVs, DVD players, set-top boxes and mobile computing devices.

The AOZ8005 comes in tiny SOT-23-6 and MSOP-10 packages and is rated -40°C to +85°C junction temperature range.

The MSOP package features a flow through layout design.

Features

ESD protection for high-speed data lines:

– IEC 61000-4-2, level 4 (ESD) immunity test

– ±15kV (air discharge) and ±8kV (contact discharge)

– Human Body Model (HBM) ±15kV

Array of surge rated diodes with internal TVS diode

Small package saves board space

Protects four I/O lines

Low capacitance between I/O lines: 0.47pF

Low clamping voltage

Low operating voltage: 5.0V

Applications

HDMI ports

Monitors and flat panel displays

Set-top box

USB 2.0 power and data line protection

Video graphics cards

Digital Video Interface (DVI)

10/100/1000 Ethernet

Notebook computers

Typical Application

AOZ8005 AOZ8005

TX2+

TX2-

HDMI

Transmitter

TX1+

TX1-

TX0+

TX0-

CLK+

CLK-

Rev. 2.5 December 2009

Connector Connector

AOZ8005

Figure 1. HDMI Ports

www.aosmd.com

AOZ8005

RX2+

RX2-

RX1+

RX1-

HDMI

Receiver

RX0+

RX0-

CLK+

CLK-

Page 1 of 14

AOZ8005

Ordering Information

Part Number

AOZ8005CIL

AOZ8005FIL

Ambient Temperature Range

-40°C to +85°C

Package

SOT-23-6

MSOP-10

AOS Green Products use reduced levels of Halogens, and are also RoHS compliant.

Please visit www.aosmd.com/web/quality/rohs_compliant.jsp

for additional information.

Pin Configuration

Environmental

RoHS Compliant

Green Product

CH1

1

VN 2

6

CH4

5 VP

CH1

1

CH2

2

VN 3

CH3

4

CH4

5

10

NC

9

NC

8

7

6

VP

NC

NC

CH2 3 4 CH3

SOT23-6

(Top View)

MSOP-10

(Top View)

Absolute Maximum Ratings

Exceeding the Absolute Maximum ratings may damage the device.

Parameter

Storage Temperature (T

S

)

ESD Rating per IEC61000-4-2, contact

(1)

ESD Rating per IEC61000-4-2, air

(1)

ESD Rating per Human Body Model

(2)

Notes:

1. IEC 61000-4-2 discharge with C

Discharge

= 150pF, R

Discharge

= 330

.

2. Human Body Discharge per MIL-STD-883, Method 3015 C

Discharge

= 100pF, R

Discharge

= 1.5k

.

Rating

-65°C to +150°C

±8kV

±15kV

±15kV

Maximum Operating Ratings

Parameter

Junction Temperature (T

J

)

Rating

-40°C to +125°C

Rev. 2.5 December 2009

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Page 2 of 14

AOZ8005

Electrical Characteristics

T

A

= 25°C unless otherwise specified. Specifications in

BOLD

indicate a temperature range of -40°C to +85°C.

Min.

Typ.

Symbol

V

RWM

V

BR

I

R

V

F

V

CL

C j

Parameter

Reverse Working Voltage

Reverse Breakdown Voltage

Reverse Leakage Current

Diode Forward Voltage

Channel Clamp Voltage

Positive Transients

Negative Transient

Channel Clamp Voltage

Positive Transients

Negative Transient

Channel Clamp Voltage

Positive Transients

Negative Transient

Channel Input Capacitance

Conditions

Between VP and VN

(3)

I

T

= 1mA, between VP and VN

(4)

V

RWM

= 5V, between VP and VN

I

F

= 15mA

I

PP

= 1A, tp = 100ns, any I/O pin to Ground

(5)

I

PP

= 5A, tp = 100ns, any I/O pin to Ground

(5)

I

PP

= 12A, tp = 100ns, any I/O pin to Ground

(5)

6.6

0.70

0.85

Δ

C j

Channel Input Capacitance

Matching

V

R

= 0V, f = 1MHz, any I/O pin to Ground

(6)

V

R

= 0V, f = 1MHz, between I/O pins

(6)

V

P

= 3.3V, V

R

= 1.65V, f = 1MHz, any I/O pin to

Ground

V

P

= 5.0V, V

R

= 2.5V, f = 1MHz, any I/O pins to ground

V

R

= 0V, f = 1MHz, between I/O pins

1.0

0.47

0.75

0.75

Notes:

3. The working peak reverse voltage, V

RWM

, should be equal to or greater than the DC or continuous peak operating voltage level.

4. V

BR

is measured at the pulse test current I

T

.

5. Measurements performed using a 100ns Transmission Line Pulse (TLP) system.

6. Measure performed with no external capacitor on V

P

.

Max.

5.5

1

1

10.50

-2.00

12.50

-3.50

16.00

-5.50

1.05

0.50

0.85

0.85

0.03

Units

V

V

µA

V

V

V

V

V pF pF

V

V pF pF pF

Rev. 2.5 December 2009

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Page 3 of 14

AOZ8005

3

0

-3

-6

-9

-12

1

Typical Operating Characteristics

17

16

15

14

13

12

11

10

0

Clamping Voltage vs. Peak Pulse Current

(tperiod = 100ns, tr = 1ns)

2 4 6 8

Peak Pulse Current (A)

10 12

Capacitance vs. Reverse Voltage

1.5

1

VP = Floating

VP = 3.3V

0.5

0

0 0.5

1 1.5

2 2.5

3 3.5

Reverse Volts, Vr (V)

4 4.5

5

Insertion Loss vs. Frequency

VP = Floating

-3dB

2,340MHz

3

2

5

4

7

6

1

0

0

Forward Voltage vs. Forward Current

(tperiod = 100ns, tr = 1ns)

2 4 6 8

Forward Current (A)

10 12

-12

-15

-18

-21

-3

-6

3

0

-9

21

18

15

12

9

6

1

I/O – Gnd Insertion Loss vs. Frequency

VP = Floating

VP = 3.3V

10 100

Frequency (MHz)

1000

ESD Clamping

8kV Contact per IEC61000-4-2

10 100

Frequency (MHz)

1,000 10,000

Note: Data was taken with a 10X attenuator

Rev. 2.5 December 2009

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Page 4 of 14

AOZ8005

Application Information

The AOZ8005 TVS is design to protect four high speed data lines from ESD and transient over-voltage by clamping them to a fixed voltage. When the voltages on the protected lines exceed the limit, the internal steering diode are forward bias will conduct the harmful transient away from the sensitive circuitry. As system frequency increase, printed circuit board layout becomes more complex. A successful high speed board must integrate the device and traces while avoiding signal transmission problems associated with HDMI data speed.

High Speed HDMI PCB Layout Guidelines

Printed circuit board layout is the key to achieving the highest level of surge immunity on power and data lines.

The location of the protection devices on the PCB is the simplest and most important design rule to follow. The

AOZ8005 devices should be located as close as possible to the noise source. The placement of the AOZ8005 devices should be used on all data and power lines that enter or exit the PCB at the I/O connector. In most systems, surge pulses occur on data and power lines that enter the PCB through the I/O connector. Placing the

AOZ8005 devices as close as possible to the noise source ensures that a surge voltage will be clamped before the pulse can be coupled into adjacent PCB traces. In addition, the PCB should use the shortest possible traces. A short trace length equates to low impedance, which ensures that the surge energy will be dissipated by the AOZ8005 device. Long signal traces will act as antennas to receive energy from fields that are produced by the ESD pulse. By keeping line lengths as short as possible, the efficiency of the line to act as an antenna for ESD related fields is reduced. Minimize interconnecting line lengths by placing devices with the most interconnect as close together as possible. The protection circuits should shunt the surge voltage to either the reference or chassis ground. Shunting the surge voltage directly to the IC’s signal ground can cause ground bounce. The clamping performance of TVS diodes on a single ground PCB can be improved by minimizing the impedance with relatively short and wide ground traces.

The PCB layout and IC package parasitic inductances can cause significant overshoot to the TVS’s clamping voltage. The inductance of the PCB can be reduced by using short trace lengths and multiple layers with separate ground and power planes. One effective method to minimize loop problems is to incorporate a ground plane in the PCB design.

The AOZ8005 ultra-low capacitance TVS is designed to protect four high speed data transmission lines from transient over-voltages by clamping them to a fixed reference. The low inductance and construction minimizes voltage overshoot during high current surges. When the voltage on the protected line exceeds the reference voltage the internal steering diodes are forward biased, conducting the transient current away from the sensitive circuitry. The AOZ8005 is designed for the ease of PCB layout by allowing the traces to run underneath the device. The pinout of the AOZ8005 is design to simply drop onto the IO lines of a High Definition Multimedia

Interface (HDMI) design without having to divert the signal lines that may add more parasitic inductance.

Pins 1, 2, 4 and 5 are connected to the internal TVS devices and pins 6, 7, 9 and 10 are no connects. The no connects was done so the package can be securely soldered onto the PCB surface. See Figure 2.

CH 1

CH 2

VN

CH 3

CH 4

CH 1

CH 2

VP

CH 3

CH 4

Figure 2. Flow through Layout for two Line Pair

It is crucial that the layout is successful for a HDMI design PCB board. Some of the problems associated with high speed design are matching impedance of the traces and to minimize the crosstalk between parallel traces. This application note is to provide you as much information to successfully design a high speed PCB using Alpha & Omega devices.

The HDMI video signals are transmitted on a very high speed pair of traces and any amount of capacitance, inductance or even bends in a trace can cause the impedance of a differential pair to drop as much as 40

.

This is not desirable because HDMI ports must maintain a 100

±15% on each of the four pairs of its differential lines per HDMI Compliance Test Specifications. The

HDMI CTS specifies that the impedance on the differential pair of a receiver must be measured using a Time

Domain Reflectometry method with a pulse rise time of

≤ 200pS. The TDR measurements of the PCB traces allows to locate and model discontinuities cause by the geometrical features of a bend and by the frequencydependant losses of the trace itself. These fast edge rates can contribute to noise and crosstalk, depending on the traces and PCB dielectric construction material.

Rev. 2.5 December 2009

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Page 5 of 14

AOZ8005

Material selection is another aspect that determines good characteristic impedance in the lines. Different material will give you different results. The dielectric material will have the dielectric constant (

ε r

). Where Q

1

, Q

2

= charges, r = distance between charges (m), F = force(N),

ε

= permittivity of dielectric (F/m).

F

=

Q Q

---------------

4

πε

r

2

(1)

Each PCB substrate has a different relative dielectric constant. The dielectric constant is the permittivity of a relative that of empty space. Where

ε constant,

ε

= permittivity, and

ε o space. r

= dielectric

= permittivity of empty

ε

r

=

-----

o

(2)

The dielectric constant affects the impedance of a transmission line and can propagate faster in materials that have a lower

ε r

. The frequency in your design will depend on the material being used. With equation 1 you can determine the type of material to use. If higher frequency is required other board material maybe considered. GETEK is another material that can be used in high speed boards. They have a typical

ε r

between 3.6 to 4.0.

The most common type of dielectric material used for

PCB is FR-4. Typical dielectric constant for FR-4 is between 4.0 to 4.5. Most PCB manufacture will be able to give you the exact value of the FR-4 dielectric constant.

Once you determined the dielectric constant of the board material you can start to calculate the impedance of each trace. Below are the formulas for a microstrip layout. This impedance is dependant on the width of the microstrip

(W) the thickness (t) of the trace and the height (h) of the

FR4 material, and (D) trace edge to edge spacing.

By solving for Zo you can calculate the differential impedance with the equation below.

Zdiff

=

2

×

Zo

1 0.48

e

0.96

h

Zdiff

=

100.77

(4)

Adjust the trace width, height, distance between the traces and FR4 thickness to obtain the desired 100

Ω differential impedance. The general rule of thumb is to route the traces as short as possible, use differential routing strategies whenever feasible and match the length and bends to each of the differential traces.

The graphs below show the differential impedance with varying trace width without the AOZ8005 MSOP-10 package part on it. Each of the graphs and board layout represent changing trace width from 50 increment of 10

.

to 80

in

Figure 4. 100

Differential Impedance

Max 103

, Min 97

W D W t

Trace

ε

r

Dielectric Material

H

Ground

Figure 3.

Typical value of W = 12.6 mil, h = 10mils, D = 10mils, t = 1.4mils and

ε r

= 4.0 with the equation below for a microstrip impedance yields:

Zo

=

ε

r

+

1.41

=

ln

×

h

0.8

W t

(3)

Zo

=

61.73

Ω

Figure 5. 120

Differential Impedance

Max 110

, Min 102

Rev. 2.5 December 2009

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Page 6 of 14

AOZ8005

X

Zo = 61

Ω

Z

1

C

(TVS)

Zo = 61

Ω

Figure 6. 140

Differential Impedance

Max 102

, Min 92

Figure 7.

K

=

Z

------

Z

0

X

=

Z

0

C

τ

TVS

----------------

K

1

(5)

(6)

Figure 7. 160

Differential Impedance

Max 123

, Min 109

140

120

100

80

60

40

20

0

50

Min.

Max.

55 60 65 70 75

Common Mode Impedance (

Ω

)

Figure 8. Differential Impedance

80

By adding a TVS onto the traces it can have a large effect on the impedance of the line. This addition of a capacitance added to a 100

differential transmission line without any compensation may decrease the impedance as much as 20

or more. Below is a formula to calculate the length for the compensation of C

(TVS)

.

Z

0

is the normal 61

differential impedance on the trace.

Z

1

is the needed impedance to compensate for the added C

(TVS)

K is defined as the unloaded impedance of the adjusted trace.

X is the length of the trace needed for the compensation.

τ

is the propagation delay time required for a signal to travel from one point to another. This value should be less than 200pS.

From the above method the designer should layout the boards with a 50

common mode trace. The result should give you approximately 100

differential impedance. Z

1

is the impedance that you choose in order to compensate the TVS capacitance. Based on Z

1

value, we can get the length of the segment from the above equations. With the value of Z

1

C

(TVS)

580 mils.

= 80

, Zo = 61

,

= 0.94 and

τ

= 180. The X(mils) equates to

Page 8 has a series of graph that represent changing width and length of the trace from 50 increment of 10

to 80

in

with a MSOP-10 package solder onto the board. As you can observe from the graphs, a small incremental capacitance that is added to the differential lines can significantly decrease the differential impedance. Thus violated the HDMI specification of

100

±15%.

Rev. 2.5 December 2009

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Page 7 of 14

AOZ8005

Figure 10. 100

Ω

Differential Impedance with

AOZ8007 MSOP-10 Package on it

Max. 97

Ω

, Min. 80

Ω

Figure 12. 140

Ω

Differential Impedance with

AOZ8007 MSOP-10 Package on it

Max. 102

Ω

, Min. 92

Ω

Figure 11. 120

Ω

Differential Impedance with

AOZ8007 MSOP-10 Package on it

Max. 99

Ω

, Min. 86

Ω

Figure 13. 160

Ω

Differential Impedance with

AOZ8007 MSOP-10 Package on it

Max. 101

Ω

, Min. 95

Ω

From Figure 13 we are able to get the best result from using all of the equation above. With the value of

Z

1

= 80

, Z

0

= 61

, C

(TVS)

= 0.94,

τ

= 180 and from

Table 1. The X(mils) equates to 580mils to give the best compensated differential impedance on the traces for the added capacitance from the AOZ8005.

Table 1. AOZ8005 MSOP-10 HDMI Evaluation Board

Specification

Number of layers

Copper Trace Thickness

Dielectric Constant

ε r

Overall Board Thickness

Dielectric thickness between top and ground layer

4

1.4 mils

4

62 mils

10 mils

Rev. 2.5 December 2009

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Page 8 of 14

100

Ω

Differential

132

Ω

Differential

580 mils

AOZ8005

Conclusion

This application section discusses ESD protection while maintaining the differential impedance of a HMDI sink device. Since the TVS add capacitance we must design the board to meet the HDMI requirements. This application note is a guideline to calculate and layout the PCB.

Different board manufacture and process will fluctuate and will cause the final board to vary slightly. You must carefully plan out a successful high speed HDMI PCB.

Factor such as PCB stack up, ground bounce, crosstalk and signal reflection can interfere with a signal. The layout, trace routing, board materials and impedance calculation discussed in this application note can help you design a more effective PCB using the AOZ8005 devices.

Figure 14. Recommend Layout for MSOP-10 Package

100

Ω

Differential

132

Ω

Differential

580 mils

Total Distance

Table 2. AOZ8005 SOT-23-6 Evaluation Board

Specifications

Number of layers

Copper Trace Thickness

Dielectric Constant

ε r

Overall Board Thickness

Dielectric thickness between top and ground layer

4

1.4 mils

4

62 mils

10 mils

Figure 15. Recommended Layout for SOT-23 Package

Rev. 2.5 December 2009

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Page 9 of 14

AOZ8005

Package Dimensions, SOT23-6L

D e1

Gauge Plane c

Seating Plane

0.25mm

L

E E1

θ

1 e b

A

A1

A2

.010mm

RECOMMENDED LAND PATTERN

0.80

0.95

2.40

0.63

UNIT: mm

Symbols

A

A1

A2 b c

D

E

E1 e e1

L

θ

1

Dimensions in millimeters

Min.

0.90

0.00

0.80

Nom.

1.10

0.30

0.08

2.70

2.50

1.50

0.40

0.13

2.90

2.80

0.30

0

°

1.60

0.95 BSC

1.90 BSC

Max.

1.25

0.15

1.20

0.60

8

°

0.50

0.20

3.10

3.10

1.70

Symbols

A

A1

A2 b c

D

E

E1 e e1

L

θ

1

Dimensions in inches

Min.

0.035

0.00

0.031

Nom.

0.043

Max.

0.049

0.006

0.047

0.012

0.003

0.106

0.098

0.016

0.005

0.114

0.110

0.020

0.008

0.122

0.122

0.059

0.063

0.037 BSC

0.067

0.012

0

°

0.075 BSC

0.024

8

°

Notes:

1. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 5 mils each.

2. Dimension “L” is measured in gauge plane.

3. Tolerance

±

0.100mm (4 mil) unless otherwise specified.

4. Followed from JEDEC MO-178C & MO-193C.

6. Controlling dimension is millimeter. Converted inch dimensions are not necessarily exact.

Rev. 2.5 December 2009

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Page 10 of 14

AOZ8005

Tape and Reel Dimensions, SOT23-5&6L

Tape

P1

D0

P2

D1

K0

E2

E1

E

B0

P0

A0

Feeding Direction

Unit: mm

Package

SOT23-5/6L

LP

A0

3.15

±0.10

B0

3.20

±0.10

K0

1.40

±0.10

D0

1.50

±0.05

D1

1.00

+0.10 / -0

E

8.00

±0.30

E1

1.75

±0.10

E2

3.50

±0.05

P0

4.00

±0.10

P1

4.00

±0.10

P2

2.00

±0.05

T

0.23

±0.03

Reel

W1

S

K

R

M

N

J

H

Unit: mm

Tape Size

8mm

Reel Size

ø177.8

M

ø177.8

Max.

N

55.0

Min.

W1 H

8.4

+1.50 / -0.0

13.0

+0.5 / -0.2

S

1.5

Min

K

10.1

Min.

R

12.7

J

4.0

±0.1

Leader/Trailer and Orientation

Trailer Tape

300mm min.

Rev. 2.5 December 2009

Components Tape

Orientation in Pocket

www.aosmd.com

Leader Tape

500mm min.

Page 11 of 14

AOZ8005

Package Dimensions, MSOP-10L

Gauge Plane Seating Plane

0.25

C

L

E1

E

D

12

°

(4x) e

A1

A2

A b

RECOMMENDED LAND PATTERN

0.76

0.50

0.30

4.37

UNIT: mm

Dimensions in millimeters

Symbols

A

A1

A2 b

C

D

E

E1 e

L y

θ

Min.

0.81

0.05

0.76

0.15

0.13

2.90

4.70

2.90

0.40

0

°

Nom.

1.02

0.86

0.20

0.15

3.00

4.90

3.00

0.50

0.53

Max.

1.12

0.15

0.97

0.30

0.23

3.10

5.10

3.10

0.66

0.10

6

°

Dimensions in inches

Symbols

A

A1

A2 b

C

D

E

E1 e

L y

θ

Min.

0.032

0.002

0.030

0.006

0.005

0.114

0.185

0.114

0.016

0

°

Nom.

0.040

0.034

0.008

0.006

0.118

0.193

0.118

0.0197

0.021

Notes:

1. All dimensions are in millimeters.

2. Tolerance 0.10mm unless otherwise specified.

3. Package body sizes exclude mold flash and gate burrs. Mold flash at the non-lead sides should be less than 5 mils each.

4. Dimension L is measured in gauge plane.

5. Controlling dimension is millimeter, converted inch dimensions are not necessarily exact.

Max.

0.044

0.006

0.038

0.012

0.009

0.122

0.201

0.122

0.026

0.004

6

°

Rev. 2.5 December 2009

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Page 12 of 14

Tape and Reel Dimensions, MSOP-10

Carrier Tape

T

D1

P1

P2

E2

E1

E

B0

K0

Section Y-Y'

P0

D0

A0

Feeding Direction

UNIT: mm

Package

MSOP-10

(12mm)

A0

5.3

±

0.1

B0

3.4

±

0.1

K0

1.4

±

0.1

D0

1.6

±

0.1

D1

1.5

+0.1/-0

E

12.0

±

0.3

E1

1.75

±

0.10

E2

5.50

±

0.05

P0

8.00

±

0.10

P1

4.00

±

0.05

P2

2.00

±

0.05

T

0.30

±

0.05

Reel

W1

S

G

M

N

K

V

R

H

UNIT: mm

Tape Size

12mm

Reel Size

ø330

M

ø330

±

0.5

N

ø97.0

±

1.0

W

13.00

W1

17.40

W

H

ø13.0

+0.5/-0.2

K

10.60

S

2.0

±

0.5

G

R

V

Leader/Trailer and Orientation

AOZ8005

Trailer Tape

300mm min. or

75 empty sockets

Rev. 2.5 December 2009

Components Tape

Orientation in Pocket

www.aosmd.com

Leader Tape

500mm min. or

125 empty sockets

Page 13 of 14

AOZ8005

Park Marking

AOZ8005CIL

(SOT-23)

ACOW Assembly

Lot Code

Part Number Code

Underscore Denotes Green Product

Week & Year Code

Option & Assembly Location Code

AOZ8005FIL

(MSOP-10)

Product Name Extension Character

Option Code

8 0 0 5

I O 7 6

P 1 1

Part Number Code, Underscore Denotes Green Product

Week Code

Year Code

Assembly Lot Code

Assembly Location Code

This datasheet contains preliminary data; supplementary data may be published at a later date.

Alpha & Omega Semiconductor reserves the right to make changes at any time without notice.

LIFE SUPPORT POLICY

ALPHA & OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL

COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.

As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

Rev. 2.5 December 2009

www.aosmd.com

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