datasheet for PIC16LF1902 by Microchip Technology Inc.

datasheet for PIC16LF1902 by Microchip Technology Inc.

PIC16LF1902/3

Data Sheet

28-Pin Flash-Based, 8-Bit

CMOS Microcontrollers with

LCD Driver and nanoWatt XLP Technology

2011 Microchip Technology Inc.

Preliminary

DS41455B

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE

.

Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

K

EE

L

OQ

, K

EE

L

OQ

logo, MPLAB, PIC, PICmicro, PICSTART,

PIC

32

logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,

TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.

© 2011, Microchip Technology Incorporated, Printed in the

U.S.A., All Rights Reserved.

Printed on recycled paper.

ISBN: 978-1-61341-030-1

Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC ® MCUs and dsPIC ® DSCs, K

EE

L

OQ

® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

DS41455B-page 2

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

28-Pin Flash-Based, 8-Bit CMOS MCUs with LCD Driver and nanoWatt XLP Technology

High-Performance RISC CPU:

• C Compiler Optimized Architecture

• Only 49 Instructions

• Up to 7 Kbytes Self-Write/Read Flash Program

Memory Addressing

• Up to 256 Bytes Data Memory Addressing

• Operating Speed:

- DC – 20 MHz clock input @ 3.6V

- DC – 16 MHz clock input @ 1.8V

- DC – 200 ns instruction cycle

• Interrupt Capability with Automatic Context

Saving

• 16-Level Deep Hardware Stack with Optional

Overflow/Underflow Reset

• Direct, Indirect and Relative Addressing modes:

- Two full 16-bit File Select Registers (FSRs)

- FSRs can read program and data memory

Flexible Oscillator Structure:

• 16 MHz Internal Oscillator:

- Accuracy to ± 3%, typical

- Software selectable frequency range from

16 MHz to 31.25 kHz

• 31 kHz Low-Power Internal Oscillator

• Three External Clock modes up to 20 MHz

• Two-Speed Oscillator Start-up

• Low-Power RTC Implementation via LPT1OSC

Special Microcontroller Features:

• Operating Voltage Range:

- 1.8V-3.6V

• Self-Programmable under Software Control

• Power-on Reset (POR)

• Power-up Timer (PWRT)

• Low-Power Brown-Out Reset (LPBOR)

• Extended Watchdog Timer (WDT)

• In-Circuit Serial Programming™ (ICSP™) via

Two Pins

• In-Circuit Debug (ICD) via Two Pins

• Enhanced Low-Voltage Programming (LVP)

• Programmable Code Protection

• Power-Saving Sleep mode

Extreme Low-Power Management

PIC16LF1902/3 with nanoWatt XLP:

• Sleep mode: 30 nA @ 1.8V, typical

• Watchdog Timer: 300 nA @ 1.8V, typical

• Timer1 Oscillator: 500 nA @ 1.8V, typical

Analog Features:

• Analog-to-Digital Converter (ADC):

- 10-bit resolution, up to 11 channels

- Conversion available during Sleep

- Dedicated ADC RC oscillator

- Fixed Voltage Reference (FVR) as channel

• Integrated Temperature Indicator

• Voltage Reference module:

- Fixed Voltage Reference (FVR) with 1.024V and 2.048V output levels

Peripheral Highlights:

• Up to 25 I/O Pins and 1 Input-only Pin:

- High current 25 mA sink/source

- Individually programmable weak pull-ups

- Individually programmable interrupt-onchange (IOC) pins

• Integrated LCD Controller:

- 19 segment pins and 72 total segments

- Variable clock input

- Contrast control

- Internal voltage reference selections

• Timer0: 8-Bit Timer/Counter with 8-Bit

Programmable Prescaler

• Enhanced Timer1:

- 16-bit timer/counter with prescaler

- External Gate Input mode

- Dedicated low-power 32 kHz oscillator driver

Preliminary

2011 Microchip Technology Inc.

DS41455B-page 3

PIC16LF1902/3

PIC16LF1902/3 Family Types

LCD

Device

PIC16LF1902 2048 128 25 11 1/1 4 19

PIC16LF1903

Note 1:

4096 256 25 11 1/1 4

COM3 and SEG15 share a pin, so the total segments are limited to 72 for 28-pin devices.

19

FIGURE 1: 28-PIN PDIP, SOIC, SSOP PACKAGE DIAGRAM FOR PIC16LF1902/3

28-Pin PDIP, SOIC, SSOP

72

(1)

72

(1)

V

PP

/MCLR/RE3

SEG12/AN0/RA0

SEG7/AN1/RA1

COM2/AN2/RA2

SEG15/COM3/V

REF

+/AN3/RA3

SEG4/T0CKI/RA4

SEG5/AN4/RA5

V

SS

SEG2/CLKIN/RA7

SEG1/CLKOUT/RA6

T1CKI/T1OSO/RC0

T1OSI/RC1

SEG3/RC2

SEG6/RC3

3

4

1

2

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RB7

(1)

/SEG13/ICSPDAT

RB6

(1)

/SEG14/ICSPCLK

RB5

(1)

/AN13/COM1

RB4

(1)

/AN11/COM0

RB3

(1)

/AN9/SEG26/VLCD3

RB2

(1)

/AN8/SEG25/VLCD2

RB1

(1)

/AN10/SEG24/VLCD1

RB0

(1)

/AN12/INT/SEG0

V

DD

V

SS

RC7/SEG8

RC6/SEG9

RC5/SEG10

RC4/T1G/SEG11

Note 1:

These pins have interrupt-on-change functionality.

DS41455B-page 4

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

FIGURE 2:

28-Pin UQFN

28-PIN UQFN PACKAGE DIAGRAM FOR PIC16LF1902/3

COM2/AN2/RA2

SEG15/COM3/V

REF

+/AN3/RA3

SEG4/T0CKI/RA4

SEG5/AN4/RA5

V

SS

SEG2/CLKIN/RA7

SEG1/CLKOUT/RA6

3

4

1

2

5

6

7

PIC16LF1902/3

17

16

15

21

20

19

18

RB3

(1)

/AN9/SEG26/VLCD3

RB2

(1)

/AN8/SEG25/VLCD2

RB1

(1)

/AN10/SEG24/VLCD1

RB0

(1)

/AN12/INT/SEG0

V

DD

V

SS

RC7/SEG8

Note 1:

These pins have interrupt-on-change functionality.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 5

PIC16LF1902/3

TABLE 1: 28-PIN ALLOCATION TABLE (PIC16LF1902/3)

RB6

RB7

RC0

RC1

RC2

RC3

RB0

RB1

RB2

RB3

RB4

RB5

RC4

RC5

RC6

RC7

RA0

RA1

RA2

RA3

RA4

RA5

RA6

RA7

RE3

V

DD

Vss

Note 1:

27

28

11

12

13

14

15

16

17

18

21

22

23

24

25

26

5

6

7

10

9

2

3

4

1

20

8,19

24

25

8

9

10

11

12

13

14

15

18

19

20

21

22

23

4

7

6

2

3

27

28

1

26

17

5,16

AN0

AN1

AN2

AN3/V

REF

+

AN4

AN12

AN10

AN8

AN9

AN11

AN13

T0CKI

T1OSO/T1CKI

T1OSI

T1G

SEG12

SEG7

COM2

SEG15/COM3

SEG4

SEG5

SEG1

SEG2

SEG0

VLCD1/SEG24

VLCD2/SEG25

VLCD3/SEG26

COM0

COM1

SEG14

SEG13

SEG3

SEG6

SEG11

SEG10

SEG9

SEG8

Y

Y

Y

Y

Y

Y

Y

Y

Y

(1)

Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control.

INT/IOC

IOC

IOC

IOC

IOC

IOC

IOC

IOC

CLKOUT

CLKIN

ICSPCLK

ICSPDAT

MCLR/V

PP

V

DD

V

SS

DS41455B-page 6

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

Table of Contents

5.0

6.0

7.0

8.0

1.0

2.0

3.0

4.0

Device Overview .......................................................................................................................................................................... 9

Enhanced Mid-Range CPU ........................................................................................................................................................ 13

Memory Organization ................................................................................................................................................................. 15

Device Configuration .................................................................................................................................................................. 37

Resets ........................................................................................................................................................................................ 43

Oscillator Module........................................................................................................................................................................ 51

Interrupts .................................................................................................................................................................................... 61

Power-Down Mode (Sleep) ........................................................................................................................................................ 73

9.0

Watchdog Timer (WDT) ............................................................................................................................................................. 75

10.0 Flash Program Memory Control ................................................................................................................................................. 79

11.0 I/O Ports ..................................................................................................................................................................................... 95

12.0 Interrupt-on-Change ................................................................................................................................................................. 107

13.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 111

14.0 Temperature Indicator .............................................................................................................................................................. 113

15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 115

16.0 Timer0 Module ......................................................................................................................................................................... 129

17.0 Timer1 Module ......................................................................................................................................................................... 133

18.0 Liquid Crystal Display (LCD) Driver Module............................................................................................................................. 145

19.0 In-Circuit Serial Programming

(ICSP

) ................................................................................................................................ 179

20.0 Instruction Set Summary .......................................................................................................................................................... 183

21.0 Electrical Specifications............................................................................................................................................................ 197

22.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 215

23.0 Development Support............................................................................................................................................................... 217

24.0 Packaging Information.............................................................................................................................................................. 221

Appendix A: Revision History............................................................................................................................................................. 231

Index .................................................................................................................................................................................................. 233

The Microchip Web Site ..................................................................................................................................................................... 237

Customer Change Notification Service .............................................................................................................................................. 237

Customer Support .............................................................................................................................................................................. 237

Reader Response .............................................................................................................................................................................. 238

Product Identification System ............................................................................................................................................................ 239

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 7

PIC16LF1902/3

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

E-mail at

[email protected]

or fax the

Reader Response Form

in the back of this data sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site;

http://www.microchip.com

• Your local Microchip sales office (see last page)

When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.

Customer Notification System

Register on our web site at

www.microchip.com

to receive the most current information on all of our products.

DS41455B-page 8

Preliminary

2011 Microchip Technology Inc.

1.0

DEVICE OVERVIEW

The PIC16LF1902/3 are described within this data sheet. They are available in 28-pin packages.

Figure 1-1 shows a block diagram of the

PIC16LF1902/3 devices. Table 1-2

shows the pinout descriptions.

Reference device.

Table 1-1

for peripherals available per

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

ADC

Fixed Voltage Reference (FVR)

LCD

Temperature Indicator

Timers

Timer0

Timer1

PIC16LF1902/3

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 9

PIC16LF1902/3

FIGURE 1-1: PIC16LF1902/3 BLOCK DIAGRAM

Program

Flash Memory

CLKOUT

Timing

Generation

CLKIN

INTRC

Oscillator

MCLR

CPU

Figure 2-1

LCD Timer0

Timer1

Temp.

Indicator

ADC

10-Bit

FVR

Note 1:

See applicable chapters for more information on peripherals.

RAM

PORTA

PORTB

PORTC

PORTE

DS41455B-page 10

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

TABLE 1-2:

Name

PIC16LF1902/3 PINOUT DESCRIPTION

Function

Input

Type

Output

Type

Description

RA0/AN0/SEG12 RA0

AN0

SEG12

RA1/AN1/SEG7

RA2/AN2/COM2

RA3/AN3/V

REF

+/COM3/SEG15

RA4/T0CKI/SEG4

RA1

AN1

SEG7

RA2

AN2

COM2

RA3

AN3

V

REF

+

COM3

SEG15

RA4

T0CKI

SEG4

TTL

AN

TTL

AN

TTL

AN

TTL

AN

AN

TTL

ST

AN

A/D Channel 0 input.

LCD Analog output.

CMOS General purpose I/O.

— A/D Channel 1 input.

AN LCD Analog output.

CMOS General purpose I/O.

AN

A/D Channel 2 input.

LCD Analog output.

CMOS General purpose I/O.

— A/D Channel 3 input.

AN

AN

A/D Voltage Reference input.

LCD Analog output.

LCD Analog output.

CMOS General purpose I/O.

AN

Timer0 clock input.

LCD Analog output.

RA5/AN4/SEG5

RA6/CLKOUT/SEG1

RA5

AN4

SEG5

RA6

CLKOUT

SEG1

TTL

AN

TTL

CMOS General purpose I/O.

AN

A/D Channel 4 input.

LCD Analog output.

CMOS General purpose I/O.

CMOS F

OSC

/4 output.

AN LCD Analog output.

RA7/CLKIN/SEG2

RB0/AN12/INT/SEG0

RB1

(1)

/AN10/SEG24/VLCD1

RA7

CLKIN

SEG2

RB0

AN12

INT

SEG0

RB1

TTL

CMOS

TTL

AN

ST

TTL

CMOS General purpose I/O.

— External clock input (EC mode).

AN LCD Analog output.

CMOS General purpose I/O.

A/D Channel 12 input.

External interrupt.

AN LCD Analog output.

CMOS General purpose I/O.

RB2

(1)

/AN8/SEG25/VLCD2

AN10

SEG24

VLCD1

RB2

AN8

SEG25

VLCD2

RB3

AN

AN

TTL

AN

AN

TTL

AN

A/D Channel 10 input.

LCD Analog output.

— LCD analog input.

CMOS General purpose I/O.

AN

A/D Channel 8 input.

LCD Analog output.

— LCD analog input.

CMOS General purpose I/O.

RB3

(1)

/AN9/SEG26/VLCD3

AN9

SEG26

AN

AN

A/D Channel 9 input.

LCD Analog output.

VLCD3 AN — LCD analog input.

Legend:

Note 1:

AN = Analog input or output

TTL = TTL compatible input

HV = High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I

OD

2

= Open Drain

C™ = Schmitt Trigger input with I

2

C

XTAL = Crystal levels

These pins have interrupt-on-change functionality.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 11

PIC16LF1902/3

TABLE 1-2: PIC16LF1902/3 PINOUT DESCRIPTION (CONTINUED)

Name Function

Input

Type

Output

Type

Description

RB4

RB5

RB6

RB7

(1)

(1)

(1)

(1)

/AN11/COM0

/AN13/COM1

/ICSPCLK/SEG14

/ICSPDAT/SEG13

RB4

AN11

COM0

RB5

AN13

COM1

RB6

ICSPCLK

SEG14

RB7

ICSPDAT

SEG13

TTL

ST

TTL

ST

TTL

AN

TTL

AN

CMOS General purpose I/O.

— A/D Channel 11 input.

AN LCD Analog output.

CMOS General purpose I/O.

AN

A/D Channel 13 input.

LCD Analog output.

CMOS General purpose I/O.

— Serial Programming Clock.

AN LCD Analog output.

CMOS General purpose I/O.

CMOS ICSP™ Data I/O.

AN LCD Analog output.

RC0/T1OSO/T1CKI

RC1/T1OSI

RC2/SEG3

RC3/SEG6

RC4/T1G/SEG11

RC0

T1OSO

T1CKI

RC1

T1OSI

RC2

SEG3

RC3

SEG6

RC4

T1G

SEG11

TTL

XTAL

ST

TTL

XTAL

TTL

TTL

TTL

XTAL

CMOS General purpose I/O.

XTAL Timer1 oscillator connection.

— Timer1 clock input.

CMOS General purpose I/O.

XTAL Timer1 oscillator connection.

CMOS General purpose I/O.

AN LCD Analog output.

CMOS General purpose I/O.

AN LCD Analog output.

CMOS General purpose I/O.

XTAL

AN

Timer1 oscillator connection.

LCD Analog output.

RC5/SEG10

RC6/SEG9

RC7/SEG8

RC5

SEG10

RC6

SEG9

RC7

SEG8

TTL

ST

ST

CMOS General purpose I/O.

AN LCD Analog output.

CMOS General purpose I/O.

AN LCD Analog output.

CMOS General purpose I/O.

AN LCD Analog output.

RE3/MCLR/V

PP

RE3

MCLR

V

PP

V

DD

TTL

ST

HV

Power

CMOS General purpose I/O.

— Master Clear with internal pull-up.

Programming voltage.

Positive supply.

V

DD

V

SS

V

SS

Power — Ground reference.

Legend:

Note 1:

AN = Analog input or output

TTL = TTL compatible input

HV = High Voltage

CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels I

OD

2

= Open Drain

C™ = Schmitt Trigger input with I

2

C

XTAL = Crystal levels

These pins have interrupt-on-change functionality.

DS41455B-page 12

Preliminary

2011 Microchip Technology Inc.

2.0

ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range

8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and

Underflow Reset capability. Direct, Indirect, and

Relative Addressing modes are available. Two File

Select Registers (FSRs) provide the ability to read program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

2.1

Automatic Interrupt Context

Saving

During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See

Section 7.5 “Automatic Context Saving”

,

for more information.

2.2

16-level Stack with Overflow and

Underflow

These devices have an external stack memory 15 bits wide and 16 words deep. A Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and if enabled will cause a soft-

ware Reset. See

Section 3.4 “Stack”

for more details.

2.3

File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one Data Pointer for all memory. When an

FSR points to program memory, there is one additional instruction cycle in instructions using INDF to allow the data to be fetched. General purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. There are also new instructions to support the FSRs. See

Section 3.5 “Indirect Addressing”

for more details.

2.4

Instruction Set

There are 49 instructions for the enhanced mid-range

CPU to support the features of the CPU. See

Section 20.0 “Instruction Set Summary”

for more

details.

2011 Microchip Technology Inc.

Preliminary

PIC16LF1902/3

DS41455B-page 13

PIC16LF1902/3

FIGURE 2-1: CORE BLOCK DIAGRAM

15

15

Program Counter

Flash

Program

Memory

16-Level Stack

(15-bit)

Program

Bus

14

Program Memory

Read (PMR)

Instruction Reg

Direct Addr 7

15

15

8

Data Bus

RAM

8

5

12

RAM Addr

Addr MUX

12

Indirect

Addr

12

FSR0 Reg

STATUS Reg

3

MUX

CLKIN

CLKOUT

Instruction

Decode and

Control

Timing

Generation

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

8

ALU

W Reg

V

DD

V

SS

DS41455B-page 14

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

3.0

MEMORY ORGANIZATION

These devices contain the following types of memory:

• Program Memory

- Configuration Words

- Device ID

- User ID

- Flash Program Memory

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

The following features are associated with access and control of program memory and data memory:

• PCL and PCLATH

• Stack

• Indirect Addressing

3.1

Program Memory Organization

The enhanced mid-range core has a 15-bit program counter capable of addressing 32K x 14 program memory space.

Table 3-1 shows the memory sizes

implemented for the PIC16LF1902/3 family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space.

The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures

3-1 , and 3-2 ).

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device

PIC16LF1902

PIC16LF1903

Program Memory Space (Words)

2,048

4,096

Last Program Memory Address

07FFh

0FFFh

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 15

PIC16LF1902/3

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR

PIC16LF1902

PC<14:0>

CALL, CALLW

RETURN, RETLW

Interrupt

, RETFIE

15

Stack Level 0

Stack Level 1

Stack Level 15

Reset Vector

0000h

On-chip

Program

Memory

Interrupt Vector

Page 0

Rollover to Page 0

Wraps to Page 0

0004h

0005h

07FFh

0800h

Wraps to Page 0

FIGURE 3-2: PROGRAM MEMORY MAP

AND STACK FOR

PIC16LF1903

PC<14:0>

CALL, CALLW

RETURN, RETLW

Interrupt

, RETFIE

15

Stack Level 0

Stack Level 1

Stack Level 15

Reset Vector

0000h

Interrupt Vector

Page 0

On-chip

Program

Memory

Page 1

Rollover to Page 0

0004h

0005h

07FFh

0800h

0FFFh

1000h

Wraps to Page 0

Rollover to Page 0

7FFFh

Rollover to Page 1

7FFFh

DS41455B-page 16

Preliminary

2011 Microchip Technology Inc.

3.1.1

READING PROGRAM MEMORY AS

DATA

There are two methods of accessing constants in program memory. The first method is to use tables of

RETLW

instructions. The second method is to set an

FSR to point to the program memory.

3.1.1.1

RETLW

Instruction

The

RETLW

instruction can be used to provide access to tables of constants. The recommended way to create

such a table is shown in Example 3-1 .

EXAMPLE 3-1:

constants

BRW

RETLW

INSTRUCTION

RETLW DATA0

RETLW DATA1

RETLW DATA2

RETLW DATA3

;Add Index in W to

;program counter to

;select data

;Index0 data

;Index1 data my_function

;… LOTS OF CODE…

MOVLW DATA_INDEX call constants

;… THE CONSTANT IS IN W

The

BRW

instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the

BRW

instruction is not available so the older table read method must be used.

3.1.1.2

Indirect Read with FSR

The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The

MOVIW

instruction will place the lower 8 bits of the addressed word in the W register.

Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete.

Example 3-2

demonstrates accessing the program memory via an FSR.

The HIGH directive will set bit<7> if a label points to a location in program memory.

PIC16LF1902/3

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

constants

RETLW DATA0

RETLW DATA1

RETLW DATA2

;Index0 data

;Index1 data

RETLW DATA3 my_function

;… LOTS OF CODE…

MOVLW LOW constants

MOVWF

MOVLW

FSR1L

HIGH constants

MOVWF FSR1H

MOVIW 0[INDF1]

;THE PROGRAM MEMORY IS IN W

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 17

PIC16LF1902/3

3.2

Data Memory Organization

The data memory is partitioned in 32 memory banks with 128 bytes in a bank. Each bank consists of

(

Figure 3-3

):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number into the Bank Select Register (BSR). Unimplemented memory will read as ‘

0

’. All data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two File Select

Registers (FSR). See

Section 3.5 “Indirect

Addressing”

for more information.

Data Memory uses a 12-bit address. The upper 7-bit of the address define the Bank address and the lower

5-bits select the registers/RAM in that bank.

3.2.1

CORE REGISTERS

The core registers contain the registers that directly affect the basic operation. The core registers occupy the first 12 addresses of every data memory bank

(addresses x00h/x08h through x0Bh/x8Bh). These

registers are listed below in

Table 3-2

. For for detailed

information, see

Table 3-4

.

TABLE 3-2: CORE REGISTERS

Addresses

x00h or x80h x01h or x81h x02h or x82h x03h or x83h x04h or x84h x05h or x85h x06h or x86h x07h or x87h x08h or x88h x09h or x89h x0Ah or x8Ah x0Bh or x8Bh

BANKx

INDF0

INDF1

PCL

STATUS

FSR0L

FSR0H

FSR1L

FSR1H

BSR

WREG

PCLATH

INTCON

DS41455B-page 18

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

3.2.1.1

STATUS Register

The STATUS register, shown in

Register 3-1

, contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than intended.

REGISTER 3-1: STATUS: STATUS REGISTER

bit 7

U-0

U-0

U-0

R-1/q

TO

For example,

CLRF STATUS

will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘

000u u1uu

’ (where u

= unchanged).

It is recommended, therefore, that only

BCF, BSF,

SWAPF

and

MOVWF

instructions are used to alter the

STATUS register, because these instructions do not affect any Status bits. For other instructions not affecting any Status bits (Refer to

Section 20.0

“Instruction Set Summary”

).

Note:

The C and DC bits operate as Borrow and

Digit Borrow out bits, respectively, in subtraction.

R-1/q

PD

R/W-0/u

Z

R/W-0/u

DC

(1)

R/W-0/u

C

(1)

bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition bit 7-5 bit 4 bit 3 bit 2 bit 1 bit 0

Unimplemented:

Read as ‘

0

TO:

Time-out bit

1

= After power-up,

CLRWDT

instruction or

SLEEP

instruction

0

= A WDT time-out occurred

PD:

Power-down bit

1

= After power-up or by the

CLRWDT

instruction

0

= By execution of the

SLEEP

instruction

Z:

Zero bit

1

= The result of an arithmetic or logic operation is zero

0

= The result of an arithmetic or logic operation is not zero

DC:

Digit Carry/Digit Borrow bit (

ADDWF

,

ADDLW,SUBLW,SUBWF

instructions)

(1)

1

= A carry-out from the 4th low-order bit of the result occurred

0

= No carry-out from the 4th low-order bit of the result

C:

Carry/Borrow bit

(1)

(

ADDWF

,

ADDLW, SUBLW, SUBWF instructions)

(1)

1

= A carry-out from the Most Significant bit of the result occurred

0

= No carry-out from the Most Significant bit of the result occurred

Note 1:

For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (

RRF

,

RLF

) instructions, this bit is loaded with either the high-order or low-order bit of the source register.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 19

PIC16LF1902/3

3.2.2

SPECIAL FUNCTION REGISTER

The Special Function Registers (SFRs) are registers used by the application to control the desired operation of peripheral functions in the device. The Special

Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh). The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet.

3.2.3

GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory bank. The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0Ch/x8Ch through x1Fh/x9Fh).

3.2.3.1

Linear Access to GPR

The general purpose RAM can be accessed in a non-banked method via the FSRs. This can simplify

access to large memory structures. See

Section 3.5.2

“Linear Data Memory”

for more information.

3.2.4

COMMON RAM

There are 16 bytes of common RAM accessible from all banks.

FIGURE 3-3: BANKED MEMORY

PARTITIONING

7-bit Bank Offset

Memory Region

00h

Core Registers

(12 bytes)

0Bh

0Ch

Special Function Registers

(20 bytes maximum)

1Fh

20h

General Purpose RAM

(80 bytes maximum)

6Fh

70h

7Fh

Common RAM

(16 bytes)

3.2.5

DEVICE MEMORY MAPS

The memory maps for PIC16LF1902

PIC16LF1903 are as shown in

Table 3-3

.

and

DS41455B-page 20

Preliminary

2011 Microchip Technology Inc.

TABLE 3-3:

BANK 0

PIC16LF1902/3 MEMORY MAP

BANK 1 BANK 2

000h

016h

017h

018h

019h

01Ah

01Bh

01Ch

01Dh

01Eh

00Bh

00Ch

00Dh

00Eh

00Fh

010h

011h

012h

013h

014h

015h

01Fh

020h

06Fh

070h

07Fh

Core Registers

( Table 3-2

)

PORTA

PORTB

PORTC

PORTE

PIR1

PIR2

TMR0

TMR1L

TMR1H

T1CON

T1GCON

General

Purpose

Register

96 Bytes

080h 100h

Core Registers

( Table 3-2

)

096h

097h

098h

099h

09Ah

09Bh

09Ch

09Dh

09Eh

08Bh

08Ch

08Dh

08Eh

08Fh

090h

091h

092h

093h

094h

095h

TRISA

TRISB

TRISC

PIE1

PIE2

OPTION_REG

PCON

WDTCON

OSCCON

OSCSTAT

ADRESL

ADRESH

ADCON0

ADCON1

09Fh —

0A0h General Purpose

Register

32 Bytes

11Fh

120h

13Fh

140h

General Purpose

Register

48 Bytes

(1)

0EFh

0F0h

16Fh

170h

Accesses

70h – 7Fh

0FFh

116h

117h

118h

119h

11Ah

11Bh

11Ch

11Dh

11Eh

10Bh

10Ch

10Dh

10Eh

10Fh

110h

111h

112h

113h

114h

115h

17Fh

Core Registers

( Table 3-2

)

General

Purpose

Register

80 Bytes

(1)

Accesses

70h – 7Fh

BORCON

FVRCON

LATA

LATB

LATC

180h

196h

197h

198h

199h

19Ah

19Bh

19Ch

19Dh

19Eh

18Bh

18Ch

18Dh

18Eh

18Fh

190h

191h

192h

193h

194h

195h

19Fh

1A0h

1EFh

1F0h

1FFh

BANK 3

Core Registers

( Table 3-2

)

Unimplemented

Read as ‘

0

Accesses

70h – 7Fh

ANSELA

ANSELB

PMADRL

PMADRH

PMDATL

PMDATH

PMCON1

PMCON2

200h

216h

217h

218h

219h

21Ah

21Bh

21Ch

21Dh

21Eh

20Bh

20Ch

20Dh

20Eh

20Fh

210h

211h

212h

213h

214h

215h

21Fh

220h

26Fh

270h

27Fh

BANK 4

Core Registers

(

Table 3-2

)

Unimplemented

Read as ‘

0

Accesses

70h – 7Fh

WPUB

WPUE

280h

296h

297h

298h

299h

29Ah

29Bh

29Ch

29Dh

29Eh

28Bh

28Ch

28Dh

28Eh

28Fh

290h

291h

292h

293h

294h

295h

29Fh

2A0h

2EFh

2F0h

2FFh

BANK 5

Core Registers

(

Table 3-2

)

Unimplemented

Read as ‘

0

Accesses

70h – 7Fh

300h

316h

317h

318h

319h

31Ah

31Bh

31Ch

31Dh

31Eh

30Bh

30Ch

30Dh

30Eh

30Fh

310h

311h

312h

313h

314h

315h

31Fh

320h

36Fh

370h

37Fh

BANK 6

Core Registers

(

Table 3-2

)

Unimplemented

Read as ‘

0

Accesses

70h – 7Fh

380h

396h

397h

398h

399h

39Ah

39Bh

39Ch

39Dh

39Eh

38Bh

38Ch

38Dh

38Eh

38Fh

390h

391h

392h

393h

394h

395h

39Fh

3A0h

3EFh

3F0h

3FFh

BANK 7

Core Registers

(

Table 3-2

)

Unimplemented

Read as ‘

0

Accesses

70h – 7Fh

IOCBF

IOCBP

IOCBN

Legend:

Note 1:

= Unimplemented data memory locations, read as ‘

0

’.

PIC16LF1903 only.

TABLE 3-3:

BANK 8

PIC16LF1902/3 MEMORY MAP (CONTINUED)

BANK 9 BANK 10 BANK 11

400h 480h 500h 580h

Core Registers

(

Table 3-2 )

Core Registers

(

Table 3-2 )

Core Registers

(

Table 3-2 )

Core Registers

(

Table 3-2 )

40Bh

40Ch

48Bh

48Ch

50Bh

50Ch

58Bh

58Ch

Unimplemented

Read as ‘

0

Unimplemented

Read as ‘

0

Unimplemented

Read as ‘

0

Unimplemented

Read as ‘

0

46Fh

470h

4EFh

4F0h

56Fh

570h

5EFh

5F0h

Common RAM

(Accesses

70h – 7Fh)

Common RAM

(Accesses

70h – 7Fh)

Common RAM

(Accesses

70h – 7Fh)

Common RAM

(Accesses

70h – 7Fh)

47Fh

4FFh 57Fh

5FFh

BANK 17 BANK 18 BANK 19

600h

60Bh

60Ch

66Fh

670h

67Fh

800h

80Bh

80Ch

86Fh

870h

87Fh

BANK 16

Core Registers

( Table 3-2

)

Table

3-2

880h

88Bh

88Ch

Unimplemented

Read as ‘

0

8EFh

8F0h

Common RAM

(Accesses

70h – 7Fh)

8FFh

Core Registers

(

Table 3-2 )

Unimplemented

Read as ‘

0

Common RAM

(Accesses

70h – 7Fh)

900h

90Bh

90Ch

96Fh

970h

97Fh

Core Registers

(

Table 3-2 )

Unimplemented

Read as ‘

0

Common RAM

(Accesses

70h – 7Fh)

980h

98Bh

98Ch

9EFh

9F0h

9FFh

Core Registers

(

Table 3-2 )

Unimplemented

Read as ‘

0

Common RAM

(Accesses

70h – 7Fh)

A00h

A0Bh

A0Ch

A6Fh

A70h

A7Fh

BANK 12

Core Registers

(

Table 3-2 )

Unimplemented

Read as ‘

0

Common RAM

(Accesses

70h – 7Fh)

BANK 20

Core Registers

(

Table 3-2 )

Unimplemented

Read as ‘

0

Common RAM

(Accesses

70h – 7Fh)

680h

68Bh

68Ch

6EFh

6F0h

6FFh

A80h

A8Bh

A8Ch

AEFh

AF0h

AFFh

BANK 13

Core Registers

( Table 3-2 )

Unimplemented

Read as ‘

0

Common RAM

(Accesses

70h – 7Fh)

BANK 21

Core Registers

( Table 3-2 )

Unimplemented

Read as ‘

0

Common RAM

(Accesses

70h – 7Fh)

700h

70Bh

70Ch

76Fh

770h

77Fh

B00h

B0Bh

B0Ch

B6Fh

B70h

B7Fh

BANK 14

Core Registers

( Table 3-2 )

Unimplemented

Read as ‘

0

Common RAM

(Accesses

70h – 7Fh)

BANK 22

Core Registers

( Table 3-2 )

Unimplemented

Read as ‘

0

Common RAM

(Accesses

70h – 7Fh)

B80h

B8Bh

B8Ch

BEFh

BF0h

BFFh

BANK 23

Core Registers

( Table 3-2 )

Unimplemented

Read as ‘

0

Common RAM

(Accesses

70h – 7Fh)

BANK 24 BANK 25 BANK 26

C00h C80h D00h

Core Registers

( Table 3-2

)

Core Registers

( Table 3-2

)

Core Registers

( Table 3-2

)

C0Bh

C0Ch

C8Bh

C8Ch

D0Bh

D0Ch

Unimplemented

Read as ‘

0

Unimplemented

Read as ‘

0

Unimplemented

Read as ‘

0

C6Fh

C70h

CEFh

CF0h

D6Fh

D70h

C7Fh

Legend:

Common RAM

(Accesses

70h – 7Fh)

CFFh

Common RAM

(Accesses

70h – 7Fh)

D7Fh

Common RAM

(Accesses

70h – 7Fh)

= Unimplemented data memory locations, read as ‘

0

D80h

D8Bh

D8Ch

DEFh

DF0h

DFFh

BANK 27

Core Registers

( Table 3-2

)

Unimplemented

Read as ‘

0

Common RAM

(Accesses

70h – 7Fh)

E00h

E0Bh

E0Ch

E6Fh

E70h

E7Fh

BANK 28

Core Registers

( Table 3-2

)

Unimplemented

Read as ‘

0

Common RAM

(Accesses

70h – 7Fh)

E80h

E8Bh

E8Ch

EEFh

EF0h

EFFh

BANK 29

Core Registers

( Table 3-2

)

Unimplemented

Read as ‘

0

Common RAM

(Accesses

70h – 7Fh)

F00h

F0Bh

F0Ch

F6Fh

F70h

F7Fh

BANK 30

Core Registers

( Table 3-2

)

Unimplemented

Read as ‘

0

Common RAM

(Accesses

70h – 7Fh)

79Fh

7ADh

7AEh

7AFh

7B0h

7B1h

7B2h

7B3h

7B4h

7B5h

7B6h

7B7h

7B8h

7A0h

7A1h

7A2h

7A3h

7A4h

7A5h

7A6h

7A7h

7A8h

7A9h

7AAh

7ABh

7ACh

TABLE 3-3:

780h

78Bh

78Ch

790h

791h

792h

793h

794h

795h

796h

797h

798h

799h

79Ah

79Bh

79Ch

LCDDATA0

LCDDATA1

LCDDATA3

LCDDATA4

LCDDATA6

LCDDATA7

LCDDATA9

LCDDATA10

LCDDATA12

LCDDATA15

LCDDATA18

LCDDATA21

PIC16LF1902/3 MEMORY MAP (CONTINUED)

Bank 15 Bank 31

F80h

Core Registers

( Table 3-2

)

Core Registers

( Table 3-2

)

F8Bh

F8Ch

Unimplemented

Read as ‘

0

Unimplemented

Read as ‘

0

LCDCON

LCDPS

LCDREF

LCDCST

LCDRL

LCDSE0

LCDSE1

LCDSE3

Unimplemented

Read as ‘

0

FE3h

FE4h

FE5h

FE6h

FE7h

FE8h

FE9h

FEAh

FEBh

FECh

FEDh

FEEh

FEFh

FF0h

STATUS_SHAD

WREG_SHAD

BSR_SHAD

PCLATH_SHAD

FSR0L_SHAD

FSR0H_SHAD

FSR1L_SHAD

FSR1H_SHAD

STKPTR

TOSL

TOSH

Common RAM

(Accesses

70h – 7Fh)

FFFh

Unimplemented

Read as ‘

0

7EFh

Legend: = Unimplemented data memory locations, read as ‘

0

’,

PIC16LF1902/3

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 23

PIC16LF1902/3

3.2.6

CORE FUNCTION REGISTERS

SUMMARY

The Core Function registers listed in

Table 3-4

can be addressed from any Bank.

TABLE 3-4: CORE FUNCTION REGISTERS SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Bank 0-31

x00h or x80h

INDF0 x01h or x81h

INDF1 x02h or x82h

PCL x03h or x83h

STATUS x04h or x84h

FSR0L x05h or x85h

FSR0H x06h or x86h

FSR1L x07h or x87h

FSR1H

Addressing this location uses contents of FSR0H/FSR0L to address data memory

(not a physical register)

Addressing this location uses contents of FSR1H/FSR1L to address data memory

(not a physical register)

Program Counter (PC) Least Significant Byte

— — — TO

Indirect Data Memory Address 0 Low Pointer

Indirect Data Memory Address 0 High Pointer

Indirect Data Memory Address 1 Low Pointer

Indirect Data Memory Address 1 High Pointer

PD Z DC C xxxx xxxx xxxx xxxx

0000 0000

---1 1000

0000 0000

0000 0000

0000 0000

0000 0000 x08h or x88h

BSR x09h or x89h

WREG

— —

Working Register

— BSR4 BSR3 BSR2 BSR1 BSR0

---0 0000

0000 0000 x0Ah or x8Ah

PCLATH x0Bh or x8Bh

INTCON

Legend:

— Write Buffer for the upper 7 bits of the Program Counter

GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF

-000 0000

0000 0000 x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

0

’, r

= reserved.

Shaded locations are unimplemented, read as ‘

0

’.

Value on all other Resets

uuuu uuuu uuuu uuuu

0000 0000

---q quuu uuuu uuuu

0000 0000 uuuu uuuu

0000 0000

---0 0000 uuuu uuuu

-000 0000

0000 0000

DS41455B-page 24

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

TABLE 3-5: SPECIAL FUNCTION REGISTER SUMMARY

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all other

Resets

Bank 0

00Ch PORTA

00Dh PORTB

00Eh PORTC

00Fh —

010h PORTE

011h PIR1

PORTA Data Latch when written: PORTA pins when read

PORTB Data Latch when written: PORTB pins when read

PORTC Data Latch when written: PORTC pins when read

Unimplemented

TMR1GIF

ADIF

RE3 —

TMR1IF xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

— —

---- x--- ---- u---

00-- ---0 0000 ---0

012h PIR2

013h —

014h —

015h TMR0

016h TMR1L

017h TMR1H

018h T1CON

019h T1GCON

Unimplemented

Unimplemented

Timer0 Module Register

— — — LCDIF

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

TMR1CS1 TMR1CS0

TMR1GE T1GPOL

T1CKPS1

T1GTM

T1CKPS0

T1GSPM

T1OSCEN

T1GGO/

DONE

T1SYNC

T1GVAL

T1GSS1

---- -0-- ---- -0--

— —

— — xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

TMR1ON

T1GSS0

0000 00-0 uuuu uu-u

0000 0x00 uuuu uxuu

01Ah to

01Fh

— Unimplemented — —

Bank 1

08Ch TRISA

08Dh TRISB

08Eh TRISC

08Fh —

090h TRISE

091h PIE1

092h PIE2

093h —

094h —

PORTA Data Direction Register

PORTB Data Direction Register

PORTC Data Direction Register

Unimplemented

TMR1GIE

Unimplemented

ADIE

(2)

LCDIE

TMR1IE

1111 1111 1111 1111

1111 1111 1111 1111

1111 1111 1111 1111

— —

---- 1--- ---- 1---

00-- ---0 0000 ---0

---- -0-- ---- -0--

— —

— —

095h OPTION_REG

096h PCON

097h WDTCON

098h —

Unimplemented

WPUEN

STKOVF

INTEDG

STKUNF

TMR0CS

WDTPS4

TMR0SE

RWDT

WDTPS3

PSA

RMCLR

WDTPS2

PS2

RI

WDTPS1

PS1

POR

WDTPS0

PS0

BOR

1111 1111 1111 1111

00-1 11qq qq-q qquu

SWDTEN

--01 0110 --01 0110

— —

099h OSCCON

09Ah OSCSTAT

09Bh ADRESL

09Ch ADRESH

Unimplemented

T1OSCR

IRCF3

A/D Result Register Low

IRCF2

OSTS

IRCF1

HFIOFR

IRCF0

SCS1

LFIOFR

SCS0

HFIOFS

-011 1-00 -011 1-00

0-q0 --00 q-qq --0q xxxx xxxx uuuu uuuu

09Dh ADCON0

09Eh ADCON1

09Fh —

Legend:

Note 1:

2:

A/D Result Register High

— CHS4

ADFM ADCS2

Unimplemented

CHS3

ADCS1

CHS2

ADCS0

CHS1

CHS0

GO/DONE ADON x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

0

’, r

= reserved.

Shaded locations are unimplemented, read as ‘

0

’.

These registers can be addressed from any bank.

Unimplemented, read as ‘

1

’.

xxxx xxxx uuuu uuuu

-000 0000 -000 0000

ADPREF1 ADPREF0

0000 ---- 0000 ----

— —

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 25

PIC16LF1902/3

TABLE 3-5: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all other

Resets

Bank 2

10Ch LATA

10Dh LATB

10Eh LATC

10Fh to

115h

116h

117h

BORCON

FVRCON

118h to

11Fh

Bank 3

18Ch ANSELA

18Dh ANSELB

18Eh —

18Fh —

190h —

191h PMADRL

192h PMADRH

193h PMDATL

194h PMDATH

195h PMCON1

196h PMCON2

197h to

19Fh

Bank 4

20Ch —

20Dh WPUB

20Eh —

20Fh —

210h WPUE

211h to

21Fh

Bank 5

28Ch

29Fh

Bank 6

30Ch

31Fh

Legend:

Note 1:

2:

PORTA Data Latch

PORTB Data Latch

PORTC Data Latch

Unimplemented

SBOREN

FVREN

BORFS

FVRRDY

Unimplemented

TSEN

TSRNG

Unimplemented

Unimplemented

ANSA5

ANSB5

ANSB4

ANSA3

ANSB3

Unimplemented

Program Memory Address Register Low Byte

— Program Memory Address Register High Byte

Program Memory Read Data Register Low Byte

ANSA2

ANSB2

(2)

CFGS

Program Memory Read Data Register High Byte

LWLO

Program Memory Control Register 2

FREE WRERR WREN

Unimplemented

Unimplemented

WPUB7 WPUB6

Unimplemented

Unimplemented

— —

Unimplemented

Unimplemented

Unimplemented

WPUB5

WPUB4

WPUB3

WPUE3

WPUB2

ADFVR1

ANSA1

ANSB1

WR

WPUB1

— xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

BORRDY

10-- ---q uu-- ---u

ADFVR0

0q00 --00 0q00 --00

ANSA0

ANSB0

RD

WPUB0

— x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

0

’, r

= reserved.

Shaded locations are unimplemented, read as ‘

0

’.

These registers can be addressed from any bank.

Unimplemented, read as ‘

1

’.

--1- 1111 --11 1111

--11 1111 --11 1111

0000 0000 0000 0000

1000 0000 1000 0000 xxxx xxxx uuuu uuuu

--xx xxxx --uu uuuu

1000 x000 1000 q000

0000 0000 0000 0000

1111 1111 1111 1111

— —

— —

---- 1--- ---- 1---

DS41455B-page 26

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

TABLE 3-5: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all other

Resets

Bank 7

38Ch

393h

394h IOCBP

395h IOCBN

396h IOCBF

397h

39Fh

Bank 8-14

x0Ch or x8Ch to x1Fh or x9Fh

Unimplemented

IOCBP7

IOCBN7

IOCBP6

IOCBN6

IOCBF7 IOCBF6

Unimplemented

Unimplemented

IOCBP5

IOCBN5

IOCBF5

IOCBP4

IOCBN4

IOCBF4

IOCBP3

IOCBN3

IOCBF3

IOCBP2

IOCBN2

IOCBF2

IOCBP1

IOCBN1

IOCBF1

IOCBP0

IOCBN0

IOCBF0

0000 0000 0000 0000

0000 0000 0000 0000

0000 0000 0000 0000

— —

Bank 15

78Ch

790h

— Unimplemented — —

791h LCDCON

792h LCDPS

793h LCDREF

794h LCDCST

795h LCDRL

796h —

797h —

798h LCDSE0

799h LCDSE1

79Ah —

79Bh LCDSE3

79Dh

79Fh

7A0h LCDDATA0

LCDEN

WFT

LCDIRE

SE15

SLPEN

BIASMD

Unimplemented

Unimplemented

LRLAP1 LRLAP0

Unimplemented

Unimplemented

SE7 SE6

SE14

WERR

LCDA

LCDIRI

LRLBP1

SE5

SE13

WA

LRLBP0

SE4

SE12

CS1

LP3

VLCD3PE

SE3

SE11

CS0

LP2

VLCD2PE

LCDCST2

LRLAT2

SE2

SE10

SE26

LMUX1

LP1

VLCD1PE

LMUX0

LP0

000- 0011 000- 0011

0000 0000 0000 0000

LCDCST1 LCDCST0

---- -000 ---- -000

LRLAT1

SE1

SE9

SE25

LRLAT0

SE0

SE8

SE24

7A1h LCDDATA1

7A2h —

7A3h LCDDATA3

7A4h LCDDATA4

SEG7

COM0

SEG15

COM0

Unimplemented

SEG6

COM0

SEG14

COM0

SEG7

COM1

SEG15

COM1

Unimplemented

SEG6

COM1

SEG14

COM1

SEG5

COM0

SEG13

COM0

SEG5

COM1

SEG13

COM1

SEG4

COM0

SEG12

COM0

SEG4

COM1

SEG12

COM1

SEG3

COM0

SEG11

COM0

SEG3

COM1

SEG11

COM1

SEG2

COM0

SEG10

COM0

SEG2

COM1

SEG10

COM1

SEG1

COM0

SEG9

COM0

SEG1

COM1

SEG9

COM1

SEG0

COM0

SEG8

COM0

SEG0

COM1

SEG8

COM1

7A5h —

7A6h LCDDATA6

7A7h LCDDATA7

7A8h —

7A9h LCDDATA9

7AAh LCDDATA10

Legend:

Note 1:

2:

SEG7

COM2

SEG15

COM2

Unimplemented

SEG6

COM2

SEG14

COM2

SEG7

COM3

SEG15

COM3

SEG6

COM3

SEG14

COM3

SEG5

COM2

SEG13

COM2

SEG5

COM3

SEG13

COM3

SEG4

COM2

SEG12

COM2

SEG4

COM3

SEG12

COM3

SEG3

COM2

SEG11

COM2

SEG3

COM3

SEG11

COM3

SEG2

COM2

SEG10

COM2

SEG2

COM3

SEG10

COM3

SEG1

COM2

SEG9

COM2

SEG1

COM3

SEG9

COM3

SEG0

COM2

SEG8

COM2

SEG0

COM3

SEG8

COM3 x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

0

’, r

= reserved.

Shaded locations are unimplemented, read as ‘

0

’.

These registers can be addressed from any bank.

Unimplemented, read as ‘

1

’.

0-0- 000- 0-0- 000-

0000 -000 0000 -000

0000 0000 uuuu uuuu

0000 0000 uuuu uuuu

---- -000 ---- -uuu

— — xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

— xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

— xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

— xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

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Preliminary

DS41455B-page 27

PIC16LF1902/3

TABLE 3-5: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR, BOR

Value on all other

Resets

Bank 15 (Continued)

7ABh —

7ACh LCDDATA12

Unimplemented

— — — — — SEG26

COM0

SEG25

COM0

SEG24

COM0

— —

---- -xxx ---- -uuu

7ADh —

7AEh —

7AFh LCDDATA15

Unimplemented

Unimplemented

— —

---- -xxx ---- -uuu

— — — SEG26

COM1

SEG25

COM1

SEG24

COM1

7B0h —

7B1h —

7B2h LCDDATA18

Unimplemented

Unimplemented

— —

---- -xxx ---- -uuu

— — — SEG26

COM2

SEG25

COM2

SEG24

COM2

7B3h —

7B4h —

7B5h LCDDATA21

Unimplemented

Unimplemented

— —

---- -xxx ---- -uuu

— — — SEG26

COM3

SEG25

COM3

SEG24

COM3

7B6h

7EFh

Bank 16-30

x0Ch or x8Ch to x1Fh or x9Fh

Unimplemented

Unimplemented

Bank 31

F8Ch

FE3h

— Unimplemented

FE4h STATUS_SHAD

FE5h WREG_SHAD

FE6h BSR_SHAD

FE7h PCLATH_SHAD

FE8h FSR0L_SHAD

FE9h FSR0H_SHAD

FEAh FSR1L_SHAD

FEBh FSR1H_SHAD

— —

Working Register Normal (Non-ICD) Shadow

— Z_SHAD

Indirect Data Memory Address 0 Low Pointer Normal (Non-ICD) Shadow

Indirect Data Memory Address 0 High Pointer Normal (Non-ICD) Shadow

Indirect Data Memory Address 1 Low Pointer Normal (Non-ICD) Shadow

Indirect Data Memory Address 1 High Pointer Normal (Non-ICD) Shadow

DC_SHAD C_SHAD

Bank Select Register Normal (Non-ICD) Shadow

Program Counter Latch High Register Normal (Non-ICD) Shadow

FECh — Unimplemented

FEDh STKPTR

FEEh TOSL

— —

Top of Stack Low byte

— Current Stack Pointer

FEFh TOSH

Legend:

Note 1:

2:

— Top of Stack High byte x

= unknown, u

= unchanged, q

= value depends on condition, - = unimplemented, read as ‘

0

’, r

= reserved.

Shaded locations are unimplemented, read as ‘

0

’.

These registers can be addressed from any bank.

Unimplemented, read as ‘

1

’.

---- -xxx ---- -uuu xxxx xxxx uuuu uuuu

---x xxxx ---u uuuu

-xxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu

— —

---1 1111 ---1 1111 xxxx xxxx uuuu uuuu

-xxx xxxx -uuu uuuu

DS41455B-page 28

Preliminary

2011 Microchip Technology Inc.

3.3

PCL and PCLATH

The Program Counter (PC) is 15 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<14:8>) is not directly readable or writable and comes from PCLATH. On any

Reset, the PC is cleared.

Figure 3-4 shows the five

situations for the loading of the PC.

FIGURE 3-4:

PCLATH

PC

14

PCH

6

7

LOADING OF PC IN

DIFFERENT SITUATIONS

PCL

0

Instruction with

PCL as

Destination

0

8

ALU Result

PC

14

PCH

6

4

PCLATH

PC

14

PCH

7

PCLATH

6

PC

14 PCH

0

11

OPCODE <10:0>

PCL 0

0

PCL

8

W

PCL

15

PC + W

PC

14

PCH PCL

15

PC + OPCODE <8:0>

0

GOTO, CALL

0

0

CALLW

BRW

BRA

3.3.1

MODIFYING PCL

Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<14:8> bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper 7 bits to the PCLATH register. When the lower 8 bits are written to the PCL register, all 15 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register.

3.3.2

COMPUTED

GOTO

A computed

GOTO

is accomplished by adding an offset to the program counter (

ADDWF PCL

). When performing a table read using a computed

GOTO

method, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). Refer to the Application

Note AN556,

“Implementing a Table Read”

(DS00556).

PIC16LF1902/3

3.3.3

COMPUTED FUNCTION CALLS

A computed function

CALL

allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table read using a computed function

CALL

, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block).

If using the

CALL

instruction, the PCH<2:0> and PCL registers are loaded with the operand of the

CALL instruction. PCH<6:3> is loaded with PCLATH<6:3>.

The

CALLW

instruction enables computed calls by combining PCLATH and W to form the destination address.

A computed

CALLW

is accomplished by loading the W register with the desired address and executing

CALLW

.

The PCL register is loaded with the value of W and

PCH is loaded with PCLATH.

3.3.4

BRANCHING

The branching instructions add an offset to the PC.

This allows relocatable code and code that crosses page boundaries. There are two forms of branching,

BRW

and

BRA

. The PC will have incremented to fetch the next instruction in both cases. When using either branching instruction, a PCL memory boundary may be crossed.

If using

BRW

, load the W register with the desired unsigned address and execute

BRW

. The entire PC will be loaded with the address PC + 1 + W.

If using

BRA

, the entire PC will be loaded with PC + 1 +, the signed value of the operand of the

BRA

instruction.

2011 Microchip Technology Inc.

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DS41455B-page 29

PIC16LF1902/3

3.4

Stack

All devices have a 16-level x 15-bit wide hardware

stack (refer to Figures 3-3 and 3-3 ). The stack space is

not part of either program or data space. The PC is

PUSHed onto the stack when

CALL

or

CALLW

instructions are executed or an interrupt causes a branch. The stack is POPed in the event of a

RETURN

,

RETLW

or a

RETFIE

instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buffer if the STVREN bit is programmed to ‘

0

‘ (Configuration Word 2). This means that after the stack has been PUSHed sixteen times, the seventeenth PUSH overwrites the value that was stored from the first PUSH. The eighteenth PUSH overwrites the second PUSH (and so on). The

STKOVF and STKUNF flag bits will be set on an Overflow/Underflow, regardless of whether the Reset is enabled.

Note:

There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the

CALL, CALLW

,

RETURN

,

RETLW

and

RETFIE

instructions or the vectoring to an interrupt address.

FIGURE 3-5: ACCESSING THE STACK EXAMPLE 1

3.4.1

ACCESSING THE STACK

The stack is available through the TOSH, TOSL and

STKPTR registers. STKPTR is the current value of the

Stack Pointer. TOSH:TOSL register pair points to the

TOP of the stack. Both registers are read/writable. TOS is split into TOSH and TOSL due to the 15-bit size of the

PC. To access the stack, adjust the value of STKPTR, which will position TOSH:TOSL, then read/write to

TOSH:TOSL. STKPTR is 5 bits to allow detection of overflow and underflow.

Note:

Care should be taken when modifying the

STKPTR while interrupts are enabled.

During normal program operation,

CALL, CALLW

and

Interrupts will increment STKPTR while

RETLW

,

RETURN

, and

RETFIE

will decrement STKPTR. At any time STKPTR can be inspected to see how much stack is left. The STKPTR always points at the currently used place on the stack. Therefore, a

CALL

or

CALLW will increment the STKPTR and then write the PC, and a return will unload the PC and then decrement the

STKPTR.

Reference

Figure 3-5

through

Figure 3-8

for examples of accessing the stack.

TOSH:TOSL

TOSH:TOSL

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x02

0x01

0x00

0x1F 0x0000

STKPTR = 0x1F

Stack Reset Disabled

(STVREN =

0

)

Initial Stack Configuration:

After Reset, the stack is empty. The empty stack is initialized so the Stack

Pointer is pointing at 0x1F. If the Stack

Overflow/Underflow Reset is enabled, the

TOSH/TOSL registers will return ‘

0

’. If the Stack Overflow/Underflow Reset is disabled, the TOSH/TOSL registers will return the contents of stack address 0x0F.

STKPTR = 0x1F

Stack Reset Enabled

(STVREN =

1

)

DS41455B-page 30

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PIC16LF1902/3

FIGURE 3-6: ACCESSING THE STACK EXAMPLE 2

TOSH:TOSL

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x0F

0x0E

0x0D

0x0C

0x0B

0x02

0x01

0x00 Return Address

This figure shows the stack configuration after the first

If a

RETURN

CALL

or a single interrupt.

instruction is executed, the return address will be placed in the

Program Counter and the Stack Pointer decremented to the empty state (0x1F).

STKPTR = 0x00

FIGURE 3-7: ACCESSING THE STACK EXAMPLE 3

TOSH:TOSL

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x0F

0x0E

0x0D

0x0C

0x0B

0x03

0x02

0x01

0x00

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

After seven

CALL s or six

CALL s and an interrupt, the stack looks like the figure on the left. A series of

RETURN

instructions will repeatedly place the return addresses into the Program Counter and pop the stack.

STKPTR = 0x06

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PIC16LF1902/3

FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

Return Address

When the stack is full, the next

CALL

or an interrupt will set the Stack Pointer to

0x10. This is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. If the Stack

Overflow/Underflow Reset is enabled, a

Reset will occur and location 0x00 will not be overwritten.

STKPTR = 0x10

TOSH:TOSL

3.4.2

OVERFLOW/UNDERFLOW RESET

If the STVREN bit in Configuration Word 2 is programmed to ‘

1

’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits

(STKOVF or STKUNF, respectively) in the PCON register.

3.5

Indirect Addressing

The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the

File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘

0

’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL.

The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions:

• Traditional Data Memory

• Linear Data Memory

• Program Flash Memory

DS41455B-page 32

Preliminary

2011 Microchip Technology Inc.

FIGURE 3-9: INDIRECT ADDRESSING

0x0000

0x0000

Traditional

Data Memory

PIC16LF1902/3

0x0FFF

0x1000

0x1FFF

0x2000

0x0FFF

Reserved

Linear

Data Memory

FSR

Address

Range

0x29AF

0x29B0

0x7FFF

0x8000

Reserved

0x0000

Program

Flash Memory

0xFFFF 0x7FFF

Note:

Not all memory regions are completely implemented. Consult device memory tables for memory limits.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 33

PIC16LF1902/3

3.5.1

TRADITIONAL DATA MEMORY

The traditional data memory is a region from FSR address 0x000 to FSR address 0xFFF. The addresses correspond to the absolute addresses of all SFR, GPR and common registers.

FIGURE 3-10: TRADITIONAL DATA MEMORY MAP

4 BSR

Direct Addressing

0 6

Bank Select

From Opcode

0

Location Select

00000 00001 00010

0x00

7

0 0 0

FSRxH

0

Indirect Addressing

0 7 FSRxL

Bank Select

11111

0

Location Select

0x7F

Bank 0 Bank 1 Bank 2 Bank 31

DS41455B-page 34

Preliminary

2011 Microchip Technology Inc.

3.5.2

LINEAR DATA MEMORY

The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of

GPR memory in all the banks.

Unimplemented memory reads as 0x00. Use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the FSR beyond one bank will go directly to the GPR memory of the next bank.

The 16 bytes of common memory are not included in the linear data memory region.

FIGURE 3-11: LINEAR DATA MEMORY

MAP

7

0 0

FSRnH

1

0 7

FSRnL 0

Location Select

0x2000

0x020

Bank 0

0x06F

0x0A0

Bank 1

0x0EF

0x120

Bank 2

0x16F

PIC16LF1902/3

3.5.3

PROGRAM FLASH MEMORY

To make constant data access easier, the entire program Flash memory is mapped to the upper half of the FSR address space. When the MSB of FSRnH is set, the lower 15 bits are the address in program memory which will be accessed through INDF. Only the lower 8 bits of each memory location is accessible via

INDF. Writing to the program Flash memory cannot be accomplished via the FSR/INDF interface. All instructions that access program Flash memory via the

FSR/INDF interface will require one additional instruction cycle to complete.

FIGURE 3-12: PROGRAM FLASH

MEMORY MAP

7

1

FSRnH 0

7

FSRnL 0

Location Select

0x8000

0x0000

Program

Flash

Memory

(low 8 bits)

0x29AF

0xF20

Bank 30

0xF6F

0xFFFF

0x7FFF

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DS41455B-page 35

PIC16LF1902/3

NOTES:

DS41455B-page 36

Preliminary

2011 Microchip Technology Inc.

4.0

DEVICE CONFIGURATION

Device Configuration consists of Configuration Word 1 and Configuration Word 2, Code Protection and Device

ID.

4.1

Configuration Words

There are several Configuration Word bits that allow different oscillator and memory protection options.

These are implemented as Configuration Word 1 at

8007h and Configuration Word 2 at 8008h.

Note:

The DEBUG bit in Configuration Word 2 is managed automatically by device development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘

1

’.

PIC16LF1902/3

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 37

PIC16LF1902/3

REGISTER 4-1:

bit 7

R/P-1

CP

CONFIGURATION WORD 1

U-1

— bit 13

U-1

R/P-1

MCLRE

R/P-1

PWRTE

R/P-1

CLKOUTEN

R/P-1 R/P-1

WDTE<1:0>

R/P-1

U-1

R/P-1

BOREN<1:0>

U-1

— bit 8

R/P-1 R/P-1

FOSC<1:0> bit 0

Legend:

R = Readable bit

‘0’ = Bit is cleared bit 13-12 bit 11 bit 10-9 bit 8 bit 7 bit 6 bit 5 bit 4-3 bit 2 bit 1-0

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘1’

-n = Value when blank or after Bulk Erase

Unimplemented:

Read as ‘

1

CLKOUTEN:

Clock Out Enable bit

1

= CLKOUT function is disabled. I/O function on the CLKOUT pin.

0

= CLKOUT function is enabled on the CLKOUT pin

BOREN<1:0>:

Brown-out Reset Enable bits

11

= BOR enabled

10

= BOR enabled during operation and disabled in Sleep

01

= BOR controlled by SBOREN bit of the BORCON register

00

= BOR disabled

Unimplemented:

Read as ‘

1

CP:

Code Protection bit

1

= Program memory code protection is disabled

0

= Program memory code protection is enabled

MCLRE:

MCLR/V

PP

Pin Function Select bit

If LVP bit =

1

:

This bit is ignored.

If LVP bit =

0

:

1

= MCLR/V

PP

pin function is MCLR; Weak pull-up enabled.

0

= MCLR/V

PP

pin function is digital input; MCLR internally disabled; Weak pull-up under control of

WPUE3 bit.

PWRTE:

Power-up Timer Enable bit

1

= PWRT disabled

0

= PWRT enabled

WDTE<1:0>:

Watchdog Timer Enable bit

11

= WDT enabled

10

= WDT enabled while running and disabled in Sleep

01

= WDT controlled by the SWDTEN bit in the WDTCON register

00

= WDT disabled

Unimplemented:

Read as ‘

1

FOSC<1:0>:

Oscillator Selection bits

00

= INTOSC oscillator: I/O function on CLKIN pin

01

= ECL: External Clock, Low-Power mode (0-0.5 MHz): device clock supplied to CLKIN pin

10

= ECM: External Clock, Medium-Power mode (0.5-4 MHz): device clock supplied to CLKIN pin

11

= ECH: External Clock, High-Power mode (4-32 MHz): device clock supplied to CLKIN pin

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REGISTER 4-2:

bit 7

U-1

U-1

CONFIGURATION WORD 2

R/P-1

LVP bit 13

R/P-1

DEBUG

U-1

U-1

R/P-1

LPBOR

U-1

R/P-1

BORV

U-1

R/P-1

STVREN

U-1

— bit 8

R/P-1 R/P-1

WRT<1:0> bit 0

Legend:

R = Readable bit

‘0’ = Bit is cleared bit 13 bit 12 bit 11 bit 10 bit 9 bit 8-2 bit 1-0

P = Programmable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘1’

-n = Value when blank or after Bulk Erase

LVP:

Low-Voltage Programming Enable bit

1

= Low-voltage programming enabled

0

= High-voltage on MCLR must be used for programming

DEBUG:

In-Circuit Debugger Mode bit

1

= In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins

0

= In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger

LPBOR:

Low-Power BOR bit

1

= Low-Power BOR is disabled

0

= Low-Power BOR is enabled

BORV:

Brown-out Reset Voltage Selection bit

1

= Brown-out Reset voltage set to 1.9V (typical)

0

= Brown-out Reset voltage set to 2.5V (typical)

STVREN:

Stack Overflow/Underflow Reset Enable bit

1

= Stack Overflow or Underflow will cause a Reset

0

= Stack Overflow or Underflow will not cause a Reset

Unimplemented:

Read as ‘

1

WRT<1:0>:

Flash Memory Self-Write Protection bits

2 kW Flash memory (PIC16LF1902 only):

11

= Write protection off

10

= 000h to 1FFh write-protected, 200h to 7FFh may be modified by PMCON control

01

= 000h to 3FFh write-protected, 400h to 7FFh may be modified by PMCON control

00

= 000h to 7FFh write-protected, no addresses may be modified by PMCON control

4 kW Flash memory (PIC16LF1903 only):

11

= Write protection off

10

= 000h to 1FFh write-protected, 200h to FFFh may be modified by PMCON control

01

= 000h to 7FFh write-protected, 800h to FFFh may be modified by PMCON control

00

= 000h to FFFh write-protected, no addresses may be modified by PMCON control

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PIC16LF1902/3

4.2

Code Protection

Code protection allows the device to be protected from unauthorized access. Program memory protection is controlled independently. Internal access to the program memory is unaffected by any code protection setting.

4.2.1

PROGRAM MEMORY PROTECTION

The entire program memory space is protected from external reads and writes by the CP bit in Configuration

Word 1. When CP =

0

, external reads and writes of program memory are inhibited and a read will return all

0

’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. See

Section 4.3 “Write

Protection”

for more information.

4.3

Write Protection

Write protection allows the device to be protected from unintended self-writes. Applications, such as boot loader software, can be protected while allowing other regions of the program memory to be modified.

The WRT<1:0> bits in Configuration Word 2 define the size of the program memory block that is protected.

4.4

User ID

Four memory locations (8000h-8003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are readable and writable during normal execution. See

Section 10.4 “User ID, Device ID and Configuration

Word Access”

for more information on accessing

these memory locations.

For more information on checksum calculation, see the

PIC16F193X/LF193X/PIC16F194X/LF194X/PIC16LF

190X Memory Programming Specification

(DS41397)

.

DS41455B-page 40

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PIC16LF1902/3

4.5

Device ID and Revision ID

The memory location 8006h is where the Device ID and

Revision ID are stored. The upper nine bits hold the

Device ID. The lower five bits hold the Revision ID. See

Section 10.4 “User ID, Device ID and Configuration

Word Access”

for more information on accessing

these memory locations.

Development tools, such as device programmers and debuggers, may be used to read the Device ID and

Revision ID.

REGISTER 4-3: DEVICEID: DEVICE ID REGISTER

R R R

DEV<8:3>

R bit 13

R R

REV<4:0>

R R

DEV<2:0>

R bit 7

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 13-5

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

DEV<8:0>:

Device ID bits

R

R

R

R

R bit 8 bit 0

U = Unimplemented bit, read as ‘1’

-n/n = Value at POR and BOR/Value at all other Resets

P = Programmable bit

Device

PIC16LF1902

PIC16LF1903

DEVICEID<13:0> Values

DEV<8:0>

01 1100 000

01 1100 001

REV<4:0>

x xxxx x xxxx bit 4-0

REV<4:0>:

Revision ID bits

These bits are used to identify the revision (see Table under DEV<8:0> above).

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NOTES:

DS41455B-page 42

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PIC16LF1902/3

A simplified block diagram of the On-Chip Reset Circuit is shown in

Figure 5-1

.

5.0

RESETS

There are multiple ways to reset this device:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Low-Power Brown-out Reset (LPBOR)

• MCLR Reset

• WDT Reset

RESET

instruction

• Stack Overflow

• Stack Underflow

• Programming mode exit

To allow V

DD

to stabilize, an optional power-up timer can be enabled to extend the Reset time after a BOR or POR event.

FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Programming Mode Exit

RESET

Instruction

MCLR

Stack

Pointer

Stack Overflow/Underflow Reset

External Reset

MCLRE

Sleep

WDT

Time-out

V

DD

Power-on

Reset

Brown-out

Reset

LPBOR

Reset

BOR

Enable

Zero

LFINTOSC

PWRT

64 ms

PWRTEN

Device

Reset

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5.1

Power-on Reset (POR)

The POR circuit holds the device in Reset until V

DD

has reached an acceptable level for minimum operation.

Slow rising V

DD

, fast operating speeds or analog performance may require greater than minimum V

DD

.

The PWRT, BOR or MCLR features can be used to extend the start-up period until all device operation conditions have been met.

5.1.1

POWER-UP TIMER (PWRT)

The Power-up Timer provides a nominal 64 ms time-out on POR or Brown-out Reset.

The device is held in Reset as long as PWRT is active.

The PWRT delay allows additional time for the V

DD

to rise to an acceptable level. The Power-up Timer is enabled by clearing the PWRTE bit in Configuration

Word 1.

The Power-up Timer starts after the release of the POR and BOR.

For additional information, refer to Application Note

AN607,

“Power-up Trouble Shooting”

(DS00607).

5.2

Brown-Out Reset (BOR)

The BOR circuit holds the device in Reset when V

DD reaches a selectable minimum level. Between the

POR and BOR, complete voltage range coverage for execution protection can be implemented.

The Brown-out Reset module has four operating modes controlled by the BOREN<1:0> bits in Configuration Word 1. The four operating modes are:

• BOR is always on

• BOR is off when in Sleep

• BOR is controlled by software

• BOR is always off

Refer to Table 5-1 for more information.

The Brown-out Reset voltage level is selectable by configuring the BORV bit in Configuration Word 2.

A V

DD

noise rejection filter prevents the BOR from triggering on small events. If V

DD

falls below V

BOR

for a duration greater than parameter T

BORDC

, the device

will reset. See Figure 5-2 for more information.

TABLE 5-1: BOR OPERATING MODES

BOREN<1:0> SBOREN Device Mode BOR Mode

Device Operation upon release of POR

Device Operation upon wake- up from

Sleep

Waits for BOR ready

(1)

11 X

X

Awake

Active

Active

10

01

X

1

Sleep

X

Waits for BOR ready

Disabled

Active

Disabled

Begins immediately

Begins immediately

0

00 X

X Disabled Begins immediately

Note 1:

Even though this case specifically waits for the BOR, the BOR is already operating, so there is no delay in start-up.

5.2.1

BOR IS ALWAYS ON

When the BOREN bits of Configuration Word 1 are set to ‘

11

’, the BOR is always on. The device start-up will be delayed until the BOR is ready and V

DD

is higher than the BOR threshold.

BOR protection is active during Sleep. The BOR does not delay wake-up from Sleep.

5.2.2

BOR IS OFF IN SLEEP

When the BOREN bits of Configuration Word 1 are set to ‘

10

’, the BOR is on, except in Sleep. The device start-up will be delayed until the BOR is ready and V

DD is higher than the BOR threshold.

BOR protection is not active during Sleep. The device wake-up will be delayed until the BOR is ready.

5.2.3

BOR CONTROLLED BY SOFTWARE

When the BOREN bits of Configuration Word 1 are set to ‘

01

’, the BOR is controlled by the SBOREN bit of the

BORCON register. The device start-up is not delayed by the BOR ready condition or the V

DD

level.

BOR protection begins as soon as the BOR circuit is ready. The status of the BOR circuit is reflected in the

BORRDY bit of the BORCON register.

BOR protection is unchanged by Sleep.

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FIGURE 5-2:

V

DD

BROWN-OUT SITUATIONS

Internal

Reset

V

DD

Internal

Reset

V

DD

< T

T

PWRT

PWRT

(1)

T

PWRT

(1)

Internal

Reset

Note 1:

T

PWRT

delay only if PWRTE bit is programmed to ‘

0

’.

T

PWRT

(1)

V

BOR

V

BOR

V

BOR

REGISTER 5-1:

R/W-1/u

SBOREN bit 7

BORCON: BROWN-OUT RESET CONTROL REGISTER

R/W-0/u

BORFS

U-0

U-0

U-0

U-0

U-0

R-q/u

BORRDY bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5-1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition

SBOREN:

Software Brown-out Reset Enable bit

If BOREN <1:0> in Configuration Word 1

01

:

SBOREN is read/write, but has no effect on the BOR.

If BOREN <1:0> in Configuration Word 1 =

01

:

1

= BOR Enabled

0

= BOR Disabled

BORFS:

Brown-out Reset Fast Start bit

(1)

If BOREN<1:0> =

11

(Always on) or BOREN<1:0> =

00

(Always off)

BORFS is Read/Write, but has no effect.

If BOREN <1:0> =

10

(Disabled in Sleep) or BOREN<1:0> =

01

(Under software control):

1

= Band gap is forced on always (covers sleep/wake-up/operating cases)

0

=

Band gap operates normally, and may turn off

Unimplemented:

Read as ‘

0

BORRDY:

Brown-out Reset Circuit Ready Status bit

1

= The Brown-out Reset circuit is active

0

= The Brown-out Reset circuit is inactive

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5.3

Low-Power Brown-out Reset

(LPBOR)

The Low-Power Brown-Out Reset (LPBOR) is an essential part of the Reset subsystem. Refer to

Figure 5-1 to see how the BOR interacts with other

modules.

The LPBOR is used to monitor the external V

DD

pin.

When too low of a voltage is detected, the device is held in Reset. When this occurs, a register bit (BOR) is changed to indicate that a BOR Reset has occurred.

The same bit is set for both the BOR and the LPBOR.

Refer to Register 5-2 .

5.3.1

ENABLING LPBOR

The LPBOR is controlled by the LPBOR bit of

Configuration Word 2. When the device is erased, the

LPBOR module defaults to disabled.

5.3.1.1

LPBOR Module Output

The output of the LPBOR module is a signal indicating whether or not a Reset is to be asserted. This signal is to be OR’d together with the Reset signal of the BOR module to provide the generic BOR signal which goes to the PCON register and to the power control block.

5.4

MCLR

The MCLR is an optional external input that can reset the device. The MCLR function is controlled by the

MCLRE bit of Configuration Word 1 and the LVP bit of

Configuration Word 2 (

Table 5-2

).

TABLE 5-2:

MCLRE

0

1 x

MCLR CONFIGURATION

LVP

0

0

1

MCLR

Disabled

Enabled

Enabled

5.4.1

MCLR ENABLED

When MCLR is enabled and the pin is held low, the device is held in Reset. The MCLR pin is connected to

V

DD

through an internal weak pull-up.

The device has a noise filter in the MCLR Reset path.

The filter will detect and ignore small pulses.

Note:

A Reset does not drive the MCLR pin low.

5.4.2

MCLR DISABLED

When MCLR is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. See

Section 11.4 “PORTE Registers”

for more information.

5.5

Watchdog Timer (WDT) Reset

The Watchdog Timer generates a Reset if the firmware does not issue a

CLRWDT

instruction within the time-out period. The TO and PD bits in the STATUS register are

changed to indicate the WDT Reset. See

Section 9.0

“Watchdog Timer”

for more information.

5.6

RESET

Instruction

A

RESET

instruction will cause a device Reset. The RI bit in the PCON register will be set to ‘

0

’. See

Table 5-4

for default conditions after a

RESET

instruction has occurred.

5.7

Stack Overflow/Underflow Reset

The device can reset when the Stack Overflows or

Underflows. The STKOVF or STKUNF bits of the PCON register indicate the Reset condition. These Resets are enabled by setting the STVREN bit in Configuration Word

2. See

Section 5.7 “Stack Overflow/Underflow Reset”

for more information.

5.8

Programming Mode Exit

Upon exit of Programming mode, the device will behave as if a POR had just occurred.

5.9

Power-Up Timer

The Power-up Timer optionally delays device execution after a BOR or POR event. This timer is typically used to allow V

DD

to stabilize before allowing the device to start running.

The Power-up Timer is controlled by the PWRTE bit of

Configuration Word 1.

5.10

Start-up Sequence

Upon the release of a POR or BOR, the following must occur before the device will begin executing:

1.

2.

Power-up Timer runs to completion (if enabled).

Oscillator start-up timer runs to completion (if required for oscillator source).

MCLR must be released (if enabled).

3.

The total time-out will vary based on oscillator configuration and Power-up Timer configuration. See

Section 6.0 “Oscillator Module”

for more information.

The Power-up Timer and oscillator start-up timer run independently of MCLR Reset. If MCLR is kept low long enough, the Power-up Timer and oscillator start-up timer will expire. Upon bringing MCLR high, the device will begin execution immediately (see

Figure 5-3 ). This is useful for testing purposes or to

synchronize more than one device operating in parallel.

DS41455B-page 46

Preliminary

2011 Microchip Technology Inc.

FIGURE 5-3: RESET START-UP SEQUENCE

V

DD

Internal POR

Power-Up Timer

MCLR

Internal RESET

External Crystal

Oscillator Start-Up Timer

Oscillator

F

OSC

Oscillator Modes

Internal Oscillator

Oscillator

F

OSC

External Clock (EC)

CLKIN

F

OSC

T

PWRT

T

MCLR

T

OST

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5.11

Determining the Cause of a Reset

Upon any Reset, multiple bits in the STATUS and

PCON register are updated to indicate the cause of the

Reset.

Table 5-3

and

Table 5-4 show the Reset condi-

tions of these registers.

TABLE 5-3: RESET STATUS BITS AND THEIR SIGNIFICANCE

STKOVF STKUNF RWDT RMCLR RI POR BOR TO PD

u u

0 u

0

0

0 u

1 u u u

0

0

1 u

1 x

0 u u u

0 u

0

1

1

0

1

0 x u u u

1 u u u

0 u x x x u u u u u u u u u

0

0

0 u u u u u u u

1 u

1

1

1

0 u u u u u u

1 u

1

1

1 u u

0

0 u u u u

0

1

1

1 u u u u u u u

0 u

0

0

0 u u u u

1

Condition

Power-on Reset

Illegal, TO is set on POR

Illegal, PD is set on POR

Brown-out Reset

WDT Reset

WDT Wake-up from Sleep

Interrupt Wake-up from Sleep

MCLR Reset during normal operation

MCLR Reset during Sleep

RESET

Instruction Executed

Stack Overflow Reset (STVREN =

1

)

Stack Underflow Reset (STVREN =

1

)

TABLE 5-4: RESET CONDITION FOR SPECIAL REGISTERS

(2)

Condition

Program

Counter

STATUS

Register

PCON

Register

Power-on Reset

MCLR Reset during normal operation

0000h

0000h

---1 1000 00-1 110x

---u uuuu uu-u 0uuu

MCLR Reset during Sleep 0000h

---1 0uuu uu-u 0uuu

WDT Reset

WDT Wake-up from Sleep

0000h

PC + 1

---0 uuuu uu-0 uuuu

---0 0uuu uu-u uuuu

Brown-out Reset

Interrupt Wake-up from Sleep

0000h

PC + 1

(1)

---1 1uuu 00-1 11u0

---1 0uuu uu-u uuuu

RESET

Instruction Executed

Stack Overflow Reset (STVREN =

1

)

0000h

0000h

---u uuuu

---u uuuu uu-u u0uu

1u-u uuuu

Stack Underflow Reset (STVREN =

1

) 0000h

---u uuuu u1-u uuuu

Legend:

Note 1:

u

= unchanged, x

= unknown,

-

= unimplemented bit, reads as ‘

0

’.

When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on

2:

the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1.

If a Status bit is not implemented, that bit will be read as ‘

0

’.

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PIC16LF1902/3

5.12

Power Control (PCON) Register

The Power Control (PCON) register contains flag bits to differentiate between a:

• Power-on Reset (POR)

• Brown-out Reset (BOR)

• Reset Instruction Reset (RI)

• MCLR Reset (RMCLR)

• Watchdog Timer Reset (RWDT)

• Stack Underflow Reset (STKUNF)

• Stack Overflow Reset (STKOVF)

The PCON register bits are shown in

Register 5-2 .

REGISTER 5-2:

R/W/HS-0/q

STKOVF bit 7

PCON: POWER CONTROL REGISTER

R/W/HS-0/q

STKUNF

U-0

R/W/HC-1/q R/W/HC-1/q

RWDT RMCLR

R/W/HC-1/q

RI

R/W/HC-q/u

POR

R/W/HC-q/u

BOR bit 0

Legend:

HC = Bit is cleared by hardware

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

HS = Bit is set by hardware

U = Unimplemented bit, read as ‘0’

-m/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition

STKOVF:

Stack Overflow Flag bit

1

= A Stack Overflow occurred

0

= A Stack Overflow has not occurred or set to ‘

0

’ by firmware

STKUNF:

Stack Underflow Flag bit

1

= A Stack Underflow occurred

0

= A Stack Underflow has not occurred or set to ‘

0

’ by firmware

Unimplemented:

Read as ‘

0

RWDT:

Watchdog Timer Reset Flag bit

1

= A Watchdog Timer Reset has not occurred or set to ‘

1

’ by firmware

0

= A Watchdog Timer Reset has occurred (set to ‘

0

’ in hardware when a Watchdog Timer Reset)

RMCLR:

MCLR Reset Flag bit

1

= A MCLR Reset has not occurred or set to ‘

1

’ by firmware

0

= A MCLR Reset has occurred (set to ‘

0

’ in hardware when a MCLR Reset occurs)

RI:

RESET

Instruction Flag bit

1

= A

RESET

instruction has not been executed or set to ‘

1

’ by firmware

0

= A

RESET

instruction has been executed (set to ‘

0

’ in hardware upon executing a

RESET

instruction)

POR:

Power-on Reset Status bit

1

= No Power-on Reset occurred

0

= A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

BOR:

Brown-out Reset Status bit

1

= No Brown-out Reset occurred

0

= A Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs)

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TABLE 5-5: SUMMARY OF REGISTERS ASSOCIATED WITH RESETS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1

BORCON

PCON

SBOREN

STKOVF

BORFS

STKUNF

RWDT

RMCLR

RI

POR

STATUS — — — TO PD Z DC

WDTCON

Legend:

— — WDTPS<4:0>

— = unimplemented location, read as ‘

0

’. Shaded cells are not used by Resets.

Bit 0

BORRDY

BOR

C

SWDTEN

Register on Page

45

49

19

77

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6.0

OSCILLATOR MODULE

6.1

Overview

The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption.

Figure 6-1

illustrates a block diagram of the oscillator module.

Clock sources can be supplied from external clock circuits. In addition, the system clock source can be supplied from one of two internal oscillators, with a choice of speeds selectable via software. Additional clock features include:

• Selectable system clock source between external or internal sources via software.

• Fast start-up oscillator allows internal circuits to power up and stabilize before switching to the 16

MHz HFINTOSC

The oscillator module can be configured in one of the following Clock modes:

1.

2.

3.

4.

ECL – External Clock Low Power mode

(0 MHz to 0.5 MHz)

ECM – External Clock Medium Power mode

(0.5 MHz to 4 MHz)

ECH – External Clock High Power mode

(4 MHz to 32 MHz)

INTOSC – Internal oscillator (31 kHz to 16 MHz).

Clock Source modes are selected by the FOSC<1:0> bits in the Configuration Word 1. The FOSC bits determine the type of oscillator that will be used when the device is first powered.

The EC Clock mode relies on an external logic level signal as the device clock source.

The INTOSC internal oscillator block produces a low and high frequency clock source, designated

LFINTOSC and HFINTOSC. (see Internal Oscillator

Block,

Figure 6-1

). A wide selection of device clock frequencies may be derived from these two clock sources.

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FIGURE 6-1: SIMPLIFIED PIC

®

MCU CLOCK SOURCE BLOCK DIAGRAM

CLKIN

CLKIN

EC

Low-Power Mode

Event Switch

(SCS<1:0>)

2

Primary Clock

00

Secondary Clock

01

Secondary Oscillator

T1CKI/

T1OSO

T1OSI

Secondary

Oscillator

(T1OSC)

Internal Oscillator

IRCF<3:0>

Start-up

Control

Logic

16 MHz

Primary Osc

Start-Up Osc

LF-INTOSC

(31 kHz)

4 4

/128

/256

/512

/1

/2

/4

/8

/16

/32

/64

HF-16 MHz

HF-8 MHz

HF-4 MHz

HF-2 MHz

HF-1 MHz

HF-500 kHz

HF-250 kHz

HF-125 kHz

HF-62.5 kHz

HF-31.25 kHz

LF-31 kHz

1111

1110

1101

1100

1011

1010/

0111

1001/

0110

1000/

0101

0100

0011

0010

0001

0000

INTOSC

1x

DS41455B-page 52

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2011 Microchip Technology Inc.

6.2

Clock Source Types

Clock sources can be classified as external or internal.

External clock sources rely on external circuitry for the clock source to function. An example is: oscillator module (EC mode) circuit.

Internal clock sources are contained internally within the oscillator module. The internal oscillator block has two internal oscillators that are used to generate the internal system clock sources: the 16 MHz High-Frequency

Internal Oscillator and the 31 kHz Low-Frequency

Internal Oscillator (LFINTOSC).

The system clock can be selected between external or internal clock sources via the System Clock Select

(SCS) bits in the OSCCON register. See

Section 6.3

“Clock Switching”

for additional information.

6.2.1

EXTERNAL CLOCK SOURCES

An external clock source can be used as the device system clock by performing one of the following actions:

• Program the FOSC<1:0> bits in the Configuration

Word 1 to select an external clock source that will be used as the default system clock upon a device Reset.

• Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to:

- Secondary oscillator during run-time, or

- An external clock source determined by the value of the FOSC bits.

See

Section 6.3 “Clock Switching”

for more informa-

tion.

6.2.1.1

EC Mode

The External Clock (EC) mode allows an externally generated logic level signal to be the system clock source. When operating in this mode, an external clock source is connected to the CLKIN input. CLKOUT is available for general purpose I/O or CLKOUT.

Figure 6-2

shows the pin connections for EC mode.

EC mode has 3 power modes to select from through

Configuration Word 1:

• High power, 4-20 MHz (FOSC =

11

)

• Medium power, 0.5-4 MHz (FOSC =

10

)

• Low power, 0-0.5 MHz (FOSC =

01

)

PIC16LF1902/3

The Oscillator Start-up Timer (OST) is disabled when

EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep. Because the PIC

®

MCU design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact.

Upon restarting the external clock, the device will resume operation as if no time had elapsed.

FIGURE 6-2: EXTERNAL CLOCK (EC)

MODE OPERATION

Clock from

Ext. System

CLKIN

PIC

®

MCU

CLKOUT

F

OSC

/4 or I/O

(1)

Note 1:

Output depends upon CLKOUTEN bit of the

Configuration Word 1.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 53

PIC16LF1902/3

6.2.1.2

Secondary Oscillator

The secondary oscillator is a separate crystal oscillator that is associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1CKI/T1OSO and

T1OSI device pins.

The secondary oscillator can be used as an alternate system clock source and can be selected during

run-time using clock switching. Refer to

Section 6.3

“Clock Switching”

for more information.

FIGURE 6-3: QUARTZ CRYSTAL

OPERATION

(SECONDARY

OSCILLATOR)

C1

C2

32.768 kHz

Quartz

Crystal

PIC

®

MCU

T1CKI/T1OSO

To Internal

Logic

T1OSI

Note 1:

Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application.

2:

3:

Always verify oscillator performance over the V

DD

and temperature range that is expected for the application.

For oscillator design assistance, reference the following Microchip Applications Notes:

• AN826, “

Crystal Oscillator Basics and

Crystal Selection for rfPIC

®

and PIC

®

Devices

” (DS00826)

• AN849, “

Basic PIC

®

Oscillator Design

(DS00849)

• AN943, “

Practical PIC

®

Oscillator

Analysis and Design

” (DS00943)

• AN949, “

Making Your Oscillator Work

(DS00949)

• TB097, “

Interfacing a Micro Crystal

MS1V-T1K 32.768 kHz Tuning Fork

Crystal to a PIC16F690/SS

” (DS91097)

• AN1288, “

Design Practices for

Low-Power External Oscillators

(DS01288)

6.2.2

INTERNAL CLOCK SOURCES

The device may be configured to use the internal oscillator block as the system clock by performing one of the following actions:

• Program the FOSC<1:0> bits in Configuration

Word 1 to select the INTOSC clock source, which will be used as the default system clock upon a device Reset.

• Write the SCS<1:0> bits in the OSCCON register to switch the system clock source to the internal oscillator during run-time. See

Section 6.3

“Clock Switching”

for more information.

In

INTOSC

mode, CLKIN is available for general purpose I/O. CLKOUT is available for general purpose

I/O or CLKOUT.

The function of the CLKOUT pin is determined by the state of the CLKOUTEN bit in Configuration Word 1.

The internal oscillator block has two independent oscillators that provides the internal system clock source.

1.

2.

The

HFINTOSC

(High-Frequency Internal

Oscillator) is factory calibrated and operates at

16 MHz.

The

LFINTOSC

(Low-Frequency Internal

Oscillator) is uncalibrated and operates at

31 kHz.

6.2.2.1

HFINTOSC

The High-Frequency Internal Oscillator (HFINTOSC) is a factory calibrated 16 MHz internal clock source.

The output of the HFINTOSC connects to a postscaler

and multiplexer (see Figure 6-1

). The frequency derived from the HFINTOSC can be selected via software using the IRCF<3:0> bits of the OSCCON register. See

Section 6.2.2.4 “Internal Oscillator Clock Switch

Timing”

for more information.

The HFINTOSC is enabled by:

• Configure the IRCF<3:0> bits of the OSCCON register for the desired HF frequency, and

• FOSC<1:0> =

11

, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘

1x

’.

The High-Frequency Internal Oscillator Ready bit

(HFIOFR) of the OSCSTAT register indicates when the

HFINTOSC is running and can be utilized.

The High-Frequency Internal Oscillator Status Stable bit (HFIOFS) of the OSCSTAT register indicates when the HFINTOSC is running within 0.5% of its final value.

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PIC16LF1902/3

6.2.2.2

LFINTOSC

The Low-Frequency Internal Oscillator (LFINTOSC) is an uncalibrated 31 kHz internal clock source.

The output of the LFINTOSC connects to a postscaler

and multiplexer (see Figure 6-1

). Select 31 kHz, via software, using the IRCF<3:0> bits of the OSCCON

register. See

Section 6.2.2.4 “Internal Oscillator

Clock Switch Timing”

for more information. The

LFINTOSC is also the frequency for the Power-up Timer

(PWRT) and Watchdog Timer (WDT).

The LFINTOSC is enabled by selecting 31 kHz

(IRCF<3:0> bits of the OSCCON register =

000)

as the system clock source (SCS bits of the OSCCON register =

1x

), or when any of the following are enabled:

• Configure the IRCF<3:0> bits of the OSCCON register for the desired LF frequency, and

• FOSC<1:0> =

01

, or

• Set the System Clock Source (SCS) bits of the

OSCCON register to ‘

1x

Peripherals that use the LFINTOSC are:

• Power-up Timer (PWRT)

• Watchdog Timer (WDT)

The Low-Frequency Internal Oscillator Ready bit

(LFIOFR) of the OSCSTAT register indicates when the

LFINTOSC is running and can be utilized.

6.2.2.3

Internal Oscillator Frequency

Selection

The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits

IRCF<3:0> of the OSCCON register.

The output of the 16 MHz HFINTOSC and 31 kHz

LFINTOSC connects to a postscaler and multiplexer

(see

Figure 6-1

). The Internal Oscillator Frequency

Select bits IRCF<3:0> of the OSCCON register select the frequency output of the internal oscillators. One of the following frequencies can be selected via software:

• 16 MHz

• 8 MHz

• 4 MHz

• 2 MHz

• 1 MHz

• 500 kHz (Default after Reset)

• 250 kHz

• 125 kHz

• 62.5 kHz

• 31.25 kHz

• 31 kHz (LFINTOSC)

Note:

Following any Reset, the IRCF<3:0> bits of the OSCCON register are set to ‘

0111

’ and the frequency selection is set to

500 kHz. The user can modify the IRCF bits to select a different frequency.

The IRCF<3:0> bits of the OSCCON register allow duplicate selections for some frequencies. These duplicate choices can offer system design trade-offs. Lower power consumption can be obtained when changing oscillator sources for a given frequency. Faster transition times can be obtained between frequency changes that use the same oscillator source.

6.2.2.4

Internal Oscillator Clock Switch

Timing

5.

6.

7.

When switching between the HFINTOSC and the

LFINTOSC, the new oscillator may already be shut

down to save power (see Figure 6-4 ). If this is the case,

there is a delay after the IRCF<3:0> bits of the

OSCCON register are modified before the frequency selection takes place. The OSCSTAT register will reflect the current active status of the HFINTOSC and

LFINTOSC oscillators. The sequence of a frequency selection is as follows:

1.

2.

3.

4.

IRCF<3:0> bits of the OSCCON register are modified.

If the new clock is shut down, a clock start-up delay is started.

Clock switch circuitry waits for a falling edge of the current clock.

The current clock is held low and the clock switch circuitry waits for a rising edge in the new clock.

The new clock is now active.

The OSCSTAT register is updated as required.

Clock switch is complete.

See Figure 6-4 for more details.

If the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. Clock switching time delays are shown in

Table 6-1

.

Start-up delay specifications are located in the oscillator tables of

Section 21.0 “Electrical

Specifications”

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 55

PIC16LF1902/3

FIGURE 6-4: INTERNAL OSCILLATOR SWITCH TIMING

HFINTOSC

HFINTOSC

LFINTOSC (WDT disabled)

Start-up Time

LFINTOSC

IRCF <3:0>

System Clock



0



0

2-cycle Sync

HFINTOSC LFINTOSC (WDT enabled)

HFINTOSC

LFINTOSC

IRCF <3:0>

System Clock



0

2-cycle Sync



0

Running

Running

LFINTOSC

LFINTOSC

HFINTOSC

Start-up Time 2-cycle Sync

HFINTOSC

IRCF <3:0>

System Clock

= 0

0

LFINTOSC turns off unless WDT is enabled

Running

DS41455B-page 56

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2011 Microchip Technology Inc.

6.3

Clock Switching

The system clock source can be switched between external and internal clock sources via software using the System Clock Select (SCS) bits of the OSCCON register. The following clock sources can be selected using the SCS bits:

• Default system oscillator determined by FOSC bits in Configuration Word 1

• Secondary oscillator 32 kHz crystal

• Internal Oscillator Block (INTOSC)

6.3.1

SYSTEM CLOCK SELECT (SCS)

BITS

The System Clock Select (SCS) bits of the OSCCON register selects the system clock source that is used for the CPU and peripherals.

• When the SCS bits of the OSCCON register =

00

, the system clock source is determined by value of the FOSC<1:0> bits in the Configuration Word 1.

• When the SCS bits of the OSCCON register =

01

, the system clock source is the secondary oscillator.

• When the SCS bits of the OSCCON register =

1x

, the system clock source is chosen by the internal oscillator frequency selected by the IRCF<3:0> bits of the OSCCON register. After a Reset, the

SCS bits of the OSCCON register are always cleared.

When switching between clock sources, a delay is required to allow the new clock to stabilize. These oscil-

lator delays are shown in Table 6-1 .

6.3.2

OSCILLATOR START-UP TIME-OUT

STATUS (OSTS) BIT

The Oscillator Start-up Time-out Status (OSTS) bit of the OSCSTAT register indicates whether the system clock is running from the external clock source, as defined by the FOSC<1:0> bits in the Configuration

Word 1, or from the internal clock source. The OST does not reflect the status of the secondary oscillator.

PIC16LF1902/3

6.3.3

SECONDARY OSCILLATOR

The secondary oscillator is a separate crystal oscillator associated with the Timer1 peripheral. It is optimized for timekeeping operations with a 32.768 kHz crystal connected between the T1OSI and T1CKI/T1OSO device pins.

The secondary oscillator is enabled using the

T1OSCEN control bit in the T1CON register. See

Section 17.0 “Timer1 Module with Gate Control”

for more information about the Timer1 peripheral.

6.3.4

SECONDARY OSCILLATOR READY

(T1OSCR) BIT

The user must ensure that the secondary oscillator is ready to be used before it is selected as a system clock source. The Secondary Oscillator Ready (T1OSCR) bit of the OSCSTAT register indicates whether the secondary oscillator is ready to be used. After the

T1OSCR bit is set, the SCS bits can be configured to select the secondary oscillator.

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PIC16LF1902/3

6.4

Oscillator Control Registers

REGISTER 6-1: OSCCON: OSCILLATOR CONTROL REGISTER

bit 7

U-0

R/W-0/0 R/W-1/1 R/W-1/1

IRCF<3:0>

R/W-1/1 U-0

R/W-0/0 R/W-0/0

SCS<1:0> bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7 bit 6-3 bit 2 bit 1-0

Unimplemented:

Read as ‘

0

IRCF<3:0>:

Internal Oscillator Frequency Select bits

000x

= 31 kHz LF

001x

= 31.25 kHz

0100

= 62.5 kHz

0101

= 125 kHz

0110

= 250 kHz

0111

= 500 kHz (default upon Reset)

1000

= 125 kHz

(1)

1001

= 250 kHz

(1)

1010

= 500 kHz

(1)

1011

= 1 MHz

1100

= 2 MHz

1101

= 4 MHz

1110

= 8 MHz

1111

= 16 MHz

Unimplemented:

Read as ‘

0

SCS<1:0>:

System Clock Select bits

1x

= Internal oscillator block

01

= Secondary oscillator

00

= Clock determined by FOSC<1:0> in Configuration Word 1.

Note 1:

Duplicate frequency derived from HFINTOSC.

DS41455B-page 58

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PIC16LF1902/3

REGISTER 6-2:

R-1/q

T1OSCR bit 7

OSCSTAT: OSCILLATOR STATUS REGISTER

U-0

R-q/q

OSTS

R-0/q

HFIOFR

U-0

U-0

R-0/0

LFIOFR

R-0/q

HFIOFS bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets q = Conditional bit 7 bit 6 bit 5 bit 4 bit 3-2 bit 1 bit 0

T1OSCR:

Timer1 Oscillator Ready bit

If T1OSCEN =

1

:

1

= Timer1 oscillator is ready

0

= Timer1 oscillator is not ready

If T1OSCEN = 0:

1

= Timer1 clock source is always ready

Unimplemented:

Read as ‘

0

OSTS:

Oscillator Start-up Time-out Status bit

1

= Running from the external clock source (EC)

0

= Running from an internal oscillator (FOSC<1:0> =

00

)

HFIOFR:

High-Frequency Internal Oscillator Ready bit

1

= HFINTOSC is ready

0

= HFINTOSC is not ready

Unimplemented:

Read as ‘

0

LFIOFR:

Low-Frequency Internal Oscillator Ready bit

1

= LFINTOSC is ready

0

= LFINTOSC is not ready

HFIOFS:

High-Frequency Internal Oscillator Stable bit

1

= HFINTOSC 16 MHz oscillator is stable and is driving the INTOSC

0

= HFINTOSC 16 MHz oscillator is not stable, the Start-up Oscillator is driving INTOSC

TABLE 6-1: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

OSCCON

OSCSTAT

T1CON

Legend:

T1OSCR —

TMR1CS<1:0>

IRCF<3:0>

OSTS HFIOFR

T1CKPS<1:0>

T1OSCEN

T1SYNC

— = unimplemented location, read as ‘

0

’. Shaded cells are not used by clock sources.

SCS<1:0>

LFIOFR HFIOFS

TMR1ON

Register on Page

58

59

141

TABLE 6-2: SUMMARY OF CONFIGURATION WORD WITH CLOCK SOURCES

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

Legend:

13:8

7:0

CP

MCLRE

PWRTE

— CLKOUTEN

WDTE<1:0>

BOREN<1:0>

— = unimplemented location, read as ‘

0

’. Shaded cells are not used by clock sources.

FOSC<1:0>

Register on Page

38

2011 Microchip Technology Inc.

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PIC16LF1902/3

NOTES:

DS41455B-page 60

Preliminary

2011 Microchip Technology Inc.

7.0

INTERRUPTS

The interrupt feature allows certain events to preempt normal program flow. Firmware is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from

Sleep mode.

This chapter contains the following information for

Interrupts:

• Operation

• Interrupt Latency

• Interrupts During Sleep

• INT Pin

• Automatic Context Saving

Many peripherals produce Interrupts. Refer to the corresponding chapters for details.

FIGURE 7-1: INTERRUPT LOGIC

PIC16LF1902/3

A block diagram of the interrupt logic is shown in

Figure 7.1

and Figure 7.1

.

Peripheral Interrupts

(TMR1IF) PIR1<0>

(TMR1IF) PIR1<0>

PIRn<7>

PIEn<7>

TMR0IF

TMR0IE

INTF

INTE

IOCIF

IOCIE

PEIE

GIE

Wake-up

(If in Sleep mode)

Interrupt to CPU

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DS41455B-page 61

PIC16LF1902/3

7.1

Operation

Interrupts are disabled upon any device Reset. They are enabled by setting the following bits:

• GIE bit of the INTCON register

• Interrupt Enable bit(s) for the specific interrupt event(s)

• PEIE bit of the INTCON register (if the Interrupt

Enable bit of the interrupt event is contained in the

PIE1 and PIE2 registers)

The INTCON, PIR1 and PIR2 registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits.

The following events happen when an interrupt event occurs while the GIE bit is set:

• Current prefetched instruction is flushed

• GIE bit is cleared

• Current Program Counter (PC) is pushed onto the stack

• Critical registers are automatically saved to the shadow registers (See

Section 7.5 “Automatic

Context Saving”

)

• PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector.

The

RETFIE

instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit.

For additional information on a specific interrupt’s operation, refer to its peripheral chapter.

Note 1:

Individual interrupt flag bits are set, regardless of the state of any other enable bits.

2:

All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again.

7.2

Interrupt Latency

Interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. The latency for synchronous interrupts is 3 or 4 instruction cycles. For asynchronous interrupts, the latency is 3 to 5 instruction cycles,

depending on when the interrupt occurs. See Figure 7-2

and Figure 7.3

for more details.

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PIC16LF1902/3

FIGURE 7-2: INTERRUPT LATENCY

CLKIN

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKOUT

Interrupt Sampled during Q1

Interrupt

GIE

PC PC-1 PC

Execute

1 Cycle Instruction at PC

Inst(PC)

PC+1

NOP

0004h

NOP

0005h

Inst(0004h)

Interrupt

GIE

PC

PC-1 PC

Execute 2 Cycle Instruction at PC

PC+1/FSR

ADDR

Inst(PC)

New PC/

PC+1

NOP

0004h

NOP

0005h

Inst(0004h)

Interrupt

GIE

PC

PC-1 PC

Execute 3 Cycle Instruction at PC

FSR ADDR

INST(PC)

Interrupt

GIE

PC

PC-1 PC

Execute 3 Cycle Instruction at PC

FSR ADDR

INST(PC)

PC+1

NOP

PC+1

NOP

PC+2

NOP

0004h

NOP

0005h

Inst(0004h) Inst(0005h)

NOP

PC+2

NOP

0004h

NOP

0005h

Inst(0004h)

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PIC16LF1902/3

FIGURE 7-3: INT PIN INTERRUPT TIMING

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKIN

CLKOUT

(3)

(4)

INT pin

INTF

(1)

(5)

(1)

Interrupt Latency

(2)

GIE

INSTRUCTION FLOW

PC

Instruction

Fetched

PC

Inst (PC)

PC + 1

Inst (PC + 1)

PC + 1

0004h

Inst (0004h)

0005h

Inst (0005h)

Instruction

Executed

Inst (PC – 1) Inst (PC)

Dummy Cycle Dummy Cycle

Inst (0004h)

Note 1:

2:

3:

4:

5:

INTF flag is sampled here (every Q1).

Asynchronous interrupt latency = 3-5 T

CY

. Synchronous latency = 3-4 T

CY

, where T

CY

= instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.

CLKOUT not available in all Oscillator modes.

For minimum width of INT pulse, refer to AC specifications in

Section 21.0 “Electrical Specifications”

.

INTF is enabled to be set any time during the Q4-Q1 cycles.

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7.3

Interrupts During Sleep

Some interrupts can be used to wake from Sleep. To wake from Sleep, the peripheral must be able to operate without the system clock. The interrupt source must have the appropriate Interrupt Enable bit(s) set prior to entering Sleep.

On waking from Sleep, if the GIE bit is also set, the processor will branch to the interrupt vector. Otherwise, the processor will continue executing instructions after the

SLEEP

instruction. The instruction directly after the

SLEEP

instruction will always be executed before

branching to the ISR. Refer to the

Section 8.0

“Power-Down Mode (Sleep)”

for more details.

7.4

INT Pin

The INT pin can be used to generate an asynchronous edge-triggered interrupt. This interrupt is enabled by setting the INTE bit of the INTCON register. The

INTEDG bit of the OPTION_REG register determines on which edge the interrupt will occur. When the INTEDG bit is set, the rising edge will cause the interrupt. When the INTEDG bit is clear, the falling edge will cause the interrupt. The INTF bit of the INTCON register will be set when a valid edge appears on the INT pin. If the GIE and

INTE bits are also set, the processor will redirect program execution to the interrupt vector.

7.5

Automatic Context Saving

Upon entering an interrupt, the return PC address is saved on the stack. Additionally, the following registers are automatically saved in the Shadow registers:

• W register

• STATUS register (except for TO and PD)

• BSR register

• FSR registers

• PCLATH register

Upon exiting the Interrupt Service Routine, these registers are automatically restored. Any modifications to these registers during the ISR will be lost. If modifications to any of these registers are desired, the corresponding Shadow register should be modified and the value will be restored when exiting the ISR. The

Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s application, other registers may also need to be saved.

PIC16LF1902/3

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PIC16LF1902/3

7.6

Interrupt Control Registers

7.6.1

INTCON REGISTER

The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, interrupt-on-change and external INT pin interrupts.

REGISTER 7-1:

Note:

INTCON: INTERRUPT CONTROL REGISTER

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global

Enable bit, GIE of the INTCON register.

User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

R/W-0/0

GIE bit 7

R/W-0/0

PEIE

R/W-0/0

TMR0IE

R/W-0/0

INTE

R/W-0/0

IOCIE

R/W-0/0

TMR0IF

R/W-0/0

INTF

R-0/0

IOCIF bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

GIE:

Global Interrupt Enable bit

1

= Enables all active interrupts

0

= Disables all interrupts

PEIE:

Peripheral Interrupt Enable bit

1

= Enables all active peripheral interrupts

0

= Disables all peripheral interrupts

TMR0IE:

Timer0 Overflow Interrupt Enable bit

1

= Enables the Timer0 interrupt

0

= Disables the Timer0 interrupt

INTE:

INT External Interrupt Enable bit

1

= Enables the INT external interrupt

0

= Disables the INT external interrupt

IOCIE:

Interrupt-on-Change Interrupt Enable bit

1

= Enables the interrupt-on-change interrupt

0

= Disables the interrupt-on-change interrupt

TMR0IF:

Timer0 Overflow Interrupt Flag bit

1

= TMR0 register has overflowed

0

= TMR0 register did not overflow

INTF:

INT External Interrupt Flag bit

1

= The INT external interrupt occurred

0

= The INT external interrupt did not occur

IOCIF:

Interrupt-on-Change Interrupt Flag bit

1

= When at least one of the interrupt-on-change pins changed state

0

= None of the interrupt-on-change pins have changed state

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7.6.2

PIE1 REGISTER

The PIE1 register contains the interrupt enable bits, as

shown in Register 7-2 .

REGISTER 7-2:

Note:

Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.

PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1

R/W-0/0

TMR1GIE bit 7

R/W-0/0

ADIE

U-0

U-0

U-0

U-0

U-0

R/W-0/0

TMR1IE bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7 bit 6 bit 5-1 bit 0

TMR1GIE:

Timer1 Gate Interrupt Enable bit

1

= Enables the Timer1 Gate Acquisition interrupt

0

= Disables the Timer1 Gate Acquisition interrupt

ADIE:

A/D Converter (ADC) Interrupt Enable bit

1

= Enables the ADC interrupt

0

= Disables the ADC interrupt

Unimplemented:

Read as ‘

0

TMR1IE:

Timer1 Overflow Interrupt Enable bit

1

= Enables the Timer1 overflow interrupt

0

= Disables the Timer1 overflow interrupt

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7.6.3

PIE2 REGISTER

The PIE2 register contains the interrupt enable bits, as

shown in Register 7-3 .

REGISTER 7-3:

Note:

Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.

PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2

bit 7

U-0

U-0

U-0

U-0

U-0

R/W-0/0

LCDIE

U-0

U-0

— bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-3 bit 2 bit 1-0

Unimplemented:

Read as ‘

0

LCDIE:

LCD Module Interrupt Enable bit

1

= Enables the LCD module interrupt

0

= Disables the LCD module interrupt

Unimplemented:

Read as ‘

0

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PIC16LF1902/3

7.6.4

PIR1 REGISTER

The PIR1 register contains the interrupt flag bits, as

shown in Register 7-4 .

REGISTER 7-4:

Note:

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1

R/W-0/0

TMR1GIF bit 7

R/W-0/0

ADIF

U-0

U-0

U-0

U-0

U-0

R/W-0/0

TMR1IF bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5-1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

TMR1GIF:

Timer1 Gate Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

ADIF:

A/D Converter Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

Unimplemented:

Read as ‘

0

TMR1IF:

Timer1 Overflow Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

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7.6.5

PIR2 REGISTER

The PIR2 register contains the interrupt flag bits, as

shown in Register 7-5 .

REGISTER 7-5:

Note:

Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

bit 7

U-0

U-0

U-0

U-0

U-0

R/W-0/0

LCDIF

U-0

U-0

— bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-3 bit 2 bit 1-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

Unimplemented:

Read as ‘

0

LCDIF:

LCD Module Interrupt Flag bit

1

= Interrupt is pending

0

= Interrupt is not pending

Unimplemented:

Read as ‘

0

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

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PIC16LF1902/3

TABLE 7-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE

OPTION_REG WPUEN

PIE1 TMR1GIE

TMR0IE INTE

INTEDG TMR0CS TMR0SE

ADIE — —

PIE2

PIR1

PIR2

Legend:

TMR1GIF

ADIF

IOCIE

PSA

TMR0IF

LCDIE

INTF

PS<2:0>

— — — — — LCDIF —

— = unimplemented location, read as ‘

0

’. Shaded cells are not used by Interrupts.

IOCIF

TMR1IE

TMR1IF

Register on Page

66

131

67

68

69

70

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NOTES:

DS41455B-page 72

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8.0

POWER-DOWN MODE (SLEEP)

The Power-Down mode is entered by executing a

SLEEP

instruction.

Upon entering Sleep mode, the following conditions exist:

2.

3.

4.

5.

1.

WDT will be cleared but keeps running, if enabled for operation during Sleep.

PD bit of the STATUS register is cleared.

TO bit of the STATUS register is set.

CPU clock is disabled.

31 kHz LFINTOSC is unaffected and peripherals that operate from it may continue operation in

Sleep.

6.

7.

Secondary oscillator is unaffected and peripherals that operate from it may continue operation in Sleep.

ADC is unaffected, if the dedicated FRC clock is selected.

Capacitive Sensing oscillator is unaffected.

8.

9.

I/O ports maintain the status they had before

SLEEP

was executed (driving high, low or high-impedance).

10. Resets other than WDT are not affected by

Sleep mode.

Refer to individual chapters for more details on peripheral operation during Sleep.

To minimize current consumption, the following conditions should be considered:

• I/O pins should not be floating

• External circuitry sinking current from I/O pins

• Internal circuitry sourcing current from I/O pins

• Current draw from pins with internal weak pull-ups

• Modules using 31 kHz LFINTOSC

• Modules using Secondary oscillator

I/O pins that are high-impedance inputs should be pulled to V

DD

or V

SS

externally to avoid switching currents caused by floating inputs.

Examples of internal circuitry that might be sourcing

current include the FVR module. See

13.0 “Fixed Voltage Reference (FVR)”

for more information.

PIC16LF1902/3

8.1

Wake-up from Sleep

The device can wake-up from Sleep through one of the following events:

4.

5.

6.

1.

2.

3.

External Reset input on MCLR pin, if enabled

BOR Reset, if enabled

POR Reset

Watchdog Timer, if enabled

Any external interrupt

Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information)

The first three events will cause a device Reset. The last three events are considered a continuation of program execution. To determine whether a device Reset or wake-up event occurred, refer to

Section 5.11,

Determining the Cause of a Reset

.

When the

SLEEP

instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the

SLEEP

instruction. If the GIE bit is enabled, the device executes the instruction after the

SLEEP

instruction, the device will then call the Interrupt

Service Routine. In cases where the execution of the instruction following

SLEEP is not desirable, the user should have a

NOP

after the

SLEEP

instruction.

The WDT is cleared when the device wakes up from

Sleep, regardless of the source of wake-up.

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8.1.1

WAKE-UP USING INTERRUPTS

When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur:

• If the interrupt occurs

before

the execution of a

SLEEP

instruction

-

SLEEP

instruction will execute as a

NOP

.

- WDT and WDT prescaler will not be cleared

- TO bit of the STATUS register will not be set

- PD bit of the STATUS register will not be cleared.

• If the interrupt occurs

during or after

the execution of a

SLEEP

instruction

-

SLEEP cuted

instruction will be completely exe-

- Device will immediately wake-up from Sleep

- WDT and WDT prescaler will be cleared

- TO bit of the STATUS register will be set

- PD bit of the STATUS register will be cleared.

Even if the flag bits were checked before executing a

SLEEP

instruction, it may be possible for flag bits to become set before the

SLEEP

instruction completes. To determine whether a

SLEEP

instruction executed, test the PD bit. If the PD bit is set, the

SLEEP

instruction was executed as a

NOP

.

FIGURE 8-1: WAKE-UP FROM SLEEP THROUGH INTERRUPT

CLKIN

(1)

CLKOUT

(2)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Interrupt flag

GIE bit

(INTCON reg.)

Processor in

Sleep

Interrupt Latency

(1)

Instruction Flow

PC

Instruction

Fetched

Instruction

Executed

PC

Inst(PC) = Sleep

Inst(PC - 1)

PC + 1

Inst(PC + 1)

Sleep

PC + 2 PC + 2

Inst(PC + 2)

Inst(PC + 1)

PC + 2

Dummy Cycle

0004h

Inst(0004h)

Dummy Cycle

0005h

Inst(0005h)

Inst(0004h)

Note 1:

GIE =

1

assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE =

0

, execution will continue in-line.

TABLE 8-1: SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON

IOCBF

IOCBN

IOCBP

PIE1

PIE2

PIR1

PIR2

STATUS

WDTCON

Legend:

GIE

IOCBF7

IOCBN7

IOCBP7

PEIE

IOCBF6

IOCBN6

IOCBP6

TMR0IE

IOCBF5

IOCBN5

IOCBP5

INTE

IOCBF4

IOCBN4

IOCBP4

IOCIE

IOCBF3

IOCBN3

IOCBP3

TMR0IF

IOCBF2

IOCBN2

IOCBP2

INTF

IOCBF1

IOCBN1

IOCBP1

IOCIF

IOCBF0

IOCBN0

IOCBP0

TMR1GIE

TMR1GIF

ADIE

ADIF

LCDIE

TMR1IE

TMR1IF

TO

PD

LCDIF

Z

DC

C

— — WDTPS<4:0>

— = unimplemented location, read as ‘

0

’. Shaded cells are not used in Power-down mode.

SWDTEN

Register on

Page

67

68

69

70

66

108

108

108

19

77

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PIC16LF1902/3

9.0

WATCHDOG TIMER

The Watchdog Timer is a system timer that generates a Reset if the firmware does not issue a

CLRWDT instruction within the time-out period. The Watchdog

Timer is typically used to recover the system from unexpected events.

The WDT has the following features:

• Independent clock source

• Multiple operating modes

- WDT is always on

- WDT is off when in Sleep

- WDT is controlled by software

- WDT is always off

• Configurable time-out period is from 1 ms to 256 seconds (typical)

• Multiple Reset conditions

• Operation during Sleep

FIGURE 9-1: WATCHDOG TIMER BLOCK DIAGRAM

WDTE<1:0> =

01

SWDTEN

WDTE<1:0> =

11

WDTE<1:0> =

10

Sleep

LFINTOSC

23-bit Programmable

Prescaler WDT

WDTPS<4:0>

WDT Time-out

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9.1

Independent Clock Source

The WDT derives its time base from the 31 kHz

LFINTOSC internal oscillator. Time intervals in this chapter are based on a nominal interval of 1 ms. See

Section 21.0 “Electrical Specifications”

for the

LFINTOSC tolerances.

9.3

Time-Out Period

The WDTPS bits of the WDTCON register set the time-out period from 1 ms to 256 seconds (nominal).

After a Reset, the default time-out period is 2 seconds.

9.2

WDT Operating Modes

The Watchdog Timer module has four operating modes controlled by the WDTE<1:0> bits in Configuration

Word 1. See

Table 9-1

.

9.2.1

WDT IS ALWAYS ON

When the WDTE bits of Configuration Word 1 are set to

11

’, the WDT is always on.

WDT protection is active during Sleep.

9.4

Clearing the WDT

The WDT is cleared when any of the following conditions occur:

• Any Reset

CLRWDT

instruction is executed

• Device enters Sleep

• Device wakes up from Sleep

• Oscillator fail event

• WDT is disabled

• Oscillator Start-up TImer (OST) is running

See Table 9-2 for more information.

9.2.2

WDT IS OFF IN SLEEP

When the WDTE bits of Configuration Word 1 are set to

10

’, the WDT is on, except in Sleep.

WDT protection is not active during Sleep.

9.2.3

WDT CONTROLLED BY SOFTWARE

When the WDTE bits of Configuration Word 1 are set to

01

’, the WDT is controlled by the SWDTEN bit of the

WDTCON register.

WDT protection is unchanged by Sleep. See

Table 9-1

for more details.

TABLE 9-1:

WDTE<1:0>

WDT OPERATING MODES

SWDTEN

Device

Mode

WDT

Mode

11

10

01

X

X

1

X

Awake

Sleep

X

Active

Active

Disabled

Active

Disabled

0

00

TABLE 9-2:

X

X Disabled

WDT CLEARING CONDITIONS

Conditions

WDTE<1:0> =

00

WDTE<1:0> =

01 and SWDTEN =

0

WDTE<1:0> =

10 and enter Sleep

CLRWDT

Command

Oscillator Fail Detected

Exit Sleep + System Clock = T1OSC, EXTRC, INTOSC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP

Change INTOSC divider (IRCF bits)

9.5

Operation During Sleep

When the device enters Sleep, the WDT is cleared. If the WDT is enabled during Sleep, the WDT resumes counting.

When the device exits Sleep, the WDT is cleared again. The WDT remains clear until the OST, if enabled, completes. See

Section 6.0 “Oscillator

Module”

for more information on the OST.

When a WDT time-out occurs while the device is in

Sleep, no Reset is generated. Instead, the device wakes up and resumes operation. The TO and PD bits in the STATUS register are changed to indicate the

event. See

Section 3.0 “Memory Organization”

and

STATUS register (

Register 3-1 )

for more information.

WDT

Cleared

Cleared until the end of OST

Unaffected

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PIC16LF1902/3

9.6

Watchdog Control Register

REGISTER 9-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER

bit 7

U-0

U-0

R/W-0/0 R/W-1/1 R/W-0/0

WDTPS<4:0>

R/W-1/1 R/W-1/1 R/W-0/0

SWDTEN bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-m/n = Value at POR and BOR/Value at all other Resets bit 7-6 bit 5-1

Unimplemented:

Read as ‘

0

WDTPS<4:0>:

Watchdog Timer Period Select bits

(1)

Bit Value = Prescale Rate

00000

= 1:32 (Interval 1 ms nominal)

00001

= 1:64 (Interval 2 ms nominal)

00010

= 1:128 (Interval 4 ms nominal)

00011

= 1:256 (Interval 8 ms nominal)

00100

= 1:512 (Interval 16 ms nominal)

00101

= 1:1024 (Interval 32 ms nominal)

00110

= 1:2048 (Interval 64 ms nominal)

00111

= 1:4096 (Interval 128 ms nominal)

01000

= 1:8192 (Interval 256 ms nominal)

01001

= 1:16384 (Interval 512 ms nominal)

01010

= 1:32768 (Interval 1s nominal)

01011

= 1:65536 (Interval 2s nominal) (Reset value)

01100

= 1:131072 (2

01101

= 1:262144 (2

17

18

) (Interval 4s nominal)

01110

= 1:524288 (2

19

01111

= 1:1048576 (2

) (Interval 8s nominal)

) (Interval 16s nominal)

20

10000

= 1:2097152 (2

21

) (Interval 32s nominal)

) (Interval 64s nominal)

10001

= 1:4194304 (2

22

10010

= 1:8388608 (2

23

) (Interval 128s nominal)

) (Interval 256s nominal) bit 0

Note 1:

10011

= Reserved. Results in minimum interval (1:32)

11111

= Reserved. Results in minimum interval (1:32)

SWDTEN:

Software Enable/Disable for Watchdog Timer bit

If WDTE<1:0> =

00

:

This bit is ignored.

If WDTE<1:0> =

01

:

1

= WDT is turned on

0

= WDT is turned off

If WDTE<1:0> =

1x

:

This bit is ignored.

Times are approximate. WDT time is based on 31 kHz LFINTOSC.

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TABLE 9-3: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER

Name

OSCCON

STATUS

WDTCON

Legend:

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register on Page

— IRCF<3:0> — SCS<1:0>

58

— — — TO PD Z DC C

19

— — WDTPS<4:0> SWDTEN

77

x

= unknown, u

= unchanged, – = unimplemented locations read as ‘

0

’. Shaded cells are not used by Watchdog Timer.

TABLE 9-4: SUMMARY OF CONFIGURATION WORD WITH WATCHDOG TIMER

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1

CONFIG1

Legend:

13:8 — — FCMEN IESO CLKOUTEN BOREN<1:0>

7:0 CP MCLRE PWRTE WDTE<1:0>

— = unimplemented location, read as ‘

0

’. Shaded cells are not used by Watchdog Timer.

FOSC<2:0>

Bit 8/0

Register on Page

38

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10.0

FLASH PROGRAM MEMORY

CONTROL

The Flash program memory is readable and writable during normal operation over the full V

DD

range.

Program memory is indirectly addressed using Special

Function Registers (SFRs). The SFRs used to access program memory are:

• PMCON1

• PMCON2

• PMDATL

• PMDATH

• PMADRL

• PMADRH

When accessing the program memory, the

PMDATH:PMDATL register pair forms a 2-byte word that holds the 14-bit data for read/write, and the

PMDATH:PMDATL register pair forms a 2-byte word that holds the 15-bit address of the program memory location being read.

The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the operating voltage range of the device.

The Flash program memory can be protected in two ways; by code protection (CP bit in Configuration Word 1) and write protection (WRT<1:0> bits in Configuration

Word 2).

Code protection (CP =

0

)

(1)

, disables access, reading and writing, to the Flash program memory via external device programmers. Code protection does not affect the self-write and erase functionality. Code protection can only be reset by a device programmer performing a Bulk Erase to the device, clearing all Flash program memory, Configuration bits and user IDs.

Write protection prohibits self-write and erase to a portion or all of the Flash program memory as defined by the bits WRT<1:0>. Write protection does not affect a device programmers ability to read, write or erase the device.

Note 1:

Code protection of the entire Flash program memory array is enabled by clearing the CP bit of Configuration Word 1.

10.1

PMADRL and PMADRH Registers

The PMADRH:PMADRL register pair can address up to a maximum of 32K words of program memory. When selecting a program address value, the MSB of the address is written to the PMADRH register and the LSB is written to the PMADRL register.

PIC16LF1902/3

10.1.1

PMCON1 AND PMCON2

REGISTERS

PMCON1 is the control register for Flash program memory accesses.

Control bits RD and WR initiate read and write, respectively. These bits cannot be cleared, only set, in software. They are cleared by hardware at completion of the read or write operation. The inability to clear the

WR bit in software prevents the accidental, premature termination of a write operation.

The WREN bit, when set, will allow a write operation to occur. On power-up, the WREN bit is clear. The

WRERR bit is set when a write operation is interrupted by a Reset during normal operation. In these situations, following Reset, the user can check the WRERR bit and execute the appropriate error handling routine.

The PMCON2 register is a write-only register. Attempting to read the PMCON2 register will return all ‘

0

’s.

To enable writes to the program memory, a specific pattern (the unlock sequence), must be written to the

PMCON2 register. The required unlock sequence prevents inadvertent writes to the program memory write latches and Flash program memory.

10.2

Flash Program Memory Overview

It is important to understand the Flash program memory structure for erase and programming operations. Flash program memory is arranged in rows. A row consists of a fixed number of 14-bit program memory words. A row is the minimum size that can be erased by user software.

After a row has been erased, the user can reprogram all or a portion of this row. Data to be written into the program memory row is written to 14-bit wide data write latches. These write latches are not directly accessible to the user, but may be loaded via sequential writes to the PMDATH:PMDATL register pair.

Note:

If the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in RAM prior to the erase.

Then, new data and retained data can be written into the write latches to reprogram the row of Flash program memory. However, any unprogrammed locations can be written without first erasing the row. In this case, it is not necessary to save and rewrite the other previously programmed locations.

See

Table 10-1 for Erase Row size and the number of

write latches for Flash program memory.

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TABLE 10-1:

Device

PIC16(L)F1526

PIC16(L)F1527

FLASH MEMORY

ORGANIZATION BY DEVICE

Row Erase

(words)

Write

Latches

(words)

32 32

10.2.1

READING THE FLASH PROGRAM

MEMORY

To read a program memory location, the user must:

1.

2.

3.

Write the desired address to the

PMADRH:PMADRL register pair.

Clear the CFGS bit of the PMCON1 register.

Then, set control bit RD of the PMCON1 register.

Once the read control bit is set, the program memory

Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “

BSF PMCON1,RD

” instruction to be ignored. The data is available in the very next cycle, in the PMDATH:PMDATL register pair; therefore, it can be read as two bytes in the following instructions.

PMDATH:PMDATL register pair will hold this value until another read or until it is written to by the user.

Note:

The two instructions following a program memory read are required to be

NOP s.

This prevents the user from executing a two-cycle instruction on the next instruction after the RD bit is set.

FIGURE 10-1: FLASH PROGRAM

MEMORY READ

FLOWCHART

Start

Read Operation

Select

Program or Configuration Memory

(CFGS)

Select

Word Address

(PMADRH:PMADRL)

Initiate Read Operation

(RD =

1

)

Instruction Fetched ignored

NOP

execution forced

Instruction Fetched ignored

NOP

execution forced

Data read now in

PMDATH:PMDATL

End

Read Operation

DS41455B-page 80

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

FIGURE 10-2: FLASH PROGRAM MEMORY READ CYCLE EXECUTION

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Flash ADDR

PC PC + 1 PMADRH,PMADRL PC + 4 PC + 5

Flash Data INSTR (PC) INSTR (PC + 1) PMDATH,PMDATL INSTR (PC + 3) INSTR (PC + 4)

INSTR(PC - 1) executed here

BSF PMCON1,RD executed here

INSTR(PC + 1) instruction ignored

Forced NOP executed here

INSTR(PC + 2) instruction ignored

Forced NOP executed here

INSTR(PC + 3) executed here

INSTR(PC + 4) executed here

RD bit

PMDATH

PMDATL

Register

EXAMPLE 10-1: FLASH PROGRAM MEMORY READ

*

*

* This code block will read 1 word of program

* memory at the memory address:

PROG_ADDR_HI : PROG_ADDR_LO data will be returned in the variables;

PROG_DATA_HI, PROG_DATA_LO

BANKSEL

MOVLW

MOVWF

MOVLW

MOVWL

BCF

BSF

NOP

NOP

PMADRL

PROG_ADDR_LO

PMADRL

PROG_ADDR_HI

PMADRH

PMCON1,CFGS

PMCON1,RD

; Select Bank for PMCON registers

;

; Store LSB of address

;

; Store MSB of address

; Do not select Configuration Space

; Initiate read

; Ignored (

; Ignored (

Figure 10-2

Figure 10-2

)

)

MOVF

MOVWF

MOVF

MOVWF

PMDATL,W

PROG_DATA_LO

PMDATH,W

PROG_DATA_HI

; Get LSB of word

; Store in user location

; Get MSB of word

; Store in user location

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 81

PIC16LF1902/3

10.2.2

FLASH MEMORY UNLOCK

SEQUENCE

The unlock sequence is a mechanism that protects the

Flash program memory from unintended self-write programming or erasing. The sequence must be executed and completed without interruption to successfully complete any of the following operations:

• Row Erase

• Load program memory write latches

• Write of program memory write latches to program memory

• Write of program memory write latches to User

IDs

The unlock sequence consists of the following steps:

1. Write 55h to PMCON2

2. Write AAh to PMCON2

3. Set the WR bit in PMCON1

4.

NOP

instruction

5.

NOP

instruction

Once the WR bit is set, the processor will always force two

NOP

instructions. When an Erase Row or Program

Row operation is being performed, the processor will stall internal operations (typical 2 ms), until the operation is complete and then resume with the next instruction.

When the operation is loading the program memory write latches, the processor will always force the two

NOP instructions and continue uninterrupted with the next instruction.

Since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed.

FIGURE 10-3: FLASH PROGRAM

MEMORY UNLOCK

SEQUENCE FLOWCHART

Start

Unlock Sequence

Write 055h to

PMCON2

Write 0AAh to

PMCON2

Initiate

Write or Erase Operation

(WR =

1

)

Instruction Fetched ignored

NOP

execution forced

Instruction Fetched ignored

NOP

execution forced

End

Unlock Sequence

DS41455B-page 82

Preliminary

2011 Microchip Technology Inc.

10.2.3

ERASING FLASH PROGRAM

MEMORY

While executing code, program memory can only be erased by rows. To erase a row:

1.

2.

3.

4.

5.

Load the PMADRH:PMADRL register pair with any address within the row to be erased.

Clear the CFGS bit of the PMCON1 register.

Set the FREE and WREN bits of the PMCON1 register.

Write 55h, then AAh, to PMCON2 (Flash programming unlock sequence).

Set control bit WR of the PMCON1 register to begin the erase operation.

See Example 10-2

.

After the “

BSF PMCON1,WR

” instruction, the processor requires two cycles to set up the erase operation. The user must place two

NOP

instructions after the WR bit is set. The processor will halt internal operations for the typical 2 ms erase time. This is not Sleep mode as the clocks and peripherals will continue to run. After the erase cycle, the processor will resume operation with the third instruction after the PMCON1

WRITE

instruction.

PIC16LF1902/3

FIGURE 10-4: FLASH PROGRAM

MEMORY ERASE

FLOWCHART

Start

Erase Operation

Disable Interrupts

(GIE =

0

)

Select

Program or Configuration Memory

(CFGS)

Select Row Address

(PMADRH:PMADRL)

Select Erase Operation

(FREE =

1

)

Enable Write/Erase Operation

(WREN =

1

)

Unlock Sequence

CPU stalls while

Erase operation completes

(2ms typical)

Disable Write/Erase Operation

(WREN =

0

)

Re-enable Interrupts

(GIE =

1

)

End

Erase Operation

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 83

PIC16LF1902/3

EXAMPLE 10-2: ERASING ONE ROW OF PROGRAM MEMORY

; This row erase routine assumes the following:

; 1. A valid address within the erase row is loaded in ADDRH:ADDRL

; 2. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)

BCF

BANKSEL

MOVF

MOVWF

MOVF

MOVWF

BCF

BSF

BSF

INTCON,GIE

PMADRL

ADDRL,W

PMADRL

ADDRH,W

PMADRH

PMCON1,CFGS

PMCON1,FREE

PMCON1,WREN

MOVLW

MOVWF

BSF

NOP

55h

MOVLW 0AAh

MOVWF

PMCON1,WR

NOP

BCF

BSF

PMCON1,WREN

INTCON,GIE

; Disable ints so required sequences will execute properly

; Load lower 8 bits of erase address boundary

; Load upper 6 bits of erase address boundary

; Not configuration space

; Specify an erase operation

; Enable writes

; Start of required sequence to initiate erase

;

; Set WR bit to begin erase

; NOP instructions are forced as processor starts

; row erase of program memory.

;

; The processor stalls until the erase process is complete

; after erase processor continues with 3rd instruction

; Disable writes

; Enable interrupts

DS41455B-page 84

Preliminary

2011 Microchip Technology Inc.

10.2.4

WRITING TO FLASH PROGRAM

MEMORY

Program memory is programmed using the following steps:

1.

2.

3.

4.

Load the address in PMADRH:PMADRL of the row to be programmed.

Load each write latch with data.

Initiate a programming operation.

Repeat steps 1 through 3 until all data is written.

Before writing to program memory, the word(s) to be written must be erased or previously unwritten. Program memory can only be erased one row at a time. No automatic erase occurs upon the initiation of the write.

Program memory can be written one or more words at a time. The maximum number of words written at one time is equal to the number of write latches. See

Figure 10-5

(row writes to program memory with 32 write latches) for more details.

The write latches are aligned to the Flash row address boundary defined by the upper 10-bits of

PMADRH:PMADRL, (PMADRH<6:0>:PMADRL<7:5>) with the lower 5-bits of PMADRL, (PMADRL<4:0>) determining the write latch being loaded. Write operations do not cross these boundaries. At the completion of a program memory write operation, the data in the write latches is reset to contain 0x3FFF.

PIC16LF1902/3

The following steps should be completed to load the write latches and program a row of program memory.

These steps are divided into two parts. First, each write latch is loaded with data from the PMDATH:PMDATL using the unlock sequence with LWLO =

1

. When the last word to be loaded into the write latch is ready, the

LWLO bit is cleared and the unlock sequence executed. This initiates the programming operation, writing all the latches into Flash program memory.

Note:

The special unlock sequence is required to load a write latch with data or initiate a

Flash programming operation. If the unlock sequence is interrupted, writing to the latches or program memory will not be initiated.

1.

2.

3.

4.

5.

6.

7.

8.

9.

Set the WREN bit of the PMCON1 register.

Clear the CFGS bit of the PMCON1 register.

Set the LWLO bit of the PMCON1 register.

When the LWLO bit of the PMCON1 register is

1

’, the write sequence will only load the write latches and will not initiate the write to Flash program memory.

Load the PMADRH:PMADRL register pair with the address of the location to be written.

Load the PMDATH:PMDATL register pair with the program memory data to be written.

Execute the unlock sequence (

Section 10.2.2

“Flash Memory Unlock Sequence”

). The write latch is now loaded.

Increment the PMADRH:PMADRL register pair to point to the next location.

Repeat steps 5 through 7 until all but the last write latch has been loaded.

Clear the LWLO bit of the PMCON1 register.

When the LWLO bit of the PMCON1 register is

0

’, the write sequence will initiate the write to

Flash program memory.

10. Load the PMDATH:PMDATL register pair with the program memory data to be written.

11. Execute the unlock sequence (

Section 10.2.2

“Flash Memory Unlock Sequence”

). The

entire program memory latch content is now written to Flash program memory.

Note:

The program memory write latches are reset to the blank state (0x3FFF) at the completion of every write or erase operation. As a result, it is not necessary to load all the program memory write latches. Unloaded latches will remain in the blank state.

An example of the complete write sequence is shown in

Example 10-3

. The initial address is loaded into the

PMADRH:PMADRL register pair; the data is loaded using indirect addressing.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 85

FIGURE 10-5: BLOCK WRITES TO FLASH PROGRAM MEMORY WITH 32 WRITE LATCHES

7 6 0 7 5 4 0

r9 r8

PMADRH r7 r6 r5 r4 r3 r2

PMADRL r1 r0 c4 c3 c2 c1 c0

7 5 0 7 0

-

PMDATH PMDATL

6 8

10 5

PMADRL<4:0>

Program Memory Write Latches

14 14

Write Latch #0

00h

Write Latch #1

01h

14 14

CFGS =

0

Row

000h

001h

002h

Addr

0000h

0020h

0040h

Addr

0001h

0021h

0041h

14

14

14

Addr

001Eh

003Eh

005Eh

Addr

001Fh

003Fh

005Fh

14

Write Latch #30

1Eh

Write Latch #31

1Fh

14

PMADRH<6:0>

:PMADRL<7:5>

Row

Address

Decode

3FEh

3FFh

7FC0h

7FE0h

7FC1h

7FE1h

Flash Program Memory

7FDEh

7FFEh

CFGS =

1

400h 8000h - 8003h

USER ID 0 - 3

8004h - 8005h reserved

8006h

DEVICEID

REVID

8007h – 8008h

Configuration

Words

Configuration Memory

7FDFh

7FFFh

8009h - 801Fh reserved

PIC16LF1902/3

FIGURE 10-6: FLASH PROGRAM MEMORY WRITE FLOWCHART

Start

Write Operation

Determine number of words to be written into Program or

Configuration Memory.

The number of words cannot exceed the number of words per row.

(word_cnt)

Enable Write/Erase

Operation (WREN =

1

)

Load the value to write

(PMDATH:PMDATL)

Update the word counter

(word_cnt--)

Write Latches to Flash

(LWLO =

0

)

Disable Interrupts

(GIE =

0

)

Select

Program or Config. Memory

(CFGS)

Select Row Address

(PMADRH:PMADRL)

Select Write Operation

(FREE =

0

)

Load Write Latches Only

(LWLO =

1

)

Last word to write ?

Yes

No

Unlock Sequence

No delay when writing to

Program Memory Latches

Increment Address

(PMADRH:PMADRL++)

Unlock Sequence

CPU stalls while Write operation completes

(2 ms typical)

Disable

Write/Erase Operation

(WREN =

0

)

Re-enable Interrupts

(GIE =

1

)

End

Erase Operation

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 87

PIC16LF1902/3

EXAMPLE 10-3: WRITING TO FLASH PROGRAM MEMORY

; This write routine assumes the following:

; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR

; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,

; stored in little endian format

; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL

; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)

;

BCF

BANKSEL

MOVF

MOVWF

MOVF

MOVWF

MOVLW

MOVWF

MOVLW

MOVWF

BCF

BSF

BSF

INTCON,GIE

PMADRH

ADDRH,W

; Disable ints so required sequences will execute properly

; Bank 3

; Load initial address

PMADRH ;

ADDRL,W ;

PMADRL ;

LOW DATA_ADDR ; Load initial data address

FSR0L ;

HIGH DATA_ADDR ; Load initial data address

FSR0H ;

PMCON1,CFGS

PMCON1,WREN

PMCON1,LWLO

; Not configuration space

; Enable writes

; Only Load Write Latches

LOOP

MOVIW

MOVWF

MOVIW

MOVWF

FSR0++ ; Load first data byte into lower

PMDATL ;

FSR0++ ; Load second data byte into upper

PMDATH ;

MOVF

XORLW

ANDLW

BTFSC

GOTO

PMADRL,W

0x1F

; Check if lower bits of address are '00000'

; Check if we're on the last of 32 addresses

0x1F ;

STATUS,Z ; Exit if last of 32 words,

START_WRITE ;

MOVLW

MOVWF

MOVLW 0AAh

MOVWF PMCON2

BSF

NOP

55h

PMCON2

PMCON1,WR

; Start of required write sequence:

; Write 55h

;

; Write AAh

; Set WR bit to begin write

; NOP instructions are forced as processor

; loads program memory write latches

NOP ;

INCF

GOTO

START_WRITE

BCF

PMADRL,F

LOOP

PMCON1,LWLO

; Still loading latches Increment address

; Write next latches

; No more loading latches - Actually start Flash program

; memory write

MOVLW

MOVWF

MOVLW

MOVWF

BSF

NOP

NOP

BCF

BSF

55h

PMCON2

; Start of required write sequence:

; Write 55h

0AAh ;

PMCON2 ; Write AAh

PMCON1,WR ; Set WR bit to begin write

; NOP instructions are forced as processor writes

; all the program memory write latches simultaneously

; to program memory.

; After NOPs, the processor

; stalls until the self-write process in complete

PMCON1,WREN

INTCON,GIE

; after write processor continues with 3rd instruction

; Disable writes

; Enable interrupts

DS41455B-page 88

Preliminary

2011 Microchip Technology Inc.

10.3

Modifying Flash Program Memory

When modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a RAM image. Program memory is modified using the following steps:

1.

2.

3.

4.

5.

6.

7.

Load the starting address of the row to be modified.

Read the existing data from the row into a RAM image.

Modify the RAM image to contain the new data to be written into program memory.

Load the starting address of the row to be rewritten.

Erase the program memory row.

Load the write latches with data from the RAM image.

Initiate a programming operation.

FIGURE 10-7:

PIC16LF1902/3

FLASH PROGRAM

MEMORY MODIFY

FLOWCHART

Start

Modify Operation

Read Operation

An image of the entire row read must be stored in RAM

Modify Image

The words to be modified are changed in the RAM image

Erase Operation

Write Operation use RAM image

End

Modify Operation

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 89

PIC16LF1902/3

10.4

User ID, Device ID and

Configuration Word Access

Instead of accessing program memory, the user ID’s,

Device ID/Revision ID and Configuration Words can be accessed when CFGS =

1

in the PMCON1 register.

This is the region that would be pointed to by

PC<15> =

1

, but not all addresses are accessible.

Different access may exist for reads and writes. Refer

to Table 10-2

.

When read access is initiated on an address outside the parameters listed in

Table 10-2

, the

PMDATH:PMDATL register pair is cleared, reading back ‘

0

’s.

TABLE 10-2: USER ID, DEVICE ID AND CONFIGURATION WORD ACCESS (CFGS =

1

)

Address

8000h-8003h

8006h

8007h-8008h

Function

User IDs

Device ID/Revision ID

Configuration Words 1 and 2

Read Access

Yes

Yes

Yes

Write Access

Yes

No

No

EXAMPLE 10-4: CONFIGURATION WORD AND DEVICE ID ACCESS

* This code block will read 1 word of program memory at the memory address:

* PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;

* PROG_DATA_HI, PROG_DATA_LO

BANKSEL

MOVLW

MOVWF

CLRF

BSF

BCF

BSF

NOP

NOP

BSF

PMADRL

PROG_ADDR_LO

PMADRL

PMADRH

PMCON1,CFGS

INTCON,GIE

PMCON1,RD

INTCON,GIE

MOVF

MOVWF

MOVF

MOVWF

PMDATL,W

PROG_DATA_LO

PMDATH,W

PROG_DATA_HI

; Select correct Bank

;

; Store LSB of address

; Clear MSB of address

; Select Configuration Space

; Disable interrupts

; Initiate read

; Executed (See Figure 10-2

)

; Ignored (See

Figure 10-2

)

; Restore interrupts

; Get LSB of word

; Store in user location

; Get MSB of word

; Store in user location

DS41455B-page 90

Preliminary

2011 Microchip Technology Inc.

10.5

Write Verify

It is considered good programming practice to verify that program memory writes agree with the intended value.

Since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in RAM after the last write is complete.

FIGURE 10-8: FLASH PROGRAM

MEMORY VERIFY

FLOWCHART

Start

Verify Operation

This routine assumes that the last row of data written was from an image saved in RAM. This image will be used to verify the data currently stored in

Flash Program Memory.

Read Operation

PMDAT =

RAM image

?

Yes

No

Fail

Verify Operation

No

Last

Word ?

Yes

End

Verify Operation

PIC16LF1902/3

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 91

PIC16LF1902/3

10.6

Flash Program Memory Control Registers

REGISTER 10-1:

R/W-x/u

PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER

R/W-x/u R/W-x/u R/W-x/u R/W-x/u

PMDAT<7:0>

R/W-x/u R/W-x/u bit 7

R/W-x/u bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

PMDAT<7:0>

: Read/write value for Least Significant bits of program memory

REGISTER 10-2: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER

U-0

U-0

R/W-x/u R/W-x/u R/W-x/u R/W-x/u

PMDAT<13:8>

R/W-x/u bit 7

R/W-x/u bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-6

Unimplemented:

Read as ‘

0

’ bit 5-0

PMDAT<13:8>

: Read/write value for Most Significant bits of program memory

REGISTER 10-3: PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

PMADR<7:0>

R/W-0/0 R/W-0/0 bit 7

R/W-0/0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

PMADR<7:0>

: Specifies the Least Significant bits for program memory address

REGISTER 10-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER

U-1

R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0

PMADR<14:8>

R/W-0/0 R/W-0/0 bit 7

R/W-0/0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

Unimplemented:

Read as ‘

1

PMADR<14:8>

: Specifies the Most Significant bits for program memory address

DS41455B-page 92

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

REGISTER 10-5:

bit 7

U-1

(1)

PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER

R/W-0/0

CFGS

R/W-0/0

LWLO

R/W/HC-0/0

FREE

R/W/HC-x/q

(2)

WRERR

R/W-0/0

WREN

R/S/HC-0/0

WR

R/S/HC-0/0

RD bit 0

Legend:

R = Readable bit

S = Bit can only be set

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HC = Bit is cleared by hardware bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

Note 1:

2:

3:

Unimplemented:

Read as ‘

1

CFGS:

Configuration Select bit

1

= Access configuration, user ID and device ID registers

0

= Access Flash program memory

LWLO:

Load Write Latches Only bit

(3)

1

= Only the addressed program memory write latch is loaded/updated on the next WR command

0

= The addressed program memory write latch is loaded/updated and a write of all program memory write latches will be initiated on the next WR command

FREE:

Program Flash Erase Enable bit

1

= Performs an erase operation on the next WR command (hardware cleared upon completion)

0

= Performs an write operation on the next WR command

WRERR:

Program/Erase Error Flag bit

1

= Condition indicates an improper program or erase sequence attempt or termination (bit is set automatically on any set attempt (write ‘

1

’) of the WR bit).

0

= The program or erase operation completed normally.

WREN:

Program/Erase Enable bit

1

= Allows program/erase cycles

0

= Inhibits programming/erasing of program Flash

WR:

Write Control bit

1

= Initiates a program Flash program/erase operation.

The operation is self-timed and the bit is cleared by hardware once operation is complete.

The WR bit can only be set (not cleared) in software.

0

= Program/erase operation to the Flash is complete and inactive.

RD:

Read Control bit

1

= Initiates a program Flash read. Read takes one cycle. RD is cleared in hardware. The RD bit can only be set

(not cleared) in software.

0

= Does not initiate a program Flash read.

Unimplemented bit, read as ‘

1

’.

The WRERR bit is automatically set by hardware when a program memory write or erase operation is started (WR =

1

).

The LWLO bit is ignored during a program memory erase operation (FREE =

1

).

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 93

PIC16LF1902/3

REGISTER 10-6:

bit 7

W-0/0

PMCON2: PROGRAM MEMORY CONTROL 2 REGISTER

W-0/0 W-0/0 W-0/0 W-0/0

Program Memory Control Register 2

W-0/0 W-0/0 W-0/0 bit 0

Legend:

R = Readable bit

S = Bit can only be set

‘1’ = Bit is set bit 7-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

Flash Memory Unlock Pattern bits

To unlock writes, a 55h must be written first, followed by an AAh, before setting the WR bit of the

PMCON1 register. The value written to this register is used to unlock the writes. There are specific timing requirements on these writes.

TABLE 10-3: SUMMARY OF REGISTERS ASSOCIATED WITH FLASH PROGRAM MEMORY

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PMCON1

PMCON2

PMADRL

PMADRH

PMDATL

PMDATH

INTCON

Legend:

CFGS LWLO FREE WRERR WREN

Program Memory Control Register 2

PMADRL<7:0>

WR RD

— PMADRH<6:0>

PMDATL<7:0>

GIE

PEIE TMR0IE INTE

PMDATH<5:0>

IOCIE TMR0IF INTF IOCIF

= unimplemented location, read as ‘

0

’. Shaded cells are not used by Flash program memory module.

Register on

Page

92

92

66

93

94

92

92

TABLE 10-4:

Name

CONFIG1

CONFIG2

Legend:

Bits

SUMMARY OF CONFIGURATION WORD WITH FLASH PROGRAM MEMORY

Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

Register on Page

13:8

7:0

CP

MCLRE

FCMEN

PWRTE

IESO CLKOUTEN

WDTE<1:0>

BOREN<1:0>

13:8 — — LVP DEBUG LPBOR BORV

7:0 — — — — — —

— = unimplemented location, read as ‘

0

’. Shaded cells are not used by clock sources.

FOSC<2:0>

STVREN

WRT<1:0>

46

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11.0

I/O PORTS

In general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output.

However, the pin can still be read.

Each port has three standard registers for its operation.

These registers are:

• TRISx registers (data direction)

• PORTx registers (reads the levels on the pins of the device)

• LATx registers (output latch)

Some ports may have one or more of the following additional registers. These registers are:

• ANSELx (analog select)

• WPUx (weak pull-up)

TABLE 11-1: PORT AVAILABILITY PER

DEVICE

Device

PIC16LF1902/3

The Data Latch (LATA register) is useful for read-modify-write operations on the value that the I/O pins are driving.

A write operation to the LATA register has the same effect as a write to the corresponding PORTA register.

A read of the LATA register reads of the values held in the I/O PORT latches, while a read of the PORTA register reads the actual I/O pin value.

Ports that support analog inputs have an associated

ANSELx register. When an ANSEL bit is set, the digital input buffer associated with that bit is disabled.

Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in

Figure 11-1 .

FIGURE 11-1:

PIC16LF1902/3

GENERIC I/O PORT

OPERATION

Read LATx

TRISx

D Q

Write LATx

Write PORTx

CK

Data Register

Data Bus

Read PORTx

To peripherals

ANSELx

V

DD

V

SS

I/O pin

EXAMPLE 11-1: INITIALIZING PORTA

; This code example illustrates

; initializing the PORTA register. The

; other ports are initialized in the same

; manner.

BANKSEL

CLRF

BANKSEL

CLRF

PORTA

PORTA

LATA

LATA

;

;Init PORTA

;Data Latch

;

; BANKSEL ANSELA

CLRF ANSELA

BANKSEL

MOVLW

MOVWF

TRISA

TRISA

;

B'00111000' ;Set RA<5:3> as inputs

;and set RA<2:0> as

;outputs

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PIC16LF1902/3

11.1

PORTA Registers

PORTA is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISA

(

Register 11-2 ). Setting a TRISA bit (=

1

) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (=

0

) will make the corresponding PORTA pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). The exception is RA3, which is input only and its TRIS bit will always read as ‘

1

’.

Example 11-1 shows how to initialize PORTA.

Reading the PORTA register ( Register 11-1 ) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATA).

The TRISA register (

Register 11-2 ) controls the

PORTA pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘

0

’.

11.1.1

ANSELA REGISTER

The ANSELA register ( Register 11-4

) is used to configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELA bit high will cause all digital reads on the pin to be read as ‘

0

’ and allow analog functions on the pin to operate correctly.

The state of the ANSELA bits has no effect on digital output functions. A pin with TRIS clear and ANSEL set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port.

Note:

The ANSELA bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘

0

’ by user software.

11.1.2

PORTA FUNCTIONS AND OUTPUT

PRIORITIES

Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities

are shown in Table 11-2 .

When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority.

Analog input functions, such as ADC, comparator and

CapSense inputs, are not shown in the priority lists.

These inputs are active when the I/O pin is set for

Analog mode using the ANSELx registers. Digital output functions may control the pin when it is in Analog

mode with the priority shown in Table 11-2

.

TABLE 11-2:

Pin Name

PORTA OUTPUT PRIORITY

Function Priority

(1)

RA0

RA1

RA2

RA3

SEG12 (LCD)

AN0

RA0

SEG7

AN1

RA1

COM2

AN2

RA2

V

REF

+

COM3

SEG15

AN3

RA3

RA4

RA5

SEG4

T0CKI

RA4

SEG6

AN5

RA5

Note 1:

RA6

RA7

CLKOUT

SEG1

RA6

CLKIN

SEG2

RA7

Priority listed from highest to lowest.

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PIC16LF1902/3

REGISTER 11-1:

bit 7

R/W-x/x

RA7

PORTA: PORTA REGISTER

R/W-x/x

RA6

R/W-x/x

RA5

R/W-x/x

RA4

R-x/x

RA3

R/W-x/x

RA2

R/W-x/x

RA1

R/W-x/x

RA0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

RA<7:0>

: PORTA I/O Value bits

(1)

1

= Port pin is > V

IH

0

= Port pin is < V

IL

Note 1:

Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values.

REGISTER 11-2:

R/W-1/1

TRISA7 bit 7

TRISA: PORTA TRI-STATE REGISTER

R/W-1/1

TRISA6

R/W-1/1

TRISA5

R/W-1/1

TRISA4

R-1/1

TRISA3

R/W-1/1

TRISA2

R/W-1/1

TRISA1

R/W-1/1

TRISA0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-4 bit 3 bit 2-0

TRISA<7:4>:

PORTA Tri-State Control bits

1

= PORTA pin configured as an input (tri-stated)

0

= PORTA pin configured as an output

TRISA3:

RA3 Port Tri-State Control bit

This bit is always ‘

1

’ as RA3 is an input only

TRISA<2:0>:

PORTA Tri-State Control bits

1

= PORTA pin configured as an input (tri-stated)

0

= PORTA pin configured as an output

REGISTER 11-3:

bit 7

R/W-x/u

LATA7

LATA: PORTA DATA LATCH REGISTER

R/W-x/u

LATA6

R/W-x/u

LATA5

R/W-x/u

LATA4

R/W-x/u

LATA3

R/W-x/u

LATA2

R/W-x/u

LATA1

R/W-x/u

LATA0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-4

LATA<7:0>

: PORTA Output Latch Value bits

(1)

Note 1:

Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return of actual I/O pin values.

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PIC16LF1902/3

REGISTER 11-4:

bit 7

U-0

ANSELA: PORTA ANALOG SELECT REGISTER

U-0

R/W-1/1

ANSA5

U-0

R/W-1/1

ANSA3

R/W-1/1

ANSA2

R/W-1/1

ANSA1

R/W-1/1

ANSA0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-6 bit 5 bit 4 bit 3-0

Unimplemented:

Read as ‘

0

ANSA5

: Analog Select between Analog or Digital Function on pins RA5, respectively

0

= Digital I/O. Pin is assigned to port or digital special function.

1

= Analog input. Pin is assigned as analog input

(1)

. Digital input buffer disabled.

Unimplemented:

Read as ‘

0

ANSA<3:0>

: Analog Select between Analog or Digital Function on pins RA<3:0>, respectively

0

= Digital I/O. Pin is assigned to port or digital special function.

1

= Analog input. Pin is assigned as analog input

(1)

. Digital input buffer disabled.

Note 1:

When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin.

TABLE 11-3: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register on Page

ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0

LATA

OPTION_REG

PORTA

TRISA

Legend:

LATA7

WPUEN

RA7

TRISA7

LATA6

INTEDG

RA6

TRISA6

LATA5

TMR0CS

RA5

TRISA5

LATA4

TMR0SE

RA4

TRISA4

LATA3

PSA

RA3

TRISA3

LATA2

RA2

TRISA2

LATA1

PS<2:0>

RA1

TRISA1

LATA0

RA0

TRISA0 x

= unknown, u

= unchanged, – = unimplemented locations read as ‘

0

’. Shaded cells are not used by PORTA.

98

97

131

97

97

TABLE 11-4: SUMMARY OF CONFIGURATION WORD WITH PORTA

Name Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0

CONFIG1

Legend:

13:8 — — — — CLKOUTEN

7:0 CP MCLRE PWRTE WDTE<1:0>

— = unimplemented location, read as ‘

0

’. Shaded cells are not used by PORTA.

BOREN<1:0>

FOSC<1:0>

Register on Page

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11.2

PORTB Registers

PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB

(

Register 11-6

). Setting a TRISB bit (=

1

) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode).

Clearing a TRISB bit (=

0

) will make the corresponding

PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).

Example 11-1 shows how to initialize an I/O port.

Reading the PORTB register ( Register 11-5 ) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATB).

The TRISB register (

Register 11-6

) controls the PORTB pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the

TRISB register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘

0

’.

11.2.1

ANSELB REGISTER

The ANSELB register ( Register 11-8

) is used to configure the Input mode of an I/O pin to analog.

Setting the appropriate ANSELB bit high will cause all digital reads on the pin to be read as ‘

0

’ and allow analog functions on the pin to operate correctly.

The state of the ANSELB bits has no effect on digital output functions. A pin with TRIS clear and ANSELB set will still operate as a digital output, but the Input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port.

Note:

The ANSELB bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘

0

’ by user software.

PIC16LF1902/3

11.2.2

PORTB FUNCTIONS AND OUTPUT

PRIORITIES

Each PORTB pin is multiplexed with other functions. The pins, their combined functions and their output priorities

are shown in Table 11-5 .

When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority.

Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output.

Certain digital input functions override other port functions and are included in

Table 11-5 .

TABLE 11-5:

Pin Name

PORTB OUTPUT PRIORITY

Function Priority

(1)

RB0

RB1

RB2

RB3

RB4

RB5

COM0

AN11

IOC

RB4

COM1

AN13

IOC

RB5

SEG25

AN8

VLCD2

IOC

RB2

SEG26

AN9

VLCD3

IOC

RB3

SEG0

AN12

INT

IOC

RB0

SEG24

AN10

VLCD1

IOC

RB1

Note 1:

RB6

RB7

SEG14

IOC

RB6

SEG13

IOC

RB7

Priority listed from highest to lowest.

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REGISTER 11-5:

R/W-x/u

RB7 bit 7

PORTB: PORTB REGISTER

R/W-x/u

RB6

R/W-x/u

RB5

R/W-x/u

RB4

R/W-x/u

RB3

R/W-x/u

RB2

R/W-x/u

RB1

R/W-x/u

RB0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

Note 1:

RB<7:0>

: PORTB General Purpose I/O Pin bits

(1)

1

= Port pin is > V

IH

0

= Port pin is < V

IL

Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values.

REGISTER 11-6:

R/W-1/1

TRISB7 bit 7

TRISB: PORTB TRI-STATE REGISTER

R/W-1/1

TRISB6

R/W-1/1

TRISB5

R/W-1/1

TRISB4

R/W-1/1

TRISB3

R/W-1/1

TRISB2

R/W-1/1

TRISB1

R/W-1/1

TRISB0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

TRISB<7:0>:

PORTB Tri-State Control bits

1

= PORTB pin configured as an input (tri-stated)

0

= PORTB pin configured as an output

REGISTER 11-7:

R/W-x/u

LATB7 bit 7

LATB: PORTB DATA LATCH REGISTER

R/W-x/u

LATB6

R/W-x/u

LATB5

R/W-x/u

LATB4

R/W-x/u

LATB3

R/W-x/u

LATB2

R/W-x/u

LATB1

R/W-x/u

LATB0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

LATB<7:0>

: PORTB Output Latch Value bits

(1)

Note 1:

Writes to PORTB are actually written to corresponding LATB register. Reads from PORTB register is return of actual I/O pin values.

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PIC16LF1902/3

REGISTER 11-8:

bit 7

U-0

ANSELB: PORTB ANALOG SELECT REGISTER

U-0

R/W-1/1

ANSB5

R/W-1/1

ANSB4

R/W-1/1

ANSB3

R/W-1/1

ANSB2

R/W-1/1

ANSB1

R/W-1/1

ANSB0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-6 bit 5-0

Note 1:

Unimplemented:

Read as ‘

0

ANSB<5:0>

: Analog Select between Analog or Digital Function on pins RB<5:0>, respectively

0

= Digital I/O. Pin is assigned to port or digital special function.

1

= Analog input. Pin is assigned as analog input

(1)

. Digital input buffer disabled.

When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin.

REGISTER 11-9:

bit 7

R/W-1/1

WPUB7

WPUB: WEAK PULL-UP PORTB REGISTER

R/W-1/1

WPUB6

R/W-1/1

WPUB5

R/W-1/1

WPUB4

R/W-1/1

WPUB3

R/W-1/1

WPUB2

R/W-1/1

WPUB1

R/W-1/1

WPUB0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

Note 1:

2:

WPUB<7:0>

: Weak Pull-up Register bits

1

= Pull-up enabled

0

= Pull-up disabled

Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.

The weak pull-up device is automatically disabled if the pin is in configured as an output.

TABLE 11-6:

Name

ANSELB

LATB

PORTB

TRISB

WPUB

Legend:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

LATB7

RB7

LATB6

RB6

ANSB5

LATB5

RB5

ANSB4

LATB4

RB4

ANSB3

LATB3

RB3

ANSB2

LATB2

RB2

ANSB1

LATB1

RB1

ANSB0

LATB0

RB0

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 x = unknown, u = unchanged, - = unimplemented locations read as ‘

0

’. Shaded cells are not used by PORTB.

WPUB0

Register on Page

101

100

100

100

101

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PIC16LF1902/3

11.3

PORTC Registers

PORTC is an 8-bit wide bidirectional port. The corresponding data direction register is TRISC

(

Register 11-6

). Setting a TRISC bit (=

1

) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode).

Clearing a TRISC bit (=

0

) will make the corresponding

PORTC pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).

Example 11-1 shows how to initialize an I/O port.

Reading the PORTC register (

Register 11-5 ) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, this value is modified and then written to the PORT data latch (LATC).

The TRISC register (

Register 11-6

) controls the PORTC pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the

TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘

0

’.

11.3.1

PORTC FUNCTIONS AND OUTPUT

PRIORITIES

Each PORTC pin is multiplexed with other functions. The pins, their combined functions and their output priorities

are shown in Table 11-7 .

When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority.

Analog input and some digital input functions are not included in the list below. These input functions can remain active when the pin is configured as an output.

Certain digital input functions override other port functions and are included in

Table 11-7 .

TABLE 11-7:

Pin Name

PORTC OUTPUT PRIORITY

Function Priority

(1)

RC0

RC1

SOSCO (T1OSCO)

T1CKI

RC0

SOSC1 (T1OSCI)

RC1

RC2

RC3

RC4

RC5

SEG2

RC2

SEG6

RC3

SEG11

T1G

RC4

SEG10

RC5

Note 1:

RC6

RC7

SEG9

RC6

SEG8

RC7

Priority listed from highest to lowest.

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PIC16LF1902/3

REGISTER 11-10: PORTC: PORTC REGISTER

R/W-x/u

RC7 bit 7

R/W-x/u

RC6

R/W-x/u

RC5

R/W-x/u

RC4

R/W-x/u

RC3

R/W-x/u

RC2

R/W-x/u

RC1

R/W-x/u

RC0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

Note 1:

RC<7:0>

: PORTC General Purpose I/O Pin bits

(1)

1

= Port pin is > V

IH

0

= Port pin is < V

IL

Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values.

REGISTER 11-11: TRISC: PORTC TRI-STATE REGISTER

R/W-1/1

TRISC7 bit 7

R/W-1/1

TRISC6

R/W-1/1

TRISC5

R/W-1/1

TRISC4

R/W-1/1

TRISC3

R/W-1/1

TRISC2

R/W-1/1

TRISC1

R/W-1/1

TRISC0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

TRISC<7:0>:

PORTC Tri-State Control bits

(1)

1

= PORTC pin configured as an input (tri-stated)

0

= PORTC pin configured as an output

REGISTER 11-12: LATC: PORTC DATA LATCH REGISTER

R/W-x/u

LATC7 bit 7

R/W-x/u

LATC6

R/W-x/u

LATC5

R/W-x/u

LATC4

R/W-x/u

LATC3

R/W-x/u

LATC2

R/W-x/u

LATC1

R/W-x/u

LATC0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

LATC<7:0>

: PORTC Output Latch Value bits

(1)

Note 1:

Writes to PORTC are actually written to corresponding LATC register. Reads from PORTC register is return of actual I/O pin values.

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PIC16LF1902/3

TABLE 11-8:

Name

LATC

PORTC

TRISC

Legend:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0

RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 x = unknown, u = unchanged, - = unimplemented locations read as ‘

0

’. Shaded cells are not used by PORTC.

Register on Page

100

100

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11.4

PORTE Registers

RE3 is input only, and also functions as MCLR. The

MCLR feature can be disabled via a configuration fuse.

RE3 also supplies the programming voltage. The TRIS bit for RE3 (TRISE3) always reads ‘

1

’.

PIC16LF1902/3

11.4.1

PORTE FUNCTIONS AND OUTPUT

PRIORITIES

No output priorities, RE3 is an input only pin.

REGISTER 11-13: PORTE: PORTE REGISTER

bit 7

U-0

U-0

U-0

U-0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

R-x/u

RE3

U-0

U-0

U-0

— bit 0

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-4 bit 3 bit 2-0

Unimplemented

: Read as ‘

0

RE3

: PORTE Input Pin bit

1

= Port pin is > V

IH

0

= Port pin is < V

IL

Unimplemented

: Read as ‘

0

REGISTER 11-14: TRISE: PORTE TRI-STATE REGISTER

U-0

U-0

U-0

U-0

U-1

(1)

— bit 7

Legend:

R = Readable bit u = bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared bit 7-4 bit 3 bit 2-0

Unimplemented

: Read as ‘

0

Unimplemented

: Read as ‘

1

Unimplemented

: Read as ‘

0

Note 1:

Unimplemented, read as ‘

1

’.

U-0

U-0

U-0

— bit 0

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

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REGISTER 11-15: WPUE: WEAK PULL-UP PORTE REGISTER

bit 7

U-0

U-0

U-0

U-0

R/W-1/1

WPUE3

U-0

U-0

U-0

— bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-4 bit 3 bit 2-0

Note 1:

2:

Unimplemented:

Read as ‘

0

WPUE:

Weak Pull-up Register bit

1

= Pull-up enabled

0

= Pull-up disabled

Unimplemented:

Read as ‘

0

Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.

The weak pull-up device is automatically disabled if the pin is in configured as an output.

TABLE 11-9: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register on Page

ADCON0

PORTE

TRISE

WPUE

Legend:

Note 1:

— — —

CHS<4:0>

— RE3

(1)

GO/DONE

ADON

121

105

— — — — — — —

105

— — — — WPUE3 — — —

106

x

= unknown, u

= unchanged, – = unimplemented locations read as ‘

0

’. Shaded cells are not used by

PORTE.

Unimplemented, read as ‘

1

’.

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PIC16LF1902/3

12.0

12.2

INTERRUPT-ON-CHANGE

The PORTB pins can be configured to operate as

Interrupt-On-Change (IOC) pins. An interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. Any individual PORTB pin, or combination of PORTB pins, can be configured to generate an interrupt. The interrupt-on-change module has the following features:

• Interrupt-on-Change enable (Master Switch)

• Individual pin configuration

• Rising and falling edge detection

• Individual pin interrupt flags

Figure 12-1 is a block diagram of the IOC module.

12.1

Enabling the Module

To allow individual PORTB pins to generate an interrupt, the IOCIE bit of the INTCON register must be set. If the

IOCIE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated.

Individual Pin Configuration

For each PORTB pin, a rising edge detector and a falling edge detector are present. To enable a pin to detect a rising edge, the associated IOCBPx bit of the IOCBP register is set. To enable a pin to detect a falling edge, the associated IOCBNx bit of the IOCBN register is set.

A pin can be configured to detect rising and falling edges simultaneously by setting both the IOCBPx bit and the IOCBNx bit of the IOCBP and IOCBN registers, respectively.

FIGURE 12-1:

12.3

Interrupt Flags

The IOCBFx bits located in the IOCBF register are status flags that correspond to the Interrupt-on-change pins of PORTB. If an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set. The IOCIF bit of the INTCON register reflects the status of all IOCBFx bits.

12.4

Clearing Interrupt Flags

The individual status flags, (IOCBFx bits), can be cleared by resetting them to zero. If another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written.

In order to ensure that no detected edge is lost while clearing flags, only AND operations masking out known changed bits should be performed. The following sequence is an example of what should be performed.

EXAMPLE 12-1:

MOVLW

XORWF

ANDWF

0xff

IOCBF, W

IOCBF, F

12.5

Operation in Sleep

The interrupt-on-change interrupt sequence will wake the device from Sleep mode, if the IOCIE bit is set.

If an edge is detected while in Sleep mode, the IOCBF register will be updated prior to the first instruction executed out of Sleep.

INTERRUPT-ON-CHANGE BLOCK DIAGRAM

IOCIE

IOCBNx D

CK

R

Q

IOCBFx

From all other IOCBFx individual pin detectors

RBx

IOC Interrupt to

CPU Core

IOCBPx D

CK

R

Q

Q2 Clock Cycle

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REGISTER 12-1:

R/W-0/0

IOCBP7 bit 7

IOCBP: INTERRUPT-ON-CHANGE POSITIVE EDGE REGISTER

R/W-0/0

IOCBP6

R/W-0/0

IOCBP5

R/W-0/0

IOCBP4

R/W-0/0

IOCBP3

R/W-0/0

IOCBP2

R/W-0/0

IOCBP1

R/W-0/0

IOCBP0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

IOCBP<7:0>:

Interrupt-on-Change Positive Edge Enable bits

1

= Interrupt-on-Change enabled on the pin for a positive going edge. Associated Status bit and interrupt flag will be set upon detecting an edge.

0

= Interrupt-on-Change disabled for the associated pin.

REGISTER 12-2: IOCBN: INTERRUPT-ON-CHANGE NEGATIVE EDGE REGISTER

R/W-0/0

IOCBN7 bit 7

R/W-0/0

IOCBN6

R/W-0/0

IOCBN5

R/W-0/0

IOCBN4

R/W-0/0

IOCBN3

R/W-0/0

IOCBN2

R/W-0/0

IOCBN1

R/W-0/0

IOCBN0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

IOCBN<7:0>:

Interrupt-on-Change Negative Edge Enable bits

1

= Interrupt-on-Change enabled on the pin for a negative going edge. Associated Status bit and interrupt flag will be set upon detecting an edge.

0

= Interrupt-on-Change disabled for the associated pin.

REGISTER 12-3: IOCBF: INTERRUPT-ON-CHANGE FLAG REGISTER

R/W/HS-0/0

IOCBF7 bit 7

R/W/HS-0/0

IOCBF6

R/W/HS-0/0 R/W/HS-0/0 R/W/HS-0/0

IOCBF5 IOCBF4 IOCBF3

R/W/HS-0/0

IOCBF2

R/W/HS-0/0

IOCBF1

R/W/HS-0/0

IOCBF0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HS - Bit is set in hardware

IOCBF<7:0>:

Interrupt-on-Change Flag bits

1

= An enabled change was detected on the associated pin.

Set when IOCBPx =

1

and a rising edge was detected on RBx, or when IOCBNx =

1

and a falling edge was detected on RBx.

0

= No change was detected, or the user cleared the detected change.

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PIC16LF1902/3

TABLE 12-1:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ANSELB

INTCON

IOCBF

IOCBN

IOCBP

TRISB

Legend:

— —

GIE PEIE

IOCBF7

IOCBN7

IOCBF6

IOCBN6

ANSB5

TMR0IE

IOCBF5

IOCBN5

ANSB4

INTE

IOCBF4

IOCBN4

ANSB3

IOCIE

IOCBF3

IOCBN3

ANSB2

TMR0IF

IOCBF2

IOCBN2

ANSB1

INTF

IOCBF1

IOCBN1

ANSB0

IOCIF

IOCBF0

IOCBN0

IOCBP7

TRISB7

IOCBP6

TRISB6

IOCBP5

TRISB5

IOCBP4

TRISB4

IOCBP3

TRISB3

IOCBP2

TRISB2

IOCBP1

TRISB1

IOCBP0

TRISB0

— = unimplemented location, read as ‘

0

’. Shaded cells are not used by interrupt-on-change.

Register on Page

101

66

108

108

108

100

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NOTES:

DS41455B-page 110

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

13.0

FIXED VOLTAGE REFERENCE

(FVR)

The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of V

DD

, with 1.024V or

2.048V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following:

• ADC input channel

• ADC positive reference

The FVR can be enabled by setting the FVREN bit of the FVRCON register.

FIGURE 13-1:

13.1

Independent Gain Amplifiers

The output of the FVR supplied to the ADC is routed through two independent programmable gain amplifiers. Each amplifier can be configured to amplify the reference voltage by 1x or 2x, to produce the two possible voltage levels.

The ADFVR<1:0> bits of the FVRCON register are used to enable and configure the gain amplifier settings for the reference supplied to the ADC module. Reference

Section 15.0 “Analog-to-Digital Converter

(ADC) Module”

for additional information.

13.2

FVR Stabilization Period

When the Fixed Voltage Reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. Once the circuits stabilize and are ready for use, the FVRRDY bit of the FVRCON register will be set. See

Section 21.0 “Electrical Specifications”

for the minimum delay requirement.

VOLTAGE REFERENCE BLOCK DIAGRAM

ADFVR<1:0>

2

FVR BUFFER1

(To ADC Module)

FVREN

Any peripheral requiring the Fixed Reference

(See Table 13-1

)

x1

x2

+

1.024V Fixed

Reference

FVRRDY

-

TABLE 13-1:

Peripheral

HFINTOSC

BOR

PERIPHERALS REQUIRING THE FIXED VOLTAGE REFERENCE (FVR)

Conditions

FOSC<2:0> =

100

and

IRCF<3:0> =

000x

BOREN<1:0> =

11

BOREN<1:0> =

10

and BORFS =

1

BOREN<1:0> =

01

and BORFS =

1

Description

INTOSC is active and device is not in Sleep

BOR always enabled

BOR disabled in Sleep mode, BOR Fast Start enabled.

BOR under software control, BOR Fast Start enabled

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13.3

FVR Control Registers

REGISTER 13-1:

R/W-0/0

FVREN bit 7

FVRCON: FIXED VOLTAGE REFERENCE CONTROL REGISTER

R-q/q

FVRRDY

(1)

R/W-0/0

TSEN

R/W-0/0

TSRNG

U-0

U-0

R/W-0/0 R/W-0/0

ADFVR<1:0> bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition bit 7 bit 6 bit 5 bit 4 bit 3-2 bit 1-0

FVREN:

Fixed Voltage Reference Enable bit

0

= Fixed Voltage Reference is disabled

1

= Fixed Voltage Reference is enabled

FVRRDY:

Fixed Voltage Reference Ready Flag bit

(1)

0

= Fixed Voltage Reference output is not ready or not enabled

1

= Fixed Voltage Reference output is ready for use

TSEN:

Temperature Indicator Enable bit

0

= Temperature Indicator is disabled

1

= Temperature Indicator is enabled

TSRNG:

Temperature Indicator Range Selection bit

0

= V

OUT

= V

DD

- 2V

T

(Low Range)

1

= V

OUT

= V

DD

- 4V

T

(High Range)

Unimplemented:

Read as ‘

0

ADFVR<1:0>:

ADC Fixed Voltage Reference Selection bit

00

= ADC Fixed Voltage Reference Peripheral output is off.

01

= ADC Fixed Voltage Reference Peripheral output is 1x (1.024V)

10

= ADC Fixed Voltage Reference Peripheral output is 2x (2.048V)

(2)

11

= Reserved

Note 1:

2:

FVRRDY will output the true state of the band gap.

Fixed Voltage Reference output cannot exceed V

DD

.

TABLE 13-2:

Name

FVRCON

Legend:

SUMMARY OF REGISTERS ASSOCIATED WITH FIXED VOLTAGE REFERENCE

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3

FVREN FVRRDY TSEN TSRNG

Shaded cells are not used with the Fixed Voltage Reference.

Bit 2

Bit 1

ADFVR1

Bit 0

ADFVR0

Register on page

112

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Preliminary

2011 Microchip Technology Inc.

14.0

TEMPERATURE INDICATOR

MODULE

This family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit’s range of operating temperature falls between of -40°C and +85°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC.

The circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. A onepoint calibration allows the circuit to indicate a temperature closely surrounding that point. A two-point calibration allows the circuit to sense the entire range of temperature more accurately. Reference Application

Note AN1333, “

Use and Calibration of the Internal

Temperature Indicator

” (DS01333) for more details regarding the calibration process.

14.1

Circuit Operation

Figure 14-1

shows a simplified block diagram of the temperature circuit. The proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions.

Equation 14-1

describes the output characteristics of the temperature indicator.

EQUATION 14-1: V

OUT

RANGES

High Range: V

OUT

= V

DD

- 4V

T

Low Range: V

OUT

= V

DD

- 2V

T

The temperature sense circuit is integrated with the

Fixed Voltage Reference (FVR) module. See

Section 13.0 “Fixed Voltage Reference (FVR)”

for

more information.

The circuit is enabled by setting the TSEN bit of the

FVRCON register. When disabled, the circuit draws no current.

The circuit operates in either high or low range. The high range, selected by setting the TSRNG bit of the

FVRCON register, provides a wider output voltage. This provides more resolution over the temperature range, but may be less consistent from part to part. This range requires a higher bias voltage to operate and thus, a higher V

DD

is needed.

The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation.

FIGURE 14-1:

PIC16LF1902/3

TEMPERATURE CIRCUIT

DIAGRAM

V

DD

TSEN

TSRNG

V

OUT

ADC

MUX n

CHS bits

(ADCON0 register)

ADC

14.2

Minimum Operating V

DD

vs.

Minimum Sensing Temperature

When the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications.

When the temperature circuit is operated in high range, the device operating voltage, V

DD

, must be high enough to ensure that the temperature circuit is correctly biased.

Table 14-1

shows the recommended minimum V

DD

vs.

range setting.

TABLE 14-1: RECOMMENDED V

DD

VS.

RANGE

Min. V

DD

, TSRNG =

1

3.6V

Min. V

DD

, TSRNG =

0

1.8V

14.3

Temperature Output

The output of the circuit is measured using the internal

Analog-to-Digital converter. A channel is reserved for

the temperature circuit output. Refer to

Section 15.0

“Analog-to-Digital Converter (ADC) Module”

for

detailed information.

14.4

ADC Acquisition Time

To ensure accurate temperature measurements, the user must wait at least 200

 s after the ADC input multiplexer is connected to the temperature indicator output before the conversion is performed. In addition, the user must wait 200

 s between sequential conversions of the temperature indicator output.

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NOTES:

DS41455B-page 114

Preliminary

2011 Microchip Technology Inc.

15.0

ANALOG-TO-DIGITAL

CONVERTER (ADC) MODULE

The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the conversion result into the

ADC result registers (ADRESH:ADRESL register pair).

Figure 15-1

shows the block diagram of the ADC.

The ADC voltage reference is software selectable to be either internally generated or externally supplied.

FIGURE 15-1: ADC BLOCK DIAGRAM

V

DD

ADPREF =

00

V

REF

+ ADPREF =

10

PIC16LF1902/3

The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep.

AN0

AN1

AN2

V

REF

+/AN3

AN4

Reserved

Reserved

Reserved

AN8

AN9

AN10

AN11

AN12

AN13

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

GO/DONE

ADON

(1)

V

SS

ADC

10

ADFM

0

= Left Justify

1

= Right Justify

16

ADRESH ADRESL

Temperature Indicator

Reserved

FVR Buffer1

11101

11110

11111

CHS<4:0>

(2)

Note 1:

2:

When ADON =

0

, all multiplexer inputs are disconnected.

See ADCON0 register ( Example 15-1

) for detailed analog channel selection per device.

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15.1

ADC Configuration

When configuring and using the ADC the following functions must be considered:

• Port configuration

• Channel selection

• ADC voltage reference selection

• ADC conversion clock source

• Interrupt control

• Result formatting

15.1.1

PORT CONFIGURATION

The ADC can be used to convert both analog and digital signals. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to

Section 11.0 “I/O Ports”

for more information.

Note:

Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current.

15.1.2

CHANNEL SELECTION

There are up to 11 channel selections available:

• AN<13:0> pins

• Temperature Indicator

• FVR (Fixed Voltage Reference) Output

Refer to

Section 13.0 “Fixed Voltage Reference

(FVR)”

and

Section 14.0 “Temperature Indicator

Module”

for more information on these channel selections.

The CHS bits of the ADCON0 register determine which channel is connected to the sample and hold circuit.

When changing channels, a delay is required before starting the next conversion. Refer to

Section 15.2

“ADC Operation”

for more information.

15.1.3

ADC VOLTAGE REFERENCE

The ADPREF bits of the ADCON1 register provides control of the positive voltage reference. The positive voltage reference can be:

• V

REF

+ pin

• V

DD

• FVR

See

Section 13.0 “Fixed Voltage Reference (FVR)”

for more details on the fixed voltage reference.

15.1.4

CONVERSION CLOCK

The source of the conversion clock is software selectable via the ADCS bits of the ADCON1 register. There are seven possible clock options:

• F

OSC

/2

• F

OSC

/4

• F

OSC

/8

• F

OSC

/16

• F

OSC

/32

• F

OSC

/64

• F

RC

(dedicated internal oscillator)

The time to complete one bit conversion is defined as

T

AD

. One full 10-bit conversion requires 11.5 T

AD

peri-

ods as shown in Figure 15-2 .

For correct conversion, the appropriate T

AD

specification must be met. Refer to the A/D conversion requirements in

Section 21.0 “Electrical Specifications”

for

more information. Table 15-1

gives examples of appropriate ADC clock selections.

Note:

Unless using the F

RC

, any changes in the system clock frequency will change the

ADC clock frequency, which may adversely affect the ADC result.

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TABLE 15-1: ADC CLOCK PERIOD (T

AD

) V

S

. DEVICE OPERATING FREQUENCIES

ADC Clock Period (T

AD

) Device Frequency (F

OSC

)

ADC

Clock Source

ADCS<2:0> 20 MHz 16 MHz 8 MHz 4 MHz 1 MHz

F

F

OSC

OSC

RC

Legend:

Note 1:

2:

3:

4:

/2

/4

F

OSC

/8

F

OSC

/16

F

F

OSC

OSC

F

/32

/64

000

100

001

101

010

110

100 ns

200 ns

400 ns

(2)

(2)

(2)

800 ns

1.6

 s

3.2

 s

1.0-6.0

 s

(1,4)

125 ns

(2)

250 ns

(2)

0.5

 s

(2)

1.0

 s

2.0

 s

4.0

 s

1.0-6.0

 s

(1,4)

250 ns

(2)

500 ns

(2)

1.0

 s

2.0

 s

4.0

 s

8.0

 s

(3)

1.0-6.0

 s

(1,4)

500 ns

(2)

1.0

 s

2.0

 s

4.0

 s

8.0

 s

(3)

16.0

 s

(3)

1.0-6.0

 s

(1,4)

2.0

 s

4.0

 s

8.0

 s

(3)

16.0

 s

(3)

32.0

 s

(3)

64.0

 s

(3)

1.0-6.0

 s

(1,4)

x11

Shaded cells are outside of recommended range.

The F

RC

source has a typical T

AD

time of 1.6

 s for V

DD

.

These values violate the minimum required T

AD

time.

For faster conversion times, the selection of another clock source is recommended.

The ADC clock period (T

AD

) and total ADC conversion time can be minimized when the ADC clock is derived from the system clock F

OSC

. However, the F

RC

clock source must be used when conversions are to be performed with the device in Sleep mode.

FIGURE 15-2: ANALOG-TO-DIGITAL CONVERSION T

AD

CYCLES

T

CY

- T

AD

T

AD

1 T

AD

2 T

AD

3 T

AD

4 T

AD

5 T

AD

6 T

AD

7 T

AD

8 b9 b8 b7 b6 b5 b4 b3

T

AD

9 T

AD

10 T

AD

11 b2 b1 b0

Conversion starts

Holding capacitor is disconnected from analog input (typically 100 ns)

Set GO bit

On the following cycle:

ADRESH:ADRESL is loaded, GO bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input.

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PIC16LF1902/3

15.1.5

INTERRUPTS

The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the

ADIE bit in the PIE1 register. The ADIF bit must be cleared in software.

Note 1:

2:

The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled.

The ADC operates during Sleep only when the F

RC

oscillator is selected.

This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from

Sleep, the next instruction following the

SLEEP

instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the

INTCON register are enabled, execution will switch to the Interrupt Service Routine.

15.1.6

RESULT FORMATTING

The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON1 register controls the output format.

Figure 15-3

shows the two output formats.

FIGURE 15-3: 10-BIT A/D CONVERSION RESULT FORMAT

ADRESH

(ADFM =

0

) MSB bit 7

(ADFM =

1

) bit 0

10-bit A/D Result bit 7

Unimplemented: Read as ‘

0

MSB bit 0

ADRESL bit 7

LSB bit 0

Unimplemented: Read as ‘

0

’ bit 7

LSB bit 0

10-bit A/D Result

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15.2

ADC Operation

15.2.1

STARTING A CONVERSION

To enable the ADC module, the ADON bit of the

ADCON0 register must be set to a ‘

1

’. Setting the

GO/DONE bit of the ADCON0 register to a ‘

1

’ will start the Analog-to-Digital conversion.

Note:

The GO/DONE bit should not be set in the same instruction that turns on the ADC.

Refer to

Section 15.2.5 “A/D Conversion

Procedure”

.

15.2.2

COMPLETION OF A CONVERSION

When the conversion is complete, the ADC module will:

• Clear the GO/DONE bit

• Set the ADIF Interrupt Flag bit

• Update the ADRESH and ADRESL registers with new conversion result

15.2.3

TERMINATING A CONVERSION

If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The

ADRESH and ADRESL registers will be updated with the partially complete Analog-to-Digital conversion sample. Incomplete bits will match the last bit converted.

Note:

A device Reset forces all registers to their

Reset state. Thus, the ADC module is turned off and any pending conversion is terminated.

PIC16LF1902/3

15.2.4

ADC OPERATION DURING SLEEP

The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F

RC option. When the F

RC

clock source is selected, the

ADC waits one additional instruction before starting the conversion. This allows the

SLEEP

instruction to be executed, which can reduce system noise during the conversion. If the ADC interrupt is enabled, the device will wake-up from Sleep when the conversion completes. If the ADC interrupt is disabled, the ADC module is turned off after the conversion completes, although the ADON bit remains set.

When the ADC clock source is something other than

F

RC

, a

SLEEP

instruction causes the present conversion to be aborted and the ADC module is turned off, although the ADON bit remains set.

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4.

5.

6.

15.2.5

A/D CONVERSION PROCEDURE

This is an example procedure for using the ADC to perform an Analog-to-Digital conversion:

1.

2.

3.

7.

8.

Configure Port:

• Disable pin output driver (Refer to the TRIS register)

• Configure pin as analog (Refer to the ANSEL register)

Configure the ADC module:

• Select ADC conversion clock

• Configure voltage reference

• Select ADC input channel

• Turn on ADC module

Configure ADC interrupt (optional):

• Clear ADC interrupt flag

• Enable ADC interrupt

• Enable peripheral interrupt

• Enable global interrupt

(1)

Wait the required acquisition time

(2)

.

Start conversion by setting the GO/DONE bit.

Wait for ADC conversion to complete by one of the following:

• Polling the GO/DONE bit

• Waiting for the ADC interrupt (interrupts enabled)

Read ADC Result.

Clear the ADC interrupt flag (required if interrupt is enabled).

Note 1:

2:

The global interrupt can be disabled if the user is attempting to wake-up from Sleep and resume in-line code execution.

Refer to

Section 15.3 “A/D Acquisition

Requirements”

.

EXAMPLE 15-1: A/D CONVERSION

;This code block configures the ADC

;for polling, Vdd and Vss references, Frc

;clock and AN0 input.

;

;Conversion start & polling for completion

; are included.

;

BANKSEL

MOVLW

ADCON1

B’11110000’

;

;Right justify, Frc

MOVWF

BANKSEL

BSF

BANKSEL

BSF

BANKSEL

MOVLW

MOVWF

ADCON1

TRISA

TRISA,0

ANSEL

ANSEL,0

ADCON0

B’00000001’

ADCON0

;clock

;Vdd and Vss Vref

;

;Set RA0 to input

;

;Set RA0 to analog

;

;Select channel AN0

CALL

BSF

BTFSC

GOTO

BANKSEL

MOVF

MOVWF

BANKSEL

MOVF

MOVWF

SampleTime

ADCON0,ADGO

ADCON0,ADGO

$-1

ADRESH

ADRESH,W

RESULTHI

ADRESL

ADRESL,W

RESULTLO

;Turn ADC On

;Acquisiton delay

;Start conversion

;Is conversion done?

;No, test again

;

;Read upper 2 bits

;store in GPR space

;

;Read lower 8 bits

;Store in GPR space

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PIC16LF1902/3

15.2.6

ADC REGISTER DEFINITIONS

The following registers are used to control the operation of the ADC.

REGISTER 15-1: ADCON0: A/D CONTROL REGISTER 0

bit 7

U-0

R/W-0/0 R/W-0/0 R/W-0/0

CHS<4:0>

R/W-0/0 R/W-0/0 R/W-0/0

GO/DONE

R/W-0/0

ADON bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7 bit 6-2 bit 1 bit 0

Unimplemented:

Read as ‘

0

CHS<4:0>:

Analog Channel Select bits

00000

= AN0

00001

= AN1

00010

= AN2

00011

= AN3

00100

= AN4

00101

= Reserved. No channel connected.

00110

= Reserved. No channel connected.

00111

= Reserved. No channel connected.

01000

= AN8

01001

= AN9

01010

= AN10

01011

= AN11

01100

= AN12

01101

= AN13

01110

= Reserved. No channel connected.

11100

= Reserved. No channel connected.

11101

= Temperature Indicator

(2)

11110

= Reserved. No channel connected.

11111

= FVR (Fixed Voltage Reference) Buffer 1 Output

(1)

GO/DONE:

A/D Conversion Status bit

1

= A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.

This bit is automatically cleared by hardware when the A/D conversion has completed.

0

= A/D conversion completed/not in progress

ADON:

ADC Enable bit

1

= ADC is enabled

0

= ADC is disabled and consumes no operating current

Note 1:

2:

See

Section 13.0 “Fixed Voltage Reference (FVR)”

for more information.

See

Section 14.0 “Temperature Indicator Module”

for more information.

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REGISTER 15-2:

R/W-0/0

ADFM bit 7

ADCON1: A/D CONTROL REGISTER 1

R/W-0/0 R/W-0/0

ADCS<2:0>

R/W-0/0 U-0

U-0

R/W-0/0 R/W-0/0

ADPREF<1:0> bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7 bit 6-4 bit 3-2 bit 1-0

ADFM:

A/D Result Format Select bit

1

= Right justified. Six Most Significant bits of ADRESH are set to ‘

0

’ when the conversion result is loaded.

0

= Left justified. Six Least Significant bits of ADRESL are set to ‘

0

’ when the conversion result is loaded.

ADCS<2:0>:

A/D Conversion Clock Select bits

000

= F

OSC

/2

001

= F

OSC

/8

010

= F

OSC

/32

011

= F

RC

(clock supplied from a dedicated RC oscillator)

100

= F

OSC

/4

101

= F

OSC

/16

110

= F

OSC

/64

111

= F

RC

(clock supplied from a dedicated RC oscillator)

Unimplemented:

Read as ‘

0

ADPREF<1:0>:

A/D Positive Voltage Reference Configuration bits

00

= V

REF

+ is connected to V

DD

01

= Reserved

10

= V

REF

+ is connected to external V

REF

+ pin

(1)

11

= Reserved

Note 1:

When selecting the FVR or the V

REF

+ pin as the source of the positive reference, be aware that a minimum voltage specification exists. See

Section 21.0 “Electrical Specifications”

for details.

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REGISTER 15-3:

R/W-x/u

ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM =

R/W-x/u R/W-x/u R/W-x/u R/W-x/u

ADRES<9:2>

R/W-x/u

0

R/W-x/u bit 7

R/W-x/u bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

ADRES<9:2>

: ADC Result Register bits

Upper 8 bits of 10-bit conversion result

REGISTER 15-4: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM =

0

R/W-x/u R/W-x/u

ADRES<1:0> bit 7

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

— bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-6 bit 5-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

ADRES<1:0>

: ADC Result Register bits

Lower 2 bits of 10-bit conversion result

Reserved

: Do not use.

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

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REGISTER 15-5:

R/W-x/u

— bit 7

ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM =

1

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u

R/W-x/u R/W-x/u

ADRES<9:8> bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-2 bit 1-0

Reserved

: Do not use.

ADRES<9:8>

: ADC Result Register bits

Upper 2 bits of 10-bit conversion result

REGISTER 15-6: ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM =

1

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

ADRES<7:0>

R/W-x/u R/W-x/u bit 7

R/W-x/u bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

ADRES<7:0>

: ADC Result Register bits

Lower 8 bits of 10-bit conversion result

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

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15.3

A/D Acquisition Requirements

For the ADC to meet its specified accuracy, the charge holding capacitor (C

HOLD

) must be allowed to fully charge to the input channel voltage level. The Analog

Input model is shown in Figure 15-4

. The source impedance (R

S

) and the internal sampling switch (R

SS

) impedance directly affect the time required to charge the capacitor C

HOLD

. The sampling switch (R

SS

) impedance varies over the device voltage (V

DD

), refer to

Figure 15-4 .

The maximum recommended impedance for analog sources is 10 k

.

As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time,

Equation 15-1

may be used. This equation assumes that 1/2 LSb error is used

(1,024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution.

EQUATION 15-1:

Assumptions:

ACQUISITION TIME EXAMPLE

Temperature = 50°C and external impedance of 10k

5.0V V

DD

T

ACQ

= Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient

=

=

T

AMP

+ T

C

+ T

COFF

2µs + T

C

+

 

Temperature - 25°C

 

0.05µs/°C

 

The value for T

C

can be approximated with the following equations:

V

AP P LI ED

1

--------------------------

2 n +

1

1

1

=

V

C H O L D

V

AP P LI ED

1

e

T

C

----------

RC

=

V

C H O L D

V

AP P LI ED

1

e

Tc

---------

RC

=

V

A PP L I E D

1

--------------------------

2 n +

1

1

1

;[1] V

CHOLD

charged to within 1/2 lsb

;[2] V

CHOLD

charge response to V

APPLIED

;combining [1] and [2]

Note: Where n = number of bits of the ADC.

Solving for T

C

:

T

C

=

=

C

HOLD

R

IC

+ R

SS

+ R

S

ln(1/511)

+ 7k

+ 10k

 

ln(0.001957)

=

1.12

µs

Therefore:

T

A C Q

= 2µs + 1.12µs +

 

50°C- 25°C

 

0.05

µs/°C

 

= 4.42µs

Note 1:

2:

3:

The reference voltage (V

REF

) has no effect on the equation, since it cancels itself out.

The charge holding capacitor (C

HOLD

) is not discharged after each conversion.

The maximum recommended impedance for analog sources is 10 k

. This is required to meet the pin leakage specification.

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FIGURE 15-4: ANALOG INPUT MODEL

Rs

Analog

Input pin

V

DD

V

T

0.6V

VA

C

PIN

5 pF

V

T

0.6V

R

IC

1k

Sampling

Switch

SS Rss

I

LEAKAGE

(1)

C

HOLD

= 10 pF

V

SS

/V

REF

-

V

DD

6V

5V

4V

3V

2V

R

SS

Legend:

C

HOLD

C

PIN

I

LEAKAGE

R

R

IC

SS

SS

V

T

= Sample/Hold Capacitance

= Input Capacitance

= Leakage current at the pin due to various junctions

= Interconnect Resistance

= Resistance of Sampling Switch

= Sampling Switch

= Threshold Voltage

Note 1:

Refer to

Section 21.0 “Electrical Specifications”

.

5 6 7 8 9 10 11

Sampling Switch

(k

)

FIGURE 15-5: ADC TRANSFER FUNCTION

Full-Scale Range

3FFh

3FEh

3FDh

3FCh

3FBh

V

REF

-

03h

02h

01h

00h

0.5 LSB

Zero-Scale

Transition Full-Scale

Transition

Analog Input Voltage

1.5 LSB

V

REF

+

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TABLE 15-2: SUMMARY OF REGISTERS ASSOCIATED WITH ADC

ADCON0

ADCON1

ADRESH

ADRESL

ANSELA

ANSELB

INTCON

PIE1

PIR1

TRISA

TRISB

FVRCON

Legend:

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Register on Page

ADFM

CHS4

ADCS2

CHS3

ADCS1

CHS2

ADCS0

CHS1

CHS0

GO/DONE

ADPREF1

ADON

ADPREF0

121

122

A/D Result Register High

123

,

124

A/D Result Register Low

123

,

124

— — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0

98

— — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0

101

GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF

66

TMR1GIE ADIE — — — — — TMR1IE

67

TMR1GIF ADIF — — — — — TMR1IF

69

TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0

97

TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0

100

FVREN FVRRDY TSEN TSRNG — — ADFVR1 ADFVR0

112

x

= unknown, u

= unchanged,

= unimplemented read as ‘

0

’, q

= value depends on condition. Shaded cells are not used for ADC module.

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DS41455B-page 128

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16.0

TIMER0 MODULE

The Timer0 module is an 8-bit timer/counter with the following features:

• 8-bit timer/counter register (TMR0)

• 8-bit prescaler (independent of Watchdog Timer)

• Programmable internal or external clock source

• Programmable external clock edge selection

• Interrupt on overflow

• TMR0 can be used to gate Timer1

Figure 16-1

is a block diagram of the Timer0 module.

16.1

Timer0 Operation

The Timer0 module can be used as either an 8-bit timer or an 8-bit counter.

16.1.1

8-BIT TIMER MODE

The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-Bit Timer mode is selected by clearing the TMR0CS bit of the

OPTION_REG register.

When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write.

Note:

The value written to the TMR0 register can be adjusted, in order to account for the two instruction cycle delay when

TMR0 is written.

FIGURE 16-1: BLOCK DIAGRAM OF THE TIMER0

16.1.2

8-BIT COUNTER MODE

In 8-Bit Counter mode, the Timer0 module will increment on every rising or falling edge of the T0CKI pin.

8-Bit Counter mode using the T0CKI pin is selected by setting the TMR0CS bit in the OPTION_REG register to

1

’.

The rising or falling transition of the incrementing edge for either input source is determined by the TMR0SE bit in the OPTION_REG register.

F

OSC

/4

T0CKI

0

1

1

Sync

2 T

CY

Data Bus

8

TMR0

0

TMR0SE

TMR0CS

8-bit

Prescaler

PSA

Set Flag bit TMR0IF on Overflow

Overflow to Timer1

8

PS<2:0>

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16.1.3

SOFTWARE PROGRAMMABLE

PRESCALER

A software programmable prescaler is available for exclusive use with Timer0. The prescaler is enabled by clearing the PSA bit of the OPTION_REG register.

Note:

The Watchdog Timer (WDT) uses its own independent prescaler.

There are 8 prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS<2:0> bits of the OPTION_REG register. In order to have a 1:1 prescaler value for the

Timer0 module, the prescaler must be disabled by setting the PSA bit of the OPTION_REG register.

The prescaler is not readable or writable. All instructions writing to the TMR0 register will clear the prescaler.

16.1.4

TIMER0 INTERRUPT

Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The TMR0IF interrupt flag bit of the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The

TMR0IF bit can only be cleared in software. The Timer0 interrupt enable is the TMR0IE bit of the INTCON register.

Note:

The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep.

16.1.5

8-BIT COUNTER MODE

SYNCHRONIZATION

When in 8-Bit Counter mode, the incrementing edge on the T0CKI pin must be synchronized to the instruction clock. Synchronization can be accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the instruction clock. The high and low periods of the external clocking source must meet the timing requirements as shown in

Section 21.0 “Electrical

Specifications”

.

16.1.6

OPERATION DURING SLEEP

Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode.

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16.2

Option and Timer0 Control Register

REGISTER 16-1: OPTION_REG: OPTION REGISTER

R/W-1/1

WPUEN bit 7

R/W-1/1

INTEDG

R/W-1/1

TMR0CS

R/W-1/1

TMR0SE

R/W-1/1

PSA

R/W-1/1 R/W-1/1

PS<2:0>

R/W-1/1 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4 bit 3 bit 2-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

WPUEN:

Weak Pull-up Enable bit

1

= All weak pull-ups are disabled (except MCLR, if it is enabled)

0

= Weak pull-ups are enabled by individual WPUx latch values

INTEDG:

Interrupt Edge Select bit

1

= Interrupt on rising edge of INT pin

0

= Interrupt on falling edge of INT pin

TMR0CS:

Timer0 Clock Source Select bit

1

= Transition on T0CKI pin

0

= Internal instruction cycle clock (F

OSC

/4)

TMR0SE:

Timer0 Source Edge Select bit

1

= Increment on high-to-low transition on T0CKI pin

0

= Increment on low-to-high transition on T0CKI pin

PSA:

Prescaler Assignment bit

1

= Prescaler is not assigned to the Timer0 module

0

= Prescaler is assigned to the Timer0 module

PS<2:0>:

Prescaler Rate Select bits

Bit Value Timer0 Rate

000

001

010

011

100

101

110

111

1 : 2

1 : 4

1 : 8

1 : 16

1 : 32

1 : 64

1 : 128

1 : 256

TABLE 16-1: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF

OPTION_REG WPUEN

TMR0

TRISA

Legend:

*

Timer0 Module Register

TRISA7

INTEDG TMR0CS TMR0SE

TRISA6 TRISA5 TRISA4

PSA

TRISA3 TRISA2

PS<2:0>

TRISA1 TRISA0

— = Unimplemented location, read as ‘

0

’. Shaded cells are not used by the Timer0 module.

Page provides register information.

Register on Page

66

131

129 *

97

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17.0

TIMER1 MODULE WITH GATE

CONTROL

The Timer1 module is a 16-bit timer/counter with the following features:

• 16-bit timer/counter register pair (TMR1H:TMR1L)

• Programmable internal or external clock source

• 2-bit prescaler

• Dedicated 32 kHz oscillator circuit

• Multiple Timer1 gate (count enable) sources

• Interrupt on overflow

• Wake-up on overflow (external clock,

Asynchronous mode only)

• Selectable Gate Source Polarity

• Gate Toggle Mode

• Gate Single-pulse Mode

FIGURE 17-1: TIMER1 BLOCK DIAGRAM

• Gate Value Status

• Gate Event Interrupt

Figure 17-1

is a block diagram of the Timer1 module.

T1GSS<1:0>

T1G

From Timer0

Overflow

0

1

T1GSPM

T1OSO

T1OSI

T1OSCEN

OUT

T1OSC

EN

T1G_IN

D

R

CK

Q

Q

T1GPOL

Set flag bit

TMR1IF on

Overflow

TMR1ON

T1GTM

TMR1H

TMR1

(2)

TMR1L

(1)

1

0

0

1

Single Pulse

Acq. Control

T1GGO/DONE

0

1

T1GVAL

D

Q1

EN

Q

Interrupt det

TMR1GE

TMR1ON

Q

EN

D

T1CLK

TMR1CS<1:0>

Reserved

F

OSC

Internal

Clock

F

OSC

/4

Internal

Clock

11

10

01

00

0

Synchronized clock input

1

T1SYNC

Prescaler

1, 2, 4, 8

2

T1CKPS<1:0>

F

OSC

/2

Internal

Clock

Synchronize

(3)

det

Sleep input

Data Bus

RD

T1GCON

Set

TMR1GIF

T1CKI

To LCD and Clock Switching Modules

Note 1:

2:

3:

ST Buffer is high speed type when using T1CKI.

Timer1 register increments on rising edge.

Synchronize does not operate while in Sleep.

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17.1

Timer1 Operation

The Timer1 module is a 16-bit incrementing counter which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter.

When used with an internal clock source, the module is a timer and increments on every instruction cycle.

When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source.

Timer1 is enabled by configuring the TMR1ON and

TMR1GE bits in the T1CON and T1GCON registers, respectively.

Table 17-1 displays the Timer1 enable

selections.

TABLE 17-1:

TMR1ON

1

1

0

0

TIMER1 ENABLE

SELECTIONS

TMR1GE

0

1

0

1

Timer1

Operation

Off

Off

Always On

Count Enabled

17.2

Clock Source Selection

The TMR1CS<1:0> and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1.

Table 17-2

displays the clock source selections.

17.2.1

INTERNAL CLOCK SOURCE

When the internal clock source is selected the

TMR1H:TMR1L register pair will increment on multiples of F

OSC

as determined by the Timer1 prescaler.

When the F

OSC

internal clock source is selected, the

Timer1 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1 value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the

Timer1 clock input.

The following asynchronous source may be used:

• Asynchronous event on the T1G pin to Timer1 gate

17.2.2

EXTERNAL CLOCK SOURCE

When the external clock source is selected, the Timer1 module may work as a timer or a counter.

When enabled to count, Timer1 is incremented on the rising edge of the external clock input T1CKI or the capacitive sensing oscillator signal. Either of these external clock sources can be synchronized to the microcontroller system clock or they can run asynchronously.

When used as a timer with a clock oscillator, an external 32.768 kHz crystal can be used in conjunction with the dedicated internal oscillator circuit.

Note:

In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions:

• Timer1 enabled after POR

• Write to TMR1H or TMR1L

• Timer1 is disabled

• Timer1 is disabled (TMR1ON =

0

) when T1CKI is high then Timer1 is enabled (TMR1ON=

1

) when T1CKI is low.

TABLE 17-2:

TMR1CS1

1

1

0

0

1

CLOCK SOURCE SELECTIONS

TMR1CS0 T1OSCEN

0

0

0

1

1

0

1 x x x

Clock Source

Instruction Clock (F

OSC

/4)

System Clock (F

OSC

)

External Clocking on T1CKI Pin

Osc. Circuit on T1OSI/T1OSO Pins

LFINTOSC

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17.3

Timer1 Prescaler

Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits of the

T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to

TMR1H or TMR1L.

17.4

Timer1 Oscillator

A dedicated low-power 32.768 kHz oscillator circuit is built-in between pins T1OSI (input) and T1OSO. This internal circuit is to be used in conjunction with an external 32.768 kHz crystal.

The oscillator circuit is enabled by setting the

T1OSCEN bit of the T1CON register. The oscillator will continue to run during Sleep.

Note:

The oscillator requires a start-up and stabilization time before use. Thus,

T1OSCEN should be set and a suitable delay observed prior to enabling Timer1.

17.5

Timer1 Operation in

Asynchronous Counter Mode

If control bit T1SYNC of the T1CON register is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If the external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see

Section 17.5.1 “Reading and Writing Timer1 in

Asynchronous Counter Mode”

).

Note:

When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment.

17.5.1

READING AND WRITING TIMER1 IN

ASYNCHRONOUS COUNTER

MODE

Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two

8-bit values itself, poses certain problems, since the timer may overflow between the reads.

For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMR1H:TMR1L register pair.

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Preliminary

PIC16LF1902/3

17.6

Timer1 Gate

Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is also referred to as Timer1 Gate Enable.

Timer1 gate can also be driven by multiple selectable sources.

17.6.1

TIMER1 GATE ENABLE

The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 Gate Enable mode is configured using the T1GPOL bit of the T1GCON register.

When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate Enable mode is disabled, no incrementing will occur and Timer1 will hold the

current count. See Figure 17-3

for timing details.

TABLE 17-3: TIMER1 GATE ENABLE

SELECTIONS

T1GPOL T1G T1CLK

1

1

0

0

0

1

0

1

Timer1 Operation

Counts

Holds Count

Holds Count

Counts

17.6.2

TIMER1 GATE SOURCE

SELECTION

The Timer1 gate source can be selected from one of four different sources. Source selection is controlled by the T1GSS bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the

T1GCON register.

TABLE 17-4:

T1GSS

00

01

TIMER1 GATE SOURCES

Timer1 Gate Source

Timer1 Gate Pin

Overflow of Timer0

(TMR0 increments from FFh to 00h)

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17.6.2.1

T1G Pin Gate Operation

The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry.

17.6.2.2

Timer0 Overflow Gate Operation

When Timer0 increments from FFh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry.

17.6.3

TIMER1 GATE TOGGLE MODE

When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse.

The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See

Figure 17-4 for timing details.

Timer1 Gate Toggle mode is enabled by setting the

T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured.

Note:

Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation.

17.6.4

TIMER1 GATE SINGLE-PULSE

MODE

When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1

Gate Single-Pulse mode is first enabled by setting the

T1GSPM bit in the T1GCON register. Next, the

T1GGO/DONE bit in the T1GCON register must be set.

The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the

T1GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the

T1GGO/DONE bit is once again set in software. See

Figure 17-5

for timing details.

If the Single Pulse Gate mode is disabled by clearing the

T1GSPM bit in the T1GCON register, the T1GGO/DONE bit should also be cleared.

Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 gate source to be measured. See

Figure 17-6 for timing

details.

17.6.5

TIMER1 GATE VALUE STATUS

When Timer1 gate value status is utilized, it is possible to read the most current level of the gate control value.

The value is stored in the T1GVAL bit in the T1GCON register. The T1GVAL bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared).

17.6.6

TIMER1 GATE EVENT INTERRUPT

When Timer1 Gate Event Interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of T1GVAL occurs, the TMR1GIF flag bit in the PIR1 register will be set. If the TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized.

The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared).

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17.7

Timer1 Interrupt

The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIR1 register is set. To enable the interrupt on rollover, you must set these bits:

• TMR1ON bit of the T1CON register

• TMR1IE bit of the PIE1 register

• PEIE bit of the INTCON register

• GIE bit of the INTCON register

The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine.

Note:

The TMR1H:TMR1L register pair and the

TMR1IF bit should be cleared before enabling interrupts.

PIC16LF1902/3

17.8

Timer1 Operation During Sleep

Timer1 can only operate during Sleep when setup in

Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device:

• TMR1ON bit of the T1CON register must be set

• TMR1IE bit of the PIE1 register must be set

• PEIE bit of the INTCON register must be set

• T1SYNC bit of the T1CON register must be set

• TMR1CS bits of the T1CON register must be configured

• T1OSCEN bit of the T1CON register must be configured

The device will wake-up on an overflow and execute the next instructions. If the GIE bit of the INTCON register is set, the device will call the Interrupt Service

Routine.

Timer1 oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting.

FIGURE 17-2:

T1CKI =

1 when TMR1

Enabled

TIMER1 INCREMENTING EDGE

T1CKI =

0 when TMR1

Enabled

Note 1:

2:

Arrows indicate counter increments.

In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.

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PIC16LF1902/3

FIGURE 17-3: TIMER1 GATE ENABLE MODE

TMR1GE

T1GPOL

T1G_IN

T1CKI

T1GVAL

Timer1

N N + 1 N + 2

FIGURE 17-4: TIMER1 GATE TOGGLE MODE

TMR1GE

T1GPOL

T1GTM

T1G_IN

T1CKI

T1GVAL

Timer1

N N + 1 N + 2 N + 3 N + 4

N + 3 N + 4

N + 5 N + 6 N + 7 N + 8

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PIC16LF1902/3

FIGURE 17-5: TIMER1 GATE SINGLE-PULSE MODE

TMR1GE

T1GPOL

T1GSPM

T1GGO/

DONE

T1G_IN

Set by software

Counting enabled on rising edge of T1G

Cleared by hardware on falling edge of T1GVAL

T1CKI

T1GVAL

Timer1

TMR1GIF

N

Cleared by software

N + 1 N + 2

Set by hardware on falling edge of T1GVAL

Cleared by software

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PIC16LF1902/3

TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE FIGURE 17-6:

TMR1GE

T1GPOL

T1GSPM

T1GTM

T1GGO/

DONE

T1G_IN

Set by software

Counting enabled on rising edge of T1G

Cleared by hardware on falling edge of T1GVAL

T1CKI

T1GVAL

Timer1

TMR1GIF

N

Cleared by software

N + 1 N + 2 N + 3

N + 4

Set by hardware on falling edge of T1GVAL

Cleared by software

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PIC16LF1902/3

17.9

Timer1 Control Register

The Timer1 Control register (T1CON), shown in

Register 17-1

, is used to control Timer1 and select the various features of the Timer1 module.

REGISTER 17-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0/u R/W-0/u

TMR1CS<1:0> bit 7

R/W-0/u R/W-0/u

T1CKPS<1:0>

R/W-0/u

T1OSCEN

R/W-0/u

T1SYNC

U-0

R/W-0/u

TMR1ON bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-6 bit 5-4 bit 3 bit 2 bit 1 bit 0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

TMR1CS<1:0>:

Timer1 Clock Source Select bits

11

= Reserved

10

= Timer1 clock source is pin or oscillator:

If T1OSCEN =

0

:

External clock from T1CKI pin (on the rising edge)

If T1OSCEN =

1

:

Crystal oscillator on T1OSI/T1OSO pins

01

= Timer1 clock source is system clock (F

OSC

)

00

= Timer1 clock source is instruction clock (F

OSC

/4)

T1CKPS<1:0>:

Timer1 Input Clock Prescale Select bits

11

= 1:8 Prescale value

10

= 1:4 Prescale value

01

= 1:2 Prescale value

00

= 1:1 Prescale value

T1OSCEN:

LP Oscillator Enable Control bit

1

= Dedicated Timer1 oscillator circuit enabled

0

= Dedicated Timer1 oscillator circuit disabled

T1SYNC:

Timer1 External Clock Input Synchronization Control bit

TMR1CS<1:0> =

1X

1

= Do not synchronize external clock input

0

= Synchronize external clock input with system clock (F

OSC

)

TMR1CS<1:0> =

0X

This bit is ignored. Timer1 uses the internal clock when TMR1CS<1:0> =

1X

.

Unimplemented:

Read as ‘

0

TMR1ON:

Timer1 On bit

1

= Enables Timer1

0

= Stops Timer1

Clears Timer1 gate flip-flop

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PIC16LF1902/3

17.10 Timer1 Gate Control Register

The Timer1 Gate Control register (T1GCON), shown in

Register 17-2

, is used to control Timer1 gate.

REGISTER 17-2: T1GCON: TIMER1 GATE CONTROL REGISTER

R/W-0/u

TMR1GE bit 7

R/W-0/u

T1GPOL

R/W-0/u

T1GTM

R/W-0/u

T1GSPM

R/W/HC-0/u

T1GGO/

DONE

R-x/x

T1GVAL

R/W-0/u R/W-0/u

T1GSS<1:0> bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

HC = Bit is cleared by hardware

TMR1GE:

Timer1 Gate Enable bit

If TMR1ON =

0

:

This bit is ignored

If TMR1ON =

1

:

1

= Timer1 counting is controlled by the Timer1 gate function

0

= Timer1 counts regardless of Timer1 gate function

T1GPOL:

Timer1 Gate Polarity bit

1

= Timer1 gate is active-high (Timer1 counts when gate is high)

0

= Timer1 gate is active-low (Timer1 counts when gate is low)

T1GTM:

Timer1 Gate Toggle Mode bit

1

= Timer1 Gate Toggle mode is enabled

0

= Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared

Timer1 gate flip-flop toggles on every rising edge.

T1GSPM:

Timer1 Gate Single-Pulse Mode bit

1

= Timer1 gate Single-Pulse mode is enabled and is controlling Timer1 gate

0

= Timer1 gate Single-Pulse mode is disabled

T1GGO/DONE:

Timer1 Gate Single-Pulse Acquisition Status bit

1

= Timer1 gate single-pulse acquisition is ready, waiting for an edge

0

= Timer1 gate single-pulse acquisition has completed or has not been started

T1GVAL:

Timer1 Gate Current State bit

Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L.

Unaffected by Timer1 Gate Enable (TMR1GE).

T1GSS<1:0>:

Timer1 Gate Source Select bits

00

= Timer1 gate pin

01

= Timer0 overflow output

10

= Reserved

11

= Reserved

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PIC16LF1902/3

TABLE 17-5: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1

Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON

PIE1

PIR1

TMR1H

TMR1L

TRISC

GIE

TMR1GIE

PEIE

ADIE

TMR0IE

INTE

IOCIE

TMR0IF

INTF

TMR1GIF ADIF — — — —

Holding Register for the Most Significant Byte of the 16-bit TMR1 Register

Holding Register for the Least Significant Byte of the 16-bit TMR1 Register

TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1

IOCIF

TMR1IE

TMR1IF

TRISC0

T1CON

TMR1CS1 TMR1CS0 T1CKPS<1:0> T1OSCEN T1SYNC — TMR1ON

T1GCON

Legend:

*

TMR1GE T1GPOL T1GTM T1GSPM T1GGO/

DONE

T1GVAL T1GSS1 T1GSS0

— = unimplemented location, read as ‘

0

’. Shaded cells are not used by the Timer1 module.

Page provides register information.

Register on Page

66

67

69

137

*

137

*

103

141

142

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NOTES:

DS41455B-page 144

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PIC16LF1902/3

18.0

LIQUID CRYSTAL DISPLAY

(LCD) DRIVER MODULE

The Liquid Crystal Display (LCD) Driver module generates the timing control to drive a static or multiplexed LCD panel. In the PIC16LF1902/3 device, the module drives the panels of up to four commons and up to 72 total segments. The LCD module also provides control of the LCD pixel data.

The LCD Driver module supports:

• Direct driving of LCD panel

• Three LCD clock sources with selectable prescaler

• Up to four common pins:

- Static (1 common)

- 1/2 multiplex (2 commons)

- 1/3 multiplex (3 commons)

- 1/4 multiplex (4 commons)

• 19 Segment pins

• Static, 1/2 or 1/3 LCD Bias

Note:

COM3 and SEG15 share the same physical pin on the PIC16LF1902/3, therefore SEG15 is not available when using 1/4 multiplex displays.

FIGURE 18-1: LCD DRIVER MODULE BLOCK DIAGRAM

18.1

LCD Registers

The module contains the following registers:

• LCD Control register (LCDCON)

• LCD Phase register (LCDPS)

• LCD Reference Ladder register (LCDRL)

• LCD Contrast Control register (LCDCST)

• LCD Reference Voltage Control register

(LCDREF)

• Up to 3 LCD Segment Enable registers (LCDSEn)

• Up to 12 LCD data registers (LCDDATAn)

Data Bus

LCDDATAx

Registers

MUX

SEG<26:24, 15:0>

(2)

To I/O Pads

(1)

Timing Control

LCDCON

LCDPS

LCDSEn

COM<3:0>

(3)

To I/O Pads

(1)

F

OSC

/256

T1OSC

LFINTOSC

Clock Source

Select and

Prescaler

Note 1:

2:

These are not directly connected to the I/O pads, but may be tri-stated, depending on the configuration of the LCD module.

COM3 and SEG15 share the same physical pin, therefore SEG15 is not available when using 1/4 multiplex displays.

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PIC16LF1902/3

TABLE 18-1: LCD SEGMENT AND DATA

REGISTERS

Device

# of LCD Registers

Segment

Enable

3

Data

12 PIC16LF1902/3

The LCDCON register (

Register 18-1 ) controls the

operation of the LCD Driver module. The LCDPS reg-

ister ( Register 18-2

) configures the LCD clock source prescaler and the type of waveform; Type-A or Type-B.

The LCDSEn registers (

Register 18-5 ) configure the

functions of the port pins.

The following LCDSEn registers are available:

• LCDSE0 SE<7:0>

• LCDSE1 SE<15:8>

• LCDSE3 SE<26:24>

Once the module is initialized for the LCD panel, the individual bits of the LCDDATAn registers are cleared/set to represent a clear/dark pixel, respectively:

• LCDDATA0

• LCDDATA1

• LCDDATA3

• LCDDATA4

• LCDDATA6

• LCDDATA7

SEG<7:0>COM0

SEG<15:8>COM0

SEG<7:0>COM1

SEG<15:8>COM1

SEG<7:0>COM2

SEG<15:8>COM2

• LCDDATA9 SEG<7:0>COM3

• LCDDATA10 SEG<15:8>COM3

• LCDDATA12 SEG<26:24>COM0

• LCDDATA15 SEG<26:24>COM1

• LCDDATA18 SEG<26:24>COM2

• LCDDATA21 SEG<26:24>COM3

As an example, LCDDATAn is detailed in

Register 18-6

.

Once the module is configured, the LCDEN bit of the

LCDCON register is used to enable or disable the LCD module. The LCD panel can also operate during Sleep by clearing the SLPEN bit of the LCDCON register.

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PIC16LF1902/3

REGISTER 18-1:

R/W-0/0

LCDEN bit 7

LCDCON: LIQUID CRYSTAL DISPLAY (LCD) CONTROL REGISTER

R/W-0/0

SLPEN

R/C-0/0

WERR

U-0

R/W-0/0 R/W-0/0

CS<1:0>

R/W-1/1 R/W-1/1

LMUX<1:0> bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4 bit 3-2 bit 1-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

C = Only clearable bit

LCDEN:

LCD Driver Enable bit

1

= LCD Driver module is enabled

0

= LCD Driver module is disabled

SLPEN:

LCD Driver Enable in Sleep Mode bit

1

= LCD Driver module is disabled in Sleep mode

0

= LCD Driver module is enabled in Sleep mode

WERR:

LCD Write Failed Error bit

1

= LCDDATAn register written while the WA bit of the LCDPS register =

0

(must be cleared in software)

0

= No LCD write error

Unimplemented:

Read as ‘

0

CS<1:0>:

Clock Source Select bits

00

= F

OSC

/256

01

= T1OSC (Timer1)

1x

= LFINTOSC (31 kHz)

LMUX<1:0>:

Commons Select bits

Maximum Number of Pixels

LMUX<1:0> Multiplex Bias

00

01

10

11

Static (COM0)

1/2 (COM<1:0>)

1/3 (COM<2:0>)

1/4 (COM<3:0>)

PIC16LF1902/3

19

38

57

72

(1)

Static

1/2 or 1/3

1/2 or 1/3

1/3

Note 1:

On these devices, COM3 and SEG15 are shared on one pin, limiting the device from driving 72 segments.

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PIC16LF1902/3

REGISTER 18-2:

R/W-0/0

WFT bit 7

LCDPS: LCD PHASE REGISTER

R/W-0/0

BIASMD

R-0/0

LCDA

R-0/0

WA

R/W-0/0 R/W-0/0 R/W-1/1

LP<3:0>

R/W-1/1 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7 bit 6 bit 5 bit 4 bit 3-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

C = Only clearable bit

WFT:

Waveform Type bit

1

= Type-B phase changes on each frame boundary

0

= Type-A phase changes within each common type

BIASMD:

Bias Mode Select bit

When LMUX<1:0> =

00

:

0

= Static Bias mode (do not set this bit to ‘

1

’)

When LMUX<1:0> =

01

:

1

= 1/2 Bias mode

0

= 1/3 Bias mode

When LMUX<1:0> =

10

:

1

= 1/2 Bias mode

0

= 1/3 Bias mode

When LMUX<1:0> =

11

:

0

= 1/3 Bias mode (do not set this bit to ‘

1

’)

LCDA:

LCD Active Status bit

1

= LCD Driver module is active

0

= LCD Driver module is inactive

WA:

LCD Write Allow Status bit

1

= Writing to the LCDDATAn registers is allowed

0

= Writing to the LCDDATAn registers is not allowed

LP<3:0>:

LCD Prescaler Selection bits

1111

= 1:16

1110

= 1:15

1101

= 1:14

1100

= 1:13

1011

= 1:12

1010

= 1:11

1001

= 1:10

1000

= 1:9

0111

= 1:8

0110

= 1:7

0101

= 1:6

0100

= 1:5

0011

= 1:4

0010

= 1:3

0001

= 1:2

0000

= 1:1

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PIC16LF1902/3

REGISTER 18-3:

R/W-0/0

LCDIRE bit 7

LCDREF: LCD REFERENCE VOLTAGE CONTROL REGISTER

U-0

R/W-0/0

LCDIRI

U-0

R/W-0/0

VLCD3PE

R/W-0/0

VLCD2PE

R/W-0/0

VLCD1PE

U-0

— bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

C = Only clearable bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

LCDIRE:

LCD Internal Reference Enable bit

1

= Internal LCD Reference is enabled and connected to the Internal Contrast Control circuit

0

= Internal LCD Reference is disabled

Unimplemented:

Read as ‘

0

LCDIRI:

LCD Internal Reference Ladder Idle Enable bit

Allows the Internal FVR buffer to shut down when the LCD Reference Ladder is in power mode ‘B’

1

= When the LCD Reference Ladder is in power mode ‘B’, the LCD Internal FVR buffer is disabled.

0

= The LCD Internal FVR Buffer ignores the LCD Reference Ladder Power mode.

Unimplemented:

Read as ‘

0

VLCD3PE:

VLCD3 Pin Enable bit

1

= The VLCD3 pin is connected to the internal bias voltage LCDBIAS3

(1)

0

= The VLCD3 pin is not connected

VLCD2PE:

VLCD2 Pin Enable bit

1

= The VLCD2 pin is connected to the internal bias voltage LCDBIAS2

(1)

0

= The VLCD2 pin is not connected

VLCD1PE:

VLCD1 Pin Enable bit

1

= The VLCD1 pin is connected to the internal bias voltage LCDBIAS1

(1)

0

= The VLCD1 pin is not connected

Unimplemented:

Read as ‘

0

Note 1:

Normal pin controls of TRISx and ANSELx are unaffected.

2011 Microchip Technology Inc.

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PIC16LF1902/3

REGISTER 18-4:

bit 7

U-0

LCDCST: LCD CONTRAST CONTROL REGISTER

U-0

U-0

U-0

U-0

R/W-0/0 R/W-0/0

LCDCST<2:0>

R/W-0/0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-3 bit 2-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

C = Only clearable bit

Unimplemented:

Read as ‘

0

LCDCST<2:0>:

LCD Contrast Control bits

Selects the resistance of the LCD contrast control resistor ladder

Bit Value = Resistor ladder

000

= Minimum Resistance (Maximum contrast). Resistor ladder is shorted.

001

= Resistor ladder is at 1/7th of maximum resistance

010

= Resistor ladder is at 2/7th of maximum resistance

011

= Resistor ladder is at 3/7th of maximum resistance

100

= Resistor ladder is at 4/7th of maximum resistance

101

= Resistor ladder is at 5/7th of maximum resistance

110

= Resistor ladder is at 6/7th of maximum resistance

111

= Resistor ladder is at maximum resistance (Minimum contrast).

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PIC16LF1902/3

REGISTER 18-5:

R/W-0/0

SEn bit 7

LCDSEn: LCD SEGMENT ENABLE REGISTERS

R/W-0/0

SEn

R/W-0/0

SEn

R/W-0/0

SEn

R/W-0/0

SEn

R/W-0/0

SEn

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

R/W-0/0

SEn

R/W-0/0

SEn bit 0

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

SEn:

Segment Enable bits

1

= Segment function of the pin is enabled

0

= I/O function of the pin is enabled

REGISTER 18-6: LCDDATAn: LCD DATA REGISTERS

R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u

SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy SEGx-COMy bit 7 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets bit 7-0

SEGx-COMy:

Pixel On bits

1

= Pixel on (dark)

0

= Pixel off (clear)

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18.2

LCD Clock Source Selection

The LCD module has 3 possible clock sources:

• F

OSC

/256

• T1OSC

• LFINTOSC

The first clock source is the system clock divided by

256 (F

OSC

/256). This divider ratio is chosen to provide about 1 kHz output when the system clock is 8 MHz.

The divider is not programmable. Instead, the LCD prescaler bits LP<3:0> of the LCDPS register are used to set the LCD frame clock rate.

The second clock source is the T1OSC. This also gives about 1 kHz when a 32.768 kHz crystal is used with the

Timer1 oscillator. To use the Timer1 oscillator as a clock source, the T1OSCEN bit of the T1CON register should be set.

The third clock source is the 31 kHz LFINTOSC, which provides approximately 1 kHz output.

The second and third clock sources may be used to continue running the LCD while the processor is in

Sleep.

FIGURE 18-2: LCD CLOCK GENERATION

Using bits CS<1:0> of the LCDCON register can select any of these clock sources.

18.2.1

LCD PRESCALER

A 4-bit counter is available as a prescaler for the LCD clock. The prescaler is not directly readable or writable; its value is set by the LP<3:0> bits of the LCDPS register, which determine the prescaler assignment and prescale ratio.

The prescale values are selectable from 1:1 through

1:16.

F

OSC

÷256

T1OSC 32 kHz

Crystal Osc.

LFINTOSC

Nominal = 31 kHz

CS<1:0>

To Ladder

Power Control

÷4

÷2

Static

1/2

1/3,

1/4

4-bit Prog

Prescaler

÷ 32

Counter

Segment

Clock

÷1, 2, 3, 4

Ring Counter

LP<3:0>

LMUX<1:0>

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PIC16LF1902/3

18.3

LCD Bias Voltage Generation

The LCD module can be configured for one of three bias types:

• Static Bias (2 voltage levels: V

SS

and V

LCD

)

• 1/2 Bias (3 voltage levels: V

SS

, 1/2 V

LCD

and

V

LCD

)

• 1/3 Bias (4 voltage levels: V

SS

, 1/3 V

LCD

,

2/3 V

LCD

and V

LCD

)

FIGURE 18-3:

TABLE 18-2: LCD BIAS VOLTAGES

LCD Bias 0

LCD Bias 1

LCD Bias 2

LCD Bias 3

Static Bias

V

SS

V

LCD

3

1/2 Bias

V

SS

1/2 V

DD

1/2 V

DD

V

LCD

3

1/3 Bias

V

SS

1/3 V

DD

2/3 V

DD

V

LCD

3

So that the user is not forced to place external components and use up to three pins for bias voltage generation, internal contrast control and an internal reference ladder are provided internally to the PIC16LF1902/3. Both of these features may be used in conjunction with the external VLCD<3:1> pins, to provide maximum flexibility. Refer to

Figure 18-3 .

LCD BIAS VOLTAGE GENERATION BLOCK DIAGRAM

V

DD

LCDIRE

LCDA

Power Mode Switching

(LRLAP or LRLBP)

2

A

B

2

2

LCDCST<2:0>

VLCD3PE

LCDA

VLCD3 lcdbias3

VLCD2

VLCD2PE lcdbias2

BIASMD

VLCD1

VLCD1PE lcdbias1 lcdbias0

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PIC16LF1902/3

18.4

LCD Bias Internal Reference

Ladder

The internal reference ladder can be used to divide the

LCD bias voltage two or three equally spaced voltages that will be supplied to the LCD segment pins. To create this, the reference ladder consists of three matched resistors. Refer to

Figure 18-3 .

18.4.1

BIAS MODE INTERACTION

When in 1/2 Bias mode (BIASMD =

1

), then the middle resistor of the ladder is shorted out so that only two voltages are generated. The current consumption of the ladder is higher in this mode, with the one resistor removed.

TABLE 18-3:

Power

Mode

Low

Medium

High

LCD INTERNAL LADDER

POWER MODES (1/3 BIAS)

Nominal Resistance of

Entire Ladder

3 Mohm

300 kohm

30 kohm

Nominal

I

DD

1 µA

10 µA

100 µA

18.4.2

POWER MODES

The internal reference ladder may be operated in one of three power modes. This allows the user to trade off LCD contrast for power in the specific application. The larger the LCD glass, the more capacitance is present on a physical LCD segment, requiring more current to maintain the same contrast level.

Three different power modes are available, LP, MP and

HP. The internal reference ladder can also be turned off for applications that wish to provide an external ladder or to minimize power consumption. Disabling the internal reference ladder results in all of the ladders being disconnected, allowing external voltages to be supplied.

Whenever the LCD module is inactive (LCDA = internal reference ladder will be turned off.

0

), the

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PIC16LF1902/3

18.4.3

AUTOMATIC POWER MODE

SWITCHING

As an LCD segment is electrically only a capacitor, current is drawn only during the interval where the voltage is switching. To minimize total device current, the LCD internal reference ladder can be operated in a different power mode for the transition portion of the duration.

This is controlled by the LCDRL Register

(

Register 18-7 ).

FIGURE 18-4:

The LCDRL register allows switching between two power modes, designated ‘A’ and ‘B’. ‘A’ Power mode is active for a programmable time, beginning at the time when the LCD segments transition. ‘B’ Power mode is the remaining time before the segments or commons change again. The LRLAT<2:0> bits select how long, if any, that the ‘A’ Power mode is active.

Refer to Figure 18-4

.

To implement this, the 5-bit prescaler used to divide the 32 kHz clock down to the LCD controller’s 1 kHz base rate is used to select the power mode.

LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM –

TYPE A

Single Segment Time

32 kHz Clock

Ladder Power

Control

Segment Clock

LRLAT<2:0>

Segment Data

‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07

‘H3

‘H0E ‘H0F ‘H00 ‘H01

LRLAT<2:0>

Power Mode A Power Mode

COM0

SEG0

COM0-SEG0

Power Mode B

V

1

V

0

V

1

V

0

V

1

V

0

-V

1

Mode A

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DS41455B-page 155

FIGURE 18-5: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE A WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE)

Single Segment Time Single Segment Time

32 kHz Clock

Ladder Power

Control

Segment Clock

Segment Data

‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H0E ‘H0F ‘H00 ‘H01 ‘H02 ‘H03 ‘H04 ‘H05 ‘H06 ‘H07 ‘H0E ‘H0F

Power Mode Power Mode A

LRLAT<2:0> =

011

Power Mode B Power Mode A

LRLAT<2:0> =

011

Power Mode B

COM0-SEG0

V

2

V

1

V

0

-V

1

-V

2

FIGURE 18-6: LCD INTERNAL REFERENCE LADDER POWER MODE SWITCHING DIAGRAM – TYPE B WAVEFORM (1/2 MUX, 1/2 BIAS DRIVE)

Single Segment Time

32 kHz Clock

Ladder Power

Control

Segment Clock

‘H00 ‘H01 ‘H02 ‘H03

Single Segment Time

‘H0E ‘H0F ‘H10 ‘H11 ‘H12 ‘H13 ‘H1E ‘H1F

Single Segment Time

‘H00 ‘H01 ‘H02 ‘H03 ‘H0E ‘H0F

Single Segment Time

‘H10 ‘H11 ‘H12 ‘H13 ‘H1E ‘H1F

Segment Data

Power Mode Power Mode A

LRLAT<2:0> =

011

Power Mode B Power Mode A

LRLAT<2:0> =

011

Power Mode B

Power Mode A

LRLAT<2:0> =

011

Power Mode B Power Mode A

LRLAT<2:0> =

011

Power Mode B

COM0-SEG0

V

2

V

1

V

0

-V

1

-V

2

PIC16LF1902/3

REGISTER 18-7: LCDRL: LCD REFERENCE LADDER CONTROL REGISTERS

R/W-0/0 R/W-0/0

LRLAP<1:0> bit 7

R/W-0/0 R/W-0/0

LRLBP<1:0>

U-0

R/W-0/0 R/W-0/0

LRLAT<2:0>

R/W-0/0 bit 0

Legend:

R = Readable bit u = Bit is unchanged

‘1’ = Bit is set bit 7-6 bit 5-4 bit 3 bit 2-0

W = Writable bit x = Bit is unknown

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

-n/n = Value at POR and BOR/Value at all other Resets

LRLAP<1:0>:

LCD Reference Ladder A Time Power Control bits

During Time interval A (Refer to

Figure 18-4 ):

00

= Internal LCD Reference Ladder is powered down and unconnected

01

= Internal LCD Reference Ladder is powered in Low-Power mode

10

= Internal LCD Reference Ladder is powered in Medium-Power mode

11

= Internal LCD Reference Ladder is powered in High-Power mode

LRLBP<1:0>:

LCD Reference Ladder B Time Power Control bits

During Time interval B (Refer to

Figure 18-4 ):

00

= Internal LCD Reference Ladder is powered down and unconnected

01

= Internal LCD Reference Ladder is powered in Low-Power mode

10

= Internal LCD Reference Ladder is powered in Medium-Power mode

11

= Internal LCD Reference Ladder is powered in High-Power mode

Unimplemented:

Read as ‘

0

LRLAT<2:0>:

LCD Reference Ladder A Time Interval Control bits

Sets the number of 32 kHz clocks that the A Time Interval Power mode is active

For type A waveforms (WFT =

0

):

000

= Internal LCD Reference Ladder is always in ‘B’ Power mode

001

= Internal LCD Reference Ladder is in ‘A’ Power mode for 1 clock and ‘B’ Power mode for 15 clocks

010

= Internal LCD Reference Ladder is in ‘A’ Power mode for 2 clocks and ‘B’ Power mode for 14 clocks

011

= Internal LCD Reference Ladder is in ‘A’ Power mode for 3 clocks and ‘B’ Power mode for 13 clocks

100

= Internal LCD Reference Ladder is in ‘A’ Power mode for 4 clocks and ‘B’ Power mode for 12 clocks

101

= Internal LCD Reference Ladder is in ‘A’ Power mode for 5 clocks and ‘B’ Power mode for 11 clocks

110

= Internal LCD Reference Ladder is in ‘A’ Power mode for 6 clocks and ‘B’ Power mode for 10 clocks

111

= Internal LCD Reference Ladder is in ‘A’ Power mode for 7 clocks and ‘B’ Power mode for 9 clocks

For type B waveforms (WFT =

1

):

000

= Internal LCD Reference Ladder is always in ‘B’ Power mode.

001

= Internal LCD Reference Ladder is in ‘A’ Power mode for 1 clock and ‘B’ Power mode for 31 clocks

010

= Internal LCD Reference Ladder is in ‘A’ Power mode for 2 clocks and ‘B’ Power mode for 30 clocks

011

= Internal LCD Reference Ladder is in ‘A’ Power mode for 3 clocks and ‘B’ Power mode for 29 clocks

100

= Internal LCD Reference Ladder is in ‘A’ Power mode for 4 clocks and ‘B’ Power mode for 28 clocks

101

= Internal LCD Reference Ladder is in ‘A’ Power mode for 5 clocks and ‘B’ Power mode for 27 clocks

110

= Internal LCD Reference Ladder is in ‘A’ Power mode for 6 clocks and ‘B’ Power mode for 26 clocks

111

= Internal LCD Reference Ladder is in ‘A’ Power mode for 7 clocks and ‘B’ Power mode for 25 clocks

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18.4.4

CONTRAST CONTROL

The LCD contrast control circuit consists of a seven-tap resistor ladder, controlled by the LCDCST

bits. Refer to Figure 18-7

.

The contrast control circuit is used to decrease the output voltage of the signal source by a total of approximately 10%, when LCDCST =

111

.

Whenever the LCD module is inactive (LCDA = contrast control ladder will be turned off (open).

0

), the

FIGURE 18-7:

V

DDIO

INTERNAL REFERENCE AND CONTRAST CONTROL BLOCK DIAGRAM

7 Stages

R R R R

3.072V

From FVR

Buffer

LCDCST<2:0>

3

Analog

MUX

7

To top of

Reference Ladder

0

Internal Reference

18.4.5

INTERNAL REFERENCE

Under firmware control, an internal reference for the

LCD bias voltages can be enabled. When enabled, the source of this voltage can be either V

DDIO

or a voltage one times the main fixed voltage reference (1.024V).

When no internal reference is selected, the LCD contrast control circuit is disabled and LCD bias must be provided externally.

Whenever the LCD module is inactive (LCDA = internal reference will be turned off.

0

), the

When the internal reference is enabled and the Fixed

Voltage Reference is selected, the LCDIRI bit can be used to minimize power consumption by tieing into the

LCD reference ladder automatic power mode switching.

When LCDIRI =

1

and the LCD reference ladder is in

Power mode ‘B’, the LCD internal FVR buffer is disables.

Contrast control

18.4.6

VLCD<3:1> PINS

The VLCD<3:1> pins provide the ability for an external

LCD bias network to be used instead of the internal ladder. Use of the VLCD<3:1> pins does not prevent use of the internal ladder. Each VLCD pin has an indepen-

dent control in the LCDREF register ( Register 18-3

), allowing access to any or all of the LCD Bias signals.

This architecture allows for maximum flexibility in different applications

For example, the VLCD<3:1> pins may be used to add capacitors to the internal reference ladder, increasing the drive capacity.

For applications where the internal contrast control is insufficient, the firmware can choose to only enable the

VLCD3 pin, allowing an external contrast control circuit to use the internal reference divider.

Note:

The LCD module automatically turns on the

Fixed Voltage Reference when needed.

2011 Microchip Technology Inc.

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PIC16LF1902/3

18.5

LCD Multiplex Types

The LCD Driver module can be configured into one of four multiplex types:

• Static (only COM0 is used)

• 1/2 multiplex (COM<1:0> are used)

• 1/3 multiplex (COM<2:0> are used)

• 1/4 multiplex (COM<3:0> are used)

The LMUX<1:0> bit setting of the LCDCON register decides which of the LCD common pins are used (see

Table 18-4

for details).

If the pin is a digital I/O, the corresponding TRIS bit controls the data direction. If the pin is a COM drive, then the TRIS setting of that pin is overridden.

TABLE 18-4:

Multiplex

LMUX

<1:0>

Static

1/2

1/3

1/4

00

01

10

11

COMMON PIN USAGE

COM3

Unused

Unused

Unused

Active

COM2

Unused

Unused

Active

Active

COM1

Unused

Active

Active

Active

COM1

Active

Active

Active

Active

18.6

Segment Enables

The LCDSEn registers are used to select the pin function for each segment pin. The selection allows each pin to operate as either an LCD segment driver or as one of the pin’s alternate functions. To configure the pin as a segment pin, the corresponding bits in the

LCDSEn registers must be set to ‘

1

’.

If the pin is a digital I/O, the corresponding TRIS bit controls the data direction. Any bit set in the LCDSEn registers overrides any bit settings in the corresponding

TRIS register.

Note:

On a Power-on Reset, these pins are configured as normal I/O, not LCD pins.

18.7

Pixel Control

The LCDDATAx registers contain bits which define the state of each pixel. Each bit defines one unique pixel.

Register 18-6

shows the correlation of each bit in the

LCDDATAx registers to the respective common and segment signals.

Any LCD pixel location not being used for display can be used as general purpose RAM.

18.8

LCD Frame Frequency

The rate at which the COM and SEG outputs change is called the LCD frame frequency.

TABLE 18-5:

Multiplex

Static

1/2

1/3

1/4

Note 1:

2:

FRAME FREQUENCY

FORMULAS

Frame Frequency

(2)

=

Clock source

(1)

/(4 x (LCD Prescaler) x 32 x 1))

Clock source

(1)

/(2 x (LCD Prescaler) x 32 x 2))

Clock source

(1)

/(1 x (LCD Prescaler) x 32 x 3))

Clock source

(1)

/(1 x (LCD Prescaler) x 32 x 4))

Clock source is F

OSC

/256, T1OSC or

LFINTOSC.

See

Figure 18-2

.

TABLE 18-6:

LP<3:0>

4

5

2

3

6

7

APPROXIMATE FRAME

FREQUENCY (IN Hz) USING

F

OSC

@ 8 MHz, TIMER1 @

32.768 kHz OR LFINTOSC

Static 1/2 1/3 1/4

122

81

61

49

41

35

122

81

61

49

41

35

162

108

81

65

54

47

122

81

61

49

41

35

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PIC16LF1902/3

SEG7

SEG8

SEG9

SEG10

SEG11

SEG12

SEG13

SEG14

SEG0

SEG1

SEG2

SEG3

SEG4

SEG5

SEG6

SEG15

SEG24

SEG25

SEG26

TABLE 18-7: LCD SEGMENT MAPPING WORKSHEET

LCD

Function

COM0

LCDDATAx

Address

LCDDATA0, 0

LCD

Segment

LCDDATA0, 1

LCDDATA0, 2

LCDDATA0, 3

LCDDATA0, 4

LCDDATA0, 5

LCDDATA0, 6

LCDDATA0, 7

LCDDATA1, 0

LCDDATA1, 1

LCDDATA1, 2

LCDDATA1, 3

LCDDATA1, 4

LCDDATA1, 5

LCDDATA1, 6

LCDDATA1, 7

LCDDATA2, 5

LCDDATA2, 6

LCDDATA2, 7

COM1

LCDDATAx

Address

LCDDATA3, 0

LCD

Segment

LCDDATA3, 1

LCDDATA3, 2

LCDDATA3, 3

LCDDATA3, 4

LCDDATA3, 5

LCDDATA3, 6

LCDDATA3, 7

LCDDATA4, 0

LCDDATA4, 1

LCDDATA4, 2

LCDDATA4, 3

LCDDATA4, 4

LCDDATA4, 5

LCDDATA4, 6

LCDDATA4, 7

LCDDATA5, 5

LCDDATA5, 6

LCDDATA5, 7

COM2

LCDDATAx

Address

LCDDATA6, 0

LCD

Segment

LCDDATA6, 1

LCDDATA6, 2

LCDDATA6, 3

LCDDATA6, 4

LCDDATA6, 5

LCDDATA6, 6

LCDDATA6, 7

LCDDATA7, 0

LCDDATA7, 1

LCDDATA7, 2

LCDDATA7, 3

LCDDATA7, 4

LCDDATA7, 5

LCDDATA7, 6

LCDDATA7, 7

LCDDATA8, 5

LCDDATA8, 6

LCDDATA8, 7

COM3

LCDDATAx

Address

LCDDATA9, 0

LCDDATA9, 1

LCDDATA9, 2

LCDDATA9, 3

LCDDATA9, 4

LCDDATA9, 5

LCDDATA9, 6

LCDDATA9, 7

LCDDATA10, 0

LCDDATA10, 1

LCDDATA10, 2

LCDDATA10, 3

LCDDATA10, 4

LCDDATA10, 5

LCDDATA10, 6

LCDDATA10, 7

LCDDATA11, 5

LCDDATA11, 6

LCDDATA11, 7

LCD

Segment

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18.9

LCD Waveform Generation

LCD waveforms are generated so that the net AC voltage across the dark pixel should be maximized and the net AC voltage across the clear pixel should be minimized. The net DC voltage across any pixel should be zero.

The COM signal represents the time slice for each common, while the SEG contains the pixel data.

The pixel signal (COM-SEG) will have no DC component and it can take only one of the two RMS values. The higher RMS value will create a dark pixel and a lower RMS value will create a clear pixel.

As the number of commons increases, the delta between the two RMS values decreases. The delta represents the maximum contrast that the display can have.

FIGURE 18-8:

The LCDs can be driven by two types of waveform:

Type-A and Type-B. In Type-A waveform, the phase changes within each common type, whereas in Type-B waveform, the phase changes on each frame boundary. Thus, Type-A waveform maintains 0 V

DC over a single frame, whereas Type-B waveform takes two frames.

Note 1:

2:

If Sleep has to be executed with LCD

Sleep disabled (LCDCON<SLPEN> is

1

’), then care must be taken to execute

Sleep only when V

DC

on all the pixels is

0

’.

When the LCD clock source is F

OSC

/256, if Sleep is executed, irrespective of the

LCDCON<SLPEN> setting, the LCD immediately goes into Sleep. Thus, take care to see that V

DC

on all pixels is ‘

0

’ when Sleep is executed.

Figure 18-8

through

Figure 18-18

provide waveforms for static, half-multiplex, 1/3-multiplex and 1/4-multiplex drives for Type-A and Type-B waveforms.

TYPE-A/TYPE-B WAVEFORMS IN STATIC DRIVE

COM0

COM0 pin

SEG0 pin

SEG1 pin

COM0-SEG0 segment voltage

(active)

COM0-SEG1 segment voltage

(inactive)

1 Frame

V

1

V

0

V

1

V

0

V

1

V

0

V

1

V

0

-V

1

V

0

DS41455B-page 162

Preliminary

2011 Microchip Technology Inc.

FIGURE 18-9:

COM1

COM0

PIC16LF1902/3

TYPE-A WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE

COM0 pin

COM1 pin

SEG0 pin

SEG1 pin

COM0-SEG0 segment voltage

(active)

COM0-SEG1 segment voltage

(inactive)

1 Frame

V

2

V

1

V

0

-V

1

-V

2

V

2

V

1

V

0

-V

1

-V

2

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

1 Segment Time

Note:

1 Frame = 2 single segment times.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 163

PIC16LF1902/3

FIGURE 18-10: TYPE-B WAVEFORMS IN 1/2 MUX, 1/2 BIAS DRIVE

COM1

COM0 pin

COM0

COM1 pin

SEG0 pin

SEG1 pin

COM0-SEG0 segment voltage

(active)

COM0-SEG1 segment voltage

(inactive)

Note:

1 Frame = 2 single segment times.

2 Frames

1 Segment Time

DS41455B-page 164

Preliminary

2011 Microchip Technology Inc.

V

2

V

1

V

0

-V

1

-V

2

V

2

V

1

V

0

-V

1

-V

2

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

PIC16LF1902/3

FIGURE 18-11: TYPE-A WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE

COM1

COM0

COM0 pin

COM1 pin

SEG0 pin

SEG1 pin

COM0-SEG0 segment voltage

(active)

COM0-SEG1 segment voltage

(inactive)

1 Frame

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

1 Segment Time

Note:

1 Frame = 2 single segment times.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 165

PIC16LF1902/3

FIGURE 18-12: TYPE-B WAVEFORMS IN 1/2 MUX, 1/3 BIAS DRIVE

COM1

COM0

COM0 pin

COM1 pin

SEG0 pin

SEG1 pin

COM0-SEG0 segment voltage

(active)

COM0-SEG1 segment voltage

(inactive)

Note:

1 Frame = 2 single segment times.

DS41455B-page 166

Preliminary

2 Frames

1 Segment Time

2011 Microchip Technology Inc.

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

PIC16LF1902/3

FIGURE 18-13: TYPE-A WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE

COM2

COM1

COM0

COM0 pin

COM1 pin

COM2 pin

SEG0 and

SEG2 pins

SEG1 pin

COM0-SEG0 segment voltage

(inactive)

COM0-SEG1 segment voltage

(active)

V

2

V

1

V

0

-V

1

-V

2

V

2

V

1

V

0

-V

1

-V

2

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

1 Frame

1 Segment Time

Note:

1 Frame = 2 single segment times.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 167

PIC16LF1902/3

FIGURE 18-14: TYPE-B WAVEFORMS IN 1/3 MUX, 1/2 BIAS DRIVE

COM0 pin

COM2

COM1

COM0

COM1 pin

COM2 pin

SEG0 pin

SEG1 pin

COM0-SEG0 segment voltage

(inactive)

COM0-SEG1 segment voltage

(active)

DS41455B-page 168

Note:

1 Frame = 2 single segment times.

Preliminary

2 Frames

1 Segment Time

2011 Microchip Technology Inc.

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

-V

1

-V

2

V

2

V

1

V

0

V

2

V

1

V

0

V

2

V

1

V

0

-V

1

-V

2

PIC16LF1902/3

FIGURE 18-15: TYPE-A WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE

COM2

COM1

COM0

COM0 pin

COM1 pin

COM2 pin

SEG0 and

SEG2 pins

SEG1 pin

COM0-SEG0 segment voltage

(inactive)

COM0-SEG1 segment voltage

(active)

V

0

V

3

V

2

V

1

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

1 Frame

1 Segment Time

Note:

1 Frame = 2 single segment times.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 169

PIC16LF1902/3

FIGURE 18-16: TYPE-B WAVEFORMS IN 1/3 MUX, 1/3 BIAS DRIVE

COM2

COM1

COM0

DS41455B-page 170

COM0 pin

COM1 pin

COM2 pin

SEG0 pin

SEG1 pin

COM0-SEG0 segment voltage

(inactive)

COM0-SEG1 segment voltage

(active)

Note:

1 Frame = 2 single segment times.

2 Frames

1 Segment Time

Preliminary

2011 Microchip Technology Inc.

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

PIC16LF1902/3

FIGURE 18-17:

COM3

COM2

TYPE-A WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE

COM0 pin

COM1

COM0

COM1 pin

COM2 pin

COM3 pin

SEG0 pin

SEG1 pin

COM0-SEG0 segment voltage

(active)

COM0-SEG1 segment voltage

(inactive)

1 Frame

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

1 Segment Time

Note:

1 Frame = 2 single segment times.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 171

PIC16LF1902/3

FIGURE 18-18:

COM3

COM2

TYPE-B WAVEFORMS IN 1/4 MUX, 1/3 BIAS DRIVE

COM0 pin

COM1 pin

COM1

COM0

COM2 pin

COM3 pin

SEG0 pin

SEG1 pin

COM0-SEG0 segment voltage

(active)

COM0-SEG1 segment voltage

(inactive)

2 Frames

1 Segment Time

Note:

1 Frame = 2 single segment times.

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

-V

1

-V

2

-V

3

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

DS41455B-page 172

Preliminary

2011 Microchip Technology Inc.

18.10 LCD Interrupts

The LCD module provides an interrupt in two cases. An interrupt when the LCD controller goes from active to inactive controller. An interrupt also provides unframe boundaries for Type B waveform. The LCD timing generation provides an interrupt that defines the LCD frame timing.

18.10.1

LCD INTERRUPT ON MODULE

SHUTDOWN

An LCD interrupt is generated when the module completes shutting down (LCDA goes from ‘

1

’ to ‘

0

’).

18.10.2

LCD FRAME INTERRUPTS

A new frame is defined to begin at the leading edge of the COM0 common signal. The interrupt will be set immediately after the LCD controller completes accessing all pixel data required for a frame. This will occur at a fixed interval before the frame boundary (T

FINT

), as

shown in Figure 18-19 . The LCD controller will begin to

access data for the next frame within the interval from the interrupt to when the controller begins to access data after the interrupt (T

FWR

). New data must be written within T

FWR

, as this is when the LCD controller will begin to access the data for the next frame.

When the LCD driver is running with Type-B waveforms and the LMUX<1:0> bits are not equal to ‘

00

’ (static drive), there are some additional issues that must be addressed. Since the DC voltage on the pixel takes two frames to maintain zero volts, the pixel data must not change between subsequent frames. If the pixel data were allowed to change, the waveform for the odd frames would not necessarily be the complement of the waveform generated in the even frames and a DC component would be introduced into the panel.

Therefore, when using Type-B waveforms, the user must synchronize the LCD pixel updates to occur within a subframe after the frame interrupt.

To correctly sequence writing while in Type-B, the interrupt will only occur on complete phase intervals. If the user attempts to write when the write is disabled, the WERR bit of the LCDCON register is set and the write does not occur.

Note:

The LCD frame interrupt is not generated when the Type-A waveform is selected and when the Type-B with no multiplex

(static) is selected.

PIC16LF1902/3

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 173

PIC16LF1902/3

FIGURE 18-19:

COM0

COM1

COM2

COM3

WAVEFORMS AND INTERRUPT TIMING IN QUARTER-DUTY CYCLE DRIVE

(EXAMPLE – TYPE-B, NON-STATIC)

LCD

Interrupt

Occurs

Controller Accesses

Next Frame Data

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

2 Frames

T

FWR

T

FINT

Frame

Boundary

Frame

Boundary

T

FWR

= T

FRAME

/2*(LMUX<1:0> + 1) + T

CY

/2

T

FINT

= (T

FWR

/2 – (2 T

CY

+ 40 ns))

 minimum = 1.5(T

FRAME

/4) – (2 T

CY

+ 40 ns)

(T

FWR

/2 – (1 T

CY

+ 40 ns))

 maximum = 1.5(T

FRAME

/4) – (1 T

CY

+ 40 ns)

Frame

Boundary

DS41455B-page 174

Preliminary

2011 Microchip Technology Inc.

18.11 Operation During Sleep

The LCD module can operate during Sleep. The selection is controlled by bit SLPEN of the LCDCON register. Setting the SLPEN bit allows the LCD module to go to Sleep. Clearing the SLPEN bit allows the module to continue to operate during Sleep.

If a

SLEEP

instruction is executed and SLPEN =

1

, the

LCD module will cease all functions and go into a very low-current Consumption mode. The module will stop operation immediately and drive the minimum LCD voltage on both segment and common lines.

Figure 18-20

shows this operation.

The LCD module can be configured to operate during

Sleep. The selection is controlled by bit SLPEN of the

LCDCON register. Clearing SLPEN and correctly configuring the LCD module clock will allow the LCD module to operate during Sleep. Setting SLPEN and correctly executing the LCD module shutdown will disable the LCD module during Sleep and save power.

If a

SLEEP

instruction is executed and SLPEN =

1

, the

LCD module will immediately cease all functions, drive the outputs to Vss and go into a very low-current mode.

The

SLEEP

instruction should only be executed after the LCD module has been disabled and the current cycle completed, thus ensuring that there are no DC voltages on the glass. To disable the LCD module, clear the LCDEN bit. The LCD module will complete the disabling process after the current frame, clear the

LCDA bit and optionally cause an interrupt.

The steps required to properly enter Sleep with the

LCD disabled are:

• Clear LCDEN

• Wait for LCDA =

0

either by polling or by interrupt

• Execute

SLEEP

If SLPEN =

0

and

SLEEP

is executed while the LCD module clock source is F

OSC

/4, then the LCD module will halt with the pin driving the last LCD voltage pattern. Prolonged exposure to a fixed LCD voltage pattern will cause damage to the LCD glass. To prevent

LCD glass damage, either perform the proper LCD module shutdown prior to Sleep, or change the LCD module clock to allow the LCD module to continue operation during Sleep.

If a

SLEEP

instruction is executed and SLPEN =

0

and the LCD module clock is either T1OSC or LFINTOSC, the module will continue to display the current contents of the LCDDATA registers. While in Sleep, the LCD data cannot be changed. If the LCDIE bit is set, the device will wake from Sleep on the next LCD frame boundary. The LCD module current consumption will not decrease in this mode; however, the overall device power consumption will be lower due to the shutdown of the CPU and other peripherals.

PIC16LF1902/3

Table 18-8

shows the status of the LCD module during a Sleep while using each of the three available clock sources.

Note:

When the LCDEN bit is cleared, the LCD module will be disabled at the completion of frame. At this time, the port pins will revert to digital functionality. To minimize power consumption due to floating digital inputs, the LCD pins should be driven low using the PORT and TRIS registers.

If a

SLEEP

instruction is executed and SLPEN =

0

, the module will continue to display the current contents of the LCDDATA registers. To allow the module to continue operation while in Sleep, the clock source must be either the LFINTOSC or T1OSC external oscillator. While in Sleep, the LCD data cannot be changed. The LCD module current consumption will not decrease in this mode; however, the overall consumption of the device will be lower due to shut down of the core and other peripheral functions.

Table 18-8

shows the status of the LCD module during

Sleep while using each of the three available clock sources:

TABLE 18-8:

Clock Source

T1OSC

LFINTOSC

F

OSC

/4

LCD MODULE STATUS

DURING SLEEP

SLPEN

0

1

0

1

0

1

Operational

During Sleep

Yes

No

Yes

No

No

No

Note:

The LFINTOSC or external T1OSC oscillator must be used to operate the

LCD module during Sleep.

If LCD interrupts are being generated (Type-B waveform with a multiplex mode not static) and LCDIE =

1

, the device will awaken from Sleep on the next frame boundary.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 175

PIC16LF1902/3

FIGURE 18-20: SLEEP ENTRY/EXIT WHEN SLPEN =

1

COM0

COM1

COM2

SEG0

2 Frames

SLEEP

Instruction Execution

Wake-up

V

3

V

2

V

1

V

0

V

3

V

2

V

1

V

0

V

0

V

3

V

2

V

1

V

0

V

3

V

2

V

1

DS41455B-page 176

Preliminary

2011 Microchip Technology Inc.

18.12 Configuring the LCD Module

The following is the sequence of steps to configure the

LCD module.

1.

2.

3.

4.

5.

6.

7.

Select the frame clock prescale using bits

LP<3:0> of the LCDPS register.

Configure the appropriate pins to function as segment drivers using the LCDSEn registers.

Configure the LCD module for the following using the LCDCON register:

- Multiplex and Bias mode, bits LMUX<1:0>

- Timing source, bits CS<1:0>

- Sleep mode, bit SLPEN

Write initial values to pixel data registers,

LCDDATA0 through LCDDATA21.

Clear LCD Interrupt Flag, LCDIF bit of the PIR2 register and if desired, enable the interrupt by setting bit LCDIE of the PIE2 register.

Configure bias voltages by setting the LCDRL,

LCDREF and the associated ANSELx registers as needed.

Enable the LCD module by setting bit LCDEN of the LCDCON register.

18.13 Disabling the LCD Module

To disable the LCD module, write all ‘

0

’s to the

LCDCON register.

PIC16LF1902/3

18.14 LCD Current Consumption

When using the LCD module the current consumption consists of the following three factors:

• Oscillator Selection

• LCD Bias Source

• Capacitance of the LCD segments

The current consumption of just the LCD module can be considered negligible compared to these other factors.

18.14.1

OSCILLATOR SELECTION

The current consumed by the clock source selected must be considered when using the LCD module. See

Section 21.0 “Electrical Specifications”

for oscillator

current consumption information.

18.14.2

LCD BIAS SOURCE

The LCD bias source, internal or external, can contribute significantly to the current consumption. Use the highest possible resistor values while maintaining contrast to minimize current.

18.14.3

CAPACITANCE OF THE LCD

SEGMENTS

The LCD segments which can be modeled as capacitors which must be both charged and discharged every frame. The size of the LCD segment and its technology determines the segment’s capacitance.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 177

PIC16LF1902/3

TABLE 18-9:

Name

SUMMARY OF REGISTERS ASSOCIATED WITH LCD OPERATION

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INTCON

LCDCON

LCDCST

LCDDATA0

LCDDATA1

LCDDATA3

LCDDATA4

LCDDATA6

LCDDATA7

LCDDATA9

LCDDATA10

LCDDATA12

LCDDATA15

LCDDATA18

LCDDATA21

LCDPS

LCDREF

LCDRL

LCDSE0

LCDSE1

LCDSE3

PIE2

PIR2

T1CON

Legend:

GIE

LCDEN

SEG7

COM0

SEG15

COM0

SEG7

COM1

SEG15

COM1

SEG7

COM2

SEG15

COM2

SEG7

COM3

SEG15

COM3

PEIE

SLPEN

SEG6

COM0

SEG14

COM0

SEG6

COM1

SEG14

COM1

SEG6

COM2

SEG14

COM2

SEG6

COM3

SEG14

COM3

TMR0IE

WERR

SEG5

COM0

SEG13

COM0

SEG5

COM1

SEG13

COM1

SEG5

COM2

SEG13

COM2

SEG5

COM3

SEG13

COM3

INTE

SEG4

COM0

SEG12

COM0

SEG4

COM1

SEG12

COM1

SEG4

COM2

SEG12

COM2

SEG4

COM3

SEG12

COM3

IOCIE

CS1

SEG3

COM0

SEG11

COM0

SEG3

COM1

SEG11

COM1

SEG3

COM2

SEG11

COM2

SEG3

COM3

SEG11

COM3

TMR0IF

CS0

INTF IOCIF

LMUX<1:0>

SEG2

COM0

SEG10

COM0

SEG2

COM1

SEG10

COM1

SEG2

COM2

SEG10

COM2

SEG2

COM3

SEG10

COM3

SEG26

COM0

SEG26

COM1

SEG26

COM2

SEG26

COM3

LCDCST<2:0>

SEG1

COM0

SEG9

COM0

SEG1

COM1

SEG9

COM1

SEG1

COM2

SEG9

COM2

SEG1

COM3

SEG9

COM3

SEG25

COM0

SEG25

COM1

SEG25

COM2

SEG25

COM3

LP<3:0>

VLCD2PE VLCD1PE

LRLAT<2:0>

SEG0

COM0

SEG8

COM0

SEG0

COM1

SEG8

COM1

SEG0

COM2

SEG8

COM2

SEG0

COM3

SEG8

COM3

SEG24

COM0

SEG24

COM1

SEG24

COM2

SEG24

COM3

WFT

LCDIRE

BIASMD

LRLAP<1:0>

LCDA

LCDIRI

WA

LRLBP<1:0>

VLCD3PE

SE<7:0>

SE<15:8>

LCDIE

LCDIF

SE<26:24>

TMR1CS1 TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC —

— = unimplemented location, read as ‘

0

’. Shaded cells are not used by the LCD module.

TMR1ON

Register on Page

66

147

150

151

151

151

151

151

151

151

151

151

151

151

151

151

151

68

70

141

148

149

158

151

DS41455B-page 178

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

19.0

IN-CIRCUIT SERIAL

PROGRAMMING™ (ICSP™)

ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming:

• ICSPCLK

• ICSPDAT

• MCLR/V

PP

• V

DD

• V

SS

In Program/Verify mode the Program Memory, User

IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSP™ refer to the

PIC16F193X/LF193X/PIC16F194X/LF194X/PIC16LF

190X Memory Programming Specification

(DS41397).

19.1

High-Voltage Programming Entry

Mode

The device is placed into High-Voltage Programming

Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/V

PP

to V

IHH

.

FIGURE 19-1: VPP LIMITER EXAMPLE CIRCUIT

Some programmers produce V

PP

greater than V

IHH

(9.0V), an external circuit is required to limit the V

PP voltage. See

Figure 19-1 for example circuit.

V

PP

V

DD

V

SS

ICSP_DATA

ICSP_CLOCK

NC

5

6

3

4

1

2

RJ11-6PIN

To MPLAB

®

ICD 2

3

2

1

6

5

4

RJ11-6PIN

To Target Board

R1

270 Ohm

6

7

2

3

LM431BCMX

A

A

A

A

U1

K

NC

NC

1

4

5

V

REF

8

R2 R3

10k 1% 24k 1%

Note:

The MPLAB

®

ICD 2 produces a V

PP voltage greater than the maximum V

PP specification of the PIC16LF1902/3.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 179

PIC16LF1902/3

19.2

Low-Voltage Programming Entry

Mode

The Low-Voltage Programming Entry mode allows the

PIC16LF1902/3 devices to be programmed using V

DD only, without high voltage. When the LVP bit of

Configuration Word 2 is set to ‘

1

’, the low-voltage ICSP programming entry is enabled. To disable the

Low-Voltage ICSP mode, the LVP bit must be programmed to ‘

0

’.

Entry into the Low-Voltage Programming Entry mode requires the following steps:

1.

2.

MCLR is brought to V

IL

.

A 32-bit key sequence is presented on

ICSPDAT, while clocking ICSPCLK.

Once the key sequence is complete, MCLR must be held at V

IL

for as long as Program/Verify mode is to be maintained.

If low-voltage programming is enabled (LVP =

1

), the

MCLR Reset function is automatically enabled and cannot be disabled. See

Section 5.3 “Ultra

Low-Power Brown-out Reset (ULPBOR)”

for more information.

The LVP bit can only be reprogrammed to ‘

0

’ by using the High-Voltage Programming mode.

19.3

Common Programming Interfaces

Connection to a target device is typically done through an ICSP™ header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6 pin, 6

connector) configuration. See Figure 19-2

.

FIGURE 19-3:

FIGURE 19-2:

Pin Description*

1 = V

PP

/MCLR

2 = V

DD

Target

3 = V

SS

(ground)

4 = ICSPDAT

5 = ICSPCLK

6 = No Connect

ICD RJ-11 STYLE

CONNECTOR INTERFACE

V

DD

V

PP

/MCLR

1

2 4

3 5

6

ICSPDAT

NC

ICSPCLK

V

SS

Target

PC Board

Bottom Side

Another connector often found in use with the PICkit™ programmers is a standard 6-pin header with 0.1 inch spacing. Refer to

Figure 19-3 .

PICkit™ STYLE CONNECTOR INTERFACE

Pin 1 Indicator

5

6

3

4

1

2

Pin Description*

1 = V

PP

/MCLR

2 = V

DD

Target

3 = V

SS

(ground)

4 = ICSPDAT

5 = ICSPCLK

6 = No Connect

* The 6-pin header (0.100" spacing) accepts 0.025" square pins.

DS41455B-page 180

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

For additional interface recommendations, refer to your specific device programmer manual prior to PCB design.

It is recommended that isolation devices be used to separate the programming pins from other circuitry.

The type of isolation is highly dependent on the specific application and may include devices such as resistors,

diodes, or even jumpers. See Figure 19-4

for more information.

FIGURE 19-4: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING

External

Programming

Signals

V

DD

V

PP

V

SS

Data

Clock

V

DD

Device to be

Programmed

V

DD

MCLR/V

PP

V

SS

ICSPDAT

ICSPCLK

*

*

To Normal Connections

*

*

Isolation devices (as required).

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 181

PIC16LF1902/3

NOTES:

DS41455B-page 182

Preliminary

2011 Microchip Technology Inc.

20.0

INSTRUCTION SET SUMMARY

Each PIC16 instruction is a 14-bit word containing the operation code (opcode) and all required operands.

The opcodes are broken into three broad categories.

• Byte Oriented

• Bit Oriented

• Literal and Control

The literal and control category contains the most varied instruction word format.

Table 20-3

lists the instructions recognized by the

MPASM TM assembler.

All instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles:

• Subroutine takes two cycles (

CALL

,

CALLW

)

• Returns from interrupts or subroutines take two cycles (

RETURN

,

RETLW

,

RETFIE

)

• Program branching takes two cycles (

GOTO

,

BRA

,

BRW

,

BTFSS

,

BTFSC

,

DECFSZ

,

INCSFZ

)

• One additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory.

One instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution rate of 1 MHz.

All instruction examples use the format ‘

0xhh

’ to represent a hexadecimal number, where ‘ h

’ signifies a hexadecimal digit.

PIC16LF1902/3

20.1

Read-Modify-Write Operations

Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register.

TABLE 20-1: OPCODE FIELD

DESCRIPTIONS

Field

f

W b k x d n mm

Description

Register file address (0x00 to 0x7F)

Working register (accumulator)

Bit address within an 8-bit file register

Literal field, constant data or label

Don’t care location (=

0

or

1

).

The assembler will generate code with x =

0

.

It is the recommended form of use for compatibility with all Microchip software tools.

Destination select; d =

0

: store result in

W

, d =

1

: store result in file register f.

Default is d =

1.

FSR or INDF number. (0-1)

Pre-post increment-decrement mode selection

TABLE 20-2: ABBREVIATION

DESCRIPTIONS

Field

PC

TO

C

DC

Z

PD

Program Counter

Time-out bit

Carry bit

Digit carry bit

Zero bit

Power-down bit

Description

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 183

PIC16LF1902/3

FIGURE 20-1: GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented file register operations

13 8 7 6 0

OPCODE d f (FILE #) d =

0

for destination W d =

1

for destination f f = 7-bit file register address

Bit-oriented file register operations

13 10 9 7 6 0

OPCODE b (BIT #) f (FILE #) b = 3-bit bit address f = 7-bit file register address

Literal and control operations

General

13 8 7 0

OPCODE k (literal) k = 8-bit immediate value

CALL

and

GOTO

instructions only

13 11 10 0

OPCODE k (literal) k = 11-bit immediate value

MOVLP

instruction only

13 7 6 0

OPCODE k (literal) k = 7-bit immediate value

MOVLB

instruction only

13 5 4 0

OPCODE k (literal) k = 5-bit immediate value

BRA

instruction only

13 9 8 0

OPCODE k (literal) k = 9-bit immediate value

FSR

Offset instructions

13 7 6 5 0

OPCODE n k (literal) n = appropriate

FSR k = 6-bit immediate value

FSR

Increment instructions

13 3 2 1 0

OPCODE n m (mode) n = appropriate

FSR m = 2-bit mode value

OPCODE only

13 0

OPCODE

DS41455B-page 184

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

TABLE 20-3:

Mnemonic,

Operands

PIC16LF1902/3 ENHANCED INSTRUCTION SET

Description Cycles

MSb

14-Bit Opcode

LSb

Status

Affected

Notes

f f, d f, d f, d f, d f, d f, d f, d f, d f, d f, d f, d f

– f, d f, d f, d f, d f, d f, d

ADDWF

ADDWFC

ANDWF

ASRF

LSLF

LSRF

CLRF

CLRW

COMF

DECF

INCF

IORWF

MOVF

MOVWF

RLF

RRF

SUBWF

SUBWFB

SWAPF

XORWF

BYTE-ORIENTED FILE REGISTER OPERATIONS

Add W and f

Add with Carry W and f

AND W with f

Arithmetic Right Shift

Logical Left Shift

Logical Right Shift

Clear f

Clear W

Complement f

Decrement f

Increment f

Inclusive OR W with f

Move f

Move W to f

Rotate Left f through Carry

Rotate Right f through Carry

Subtract W from f

Subtract with Borrow W from f

Swap nibbles in f

Exclusive OR W with f

BYTE ORIENTED SKIP OPERATIONS

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

00

00

00

00

00

00

00

11

00

11

11

11

00

00

00

00

00

11

00

00

Decrement f, Skip if 0

Increment f, Skip if 0

1(2)

1(2)

00

00

1011

1111

0111

1101

0101

0111

0101

0110

0001

0001

1001

0011

1010

0100

1000

0000

1101

1100

0010

1011

1110

0110 dfff dfff ffff ffff ffff ffff ffff ffff ffff ffff ffff

00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff dfff dfff dfff dfff dfff dfff lfff

0000 dfff dfff dfff dfff dfff

1fff dfff dfff dfff dfff dfff dfff

Z

Z

Z

Z

Z

C, DC, Z

C, DC, Z

Z

C, Z

Z

Z

C, Z

C, Z

C

C

C, DC, Z

C, DC, Z

Z

2

2

2

2

2

2

2

DECFSZ

INCFSZ f, d f, d

1, 2

1, 2

BCF

BSF f, b f, b

Bit Clear f

Bit Set f

BIT-ORIENTED FILE REGISTER OPERATIONS

1

1

01

01

00bb

01bb bfff bfff ffff ffff

2

2

BIT-ORIENTED SKIP OPERATIONS

BTFSC

BTFSS f, b f, b

LITERAL OPERATIONS

Bit Test f, Skip if Clear

Bit Test f, Skip if Set

ADDLW

ANDLW

IORLW

MOVLB

MOVLP

MOVLW

SUBLW

XORLW

Note 1:

2:

k k k k k k k k

Add literal and W

AND literal with W

Inclusive OR literal with W

Move literal to BSR

Move literal to PCLATH

Move literal to W

Subtract W from literal

Exclusive OR literal with W

1 (2)

1 (2)

1

1

1

1

1

1

1

1

01

01

11

11

11

00

11

11

11

11

10bb

11bb

1110

1001

1000

0000

0001

0000

1100

1010 bfff bfff kkkk kkkk kkkk

001k

1kkk kkkk kkkk kkkk ffff ffff kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk

C, DC, Z

Z

Z

C, DC, Z

Z

1, 2

1, 2

If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a

NOP

.

If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle.

2

2

2

2

2

2

2

2

2

2

2

2

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 185

PIC16LF1902/3

TABLE 20-3: PIC16LF1902/3 ENHANCED INSTRUCTION SET (CONTINUED)

Mnemonic,

Operands

Description Cycles

14-Bit Opcode

Status

Affected

Notes

MSb LSb

BRA

BRW

CALL

CALLW

GOTO

RETFIE

RETLW

RETURN k

– k

– k k k

Relative Branch

Relative Branch with W

Call Subroutine

Call Subroutine with W

Go to address

Return from interrupt

Return with literal in W

Return from Subroutine

CONTROL OPERATIONS

2

2

2

2

2

2

2

2

INHERENT OPERATIONS

11

00

10

00

10

00

11

00

001k

0000

0kkk

0000

1kkk

0000

0100

0000 kkkk

0000 kkkk

0000 kkkk

0000 kkkk

0000 kkkk

1011 kkkk

1010 kkkk

1001 kkkk

1000

CLRWDT

NOP

OPTION

RESET

SLEEP

TRIS

– f

Clear Watchdog Timer

No Operation

Load OPTION_REG register with W

Software device Reset

Go into Standby mode

Load TRIS register with W

1

1

1

1

1

1

00

00

00

00

00

00

0000

0000

0000

0000

0000

0000

0110

0000

0110

0000

0110

0110

0100

0000

0010

0001

0011

0fff

TO, PD

TO, PD

ADDFSR

MOVIW

MOVWI

Note 1:

2:

3:

n, k n mm k[n] n mm

Add Literal k to FSRn

C-COMPILER OPTIMIZED

Move Indirect FSRn to W with pre/post inc/dec modifier, mm

Move INDFn to W, Indexed Indirect.

Move W to Indirect FSRn with pre/post inc/dec modifier, mm

Move W to INDFn, Indexed Indirect.

1

1

1

1

1

11

00

11

00

0001

0000

1111

0000

0nkk

0001

0nkk

0001 kkkk

0nmm kkkk

1nmm

Z

Z

2, 3

2

2, 3

k[n]

11 1111 1nkk kkkk

2

If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a

NOP

.

If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle.

See Table in the MOVIW and MOVWI instruction descriptions.

DS41455B-page 186

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

20.2

ADDFSR

Syntax:

Operands:

Instruction Descriptions

Operation:

Status Affected:

Description:

Add Literal to FSRn

[

label

] ADDFSR FSRn, k

-32

k

31 n

[ 0, 1]

FSR(n) + k

FSR(n)

None

The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair.

FSRn is limited to the range 0000h -

FFFFh. Moving beyond these bounds will cause the FSR to wrap-around.

ADDLW

Syntax:

Operands:

Operation:

Status Affected:

Description:

Add literal and W

[

label

] ADDLW k

0

k

255

(W) + k

(W)

C, DC, Z

The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register.

ADDWF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Add W and f

[

label

] ADDWF f,d

0

f

127 d



0

,

1

(W) + (f)

(destination)

C, DC, Z

Add the contents of the W register with register ‘f’. If ‘d’ is ‘

0

’, the result is stored in the W register. If ‘d’ is ‘

1

’, the result is stored back in register ‘f’.

ADDWFC

Syntax:

Operands:

Operation:

Status Affected:

Description:

ADD W and CARRY bit to f

[

label

] ADDWFC f {,d}

0

f

127 d



[0,1]

(W) + (f) + (C)

dest

C, DC, Z

Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘

0

’, the result is placed in W. If ‘d’ is ‘

1

’, the result is placed in data memory location ‘f’.

2011 Microchip Technology Inc.

Preliminary

ANDLW

Syntax:

Operands:

Operation:

Status Affected:

Description:

AND literal with W

[

label

] ANDLW k

0

k

255

(W) .AND. (k)

(W)

Z

The contents of W register are

AND’ed with the eight-bit literal ‘k’.

The result is placed in the W register.

ANDWF

Syntax:

Operands:

Operation:

Status Affected:

Description:

AND W with f

[

label

] ANDWF f,d

0

f

127 d



0

,

1

(W) .AND. (f)

(destination)

Z

AND the W register with register ‘f’. If

‘d’ is ‘

0

’, the result is stored in the W register. If ‘d’ is ‘

1

’, the result is stored back in register ‘f’.

ASRF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Arithmetic Right Shift

[

label

] ASRF f {,d}

0

f

127 d



[0,1]

(f<7>)

dest<7>

(f<7:1>)

dest<6:0>,

(f<0>)

C,

C, Z

The contents of register ‘f’ are shifted one bit to the right through the Carry flag. The MSb remains unchanged. If

‘d’ is ‘

0

’, the result is placed in W. If ‘d’ is ‘

1

’, the result is stored back in register ‘f’.

register f

C

DS41455B-page 187

PIC16LF1902/3

BCF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Bit Clear f

[

label

] BCF f,b

0

f

127

0

b

7

0

(f<b>)

None

Bit ‘b’ in register ‘f’ is cleared.

BRA

Syntax:

Operands:

Operation:

Status Affected:

Description:

Relative Branch

[

label

] BRA label

[

label

] BRA $+k

-256

 label - PC + 1

255

-256

k

255

(PC) + 1 + k

PC

None

Add the signed 9-bit literal ‘k’ to the

PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + k.

This instruction is a two-cycle instruction. This branch has a limited range.

BRW

Syntax:

Operands:

Operation:

Status Affected:

Description:

Relative Branch with W

[

label

] BRW

None

(PC) + (W)

PC

None

Add the contents of W (unsigned) to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + (W).

This instruction is a two-cycle instruction.

BSF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Bit Set f

[

label

] BSF f,b

0

f

127

0

b

7

1

(f<b>)

None

Bit ‘b’ in register ‘f’ is set.

BTFSC

Syntax:

Operands:

Operation:

Status Affected:

Description:

Bit Test f, Skip if Clear

[

label

] BTFSC f,b

0

f

127

0

b

7 skip if (f<b>) =

0

None

If bit ‘b’ in register ‘f’ is ‘

1

’, the next instruction is executed.

If bit ‘b’, in register ‘f’, is ‘

0

’, the next instruction is discarded, and a

NOP

is executed instead, making this a

2-cycle instruction.

BTFSS

Syntax:

Operands:

Operation:

Status Affected:

Description:

Bit Test f, Skip if Set

[

label

] BTFSS f,b

0

f

127

0

b < 7 skip if (f<b>) =

1

None

If bit ‘b’ in register ‘f’ is ‘

0

’, the next instruction is executed.

If bit ‘b’ is ‘

1

’, then the next instruction is discarded and a

NOP

is executed instead, making this a

2-cycle instruction.

DS41455B-page 188

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

CALL

Syntax:

Operands:

Operation:

Status Affected:

Description:

Call Subroutine

[

label

] CALL k

0

k

2047

(PC)+ 1

TOS, k

PC<10:0>,

(PCLATH<6:3>)

PC<14:11>

None

Call Subroutine. First, return address

(PC + 1) is pushed onto the stack.

The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from

PCLATH.

CALL

is a two-cycle instruction.

CALLW

Syntax:

Operands:

Operation:

Status Affected:

Description:

Subroutine Call With W

[

label

] CALLW

None

(PC) +1

TOS,

(W)

PC<7:0>,

(PCLATH<6:0>)



PC<14:8>

None

Subroutine call with W. First, the return address (PC + 1) is pushed onto the return stack. Then, the contents of W is loaded into PC<7:0>, and the contents of PCLATH into

PC<14:8>.

CALLW

is a two-cycle instruction.

CLRF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Clear f

[

label

] CLRF f

0

f

127

00h

(f)

1

Z

Z

The contents of register ‘f’ are cleared and the Z bit is set.

CLRW

Syntax:

Operands:

Operation:

Status Affected:

Description:

Clear W

[

label

] CLRW

None

00h

(W)

1

Z

Z

W register is cleared. Zero bit (Z) is set.

CLRWDT

Syntax:

Operands:

Operation:

Status Affected:

Description:

Clear Watchdog Timer

[

label

] CLRWDT

None

00h

WDT

0

WDT prescaler,

1

TO

1

PD

TO, PD

CLRWDT

instruction resets the Watchdog Timer. It also resets the prescaler of the WDT.

Status bits TO and PD are set.

COMF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Complement f

[

label

] COMF f,d

0

f

127 d

[

0

,

1

]

(f)

(destination)

Z

The contents of register ‘f’ are complemented. If ‘d’ is ‘

0

’, the result is stored in W. If ‘d’ is ‘

1

’, the result is stored back in register ‘f’.

DECF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Decrement f

[

label

] DECF f,d

0

f

127 d

[

0

,

1

]

(f) - 1

(destination)

Z

Decrement register ‘f’. If ‘d’ is ‘

0

’, the result is stored in the W register. If ‘d’ is ‘

1

’, the result is stored back in register ‘f’.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 189

PIC16LF1902/3

DECFSZ

Syntax:

Operands:

Operation:

Status Affected:

Description:

Decrement f, Skip if 0

[

label

] DECFSZ f,d

0

f

127 d

[

0

,

1

]

(f) - 1

(destination); skip if result =

0

None

The contents of register ‘f’ are decremented. If ‘d’ is ‘

0

’, the result is placed in the W register. If ‘d’ is ‘

1

’, the result is placed back in register ‘f’.

If the result is ‘

1

’, the next instruction is executed. If the result is ‘

0

’, then a

NOP

is executed instead, making it a

2-cycle instruction.

GOTO

Syntax:

Operands:

Operation:

Status Affected:

Description:

Unconditional Branch

[

label

] GOTO k

0

k

2047 k

PC<10:0>

PCLATH<6:3>

PC<14:11>

None

GOTO

is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of

PC are loaded from PCLATH<4:3>.

GOTO

is a two-cycle instruction.

INCF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Increment f

[

label

] INCF f,d

0

f

127 d

[

0

,

1

]

(f) + 1

(destination)

Z

The contents of register ‘f’ are incremented. If ‘d’ is ‘

0

’, the result is placed in the W register. If ‘d’ is ‘

1

’, the result is placed back in register ‘f’.

INCFSZ

Syntax:

Operands:

Operation:

Status Affected:

Description:

Increment f, Skip if 0

[

label

] INCFSZ f,d

0

f

127 d

[

0

,

1

]

(f) + 1

(destination),

skip if result =

0

None

The contents of register ‘f’ are incremented. If ‘d’ is ‘

0

’, the result is placed in the W register. If ‘d’ is ‘

1

’, the result is placed back in register ‘f’.

If the result is ‘

1

’, the next instruction is executed. If the result is ‘

0

’, a

NOP

is executed instead, making it a 2-cycle instruction.

IORLW

Syntax:

Operands:

Operation:

Status Affected:

Description:

Inclusive OR literal with W

[

label

] IORLW k

0

k

255

(W) .OR. k

(W)

Z

The contents of the W register are

OR’ed with the eight-bit literal ‘k’. The result is placed in the W register.

IORWF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Inclusive OR W with f

[

label

] IORWF f,d

0

f

127 d

[

0

,

1

]

(W) .OR. (f)

(destination)

Z

Inclusive OR the W register with register ‘f’. If ‘d’ is ‘

0

’, the result is placed in the W register. If ‘d’ is ‘

1

’, the result is placed back in register ‘f’.

DS41455B-page 190

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

LSLF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Logical Left Shift

[

label

] LSLF f {,d}

0

f

127 d



[0,1]

(f<7>)

C

(f<6:0>)

dest<7:1>

0

dest<0>

C, Z

The contents of register ‘f’ are shifted one bit to the left through the Carry flag.

A ‘

0

’ is shifted into the LSb. If ‘d’ is ‘

0

’, the result is placed in W. If ‘d’ is ‘

1

’, the result is stored back in register ‘f’.

C register f 0

LSRF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Logical Right Shift

[

label

] LSLF f {,d}

0

f

127 d



[0,1]

0

dest<7>

(f<7:1>)

dest<6:0>,

(f<0>)

C,

C, Z

The contents of register ‘f’ are shifted one bit to the right through the Carry flag. A ‘

0

’ is shifted into the MSb. If ‘d’ is

0

’, the result is placed in W. If ‘d’ is ‘

1

’, the result is stored back in register ‘f’.

0 register f

C

MOVF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Words:

Cycles:

Example:

Move f

1

1

[

label

] MOVF f,d

0

f

127 d

[

0

,

1

]

(f)

(dest)

Z

The contents of register f is moved to a destination dependent upon the status of d. If d =

0

, destination is W register. If d =

1

, the destination is file register f itself. d =

1 is useful to test a file register since status flag Z is affected.

MOVF FSR, 0

After Instruction

W = value in FSR register

Z =

1

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 191

PIC16LF1902/3

MOVIW

Syntax:

Operands:

Operation:

Status Affected:

Mode

Preincrement

Predecrement

Postincrement

Postdecrement

Description:

MOVLB

Syntax:

Operands:

Operation:

Status Affected:

Description:

Move INDFn to W

[

label

] MOVIW ++FSRn

[

label

] MOVIW --FSRn

[

label

] MOVIW FSRn++

[

label

] MOVIW FSRn--

[

label

] MOVIW k[FSRn] n

[

0

,

1

] mm

[

00

,

01

,

10

,

11

]

-32

k

31

INDFn

W

Effective address is determined by

• FSR + 1 (preincrement)

• FSR - 1 (predecrement)

• FSR + k (relative offset)

After the Move, the FSR value will be either:

• FSR + 1 (all increments)

• FSR - 1 (all decrements)

• Unchanged

Z

Syntax

++FSRn

--FSRn

FSRn++

FSRn--

mm

00

01

10

11

This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it.

Note:

The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn.

FSRn is limited to the range 0000h -

FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap-around.

Move literal to BSR

[

label

] MOVLB k

0

k

15 k

BSR

None

The five-bit literal ‘k’ is loaded into the

Bank Select Register (BSR).

MOVLP

Syntax:

Operands:

Operation:

Status Affected:

Description:

Move literal to PCLATH

[

label

] MOVLP k

0

k

127 k

PCLATH

None

The seven-bit literal ‘k’ is loaded into the

PCLATH register.

MOVLW

Syntax:

Operands:

Operation:

Status Affected:

Description:

Words:

Cycles:

Example:

Move literal to W

1

1

[

label

] MOVLW k

0

k

255 k

(W)

None

The eight-bit literal ‘k’ is loaded into W register. The “don’t cares” will assemble as ‘

0

’s.

MOVLW 0x5A

After Instruction

W = 0x5A

MOVWF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Words:

Cycles:

Example:

Move W to f

1

1

[

label

] MOVWF f

0

f

127

(W)

(f)

None

Move data from W register to register

‘f’.

MOVWF OPTION_REG

Before Instruction

OPTION_REG = 0xFF

W = 0x4F

After Instruction

OPTION_REG = 0x4F

W = 0x4F

DS41455B-page 192

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

MOVWI

Syntax:

Operands:

Operation:

Status Affected:

Mode

Preincrement

Predecrement

Postincrement

Postdecrement

Description:

Move W to INDFn

[

label

] MOVWI ++FSRn

[

label

] MOVWI --FSRn

[

label

] MOVWI FSRn++

[

label

] MOVWI FSRn--

[

label

] MOVWI k[FSRn] n

[

0

,

1

] mm

[

00

,

01

,

10

,

11

]

-32

k

31

W

INDFn

Effective address is determined by

• FSR + 1 (preincrement)

• FSR - 1 (predecrement)

• FSR + k (relative offset)

After the Move, the FSR value will be either:

• FSR + 1 (all increments)

• FSR - 1 (all decrements)

Unchanged

None

Syntax

++FSRn

--FSRn

FSRn++

FSRn--

mm

00

01

10

11

This instruction is used to move data between W and one of the indirect registers (INDFn). Before/after this move, the pointer (FSRn) is updated by pre/post incrementing/decrementing it.

Note:

The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn.

FSRn is limited to the range 0000h -

FFFFh. Incrementing/decrementing it beyond these bounds will cause it to wrap-around.

The increment/decrement operation on

FSRn WILL NOT affect any Status bits.

NOP

Syntax:

Operands:

Operation:

Status Affected:

Description:

Words:

Cycles:

Example:

No Operation

[

label

] NOP

None

No operation

None

No operation.

1

1

NOP

OPTION

Syntax:

Operands:

Operation:

Status Affected:

Description:

Words:

Cycles:

Example:

RESET

Syntax:

Operands:

Operation:

Status Affected:

Description:

Load OPTION_REG Register with W

[

label

] OPTION

None

(W)

OPTION_REG

None

Move data from W register to

OPTION_REG register.

1

1

OPTION

Before Instruction

OPTION_REG = 0xFF

W = 0x4F

After Instruction

OPTION_REG = 0x4F

W = 0x4F

Software Reset

[

label

] RESET

None

Execute a device Reset. Resets the nRI flag of the PCON register.

None

This instruction provides a way to execute a hardware Reset by software.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 193

PIC16LF1902/3

RETFIE

Syntax:

Operands:

Operation:

Status Affected:

Description:

Words:

Cycles:

Example:

Return from Interrupt

1

2

[

label

] RETFIE k

None

TOS

PC,

1

GIE

None

Return from Interrupt. Stack is POPed and Top-of-Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global

Interrupt Enable bit, GIE

(INTCON<7>). This is a two-cycle instruction.

RETFIE

After Interrupt

PC =

GIE =

TOS

1

RETLW

Syntax:

Operands:

Operation:

Status Affected:

Description:

Words:

Cycles:

Example:

TABLE

Return with literal in W

1

2

[

label

] RETLW k

0

k

255 k

(W);

TOS

PC

None

The W register is loaded with the eight bit literal ‘k’. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction.

CALL TABLE;W contains table

;offset value

;W now has table value

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

RETLW kn ; End of table

Before Instruction

W =

After Instruction

W =

0x07 value of k8

RETURN

Syntax:

Operands:

Operation:

Status Affected:

Description:

Return from Subroutine

[

label

] RETURN

None

TOS

PC

None

Return from subroutine. The stack is

POPed and the top of the stack (TOS) is loaded into the program counter.

This is a two-cycle instruction.

RLF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Words:

Cycles:

Example:

Rotate Left f through Carry

[

label

]

0

f

127 d

[

0

,

1

]

RLF f,d

See description below

C

The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘

0

’, the result is placed in the W register. If ‘d’ is ‘

1

’, the result is stored back in register ‘f’.

C Register f

1

1

RLF REG1,0

Before Instruction

REG1

C

After Instruction

REG1

W

C

=

=

=

=

=

1110 0110

0

1110 0110

1100 1100

1

DS41455B-page 194

Preliminary

2011 Microchip Technology Inc.

RRF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Rotate Right f through Carry

[

label

] RRF f,d

0

f

127 d

[

0

,

1

]

See description below

C

The contents of register ‘f’ are rotated one bit to the right through the Carry flag. If ‘d’ is ‘

0

’, the result is placed in the W register. If ‘d’ is ‘

1

’, the result is placed back in register ‘f’.

C Register f

SLEEP

Syntax:

Operands:

Operation:

Status Affected:

Description:

Enter Sleep mode

[

label

] SLEEP

None

00h

WDT,

0

WDT prescaler,

1

TO,

0

PD

TO, PD

The power-down Status bit, PD is cleared. Time-out Status bit, TO is set. Watchdog Timer and its prescaler are cleared.

The processor is put into Sleep mode with the oscillator stopped.

PIC16LF1902/3

SUBLW

Syntax:

Operands:

Operation:

Status Affected:

Description:

Subtract W from literal

[

label

] SUBLW k

0

 k



255 k - (W)



W)

C, DC, Z

The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register.

C =

C =

0

1

DC =

DC =

0

1

W

k

W

k

W<3:0>

k<3:0>

W<3:0>

k<3:0>

SUBWF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Subtract W from f

[

label

]

0

 f



127 d

[

0

,

1

]

SUBWF f,d

(f) - (W)

 destination)

C, DC, Z

Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is ‘

0

’, the result is stored in the W register. If ‘d’ is ‘

1

’, the result is stored back in register ‘f.

C =

C =

0

1

DC =

DC =

0

1

W

f

W

f

W<3:0>

f<3:0>

W<3:0>

f<3:0>

SUBWFB

Syntax:

Operands:

Operation:

Status Affected:

Description:

Subtract W from f with Borrow

SUBWFB f {,d}

0

f

127 d

[0,1]

(f) – (W) – (B)

 dest

C, DC, Z

Subtract W and the BORROW flag

(CARRY) from register ‘f’ (2’s complement method). If ‘d’ is ‘

0

’, the result is stored in W. If ‘d’ is ‘

1

’, the result is stored back in register ‘f’.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 195

PIC16LF1902/3

SWAPF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Swap Nibbles in f

[

label

] SWAPF

0

f

127 d

[

0

,

1

]

(f<3:0>)

(destination<7:4>),

(f<7:4>)

(destination<3:0>)

None

The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘

0

’, the result is placed in the W register. If ‘d’ is ‘

1

’, the result is placed in register ‘f’.

TRIS

Syntax:

Operands:

Operation:

Status Affected:

Description:

Load TRIS Register with W

[

label

] TRIS f

5

f

7

(W)

TRIS register ‘f’

None

Move data from W register to TRIS register.

When ‘f’ = 5, TRISA is loaded.

When ‘f’ = 6, TRISB is loaded.

When ‘f’ = 7, TRISC is loaded.

XORLW

Syntax:

Operands:

Operation:

Status Affected:

Description:

Exclusive OR literal with W

[

label

] XORLW k

0

 k



255

(W) .XOR. k



W)

Z

The contents of the W register are

XOR’ed with the eight-bit literal ‘k’. The result is placed in the

W register.

XORWF

Syntax:

Operands:

Operation:

Status Affected:

Description:

Exclusive OR W with f

[

label

] XORWF f,d

0

f

127 d

[

0

,

1

]

(W) .XOR. (f)

 destination)

Z

Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘

0

’, the result is stored in the W register. If ‘d’ is ‘

1

’, the result is stored back in register ‘f’.

DS41455B-page 196

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

21.0

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

(†)

Ambient temperature under bias....................................................................................................... -40°C to +125°C

Storage temperature ........................................................................................................................ -65°C to +150°C

Voltage on V

DD

with respect to V

SS

................................................................................................... -0.3V to +4.0V

Voltage on MCLR with respect to Vss ................................................................................................. -0.3V to +9.0V

Voltage on all other pins with respect to V

SS

........................................................................... -0.3V to (V

DD

+ 0.3V)

Total power dissipation

(1)

............................................................................................................................... 800 mW

Maximum current out of V

SS

pin, -40°C

T

A

+85°C for industrial............................................................... 300 mA

Maximum current out of V

SS

pin, -40°C

T

A

+125°C for extended .............................................................. 95 mA

Maximum current into V

DD

pin, -40°C

T

A

+85°C for industrial.................................................................. 250 mA

Maximum current into V

DD

pin, -40°C

T

A

+125°C for extended ................................................................. 70 mA

Clamp current, I

K

(V

PIN

< 0 or V

PIN

> V

DD

)



20 mA

Maximum output current sunk by any I/O pin.................................................................................................... 25 mA

Maximum output current sourced by any I/O pin .............................................................................................. 25 mA

Note 1:

Power dissipation is calculated as follows: P

DIS

= V

DD

x {I

DD

I

OH

} +

{(V

DD

– V

OH

) x I

OH

} +

(V

O l x I

OL

).

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 197

PIC16LF1902/3

FIGURE 21-1: VOLTAGE FREQUENCY GRAPH, -40°C

T

A



+125°C

3.6

2.5

2.3

EC Mode

Only

Internal Oscillator or EC Mode

2.0

1.8

0 4

10

Frequency (MHz)

16 20

Note 1:

2:

The shaded region indicates the permissible combinations of voltage and frequency.

Refer to

Table 21-1 for each Oscillator mode’s supported frequencies.

FIGURE 21-2: HFINTOSC FREQUENCY ACCURACY OVER DEVICE V

DD

AND TEMPERATURE

125

+ 15%

85

60

25

0

-20

-40

1.8

2.0

± 10%

2.5

3.0

V

DD

(V)

+ 15%

3.5

3.6

DS41455B-page 198

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

21.1

DC Characteristics: PIC16LF1902/3-I/E (Industrial, Extended)

PIC16LF1902/3

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C

T

A

+85°C for industrial

-40°C

T

A

+125°C for extended

Min.

Typ† Max.

Units Conditions Param.

No.

Sym.

Characteristic

Supply Voltage

D001

D002*

V

V

DD

DR

RAM Data Retention Voltage

(1)

1.8

1.5

3.6

V

V

F

OSC

16 MHz:

Device in Sleep mode

D002A*

D002B*

D003

D003A

D003B

V

V

V

V

V

POR

*

PORR

ADFVR

*

CDAFVR

LCDFVR

Power-on Reset Release Voltage

Power-on Reset Rearm Voltage

Fixed Voltage Reference Voltage for

ADC, Initial Accuracy

Fixed Voltage Reference Voltage for

Comparator and DAC, Initial Accuracy

Fixed Voltage Reference Voltage for

LCD Bias, Initial Accuracy

1.54

6

7

7

8

7

8

8

9

9

9.5

1.64

1.7

1.74

4

4

6

6

5

5

7

7

9

9

V

V

%

%

%

Device in Sleep mode

1.024V, V

DD

1.8V, 85°C

1.024V, V

DD

1.8V, 125°C

2.048V, V

DD

2.5V, 85°C

2.048V, V

DD

2.5V, 125°C

1.024V, V

DD

1.8V, 85°C

1.024V, V

DD

1.8V, 125°C

2.048V, V

DD

2.5V, 85°C

2.048V, V

DD

2.5V, 125°C

3.072V, V

DD

3.6V, 85°C

3.072V, V

DD

3.6V, 125°C

D003C* TCV

FVR

Temperature Coefficient, Fixed Voltage Reference

— -130 — ppm/°C

D003D*

D004*

Note

V

FVR

/

V

IN

S

VDD

Line Regulation, Fixed Voltage Reference

V

DD

Rise Rate

to ensure internal

Power-on Reset signal

0.05

0.270

%/V

V/ms See

Section 5.1 “Power-on Reset

(POR)”

for details.

*

1:

These parameters are characterized but not tested.

Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

This is the limit to which V

DD

can be lowered in Sleep mode without losing RAM data.

FIGURE 21-3:

V

DD

POR AND POR REARM WITH SLOW RISING V

DD

V

POR

V

PORR

V

SS

NPOR

POR REARM

V

SS

Note 1:

2:

3:

T

VLOW

(2)

When NPOR is low, the device is held in Reset.

T

POR

1

 s typical.

T

VLOW

2.7

 s typical.

T

POR

(3)

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 199

PIC16LF1902/3

21.2

DC Characteristics: PIC16LF1902/3-I/E (Industrial, Extended)

PIC16LF1902/3

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C

T

A

+85°C for industrial

-40°C

T

A

+125°C for extended

Param

No.

Device

Characteristics

Min.

Typ† Max.

Units

Conditions

V

DD

Note

D010

D011

D012

D013

D014

D015

D016

Legend:

Note 1:

2:

3:

Supply Current (I

DD

)

(1, 2)

45

80

100

130

225

260

200

260

300

225

75

140

160

200

300

350

275

375

395

TBD

TBD

TBD

TBD

TBD

A

A

A

A

A

A

A

A

A

A

A

A

1.8

3.0

3.6

1.8

3.0

3.6

1.8

3.0

3.6

1.8

3.0

3.6

F

EC Oscillator mode

High Power mode

F

OSC

OSC

= 1 MHz

= 4 MHz

EC Oscillator mode

High Power mode

F

OSC

= 500 kHz

HFINTOSC mode

F

OSC

= 1 MHz

HFINTOSC mode

290

325

300

415

480

0.4

0.5

0.6

TBD

0.9

1

1.1

mA mA mA mA mA mA

1.8

3.0

3.6

1.8

3.0

3.6

F

OSC

= 4 MHz

HFINTOSC mode

F

OSC

= 8 MHz

HFINTOSC mode

0.8

1.5

mA mA

1.8

3.0

F

OSC

= 16 MHz

HFINTOSC mode

0.9

1.6

1.0

1.7

mA 3.6

TBD = To Be Determined

The test conditions for all I

DD

measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to V

DD

; MCLR = V

DD

; WDT disabled.

The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption.

FVR and BOR are disabled.

DS41455B-page 200

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

21.3

DC Characteristics: PIC16LF1902/3-I/E (Power-Down)

PIC16LF1902

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C

T

A

+85°C for industrial

-40°C

T

A

+125°C for extended

Param

No.

D023

D024

D025

D026

D027

D028

D029

D030

D031

Legend:

Note 1:

*

2:

3:

Device Characteristics Min.

Typ†

Max.

+85°C

Max.

+125°

C

Units

V

DD

Conditions

Note

Power-down Base Current (I

PD

)

(2)

0.03

0.04

0.09

0.3

0.5

0.6

20

22

24

121

1.0

2.0

3.0

2.0

3.0

4.0

31

41

46

300

3.0

4.0

5.0

4.0

5.0

6.0

35

45

50

560

A

A

A

A

A

A

A

A

A nA

1.8

3.0

3.6

1.8

3.0

3.6

1.8

3.0

3.6

3.0

WDT, BOR, FVR, and T1OSC disabled, all Peripherals Inactive

LPWDT Current

FVR current

(Note 1)

LPBOR current

(Note 1)

141

7.5

8.0

0.5

0.6

0.7

0.4

0.7

0.9

400

16

18

2.0

3.0

4.0

2.0

3.0

4.0

250

250

250

700

32

34

4.0

5.0

6.0

4.0

5.0

6.0

A

A

A

A nA

A

A

A

A

A

A

A

3.6

3.0

3.6

1.8

3.0

3.6

1.8

3.0

3.6

1.8

3.0

3.6

BOR Current

(Note 1)

T1OSC Current

A/D Current conversion in progress

A/D Current

(Note 1)

(Note 1, Note 3)

(Note 1, Note 3)

conversion in progress

, no

,

LCD Bias Ladder

Low power

Medium Power

High Power

1

10

100

5

16

110

6

21

120

A

A

A

3.6

3.6

3.6

These parameters are characterized but not tested.

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

TBD = To Be Determined

The peripheral current is the sum of the base I

DD

or I

PD

and the additional current consumed when this peripheral is enabled. The peripheral

current can be determined by subtracting the base I

DD

or I

PD

current from this limit. Max values should be used when calculating total current consumption.

The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode, with all I/O pins in high-impedance state and tied to V

DD

.

A/D oscillator source is F

RC

.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 201

PIC16LF1902/3

21.4

DC Characteristics: PIC16LF1902/3-I/E

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C

T

A

+85°C for industrial

-40°C

T

A

+125°C for extended

Param

No.

Sym.

Characteristic Min.

Typ† Max.

Units Conditions

D032

D033

D034

D040

D041

D042

D060

D061

D070*

D080

D090

D101*

*

Note 1:

V

V

IL

IH

Input Low Voltage

I/O PORT: with TTL buffer with Schmitt Trigger buffer

MCLR, OSC1

Input High Voltage

I/O ports: with TTL buffer

0.15 V

0.2 V

0.2 V

DD

DD

DD

V

V

V

1.8V

1.8V

V

V

DD

DD

3.6V

3.6V

I

IL with Schmitt Trigger buffer

MCLR

Input Leakage Current

(2)

I/O ports

0.25 V

DD

+

0.8

0.8 V

0.8 V

DD

DD

V

V

V

1.8V

1.8V

V

V

DD

DD

3.6V

3.6V

— ± 5

± 5

± 50

± 125

± 1000

± 200 nA nA nA

V

SS

V

PIN

V

DD

, Pin at high-impedance @ 85°C

125°C

V

SS

V

PIN

V

DD

@ 85°C

I

PUR

MCLR

(3)

Weak Pull-up Current

25 100 200

A V

DD

= 3.3V, V

PIN

= V

SS

V

OL

Output Low Voltage

I/O ports

— 0.6

V

I

OL

= 6mA, V

DD

= 3.3V

I

OL

= 1.8mA, V

DD

= 1.8V

V

OH

Output High Voltage

I/O ports

V

DD

- 0.7

— — V

I

OH

= 3mA, V

DD

= 3.3V

I

OH

= 1mA, V

DD

= 1.8V

C

IO

Capacitive Loading Specs on Output Pins

All I/O pins — — 50 pF

These parameters are characterized but not tested.

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Negative current is defined as current sourced by the pin.

DS41455B-page 202

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

21.5

Memory Programming Requirements

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C

T

A

+125°C

Param

No.

Sym.

Characteristic Min.

Typ† Max.

Units Conditions

D110

D111 I

V

IHH

DDP

Program Memory

Programming Specifications

Voltage on MCLR/V

PP

/RE3 pin

Supply Current during

Programming

V

DD

for Bulk Erase

8.0

9.0

10

V mA

(Note 2, Note 3)

D112

D113 V

PEW

V

DD

for Write or Row Erase

2.7

V

DD min.

V

DD max.

V

DD max.

V

V

D114

I

PPPGM

Current on MCLR/V

PP

during

Erase/Write

Current on V

DD

during Erase/Write

— — 1.0

mA

D115 I

DDPGM

5.0

mA

D121

D122

E

V

P

PR

Program Flash Memory

Cell Endurance

V

DD

for Read

1K

V

DD min.

10K

V

DD max.

E/W

V

-40

C to +85

C (

Note 1

)

D123

D124

T

T

IW

RETD

Self-timed Write Cycle Time

Characteristic Retention

40

2

2.5

— ms

Year Provided no other specifications are violated

Note 1:

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

2:

3:

Self-write and Block Erase.

Required only if single-supply programming is disabled.

The MPLAB ICD 2 does not support variable V

PP

output. Circuitry to limit the ICD 2 V

PP

voltage must be placed between the ICD 2 and target system when programming or debugging with the ICD 2.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 203

PIC16LF1902/3

21.6

Thermal Considerations

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C

T

A

+125°C

Param

No.

Sym.

Characteristic Typ.

Units Conditions

TH01

TH02

TH03

TH04

TH05

TH06

TH07

Note 1:

2:

3:

JA

JC

Thermal Resistance Junction to Ambient

Thermal Resistance Junction to Case

Maximum Junction Temperature

Power Dissipation

Internal Power Dissipation

I/O Power Dissipation

60

80

90

27.5

31.4

24

24

24

150

C/W

C/W

C/W

C/W

C/W

C/W

C/W

C/W

C T

JMAX

PD

P

INTERNAL

P

I

/

O

P

DER

Derated Power —

W

W

W

W

I

DD

is current to run the chip alone without driving any load on the output pins.

T

A

= Ambient Temperature

T

J

= Junction Temperature

28-pin SPDIP package

28-pin SOIC package

28-pin SSOP package

28-pin UQFN 4x4mm package

28-pin SPDIP package

28-pin SOIC package

28-pin SSOP package

28-pin UQFN 4x4mm package

PD = P

INTERNAL

+ P

I

/

O

P

INTERNAL

= I

DD

x V

DD

(1)

P

I

/

O

=

(I

OL

* V

OL

) +

(I

OH

* (V

DD

- V

OH

))

P

DER

= PD

MAX

(T

J

- T

A

)/

JA

(2)

DS41455B-page 204

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

21.7

Timing Parameter Symbology

The timing parameter symbols have been created with one of the following formats:

pp

cc ck cs di

1. TppS2ppS

2. TppS

T

F Frequency

Lowercase letters (pp) and their meanings:

CCP1

CLKOUT

CS

SDI do dt io

SDO

Data in

I/O PORT mc MCLR

Uppercase letters and their meanings:

S

F

I

H

L

Fall

High

Invalid (High-Impedance)

Low

FIGURE 21-4: LOAD CONDITIONS

Load Condition

T osc rd rw sc ss t0 t1 wr

P

R

V

Z

Time

OSC1

RD

RD or WR

SCK

SS

T0CKI

T1CKI

WR

Period

Rise

Valid

High-Impedance

Pin

C

L

V

SS

Legend:

C

L

= 50 pF for all pins, 15 pF for

OSC2 output

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 205

PIC16LF1902/3

21.8

AC Characteristics: PIC16LF1902/3-I/E

TABLE 21-1: CLOCK OSCILLATOR TIMING REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C

T

A

+125°C

Param

No.

Sym.

Characteristic Min.

Typ† Max.

OS01

OS02

OS03

*

Note 1:

Units Conditions

F

T

OSC

OSC

External CLKIN Frequency

(1)

External CLKIN Period

(1)

DC

31.25

Instruction Cycle Time

(1)

200

0.5

DC

MHz ns

EC Oscillator mode

EC Oscillator mode

T

CY

T

CY ns T

CY

= 4/F

OSC

These parameters are characterized but not tested.

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Instruction cycle period (T

CY

) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code.

Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

TABLE 21-2: OSCILLATOR PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C



T

A



+125°C

Param

No.

Sym.

Characteristic

Freq.

Tolerance

Min.

Typ† Max.

Units Conditions

OS08

OS08A

OS10

OS10A*

*

Legend:

Note 1:

2:

HF

OSC

Internal Calibrated HFINTOSC

Frequency

(2)

(Primary)

10%

15%

TBD 16.0

16.0

8.0

16.0

MHz

MHz

MHz

0°C

T

A

+85°C,

-40°C

T

A

+125°C

Internal Calibrated HFINTOSC

Frequency

(2)

(Secondary)

TBD

8.0

TBD

16.0

1.0

0°C

T

A

+85°C,

-40°C

T

A

+125°C

T

IOSC ST

HFINTOSC 16 MHz (Secondary)

Oscillator Wake-up from Sleep

Start-up Time

— — TBD 1.0

MHz

 s s

V

V

DD

DD

= 2.0V, -40°C to +85°C

= 3.0V, -40°C to +85°C

HFINTOSC 16 MHz (Primary)

Oscillator Wake-up from Sleep

Start-up Time

5

5

7

7

 s s

V

V

DD

DD

= 2.0V, -40°C to +85°C

= 3.0V, -40°C to +85°C

These parameters are characterized but not tested.

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

TBD = To Be Determined

Instruction cycle period (T

CY

) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

To ensure these oscillator frequency tolerances, V

DD

and V

SS

must be capacitively decoupled as close to the device as possible. 0.1

F and 0.01

F values in parallel are recommended.

DS41455B-page 206

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

FIGURE 21-5:

Cycle

F

OSC

CLKOUT

CLKOUT AND I/O TIMING

Write

Q4

Fetch

Q1

OS11

OS19

OS13

I/O pin

(Input)

I/O pin

(Output)

Old Value

OS15

OS18, OS19

Read

Q2

OS17

OS20

OS21

OS16

OS14

Execute

Q3

OS12

OS18

New Value

TABLE 21-3: CLKOUT AND I/O TIMING PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C



T

A



+125°C

Param

No.

Sym.

Characteristic Min.

Typ†

OS11

OS12

OS13

OS14

OS15

OS16

OS17

TosH2ckL F

OSC

to CLKOUT

(1)

TosH2ckH F

OSC

to CLKOUT

(1)

TckL2ioV

TioV2ckH

TosH2ioV

TosH2ioI

TioV2osH

TioR

CLKOUT

to Port out valid

(1)

Port input valid before CLKOUT

(1)

F

OSC

(Q1 cycle) to Port out valid

F

OSC

(Q2 cycle) to Port input invalid

(I/O in hold time)

Port input valid to F

OSC



(Q2 cycle)

(I/O in setup time)

Port output rise time

T

OSC

+ 200 ns

50

20

OS18

OS19

*

Note 1:

TioF

OS20* Tinp

OS21* Tioc

Port output fall time

INT pin input high or low time

Interrupt-on-change new input level time

25

25

These parameters are characterized but not tested.

Data in “Typ” column is at 3.0V, 25

C unless otherwise stated.

Measurements are taken in EC mode where CLKOUT output is 4 x T

OSC

.

40

15

28

15

50

Max.

Units

70

72

20

70*

72

32

55

30

— ns ns ns ns ns ns ns ns ns ns ns

Conditions

V

DD

= 3.0V

V

DD

= 3.0V

V

DD

= 3.0V

V

DD

= 3.0V

V

DD

= 3.0V

V

DD

= 2.0V

V

DD

= 2.0V

V

DD

= 3.0V

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 207

PIC16LF1902/3

FIGURE 21-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

V

DD

MCLR

Internal

POR

PWRT

Time-out

OSC

Start-Up Time

Internal Reset

(1)

Watchdog Timer

Reset

(1)

33

32

30

31

34

34

I/O pins

Note 1:

Asserted low.

FIGURE 21-7:

V

DD

BROWN-OUT RESET TIMING AND CHARACTERISTICS

V

BOR

and V

HYST

V

BOR

(Device in Brown-out Reset) (Device not in Brown-out Reset)

37

Reset

(due to BOR)

33

(1)

Note 1:

64 ms delay only if PWRTE bit in the Configuration Word register is programmed to ‘

0

’.

2 ms delay if PWRTE =

0

and VREGEN =

1

.

DS41455B-page 208

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

FIGURE 21-8:

V

DDIO

(Monitored Voltage)

MINIMUM PULSE WIDTH FOR LPBOR DETECTION

V

LPBOR

500 nVs < V

BPW

V

BPW

< 10 nVs

Pulse Rejected

10 nVs < V

BPW

< 500 nVs

Maybe Detected

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 209

PIC16LF1902/3

TABLE 21-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET PARAMETERS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C



T

A



+125°C

Param

No.

Sym.

Characteristic Min.

Typ† Max.

Units Conditions

30

31

32

33*

34*

T

F

T

T

T

MC

L

WDTLP

OST

PWRT

IOZ

MCLR Pulse Width (low)

Low Frequency Internal Oscillator

Frequency

Oscillator Start-up Timer Period

(1)

Power-up Timer Period, PWRTE =

0

I/O High-Impedance from MCLR

Low or Watchdog Timer Reset

2

5

19

33

1024

2048

52

2.0

 s

 s kHz

Tosc

V

V

DD

DD

= 3.0V, -40°C to +85°C

= 3.0V

(Note 2)

Tosc Clocked by LFINTOSC

 s

34A

35

35A*

35B*

35C

T

V

V

T

T

REARM

BOR

HYST

BORDC

BORAC

POR Rearm Time

Brown-out Reset Voltage

Brown-out Reset Hysteresis

Brown-out Reset DC Response

Time

Brown-out Reset AC Response

Time

50

40

2.40

1.80

25

1

100

100

2.5

1.9

50

3

100

1000

1000

2.60

2.00

75

100

5

10

V

V

V

V mV mV

 s

 s ns

-40°C to 85°C, at Maximum

Rearm Voltage

BORV = 2.5V

BORV = 1.9V

-40°C to +85°C

-40°C to +125°C

V

DD

V

BOR

, -40°C to +85°C

V

DD

V

BOR

Transient Response immunity for a noise spike that goes from V

DD

to V

SS

and back with

10 ns rise and fall times.

Guidance only.

Turn on to specified stability 36

37

38*

39*

T

FVRS

V

LPBOR

Zero-Power Brown-out Reset

Voltage

V

ZPHYST

Zero-Power Brown-out Reset

Hysteresis

T

ZPBPW

Fixed Voltage Reference Turn-on

Time

Zero-Power Brown-out Reset AC

Response Time for BOR detection

1.85

0

10

1.95

TBD

TBD

5

2.10

TBD

500

V s mV nVs

-40°C to +85°C

-40°C to +85°C

-40°C to +125°C

V

DD

V

BOR

, -40°C to +85°C

*

Note 1:

2:

3:

These parameters are characterized but not tested.

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Instruction cycle period (T

CY

) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

Period of the slower clock.

To ensure these voltage tolerances, V

DD

and V

SS

must be capacitively decoupled as close to the device as possible. 0.1

F and 0.01

F values in parallel are recommended.

DS41455B-page 210

Preliminary

2011 Microchip Technology Inc.

FIGURE 21-9:

PIC16LF1902/3

TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI

40

41

42

T1CKI

45 46

47 49

TMR0 or

TMR1

TABLE 21-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating Temperature -40°C



T

A



+125°C

Param

No.

40*

41*

42*

45*

46*

47*

48

49*

Sym.

Characteristic Min.

Typ† Max.

Units Conditions

*

T

T

T

T

T

T

0H

0L

0P

T0CKI High Pulse Width

T0CKI Low Pulse Width

T0CKI Period

No Prescaler

With Prescaler

No Prescaler

With Prescaler

0.5 T

CY

+ 20

10

0.5 T

CY

+ 20

10

Greater of:

20 or T

CY

+ 40

N

0.5 T

CY

+ 20

15

— ns ns ns ns ns N = prescale value

(2, 4, ..., 256)

T

T

T

T

T

T

1H

1L

1P

T1CKI High

Time

T1CKI Low

Time

Synchronous, No Prescaler

Synchronous, with Prescaler

Asynchronous

Synchronous, No Prescaler

Synchronous, with Prescaler

Asynchronous

T1CKI Input

Period

Synchronous

30

0.5 T

CY

+ 20

15

30

Greater of:

30 or T

CY

+ 40

N

— ns ns ns ns ns ns ns N = prescale value

(1, 2, 4, 8)

F

T

1

Asynchronous

Timer1 Oscillator Input Frequency Range

(oscillator enabled by setting bit T1OSCEN)

60

32.4

— —

32.768 33.1

ns kHz

TCKEZ

TMR

1 Delay from External Clock Edge to Timer

Increment

2 T

OSC

— 7 T

OSC

— Timers in Sync mode

These parameters are characterized but not tested.

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 211

PIC16LF1902/3

TABLE 21-6: PIC16LF1902/3 A/D CONVERTER (ADC) CHARACTERISTICS

:

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C

T

A

+125°C

Param

No.

Sym.

Characteristic Min.

Typ† Max.

Units Conditions

AD01

AD02

AD03

AD04

AD05

AD06

AD07

N

E

IL

E

DL

E

E

E

E

R

OFF

GN

ABS

LIN

AD08

AD08A

V

REF

Resolution

Integral Error

Differential Error

Offset Error

Gain Error

Absolute Error

Linearity Error

Reference Voltage

(3)

1.8

2.0

±1

±1

±1

±1

10

±1

±1

V

DD

V

DD bit

LSb V

REF

= 5.0V

LSb No missing codes, V

REF

= 5.0V

LSb V

REF

= 5.0V

LSb V

REF

= 5.0V

LSb V

REF

= 5.0V

LSb V

REF

= 5.0V

V

V Absolute minimum to ensure 1 LSb accuracy

(

Note 5

)

AD09

AD10

V

Z

AIN

AIN

Full-Scale Range

Recommended Impedance of

Analog Voltage Source

V

REF

Input Current

(3)

V

SS

V

REF

50

V k

Can go higher if external 0.01

present on input pin.

F capacitor is

AD11

I

REF

10

1000

10

A

A

During V

AIN

acquisition.

Based on differential of V

HOLD

to V

AIN

.

During A/D conversion cycle.

*

Note 1:

2:

3:

4:

5:

These parameters are characterized but not tested.

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Total Absolute Error includes integral, differential, offset and gain errors.

The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

ADC V

REF

is from the V

DD

pin.

When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module.

Not targeting 1.8V as minimum voltage for die size reasons.

TABLE 21-7: PIC16LF1902/3 A/D CONVERSION REQUIREMENTS

Standard Operating Conditions (unless otherwise stated)

Operating temperature -40°C

T

A

+125°C

Param

No.

Sym.

Characteristic Min.

Typ† Max.

Units Conditions

AD130* T

AD

A/D Clock Period 1.6

3.0

9.0

9.0

 s

 s

T

T

OSC

OSC

-based, V

-based, V

REF

REF

3.0V

full range

AD131 T

CNV

A/D Internal RC Oscillator

Period

Conversion Time (not including

Acquisition Time)

(1)

3.0

1.6

6.0

4.0

11

9.0

6.0

T s s

AD

ADCS<1:0> =

11

(ADRC mode) at V

DD

= 2.0V

at V

DD

= 3.0V

Set GO/DONE bit to conversion complete.

AD132* T

ACQ

AD134

*

Note 1:

T

GO

Acquisition Time

Q4 to A/D Clock Start

Acquisition Time

11.5

T

OSC

/2

T

OSC

/2+T

CY

 s

If the A/D clock source is selected as RC, a time of T

CY

is added before the A/D clock starts. This allows the

SLEEP instruction to be executed.

These parameters are characterized but not tested.

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

The ADRES register may be read on the following T

CY

cycle.

DS41455B-page 212

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

FIGURE 21-10: PIC16LF1902/3 A/D CONVERSION TIMING (NORMAL MODE)

BSF ADCON0, GO

AD134

Q4

(T

OSC

/2

(1)

)

AD131

1 T

CY

AD130

A/D CLK

A/D Data

7 6 5 4 3 2 1 0

ADRES

OLD_DATA

NEW_DATA

ADIF

GO

Sample

AD132

Sampling Stopped

1 T

DONE

CY

Note 1:

If the A/D clock source is selected as RC, a time of T

CY

is added before the A/D clock starts. This allows the

SLEEP

instruction to be executed.

FIGURE 21-11: PIC16LF1902/3 A/D CONVERSION TIMING (SLEEP MODE)

BSF ADCON0, GO

AD134

Q4

A/D CLK

A/D Data

ADRES

ADIF

GO

Sample

AD132

(T

OSC

/2 + T

CY

(1)

)

AD131

7 6

OLD_DATA

5 4

AD130

Sampling Stopped

3 2 1 0

1 T

CY

NEW_DATA

1 T

CY

DONE

Note 1:

If the A/D clock source is selected as RC, a time of T

CY

is added before the A/D clock starts. This allows the

SLEEP

instruction to be executed.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 213

PIC16LF1902/3

NOTES:

DS41455B-page 214

Preliminary

2011 Microchip Technology Inc.

22.0

DC AND AC

CHARACTERISTICS GRAPHS

AND CHARTS

Graphs and charts are not available at this time.

PIC16LF1902/3

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 215

PIC16LF1902/3

NOTES:

DS41455B-page 216

Preliminary

2011 Microchip Technology Inc.

23.0

DEVELOPMENT SUPPORT

The PIC

®

microcontrollers and dsPIC

®

digital signal controllers are supported with a full range of software and hardware development tools:

• Integrated Development Environment

- MPLAB

®

IDE Software

• Compilers/Assemblers/Linkers

- MPLAB C Compiler for Various Device

Families

- HI-TECH C for Various Device Families

- MPASM TM Assembler

- MPLINK

TM

Object Linker/

MPLIB TM Object Librarian

- MPLAB Assembler/Linker/Librarian for

Various Device Families

• Simulators

- MPLAB SIM Software Simulator

• Emulators

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers

- MPLAB ICD 3

- PICkit™ 3 Debug Express

• Device Programmers

- PICkit™ 2 Programmer

- MPLAB PM3 Device Programmer

• Low-Cost Demonstration/Development Boards,

Evaluation Kits, and Starter Kits

PIC16LF1902/3

23.1

MPLAB Integrated Development

Environment Software

The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows

® operating system-based application that contains:

• A single graphical interface to all debugging tools

- Simulator

- Programmer (sold separately)

- In-Circuit Emulator (sold separately)

- In-Circuit Debugger (sold separately)

• A full-featured editor with color-coded context

• A multiple project manager

• Customizable data windows with direct edit of contents

• High-level source code debugging

• Mouse over variable inspection

• Drag and drop variables from source to watch windows

• Extensive on-line help

• Integration of select third party tools, such as

IAR C Compilers

The MPLAB IDE allows you to:

• Edit your source files (either C or assembly)

• One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information)

• Debug using:

- Source files (C or assembly)

- Mixed C and assembly

- Machine code

MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 217

PIC16LF1902/3

23.2

MPLAB C Compilers for Various

Device Families

The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18,

PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use.

For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.

23.3

HI-TECH C for Various Device

Families

The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use.

For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.

The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms.

23.4

MPASM Assembler

The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs.

The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel

®

standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging.

The MPASM Assembler features include:

• Integration into MPLAB IDE projects

• User-defined macros to streamline assembly code

• Conditional assembly for multi-purpose source files

• Directives that allow complete control over the assembly process

23.5

MPLINK Object Linker/

MPLIB Object Librarian

The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the

MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script.

The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many smaller files

• Enhanced code maintainability by grouping related modules together

• Flexible creation of libraries with easy module listing, replacement, deletion and extraction

23.6

MPLAB Assembler, Linker and

Librarian for Various Device

Families

MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24,

PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include:

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command line interface

• Rich directive set

• Flexible macro language

• MPLAB IDE compatibility

DS41455B-page 218

Preliminary

2011 Microchip Technology Inc.

23.7

MPLAB SIM Software Simulator

The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC

®

DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers.

The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.

23.8

MPLAB REAL ICE In-Circuit

Emulator System

MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and programs PIC

®

Flash MCUs and dsPIC

®

Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit.

The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal

(LVDS) interconnection (CAT5).

The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of

MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.

PIC16LF1902/3

23.9

MPLAB ICD 3 In-Circuit Debugger

System

MPLAB ICD 3 In-Circuit Debugger System is Microchip’s most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC

®

Flash microcontrollers and dsPIC

®

DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated

Development Environment (IDE).

The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a high-speed

USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB

REAL ICE systems (RJ-11). MPLAB ICD 3 supports all

MPLAB ICD 2 headers.

23.10 PICkit 3 In-Circuit Debugger/

Programmer and

PICkit 3 Debug Express

The MPLAB PICkit 3 allows debugging and programming of PIC

®

and dsPIC

®

Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development

Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer’s PC using a full speed USB interface and can be connected to the target via an

Microchip debug (RJ-11) connector (compatible with

MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™.

The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 219

PIC16LF1902/3

23.11 PICkit 2 Development

Programmer/Debugger and

PICkit 2 Debug Express

The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers. The full featured

Windows

®

programming interface supports baseline

(PIC10F, PIC12F5xx, PIC16F5xx), midrange

(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip’s powerful MPLAB Integrated

Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC

®

microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified.

The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and

MPLAB IDE software.

23.12 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable voltage verification at V

DDMIN

and V

DDMAX

for maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB

PM3 Device Programmer can read, verify and program

PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications.

23.13 Demonstration/Development

Boards, Evaluation Kits, and

Starter Kits

A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification.

The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional

EEPROM memory.

The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications.

In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, K

EE

L

OQ

® security ICs, CAN,

IrDA

®

, PowerSmart battery management, SEEVAL

® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more.

Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board.

Check the Microchip web page ( www.microchip.com

) for the complete list of demonstration, development and evaluation kits.

DS41455B-page 220

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

24.0

PACKAGING INFORMATION

24.1

Package Marking Information

28-Lead PDIP (600 mil)

XXXXXXXXXXXXXXX

XXXXXXXXXXXXXXX

XXXXXXXXXXXXXXX

YYWWNNN

28-Lead SOIC (7.50 mm)

XXXXXXXXXXXXXXXXXXXX

XXXXXXXXXXXXXXXXXXXX

XXXXXXXXXXXXXXXXXXXX

YYWWNNN

28-Lead SSOP (5.30 mm)

Example

PIC16LF1902-I/P

1148017

Example

PIC16LF1902-E/SO

1148017

e

3

Example

PIC16LF1902

-E/SS

e

3

1148017

Legend:

XX...X

Y

YY

WW

NNN e

3

*

Customer-specific information

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn) can be found on the outer packaging for this package.

e

Note

: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 221

PIC16LF1902/3

24.2

Package Marking Information

28-Lead UQFN (4x4x0.5 mm)

PIN 1

Example

PIN 1

PIC16

LF1903

E/MV

148017

3

Legend:

XX...X

Y

YY

WW

NNN e

3

*

Customer-specific information

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn) can be found on the outer packaging for this package.

e

Note

: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.

DS41455B-page 222

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

24.3

Package Details

The following sections give the technical details of the packages.

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2011 Microchip Technology Inc.

Preliminary

DS41455B-page 223

PIC16LF1902/3

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

DS41455B-page 224

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 225

PIC16LF1902/3

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

DS41455B-page 226

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

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2011 Microchip Technology Inc.

Preliminary

DS41455B-page 227

PIC16LF1902/3

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

DS41455B-page 228

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 229

PIC16LF1902/3

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging

DS41455B-page 230

Preliminary

2011 Microchip Technology Inc.

APPENDIX A: DATA SHEET

REVISION HISTORY

Revision A

Original release (01/2011)

Revision B (04/2011)

Revised Sections: Flexible Oscillator Structure;

Low-Power Features; Electrical Specifications;

Changed ULPBOR to LPBOR.

PIC16LF1902/3

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 231

PIC16LF1902/3

NOTES:

DS41455B-page 232

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

INDEX

A

A/D

Specifications............................................................ 210

Absolute Maximum Ratings .............................................. 195

AC Characteristics

Industrial and Extended (PIC16LF1902/3-I/E) .......... 204

Load Conditions ........................................................ 203

ADC .................................................................................. 113

Acquisition Requirements ......................................... 123

Associated registers.................................................. 125

Block Diagram........................................................... 113

Calculating Acquisition Time..................................... 123

Channel Selection..................................................... 114

Configuration............................................................. 114

Configuring Interrupt ................................................. 118

Conversion Clock...................................................... 114

Conversion Procedure .............................................. 118

Internal Sampling Switch (R

SS

) Impedance.............. 123

Interrupts................................................................... 116

Operation .................................................................. 117

Operation During Sleep ............................................ 117

Port Configuration ..................................................... 114

Reference Voltage (V

REF

)......................................... 114

Source Impedance.................................................... 123

Starting an A/D Conversion ...................................... 116

ADCON0 Register....................................................... 25, 119

ADCON1 Register....................................................... 25, 120

ADDFSR ........................................................................... 185

ADDWFC .......................................................................... 185

ADRESH Register............................................................... 25

ADRESH Register (ADFM = 0) ......................................... 121

ADRESH Register (ADFM = 1) ......................................... 122

ADRESL Register (ADFM = 0).......................................... 121

ADRESL Register (ADFM = 1).......................................... 122

Analog-to-Digital Converter.

See

ADC

ANSELA Register ............................................................... 96

ANSELB Register ............................................................... 99

Assembler

MPASM Assembler................................................... 216

B

Block Diagrams ................................................................. 4, 5

ADC .......................................................................... 113

ADC Transfer Function ............................................. 124

Analog Input Model ................................................... 124

Clock Source............................................................... 52

Crystal Operation ........................................................ 54

Generic I/O Port .......................................................... 93

Interrupt Logic ............................................................. 61

LCD Bias Voltage Generation................................... 151

LCD Clock Generation .............................................. 150

On-Chip Reset Circuit ................................................. 43

PIC16LF1902/3............................................. 4, 5, 10, 14

Timer0....................................................................... 127

Timer1....................................................................... 131

Timer1 Gate .............................................. 136, 137, 138

Voltage Reference .................................................... 109

BORCON Register .............................................................. 45

BRA................................................................................... 186

Brown-out Reset (BOR) ...................................................... 45

Specifications............................................................ 208

Timing and Characteristics ....................................... 206

C

C Compilers

MPLAB C18.............................................................. 216

CALL................................................................................. 187

CALLW ............................................................................. 187

Clock Sources

External Modes........................................................... 53

EC ...................................................................... 53

Internal Modes............................................................ 54

HFINTOSC ......................................................... 54

Internal Oscillator Clock Switch Timing .............. 55

LFINTOSC.......................................................... 55

Clock Switching .................................................................. 57

Code Examples

A/D Conversion ........................................................ 118

Initializing PORTA ...................................................... 93

Writing to Flash Program Memory.............................. 86

Comparators

C2OUT as T1 Gate................................................... 133

CONFIG1 Register ............................................................. 38

CONFIG2 Register ............................................................. 39

Core Function Register....................................................... 24

Customer Change Notification Service............................. 233

Customer Notification Service .......................................... 233

Customer Support............................................................. 233

D

Data Memory ................................................................ 18, 21

DC and AC Characteristics............................................... 213

DC Characteristics

Extended and Industrial............................................ 200

Industrial and Extended............................................ 197

Development Support ....................................................... 215

Device Configuration .......................................................... 37

Code Protection.......................................................... 40

Configuration Word..................................................... 37

User ID ................................................................. 40, 41

Device ID Register.............................................................. 41

Device Overview............................................................. 9, 75

E

EEDATL Register ............................................................... 89

Electrical Specifications .................................................... 195

Enhanced Mid-Range CPU ................................................ 13

Errata .................................................................................... 8

Extended Instruction Set

ADDFSR................................................................... 185

F

Firmware Instructions ....................................................... 181

Fixed Voltage Reference (FVR)

Associated Registers................................................ 110

Flash Program Memory ...................................................... 79

Associated Registers.................................................. 91

Configuration Word w/ Flash Program Memory ......... 91

Erasing ....................................................................... 82

Modifying .................................................................... 87

Write Verify ................................................................. 88

Writing ........................................................................ 83

FSR Register ...................................................................... 24

FVRCON (Fixed Voltage Reference Control) Register..... 110

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 233

PIC16LF1902/3

I

INDF Register ..................................................................... 24

Indirect Addressing ............................................................. 32

Instruction Format ............................................................. 182

Instruction Set ................................................................... 181

ADDLW ..................................................................... 185

ADDWF ..................................................................... 185

ADDWFC .................................................................. 185

ANDLW ..................................................................... 185

ANDWF ..................................................................... 185

BRA........................................................................... 186

CALL ......................................................................... 187

CALLW...................................................................... 187

LSLF ......................................................................... 189

LSRF ......................................................................... 189

MOVF........................................................................ 189

MOVIW ..................................................................... 190

MOVLB ..................................................................... 190

MOVWI ..................................................................... 191

OPTION .................................................................... 191

RESET ...................................................................... 191

SUBWFB................................................................... 193

TRIS .......................................................................... 194

BCF ........................................................................... 186

BSF ........................................................................... 186

BTFSC ...................................................................... 186

BTFSS ...................................................................... 186

CALL ......................................................................... 187

CLRF......................................................................... 187

CLRW ....................................................................... 187

CLRWDT................................................................... 187

COMF ....................................................................... 187

DECF ........................................................................ 187

DECFSZ.................................................................... 188

GOTO ....................................................................... 188

INCF.......................................................................... 188

INCFSZ ..................................................................... 188

IORLW ...................................................................... 188

IORWF ...................................................................... 188

MOVLW .................................................................... 190

MOVWF .................................................................... 190

NOP .......................................................................... 191

RETFIE ..................................................................... 192

RETLW ..................................................................... 192

RETURN ................................................................... 192

RLF ........................................................................... 192

RRF........................................................................... 193

SLEEP ...................................................................... 193

SUBLW ..................................................................... 193

SUBWF ..................................................................... 193

SWAPF ..................................................................... 194

XORLW ..................................................................... 194

XORWF..................................................................... 194

INTCON Register ................................................................ 66

Internal Oscillator Block

INTOSC

Specifications.................................................... 204

Internal Sampling Switch (R

SS

) Impedance ...................... 123

Internet Address................................................................ 233

Interrupt-On-Change ......................................................... 105

Associated Registers ................................................ 107

Interrupts ............................................................................. 61

ADC .......................................................................... 118

Associated registers w/ Interrupts ............................... 71

Configuration Word w/ Clock Sources ........................ 59

DS41455B-page 234

TMR1 ........................................................................ 135

INTOSC Specifications ..................................................... 204

IOCBF Register ................................................................ 106

IOCBN Register ................................................................ 106

IOCBP Register ................................................................ 106

L

LATA Register .................................................................... 95

LATB Register .................................................................... 98

LATC Register .................................................................. 101

LCD

Associated Registers ................................................ 176

Bias Voltage Generation................................... 151, 152

Clock Source Selection............................................. 150

Configuring the Module............................................. 175

Disabling the Module ................................................ 175

Frame Frequency ..................................................... 158

Interrupts .................................................................. 171

LCDCON Register .................................................... 143

LCDPS Register ....................................................... 143

Multiplex Types......................................................... 158

Operation During Sleep ............................................ 173

Pixel Control ............................................................. 158

Prescaler .................................................................. 150

Segment Enables ..................................................... 158

Waveform Generation............................................... 160

LCDCON Register .................................................... 143, 145

LCDCST Register ............................................................. 148

LCDDATAx Registers ............................................... 149, 156

LCDPS Register ....................................................... 143, 146

LP Bits ...................................................................... 150

LCDREF Register ............................................................. 147

LCDRL Register................................................................ 156

LCDSEn Registers............................................................ 149

Liquid Crystal Display (LCD) Driver .................................. 143

Load Conditions................................................................ 203

LSLF ................................................................................. 189

LSRF................................................................................. 189

M

MCLR.................................................................................. 46

Internal........................................................................ 46

Memory Organization

Data ...................................................................... 18, 21

Program ...................................................................... 15

Microchip Internet Web Site.............................................. 233

MOVIW ............................................................................. 190

MOVLB ............................................................................. 190

MOVWI ............................................................................. 191

MPLAB ASM30 Assembler, Linker, Librarian ................... 216

MPLAB Integrated Development Environment Software.. 215

MPLAB PM3 Device Programmer .................................... 218

MPLAB REAL ICE In-Circuit Emulator System ................ 217

MPLINK Object Linker/MPLIB Object Librarian ................ 216

O

OPCODE Field Descriptions............................................. 181

OPTION ............................................................................ 191

OPTION_REG Register.................................................... 129

OSCCON Register.............................................................. 58

Oscillator

Associated Registers .................................................. 59

Oscillator Module ................................................................ 51

ECH ............................................................................ 51

ECL............................................................................. 51

ECM............................................................................ 51

Preliminary

2011 Microchip Technology Inc.

PIC16LF1902/3

INTOSC ...................................................................... 51

Oscillator Parameters ....................................................... 204

Oscillator Specifications .................................................... 204

Oscillator Start-up Timer (OST)

Specifications............................................................ 208

OSCSTAT Register............................................................. 59

P

Packaging ......................................................................... 219

Marking ..................................................................... 219

PDIP Details.............................................................. 220

PCL and PCLATH ............................................................... 14

PCL Register....................................................................... 24

PCLATH Register ............................................................... 24

PCON Register ............................................................. 25, 49

PIE1 Register ...................................................................... 67

PIE2 Register ................................................................ 25, 68

Pinout Descriptions

PIC16LF1902/3........................................................... 11

PIR1 Register...................................................................... 69

PIR2 Register................................................................ 25, 70

PMADR Registers ............................................................... 79

PMADRH Registers ............................................................ 79

PMADRL Register............................................................... 89

PMADRL Registers ............................................................. 79

PMCON1 Register ........................................................ 79, 90

PMCON2 Register ........................................................ 79, 91

PMDATH Register .............................................................. 89

PORTA................................................................................ 94

ANSELA Register ....................................................... 94

Associated Registers .................................................. 96

Configuration Word w/ PORTA ................................... 96

PORTA Register ................................................... 25, 26

Specifications............................................................ 205

PORTA Register ................................................................. 95

PORTB................................................................................ 97

ANSELB Register ....................................................... 97

Associated Registers .................................................. 99

PORTB Register ................................................... 25, 26

PORTB Register ................................................................. 98

PORTC ............................................................................. 100

Associated Registers ................................................ 102

PORTC Register ................................................... 25, 26

Specifications............................................................ 205

PORTC Register ............................................................... 101

PORTE.............................................................................. 103

Associated Registers ................................................ 104

PORTE Register ......................................................... 25

PORTE Register ............................................................... 103

Power-Down Mode (Sleep) ................................................. 73

Associated Registers .................................................. 74

Power-on Reset .................................................................. 44

Power-up Time-out Sequence ............................................ 46

Power-up Timer (PWRT) .................................................... 44

Specifications............................................................ 208

Precision Internal Oscillator Parameters........................... 204

Program Memory ................................................................ 15

Map and Stack ................................................ 15, 17, 21

Map and Stack (PIC16LF1902) .................................. 16

Programming, Device Instructions .................................... 181

R

Reader Response ............................................................. 234

Read-Modify-Write Operations ......................................... 181

Registers

ADCON0 (ADC Control 0) ........................................ 119

2011 Microchip Technology Inc.

ADCON1 (ADC Control 1) ........................................ 120

ADRESH (ADC Result High) with ADFM = 0) .......... 121

ADRESH (ADC Result High) with ADFM = 1) .......... 122

ADRESL (ADC Result Low) with ADFM = 0)............ 121

ADRESL (ADC Result Low) with ADFM = 1)............ 122

ANSELA (PORTA Analog Select) .............................. 96

ANSELB (PORTB Analog Select) .............................. 99

BORCON Brown-out Reset Control) .......................... 45

Configuration Word 1.................................................. 38

Configuration Word 2.................................................. 39

Core Function, Summary............................................ 24

Device ID .................................................................... 41

EEDATL (EEPROM Data) .......................................... 89

FVRCON .................................................................. 110

INTCON (Interrupt Control) ........................................ 66

IOCBF (Interrupt-on-Change Flag)........................... 106

IOCBN (Interrupt-on-Change Negative Edge).......... 106

IOCBP (Interrupt-on-Change Positive Edge)............ 106

LATA (Data Latch PORTA) ........................................ 95

LATB (Data Latch PORTB) ........................................ 98

LATC (Data Latch PORTC) ...................................... 101

LCDCON (LCD Control) ........................................... 145

LCDCST (LCD Contrast Control) ............................. 148

LCDDATAx (LCD Data) .................................... 149, 156

LCDPS (LCD Phase)................................................ 146

LCDREF (LCD Reference Voltage Control) ............. 147

LCDRL (LCD Reference Voltage Control)................ 156

LCDSEn (LCD Segment Enable) ............................. 149

OPTION_REG (OPTION)......................................... 129

OSCCON (Oscillator Control)..................................... 58

OSCSTAT (Oscillator Status) ..................................... 59

PCON (Power Control Register)................................. 49

PCON (Power Control) ............................................... 49

PIE1 (Peripheral Interrupt Enable 1) .......................... 67

PIE2 (Peripheral Interrupt Enable 2) .......................... 68

PIR1 (Peripheral Interrupt Register 1) ........................ 69

PIR2 (Peripheral Interrupt Request 2) ........................ 70

PMADRL (Program Memory Address) ....................... 89

PMCON1 (Program Memory Control 1) ..................... 90

PMCON2 (Program Memory Control 2) ..................... 91

PMDATH (Program Memory Data)............................. 89

PORTA ....................................................................... 95

PORTB ....................................................................... 98

PORTC ..................................................................... 101

PORTE ..................................................................... 103

Special Function, Summary........................................ 25

STATUS ..................................................................... 19

T1CON (Timer1 Control) .......................................... 139

T1GCON (Timer1 Gate Control)............................... 140

TRISA (Tri-State PORTA) .......................................... 95

TRISB (Tri-State PORTB) .......................................... 98

TRISC (Tri-State PORTC) ........................................ 101

TRISE (Tri-State PORTE) ........................................ 103

WDTCON (Watchdog Timer Control) ......................... 77

WPUB (Weak Pull-up PORTB)................................... 99

RESET.............................................................................. 191

Reset .................................................................................. 43

Reset Instruction................................................................. 46

Resets ................................................................................ 43

Associated Registers.................................................. 50

Revision History................................................................ 227

S

Software Simulator (MPLAB SIM) .................................... 217

Special Function Registers (SFRs)..................................... 25

Stack................................................................................... 30

Preliminary

DS41455B-page 235

PIC16LF1902/3

Accessing.................................................................... 30

Reset........................................................................... 32

Stack Overflow/Underflow................................................... 46

STATUS Register................................................................ 19

SUBWFB........................................................................... 193

T

T1CON Register.......................................................... 25, 139

T1GCON Register............................................................. 140

Temperature Indicator Module .......................................... 111

Thermal Considerations .................................................... 202

Timer0 ............................................................................... 127

Associated Registers ................................................ 129

Operation .................................................................. 127

Specifications ............................................................ 209

Timer1 ............................................................................... 131

Associated registers.................................................. 141

Asynchronous Counter Mode ................................... 133

Reading and Writing ......................................... 133

Clock Source Selection ............................................. 132

Interrupt..................................................................... 135

Operation .................................................................. 132

Operation During Sleep ............................................ 135

Oscillator ................................................................... 133

Prescaler ................................................................... 133

Specifications ............................................................ 209

Timer1 Gate

Selecting Source............................................... 133

TMR1H Register ....................................................... 131

TMR1L Register ........................................................ 131

Timers

Timer1

T1CON.............................................................. 139

T1GCON ........................................................... 140

Timing Diagrams

A/D Conversion ......................................................... 211

A/D Conversion (Sleep Mode) .................................. 211

Brown-out Reset (BOR) ............................................ 206

Brown-out Reset Situations ........................................ 45

CLKOUT and I/O....................................................... 205

INT Pin Interrupt.......................................................... 64

Internal Oscillator Switch Timing................................. 56

LCD Interrupt Timing in Quarter-Duty Cycle Drive.... 172

LCD Sleep Entry/Exit when SLPEN = 1 or CS = 00 . 174

Reset Start-up Sequence............................................ 47

Reset, WDT, OST and Power-up Timer ................... 206

SPI Slave Mode (CKE = 0) ....................................... 212

Timer0 and Timer1 External Clock ........................... 208

Timer1 Incrementing Edge........................................ 135

Type-A in 1/2 MUX, 1/2 Bias Drive ........................... 161

Type-A in 1/2 MUX, 1/3 Bias Drive ........................... 163

Type-A in 1/3 MUX, 1/2 Bias Drive ........................... 165

Type-A in 1/3 MUX, 1/3 Bias Drive ........................... 167

Type-A in 1/4 MUX, 1/3 Bias Drive ........................... 169

Type-A/Type-B in Static Drive................................... 160

Type-B in 1/2 MUX, 1/2 Bias Drive ........................... 162

Type-B in 1/2 MUX, 1/3 Bias Drive ........................... 164

Type-B in 1/3 MUX, 1/2 Bias Drive ........................... 166

Type-B in 1/3 MUX, 1/3 Bias Drive ........................... 168

Type-B in 1/4 MUX, 1/3 Bias Drive ........................... 170

Wake-up from Interrupt ............................................... 74

Timing Parameter Symbology........................................... 203

TMR0 Register .................................................................... 25

TMR1H Register ................................................................. 25

TMR1L Register .................................................................. 25

TRIS .................................................................................. 194

DS41455B-page 236

Preliminary

TRISA Register............................................................. 25, 95

TRISB ................................................................................. 97

TRISB Register............................................................. 25, 98

TRISC ............................................................................... 100

TRISC Register........................................................... 25, 101

TRISE ............................................................................... 103

TRISE Register........................................................... 25, 103

U

USART

Synchronous Master Mode

Requirements, Synchronous Transmission...... 212

V

V

REF

.

S

EE

ADC Reference Voltage

W

Wake-up Using Interrupts ................................................... 74

Watchdog Timer (WDT)...................................................... 46

Modes ......................................................................... 76

Specifications ........................................................... 208

WDTCON Register ............................................................. 77

WPUB Register................................................................... 99

Write Protection .................................................................. 40

WWW Address ................................................................. 233

WWW, On-Line Support ....................................................... 8

2011 Microchip Technology Inc.

THE MICROCHIP WEB SITE

Microchip provides online support via our WWW site at www.microchip.com

. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:

Product Support

– Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software

General Technical Support

– Frequently Asked

Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing

Business of Microchip

– Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of

Microchip sales offices, distributors and factory representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest.

To register, access the Microchip web site at www.microchip.com

. Under “Support”, click on

“Customer Change Notification” and follow the registration instructions.

PIC16LF1902/3

CUSTOMER SUPPORT

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Development Systems Information Line

Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.

Technical support is available through the web site at: http://microchip.com/support

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 237

PIC16LF1902/3

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at

(480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

TO:

RE:

Technical Publications Manager

Reader Response

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Total Pages Sent ________

FAX: (______) _________ - _________

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

2011 Microchip Technology Inc.

DS41455B-page 238

PIC16LF1902/3

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office

.

PART NO.

[X]

(1)

-

X /XX XXX

Examples:

Device Tape and Reel

Option

Temperature

Range

Package Pattern

a)

Device:

Tape and Reel

Option:

PIC16LF1902

,

PIC16LF1903

Blank

T

= Standard packaging (tube or tray)

= Tape and Reel

(1)

b) c)

PIC16LF1902T - I/MV 301

Tape and Reel,

Industrial temperature,

UQFN package,

QTP pattern #301

PIC16LF1903 - I/P

Industrial temperature

PDIP package

PIC16LF1903 - E/SS

Extended temperature,

SSOP package

Temperature

Range:

I

E

= -40

C to +85

C

= -40

C to +125

C

(Industrial)

(Extended)

Package:

MV

P

SO

SS

= UQFN (4x4)

= PDIP

= SOIC

= SSOP

Pattern:

QTP, SQTP, Code or Special Requirements

(blank otherwise)

Note 1:

Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.

2011 Microchip Technology Inc.

Preliminary

DS41455B-page 239

AMERICAS

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support: http://www.microchip.com/ support

Web Address: www.microchip.com

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Cleveland

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

DS41455B-page 240

Worldwide Sales and Service

ASIA/PACIFIC

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

ASIA/PACIFIC

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Korea - Seoul

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Taiwan - Hsin Chu

Tel: 886-3-6578-300

Fax: 886-3-6578-370

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Fax: 886-7-330-9305

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

EUROPE

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

02/18/11

Preliminary

2011 Microchip Technology Inc.

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