DisplayPort Procedure Descriptions
ValiFrame DisplayPort Test
Calibration and Receiver Test Procedure Descriptions
Rev.1.0
BitifEye Digital Test Solutions GmbH
Herrenberger Strasse 130
71034 Boeblingen, Germany
info@bitifeye.com
www.bitifeye.com
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Notices
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Edition
Apr. 08, 2015
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Contents
1 Introduction...................................................................................................................................................9
2 ValiFrame DisplayPort Station..................................................................................................................10
2.1 ValiFrame DisplayPort Station Configuration.....................................................................................................10
2.1.1 Pattern Generator......................................................................................................................................11
2.1.2 AUX Channel Controller............................................................................................................................11
2.1.3 Use Tx Switch / Use Rx Switch.................................................................................................................11
2.1.4 Oscilloscope Application Supplier Company Name..................................................................................11
2.2 Starting ValiFrame DisplayPort Station..............................................................................................................12
2.3 Configure DUT...................................................................................................................................................13
2.3.1 DUT Parameters.......................................................................................................................................14
2.3.2 Sink Test Configuration.............................................................................................................................14
2.3.3 Source Test Configuration.........................................................................................................................16
3 Calibration and Test Procedures..............................................................................................................18
3.1 Example of Calibration and Test Procedure......................................................................................................18
3.2 Connection Diagram..........................................................................................................................................19
3.3 Result Description..............................................................................................................................................19
3.4 DisplayPort Parameters.....................................................................................................................................20
3.4.1 Sequencer Parameters.............................................................................................................................20
3.4.2 Group Parameters.....................................................................................................................................20
3.4.3 Procedure Parameters..............................................................................................................................21
4 Connection Diagrams................................................................................................................................22
4.1 DisplayPort Connection Diagrams.....................................................................................................................22
4.1.1 ParBERT Configuration.............................................................................................................................22
4.1.2 J-BERT N4903B Configuration.................................................................................................................27
4.1.3 J-BERT M8020A Configuration.................................................................................................................31
4.1.4 J-BERT N4903B and Switch Configuration...............................................................................................35
4.1.5 J-BERT M8020A and Switch Configuration..............................................................................................38
4.2 Embedded DisplayPort (eDP) Connection Diagrams........................................................................................41
4.2.1 J-BERT N4903B Configuration.................................................................................................................41
4.2.2 J-BERT M8020A Configuration.................................................................................................................44
4.2.3 J-BERT N4903B and Switch Configuration...............................................................................................47
4.2.4 J-BERT M8020A and Switch Configuration..............................................................................................49
4.3 Switch Connections...........................................................................................................................................51
5 Sink Calibration Procedures.....................................................................................................................52
5.1 Calibration Overview..........................................................................................................................................52
5.2 DisplayPort Sink Calibrations.............................................................................................................................54
5.2.1 Intersymbol Interference (ISI) Calibration.................................................................................................54
5.2.2 Random Jitter Calibration..........................................................................................................................57
5.2.3 High Speed Sinusoidal Jitter Calibration...................................................................................................59
5.2.4 Fixed Sinusoidal Jitter Calibration.............................................................................................................61
5.2.5 Eye Opening Calibration...........................................................................................................................63
5.2.6 Aggressor Amplitude Calibration...............................................................................................................66
5.2.7 Data Skew Calibration...............................................................................................................................68
5.3 Embedded DisplayPort Sink Calibrations..........................................................................................................70
5.3.1 ISI Calibration............................................................................................................................................70
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5.3.2 Random Jitter Calibration..........................................................................................................................72
5.3.3 Fixed Sinusoidal Jitter Calibration.............................................................................................................74
5.3.4 Eye Opening Calibration...........................................................................................................................76
5.3.5 Aggressor Amplitude Calibration...............................................................................................................79
6 Sink Test Procedures.................................................................................................................................81
6.1 DisplayPort Sink Tests.......................................................................................................................................82
6.1.1 Jitter Tolerance Test..................................................................................................................................83
6.1.2 Jitter Tolerance Test Zero-Length Cable..................................................................................................85
6.1.3 Jitter Tolerance Characterization Test......................................................................................................87
6.1.4 Data Rate Deviation Test..........................................................................................................................90
6.1.5 Intra-Pair Skew Test..................................................................................................................................92
6.1.6 Sensitivity Test..........................................................................................................................................94
6.1.7 Variable Parameter Test............................................................................................................................96
6.2 Embedded DisplayPort Sink Tests.....................................................................................................................99
6.2.1 Jitter Tolerance Test.................................................................................................................................99
7 Source Test Procedures..........................................................................................................................102
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List of Figures
Figure 1: J-BERT M8020A Test Setup.............................................................................................................................9
Figure 2: J-BERT N4903B Test Setup.............................................................................................................................9
Figure 3: ParBERT Test Setup........................................................................................................................................9
Figure 4: DisplayPort Station Configuration Icon..........................................................................................................10
Figure 5: DisplayPort Station Selection Window...........................................................................................................10
Figure 6: DisplayPort Station Configuration Window.....................................................................................................11
Figure 7: DisplayPort Instruments Configuration...........................................................................................................12
Figure 8: ValiFrame DisplayPort Icon............................................................................................................................12
Figure 9: ValiFrame DisplayPort User Interface............................................................................................................13
Figure 10: Configure DUT Panel with (right) and without (left) Database Connection..................................................13
Figure 11: Sink Basic Configuration Parameters (for DisplayPort)................................................................................15
Figure 12: Sink Basic Configuration Parameters (for Embedded DisplayPort).............................................................15
Figure 13: Sink Advanced Configuration Parameters...................................................................................................15
Figure 14: Source Test Configuration Panel..................................................................................................................16
Figure 15: Automation Control Dialog............................................................................................................................17
Figure 16: Automation Control Dialog............................................................................................................................17
Figure 17: Example for DisplayPort Calibration and Test Procedure............................................................................18
Figure 18: Show Connection Dialog..............................................................................................................................19
Figure 19: DisplayPort Sequencer Parameters.............................................................................................................20
Figure 20: DisplayPort Group Parameters....................................................................................................................21
Figure 21: Connection Diagram for DP ParBERT Calibrations (with ISI Box)...............................................................22
Figure 22: Connection Diagram for DP ParBERT Aggressor Amplitude Calibration (with ISI Box)..............................23
Figure 23: Connection Diagram for DP ParBERT Skew Calibration.............................................................................24
Figure 24: Connection Diagram for DP ParBERT Sink Test..........................................................................................25
Figure 25: Connection Diagram for DP ParBERT Zero-Length Test.............................................................................26
Figure 26: Connection Diagram for DP J-BERT N4903B Calibrations (with ISI Box)...................................................27
Figure 27: Connection Diagram for DP J-BERT N4903B Aggressor Amplitude Calibration (with ISI Box)...................28
Figure 28: Connection Diagram for DP J-BERT N4903B Sink Tests............................................................................29
Figure 29: Connection Diagram for DP J-BERT N4903B Zero Length Tests................................................................30
Figure 30: Connection Diagram for J-BERT M8020A Calibrations (with ISI Box).........................................................31
Figure 31: Connection Diagram for DP J-BERT M8020A Aggressor Amplitude Calibration (with ISI Box)...................32
Figure 32: Connection Diagram for DP J-BERT M8020A Sink Tests............................................................................33
Figure 33: Connection Diagram for DP J-BERT M8020A Zero Length Tests................................................................34
Figure 34: Connection Diagram for DP J-BERT N4903B and Switch Calibrations.......................................................35
Figure 35: Connection Diagram for DP J-BERT N4903B and Switch Sink Tests..........................................................36
Figure 36: Connection Diagram for DP J-BERT N4903B and Switch Zero-Length Test...............................................37
Figure 37: Connection Diagram for DP J-BERT M8020A and Switch Calibrations.......................................................38
Figure 38: Connection Diagram for DP J-BERT M8020A and Switch Sink Tests..........................................................39
Figure 39: Connection Diagram for DP J-BERT M8020A and Switch Zero-Length Test...............................................40
Figure 40: Connection Diagram for eDP J-BERT N4903B Calibrations........................................................................41
Figure 41: Connection Diagram for eDP J-BERT N4903B Aggressor Amplitude Calibration........................................42
Figure 42: Connection Diagram for eDP J-BERT N4903B Sink Tests..........................................................................43
Figure 43: Connection Diagram for eDP J-BERT M8020A Calibrations........................................................................44
Figure 44: Connection Diagram for eDP J-BERT M8020A Aggressor Amplitude Calibration.......................................45
Figure 45: Connection Diagram for eDP J-BERT M8020A Sink Tests..........................................................................46
Figure 46: Connection Diagram for eDP J-BERT N4903B and Switch Calibrations.....................................................47
Figure 47: Connection Diagram for eDP J-BERT N4903B and Switch Sink Tests........................................................48
Figure 48: Connection Diagram for eDP J-BERT M8020A and Switch Calibrations.....................................................49
Figure 49: Connection Diagram for eDP J-BERT M8020A and Switch Sink Tests........................................................50
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Figure 50: Connection Diagram for Switch Connections...............................................................................................51
Figure 51: Example of HTML Viewer for ISI Calibration................................................................................................55
Figure 52: Example HTML Viewer for ISI Calibration (with ISI Box).............................................................................56
Figure 53: Example HTML Viewer for Random Jitter Calibration..................................................................................58
Figure 54: Example HTML Viewer for High Speed Sinusoidal Jitter Calibration...........................................................60
Figure 55: Example HTML Viewer for Fixed Sinusoidal Jitter Calibration.....................................................................62
Figure 56: Example HTML Viewer for Eye Opening Calibration...................................................................................65
Figure 57: Example HTML Viewer for Aggressor Amplitude Amplitude Calibration......................................................67
Figure 58: Example HTML Viewer for Data Skew Calibration.......................................................................................69
Figure 59: Example of HTML Viewer for eDP ISI Calibration........................................................................................71
Figure 60: Example HTML Viewer for eDP Random Jitter Calibration..........................................................................73
Figure 61: Example HTML Viewer for eDP Fixed Sinusoidal Jitter Calibration.............................................................75
Figure 62: Example HTML Viewer for eDP Eye Opening Calibration...........................................................................78
Figure 63: Example HTML Viewer for eDP Aggressor Amplitude Amplitude Calibration..............................................80
Figure 64: Example HTML Viewer for Jitter Tolerance Test...........................................................................................84
Figure 65: Example HTML Viewer for Jitter Tolerance Test (Zero-Length)....................................................................86
Figure 66: Example HTML Viewer for Jitter Characterization Test................................................................................89
Figure 67: Example HTML Viewer for Datarate Deviation Test.....................................................................................91
Figure 68: Example HTML Viewer for Intra-Pair Skew Test..........................................................................................93
Figure 69: Example HTML Viewer for Sensitivity Test...................................................................................................95
Figure 70: Variable Parameter Test Window.................................................................................................................96
Figure 71: Example HTML Viewer for Variable Parameter Test....................................................................................97
Figure 72: Example HTML Viewer for eDP Jitter Tolerance Test.................................................................................101
Figure 73: Source Test List..........................................................................................................................................102
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List of Tables
Table 1: DUT Parameter List.........................................................................................................................................14
Table 2: Sink Test Configuration Parameters................................................................................................................16
Table 3: Allowed Vdiff_pp – Pre-emphasis Combinations.............................................................................................17
Table 4: Smiley Result Description table.......................................................................................................................19
Table 5: DisplayPort Sequencer Parameters.................................................................................................................20
Table 6: DisplayPort Group Parameters........................................................................................................................21
Table 7: Sink Calibration Parameters............................................................................................................................53
Table 8: Data Table for ISI Calibration...........................................................................................................................55
Table 9: Data Table for ISI Calibration (with ISI Box).....................................................................................................56
Table 10: Data Table for Random Jitter Calibration.......................................................................................................58
Table 11: Data Table for High Speed Sinusoidal Jitter Calibration................................................................................60
Table 12: Data Table for Fixed Sinusoidal Jitter Calibration..........................................................................................63
Table 13: Data Table for Eye Opening Calibration.........................................................................................................65
Table 14: Data Table for Aggressor Amplitude Calibration............................................................................................67
Table 15: Data Table for Data Skew Calibration............................................................................................................69
Table 16: Data Table for eDP ISI Calibration.................................................................................................................71
Table 17: Data Table for eDP Random Jitter Calibration...............................................................................................73
Table 18: Data Table for eDP Fixed Sinusoidal Jitter Calibration..................................................................................76
Table 19: Data Table for eDP Eye Opening Calibration.................................................................................................79
Table 20: Data Table for eDP Aggressor Amplitude Calibration....................................................................................80
Table 21: Sink Rx Tests Parameters..............................................................................................................................82
Table 22: Data Table for Jitter Tolerance Test................................................................................................................84
Table 23: Data Table for Jitter Tolerance Test (Zero-Length).........................................................................................86
Table 24: Data Table for Jitter Characterization Test.....................................................................................................88
Table 25: Data Table for Datarate Deviation Test..........................................................................................................91
Table 26: Data Table for Intra-Pair Skew Test...............................................................................................................93
Table 27: Data Table for Sensitivity Test........................................................................................................................96
Table 28: Data Table for Variable Parameters Test.......................................................................................................98
Table 29: Data Table for eDP Jitter Tolerance Test......................................................................................................101
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1 Introduction
1 Introduction
The BitifEye “ValiFrame” Test Automation software is globally marketed and supported by Keysight Technologies (formerly
Agilent Technologies) as N5990A. This document describes the calibrations and test procedures conducted by N5990A
ValiFrame for DisplayPort in detail. The N5990A software implements the compliance tests according to the requirements
of the latest DP 1.2b and eDP1.4 MOI (Method of Implementation) draft, and also offers additional custom characterization
tests to provide more details of the DUT (Device Under Test) behavior beyond the limits of compliance testing.
The ValiFrame DisplayPort Receiver tests support automatic control of the J-BERT M8020A and J-BERT N4903 highperformance BERTs (Bit Error Ratio Testers), and of the 81250A ParBERT (Parallel Bit Error Ratio Tester)-based
DisplayPort generator hardware for physical layer tests, including external clock and jitter sources such as the ESG Vector
Signal Generator and the 81160A PulsAr (which are required for the ParBERT setup). An Auxiliary Channel Controller is
required-0 as well as suitable ISI (Inter-Symbol Interference) generators. The software runs on a standard Windows XP or
Windows 7 PC and controls the hardware test resources through appropriate interfaces such as LAN (Local Area
Network).
Figure 1, Figure 2 and Figure 3 show the receiver test setup for J-BERT and ParBERT configurations.
Figure 1: J-BERT M8020A Test Setup
Figure 2: J-BERT N4903B Test Setup
Figure 3: ParBERT Test Setup
The N5990A Test Automation software supports the Keysight (or Agilent) Technologies Electrical Performance and
Compliance Test Software U7232C for the DisplayPort Source tests. A real-time oscilloscope (Infiniium Series 90000 or
higher) is required to run the U7232C software.
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2 ValiFrame DisplayPort Station
Refer to the “N5990A_Getting_Started_Guide.pdf” for instructions on how to install and start the ValiFrame Test
Automation software platform. After the software has been installed, two icons are added to the desktop as shown in
Figure 4 and Figure 8. One is for the Station Configuration and the other for ValiFrame.
2.1 ValiFrame DisplayPort Station Configuration
The ValiFrame Station Configuration needs to be started prior to ValiFrame. It allows the user to select the application (i.e.,
MHL, PCI Express 3, HDMI …) and the set of instruments used for it. Start the software with a double-click of the left
mouse button on the icon (see Figure 4) or, alternatively, start the application from “All Programs / BitifEye / DisplayPort /
ValiFrame DisplayPort Station Configuration”.
Figure 4: DisplayPort Station Configuration Icon
When the software is started, the Station Selection window appears as shown in Figure 5. The “DisplayPort Station” is
preselected.
Figure 5: DisplayPort Station Selection Window
If the option N5990A opt. 001 was purchased, the interface to SQL databases (and web browsers) is available. The
connection to the database application server is established by unchecking the default “Database Offline” selection and
entering the IP address of the server.
Here the viewer for the test results can be selected. Choices are (Microsoft) Excel or HTML.
After the DisplayPort station has been selected, press “Next” button to continue. The Station Configuration window is
displayed as shown in Figure 6. It shows the possible instrument combinations that can be used for DisplayPort testing. It
contains such options as:
•
Pattern Generator
•
AUX Channel Controller
•
Use Tx Switch / Use Rx Switch
•
Company Name
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Figure 6: DisplayPort Station Configuration Window
2.1.1 Pattern Generator
ValiFrame supports three different station settings:
•
J-BERT M8020A
•
J-BERT N4903B
•
ParBERT 7G
With all the configurations, the Artek CLE1000-A2 (Variable ISI Channel) can be selected to fine-tune the ISI value. This
box is connected via USB to the PC where ValiFrame is run. If this is not selected, the ISI value needs to be adjusted
manually and the selection of the ISI channel is up to the user.
2.1.2 AUX Channel Controller
For testing, an Auxiliary Channel Controller (short “AUX Channel Controller” or “AUX Controller”) is required. The AUX
Channel Controller is the bidirectional communication lane for DisplayPort. ValiFrame supports the following AUX
Controllers:
•
Unigraf DPT-200
•
Agilent W2642A (obsolete, no longer available)
For Receiver (short “Rx”) tests, the AUX controller is used to read and write the DisplayPort Configuration Data (DPCD)
register in order to prepare the DUT for Rx testing and to read the DUT state. For Tx test, the AUX controller is used to
read and write the DPCD register in order to control the DUT to generate specific signals.
2.1.3 Use Tx Switch / Use Rx Switch
The use of this switch allows the required number of connection changes to be reduced.
The Tx scope app provides switch support. Through the option “Use Tx Switch” the switch handling will be activated on the
scope side.
For Rx tests the switch solution is only available for the two J-BERT generators N4903B and M8020A. When Rx Switch is
selected, the Artek CLE1000-A2 is also automatically selected because it is required for the setup.
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2.1.4 Oscilloscope Application Supplier Company Name
Agilent Technologies was the supplier of the initial version of the DisplayPort oscilloscope application software. Since the
foundation of Keysight Technologies in 2014, Keysight has supplied this application. Select the proper company name:
•
Agilent (likely holds for oscilloscopes purchased prior to July 2014)
•
Keysight (likely holds for oscilloscopes purchased after July 2014).
If you do not know the purchase date or you are not sure about the software supplier company name, check by opening
the U7232C software on the oscilloscope and choosing “Help→About …” in the menu. In the About dialog, the supplier
company name is shown.
Once the DisplayPort station is configured, the instrument addresses must be set. An example of the instrument
configuration is shown in Figure 7.
Figure 7: DisplayPort Instruments Configuration
After the installation process, all instruments are configured by default in “Offline” mode. In this simulation mode, hardware
does not need to be physically connected to the test controller PC. The ValiFrame cannot connect to any instrument in this
mode. In order to control the instruments that are connected to the PC, the instrument address must be entered. The
address depends on the bus type used for the connection, for example, GPIB (General Purpose Interface BUS) or LAN
(Local Area Network). Most of the instruments used in the DisplayPort station use a VISA (Virtual Instrument System
Architecture) connection, except the ParBERT and the DisplayPort AUX Controller. To determine the VISA address, run
the “VISA Connection Expert” (right-click on the VISA icon in the task bar and select the first entry “ Keysight Connection
Expert”). Enter the instrument addresses in the “Station Configuration Wizard”, for example by copying and pasting the
address strings from the Connection Expert entries. After the address strings have been entered, click on the “Apply
Address” button before checking the “Offline” box to set all instruments needed to online and then press “Check
Connections” button to verify that the connections for the instruments are established properly. If anything is wrong in the
Instrument Address, a window is displayed with a message describing the problem.
2.2 Starting ValiFrame DisplayPort Station
Start the ValiFrame DisplayPort station with a double click on the “ValiFrame DisplayPort” icon on the desktop as shown in
Figure 8, or, alternatively, start from “Start / All Programs / BitifEye / DisplayPort / ValiFrame DisplayPort”.
Figure 8: ValiFrame DisplayPort Icon
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Starting the ValiFrame DisplayPort station opens the window shown in Figure 9.
Figure 9: ValiFrame DisplayPort User Interface
The DUT needs to be configured before any test or calibration procedure is run. Click on the “Configure DUT” button to
pop up the Configure Product window (Figure 10).
2.3 Configure DUT
The configure Product window allows the user to select Product and Test parameters that are going to be used later in
several calibration and test procedures. Some parameters will determine the set of tests displayed.
Figure 10: Configure DUT Panel with (right) and without (left) Database Connection
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If the database option is selected in the ValiFrame DisplayPort Station Selection window (see Figure 5), the Configure
DUT panel appears as shown on the right side of Figure 10. To configure the DUT with database connection, enter values
(any) for “Product Number”, “Serial Number”, and “Product ID”. Then, press on the “Register Product” button to register the
database connection with the provided values. Pressing on “Register Product” button, enables the button “OK”. With a
click on the “OK” button, the DUT is configured with the selected parameters. The procedures run with the database
settings are stored at ValiFrame Webviewer and those can be viewed by selecting the “Product Number” and “Serial
Number” (these values should be the same as those provided in Figure 10).
2.3.1 DUT Parameters
In Figure 10, the DUT parameters, such as Product type, CTS Version, and compliance mode or expert mode, can be
selected. The DUT Parameters are listed in Table 1.
Parameter name
Parameter description
Product Parameters
Product Number
Name of the Product. Used to identify the product when database option is selected.
Serial Number
Serial number of the Product. Used to identify the product when database option is
selected.
Port Name
Select the port number between 1 and 10.
Product Type
The product type can be chosen as:
• DP/eDP Sink: PC Monitors
• DP/eDP Source: Computer, Motherboards, ICs, Graphic Cards
Description
Description of the Product.
CTS Version
The selected CTS version defines the calibrations and tests according to the DisplayPort
CTS revision.
Number of Lanes
DUTs with 1, 2 or 4 lanes can be tested.
Test Parameters
User Name
User name text field.
Comment
Text file for user comments.
Initial Start Date
Time stamp of the start of the current session.
Last Test Date
Time stamp of the last test conducted in the current session.
Compliance Mode
Test are conducted as mandated by the CTS. The parameters that are shown in the
calibration and test procedures cannot be modified by the user.
Expert Mode
Calibrations and tests can be conducted beyond the limits and constraints of the CTS. The
parameters that are shown in the calibrations and test procedures can be modified by the
user.
Table 1: DUT Parameter List
There are two different test configurations: Sink and Source. Each one has different parameters to select, which
characterize the tests.
2.3.2 Sink Test Configuration
This configuration appears when Sink is selected as product type. There are two parameter groups which offer different
possibilities for running the test and calibrations:
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1.
Basic parameters: such as the data rates supported by the DUT. See Figures 11 and 12.
Figure 11: Sink Basic Configuration Parameters (for DisplayPort)
Figure 12: Sink Basic Configuration Parameters (for Embedded DisplayPort)
2.
Advanced parameters: Useful features for debugging purposes. See Figure 13.
Figure 13: Sink Advanced Configuration Parameters
All the Sink Configuration Parameters are described in Table 2.
Parameter name
Parameter description
Basic Parameters
Plug Fixture
Select the Plug Fixture from those available: Wilder Technologies DP-TPA-P, Keysight DP
Plug Fixture W2641B or mDP Plug Fixture.
Receptacle Fixture
Select the Receptacle Fixture from those available: Wilder Technologies DP-TPA-R,
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2 ValiFrame DisplayPort Station
BitifEye DP-RTF-0001, or BitifEye DP-RTF-0002
Supported Data Rates
Depending on the maximum supported data rate, different sets of tests will be displayed.
TPS3 Supported
If the device supports data rates higher than HBR, then it must support TPS3. If it supports
data rates lower than HBR, TPS3 is just recommended.
Advanced Parameters
Use Dummy AUX Channel
Controller
If this box is checked, a physical AUX controller is not needed for the tests. ValiFrame will
be responsible for the communication with the DUT.
Use Differential Probe for
Calibration
Differential probes can be used for the calibrations instead of Direct SMA Single-Ended
connections.
Use 4-Way Dividers for
Aggressor Lanes
For ParBERT setup, power dividers can be used or not (one clock generator or 3 clock
generators). If they are selected, they can be 4-way or 3-way power dividers. For J-BERT
N4903B setup, the use of power dividers is mandatory, but they can be 4-way or 3-way
power dividers. For J-BERT M8020A setup, only 3-way power dividers can be used.
Keep Signals after test
When the test is done, ValiFrame keeps the tested signal, and the user can check it on the
scope.
Skip Link Training
Frequency lock and symbol lock are skipped during Sink testing.
ISI Cal Lane per Lane
An ISI calibration for each lane will be performed. If this box is not checked, the same ISI
calibration table will be used for every lane test. This is recommended if the BitifEye DPRTF-0001 or BitifEye DP-RTF-0002 receptacle fixture is used.
DPCD Revision 1.1
If this option is selected, the DPCD Revision 1.1 register layout will be used during testing
regardless of the CTS version.
Query DUT capabilities
By selecting this option, the capabilities of the DUT are returned after communication have
been started with the AUX Controller. They will be automatically selected in the
configuration window.
Table 2: Sink Test Configuration Parameters
2.3.3 Source Test Configuration
This configuration appears when Source is selected as product type. Figure 14 shows the Configure Product section for
the source test configuration parameters.
Figure 14: Source Test Configuration Panel
There are some tests that appear only if the maximum supported data rate is HBR2. For this data rate, it is also possible to
choose one of the preferred settings, according to the combinations of Table 3.
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Pre-emphasis Level
Level 0
Vdiff_pre_pp
Level 1
Vdiff_pre_pp
Level 2
Vdiff_pre_pp
Level 3
Vdiff_pre_pp
Voltage Swing Level 0
Required
Required
Required
Optional
Voltage Swing Level 1
Required
Required
Required
Not allowed
Voltage Swing Level 2
Required
Required
Not allowed
Not allowed
Voltage Swing Level 3
Optional
Not allowed
Not allowed
Not allowed
Table 3: Allowed Vdiff_pp – Pre-emphasis Combinations
The Automation Setup button allows the automation to be enabled as shown in Figure 15. The AUX Channel Controller
can be selected in the Driver options and the Address of this instrument must be set. If the Keysight W2642A is used, the
IP Address is set in the white space, but if the Unigraf DPTC is used, the COM port where this is connected is required.
Figure 15: Automation Control Dialog
When the DUT configuration is finished, the oscilloscope connection must be specified by selecting the Direct SMA
connections and Differential Probe connections that are going to be used (Figure 16). It is recommended that you use the
same number of differential connections as SMA connections, in order to have access to all the possible tests and the
least number of re-connections.
Figure 16: Automation Control Dialog
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3 Calibration and Test Procedures
3 Calibration and Test Procedures
During the execution of all calibration and test procedures, the results are displayed automatically in a data table as well
as graphically. The viewer can be either a MS-Excel or a HTML worksheet; this can be chosen in the Station Configuration
window (see Figure 5).Once a specific calibration or test procedure is finished, the MS Excel/HTML worksheet is closed.
To reopen it at any time, double click on the respective procedure. All calibration and test data worksheets can be saved in
a workbook by selecting “File > Save Results as Workbook…” at any time. It is recommended that this step is carried out
at least at the end of each ValiFrame run. If the calibration and test procedures are conducted during the same ValiFrame
run, the calibration and test result worksheets are combined in the workbook. If a test procedure is conducted without prior
execution of calibration procedures in the same test run, only the test results will be saved to the workbook.
As a safety feature, all calibration and test procedure results are saved by default to the ValiFrame “Tmp” directory. In
addition to the calibration data worksheets, calibration data files are also generated. These files are saved by default to the
ValiFrame calibrations folder (refer to “N5990A_Getting_Started_Guide.pdf”).
3.1 Example of Calibration and Test Procedure
All calibration and test procedures are organized in corresponding groups, such as “Calibration” and “Sink Lane X” for Sink
devices and “Source PHY” for Source devices. For most of the calibration and test procedures, some specific parameters
can be set in expert mode by the user. In Figure 17, the “ISI Calibration RBR” procedure is highlighted as an example and
the respective calibration parameters are shown on the right-hand side of the ValiFrame user interface. This is achieved by
clicking on the calibration name. To start the calibration or test procedure, check the box corresponding to the selected
procedure. Then, the “Start” button is enabled and colored green. Pressing the “Start” button runs the calibration/test.
Figure 17: Example for DisplayPort Calibration and Test Procedure
CAUTION Before executing any calibration or test procedure, ensure that the DisplayPort Station Configuration is
conducted properly with all necessary instruments such as the Infiniium oscilloscope and J-BERT set to “online”.
All calibrations can be run in offline mode, this means, without any instrument connected. The offline mode is
intended for product demonstrations with simulated data. CALIBRATIONS RUN IN OFFLINE MODE DO NOT
GENERATE VALID CALIBRATION DATA!
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3.2 Connection Diagram
The connection diagram is displayed by right-clicking on the desired test or calibration and selecting “Show Connection” as
shown in Figure 18. Alternatively, the connection diagram is displayed automatically on starting the selected test or
calibration.
Figure 18: Show Connection Dialog
3.3 Result Description
Once the selected procedures are running successfully, the individual procedure displays the result by representing the
smiley in different styles such as given below (see Table 4).
Smiley
Description
This indicates that the procedure was passed successfully in the previous run and the results are available.
This indicates that the procedure was passed in offline mode previously and the results are available.
This indicates that the procedure was passed successfully in the last run.
This indicates that the procedure was aborted/disturbed somehow and failed in the previous run.
This indicates that the procedure was aborted/disturbed somehow and failed in the last run.
This indicates that the procedure was failed in the previous run.
This indicates that the procedure was failed in the last run.
Generally this kind of smiley indicates two results, for instance the results of the last run (left half) and the
result of the previous run (right half). In this example, the procedure was passed successfully in the last run
but not completely run in the previous run.
Table 4: Smiley Result Description table
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3.4 DisplayPort Parameters
The DisplayPort parameters are of three types:
1.
Sequencer Parameters
2.
Group Parameters
3.
Procedure Parameters
3.4.1 Sequencer Parameters
The sequencer parameters control the flow of the test sequencer, not the behavior of individual procedures. They are
identical across all versions of ValiFrame. One of them, Repetitions, is available for all procedures and groups in the
procedure tree. The others are only available for procedures. Like all other parameters, the sequencer parameters are
shown on the right side of the ValiFrame user interface and they can be changed by the user as illustrated in Figure 19.
Figure 19: DisplayPort Sequencer Parameters
All sequencer parameters are listed in alphabetical order in Table 5.
Parameter Name
Parameter Description
Procedure Error Case
Behavior
“Proceed With Next Procedure”: If an error occurs in the current test or calibration
procedure, continue by running the next procedure in the sequence.
“Abort Sequence”: Abort the execution of the sequence.
Procedure Failed Case
Behavior
“Proceed With Next Procedure”: If the current test or calibration procedure fails, continue by
running the next procedure in the sequence.
“Abort Sequence”: Abort the execution of the sequence.
Repetitions
The number of times the group or procedure is going to be repeated. If the value is '0', it
runs only once.
Table 5: DisplayPort Sequencer Parameters
3.4.2 Group Parameters
The group parameters are used for several related calibration or test procedures. They are shown on the right side of the
ValiFrame user interface when the selected entry of the procedure tree on the left is a group instead of an individual
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procedure.
The DisplayPort Test Software has two other group parameters (in addition to “Repetitions) on the top level of the
procedure tree as shown in Figure 20. These will be common to all ValiFrame procedures.
Figure 20: DisplayPort Group Parameters
Table 6 describes the group parameters.
Parameter Name
Parameter Description
DisplayPort
Use Differential Probe
Use channel subtraction instead of using a differential probe; only recommended if the
oscilloscope supports hardware channel subtraction.
Use Dummy AUX Channel If this property is set to true, the calls for the AUX channel controller will be shown as dialogs
Controller
and it is left up to the user to deal with how to get the information.
Table 6: DisplayPort Group Parameters
3.4.3 Procedure Parameters
The Procedure Parameters are all parameters that do not fall into one of the previously described categories. They are
shown on the right side of the ValiFrame user interface when the selected entry of the procedure tree on the left is an
individual procedure. They only change the behavior of that single procedure. Procedures often have parameters with the
same name, but settings always apply only on a procedure basis, and the meaning may be slightly different. These
parameters are listed in the chapters dealing with the procedure they belong to.
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4 Connection Diagrams
4 Connection Diagrams
4.1 DisplayPort Connection Diagrams
For each configuration, use the required instrument list for DP1.2b according to the MOI.
4.1.1 ParBERT Configuration
Calibrations
For calibrations using the ParBERT Configuration use the connection diagram shown in Figure 21.
Figure 21: Connection Diagram for DP ParBERT Calibrations (with ISI Box)
Instructions:
•
Connect the vector signal generator RF OUTPUT to the first ParBERT clock module CLK INPUT.
•
Connect the function/arbitrary generator OUT 1 to the ParBERT generator DELAY CTRL input of the first
ParBERT group.
•
Connect the data output OUT of the data ParBERT generator group to the Artek CLE1000-A2 via blocking
capacitors and 60 ps TTCs (if the Artek box was not selected, use your own ISI Adjustment).
•
Connect the Artek CLE1000-A2 output to the lane under test of the DisplayPort Plug fixture.
•
Connect the aggressor lanes via blocking capacitors and 150 ps TTCs to the DisplayPort plug fixture according
to your setup:
◦
With power divider: connect the data output of the first clock ParBERT generator to the 3- or 4-way power
dividers. Connect the power divider outputs to the aggressor lanes of the fixture.
◦
Without power dividers: connect each output of the clock ParBERT generators to each aggressor lane of
the Plug fixture.
•
Connect the lane under test from the DisplayPort Receptacle fixture to the oscilloscope according to the selected
way: either with Differential Probe (connected to CH1) or directly with SMA connections (connected to CH1 and
CH3).
•
Connect CH4 of the oscilloscope to the clock output of the first data ParBERT generator group.
•
Connect 50 Ω terminations to the aggressor lanes of the DisplayPort Receptacle fixture.
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Aggressor Amplitude Calibration
For Aggressor Amplitude Calibration using the ParBERT Configuration use the connection diagram shown in Figure 22.
Figure 22: Connection Diagram for DP ParBERT Aggressor Amplitude Calibration (with ISI Box)
Instructions:
•
Connect the vector signal generator RF OUTPUT to the first ParBERT clock module CLK INPUT.
•
Connect the function/arbitrary generator OUT 1 to the ParBERT generator DELAY CTRL input of the first
ParBERT group.
•
Connect the data output OUT of the data ParBERT generator group to the Artek CLE1000-A2 via blocking
capacitors and 60 ps TTCs (if the Artek box was not selected, use your own ISI Adjustment).
•
Connect the Artek CLE1000-A2 output to the lane under test of the DisplayPort Plug fixture.
•
Connect the aggressor lanes via blocking capacitors and 150 ps TTCs to the DisplayPort plug fixture according
to your setup:
◦
With power divider: connect the data output of the first clock ParBERT generator to the 3- or 4-way power
dividers. Connect the power divider outputs to the aggressor lanes of the fixture.
◦
Without power dividers: connect each output of the clock ParBERT generators to each aggressor lane of
the Plug fixture.
•
Connect one of the aggressor lanes (any lane other than the lane under test) from the DisplayPort Receptacle
fixture to the oscilloscope according to the selected way: either with Differential Probe (connected to CH1) or
directly with SMA connections (connected to CH1 and CH3).
•
Connect CH4 of the oscilloscope to the clock output of the first data ParBERT generator group.
•
Connect 50 Ω terminations to the aggressor lanes of the DisplayPort Receptacle fixture.
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Skew Calibration
For Data Skew Calibration using the ParBERT Configuration use the connection diagram shown in Figure 23.
Figure 23: Connection Diagram for DP ParBERT Skew Calibration
Instructions:
•
Connect the vector signal generator RF OUTPUT to the first ParBERT clock module CLK INPUT.
•
Connect the function/arbitrary generator OUT 1 to the ParBERT generator DELAY CTRL input of the first
ParBERT group.
•
Connect the data output OUT of the first ParBERT generator group of the second ParBERT clock module to the
“Probe” input of the second ParBERT clock module, using a SMA-to-BCN adapter.
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Sink Tests
For Sink Tests using the ParBERT Configuration use the connection diagram shown in Figure 24.
Figure 24: Connection Diagram for DP ParBERT Sink Test
Instructions:
•
Connect the vector signal generator RF OUTPUT to the first ParBERT clock module CLK INPUT.
•
Connect the function/arbitrary generator OUT 1 to the ParBERT generator DELAY CTRL input of the first
ParBERT group.
•
Connect the data output OUT of the data ParBERT generator group to the Artek CLE1000-A2 via blocking
capacitors and 60 ps TTCs (if the Artek box was not selected, use your own ISI Adjustment).
•
Connect the Artek CLE1000-A2 output to the lane under test of the DisplayPort Plug fixture.
•
Connect the aggressor lanes via blocking capacitors and 150 ps TTCs to the DisplayPort plug fixture according
to your setup:
◦
With power divider: connect the data output of the first clock ParBERT generator to the 3- or 4-way power
dividers. Connect the power divider outputs to the aggressor lanes of the fixture.
◦
Without power dividers: connect each output of the clock ParBERT generators to each aggressor lane of
the Plug fixture.
•
Connect the AUX Controller to the DisplayPort Plug Fixture.
•
Connect the DisplayPort Plug fixture to the DUT.
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Zero-Length Tests
For Zero-Length Tests using the ParBERT Configuration use the connection diagram shown in Figure 25.
Figure 25: Connection Diagram for DP ParBERT Zero-Length Test
Instructions:
•
Connect the vector signal generator RF OUTPUT to the first ParBERT clock module CLK INPUT.
•
Connect the function/arbitrary generator OUT 1 to the ParBERT generator DELAY CTRL input of the first
ParBERT group.
•
Connect the data output OUT of the data ParBERT generator group to the lane under test of the DisplayPort
Plug fixture via blocking capacitors and 60ps TTCs (no ISI channel).
•
Connect the aggressor lanes via blocking capacitors and 150 ps TTCs to the DisplayPort plug fixture according
to your setup:
◦
With power divider: connect the data output of the first clock ParBERT generator to the 3- or 4-way power
dividers. Connect the power divider outputs to the aggressor lanes of the fixture.
◦
Without power dividers: connect each output of the clock ParBERT generators to each aggressor lane of
the Plug fixture.
•
Connect the AUX Controller to the DisplayPort Plug Fixture.
•
Connect the DisplayPort Plug fixture to the DUT.
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4.1.2 J-BERT N4903B Configuration
Calibrations
For calibrations using J-BERT N4903B Configuration use the connection diagram shown in Figure 26.
Figure 26: Connection Diagram for DP J-BERT N4903B Calibrations (with ISI Box)
Instructions:
•
Connect the J-BERT data output to the Artek CLE1000-A2 via blocking capacitors and 60 ps TTCs (if the Artek
box was not selected, use your own ISI Adjustment).
•
Connect the Artek CLE1000-A2 to the lane under test of the DisplayPort Plug fixture.
•
Connect the J-BERT TRIGGER/REF CLK output to the 3-way power dividers (4-way if you selected them in the
Product Configuration) via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the aggressor lanes of the DisplayPort plug fixture.
•
Connect the lane under test from the DisplayPort Receptacle fixture to the oscilloscope according to the selected
way: with Differential Probe (connected to CH1) or directly with SMA connections (connected to CH1 and CH3).
•
Connect CH4 of the oscilloscope to the clock output CLK of the J-BERT. Connect a 50Ω termination to the
negative clock output.
•
Connect 50Ω terminations to the aggressor lanes of the DisplayPort Receptacle fixture.
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Aggressor Amplitude Calibration
For Aggressor Amplitude Calibration using the J-BERT N4903B Configuration use the connection diagram shown in Figure
27.
Figure 27: Connection Diagram for DP J-BERT N4903B Aggressor Amplitude Calibration (with ISI Box)
Instructions:
•
Connect the J-BERT data output to the Artek CLE1000-A2 via blocking capacitors and 60 ps TTCs (if the Artek
box was not selected, use your own ISI Adjustment).
•
Connect the Artek CLE1000-A2 to the lane under test of the DisplayPort Plug fixture.
•
Connect the J-BERT TRIGGER/REF CLK output to the 3-way power dividers (4-way if you selected them in the
Product Configuration) via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the aggressor lanes of the DisplayPort plug fixture.
•
Connect one of the aggressor lanes (any lane other than the lane under test) from the DisplayPort Receptacle
fixture to the oscilloscope according to the selected way: with Differential Probe (connected to CH1) or directly
with SMA connections (connected to CH1 and CH3).
•
Connect CH4 of the oscilloscope to the clock output CLK of the J-BERT. Connect a 50 Ω termination to the
negative clock output.
•
Connect 50 Ω terminations to the aggressor lanes of the DisplayPort Receptacle fixture.
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Sink Tests
For Sink Tests using the J-BERT N4903B Configuration use the connection diagram shown in Figure 28.
Figure 28: Connection Diagram for DP J-BERT N4903B Sink Tests
Instructions:
•
Connect the J-BERT data output to the Artek CLE1000-A2 via blocking capacitors and 60 ps TTCs (if the Artek
box was not selected, use your own ISI Adjustment).
•
Connect the Artek CLE1000-A2 to the lane under test of the DisplayPort Plug fixture.
•
Connect the J-BERT TRIGGER/REF CLK output to the 3-way power dividers (4-way if you selected them in the
Product Configuration) via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the aggressor lanes of the DisplayPort plug fixture.
•
Connect the AUX Controller to the DisplayPort Plug Fixture.
•
Connect the DisplayPort Plug fixture to the DUT.
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Zero-Length Tests
For Zero-Length Tests using the J-BERT N4903B Configuration use the connection diagram shown in Figure 29.
Figure 29: Connection Diagram for DP J-BERT N4903B Zero Length Tests
Instructions:
•
Connect the J-BERT data output to the lane under test of the DisplayPort Plug fixture via blocking capacitors and
60 ps TTCs.
•
Connect the J-BERT TRIGGER/REF CLK output to the 3-way power dividers (4-way if you selected them in the
Product Configuration) via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the aggressor lanes of the DisplayPort plug fixture.
•
Connect the AUX Controller to the DisplayPort Plug Fixture.
•
Connect the DisplayPort Plug fixture to the DUT.
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4.1.3 J-BERT M8020A Configuration
Calibrations
For calibrations using the J-BERT M8020A Configuration use the connection diagram shown in Figure 30.
Figure 30: Connection Diagram for J-BERT M8020A Calibrations (with ISI Box)
Instructions:
•
Connect the J-BERT data output to the Artek CLE1000-A2 via blocking capacitors and 60 ps TTCs (if the Artek
box was not selected, use your own ISI Adjustment).
•
Connect the Artek CLE1000-A2 to the lane under test of the DisplayPort Plug fixture.
•
Connect the J-BERT TRIG output to the 3-way power dividers via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the aggressor lanes of the DisplayPort plug fixture.
•
Connect the lane under test from the DisplayPort Receptacle fixture to the oscilloscope according to the selected
way: with Differential Probe (connected to CH1) or directly with SMA connections (connected to CH1 and CH3).
•
Connect CH4 of the oscilloscope to the clock output CLK of the J-BERT. Connect a 50 Ω termination to the
negative clock output.
•
Connect 50 Ω terminations to the aggressor lanes of the DisplayPort Receptacle fixture.
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Aggressor Amplitude Calibration
For Aggressor Amplitude Calibration using the J-BERT M8020A Configuration use the connection diagram shown in Figure
31.
Figure 31: Connection Diagram for DP J-BERT M8020A Aggressor Amplitude Calibration (with ISI Box)
Instructions:
•
Connect the J-BERT data output to the Artek CLE1000-A2 via blocking capacitors and 60 ps TTCs (if the Artek
box was not selected, use your own ISI Adjustment).
•
Connect the Artek CLE1000-A2 to the lane under test of the DisplayPort Plug fixture.
•
Connect the J-BERT TRIG output to the 3-way power dividers via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the aggressor lanes of the DisplayPort plug fixture.
•
Connect one of the aggressor lanes (any lane other than the lane under test) from the DisplayPort Receptacle
fixture to the oscilloscope according to the selected way: with Differential Probe (connected to CH1) or directly
with SMA connections (connected to CH1 and CH3).
•
Connect CH4 of the oscilloscope to the clock output CLK of the J-BERT. Connect a 50 Ω termination to the
negative clock output.
•
Connect 50 Ω terminations to the aggressor lanes of the DisplayPort Receptacle fixture.
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Sink Tests
For Sink Tests using the J-BERT M8020A Configuration use the connection diagram shown in Figure 32.
Figure 32: Connection Diagram for DP J-BERT M8020A Sink Tests
Instructions:
•
Connect the J-BERT data output to the Artek CLE1000-A2 via blocking capacitors and 60 ps TTCs (if the Artek
box was not selected, use your own ISI Adjustment).
•
Connect the Artek CLE1000-A2 to the lane under test of the DisplayPort Plug fixture.
•
Connect the J-BERT TRIG output to the 3-way power dividers via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the aggressor lanes of the DisplayPort plug fixture.
•
Connect the AUX Controller to the DisplayPort Plug Fixture.
•
Connect the DisplayPort Plug fixture to the DUT.
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Zero-Length Tests
For Zero-Length Tests using the J-BERT M8020A Configuration use the connection diagram shown in Figure 33.
Figure 33: Connection Diagram for DP J-BERT M8020A Zero Length Tests
Instructions:
•
Connect the J-BERT data output to the lane under test of the DisplayPort Plug fixture via blocking capacitors and
60 ps TTCs.
•
Connect the J-BERT TRIG output to the 3-way power dividers via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the aggressor lanes of the DisplayPort plug fixture.
•
Connect the AUX Controller to the DisplayPort Plug Fixture.
•
Connect the DisplayPort Plug fixture to the DUT.
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4.1.4 J-BERT N4903B and Switch Configuration
Calibrations
For calibrations using the J-BERT N4903B and Switch Configuration use the connection diagram shown in Figure 34.
Figure 34: Connection Diagram for DP J-BERT N4903B and Switch Calibrations
Instructions:
•
Connect the J-BERT data output to the Artek CLE1000-A2 via blocking capacitors and 60 ps TTCs.
•
Connect the Artek CLE1000-A2 to the Switch according to the detailed Switch connections (Section 4.3).
•
Connect the J-BERT TRIGGER/REF CLK output to the 3-way power dividers (4-way if you selected them in the
Product Configuration) via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the Switch according to the detailed Switch connections.
•
Connect the Switch outputs to the DisplayPort Plug fixture.
•
Connect the lane under test from the DisplayPort Receptacle fixture to the oscilloscope according to the selected
way: with Differential Probe (connected to CH1) or directly with SMA connections (connected to CH1 and CH3).
•
Connect CH4 of the oscilloscope to the clock output CLK of the J-BERT. Connect a 50 Ω termination to the
negative clock output.
•
Connect 50 Ω terminations to the aggressor lanes of the DisplayPort Receptacle fixture.
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Sink Tests
For Sink Tests using the J-BERT N4903B and Switch Configuration use the connection diagram shown in Figure 35.
Figure 35: Connection Diagram for DP J-BERT N4903B and Switch Sink Tests
Instructions:
•
Connect the J-BERT data output to the Artek CLE1000-A2 via blocking capacitors and 60 ps TTCs.
•
Connect the Artek CLE1000-A2 to the Switch according to the detailed Switch connections in (Section 4.3).
•
Connect the J-BERT TRIGGER/REF CLK output to the 3-way power dividers (4-way if you selected them in the
Product Configuration) via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the Switch according to the detailed Switch connections.
•
Connect the Switch outputs to the DisplayPort Plug fixture.
•
Connect the AUX Controller to the DisplayPort Plug Fixture.
•
Connect the DisplayPort Plug fixture to the DUT.
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Zero-Length Tests
For Zero-Length Tests using the J-BERT N4903B and Switch Configuration use the connection diagram shown in Figure
36.
Figure 36: Connection Diagram for DP J-BERT N4903B and Switch Zero-Length Test
Instructions:
•
Connect the J-BERT data output to the Switch, according to the detailed Switch connections (Section 4.3), via
blocking capacitors and 60 ps TTCs.
•
Connect the J-BERT TRIGGER/REF CLK output to the 3-way power dividers (4-way if you selected them in the
Product Configuration) via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the Switch according to the detailed Switch connections.
•
Connect the Switch outputs to the DisplayPort Plug fixture.
•
Connect the AUX Controller to the DisplayPort Plug Fixture.
•
Connect the DisplayPort Plug fixture to the DUT.
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4.1.5 J-BERT M8020A and Switch Configuration
Calibrations
For calibrations using the J-BERT M8020A and Switch Configuration use the connection diagram shown in Figure 37.
Figure 37: Connection Diagram for DP J-BERT M8020A and Switch Calibrations
Instructions:
•
Connect the J-BERT data output to the Artek CLE1000-A2 via blocking capacitors and 60 ps TTCs.
•
Connect the Artek CLE1000-A2 to the Switch according to the detailed Switch connections(Section 4.3).
•
Connect the J-BERT TRIG output to the 3-way power dividers via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the Switch according to the Switch connections in detail.
•
Connect the Switch outputs to the DisplayPort Plug fixture.
•
Connect the lane under test from the DisplayPort Receptacle fixture to the oscilloscope according to the selected
way: with Differential Probe (connected to CH1) or directly with SMA connections (connected to CH1 and CH3).
•
Connect CH4 of the oscilloscope to the clock output CLK of the J-BERT. Connect a 50 Ω termination to the
negative clock output.
•
Connect 50 Ω terminations to the aggressor lanes of the DisplayPort Receptacle fixture.
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Sink Tests
For Sink Tests using the J-BERT M8020A and Switch Configuration use the connection diagram shown in Figure 38.
Figure 38: Connection Diagram for DP J-BERT M8020A and Switch Sink Tests
Instructions:
•
Connect the J-BERT data output to the Artek CLE1000-A2 via blocking capacitors and 60 ps TTCs.
•
Connect the Artek CLE1000-A2 to the Switch according to the detailed Switch connections(Section 4.3).
•
Connect the J-BERT TRIG output to the 3-way power dividers via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the Switch according to the detailed Switch connections.
•
Connect the Switch outputs to the DisplayPort Plug fixture.
•
Connect the AUX Controller to the DisplayPort Plug Fixture.
•
Connect the DisplayPort Plug fixture to the DUT.
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Zero-Length Tests
For Zero-Length Tests using the J-BERT M8020A and Switch Configuration use the connection diagram shown in Figure
39.
Figure 39: Connection Diagram for DP J-BERT M8020A and Switch Zero-Length Test
Instructions:
•
Connect the J-BERT data output to the Switch, according to the detailed Switch connections (Section 4.3), via
blocking capacitors and 60 ps TTCs.
•
Connect the J-BERT TRIG output to the 3-way power dividers via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the Switch according to the detailed Switch connections.
•
Connect the Switch outputs to the DisplayPort Plug fixture.
•
Connect the AUX Controller to the DisplayPort Plug Fixture.
•
Connect the DisplayPort Plug fixture to the DUT.
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4.2 Embedded DisplayPort (eDP) Connection Diagrams
4.2.1 J-BERT N4903B Configuration
Calibrations
For calibrations using the J-BERT N4903B Configuration use the connection diagram shown in Figure 40.
Figure 40: Connection Diagram for eDP J-BERT N4903B Calibrations
Instructions:
•
Connect the J-BERT data output to the lane under test of the DisplayPort Plug fixture via blocking capacitors and
60 ps TTCs
•
Connect the J-BERT TRIGGER/REF CLK output to the 3-way power dividers (4-way if you selected them in the
Product Configuration) via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the aggressor lanes of the DisplayPort plug fixture.
•
Connect the lane under test from the DisplayPort Receptacle fixture to the oscilloscope according to the selected
way: with Differential Probe (connected to CH1) or directly with SMA connections (connected to CH1 and CH3).
•
Connect CH4 of the oscilloscope to the clock output CLK of the J-BERT. Connect a 50 Ω termination to the
negative clock output.
•
Connect 50 Ω terminations to the aggressor lanes of the DisplayPort Receptacle fixture.
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Aggressor Amplitude Calibration
For Aggressor Amplitude Calibration using the J-BERT N4903B Configuration use the connection diagram shown in Figure
41.
Figure 41: Connection Diagram for eDP J-BERT N4903B Aggressor Amplitude Calibration
Instructions:
•
Connect the J-BERT data output to the lane under test of the DisplayPort Plug fixture via blocking capacitors and
60 ps TTCs.
•
Connect the J-BERT TRIGGER/REF CLK output to the 3-way power dividers (4-way if you selected them in the
Product Configuration) via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the aggressor lanes of the DisplayPort plug fixture.
•
Connect one of the aggressor lanes (any lane other than the lane under test) from the DisplayPort Receptacle
fixture to the oscilloscope according to the selected way: with Differential Probe (connected to CH1) or directly
with SMA connections (connected to CH1 and CH3).
•
Connect CH4 of the oscilloscope to the clock output CLK of the J-BERT. Connect a 50 Ω termination to the
negative clock output.
•
Connect 50 Ω terminations to the aggressor lanes of the DisplayPort Receptacle fixture.
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Sink Tests
For Sink Tests using the J-BERT N4903B Configuration use the connection diagram shown in Figure 42.
Figure 42: Connection Diagram for eDP J-BERT N4903B Sink Tests
Instructions:
•
Connect the J-BERT data output to the lane under test of the DisplayPort Plug fixture via blocking capacitors and
60 ps TTCs.
•
Connect the J-BERT TRIGGER/REF CLK output to the 3-way power dividers (4-way if you selected them in the
Product Configuration) via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the aggressor lanes of the DisplayPort plug fixture.
•
Connect the AUX Controller to the DisplayPort Plug Fixture.
•
Connect the DisplayPort Plug fixture to the DUT.
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4.2.2 J-BERT M8020A Configuration
Calibrations
For calibrations using the J-BERT M8020A Configuration use the connection diagram shown in Figure 43.
Figure 43: Connection Diagram for eDP J-BERT M8020A Calibrations
Instructions:
•
Connect the J-BERT data output to the lane under test of the DisplayPort Plug fixture via blocking capacitors and
60 ps TTCs.
•
Connect the J-BERT TRIG output to the 3-way power dividers via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the aggressor lanes of the DisplayPort plug fixture.
•
Connect the lane under test from the DisplayPort Receptacle fixture to the oscilloscope according to the selected
way: with Differential Probe (connected to CH1) or directly with SMA connections (connected to CH1 and CH3).
•
Connect CH4 of the oscilloscope to the clock output CLK of the J-BERT. Connect a 50 Ω termination to the
negative clock output.
•
Connect 50 Ω terminations to the aggressor lanes of the DisplayPort Receptacle fixture.
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Aggressor Amplitude Calibration
For Aggressor Amplitude Calibration using the J-BERT M8020A Configuration use the connection diagram shown in Figure
44.
Figure 44: Connection Diagram for eDP J-BERT M8020A Aggressor Amplitude Calibration
Instructions:
•
Connect the J-BERT data output to the lane under test of the DisplayPort Plug fixture via blocking capacitors and
60 ps TTCs.
•
Connect the J-BERT TRIG output to the 3-way power dividers via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the aggressor lanes of the DisplayPort plug fixture.
•
Connect one of the aggressor lanes (any lane other than the lane under test) from the DisplayPort Receptacle
fixture to the oscilloscope according to the selected way: with Differential Probe (connected to CH1) or directly
with SMA connections (connected to CH1 and CH3).
•
Connect CH4 of the oscilloscope to the clock output CLK of the J-BERT. Connect a 50 Ω termination to the
negative clock output.
•
Connect 50 Ω terminations to the aggressor lanes of the DisplayPort Receptacle fixture.
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Sink Tests
For Sink Tests using the J-BERT M8020A Configuration use the connection diagram shown in Figure 45.
Figure 45: Connection Diagram for eDP J-BERT M8020A Sink Tests
Instructions:
•
Connect the J-BERT data output to the lane under test of the DisplayPort Plug fixture via blocking capacitors and
60 ps TTCs.
•
Connect the J-BERT TRIG output to the 3-way power dividers via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the aggressor lanes of the DisplayPort plug fixture.
•
Connect the AUX Controller to the DisplayPort Plug Fixture.
•
Connect the DisplayPort Plug fixture to the DUT.
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4.2.3 J-BERT N4903B and Switch Configuration
Calibrations
For calibrations using the J-BERT N4903B and Switch Configuration use the connection diagram shown in Figure 46.
Figure 46: Connection Diagram for eDP J-BERT N4903B and Switch Calibrations
Instructions:
•
Connect the J-BERT data output to the Switch, according to the detailed Switch connections (Section 4.3), via
blocking capacitors and 60 ps TTCs.
•
Connect the J-BERT TRIGGER/REF CLK output to the 3-way power dividers (4-way if you selected them in the
Product Configuration) via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the Switch according to the detailed Switch connections.
•
Connect the Switch outputs to the DisplayPort Plug fixture.
•
Connect the lane under test from the DisplayPort Receptacle fixture to the oscilloscope according to the selected
way: with Differential Probe (connected to CH1) or directly with SMA connections (connected to CH1 and CH3).
•
Connect CH4 of the oscilloscope to the clock output CLK of the J-BERT. Connect a 50 Ω termination to the
negative clock output.
•
Connect 50 Ω terminations to the aggressor lanes of the DisplayPort Receptacle fixture.
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Sink Tests
For Sink Tests using the J-BERT N4903B and Switch Configuration use the connection diagram shown in Figure 47.
Figure 47: Connection Diagram for eDP J-BERT N4903B and Switch Sink Tests
Instructions:
•
Connect the J-BERT data output to the to the Switch, according to the detailed Switch connections (Section 4.3),
via blocking capacitors and 60 ps TTCs.
•
Connect the J-BERT TRIGGER/REF CLK output to the 3-way power dividers (4-way if you selected them in the
Product Configuration) via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the Switch according to the detailed Switch connections.
•
Connect the Switch outputs to the DisplayPort Plug fixture.
•
Connect the AUX Controller to the DisplayPort Plug Fixture.
•
Connect the DisplayPort Plug fixture to the DUT.
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4.2.4 J-BERT M8020A and Switch Configuration
Calibrations
For calibrations using the J-BERT M8020A and Switch Configuration use the connection diagram shown in Figure 48.
Figure 48: Connection Diagram for eDP J-BERT M8020A and Switch Calibrations
Instructions:
•
Connect the J-BERT data output to the Switch, according to the detailed Switch connections (Section 4.3), via
blocking capacitors and 60 ps TTCs.
•
Connect the J-BERT TRIG output to the 3-way power dividers via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the Switch according to the detailed Switch connections.
•
Connect the Switch outputs to the DisplayPort Plug fixture.
•
Connect the lane under test from the DisplayPort Receptacle fixture to the oscilloscope according to the selected
way: with Differential Probe (connected to CH1) or directly with SMA connections (connected to CH1 and CH3).
•
Connect CH4 of the oscilloscope to the clock output CLK of the J-BERT. Connect a 50 Ω termination to the
negative clock output.
•
Connect 50 Ω terminations to the aggressor lanes of the DisplayPort Receptacle fixture.
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Sink Tests
For Sink Tests using the J-BERT M8020A and Switch Configuration use the connection diagram shown in Figure 49.
Figure 49: Connection Diagram for eDP J-BERT M8020A and Switch Sink Tests
Instructions:
•
Connect the J-BERT data output to the Switch, according to the detailed Switch connections (Section 4.3), via
blocking capacitors and 60 ps TTCs.
•
Connect the J-BERT TRIG output to the 3-way power dividers via blocking capacitors and 150 ps TTCs.
•
Connect the power divider outputs to the Switch according to the detailed Switch connections.
•
Connect the Switch outputs to the DisplayPort Plug fixture.
•
Connect the AUX Controller to the DisplayPort Plug Fixture.
•
Connect the DisplayPort Plug fixture to the DUT.
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4.3 Switch Connections
When the switch is used, the connection diagram is shown in two images. The first image illustrates the complete setup,
and the switch is represented as a gray box (see Figures 34-39). Pressing the button “Show Switch Connection” will
change to the second image. This one shows just the switch matrix with its input and output connections in detail ( Figure
50). Pressing the button “Show General Connections” will return to the entire-setup diagram.
Figure 50: Connection Diagram for Switch Connections
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5 Sink Calibration Procedures
5.1 Calibration Overview
Before any sink test procedure can be run, the DisplayPort sink test system must be calibrated. The ValiFrame calibration
plane is given by the DUT input ports. The sink test signal characteristics such as the signal generator output voltage level
and jitter parameters are typically affected by the signal transmission between the generator output ports and the DUT
input ports. Thus, for any signal output parameter selected by the user (set value), the jitter and the signal received at the
DUT input ports (actual value) deviate from the set value. Additional deviations can be caused by effects such as offset
errors, hysteresis, and nonlinear behavior of the signal generator. The ValiFrame calibration procedures compensate the
deviations of the relevant signal output parameter actual values from the set values over the required parameter range. All
calibration procedures required for DisplayPort sink testing are included in the ValiFrame software. The ValiFrame
calibration procedures are implemented such that the calibration process is conducted as fast as possible and is
automated as much as possible, for example, by minimizing the number of reconfigurations of the hardware connections.
Depending on the DUT configuration, more or fewer calibrations will need to be conducted.
Table 7 presents a description of the procedure parameters used in the different calibrations.
Parameter Name
Parameter Description
Calibration
Oscilloscope Bandwidth
Bandwidth of the oscilloscope in use
Acquisition Time
The acquisition time for each captured data signal. Decreasing this value might speed up
the calibration but reduces accuracy
Measured ISI with
histogram
Uses histogram instead of EzJit+ oscilloscope software for ISI measurement
Memory Depth
Number of acquired points used by the scope to measure jitter
Measurement Cycles
Number of averaged measurements for each calibration step. Decreasing this value might
speed up the calibration but reduces accuracy
Skip Delay Auto
Calibration
Set to true to skip delay auto calibration of ParBERT.
Jitter
Use Explicit Clock
Jitter is measured with explicit clock, otherwise, with Constant Clock
ISI Amplitude
ISI amplitude applied
First Variable ISI Value
First Variable ISI value set to the Artek CLE1000-A2
Stop Jitter
The maximum calibrated random jitter (RJ) amplitude
Jitter Step Count
The number of jitter calibrated steps
SJ Frequency
Sinusoidal jitter (SJ) frequency used to apply the jitter values
Pattern
Sequence File
Specifies the name of the sequence file that should be used
Aggressor Clock Divider
The clock divider for the aggressor lane pattern
Pattern Period Length
Period length of the pattern; this information is required for jitter measurements. It should be
changed only when using a custom pattern.
Pattern Period Length
Auto Detect
Automatically determined period length of the pattern
Phase-Locked Loop (PLL)
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Loop Bandwidth
PLL Loop Bandwidth. The default value is scaled to 62.6% of the specified value, to
compensate for a slightly different PLL implementation in the oscilloscope
Damping Factor
PLL Damping Factor (Zeta)
Voltages
Differential Voltage
Amplitude value of the generator output
First Differential Voltage
First amplitude value of the output generator
Minimum Eye Opening
Lowest calibrated eye opening voltage
Applied Voltage Step
Differential voltage step size for the calibration. At every step, the output voltage is
decreased by this value.
Table 7: Sink Calibration Parameters
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5 Sink Calibration Procedures
5.2 DisplayPort Sink Calibrations
This section contains the set of calibrations required for the DP Sink test procedures.
Calibrations are organized in groups depending on the data rate:
•
RBR (Reduced Bit Rate)
•
HBR (High Bit Rate)
•
HBR2
5.2.1 Intersymbol Interference (ISI) Calibration
Purpose
This procedure is used to calibrate the ISI.
There is a separate calibration for each supported data rate.
Procedure
For this purpose, either the EzJit+ application or the Histogram on the real-time scope can be used. All jitter components
are disabled and the pattern is set according to the data bit rate. For RBR or HBR the pattern is PRBS7 and for HBR2 the
pattern is CP2520 (compliance pattern).
The ISI is measured and averaged over a number of cycles. If the ISI value is within the ±7.5% (for RBR –2.3%) tolerance
of the target value, the calibration will pass. If it is out of the mentioned range, the calibration will fail.
The Artek CLE1000-A2 can be used as the ISI Channel for all the pattern generators. In that case, the ISI calibration starts
by setting a variable ISI value (%) for the Artek CLE1000-A2 whose measured ISI value on the scope is lower than the
target ISI. Afterwards, the variable ISI value is increased until the measured ISI is higher than the target value. If the Artek
box is not used, the user has to adjust the ISI manually by some other method.
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) depending on your configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
•
•
Calibration
◦
Oscilloscope Bandwidth
◦
Acquisition Time (for RBR)
◦
Measured ISI with histogram (for HBR and HBR2)
◦
Measured Depth (for HBR and HBR2)
◦
Measurement Cycles
Jitter
◦
ISI Amplitude
◦
First Variable ISI Value
Pattern
◦
Sequence File
◦
Aggressor Clock Divider
◦
Pattern Period Length
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5 Sink Calibration Procedures
◦
•
•
Pattern Period Length Auto Detect
PLL
◦
Loop Bandwidth
◦
Damping Factor
Voltages
◦
Differential Voltage
These parameters are listed in Table 7.
Dependences
No calibration is required for this method.
Results
Two examples of HTML viewers for the ISI Calibration procedure are shown in Figures 51 and 52. The results comprise:
•
The common parameter list (in expert mode)
•
A calibration data table for the ISI that is being calibrated (see Tables 8 and 9)
Figure 51: Example of HTML Viewer for ISI Calibration
Parameter Name
Parameter Description
Result
Pass if the measured ISI is in range ±7.5% of the required value
Measured ISI
The averaged value of the ISI measurements
Table 8: Data Table for ISI Calibration
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5 Sink Calibration Procedures
Figure 52: Example HTML Viewer for ISI Calibration (with ISI Box)
Parameter Name
Parameter Description
Set Variable ISI Value (%) The ISI value set in the Artek CLE1000-A2
Measured ISI
The ISI value measured in the scope.
Table 9: Data Table for ISI Calibration (with ISI Box)
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5.2.2 Random Jitter Calibration
Purpose
This calibration calibrates the random jitter (RJ).
There is a separate calibration for each supported data rate.
Procedure
For this purpose the EzJit+ application running on the real-time scope is used. The test automation starts by applying
small RJ amplitudes and increases them. For every set RJ value, the corresponding amplitude is measured.
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) depending on your configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
•
•
•
Calibration
◦
Oscilloscope Bandwidth
◦
Measurement Cycles
Jitter
◦
Use Explicit Clock
◦
ISI Amplitude
◦
Stop Jitter
◦
Jitter Step Count
Pattern
◦
Sequence File
◦
Aggressor Clock Divider
◦
Pattern Period Length
◦
Pattern Period Length Auto Detect
Voltages
◦
Differential Voltage
These parameters are listed in Table 7.
Dependences
The calibration required for this method is:
•
ISI Calibration
Results
An example HTML viewer for the Random Jitter Calibration procedure is shown in Figure 53. The results comprise:
•
A calibration data graph
•
The common parameter list (in expert mode)
•
A calibration data table for the Random Jitter that is being calibrated (see Table 10)
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Figure 53: Example HTML Viewer for Random Jitter Calibration
Parameter Name
Parameter Description
Set Jitter
The applied random jitter value
Measured Jitter
The measured random jitter value
Table 10: Data Table for Random Jitter Calibration
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5.2.3 High Speed Sinusoidal Jitter Calibration
Purpose
This procedure is used to calibrate the sinusoidal jitter injected through the delay line of the ParBERT.
There is a separate calibration for each supported data rate.
Procedure
Different values of jitter amplitude are applied and measured at the real-time scope using the EzJit+ application.
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) depending on your configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
•
•
•
Calibration
◦
Oscilloscope Bandwidth
◦
Measurement Cycles
Jitter
◦
Use Explicit Clock
◦
ISI Amplitude
◦
Stop Jitter
◦
Jitter Step Count
Pattern
◦
Sequence File
◦
Aggressor Clock Divider
◦
Pattern Period Length
◦
Pattern Period Length Auto Detect
Voltages
◦
Differential Voltage
These parameters are listed in Table 7.
Dependences
The calibration required for this method is:
•
ISI Calibration
Results
An example HTML viewer for the High Speed Sinusoidal Jitter Calibration procedure is shown in Figure 54. The results
comprise:
•
A calibration data graph
•
The common parameter list (in expert mode)
•
A calibration data table for the Sinusoidal Jitter that is being calibrated (see Table 11)
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Figure 54: Example HTML Viewer for High Speed Sinusoidal Jitter Calibration
Parameter Name
Parameter Description
Set Jitter
The value of jitter set at the jitter generator instrument
Measured Jitter
The measured jitter amplitude
Table 11: Data Table for High Speed Sinusoidal Jitter Calibration
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5.2.4 Fixed Sinusoidal Jitter Calibration
Purpose
This calibration calibrates the fixed sinusoidal jitter (SJFIXED), which consists of sinusoidal jitter of 200 MHz frequency.
Only HBR2 contains a jitter component of 200 MHz, which is why this calibration is available only for this data rate.
Procedure
For this purpose the EzJit+ application running on the real-time scope is used. The test automation starts with small SJ
amplitudes and increases and measures them for each set amplitude.
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) depending on your configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
•
•
•
Calibration
◦
Oscilloscope Bandwidth
◦
Measurement Cycles
Jitter
◦
Use Explicit Clock
◦
ISI Amplitude
◦
Stop Jitter
◦
Jitter Step Count
Pattern
◦
Sequence File
◦
Aggressor Clock Divider
◦
Pattern Period Length
◦
Pattern Period Length Auto Detect
Voltages
◦
Differential Voltage
These parameters are listed in Table 7.
Dependences
The calibration required for this method is:
•
ISI Calibration
Results
An example HTML viewer for the Fixed Sinusoidal Jitter Calibration procedure is shown in Figure 55. The results
comprise:
•
A calibration data graph
•
The common parameter list (in expert mode)
•
A calibration data table for the Sinusoidal Jitter that is being calibrated (see Table 12)
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5 Sink Calibration Procedures
Figure 55: Example HTML Viewer for Fixed Sinusoidal Jitter Calibration
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5 Sink Calibration Procedures
Parameter Name
Parameter Description
Set Sinusoidal Jitter
The applied sinusoidal jitter amplitude fixed at 200MHz
Measured Jitter
Measured fixed jitter amplitude
Table 12: Data Table for Fixed Sinusoidal Jitter Calibration
5.2.5 Eye Opening Calibration
Purpose
This calibration calibrates the eye opening after the ISI emulator.
There is a separate calibration for each supported data rate.
Procedure
All the jitter impairments (RJ, ISI, SSC, SJ FIXED, and SJSWEEP) are applied to the data signal. Aggressor signals are not
considered for this calibration. The scope is configured to show the real-time eye.
For RBR and HBR, the test automation detects the crossing points of the eye by using a histogram measurement and
calculates the 50% crossing point (middle of the eye). At this location two histogram measurements are used to measure
the eye opening.
For HBR2, the test automation uses the location between 37.5% and 62.5% of the horizontal UI, where the eye opening is
maximum, for the measurement.
After that, the generator output voltage is decreased and the same measurement is repeated. This allows an amplitude
range to be calibrated. The eye opening is measured and averaged over a number of cycles.
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) depending on your configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
•
•
•
•
Calibration
◦
Oscilloscope Bandwidth
◦
Memory Depth
◦
Measurement Cycles
Jitter
◦
ISI Amplitude
◦
RJ Amplitude (RMS)
◦
SJ Frequency
Pattern
◦
Sequence File
◦
Aggressor Clock Divider
PLL
◦
Loop Bandwidth
◦
Damping Factor
Voltages
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◦
First Differential Voltage
◦
Minimum Eye Opening
◦
Applied Voltage Step
These parameters are listed in Table 7.
Dependences
The calibrations required for this method are:
•
ISI Calibration
•
RJ Jitter Calibration
•
High Speed Sinusoidal Jitter Calibration
•
Fixed Sinusoidal Jitter Calibration
Results
An example HTML viewer for the Eye Opening Calibration procedure is shown in Figure 56. The results comprise:
•
A calibration data graph
•
•
The common parameter list (in expert mode)
A calibration data table for the Eye that is being calibrated (see Table 13)
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5 Sink Calibration Procedures
Figure 56: Example HTML Viewer for Eye Opening Calibration
Parameter Name
Parameter Description
Set Voltage
The generator set output voltage
Measured Eye Opening
Measured eye opening with the scope
Table 13: Data Table for Eye Opening Calibration
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5.2.6 Aggressor Amplitude Calibration
Purpose
This calibration calibrates the differential output voltage of the aggressor signal.
There is a separate calibration for each supported data rate.
Procedure
The test automation starts by applying a high differential voltage and decreases it in each step. The corresponding
aggressor signal amplitude is measured on the scope.
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) depending on your configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
•
•
•
Calibration
◦
Oscilloscope Bandwidth
◦
Memory Depth
◦
Measurement Cycles
Pattern
◦
Sequence File
◦
Aggressor Clock Divider
PLL
◦
Loop Bandwidth
◦
Damping Factor
Voltages
◦
First Differential Voltage
◦
Minimum Eye Opening
◦
Applied Voltage Step
These parameters are listed in Table 7.
Dependences
No calibrations are required for this method.
Results
An example HTML viewer for the Aggressor Amplitude Calibration procedure is shown in Figure 57. The results comprise:
•
A calibration data graph
•
The common parameter list (in expert mode)
•
A calibration data table for the Aggressor Amplitude that is being calibrated (see Table 14)
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5 Sink Calibration Procedures
Figure 57: Example HTML Viewer for Aggressor Amplitude Amplitude Calibration
Parameter Name
Parameter Description
Set Voltage
Set Clock Generator output voltage
Measured Voltage
Measured aggressor signal voltage
Table 14: Data Table for Aggressor Amplitude Calibration
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5.2.7 Data Skew Calibration
Purpose
The data skew calibration is only available in expert mode when the ParBERT Configuration is used.
This calibration does not depend on the data rate.
Procedure
This procedure, first, runs the internal delay auto calibration of the ParBERT clock groups and, afterward, measures the
cable skews between the different generators of the multi-generator clock group.
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) in the ParBERT configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
•
Calibration
◦
Oscilloscope Bandwidth
◦
Skip Delay Auto Calibration
Pattern
◦
Sequence File
These parameters are listed in Table 7.
Dependences
No calibrations are required for this method.
Results
An example HTML viewer for the Generator Single-Ended Swing Calibration procedure is shown in Figure 58. The results
comprise:
•
•
The common parameter list (in expert mode)
A calibration data table for the Data Skew that is being calibrated (see Table 15)
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5 Sink Calibration Procedures
Figure 58: Example HTML Viewer for Data Skew Calibration
Parameter Name
Parameter Description
Result
Pass/Fail, according to whether the ParBERT was able to measure the delay
Module
Shows the name of the clock generator module that was calibrated
Skew Value
Skew value measured by the ParBERT
Table 15: Data Table for Data Skew Calibration
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5.3 Embedded DisplayPort Sink Calibrations
This section contains the set of calibrations required for the eDP Sink test procedures.
The calibrations are organized in groups depending on the data rate:
•
Reduced Bitrate (1.62 Gbps)
•
Rate_2 (2.16 Gbps)
•
Rate_3 (2.43 Gbps)
•
High Bitrate (2.7 Gbps)
•
Rate_5 (3.24 Gbps)
•
Rate_6 (4.32 Gbps)
•
High Bitrate 2 (5.4 Gbps)
5.3.1 ISI Calibration
Purpose
This procedure is used to calibrate the ISI.
There is a separate calibration for each supported data rate.
Procedure
For this purpose, either the EzJit+ application or the Histogram on the real-time scope can be used. All jitter components
are disabled and the HBR2 Compliance Pattern (CP2520) is set for every data rate.
There is no ISI generator, so the ISI value is just measured and averaged over a number of cycles. To get the ISI value,
DDJ(p-p) is measured with EzJit+ or the histograms are used to measure TJ.
This calibration will always pass because there is no target ISI value.
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) depending on your configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
•
•
Calibration
◦
Oscilloscope Bandwidth
◦
Measured ISI with histogram
◦
Measured Depth
◦
Measurement Cycles
Pattern
◦
Sequence File
◦
Aggressor Clock Divider
◦
Pattern Period Length
◦
Pattern Period Length Auto Detect
PLL
◦
Loop Bandwidth
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◦
•
Damping Factor
Voltages
◦
Differential Voltage
These parameters are listed in Table 7.
Dependences
No calibrations are required for this method.
Results
An example HTML viewer for the ISI Calibration procedure is shown in Figure 59. The results comprise:
•
The common parameter list (in expert mode)
•
A calibration data table for the ISI that is being calibrated (see Table 16)
Figure 59: Example of HTML Viewer for eDP ISI Calibration
Parameter Name
Parameter Description
Result
This calibration always passes.
Measured ISI
The averaged value of the ISI measurements.
Table 16: Data Table for eDP ISI Calibration
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5.3.2 Random Jitter Calibration
Purpose
This calibration calibrates the random jitter (RJ).
There is a separate calibration for each supported data rate.
Procedure
For this purpose the EzJit+ application running on the real-time scope is used. The test automation starts by applying
small RJ amplitudes and increases them. For every set RJ value, the corresponding amplitude is measured and averaged
over a number of cycles.
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) depending on your configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
•
•
•
Calibration
◦
Oscilloscope Bandwidth
◦
Measurement Cycles
Jitter
◦
Use Explicit Clock
◦
Stop Jitter
◦
Jitter Step Count
Pattern
◦
Sequence File
◦
Aggressor Clock Divider
◦
Pattern Period Length
◦
Pattern Period Length Auto Detect
Voltages
◦
Differential Voltage
These parameters are listed in Table 7.
Dependences
The calibrations required for this method is:
•
ISI Calibration
Results
An example HTML viewer for the Random Jitter Calibration procedure is shown in Figure 60. The results comprise:
•
A calibration data graph
•
The common parameter list (in expert mode)
•
A calibration data table for the Random Jitter that is being calibrated (see Table 17)
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Figure 60: Example HTML Viewer for eDP Random Jitter Calibration
Parameter Name
Parameter Description
Set Jitter
The applied random jitter value
Actual Jitter
The measured random jitter value
Table 17: Data Table for eDP Random Jitter Calibration
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5.3.3 Fixed Sinusoidal Jitter Calibration
Purpose
This calibration calibrates the fixed sinusoidal jitter (SJFIXED), which consists of sinusoidal jitter of 200 MHz frequency.
There is a separate calibration for each supported data rate.
Procedure
For this purpose the EzJit+ application running on the real-time scope is used. The test automation starts with small SJ
amplitudes and increases and measures them for each set amplitude. It is averaged over a number of cycles.
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) depending on your configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
•
•
•
Calibration
◦
Oscilloscope Bandwidth
◦
Measurement Cycles
Jitter
◦
Use Explicit Clock
◦
Stop Jitter
◦
Jitter Step Count
Pattern
◦
Sequence File
◦
Aggressor Clock Divider
◦
Pattern Period Length
◦
Pattern Period Length Auto Detect
Voltages
◦
Differential Voltage
These parameters are listed in Table 7.
Dependences
The calibration required for this method is:
•
ISI Calibration
Results
An example HTML viewer for the Fixed Sinusoidal Jitter Calibration procedure is shown in Figure 61. The results
comprise:
•
A calibration data graph
•
The common parameter list (in expert mode)
•
A calibration data table for the Sinusoidal Jitter that is being calibrated (see Table 18)
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Figure 61: Example HTML Viewer for eDP Fixed Sinusoidal Jitter Calibration
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Parameter Name
Parameter Description
Set Sinusoidal Jitter
The applied sinusoidal jitter amplitude fixed at 200 MHz
Measured Jitter
Measured fixed jitter amplitude
Table 18: Data Table for eDP Fixed Sinusoidal Jitter Calibration
5.3.4 Eye Opening Calibration
Purpose
This calibration calibrates the eye opening at TP3_EQ.
There is a separate calibration for each supported data rate.
Procedure
It starts with large amplitude and all the jitter impairments (RJ, SSC, SJ FIXED, and SJSWEEP) are applied to the data signal.
Aggressor signals are not considered for this calibration. The scope is configured to show the real-time eye.
The test automation uses the location between 37.5% and 62.5% of the horizontal UI, where the eye opening is maximum,
for measurement.
After that, the generator output voltage is decreased and the same measurement is repeated. This allows an amplitude
range to be calibrated. The eye opening is measured and averaged over a number of cycles.
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) depending on your configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
•
•
•
•
Calibration
◦
Oscilloscope Bandwidth
◦
Memory Depth
◦
Measurement Cycles
Jitter
◦
RJ Amplitude (RMS)
◦
Fixed SJ Amplitude
◦
Fixed SJ Frequency
◦
SJ Frequency
Pattern
◦
Sequence File
◦
Aggressor Clock Divider
PLL
◦
Loop Bandwidth
◦
Damping Factor
Voltages
◦
First Differential Voltage
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◦
Minimum Eye Opening
◦
Applied Voltage Step
These parameters are listed in Table 7.
Dependences
The calibrations required for this method are:
•
ISI Calibration
•
RJ Jitter Calibration
•
High Speed Sinusoidal Jitter Calibration
•
Fixed Sinusoidal Jitter Calibration
Results
An example HTML viewer for the Eye Opening Calibration procedure is shown in Figure 62. The results comprise:
•
A calibration data graph
•
The common parameter list (in expert mode)
•
A calibration data table for the Eye that is being calibrated (see Table 19)
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Figure 62: Example HTML Viewer for eDP Eye Opening Calibration
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Parameter Name
Parameter Description
Set Voltage
The generator set output voltage
Measured Voltage
Measured eye opening with the scope
Table 19: Data Table for eDP Eye Opening Calibration
5.3.5 Aggressor Amplitude Calibration
Purpose
This calibration calibrates the differential output voltage of the aggressor signal.
There is a separate calibration for each supported data rate.
Procedure
The test automation starts by applying a high differential voltage and decreases it in each step. The corresponding
aggressor signal amplitude is measured on the scope.
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) depending on your configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
•
•
Calibration
◦
Oscilloscope Bandwidth
◦
Memory Depth
◦
Measurement Cycles
Pattern
◦
Sequence File
◦
Aggressor Clock Divider
Voltages
◦
First Differential Voltage
◦
Minimum Eye Opening
◦
Applied Voltage Step
These parameters are listed in Table 7.
Dependences
No calibrations are required for this method.
Results
An example HTML viewer for the Aggressor Amplitude Calibration procedure is shown in Figure 63. The results comprise:
•
A calibration data graph
•
The common parameter list (in expert mode)
•
A calibration data table for the Aggressor Amplitude that is being calibrated (see Table 20)
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Figure 63: Example HTML Viewer for eDP Aggressor Amplitude Amplitude Calibration
Parameter Name
Parameter Description
Set Voltage
Set Clock Generator output voltage
Measured Voltage
Measured aggressor signal voltage
Table 20: Data Table for eDP Aggressor Amplitude Calibration
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6 Sink Test Procedures
The basic approach is always the same:
1.
Archive frequency lock
2.
Archive symbol lock
3.
Configure the DUT for error counting
4.
Verify the error counting
5.
Run the BER test
Before starting the Sink Tests, it is recommended that you press the button "Query DUT Capabilities" in the Advanced
Product Configuration. Then the AUX Controller will communicate with the DUT, and the DUT capabilities will be displayed.
This is a good way to ensure that there is communication between them before you start running the tests.
Table 21 presents a description of the procedure parameters used in the different Sink Rx Tests.
Parameter Name
Parameter Description
Bit Error Rate Testing
Link Quality Pattern Hint
Represents the link quality pattern that is written to the DPCD register according to the
spec. Make sure that this value is in sync with the Sequence File property.
Observation Time
The time in seconds during which the PRBS pattern is sent out.
Allowed Number of Errors
Maximum allowed number of errors in order to pass the test.
Intra-Pair Skew
SJ Frequency
Sinusoidal jitter frequency injected during the test.
SJ Amplitude
Sinusoidal jitter amplitude injected during the test.
Bitrate
Maximum Frequency
Deviation
The maximum data rate deviation used for the test.
Deviation Step Size
Step size applied to the data rate
DPCD
Extra DPCD
Additional data written to the DPCD registers (format: “<register>=<value>, …” where
<register> and <value> are hexadecimal, e.g., “0909=01, 090A=FF”)
Extra DPCD Order
Defines at which point the extra DPCD (if any) is written to the DPCD registers.
Jitter
ISI Amplitude
ISI amplitude applied during the test.
RJ Amplitude (RMS)
The RJ amplitude injected during the test.
Fixed SJ Amplitude(pk-pk)
Fixed peak–peak SJ Amplitude injected during the test.
Fixed SJ Frequency
Fixed SJ Frequency used for the test. It is read-only.
Pattern
Sequence File
The name of the sequence file that is used for testing. Make sure this property is in sync
with the Link Quality Pattern Hint.
Aggressor Clock Divider
The clock divider for the aggressor lane pattern.
SSC (Spread Spectrum Clocking)
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Parameter Name
Parameter Description
SSC Frequency
The frequency of the SSC modulation.
SSC Amplitude
The amplitude of the SSC modulation.
Use SSC
SSC is applied for testing with the specified frequency and amplitude.
Swept SJ Amplitude
Swept SJ Amplitude Step
Size
If you are running the test in binary search mode, this is the precision for the binary
search mode to stop, if not, this is the step size of the jitter amplitude.
Minimum Swept SJ
Amplitude
Starting value of the SJ for each frequency.
Maximum Swept SJ
amplitude
Maximum SJ amplitude that is tested provided the device does not fail earlier and the
instrument can generate this amplitude.
Use Binary Search
Search in binary search mode to find the failing amplitude point for each SJ frequency or
use linear steps.
Swept SJ Frequency
Start Frequency
The lowest SJ frequency that should be tested.
Stop Frequency
The highest SJ frequency that should be tested.
Number of Frequency
Steps
The number of different frequencies that should be tested in the specified range.
Use Linear Frequency
Steps
Set to true to use linear frequency steps or false to use logarithmic steps.
Use Frequency Points
Use frequency points instead of the list generated by the start and stop values.
Frequency Points
Frequency values to use if the previous option is selected.
Voltages
Tested Lane Voltage
Calibrated eye opening used during the test.
Aggressor Lane Voltage
Calibrated aggressor signal differential voltage used during the test.
Start Differential Amplitude
First amplitude value of the output generator.
Differential Amplitude Step
Size
Differential voltage step size for the test. At every step, the output voltage is decreased by
this value.
Use Eye Opening
Calibration
The amplitude is set according to the eye height calibration table.
Table 21: Sink Rx Tests Parameters
6.1 DisplayPort Sink Tests
The Sink Tests for DisplayPort are implemented according to the DisplayPort 1.2b CTS in the section “Sink Compliance
Test”.
The Sink test groups are divided by lane (1–4) and subdivided by supported data rate (RBR, HBR, and HBR2) and SJ
Frequency (2, 10, 20 and 100 MHz). There are three types of tests:
•
Jitter Tolerance Test
•
Zero-Length Test
•
Expert Mode Test
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6.1.1 Jitter Tolerance Test
Purpose
This test procedure is described in the DisplayPort 1.2b compliance test specification. It generates a stressed eye and
verifies that the receiver sustains a BER of 10e–9.
Procedure
The test automation sets up the instrument with the calibrated amplitudes and jitter values required by the specification.
First, it runs the link training, which is done in two steps: frequency and symbol lock phase. Afterward, the data pattern is
applied (PRBS7 for RBR and HBR or CP2520 for HBR2) and the error counter started. A count-down timer is displayed
and, when it is finished, the result of the test will be decided depending on the number of errors.
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) depending on your configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
•
•
•
•
•
Bit Error Rate Testing
◦
Link Quality Pattern Hint
◦
Allowed Number of Errors
◦
Observation Time
DPCD
◦
Extra DPCD
◦
Extra DPCD Order
Jitter
◦
ISI Amplitude
◦
RJ Amplitude (RMS)
◦
Fixed SJ Amplitude (pk-pk)
◦
Fixed SJ Frequency
Pattern
◦
Sequence File
◦
Aggressor Clock Divider
SSC
◦
Use SSC
◦
SSC Frequency
◦
SSC Amplitude
Voltage Levels
◦
Tested lane voltage
◦
Aggressor Lane Voltage
These parameters are listed in Table 21.
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Dependences
The calibrations required for this method are:
•
ISI Calibration
•
RJ Jitter Calibration
•
High Speed Sinusoidal Jitter Calibration
•
Fixed Sinusoidal Jitter Calibration
•
Eye Opening Calibration
•
Aggressor Amplitude Calibration
Results
An example HTML viewer for the Jitter Tolerance Test procedure is shown in Figure 64. The results comprise:
•
The common parameter list (in expert mode)
•
A data table for the Result (see Table 22)
Figure 64: Example HTML Viewer for Jitter Tolerance Test
Parameter Name
Parameter Description
Result
Pass/Fail, pass means this test succeeded
Jitter Frequency
The frequency of the sinusoidal jitter injected during the test
Sinusoidal Jitter Amplitude
The amplitude of the sinusoidal jitter injected during the test
Number of Errors
The number of errors counted during the test
Min Spec
The minimum allowed number of errors
Max Spec
The maximum allowed number of errors
Details
Description of the possible problems found during the test
Table 22: Data Table for Jitter Tolerance Test
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6.1.2 Jitter Tolerance Test Zero-Length Cable
Purpose
This test procedure is described in the DisplayPort 1.2b compliance test specification. It generates a stressed eye and
verifies that the receiver sustains a BER of 10e–9.
Procedure
This test follows the same procedure as explained in the Jitter Tolerance Test (Section 6.1.1) but without ISI channel and
only for the data rates HBR and HBR2.
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) depending on your configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
•
•
•
•
•
Bit Error Rate Testing
◦
Link Quality Pattern Hint
◦
Allowed Number of Errors
◦
Observation Time
DPCD
◦
Extra DPCD
◦
Extra DPCD Order
Jitter
◦
ISI Amplitude
◦
RJ Amplitude (RMS)
◦
Fixed SJ Amplitude (pk-pk)
◦
Fixed SJ Frequency
Pattern
◦
Sequence File
◦
Aggressor Clock Divider
SSC
◦
Use SSC
◦
SSC Frequency
◦
SSC Amplitude
Voltage Levels
◦
Tested lane voltage
◦
Aggressor Lane Voltage
These parameters are listed in Table 21.
Dependences
The calibrations required for this method are:
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•
ISI Calibration
•
RJ Jitter Calibration
•
High Speed Sinusoidal Jitter Calibration
•
Fixed Sinusoidal Jitter Calibration
•
Eye Opening Calibration
•
Aggressor Amplitude Calibration
Results
An example HTML viewer for the Jitter Tolerance Test procedure is shown in Figure 65. The results comprise:
•
•
The common parameter list (in expert mode)
A data table for the Result (see Table 23)
Figure 65: Example HTML Viewer for Jitter Tolerance Test (Zero-Length)
Parameter Name
Parameter Description
Result
Pass/Fail, pass means this test succeeded
Jitter Frequency
The frequency of the sinusoidal jitter injected during the test
Sinusoidal Jitter Amplitude
The amplitude of the sinusoidal jitter injected during the test
Number of Errors
The number of errors counted during the test
Min Spec
The minimum allowed number of errors
Max Spec
The maximum allowed number of errors
Details
Description of the possible problems found during the test
Table 23: Data Table for Jitter Tolerance Test (Zero-Length)
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6.1.3 Jitter Tolerance Characterization Test
Purpose
This procedure tests the jitter tolerance of a device for different sinusoidal jitter frequencies.
Procedure
For each sinusoidal jitter frequency, this procedure tries to find the amplitude at which the target BER can be sustained. It
starts by setting the maximum jitter amplitude. Then the value is decreased using either a binary or linear search
algorithm. The range of jitter frequencies to be tested can be defined in the “Swept SJ frequency” parameters section.
The result is a curve that shows the maximum jitter that the DUT can tolerate as a function of the SJ frequency.
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) depending on your configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
•
•
•
•
•
•
Bit Error Rate Testing
◦
Link Quality Pattern Hint
◦
Allowed Number of Errors
◦
Observation Time
DPCD
◦
Extra DPCD
◦
Extra DPCD Order
Jitter
◦
ISI Amplitude
◦
RJ Amplitude (RMS)
Pattern
◦
Sequence File
◦
Aggressor Clock Dividers
SSC
◦
SSC Frequency
◦
SSC Amplitude
◦
Use SSC
Swept SJ Amplitude
◦
Swept SJ Amplitude Step
◦
Minimum Swept SJ Amplitude
◦
Maximum Swept SJ Amplitude
◦
Use Binary Search
Swept SJ Frequency
◦
Start Frequency
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•
◦
Stop Frequency
◦
Number of Frequency Steps
◦
User Linear Frequency Steps
◦
User Frequency Points
◦
Frequency Points
Voltage Levels
◦
Tested lane voltage
◦
Aggressor Lane Voltage
These parameters are listed in Table 21.
Dependences
The calibrations required for this method are:
•
ISI Calibration
•
RJ Jitter Calibration
•
Fixed Sinusoidal Jitter Calibration
•
Eye Opening Calibration
•
Aggressor Amplitude Calibration
Results
An example HTML viewer for the Jitter Characterization Test procedure is shown in Figure 66. The results comprise:
•
A test data graph
•
The common parameter list (in expert mode)
•
A data table for the Result (see Table 24)
Parameter Name
Parameter Description
Result
Pass/Fail, pass means this test was completed for this SJ
Sinusoidal Jitter Frequency
Shows the frequency of the Sinusoidal Jitter used for this point
Max Passed SJ
Maximum SJ amplitude where the device passed the test
Min Spec
Minimum SJ amplitude for this frequency specified in the CTS
Generator Limit Reached
Determines whether the test for this frequency was stopped owing to instrument
limitation or to the device failing this amplitude
Table 24: Data Table for Jitter Characterization Test
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Figure 66: Example HTML Viewer for Jitter Characterization Test
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6.1.4 Data Rate Deviation Test
Purpose
This test defines the data rate limits where the device can still work.
Procedure
This procedure adjusts the data rate until the target BER specified in DP1.2b CTS cannot be sustained by the DUT. First, it
increases the original data rate value by a deviation step size (by default 1 ppm), until it reaches the maximum deviation
value. Afterward, it repeats the same procedure but decreases the original data rate by the deviation step size.
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) depending on your configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
•
•
•
•
•
Bit Error Rate Testing
◦
Link Quality Pattern Hint
◦
Allowed Number of Errors
◦
Observation Time
Bitrate
◦
Maximum Frequency Deviation
◦
Deviation Step Size
DPCD
◦
Extra DPCD
◦
Extra DPCD Order
Pattern
◦
Sequence File
◦
Aggressor Clock Dividers
SSC
◦
SSC Frequency
◦
SSC Amplitude
◦
Use SSC
Voltage Levels
◦
Tested lane voltage
◦
Aggressor Lane Voltage
These parameters are listed in Table 21.
Dependences
The calibration required for this method is:
•
Eye Opening Calibration
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Results
An example HTML Viewer for the Datarate Deviation Test is shown in Figure 67. The results comprise:
•
The common parameter list (in expert mode)
•
A data table for the Result (see Table 25)
Figure 67: Example HTML Viewer for Datarate Deviation Test
Parameter Name
Parameter Description
Result
Pass/Fail, pass means the deviation is within the spec limits
Test Point
Datarate with positive or negative deviation
Max passed Datarate Deviation
This is the maximum datarate deviation allowed to pass the test
Details
Detailed comments if the test fails
Table 25: Data Table for Datarate Deviation Test
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6.1.5 Intra-Pair Skew Test
Purpose
This procedure tests intra-pair skew tolerance of the device.
Procedure
This test increases the skew between normal and complement of the tested lane and tries to run the training sequence as
well as sustain the specified BER. The skew is increased until the test fails or 1 UI skew is reached. After that, the skew is
tested in the opposite direction.
This procedure is an expert mode test and only for the ParBERT configuration.
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) depending on your configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
•
•
Intra-Pair Skew
◦
SJ Frequency
◦
SJ Amplitude
Bit Error Rate Testing
◦
Sequence File
◦
Link Quality Pattern Hint
SSC
◦
SSC Frequency
◦
SSC Amplitude
◦
Use SSC
These parameters are listed in Table 21.
Dependences
The calibration required for this method is:
•
Data Skew Calibration
Results
An example HTML Viewer for the Intra-Pair Skew Test procedure is shown in Figure 68. The results comprise:
•
The common parameter list (in expert mode)
•
A data table for the Result (see Table 26)
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Figure 68: Example HTML Viewer for Intra-Pair Skew Test
Parameter Name
Parameter Description
Result
Pass/Fail, pass means the skew is within the spec limits
Max Passed Skew
Maximum skew value at which the device passes the test
Min Passed Skew
Minimum skew value at which the device passes the test
Table 26: Data Table for Intra-Pair Skew Test
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6.1.6 Sensitivity Test
Purpose
This test characterizes that the DUT can still work with the minimum differential voltage.
Procedure
The procedures starts at the maximum output voltage and does the Link Training. If the device passes, the generator
output is decreased and tested again. This is repeated until the device fails because the bits are not detected properly
anymore owing to the low voltage level applied.
The table also shows the eye opening corresponding to the set amplitude. This value is taken from the Eye Height
Calibration.
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) depending on your configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
•
•
•
•
Bit Error Rate Testing
◦
Link Quality Pattern Hint
◦
Allowed Number of Errors
◦
Observation Time
DPCD
◦
Extra DPCD
◦
Extra DPCD Order
Pattern
◦
Sequence File
◦
Aggressor Clock Dividers
SSC
◦
SSC Frequency
◦
SSC Amplitude
◦
Use SSC
Voltage Levels
◦
Start Differential Amplitude
◦
Differential Amplitude Step Size
◦
Use Eye Opening Calibration
These parameters are listed in Table 21.
Dependences
The calibration required for this method is:
•
Eye Opening Calibration
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Results
An example HTML Viewer for the Sensitivity Test procedure is shown in Figure 69. The results comprise:
•
A test data graph
•
The common parameter list (in expert mode)
•
A data table for the Result (see Table 27)
Figure 69: Example HTML Viewer for Sensitivity Test
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Parameter Name
Parameter Description
Result
Pass/Fail, pass means the voltage is within the spec limits
Generator Output
The applied generator output voltage
Eye Opening
The eye opening corresponding to the applied voltage
Table 27: Data Table for Sensitivity Test
6.1.7 Variable Parameter Test
Purpose
This test lets you select a wide variety of combinations for all relevant parameters, such as jitter frequencies and
amplitudes as well as voltage levels, to test your device against.
Procedure
First, the combination of parameters can be selected in the Variable Parameter Test window (see Figure 70). Then the
BER error test is executed by pressing the “Test Sink and Add Entry” button. The test can be performed as many times as
desired with different selections of parameters. Finally, when the button “Finish Test” is pressed the results are saved in an
Excel file.
Figure 70: Variable Parameter Test Window
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) depending on your configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
Bit Error Rate Testing
◦
Sequence File
◦
Link Quality Pattern Hint
These parameters are listed in Table 21.
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Dependences
The calibrations required for this method are:
•
ISI Calibration
•
RJ Jitter Calibration
•
High Speed Sinusoidal Jitter Calibration
•
Fixed Sinusoidal Jitter Calibration
•
Eye Opening Calibration
•
Aggressor Amplitude
Results
An example HTML Viewer for the Variable Parameter Test procedure is shown in Figure 71. The results comprise:
•
The common parameter list (in expert mode)
•
A data table for the Result (see Table 28)
Figure 71: Example HTML Viewer for Variable Parameter Test
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Parameter Name
Parameter Description
Result
Pass/Fail, pass means the BER test was passed
Data Amplitude
The generator output level
Aggressor Lanes Amplitude
The aggressor signal level
RJ Amplitude
The RMS amplitude of the random jitter
Bitrate
The bit rate used during the test
1st Jitter Comp. Amplitude
The amplitude of the first SJ component
1st Jitter Comp. Frequency
The frequency of the first SJ component
2nd Jitter Comp. Amplitude
The amplitude of the second SJ component
2nd Jitter Comp. Frequency
The frequency of the second SJ component
SSC Frequency
The frequency of the SSC modulation
SSC Amplitude
The amplitude of the SSC modulation
Observation Time
The observation time of the error counter
Error Counter Limit
The limit of the error counter
Error Counter
The number of errors found after the observation time has elapsed
Table 28: Data Table for Variable Parameters Test
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6.2 Embedded DisplayPort Sink Tests
The Sink Tests for Embedded DisplayPort are implement according to the eDP 1.4 CTS.
The Sink test groups are divided by lane (1–4), and subdivided by supported data rate (Reduced Bitrate, Rate_2, Rate_3,
High Bitrate, Rate_5, Rate_6, High Bitrate 2) and SJ Frequency (2.1, 9, 18 and 90 MHz).
6.2.1 Jitter Tolerance Test
Purpose
This test procedure is described in the eDP 1.4 compliance test specification. It generates a stressed eye and verifies that
the receiver sustains a BER of 10e–9.
Procedure
The test automation sets up the instrument with the calibrated amplitudes and jitter values required by the specification.
First, it runs the link training, which is done in two steps: frequency and symbol lock phase. Afterward, the data pattern is
applied (CP2520) and the error counter started. A count-down timer is displayed and, when it is finished, the result of the
test will be decided depending on the number of errors.
Connection Diagram
Follow the pictures of the Connection Diagrams Section (Chapter 4) depending on your configuration.
Parameters
The parameters used in expert mode for this calibration are:
•
•
•
•
•
Bit Error Rate Testing
◦
Link Quality Pattern Hint
◦
Allowed Number of Errors
◦
Observation Time
DPCD
◦
Extra DPCD
◦
Extra DPCD Order
Jitter
◦
RJ Amplitude (RMS)
◦
Fixed SJ Amplitude (pk–pk)
◦
Fixed SJ Frequency
◦
SJ via Clock Jitter
Pattern
◦
Sequence File
◦
Aggressor Clock Divider
SSC
◦
Use SSC
◦
SSC Frequency
◦
SSC Amplitude
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6 Sink Test Procedures
•
Voltage Levels
◦
Tested lane voltage
◦
Aggressor Lane Voltage
These parameters are listed in Table 26.
Dependences
The calibrations required for this method are:
•
ISI Calibration
•
RJ Jitter Calibration
•
Fixed Sinusoidal Jitter Calibration
•
Eye Opening Calibration
•
Aggressor Amplitude Calibration
Results
An example HTML viewer for the Jitter Tolerance Test procedure is shown in Figure 72. The results comprise:
•
The common parameter list (in expert mode)
•
A data table for the Result (see Table 29)
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6 Sink Test Procedures
Figure 72: Example HTML Viewer for eDP Jitter Tolerance Test
Parameter Name
Parameter Description
Result
Pass/Fail, pass means this test was passed
Jitter Frequency
The frequency of the sinusoidal jitter injected during the test
Sinusoidal Jitter Amplitude
The amplitude of the sinusoidal jitter injected during the test
Number of Errors
The number of errors counted during the test
Min Spec
The minimum allowed number of errors
Max Spec
The maximum allowed number of errors
Details
Description of the possible problems found during the test
Table 29: Data Table for eDP Jitter Tolerance Test
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7 Source Test Procedures
7 Source Test Procedures
DisplayPort source compliance testing consists in measuring the DisplayPort signal generated by the DUT. The signal
analysis is conducted by the Keysight (or Agilent) oscilloscope application. ValiFrame remote-controls the scope
application and shows the connection diagrams as well as the result in a coalesced report.
There are Physical and Link Layer tests. The Source PHY tests are divided into four groups depending on the used pattern
(PRBS7, D10.2, HBR2CPAT, PLTPAT). See Figure 73:
Figure 73: Source Test List
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