TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES 2M x 8 SRAM MODULE SYS82000FKX - 70/85/10/12 Elm Road, West Chirton Industrial Estate, North Shields, NE29 8SE, ENGLAND. TEL +44 (0191) 2930500. FAX +44 (0191) 2590997 Issue 2.5 : February 2000 Description Features The SYS82000FKX is a plastic 16Mbit Static RAM Module housed in a JEDEC standard 36 pin Dual In-Line package organised as 2Mx8. The module utilises 512Kx8 SRAM's housed in TSOPII packages, and uses double sided surface mount techniques, buried decoder and dual board construction to achieve a very high density module, emulating the 16Mbit monolithic pinout. Access times of 70 to 120 ns are available. The OE pin allows faster access times than address access during a read cycle. Block Diagram • • • • Access Times of 70/85/100/120 ns. 36 Pin JEDEC standard Dual-In-Line package. 5 Volt Supply ± 10%. Center Power and Ground Pinout. Low Power Dissipation: Average (min cycle) 600mW (max). Standby 26.4mW (max). Low Voltage VCC Data Retention. Equal Access and Cycle Times. Directly TTL Compatible. On-board Supply Decoupling Capacitors. Pin Definition A0 - A18 D0 - D7 WE OE 512K X 8 512K X 8 512K X 8 512K X 8 SRAM SRAM SRAM SRAM CS CS CS CS CS A19 A20 • • • • • DECODER Pin Functions Address Inputs Data Input/Output Chip Select Write Enable Output Enable Power (+5V) Ground A0 - A20 D0 - D7 CS WE OE VCC GND A0 A1 A2 A3 A4 CS D0 D1 Vcc GND D2 D3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 TOP VIEW 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 A20 A19 A18 A17 A16 OE D7 D6 GND Vcc D5 D4 A15 A14 A13 A12 A11 A10 Package Details Plastic 36 Pin 0.6" Dual-In-Line low profile Package.(DIP) SYS82000FKX - 70/85/10/12 Issue 2.5 : February 2000 DC OPERATING CONDITIONS Absolute Maximum Ratings (1) Parameter Symbol (2) T Voltage on any pin relative to VSS Power Dissipation Storage Temperature V PT TSTG Min Typ Max Unit -0.3 -55 1.0 - 7.0 125 V W o C Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (2) VT can be -3.0V pulse of less than 30ns. Recommended Operating Conditions Parameter Supply Voltage Input High Voltage Input Low Voltage Operating Temperature (Commercial) (Industrial) DC Electrical Characteristics Parameter I/P Leakage Current Symbol Min Typ Max Unit VCC VIH VIL TA TAI 4.5 2.2 -0.3 0 -40 5.0 - 5.5 Vcc+0.3 0.8 70 85 V V V o C o C TA 0 to 70 oC (VCC=5V±10%) Symbol Test Condition Min Typ max Unit ILI 0V < VIN < VCC -5 - 5 µA Output Leakage Current ILO CS = VIH, VI/O = GND to VCC , OE=VIH -5 - 5 µA Operating Supply Current ICC1 Min. Cycle, CS = VIL,VIL<VIN<VIH - - 109 mA TTL levels ISB1 CS = VIH - - 12 mA CMOS levels ISB2 CS > VCC-0.2V, 0.2<VIN<VCC-0.2V - - 480 µA -L Version (CMOS) ISB3 CS > VCC-0.2V, 0.2<VIN<VCC-0.2V - - 280 µA VOL IOL = 2.1mA - - 0.4 V VOH IOH = -1.0mA 2.4 - - V Address,OE,WE Standby Supply Current Output Voltage Typical values are at VCC=5.0V,TA=25oC and specified loading. Capacitance (VCC=5V±10%,TA=25oC) Parameter Input Capacitance (Address,OE,WE) I/P Capacitance (other) I/O Capacitance Note: Capacitance calculated, not measured. Symbol Test Condition CIN1 CIN2 CI/O VIN = 0V VIN = 0V VI/O = 0V 2 max Unit 38 10 32 pF pF pF SYS82000FKX - 70/85/10/12 Issue 2.5 : February 2000 AC Test Conditions Output Load * Input pulse levels: 0V to 3.0V I/O Pin 645Ω * Input rise and fall times: 5ns 1.76V * Input and Output timing reference levels: 1.5V 100pF * Output load: see diagram * VCC=5V±10% Operation Truth Table CS OE WE DATA PINS SUPPLY CURRENT MODE H X X High Impedance ISB1 , ISB2 , ISB3 Standby L L H Data Out ICC1 Read L H L Data In ICC1 Write L L L Data In ICC1 Write L H H High-Impedance ISB1 , ISB2 , ISB3 High-Z Notes : H = VIH : L =VIL : X = VIH or VIL Low Vcc Data Retention Characteristics - L Version Only Parameter VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Notes Symbol VDR ICCDR1 tCDR tR Test Condition min CS > VCC-0.2V 2.0 2.0 < Vcc < 5.5V,CS>Vcc-0.2 See Retention Waveform 0 See Retention Waveform 5 (1) Typical figures are measured at 25°C. (2) This parameter is guaranteed not tested. 3 typ(1) max Unit - 280 - V µA ns ms SYS82000FKX - 70/85/10/12 Issue 2.5 : February 2000 AC OPERATING CONDITIONS Read Cycle -70 Parameter -85 -10 -12 Symbol min max min max min max min max Unit Read Cycle Time tRC 70 - 85 - 100 - 120 - ns Address Access Time tAA - 70 - 85 - 100 - 120 ns Chip Select Access Time tACS - 70 - 85 - 100 - 120 ns Output Enable to Output Valid tOE - 40 - 45 - 50 - 55 ns Output Hold from Address Change tOH 10 - 10 - 10 - 10 - ns Chip Selection to Output in Low Z tCLZ 10 - 10 - 10 - 10 - ns Output Enable to Output in Low Z tOLZ 5 - 5 - 5 - 5 - ns Chip Deselection to O/P in High Z tCHZ 0 25 0 30 0 35 0 40 ns Output Disable to Output in High Z tOHZ 0 25 0 30 0 35 0 40 ns Write Cycle -70 Parameter -85 -10 -12 Symbol min max min max min max min Write Cycle Time tWC 70 - 85 - 100 - 120 - ns Chip Selection to End of Write tCW 60 - 70 - 80 - 100 - ns Address Valid to End of Write tAW 60 - 70 - 85 - 100 - ns Address Setup Time tAS 0 - 0 - 0 - 0 - ns Write Pulse Width tWP 50 - 60 - 70 - 80 - ns Write Recovery Time tWR 5 - 5 - 5 - 5 - ns Write to Output in High Z tWHZ 0 25 0 30 0 35 0 40 ns Data to Write Time Overlap tDW 30 - 35 - 40 - 45 - ns Data Hold from Write Time tDH 0 - 0 - 0 - 0 - ns Output active from End of Write tOW 5 - 5 - 5 - 5 - ns 4 max Unit SYS82000FKX - 70/85/10/12 Issue 2.5 : February 2000 Read Cycle Timing Waveform (1,2) t RC Address t AA OE t OE t OH t OLZ CS t ACS Don't care. t OHZ (3) t CLZ (4,5) Dout Data Valid t CHZ (3,4,5) AC Read Characteristics Notes (1) WE is High for Read Cycle. (2) All read cycle timing is referenced from the last valid address to the first transition address. (3) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. (4) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given module and from module to module. (5) These parameters are sampled and not 100% tested. Write Cycle No.1 Timing Waveform(1,4) tWC Address t WR(7) OE t AS(6) t AW t CW CS Don't Care WE t OHZ(3,9) t OW t WP(2) High-Z Dout t DW Din High-Z t DH Data Valid 5 (8) SYS82000FKX - 70/85/10/12 Issue 2.5 : February 2000 Write Cycle No.2 Timing Waveform (1,5) tWC Address t AS(6) t WR(7) t CW CS t AW t WP(2) WE tOH t WHZ(3,9) t OW High-Z Dout t DW (8) (4) Don't Care t DH High-Z Din Data Valid AC Write Characteristics Notes (1) All write cycle timing is referenced from the last valid address to the first transition address. (2) All writes occur during the overlap of CS and WE low. (3) If OE, CS, and WE are in the Read mode during this period, the I/O pins are low impedance state. Inputs of opposite phase to the output must not be applied because bus contention can occur. (4) Dout is the Read data of the new address. (5) OE is continuously low. (6) Address is valid prior to or coincident with CS and WE low, too avoid inadvertant writes. (7) CS or WE must be high during address transitions. (8) When CS is low : I/O pins are in the output state. Input signals of opposite phase leading to the output should not be applied. (9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. These parameters are sampled and not 100% tested. Data Retention Waveform DATA RETENTION MODE Vcc 4.5V 4.5V t CDR tR 2.2V 2.2V V DR CS CS > Vcc -0.2V 0V 6 SYS82000FKX - 70/85/10/12 Package Information Issue 2.5 : February 2000 Dimensions in mm Plastic 36 Pin 0.6" Dual-in-Line Low profile (DIP) 15.92 MAX 6.0 MAX 3.50 +/-0.50 48.26 MAX 2.54 TYP. 15.24 TYP. Ordering Information SYS82000FKXLI - 70 Speed 70 85 10 12 = = = = 70 ns 85 ns 100 ns 120 ns Temperature Range Blank = Commercial Temperature I = Industrial Temperature Power Consumption Blank = Standard Part L = Low Power Part Package FKX = Plastic 36 Pin 0.6" Low Profile DIP Organization 82000 = 2M x 8 Memory Type SYS = Static RAM Note : Although this data is believed to be accurate, the information contained herein is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed at any time without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director. 7
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