datasheet for ML610Q482P by LAPIS Semiconductor

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datasheet for ML610Q482P by LAPIS Semiconductor | Manualzz

FEDL610Q482P-0

Issue Date: Dec.9, 2009

ML610Q482P

8-bit Microcontroller

GENERAL DESCRIPTION

This LSI is a high-performance 8-bit CMOS microcontroller into which rich peripheral circuits, such as synchronous serial port,

UART, I

2

C bus interface (master), buzzer driver, battery level detect circuit, and RC oscillation type A/D converter, are incorporated around 8-bit CPU nX-U8/100.

The CPU nX-U8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture parallel procesing. The Flash ROM that is installed as program memory achieves low-voltage low-power consumption operation

(read operation) equivalent to mask ROM and is most suitable for battery-driven applications.

The on-chip debug function that is installed enables program debugging and programming.

FEATURES

 CPU

 8-bit RISC CPU (CPU name: nX-U8/100)

 Instruction system: 16-bit instructions

 Instruction set:

Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on

 On-Chip debug function

 Minimum instruction execution time

30.5

s (@32.768 kHz system clock)

0.244

s (@4.096 MHz system clock)

 Internal memory

 Internal 64KByte Flash ROM (32K16 bits) (including unusable 1KByte TEST area)

 Internal 4KByte Data RAM (40968 bits)

 Interrupt controller

 2 non-maskable interrupt sources (Internal source: 1, External source: 1)

 18 maskable interrupt sources (Internal sources: 14, External sources: 4)

 Time base counter

 Low-speed time base counter 1 channel

Frequency compensation (Compensation range: Approx.

488ppm to +488ppm. Compensation accuracy: Approx.

0.48ppm)

 High-speed time base counter 1 channel

 Watchdog timer

 Non-maskable interrupt and reset

 Free running

 Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s @32.768 kHz)

 Timers

 8 bits  4 channels (Timer0-3: 16-bit x 2 configuration available by using Timer0-1 or Timer2-3)

 Clock frequency measurement mode (in one channel of 16-bit configuration using Timer2-3)

1/27

LAPIS Semiconductor

 PWM

 Resolution 16 bits  1 channel

 Synchronous serial port

 Master/slave selectable

 LSB first/MSB first selectable

 8-bit length/16-bit length selectable

 UART

 TXD/RXD  1 channel

 Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits

 Positive logic/negative logic selectable

 Built-in baud rate generator

 I

2

C bus interface

 Master function only

 Fast mode (400 kbps@4MH ), standard mode (100 kbps@1MH , 50kbps@500kHz)

 Buzzer driver

 4 output modes, 8 frequencies, 16 duty levels

 RC oscillation type A/D converter

 24-bit counter

 Time division  2 channels

 Analog Comparator

 Operating voltage:

V

DD

=1.8V

3.6V

 Common mode input voltage:

0.2V

VDD 1.0V

 Input offset voltage:

50mV(max)

 Interrupt allow edge selection and sampling selection

 General-purpose ports

 Non-maskable interrupt input port  1 channel

 Input-only port  6 channels (including secondary functions)

 Output-only port  4 channels (including secondary functions)

 Input/output port  22 channels (including secondary functions)

 Reset

 Reset through the RESET_N pin

 Power-on reset generation when powered on

 Reset when oscillation stop of the low-speed clock is detected

 Reset by the watchdog timer (WDT) overflow

 Power supply voltage detect function

 Judgment voltages:

 Judgment accuracy:

One of 16 levels

2% (Typ.)

 Clock

 Low-speed clock: (This LSI can not guarantee the operation withou low-speed clock)

Crystal oscillation (32.768 kHz/38.4KHz)

 High-speed clock:

Built-in RC oscillation (500 kHz)

Built-in PLL oscillation (8.192 MHz

2.5%), crystal/ceramic oscillation (4.096 MHz), external clock

 Selection of high-speed clock mode by software:

Built-in RC oscillation, built-in PLL oscillation, crystal/ceramic oscillation, external clock

FEDL610Q482P-01

ML610Q482P

2/27

FEDL610Q482P-01

LAPIS Semiconductor

ML610Q482P

 Power management

 HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).

 STOP mode: Stop of low-speed oscillation and high-speed oscillation (Operations of CPU and peripheral circuits are stopped.)

 Clock gear: The frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock)

 Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals.

 Shipment

 Chip

ML610Q482P-xxxWA (Blank product: ML610Q482P-NNNWA)

 48-pin plastic TQFP

ML610Q482P-xxxTBZ03A (Blank product: ML610Q482P-NNNTBZ03A) xxx: ROM code number

 Guaranteed operating range

 Operating temperature: 40C to +85C

 Operating voltage: V

DD

= 1.1V to 3.6V

3/27

LAPIS Semiconductor

BLOCK DIAGRAM

ML610Q482P Block Diagram

Figure 1 show the block diagram of the ML610Q482P.

"*" indicates the secondary function of each port.

V

DD

V

SS

RESET_N

TEST

XT0

XT1

OSC0*

OSC1*

LSCLK*

OUTCLK*

V

DDL

V

DDX

IN0*

CS0*

RS0*

RT0*

CRT0*

RCM*

IN1*

CS1*

RS1*

RT1*

CMPP

CMPM

EPSW1 3

PSW

Timing

Controller

On-Chip

ICE

RESET &

TEST

OSC

Power

RC-ADC

2

Analog

Comparator

INT

1

INT

1

CPU (nX-U8/100)

GREG

0 15

ALU

Instruction

Decoder

INT

1

INT

4

INT

4

ELR1 3

LR

EA

SP

Instruction

Register

Data-bus

RAM

4096byte

Interrupt

Controller

WDT

TBC

8bit Timer

4

BLD

ECSR1 3

DSR/CSR

PC

BUS

Controller

INT

1

INT

1

INT

1

INT

1

INT

9

Figure 1 ML610Q482P Block Diagram

Program

Memory

(Flash)

64Kbyte

SSIO

UART

I

2

C

PWM

Buzzer

GPIO

V

PP

SCK0*

SIN0*

SOUT0*

RXD0*

TXD0*

SDA*

SCL*

FEDL610Q482P-01

ML610Q482P

PWM0*

BZ0*

NMI

P00 to P03

P10, P11

P20, P21, P22, P24

P30 to P35

P40 to P47

PA0 to PA7

4/27

LAPIS Semiconductor

PIN CONFIGURATION

ML610Q482P TQFP48 Pin Layout

FEDL610Q482P-01

ML610Q482P

P30

P31

P34

P32

P33

P35

VDD

VDDL

VSS

VDDX

XT0

XT1

37

38

39

40

41

42

43

44

45

46

47

48

Note:

The assignment of the pads P30 to P35 are not in order.

Figure 2 ML610Q482P TQFP48 Pin Configuration

20

19

18

17

24

23

22

21

16

15

14

13

VDD

P11/OSC1

P10/OSC0

VSS

VPP

NMI

RESET_N

TEST

P47

P46

P45

P44

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LAPIS Semiconductor

ML610Q482P Chip Pin Layout & Dimension

FEDL610Q482P-01

ML610Q482P

3.00mm

2.76mm

(NC): No Connection

Note:

The assignment of the pads P30 to P35 are not in order.

Chip size:

PAD count:

Minimum PAD pitch:

PAD aperture:

Chip thickness:

2.76 mm

 3.00 mm

48 pins

100

m

80

m  80 m

350

m

Voltage of the rear side of chip: V

SS

level

Figure 3 ML610Q482P Chip Layout & Dimension

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LAPIS Semiconductor

ML610Q482P Pad Coordinates

Table 1 ML610Q482P Pad Coordinates

Chip Center: X=0,Y=0

PAD

No.

Pad

Name

X

( m)

Y

( m)

1 CMPP -1380.0

2 CMPM -830.0

-1380.0

3 P00 -730.0

-1380.0

4 P01 -482.0

-1380.0

5 P02 -382.0

-1380.0

6 P03 -134.0

-1380.0

7 VSS -34.0

-1380.0

8 P24 219.0

-1380.0

9 P40 327.0

-1380.0

10 P41 655.0

-1380.0

11 P42 775.0

-1380.0

12 P43 1023.0

-1380.0

13 P44 1260.0

-912.0

14 P45 1260.0

15 P46 1260.0

16 P47 1260.0

17 TEST 1260.0

-778.0

-530.0

-426.0

-167.0

18 RESET_N 1260.0

19 NMI 1260.0

20 VPP 1260.0

21 VSS 1260.0

-67.0

181.0

281.0

411.0

22 P10 1261.3

23 P11 1261.3

610.0

858.0

24 VDD 1260.0

1010.0

PAD

No.

Pad

Name

X

( m)

Y

( m)

PA0 1380.0

1380.0

PA2 1380.0

PA3 1380.0

PA4 1380.0

1380.0

1380.0

PA7 1380.0

VSS 1380.0

P20 1380.0

P21 1380.0

P22 1380.0

922.0

769.0

42 P35 -1260.0

521.0

417.0

169.0

67.0

44 -1260.0

-122.0

-333.0

46 -1260.0

-503.0

-673.0

-773.0

XT1 -1021.0

FEDL610Q482P-01

ML610Q482P

7/27

LAPIS Semiconductor

PIN LIST

PAD

Primary function

No.

Pin name I/O Function

7,21,

33,45

Vss

24,43 V

44 V

46 V

20 V

DD

DDL

DDX

PP

Negative power supply pin

Positive power supply pin

Power supply pin for internal logic

(internally generated)

Power supply pin for low-speed oscillation

(internally generated)

Power supply pin for

Flash ROM

Input/output pin for

I/O testing

Secondary function

Pin name I/O

Function



18

RESET_

N

I

Reset input pin

  

Low-speed clock

I oscillation pin

  

Low-speed clock oscillation pin

  

3

4

5

6

P00/EXI

0

P01/EXI

1

P02/EXI

2/RXD0

P03/EXI

3

Non-maskable

I interrupt pin

I

I

I

I

Input port, External interrupt 0, Capture 0 input

Input port, External interrupt 1, Capture 1 input

Input port, External interrupt 2, UART0 receive

Input port, External interrupt 3

Analog comparator

I non-inverted input

Analog comparator

I inverted input





34

35

36

8

P20/LE

D0

P21LED

1

P22/LE

D2

P24/LE

D4

O

Output port

O

Output port

O

Output port

O

Output port

FEDL610Q482P-01

ML610Q482P

Tertiary function

Pin name I/O Function

  

  

OSC1 O

High-speed oscillation

LSCLK O

Low-speed clock output

OUTCLK O

High-speed clock output

BZ0 O

BZ0 output

PWM0 O

PWM0 output

CS0 O

RS0 O

RT0 O

RCT0 O

RC type ADC0 oscillation input pin

  

RC type ADC0 reference capacitor connection pin

RC type ADC0 reference resistor connection pin

RC type ADC0 resistor sensor connection pin

RC type ADC0 resistor/capacitor sensor connection pin

PWM0 O PWM0





8/27

LAPIS Semiconductor

PAD

Primary function

No.

Pin name I/O Function

13

14

P44/T02

P0CK

P45/T13

P1CK

I/O

I/O

Input/output port,

Timer 0/Timer

2/PWM0 external clock input

Input/output port,

Timer 1/Timer 3 external clock input

Input/output port

Input/output port

Input/output port

Input/output port

Input/output port

Input/output port

Input/output port

Input/output port

FEDL610Q482P-01

ML610Q482P

Secondary function

Pin name I/O Function

RC type ADC

RCM O oscillation monitor

SDA I/O

I

2

C data input/output

SCL I/O

I

2

C clock input/output

Tertiary function

Pin name I/O Function

  

SOUT0 I SSIO data output

TXD0 O

UART data output

RC type ADC1

IN1 I oscillation input pin

CS1 O

RS1 O

RT1 O

RC type ADC1 reference capacitor connection pin

RC type ADC1 reference resistor connection pin

RC type ADC1 resistor sensor connection pin

SSIO0 synchronous

SCK0 I/O clock

SOUT0 O SSIO0 data output

9/27

FEDL610Q482P-01

LAPIS Semiconductor

PIN DESCRIPTION

ML610Q482P

Pin name I/O Description

Primary/

Secondary/

Tertiary

Logic

System

— Negative set and the internal section is initialized. When this pin is set to a “H” level subsequently, program execution starts. A pull-up resistor is internally connected.

— —

XT1 O this pin. Capacitors CDL and CGL are connected across this pin and V

SS as required.

— —

OSC1 O

CDH and CGH (see measuring circuit 1) are connected across this pin and V

SS

.

This pin is used as the secondary function of the P10 pin(OSC0) and P11 pin(OSC1).

Secondary —

Secondary —

Secondary — the P20 pin.

Secondary — the P21 pin.

General-purpose input port

Primary Positive

Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used.

Primary Positive

Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used.

General-purpose output port

P20,P21,

P22,P24

O General-purpose output port.

Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used.

General-purpose input/output port

Primary Positive

Primary Positive

Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used.

Primary Positive

Since these pins have secondary functions, the pins cannot be used as a port when the secondary functions are used.

Primary Positive

10/27

FEDL610Q482P-01

LAPIS Semiconductor

ML610Q482P

Pin name I/O Description

Primary/

Secondary/

Tertiary

Logic

UART

Secondary Positive

P43 pin.

P42 or the primary function of the P02 pin.

I

2

C bus interface

I

2

C data input/output pin. This pin is used as the secondary function of the

P40 pin. This pin has an NMOS open drain output. When using this pin as a function of the I

2

C, externally connect a pull-up resistor.

I

2

C clock output pin. This pin is used as the secondary function of the P41 pin. This pin has an NMOS open drain output. When using this pin as a

2 function of the I C, externally connect a pull-up resistor.

Synchronous serial (SSIO)

Primary/Se condary

Positive

Secondary Positive

Secondary Positive

Tertiary — function of the P41 or P45 pin.

Tertiary Positive of the P40 or P44 pin.

Tertiary Positive function of the P42 or P46 pin.

PWM

Tertiary Positive

P43 or P34 pin.

Primary — the P44 pin.

External interrupt both edges. selection can be performed for each bit by software. These pins are used as the primary functions of the P00-P03 pins.

Primary

Positive/ negative

Primary

Positive/ negative

Timer

Primary these timers are selected by software. This pin is used as the primary function of the P44 pin.

Primary these timers are selected by software. This pin is used as the primary function of the P45 pin.

Buzzer

Secondary Positive/ negative

P22 pin.

LED drive

LED0,1,2,4 O NMOS open drain output pins to drive LED. These pins are used as the primary function of the P20,P21,P22,P24 pins.

Primary

Positive/ negative

11/27

LAPIS Semiconductor

Pin name I/O Description

RC oscillation type A/D converter of the P30 pin. secondary function of the P31 pin. reference resistor connection pin of Channel 0. used as the secondary function of the P34 pin.

This pin is used as the secondary function of the P33 pin. the P35 pin. function of the P44 pin. secondary function of the P45 pin. secondary function of the P46 pin.

Analog comparator used as the secondary function of the P47 pin.

For testing

Power supply

V

SS

V

DD

V

DDL

Capacitors CL0 and CL1 (see measuring circuit 1) are connected between this pin and V

SS

.

V

DDX

Capacitor Cx (see measuring circuit 1) is connected between this pin and

V

SS

.

V

PP

— internally connected.

FEDL610Q482P-01

ML610Q482P

Primary/

Secondary/

Tertiary

Logic

Secondary

Secondary

Secondary

Secondary

Secondary

Secondary

Secondary

Secondary

Secondary

Secondary

— —

— —

— —

— —

— —

— —

— —

— —

12/27

LAPIS Semiconductor

TERMINATION OF UNUSED PINS

Table 2 shows methods of terminating the unused pins.

Table 2 Termination of Unused Pins

FEDL610Q482P-01

ML610Q482P

Pin Recommended pin termination

V

PP

RESET_N

TEST

NMI

Open

Open

Open

P00 to P03

P10, P11

P20, P21, P22, P24

Open

V

DD

or V

SS

V

DD

Open

Open P30 to P35

P40 to P47

PA0 to PA7

Open

Open

CMPP,CMPM

V

DD

Note:

It is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting.

13/27

FEDL610Q482P-01

LAPIS Semiconductor

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ML610Q482P

(V

SS

= 0V)

Parameter Symbol Condition

Power supply voltage 1

Power supply voltage 2

Power supply voltage 3

Power supply voltage 4

Input voltage

Output voltage

Output current 1

Output current 2

Power dissipation

Storage temperature

V

I

I

V

V

V

V

OUT1

OUT2

T

V

DD

PP

DDL

DDX

IN

OUT

PD

STG

Ta = 25

C

Ta = 25

C

Ta = 25

C

Ta = 25

C

0.3 to +4.6

0.3 to +9.5

0.3 to +3.6

0.3 to +3.6

V

V

V

V

Ta = 25

C

Ta = 25

C

0.3 to V

0.3 to V

DD

DD

+0.3 V

+0.3 V

Port3–A, Ta = 25

C

Port2, Ta = 25

C

12 to +11

12 to +20 mA mA

Ta = 25

C 1.16

 55 to +150 C

RECOMMENDED OPERATING CONDITIONS

(V

SS

= 0V)

Parameter Symbol Condition

Operating temperature

Operating voltage

T

V

OP

DD





40 to +85 C

1.1 to 3.6 V

Operating frequency (CPU) f

OP

V

DD

= 1.1 to 3.6V

V

DD

= 1.3 to 3.6V

V

DD

= 1.8 to 3.6V

30k to 36k

30k to 650k

30k to 4.2M

Hz

Low-speed crystal oscillation frequency

Low-speed crystal oscillation external capacitor f

XTL

C

DL

C

GL

High-speed crystal/ceramic oscillation frequency

High-speed crystal oscillation external capacitor f

XTH

C

DH

Capacitor externally connected to

V

DDL

pin

C

GH

C

L0

C

L1

Capacitor externally connected to

V

DDX

pin

C

X

OPERATING CONDITIONS OF FLASH ROM



















32.768k/38.4k Hz

0 to 12

0 to 12

4.0M / 4.096M

24

24

1.0

30%

0.1

30%

0.1

30% pF

Hz pF

F

F

(V

SS

= 0V)

Parameter Symbol Condition

Operating temperature

Operating voltage

T

OP

At write/erase

V

DD

At

*1

V

DDL

At

V

PP

At

0 to +40

2.75 to 3.6

C

V

Write cycles

Data retention

C

EP

Y

DR





10 cycles

10

*1

: Those voltages must be supplied to V

DDL

pin and V

PP

pin when programming and eraseing Flash ROM. years

V

PP pin has an internal pulldown resister.

14/27

FEDL610Q482P-01

LAPIS Semiconductor

ML610Q482P

CONDITIONS OF ANALOG COMPARATOR

(V

DD

= 1.1 to 3.6V, V

SS

= 0V, Ta =

40 to +85C, unless otherwise specified) (2/4)

Parameter Symbol Condition

Common mode Input voltage CMV

IN

Input offset voltage

V

CMPOF

Response time T

CMP

V

DD

= 1.8 to 3.6V

V

DD

= 1.8 to 3.6V, Ta = 25

C

V

DD

= 1.8 to 3.6V, Ta = 25

C

Over drive = 100mV

Rating

Min. Typ. Max.

Unit

0.2













V

DD



100

3

1 V mV

Measuring circuit

1

Wake-up time

T

CMPw

Circuit current (during operation)

I

CMP

DC CHARACTERISTICS (1/4)

V

DD

= 1.8 to 3.6V,Ta = 25

C  

4

A

(V

DD

= 1.1 to 3.6V, V

SS

= 0V, Ta =

40 to +85C, unless otherwise specified) (1/4)

Parameter Symbol Condition

Rating

Min. Typ. Max.

Unit

Measuring circuit

500kHz RC oscillation frequency

PLL oscillation frequency*

4 f

RC f

PLL

Ta = 25

C

V

DD

= 1.3 to 3.6V

Ta =

40 to

+85

C

LSCLK = 32.768kHz

V

DD

= 1.8 to 3.6V

Typ.

10%

Typ.

35%

500

500

Typ.

10%

Typ.

35% kHz kHz

-2.5% 8.192

+2.5% MHz

Low-speed crystal oscillation start time*

2

500kHz RC oscillation start time

High-speed crystal oscillation start time*

3

T

XTL

T

RC

T

XTH





V

DD

= 1.8 to 3.6V





0.3 2 s

50 500

s

2 20

1

RESET

PLL oscillation start time

Low-speed oscillation stop detect time

*1

T

T

PLL

STOP

V

DD

= 1.8 to 3.6V



0.2 3 20

Reset pulse width

Reset noise elimination pulse width

P

P

RST

NRST





200









0.3

s

Power-on reset activation power rise time

T

POR

  

10 ms

*

1

: When low-speed crystal oscillation stops for a duration more than the low-speed oscillation stop detect time, the system is

* reset to shift to system reset mode.

2

: Use 32.768KHz Crystal Oscillator C-001R (Epson Toyocom) with capacitance C

GL

/C

DL

0pF.

*

*

3

4

: Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera).

: 1024 clock average.

RESET_N

VDD

0.1xV

DD

0.9xV

DD

T

POR

VIL1 VIL1

P

RST

RESET_N pin reset

Power on reset

15/27

FEDL610Q482P-01

LAPIS Semiconductor

ML610Q482P

DC CHARACTERISTICS (2/4)

Parameter Symbol

BLD threshold voltage

V

BLD

V

DD

(V

DD

= 1.1 to 3.6V, V

SS

= 0V, Ta =

40 to +85C, unless otherwise specified) (2/4)

Condition

LD2–0 = 0H

Rating

Min. Typ. Max.

Unit

1.35

Measuring circuit

LD2–0 = 1H

LD2–0 = 2H

LD2–0 = 3H

LD2–0 = 4H

LD2–0 = 5H

1.4

1.45

1.5

1.6

1.7

= 1.35 to 3.6V

LD2–0 = 6H

LD2–0 = 7H

LD2–0 = 8H

LD2–0 = 9H

LD2–0 = 0AH

LD2–0 = 0BH

LD2–0 = 0CH

LD2–0 = 0DH

LD2–0 = 0EH

LD2–0 = 0FH

Typ.

2%

1.8

1.9

2.0

2.1

2.2

2.3

2.4

2.5

2.7

2.9

Typ.

+2%

V

BLD threshold voltage temperature deviation

V

BLD

V

DD

= 1.35 to 3.6V

   %/C

Supply current 1 IDD1

CPU: In STOP state.

Low-speed/high-speed oscillation: stopped.

Ta=25

Ta=-40 to + 85



  5

A

1

Supply current 2

Supply current 3

Supply current 4

Supply current 5

IDD2

IDD3

IDD4

IDD5

CPU: In HALT state

(LTBC,WDT:Operating*

3

).High-speed oscillation:

Stopped.

CPU: In 32.768kHz operating state.*

1

High-speed oscillation:

Stopped.

CPU: In 500kHz CR operating state.

CPU: In 4.096MHz operating state.PLL: In oscillating state.V

DD

=

1.8 to 3.6V

Ta=25

Ta=-40 to + 85

Ta=25

Ta=-40 to + 85

Ta=25

Ta=-40 to + 85

Ta=25

Ta=-40 to + 85

















 6

A

5

 12

A

70 85

 100

A

0.83 1

 1.2 mA

Supply current 6 IDD6

CPU: In 4.096MHz operating state.Crystal/ceramic: In oscillating state. *

1

*

2

V

DD

= 3.0V

Ta=25

Ta=-40 to + 85





1.3 1.4

 2.0

*

1

: Use 32.768KHz Crystal Oscillator C-001R (Epson Toyocom) with capacitance C

GL

/C

DL

0pF.

*

*

2

3

: Use 4.096MHz Crystal Oscillator CHC49SFWB (Kyocera).

: Significant bits of BLKCON0~BLKCON4 registers are all “1”. mA

16/27

FEDL610Q482P-01

LAPIS Semiconductor

DC CHARACTERISTICS (3/4)

ML610Q482P

Parameter Symbol

Output voltage 1

(P20, P21, P22,

P24/2 nd

function is selected)

(P30–P35)

(P40–P47)

(PA0–PA7)

VOH1

VOL1

IOH1 =

(V

DD

= 1.1 to 3.6V, V

SS

= 0V, Ta =

40 to +85C, unless otherwise specified) (3/4)

Condition

Rating

Min. Typ. Max.

Unit

Measuring circuit

0.5mA, V

IOH1 = -0.1mA, V

IOH1 = -0.03mA, V

IOL1 = +0.5mA, V

IOL1 = +0.1mA, V

DD

DD

DD

DD

DD

= 1.8 to 3.6V

= 1.3 to 3.6V

= 1.1 to 3.6V

= 1.8 to 3.6V

= 1.3 to 3.6V

V

DD

0.5

V

DD

0.3

V

DD

0.3

















0.5

0.5

V 2

IOL1 = +0.03mA, V

DD

= 1.1 to 3.6V

 

0.3

Output voltage 2

(P20, P21, P22,

P24/2 nd

function is

Not selected)

Output voltage 3

(P40, P41)

Output leakage

(P20, P21, P22,

P24)

(P30–P35)

(P40–P47)

(PA0–PA7)

*1

VOL2

VOL3

IOOH

IOOL

IOL2 = +5mA, V

DD

= 1.8 to 3.6V

IOL3 = +3mA, V

DD

= 2.0 to 3.6V

(when I

2

C mode is selected)

VOH = V

DD

(in high-impedance state)

VOL = V

SS

(in high-impedance state)







1









0.5

0.4

1



A 3

Input current 1

(RESET_N)

Input current 1

(TEST)

Input current 2

(NMI)

(P00–P03)

(P10, P11)

(P30–P35)

(P40–P47)

(PA0–PA7)

IIH1

IIL1

IIH1

IIL1

IIH2

IIL2

IIH2Z

IIL2Z

VIL1 = V

VIH1 = V

DD

1

SS

V

DD

= 1.8 to 3.6V

600

V

DD

= 1.3 to 3.6V

600

300

300

20

-10

VIH1 = V

DD

V

DD

= 1.1 to 3.6V

600 300

V

DD

= 1.8 to 3.6V

20

300

V

DD

= 1.3 to 3.6V

V

DD

= 1.1 to 3.6V

10

2

VIL1 = V ss

-1

300

300



-2

600

600

600

V

DD

= 1.8 to 3.6V

2 30 200

VIH2 = V

DD

(when pulled-down)

VIL2 = V

SS

(when pulled-up)

V

DD

= 1.3 to 3.6V

0.2

V

DD

= 1.1 to 3.6V

0.01

V

DD

= 1.8 to 3.6V

200

V

DD

= 1.3 to 3.6V

200

V

DD

= 1.1 to 3.6V

200

30 200

30

30

200

2

30 -0.2

30

-0.01

A 4

VIH2 = V

DD

(in high-impedance state)

 

1

VIL2 = V

SS

(in high-impedance state)

1  

17/27

LAPIS Semiconductor

DC CHARACTERISTICS (4/4)

Input pin capacitance

(NMI)

(P00–P03)

(P10, P11)

(P30–P35)

(P40–P47)

(PA0–PA7)

Parameter Symbol

Input voltage 1

(RESET_N)

(TEST)

(NMI)

(P00–P03)

(P10, P11)

(P31–P35)

(P40–P43)

(P45–P47)

(PA0–PA7)

*1

VIH1

VIL1

VIH2

Input voltage 2

(P30, P44)

VIL2

CIN

FEDL610Q482P-01

ML610Q482P

V

V

(V

DD

= 1.1 to 3.6V, V

SS

= 0V, Ta =

40 to +85C, unless otherwise specified) (4/4)

Condition

Rating

Min. Typ. Max.

Unit

Measuring circuit

DD

DD

= 1.3 to 3.6V

= 1.1 to 3.6V



0.7

V

DD

0.7

V

DD





V

V

DD

DD

V

V

DD

DD

= 1.3 to 3.6V

= 1.1 to 3.6V



0

0





0.3

V

DD

0.2

V

DD

V 5

0.7

V

DD

V

DD



0



0.3

V

DD f = 10kHz

V rms

= 50mV

Ta = 25

C

 

5 pF



18/27

FEDL610Q482P-01

LAPIS Semiconductor

ML610Q482P

MEASURING CIRCUITS

MEASURING CIRCUIT 1

XT0

32.768kHz crystal

C

GH

C

DH

4.096MHz crystal

C

V

XT1

P10/OSC0

P11/OSC1

V

DD

A

V

DDL

C

L1

C

L0

MEASURING CIRCUIT 2

VIH

VIL

(*1)

V

DDX

C

X

V

DD

V

DDL

V

DDX

V

SS

V

SS

C

V

: 1

F

C

L0

: 1

F

C

L1

: 0.1

F

C

X

: 0.1

F

C

GH

: 24pF

C

DH

: 24pF

32.768kHz crystal:

C-001R (Epson Toyocom)

4.096MHz crystal:

HC49SFWB (Kyocera)

(*2)

V

(*1) Input logic circuit to determine the specified measuring conditions.

(*2) Measured at the specified output pins.

19/27

LAPIS Semiconductor

MEASURING CIRCUIT 3

VIH

VIL

RS1

MEASURING CIRCUIT 4

(*3)

A

MEASURING CIRCUIT 5

VIH

VIL

(*1)

V

DD

V

DDL

V

DDX

*1: Input logic circuit to determine the specified measuring conditions.

*2: Measured at the specified output pins.

V

DD

V

DDL

V

DDX

*3: Measured at the specified output pins.

V

DD

V

DDL

V

DDX

V

SS

V

SS

V

SS

(*2)

A

*1: Input logic circuit to determine the specified measuring conditions.

FEDL610Q482P-01

ML610Q482P

20/27

FEDL610Q482P-01

LAPIS Semiconductor

ML610Q482P

AC CHARACTERISTICS (External Interrupt)

(V

DD

= 1.1 to 3.6V, V

SS

= 0V, Ta =

40 to +85C, unless otherwise specified)

Rating

Parameter Symbol Condition

Min. Typ. Max.

Unit

Interrupt: Enabled (MIE = 1),

External interrupt disable period

T

NUL

CPU: NOP operation

System clock: 32.768kHz

76.8



106.8

s

P00–P03

(Rising-edge interrupt)

P00–P03

(Falling-edge interrupt)

NMI, P00–P03

(Both-edge interrupt)

AC CHARACTERISTICS (UART)

t

NUL t

NUL t

NUL

Parameter Symbol

(V

DD

= 1.3 to 3.6V, V

SS

= 0V, Ta =

40 to +85C, unless otherwise specified)

Condition

Rating

Unit

Min. Typ. Max.

Transmit baud rate t

TBRT

 

BRT*

1  s

Receive baud rate t

RBRT



BRT*

1

3%

BRT*

1

BRT*

1 s

+3%

*

1

: Baud rate period (including the error of the clock frequency selected) set with the UART0 baud rate register (UA0BRTL,H) and the UART0 mode register 0 (UA0MOD0).

TXD0*

RXD0* t

TBRT t

RBRT

*: Indicates the secondary function of the port.

21/27

FEDL610Q482P-01

LAPIS Semiconductor

ML610Q482P

AC CHARACTERISTICS (Synchronous Serial Port)

(V

DD

= 1.3 to 3.6V, V

SS

= 0V, Ta =

40 to +85C, unless otherwise specified)

Parameter Symbol Condition

Rating

Unit

Min. Typ. Max.

SCLK input cycle

(slave mode)

When RC oscillation is active *

2 t

SCYC

(V

DD

= 1.3 to 3.6V)

10

1









SCLK output cycle

(master mode) t

SCYC

 

SCLK*

1 

SCLK input pulse width

(slave mode)

When RC oscillation is active *

2 t

SW

(V

DD

= 1.3 to 3.6V)

When high-speed oscillation is active *

3

(V

DD

= 1.8 to 3.6V)

4

0.4









SCLK output pulse width

(master mode) t

SW



SCLK*

1

0.4

SCLK*

1

0.5

SCLK*

1

0.6

SOUT output delay time

(slave mode)

When RC oscillation is active *

2

(V

DD

= 1.3 to 3.6V)

 

500

SOUT output delay time

(master mode) t t

SD

SD

When high-speed oscillation is active *

3

(V

DD

= 1.8 to 3.6V)

When RC oscillation is active *

(V

DD

= 1.3 to 3.6V)

2

When high-speed oscillation is active *

3

(V

DD

= 1.8 to 3.6V)





240

500

240

SIN input setup time

(slave mode) t

SS



80

 

SIN input setup time

(master mode) t

SS

When RC oscillation is active *

(V

DD

= 1.3 to 3.6V)

2

When high-speed oscillation is active *

3

(V

DD

= 1.8 to 3.6V)

500

240









When RC oscillation is active *

2

(V

DD

= 1.3 to 3.6V)

300

 

SIN input hold time t

SH

When high-speed oscillation is active *

3

(V

DD

= 1.8 to 3.6V)

80

 

*

*

1

2

: Clock period selected with S0CK3–0 of the serial port 0 mode register (SIO0MOD1)

*

3

: When RC oscillation is selected with OSCM1–0 of the frequency control register (FCON0)

: When Crystal/ceramic oscillation , built-in PLL oscillation , or external clock input is selected with OSCM1–0 of the frequency control register (FCON0)

When high-speed oscillation is active *

3

(V

DD

= 1.8 to 3.6V)

s

s s

s

s s ns ns ns ns ns

SCLK0*

SOUT0*

SIN0* t

SD t

SW t

SCYC t

SS t

SW

*: Indicates the secondary function of the port.

t

SH t

SD

22/27

FEDL610Q482P-01

LAPIS Semiconductor

ML610Q482P

AC CHARACTERISTICS (I

2

C Bus Interface: Standard Mode 100kbit/s)

(V

DD

= 1.8 to 3.6V, V

SS

= 0V, Ta =

40 to +85C, unless otherwise specified)

SDA setup time

SDA setup time

(stop condition)

Bus-free time

Parameter Symbol

SCL clock frequency

SCL hold time

(start/restart condition)

SCL ”L” level time

SCL ”H” level time

SCL setup time

(restart condition)

SDA hold time f

SCL t

HD:STA t

LOW t

HIGH t

SU:STA t

HD:DAT t

SU:DAT t

SU:STO

Rating

Condition

Min. Typ. Max.

Unit



0



100 kHz















4.0

4.7

4.0

4.7

0

0.25

4.0



























s

s

s

s

s

s

s t

BUF



4.7

  s

AC CHARACTERISTICS (I

2

C Bus Interface: Fast Mode 400kbit/s)

(V

DD

= 1.8 to 3.6V, V

SS

= 0V, Ta =

40 to +85C, unless otherwise specified)

Parameter Symbol f

SCL

Rating

Condition

Min. Typ. Max.

Unit



0



400 kHz

SCL clock frequency

SCL hold time

(start/restart condition)

SCL ”L” level time

SCL ”H” level time

SCL setup time

(restart condition)

SDA hold time

SDA setup time

SDA setup time

(stop condition)

Bus-free time t

HD:STA t

LOW t

HIGH t

SU:STA t

HD:DAT t

SU:DAT t

SU:STO t

BUF

















0.6

1.3

0.6

0.6

0

0.1

0.6

1.3































s

s

s

s

s

s

s

s

P40/SDA

P41/SCL

Start condition t

HD:STA t

LOW t

HIGH

Restart condition t

SU:STA t

HD:STA t

SU:DAT t

HD:DAT

Stop condition t

SU:STO t

BUF

23/27

FEDL610Q482P-01

LAPIS Semiconductor

ML610Q482P

AC CHARACTERISTICS (RC Oscillation A/D Converter)

(V

DD

= 1.3 to 3.6V, V

SS

= 0V, Ta =

20 to +70C, unless otherwise specified)

Parameter Symbol Condition

Rating

Unit

Min. Typ. Max.

Resistors for oscillation

RS0, RS1,

RT0, CS0, CT0, CS1

 740pF

1

  k

RT0-1,RT1

Oscillation frequency

VDD = 1.5V f f

OSC1

OSC2

Resistor for oscillation = 1k

Resistor for oscillation = 10k

 209.4

 41.29 55.27 64.16

RS to RT oscillation frequency ratio

*1

VDD = 1.5V f

OSC3

Kf1

Kf2

Resistor for oscillation = 100k

 4.71 5.97 7.06

RT0, RT0-1, RT1 = 1kHz

RT0, RT0-1, RT1 = 10kHz

5.567

0.99

5.982

1

6.225

1.01





Kf3 f

OSC1

RT0, RT0-1, RT1 = 100kHz 0.104 0.108 0.118



Resistor for oscillation = 1k

 407.3

594.6

Oscillation frequency

VDD = 3.0V

RS to RT oscillation frequency ratio

*1 f f

OSC2

OSC3

Kf1

Kf2

Resistor for oscillation = 10k

 49.76 59.28 72.76 

Resistor for oscillation = 100k

 5.04 5.993 7.04 

RT0, RT0-1, RT1 = 1kHz

RT0, RT0-1, RT1 = 10kHz

8.006

0.99

8.210

1

8.416

1.01

VDD = 3.0V

Kf3 RT0, RT0-1, RT1 = 100kHz 0.100 0.108 0.115

*

1

: Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same





 conditions.

Kfx = f f

OSCX

OSCX

(RT0

(RS0

CS0 oscillation)

CS0 oscillation)

(x = 1, 2, 3)

, f

OSCX

(RT0-1

CS0 oscillation) f

OSCX

(RS0

CS0 oscillation)

, f f

OSCX

OSCX

(RT1

(RS1

CS1 oscillation)

CS1 oscillation)

Note:

VIH

VIL

(*1)

*1: Input logic circuit to determine the specified measuring conditions.

C

V

CVR0

V

DD

V

DDL

RS0

V

DDX

C

L1

C

L0

C

X

RT0

CVR1

IN1 CS1 RS1 RT1

V

SS

RCM

RT0, RT0-1, RT1: 1k

 /10k/100k

RS0, RS1: 10k

CS0, CT0, CS1: 560pF

CVR0, CVR1: 820pF

Frequency measurement

(f

OSCX

)

- Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1 and RS0/RS1. The coupling capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise around the node.

- When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please have VSS(GND) trace next to the signal.

- Please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. Wiring to reserved components may affect to the A/D conversion operation by noise the components itself may have.

24/27

LAPIS Semiconductor

Package Dimensions

(Unit: mm)

FEDL610Q482P-01

ML610Q482P

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact our responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).

25/27

LAPIS Semiconductor

REVISION HISTORY

Document No. Date

FEDL610Q482P-01 Dec.9, 2009

Page

Previous

Edition

Current

Edition

– – Formally edition 1

Description

FEDL610Q482P-01

ML610Q482P

26/27

FEDL610Q482P-01

LAPIS Semiconductor

ML610Q482P

NOTICE

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Co., Ltd.

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Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production.

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Copyright 2008 - 2011 LAPIS Semiconductor Co., Ltd.

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