8 Mbit (1M x 8-Bit/512 K x 16-Bit), 3 V S29AL008D

8 Mbit (1M x 8-Bit/512 K x 16-Bit), 3 V S29AL008D
S29AL008D
8 Mbit (1M x 8-Bit/512 K x 16-Bit), 3 V
Boot Sector Flash
This product has been retired and is not recommended for designs. For new and current designs, S29AL008J supercedes
S29AL008D. This is the factory-recommended migration path. Please refer to the S29AL008J data sheet for specifications and
ordering information.
Distinctive Characteristics
Performance Characteristics
 Single Power Supply Operation
– 2.7 to 3.6 volt read and write operations for battery-powered
applications
 High Performance
– Access times as fast as 55 ns
– Extended temperature range (-40°C to +125°C)
 Manufactured on 200 nm Process Technology
– Compatible with 0.32 µm and 230 nm Am29LV800 devices
 Ultra-low Power Consumption (typical values at 5 MHz)
– 200 nA Automatic Sleep mode current
– 200 nA standby mode current
– 7 mA read current
– 15 mA program/erase current
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 Cycling Endurance: 1,000,000 cycles per sector typical
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 Data Retention: 20 years typical
– Reliable operation for the life of the system
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Package Option
 48-ball FBGA
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 48-pin TSOP
 44-pin SO
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 Flexible Sector Architecture
– One 16-Kbyte, two 8-Kbyte, one 32-Kbyte, and fifteen 64-Kbyte
sectors (byte mode)
– One 8 Kword, two 4 Kword, one 16-Kword, and fifteen 32-Kword
sectors (word mode)
– Supports full chip erase
– Sector Protection features:
– A hardware method of locking a sector to prevent any program or
erase operations within that sector
– Sectors can be locked in-system or via programming equipment
– Temporary Sector Unprotect feature allows code changes in
previously locked sectors
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Architectural Advantage
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 Unlock Bypass Program Command
– Reduces overall programming time when issuing multiple program
command sequences
 Top or Bottom Boot Block Configurations Available
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 Embedded Algorithms
– Embedded Erase algorithm automatically preprograms and
erases the entire chip or any combination of designated sectors
– Embedded Program algorithm automatically writes and verifies
data at specified addresses
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 Compatibility with JEDEC Standards
– Pinout and software compatible with single-power supply Flash
– Superior inadvertent write protection
Cypress Semiconductor Corporation
Document Number: 002-01233 Rev. *A
Software Features
 Data# Polling and Toggle Bits
– Provides a software method of detecting program or erase
operation completion
 Erase Suspend/Erase Resume
– Suspends an erase operation to read data from, or program data
to, a sector that is not being erased, then resumes the erase
operation
Hardware Features
 Ready/Busy# Pin (RY/BY#)
– Provides a hardware method of detecting program or erase cycle
completion
 Hardware Reset Pin (RESET#)
– Hardware method to reset the device to reading array data
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 09, 2015
S29AL008D
General Description
The S29AL008D is an 8 Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in
48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. For more information, refer to publication number 21536. The word-wide data
(x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device requires only a single, 3.0 volt VCC supply
to perform read, program, and erase operations. A standard EPROM programmer can also be used to program and erase the device.
This device is manufactured using Spansion’s 200 nm process technology, and offers all the features and benefits of the
Am29LV800B, which was manufactured using 0.32 µm process technology.
The standard device offers access times of 55, 60, 70, and 90 ns, allowing high speed microprocessors to operate without wait
states. To eliminate bus contention the device contains separate chip enable (CE#), write enable (WE#) and output enable (OE#)
controls.
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The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated
voltages are provided for the program and erase operations.
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The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to
the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine
that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming
and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
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Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an
internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode
facilitates faster programming times by requiring only two write cycles to program data instead of four.
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Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal
algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During
erase, the device automatically times the erase pulse widths and verifies proper cell margin.
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The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7
(Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle is completed, the device is ready to read array data or
accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other
sectors. The device is fully erased when shipped from the factory.
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Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power
transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors
of memory. This can be achieved in-system or via programming equipment.
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The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any
sector that is not selected for erasure. True background erase can thus be achieved.
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The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The
RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system
microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses are stable for a specified amount of time, the device enters the
automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in
both these modes.
Spansion’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality,
reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.
Document Number: 002-01233 Rev. *A
Page 2 of 49
S29AL008D
Contents
Pin Configuration......................................................... 6
5.
Logic Symbol ............................................................... 7
6.
6.1
Ordering Information ................................................... 7
Standard Products ......................................................... 7
7.
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
Device Bus Operations................................................ 8
Word/Byte Configuration................................................ 9
Requirements for Reading Array Data........................... 9
Writing Commands/Command Sequences.................... 9
Program and Erase Operation Status............................ 9
Standby Mode................................................................ 9
Automatic Sleep Mode................................................. 10
RESET#: Hardware Reset Pin..................................... 10
Output Disable Mode ................................................... 10
Autoselect Mode .......................................................... 12
Sector Protection/Unprotection .................................... 12
Temporary Sector Unprotect........................................ 13
Hardware Data Protection............................................ 15
8.
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
Command Definitions................................................
Reading Array Data .....................................................
Reset Command ..........................................................
Autoselect Command Sequence .................................
Word/Byte Program Command Sequence...................
Unlock Bypass Command Sequence ..........................
Chip Erase Command Sequence ................................
Sector Erase Command Sequence .............................
Erase Suspend/Erase Resume Commands ................
15
15
16
16
16
16
18
18
19
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
Write Operation Status ..............................................
DQ7: Data# Polling ......................................................
RY/BY#: Ready/Busy#.................................................
DQ6: Toggle Bit I .........................................................
DQ2: Toggle Bit II ........................................................
Reading Toggle Bits DQ6/DQ2....................................
DQ5: Exceeded Timing Limits .....................................
DQ3: Sector Erase Timer.............................................
21
21
22
22
23
23
23
24
10.
Absolute Maximum Ratings...................................... 25
11.
Operating Ranges ...................................................... 26
17. Revision History.......................................................... 44
17.1 Revision A (September 8, 2004)................................... 44
17.2 Revision A 1 (February 18, 2005) ................................. 44
17.3 Revision A2 (June 1, 2005)........................................... 44
17.4 Revision A3 (June 16, 2005)......................................... 45
17.5 Revision A4 (February 16, 2006) .................................. 45
17.6 Revision A5 (May 22, 2006).......................................... 45
17.7 Revision A6 (September 6, 2006)................................. 45
17.8 Revision A7 (October 31, 2006).................................... 45
17.9 Revision A8 (August 29, 2007) ..................................... 45
17.10Revision A9 (September 19, 2007) .............................. 45
17.11Revision A10 (November 27, 2007) ............................. 46
17.12Revision A11 (February 27, 2009)................................ 46
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4.
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Connection Diagrams.................................................. 5
Special Handling Instructions for FBGA Package.......... 6
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Block Diagram.............................................................. 4
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2.
16.1 TS 048—48-Pin Standard TSOP .................................. 41
16.2 VBK 048—48 Ball Fine-Pitch Ball Grid Array (FBGA)
8.15 x 6.15 mm .............................................................42
16.3 SO 044—44-Pin Small Outline Package ...................... 43
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Product Selector Guide ............................................... 4
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1.
12. DC Characteristics..................................................... 27
12.1 Zero Power Flash......................................................... 28
13.
Test Conditions .......................................................... 29
14.
Key to Switching Waveforms.................................... 29
15. AC Characteristics..................................................... 30
15.1 Erase/Program Operations .......................................... 33
15.2 Erase and Programming Performance ........................ 39
16.
Physical Dimensions ................................................. 41
Document Number: 002-01233 Rev. *A
Page 3 of 49
S29AL008D
1.
Product Selector Guide
Family Part Number
Speed Options
S29AL008D
Full Voltage Range: VCC = 2.7 – 3.6 V
Regulated Voltage Range: VCC = 3.0 – 3.6V
60
70
90
55
Max access time, ns (tACC)
55
60
70
90
Max CE# access time, ns (tCE)
55
60
70
90
Max OE# access time, ns (tOE)
25
25
30
35
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Note
See AC Characteristics on page 30 for full specifications.
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2. Block Diagram
Input/Output
Buffers
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Erase Voltage
Generator
RESET#
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Sector Switches
VSS
DQ0–DQ15 (A-1)
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RY/BY#
VCC
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State
Control
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WE#
BYTE#
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Command
Register
PGM Voltage
Generator
CE#
STB
Data
Latch
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OE#
Chip Enable
Output Enable
Logic
Timer
Address Latch
VCC Detector
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
STB
A0–A18
Document Number: 002-01233 Rev. *A
Page 4 of 49
S29AL008D
3.
Connection Diagrams
Figure 3.1 Standard TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
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A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
Figure 3.2 SO Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
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RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
CE#
VSS
OE#
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
Document Number: 002-01233 Rev. *A
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
Page 5 of 49
S29AL008D
B6
C6
D6
E6
F6
G6
H6
A13
A12
A14
A15
A16
BYTE#
DQ15/A-1
VSS
A5
B5
C5
D5
E5
F5
G5
H5
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
WE#
RESET#
NC
NC
DQ5
DQ12
VCC
DQ4
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY#
NC
A18
NC
DQ2
DQ10
DQ11
DQ3
A2
B2
C2
D2
E2
F2
G2
A7
A17
A6
A5
DQ0
DQ8
DQ9
A1
B1
C1
D1
E1
F1
A3
A4
A2
A1
A0
CE#
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A6
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Figure 3.3 Fine-pitch BGA Pinout (Top View, Balls Facing Down)
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H2
DQ1
H1
VSS
3.1
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G1
OE#
Special Handling Instructions for FBGA Package
Description
A0–A18
19 addresses
DQ0–DQ14
DQ15/A-1
BYTE#
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I/O Name
15 data inputs/outputs
DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode)
Selects 8-bit or 16-bit mode
CE#
Chip enable
OE#
Output enable
WE#
R
Pin Configuration
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Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be
damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is
exposed to temperatures above 150°C for prolonged periods of time.
Write enable
RESET#
Hardware reset pin, active low
RY/BY#
Ready/Busy# output
VCC
3.0 volt-only single power supply (see Product Selector Guide on page 4 for speed options and voltage supply
tolerances)
VSS
Device ground
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Pin not connected internally
Document Number: 002-01233 Rev. *A
Page 6 of 49
S29AL008D
5. Logic Symbol
19
A0–A18
16 or 8
DQ0–DQ15
(A-1)
CE#
OE#
WE#
Ordering Information
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RY/BY#
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BYTE#
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RESET#
Standard Products
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This product has been retired and is not recommended for designs. For new and current designs, S29AL008J supercedes
S29AL008D. This is the factory-recommended migration path. Please refer to the S29AL008J data sheet for specifications and
ordering information.
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S29AL008D
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Spansion standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
Packing Type
0 = Tray
1 = Tube
2 = 7” Tape and Reel
3 = 13” Tape and Reel
Model Number
01 = x8/x16, VCC = 2.7 - 3.6V, top boot sector device
R1 = x8/x16, VCC = 3.0 - 3.6V. top boot sector device
02 = x8/x16, VCC = 2.7 - 3.6V, bottom boot sector device
R2 = x8/x16, VCC = 3.0 - 3.6V. bottom boot sector device
Temperature Range
I = Industrial (-40°C to +85°C)
N = Extended (-40°C to +125°C)
Package Material Set
A = Standard
F = Pb-Free
Package Type
T = Thin Small Outline Package (TSOP) Standard Pinout
B = Fine-pitch Ball-Grid Array Package
M = Small Outline Package (SOP) Standard Pinout
Speed Option
55 = 55 ns Access Speed
60 = 60 ns Access Speed
70 = 70 ns Access Speed
90 = 90 ns Access Speed
Device Number/Description
S29AL008D
8 Megabit Flash Memory manufactured using 200 nm process technology
3.0 Volt-only Read, Program, and Erase
Document Number: 002-01233 Rev. *A
Page 7 of 49
S29AL008D
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm
availability of specific valid combinations and to check on newly released combinations.
S29AL008D Valid Combinations
Package Type,
Material, and
Temperature Range
Model
Number
55
TAI, TFI
R1, R2
60, 70, 90
TAI, TFI, TAN, TFN
01, 02
55
BAI, BFI
R1, R2
60, 70, 90
BAI, BFI, BAN, BFN
01, 02
55
MAI, MFI
R1, R2
60, 70, 90
MAI, MFI, MAN, MFN
01, 02
Speed
Option
Device Number
Packing Type
0, 3 (Note 1)
TS048 (Note 3)
TSOP
0, 2, 3 (Note 1)
VBK048 (Note 4)
Fine-Pitch
BGA
0, 1, 3 (Note 2)
SO044 (Note 3)
SOP
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S29AL008D
Package Description
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Notes
1. Type 0 is standard. Specify other options as required.
3. TSOP and SOP package markings omit packing type designator from ordering part number.
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4. BGA package marking omits leading S29 and packing type designator from ordering part number.
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2. Type 1 is standard. Specify other options as required.
Device Bus Operations
CE#
BYTE#
= VIL
DQ8–DQ14 = High-Z,
DQ15 = A-1
RESET#
H
H
AIN
DOUT
DOUT
H
AIN
DIN
DIN
X
VCC 
0.3 V
X
High-Z
High-Z
High-Z
L
L
H
L
R
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X
L
H
H
H
X
High-Z
High-Z
High-Z
X
X
X
L
X
High-Z
High-Z
High-Z
Sector Protect (Note 2)
L
H
L
VID
Sector Address,
A6 = L, A1 = H,
A0 = L
DIN
X
X
Sector Unprotect (Note 2)
L
H
L
VID
Sector Address,
A6 = H, A1 = H,
A0 = L
DIN
X
X
Temporary Sector Unprotect
X
X
X
VID
AIN
DIN
DIN
High-Z
Reset
N
Output Disable
BYTE#
= VIH
WE#
Write
VCC 
0.3 V
DQ0–
DQ7
OE#
Read
Standby
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Operation
DQ8–DQ15
Addresses
(Note 1)
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S29AL008D Device Bus Operations
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This section describes the requirements and use of the device bus operations, which are initiated through the internal command
register. The command register itself does not occupy any addressable memory location. The register is composed of latches that
store the commands, along with the address and data information needed to execute the command. The contents of the register
serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table lists the device bus
operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these
operations in further detail.
Legend
L = Logic Low = VIL
H = Logic High = VIH
VID = 12.0 0.5 V
X = Don’t Care
AIN = Address In
DIN = Data In
DOUT = Data Out
Notes
1. Addresses are A18:A0 in word mode (BYTE# = VIH), A18:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See Sector Protection/Unprotection on page 12.
Document Number: 002-01233 Rev. *A
Page 8 of 49
S29AL008D
7.1
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is
set at logic 1, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by
CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
7.2
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the
device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines
whether the device outputs array data in words or bytes.
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The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no
spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read access until the command register contents are altered.
Writing Commands/Command Sequences
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7.3
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See Reading Array Data on page 15 for more information. Refer to Table , Read Operations on page 30 for timing specifications and
to Figure 15.1 on page 30 for the timing diagram. ICC1 in DC Characteristics on page 27 represents the active current specification
for reading array data.
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To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the
system must drive WE# and CE# to VIL, and OE# to VIH.
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For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to Word/Byte
Configuration on page 9 for more information.
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The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the Unlock Bypass mode,
only two write cycles are required to program a word or byte, instead of four. The Word/Byte Program Command Sequence
on page 16 contains details on programming data to the device using both standard and Unlock Bypass command sequences.
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An erase operation can erase one sector, multiple sectors, or the entire device. Table on page 10 and Table on page 11 indicate
the address space that each sector occupies. A sector address consists of the address bits required to uniquely select a sector. The
Command Definitions on page 15 contains details on erasing a sector or the entire chip, or suspending/resuming the erase
operation.
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After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read
autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings
apply in this mode. Refer to the Autoselect Mode on page 12 and Autoselect Command Sequence on page 16 for more information.
ICC2 in DC Characteristics on page 27 represents the active current specification for the write mode. The AC Characteristics
on page 30 contains timing specification tables and timing diagrams for write operations.
7.4
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0.
Standard read cycle timings and ICC read specifications apply. Refer to Write Operation Status on page 21 for more information, and
to AC Characteristics on page 30 for timing diagrams.
7.5
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current
consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC  0.3 V. (Note that this is a more
restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within VCC  0.3 V, the device is in the standby mode,
Document Number: 002-01233 Rev. *A
Page 9 of 49
S29AL008D
but the standby current is greater. The device requires standard access time (tCE) for read access when the device is in either of
these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation is completed.
In DC Characteristics on page 27, ICC3 and ICC4 represents the standby current specification.
7.6
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when
addresses remain stable for tACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals.
Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and
always available to the system. ICC5 in DC Characteristics on page 27 represents the automatic sleep mode current specification.
RESET#: Hardware Reset Pin
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es
The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for
at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/
write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The
operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data
integrity.
rN
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby
current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current is greater.
fo
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the
system to read the boot-up firmware from the Flash memory.
om
m
en
de
d
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is
complete, which requires a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine
whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is
1), the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after
the RESET# pin returns to VIH.
Refer to AC Characteristics on page 30 for RESET# parameters and to Figure 15.2 on page 31 for the timing diagram.
Output Disable Mode
ec
7.8
R
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.
N
ot
S29AL008D Top Boot Block Sector Addresses
Address Range (in hexadecimal)
Sector
A18
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
SA0
0
0
0
0
X
X
X
64/32
00000h–0FFFFh
00000h–07FFFh
SA1
0
0
0
1
X
X
X
64/32
10000h–1FFFFh
08000h–0FFFFh
SA2
0
0
1
0
X
X
X
64/32
20000h–2FFFFh
10000h–17FFFh
SA3
0
0
1
1
X
X
X
64/32
30000h–3FFFFh
18000h–1FFFFh
SA4
0
1
0
0
X
X
X
64/32
40000h–4FFFFh
20000h–27FFFh
SA5
0
1
0
1
X
X
X
64/32
50000h–5FFFFh
28000h–2FFFFh
SA6
0
1
1
0
X
X
X
64/32
60000h–6FFFFh
30000h–37FFFh
SA7
0
1
1
1
X
X
X
64/32
70000h–7FFFFh
38000h–3FFFFh
SA8
1
0
0
0
X
X
X
64/32
80000h–8FFFFh
40000h–47FFFh
SA9
1
0
0
1
X
X
X
64/32
90000h–9FFFFh
48000h–4FFFFh
SA10
1
0
1
0
X
X
X
64/32
A0000h–AFFFFh
50000h–57FFFh
SA11
1
0
1
1
X
X
X
64/32
B0000h–BFFFFh
58000h–5FFFFh
SA12
1
1
0
0
X
X
X
64/32
C0000h–CFFFFh
60000h–67FFFh
Document Number: 002-01233 Rev. *A
(x8)
Address Range
(x16)
Address Range
Page 10 of 49
S29AL008D
S29AL008D Top Boot Block Sector Addresses
Address Range (in hexadecimal)
Sector
A18
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
SA13
1
1
0
1
X
X
X
64/32
D0000h–DFFFFh
SA14
1
1
1
0
X
X
X
64/32
E0000h–EFFFFh
70000h–77FFFh
SA15
1
1
1
1
0
X
X
32/16
F0000h–F7FFFh
78000h–7BFFFh
SA16
1
1
1
1
1
0
0
8/4
F8000h–F9FFFh
7C000h–7CFFFh
SA17
1
1
1
1
1
0
1
8/4
FA000h–FBFFFh
7D000h–7DFFFh
SA18
1
1
1
1
1
1
X
16/8
FC000h–FFFFFh
7E000h–7FFFFh
(x8)
Address Range
(x16)
Address Range
68000h–6FFFFh
Note
Address range is A18:A-1 in byte mode and A18:A0 in word mode. See Word/Byte Configuration on page 9.
A18
A17
A16
A15
A14
A13
A12
SA0
0
0
0
0
0
0
X
SA1
0
0
0
0
0
1
0
SA2
0
0
0
0
0
1
SA3
0
0
0
0
1
SA4
0
0
0
1
X
SA5
0
0
1
0
SA6
0
0
1
1
SA7
0
1
0
SA8
0
1
0
Address Range (in hexadecimal)
es
Sector
Sector Size
(Kbytes/
Kwords)
ig
n
S29AL008D Bottom Boot Block Sector Addresses
(x16)
Address Range
16/8
00000h–03FFFh
00000h–01FFFh
8/4
04000h–05FFFh
02000h–02FFFh
1
8/4
06000h–07FFFh
03000h–03FFFh
X
X
32/16
X
X
64/32
X
X
X
64/32
X
X
X
0
X
X
X
1
X
X
X
1
1
0
X
1
1
1
X
ew
rN
04000h–07FFFh
10000h–1FFFFh
08000h–0FFFFh
fo
d
de
64/32
20000h–2FFFFh
10000h–17FFFh
30000h–3FFFFh
18000h–1FFFFh
64/32
40000h–4FFFFh
20000h–27FFFh
64/32
50000h–5FFFFh
28000h–2FFFFh
om
m
en
0
0
08000h–0FFFFh
X
X
64/32
60000h–6FFFFh
30000h–37FFFh
X
X
64/32
70000h–7FFFFh
38000h–3FFFFh
X
X
64/32
80000h–8FFFFh
40000h–47FFFh
X
X
64/32
90000h–9FFFFh
48000h–4FFFFh
ec
SA9
SA10
D
(x8)
Address Range
SA11
1
0
0
0
X
SA12
1
0
0
1
X
SA13
1
0
1
0
SA14
1
0
1
1
SA15
1
1
0
0
SA16
1
1
0
SA17
1
1
SA18
1
1
X
X
64/32
A0000h–AFFFFh
50000h–57FFFh
X
X
X
64/32
B0000h–BFFFFh
58000h–5FFFFh
X
X
64/32
C0000h–CFFFFh
60000h–67FFFh
X
X
X
64/32
D0000h–DFFFFh
68000h–6FFFFh
ot
X
1
N
R
X
1
0
X
X
X
64/32
E0000h–EFFFFh
70000h–77FFFh
1
1
X
X
X
64/32
F0000h–FFFFFh
78000h–7FFFFh
Note
Address range is A18:A-1 in byte mode and A18:A0 in word mode. See Word/Byte Configuration on page 9.
Document Number: 002-01233 Rev. *A
Page 11 of 49
S29AL008D
7.9
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes
output on DQ7–DQ0. This mode is primarily intended for programming equipment to automatically match a device to be
programmed with its corresponding programming algorithm. However, the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9. Address pins A6, A1,
and A0 must be as shown in Table . In addition, when verifying sector protection, the sector address must appear on the appropriate
highest order address bits (see Table on page 10 and Table on page 11). Table shows the remaining address bits that are don’t
care. When all necessary bits are set as required, the programming equipment may then read the corresponding identifier code on
DQ7–DQ0.
ig
n
To access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown
in Table on page 20. This method does not require VID. See Command Definitions on page 15 for details on using the autoselect
mode.
WE#
X
L
L
H
Device ID:
S29AL008D
(Top Boot Block)
Word
L
L
H
Byte
L
L
H
Device ID:
S29AL008D
(Bottom Boot Block)
Word
L
L
H
X
X
L
L
H
L
L
H
X
A6
VID
X
L
X
VID
X
X
VID
L
X
L
A1
A0
L
L
L
X
X
L
L
L
L
de
X
VID
X
L
X
L
H
DQ7
to
DQ0
X
01h
22h
DAh
X
DAh
22h
5Bh
X
5Bh
X
01h (protected)
X
00h
(unprotected)
H
L
ec
Legend
L = Logic Low = VIL
H = Logic High = VIH
SA = Sector Address
X = Don’t care.
Sector Protection/Unprotection
R
7.10
SA
om
m
en
Sector Protection Verification
DQ8
to
DQ15
H
d
Byte
X
A9
A3
to
A2
D
OE#
A5
to
A4
ew
Manufacturer ID: Spansion
CE#
A8
to
A7
rN
Mode
A11
to
A10
fo
Description
A18
to
A12
es
S29AL008D Autoselect Codes (High Voltage Method)
N
ot
The hardware sector protection feature disables both program and erase operations in any sector. The hardware sector unprotection
feature re-enables both program and erase operations in previously protected sectors.
The device is shipped with all sectors unprotected. Spansion offers the option of programming and protecting sectors at its factory
prior to shipping the device through Spansion’s ExpressFlash™ Service. Contact an Spansion representative for details.
It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode on page 12 for details.
Sector Protection/unprotection can be implemented via two methods.
The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via programming equipment.
Figure 7.2 on page 14 shows the algorithms and Figure 15.12 on page 37 shows the timing diagram. This method uses standard
microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector
unprotect write cycle.
The alternate method intended only for programming equipment requires VID on address pin A9 and OE#. This method is
compatible with programmer routines written for earlier 3.0 volt-only Spansion flash devices. Publication number 20536 contains
further details; contact an Spansion representative to request a copy.
Document Number: 002-01233 Rev. *A
Page 12 of 49
S29AL008D
7.11
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is
activated by setting the RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by selecting
the sector addresses. Once VID is removed from the RESET# pin, all the previously protected sectors are protected again.
Figure 7.1 shows the algorithm, and Figure 15.11 on page 37 shows the timing diagrams, for this feature.
Figure 7.1 Temporary Sector Unprotect Operation
START
RESET# = VID
es
ig
n
(Note 1)
ew
fo
rN
RESET# = VIH
D
Perform Erase or
Program Operations
de
d
Temporary Sector
Unprotect Completed
(Note 2)
om
m
en
Notes
1. All protected sectors unprotected.
N
ot
R
ec
2. All previously protected sectors are protected once again.
Document Number: 002-01233 Rev. *A
Page 13 of 49
S29AL008D
Figure 7.2 In-System Sector Protect/Sector Unprotect Algorithms
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
PLSCNT = 1
RESET# = VID
Wait 1 ms
Temporary Sector
Unprotect Mode
No
PLSCNT = 1
RESET# = VID
Wait 1 ms
First Write
Cycle = 60h?
First Write
Cycle = 60h?
No
D
Yes
ew
Set up first sector
address
fo
Wait 15 ms
Protect another
sector?
No
de
om
m
en
Increment
PLSCNT
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
No
Yes
PLSCNT
= 1000?
Yes
Remove VID
from RESET#
Device failed
Write reset
command
Sector Protect
Algorithm
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
ec
ot
R
Yes
N
Device failed
Data = 01h?
Reset
PLSCNT = 1
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
d
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
No
Yes
rN
Wait 150 µs
PLSCNT
= 25?
All sectors
protected?
es
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
No
ig
n
Set up sector
address
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Sector Protect
complete
Temporary Sector
Unprotect Mode
Yes
Yes
Increment
PLSCNT
No
Set up
next sector
address
No
Data = 00h?
Yes
Last sector
verified?
No
Yes
Sector Unprotect
Algorithm
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
Document Number: 002-01233 Rev. *A
Page 14 of 49
S29AL008D
7.12
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent
writes (refer to Table on page 20 for command definitions). In addition, the following hardware data protection measures prevent
accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and
power-down transitions, or from system noise.
7.12.1
Low VCC Write Inhibit
7.12.2
Write Pulse Glitch Protection
Logical Inhibit
D
7.12.3
es
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
ig
n
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC power-up and power-down.
The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored
until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when
VCC is greater than VLKO.
Power-Up Write Inhibit
fo
7.12.4
rN
ew
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle, CE# and WE# must be
a logical zero while OE# is a logical one.
om
m
en
8. Command Definitions
de
d
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal
state machine is automatically reset to reading array data on power-up.
Writing specific address and data commands or sequences into the command register initiates device operations. Table on page 20
defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper
sequence resets the device to reading array data.
Reading Array Data
ot
8.1
R
ec
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE#
or CE#, whichever happens first. Refer to the appropriate timing diagrams in the AC Characteristics on page 30.
N
The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device
is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data
using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data.
After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same
exception. See Erase Suspend/Erase Resume Commands on page 19 for more information on this mode.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes high, or while in the autoselect
mode. See Reset Command on page 16.
See also Requirements for Reading Array Data on page 9 for more information. Table , Read Operations on page 30 provides the
read parameters, and Figure 15.1 on page 30 shows the timing diagram.
Document Number: 002-01233 Rev. *A
Page 15 of 49
S29AL008D
8.2
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command.
The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This
resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is
complete.
The reset command may be written between the sequence cycles in a program command sequence before programming begins.
This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect
mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend).
Autoselect Command Sequence
es
8.3
ig
n
If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also
applies during Erase Suspend).
ew
D
The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether
or not a sector is protected. Table on page 20 shows the address and data requirements. This method is an alternative to that
shown in Table on page 12, which is intended for PROM programmers and requires VID on address bit A9.
fo
rN
The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then
enters the autoselect mode, and the system may read at any address any number of times, without initiating another command
sequence.
om
m
en
de
d
A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h in word mode (or 02h in byte mode)
returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode)
returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table on page 10 and Table on page 11 for valid sector
addresses.
The system must write the reset command to exit the autoselect mode and return to reading array data.
8.4
Word/Byte Program Command Sequence
N
ot
R
ec
The system may program the device by word or byte, depending on the state of the BYTE# pin. Programming is a four-bus-cycle
operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up
command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is
not required to provide further controls or timings. The device automatically provides internally generated program pulses and
verifies the programmed cell margin. Table on page 20 shows the address and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer
latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See Write Operation Status
on page 21 for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a hardware reset immediately
terminates the programming operation. The program command sequence should be reinitiated once the device resets to reading
array data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from a 0 back to a 1.
Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling algorithm to indicate the operation was
successful. However, a succeeding read shows that the data is still 0. Only erase operations can convert a 0 to a 1.
8.5
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program
command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third
write cycle containing the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle unlock
bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the
Document Number: 002-01233 Rev. *A
Page 16 of 49
S29AL008D
unlock bypass program command, A0h; the second cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence,
resulting in faster total programming time. Table shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are valid. To exit the unlock
bypass mode, the system must issue the two-cycle unlock bypass reset command sequence. The first cycle must contain the data
90h; the second cycle the data 00h. Addresses are don’t care for both cycles. The device then returns to reading array data.
Table 8.1 illustrates the algorithm for the program operation. See Erase/Program Operations on page 33 for parameters, and
Figure 15.5 on page 33 for timing diagrams.
Figure 8.1 Program Operation
es
ig
n
START
rN
ew
D
Write Program
Command Sequence
om
m
en
de
d
Embedded
Program
algorithm
in progress
fo
Data Poll
from System
No
Yes
No
Last Address?
N
ot
R
ec
Increment Address
Verify Data?
Yes
Programming
Completed
Note
See Table on page 20 for program command sequence.
Document Number: 002-01233 Rev. *A
Page 17 of 49
S29AL008D
8.6
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a
set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the
Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm
automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these operations. Table on page 20 shows the address and data requirements for
the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip
erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device
returns to reading array data, to ensure data integrity.
ig
n
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write Operation Status
on page 21 for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading
array data and addresses are no longer latched.
Sector Erase Command Sequence
ew
8.7
D
es
Figure 8.2 on page 19 illustrates the algorithm for the erase operation. See Erase/Program Operations on page 33 for parameters,
and Figure 15.6 on page 34 for timing diagrams.
rN
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by
a set-up command. Two additional unlock write cycles are then followed by the address of the sector to be erased, and the sector
erase command. Table on page 20 shows the address and data requirements for the sector erase command sequence.
de
d
fo
The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algorithm automatically
programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings during these operations.
R
ec
om
m
en
After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector
addresses and sector erase commands may be written. Loading the sector erase buffer may be done in any sequence, and the
number of sectors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs,
otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor
interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector
Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system
need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the
device to reading array data. The system must rewrite the command sequence and any additional sector addresses and
commands.
ot
The system can monitor DQ3 to determine if the sector erase timer has timed out. (See DQ3: Sector Erase Timer on page 24.) The
time-out begins from the rising edge of the final WE# pulse in the command sequence.
N
Once the sector erase operation begins, only the Erase Suspend command is valid. All other commands are ignored. Note that a
hardware reset during the sector erase operation immediately terminates the operation. The Sector Erase command sequence
should be reinitiated once the device returns to reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to Write Operation Status
on page 21 for information on these status bits.
Figure 8.2 on page 19 illustrates the algorithm for the erase operation. Refer to Erase/Program Operations on page 33 for
parameters, and to Figure 15.6 on page 34 for timing diagrams.
Document Number: 002-01233 Rev. *A
Page 18 of 49
S29AL008D
8.8
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to,
any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out
period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase
operation or Embedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately
terminates the time-out period and suspends the erase operation. Addresses are don’t-cares when writing the Erase Suspend
command.
When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend
the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends the erase operation.
es
ig
n
After the erase operation is suspended, the system can read array data from or program data to any sector not selected for erasure.
(The device erase suspends all sectors selected for erasure.) Normal read and write timings and command definitions apply.
Reading at any address within erase-suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and
DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See Write Operation Status on page 21 for
information on these status bits.
ew
D
After an erase-suspended program operation is complete, the system can once again read array data within non-suspended
sectors. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard
program operation. See Write Operation Status on page 21 for more information.
fo
rN
The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows
reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See
Autoselect Command Sequence on page 16 for more information.
om
m
en
de
d
The system must write the Erase Resume command (address bits are don’t care) to exit the erase suspend mode and continue the
sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after
the device resumes erasing.
Figure 8.2 Erase Operation
ec
START
N
ot
R
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes
1. See Table on page 20 for erase command sequence.
2. See DQ3: Sector Erase Timer on page 24 for more information.
Document Number: 002-01233 Rev. *A
Page 19 of 49
S29AL008D
Cycles
S29AL008D Command Definitions
Command
Sequence
(Note 1)
Bus Cycles (Notes 2-5)
First
Second
Addr
Data
Read (Note 6)
1
RA
RD
Reset (Note 7)
1
XXX
F0
Word
555
Manufacturer ID
4
Data
Addr
2AA
55
555
Data
90
X00
01
X01
22DA
Word
Byte
AAA
2AA
555
AAA
555
X02
DA
Device ID,
Bottom Boot Block
Word
555
2AA
555
X01
225B
5B
AA
4
55
AA
55
AAA
X02
Word
555
2AA
555
(SA)
X02
AA
555
4
Byte
2AA
Word
3
Byte
55
A0
555
555
Unlock Bypass
555
AA
AAA
AAA
2AA
55
A0
PA
PD
Unlock Bypass Reset (Note 11)
2
XXX
90
XXX
00
(F0)
2AA
AA
Word
555
6
Byte
2AA
AA
AAA
1
Erase Resume (Note 13)
1
XXX
B0
30
555
55
555
555
80
AAA
2AA
AA
AAA
555
55
555
XXX
555
80
AAA
10
AAA
2AA
AA
AAA
55
SA
30
555
ec
Erase Suspend (Note 12)
555
55
555
om
m
en
AAA
Sector Erase
de
555
6
d
XXX
Byte
PD
AAA
2
Word
01
20
555
Unlock Bypass Program (Note 10)
Chip Erase
PA
00
555
AA
AAA
(SA)
X04
AAA
D
555
XX01
rN
Word
Program
90
ew
AAA
55
XX00
es
555
Byte
Data
90
AAA
4
Addr
90
Byte
Sector Protect Verify
(Note 9)
Sixth
Data
AAA
Device ID,
Top Boot Block
4
Addr
ig
n
555
Fifth
Addr
555
AA
AAA
Fourth
Data
fo
Autoselect (Note 8)
Byte
Addr
Third
N
ot
R
Legend
X = Don’t care
RA = Address of the memory location to be read
RD = Data read from location RA during read operation, and
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE# or CE# pulse, whichever happens later.
PD = Data to be programmed at location PA. Data latches on the rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A18–A12 uniquely select any sector.
Notes
1. See Table on page 8 for a description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are write operations.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.
5. Address bits A18–A11 are don’t cares for unlock and command cycles, unless PA or SA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device is in the autoselect mode, or if DQ5 goes high (while the device is providing status data).
8. The fourth cycle of the autoselect command sequence is a read cycle.
9. The data is 00h for an unprotected sector and 01h for a protected sector. See Autoselect Command Sequence on page 16 for more information.
10. The Unlock Bypass command is required prior to the Unlock Bypass Program command.
11. The Unlock Bypass Reset command is required to return to reading array data when the device is in the unlock bypass mode.
12. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid
only during a sector erase operation.
13. The Erase Resume command is valid only during the Erase Suspend mode.
Document Number: 002-01233 Rev. *A
Page 20 of 49
S29AL008D
9. Write Operation Status
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table
on page 25 and the following subsections describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for
determining whether a program or erase operation is complete or in progress. These three bits are discussed first.
9.1
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or completed, or whether
the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the program or erase command
sequence.
es
ig
n
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7
status also applies to programming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs
the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program
address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading
array data.
rN
ew
D
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase algorithm is complete, or if
the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7. This is analogous to the complement/true datum
output described for the Embedded Program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the
device outputs the complement, or 0. The system must provide an address within any of the sectors selected for erasure to read
valid status information on DQ7.
fo
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling on DQ7 is active for
approximately 100 µs, then the device returns to reading array data. If not all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the selected sectors that are protected.
om
m
en
de
d
When the system detects DQ7 changes from the complement to true data, it can read valid data at DQ7–DQ0 on the following read
cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. Figure 15.8,
Data# Polling Timings (During Embedded Algorithms) on page 35, illustrates this.
N
ot
R
ec
Table on page 25 shows the outputs for Data# Polling on DQ7. Figure 9.1 on page 22 shows the Data# Polling algorithm.
Document Number: 002-01233 Rev. *A
Page 21 of 49
S29AL008D
Figure 9.1 Data# Polling Algorithm
START
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
es
DQ5 = 1?
D
No
ig
n
No
ew
Yes
fo
rN
Read DQ7–DQ0
Addr = VA
d
Yes
om
m
en
de
DQ7 = Data?
No
FAIL
PASS
ec
Notes
1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
RY/BY#: Ready/Busy#
N
9.2
ot
R
2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The
RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied together in parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.)
If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby
mode.
Table on page 25 shows the outputs for RY/BY#. Figure 15.1 on page 30, Figure 15.2 on page 31, Figure 15.5 on page 33 and
Figure 15.6 on page 34 shows RY/BY# for read, reset, program, and erase operations, respectively.
9.3
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device
entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse
in the command sequence (prior to the program or erase operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The
system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling.
Document Number: 002-01233 Rev. *A
Page 22 of 49
S29AL008D
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs,
then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the
device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase
Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erasesuspended. Alternatively, the system can use DQ7 (see DQ7: Data# Polling on page 21).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is
written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program algorithm is complete.
DQ2: Toggle Bit II
es
9.4
ig
n
Table on page 25 shows the outputs for Toggle Bit I on DQ6. Figure 9.2 on page 24 shows the toggle bit algorithm. Figure 15.9
on page 36 shows the toggle bit timing diagrams. Figure 15.10 on page 36 shows the differences between DQ2 and DQ6 in
graphical form. See also DQ2: Toggle Bit II on page 23.
ew
D
The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that is, the Embedded
Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE#
pulse in the command sequence.
d
fo
rN
DQ2 toggles when the system reads at addresses within those sectors that were selected for erasure. (The system may use either
OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended.
DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors
are selected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table on page 25 to compare
outputs for DQ2 and DQ6.
9.5
om
m
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de
Figure 9.2 on page 24 shows the toggle bit algorithm in flowchart form, and DQ2: Toggle Bit II on page 23 explains the algorithm.
See also DQ6: Toggle Bit I on page 22. Figure 15.9 on page 36 shows the toggle bit timing diagram. Figure 15.10 on page 36 shows
the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
ot
R
ec
Refer to Figure 9.2 on page 24 for the following discussion. Whenever the system initially begins reading toggle bit status, it must
read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the
value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device completed the program or erase operation. The system can read array data on DQ7–
DQ0 on the following read cycle.
N
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note
whether the value of DQ5 is high (see DQ5: Exceeded Timing Limits on page 23). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer
toggling, the device successfully completed the program or erase operation. If it is still toggling, the device did not completed the
operation successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system
may continue to monitor the toggle bit and DQ5 through successive read cycles, determining the status as described in the previous
paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the operation (top of Figure 9.2 on page 24).
9.6
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time exceeded a specified internal pulse count limit. Under these conditions DQ5
produces a 1. This is a failure condition that indicates the program or erase cycle was not successfully completed.
The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously programmed to 0. Only an
erase operation can change a 0 back to a 1. Under this condition, the device halts the operation, and when the operation exceeds
the timing limits, DQ5 produces a 1.
Document Number: 002-01233 Rev. *A
Page 23 of 49
S29AL008D
Under both these conditions, the system must issue the reset command to return the device to reading array data.
9.7
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an erase operation started.
(The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out
also applies after each additional sector erase command. When the time-out is complete, DQ3 switches from 0 to 1. The system
may ignore DQ3 if the system can guarantee that the time between additional
sector erase commands is always less than 50 µs. See also Sector Erase Command Sequence on page 18.
Figure 9.2 Toggle Bit Algorithm
es
ig
n
START
D
Read DQ7–DQ0
ew
(Note 1)
No
d
fo
Toggle Bit
= Toggle?
rN
Read DQ7–DQ0
om
m
en
de
Yes
No
DQ5 = 1?
Read DQ7–DQ0
Twice
(Notes
1, 2)
Toggle Bit
= Toggle?
No
N
ot
R
ec
Yes
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes
1. Read toggle bit twice to determine whether or not it is toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text.
After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit
I) to ensure the device accepted the command sequence, and then read DQ3. If DQ3 is 1, the internally controlled erase cycle
started; all further commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ3 is 0, the device
accepts additional sector erase commands. To ensure the command is accepted, the system software should check the status of
DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command
might not be accepted. Table shows the outputs for DQ3.
Document Number: 002-01233 Rev. *A
Page 24 of 49
S29AL008D
Write Operation Status
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
DQ7#
Toggle
0
N/A
No toggle
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
0
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Reading within Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
1
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
0
Operation
Standard
Mode
Erase
Suspend
Mode
Embedded Program Algorithm
RY/BY#
Notes
1. DQ5 switches to 1 when an Embedded Program or Embedded Erase operation exceeds the maximum timing limits. See DQ5: Exceeded Timing Limits on page 23 for
more information.
es
ig
n
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
D
10. Absolute Maximum Ratings
Rating
ew
Parameter
Storage Temperature Plastic Packages
–65C to +150C
rN
Ambient Temperature with Power Applied
Voltage with Respect to Ground VCC (Note 1)
fo
A9, OE#, and RESET# (Note 2)
d
All other pins (Note 1)
–0.5 V to +4.0 V
–0.5 V to +12.5 V
–0.5 V to VCC+0.5 V
200 mA
de
Output Short Circuit Current (Note 3)
–65C to +125C
om
m
en
Notes
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to –2.0 V for periods of up to 20 ns. See
Figure 11.1 on page 26. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods
up to 20 ns. See Figure 11.2 on page 26.
2. Minimum DC input voltage on pins A9, OE#, and RESET# is –0.5 V. During voltage transitions, A9, OE#, and RESET# may undershoot VSS to –2.0 V for periods of up
to 20 ns. See Figure 11.1 on page 26. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
N
ot
R
ec
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum
rating conditions for extended periods may affect device reliability.
Document Number: 002-01233 Rev. *A
Page 25 of 49
S29AL008D
11. Operating Ranges
Industrial (I) Devices
Ambient Temperature (TA)
-40°C to +85°C
Extended (N) Devices
Ambient Temperature (TA)
-40°C to +125°C
VCC Supply Voltages
VCC for regulated voltage range+3.0 V to +3.6 V
VCC for full voltage range
+2.7 V to +3.6 V
ig
n
Operating ranges define those limits between which the functionality of the device is guaranteed
20 ns
D
20 ns
es
Figure 11.1 Maximum Negative Overshoot Waveform
ew
+0.8 V
rN
–0.5 V
fo
–2.0 V
de
d
20 ns
om
m
en
Figure 11.2 Maximum Positive Overshoot Waveform
20 ns
VCC
+2.0 V
R
ec
VCC
+0.5 V
20 ns
20 ns
N
ot
2.0 V
Document Number: 002-01233 Rev. *A
Page 26 of 49
S29AL008D
12. DC Characteristics
Parameter
Description
Test Conditions
Min
ILI
Input Load Current
VIN = VSS to VCC,
VCC = VCC max
ILIT
A9 Input Load Current
VCC = VCC max; A9 = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC, VCC = VCC max
ICC1
VCC Active Read Current
(Notes 1, 2)
Max
Unit
1.0
µA
35
µA
1.0
µA
10 MHz
15
30
5 MHz
9
16
1 MHz
2
4
10 MHz
15
30
5 MHz
9
16
1 MHz
2
4
20
ig
n
CE# = VIL, OE# = VIH,
Byte Mode
Typ
mA
ICC2
VCC Active Write Current
(Notes 2, 3, 6)
ICC3
VCC Standby Current (Notes 2, 4)
CE#, RESET# = VCC0.3 V
0.2
5
µA
ICC4
VCC Reset Current (Notes 2, 4)
RESET# = VSS 0.3 V
0.2
5
µA
ICC5
Automatic Sleep Mode
(Notes 2, 4, 5)
VIH = VCC  0.3 V;
VIL = VSS 0.3 V
D
CE# = VIL, OE# = VIH,
Word Mode
0.2
5
µA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
0.7 x VCC
VCC + 0.3
V
VID
Voltage for Autoselect and
Temporary Sector Unprotect
VCC = 3.3 V
11.5
12.5
V
VOL
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min
0.45
V
IOH = –2.0 mA, VCC = VCC min
2.4
IOH = –100 µA, VCC = VCC min
VCC–0.4
om
m
en
Low VCC Lock-Out Voltage
35
es
ew
fo
d
Output High Voltage
VOH2
VLKO
rN
–0.5
de
VOH1
CE# = VIL, OE# = VIH
2.3
mA
V
2.5
V
Notes
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
2. Maximum ICC specifications are tested with VCC = VCCmax.
ec
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. At extended temperature range (>+85°C), typical current is 5µA and maximum current is 10µA.
N
ot
R
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
6. Not 100% tested.
Document Number: 002-01233 Rev. *A
Page 27 of 49
S29AL008D
12.1
Zero Power Flash
Figure 12.1 ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
15
ig
n
10
es
5
0
500
1000
1500
2000
2500
3000
3500
4000
rN
0
ew
D
Supply Current in mA
20
Time in ns
de
d
fo
Note
Addresses are switching at 1 MHz
om
m
en
Figure 12.2 Typical ICC1 vs. Frequency
ec
10
R
ot
3.6 V
6
N
Supply Current in mA
8
2.7 V
4
2
0
1
2
3
4
5
Frequency in MHz
Note
T = 25 C
Document Number: 002-01233 Rev. *A
Page 28 of 49
S29AL008D
13. Test Conditions
Figure 13.1 Test Setup
3.3 V
2.7 k
Device
Under
Test
CL
rN
ew
D
es
ig
n
6.2 k
d
fo
Note
Nodes are IN3064 or equivalent.
de
Test Specifications
55
om
m
en
Test Condition
Output Load
Output Load Capacitance, CL
(including jig capacitance)
Input Rise and Fall Times
Input timing measurement reference levels
30
90
Unit
30
30
100
pF
5
ns
0.0 or VCC
0.5 VCC
V
0.5 VCC
ot
R
Output timing measurement reference levels
70
1 TTL gate
ec
Input Pulse Levels
60
N
14. Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Document Number: 002-01233 Rev. *A
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
Page 29 of 49
S29AL008D
Figure 14.1 Input Waveforms and Measurement Levels
VCC
0.5 VCC
Input
0.5 VCC
Measurement Level
Output
0.0 V
15. AC Characteristics
Read Operations
Parameter
Speed Options
JEDEC
Std
Description
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
Test Setup
55
60
70
90
Min
55
60
70
90
CE# = VIL
OE# = VIL
Max
55
60
70
90
OE# = VIL
tCE
Chip Enable to Output Delay
Max
55
60
70
90
tOE
Output Enable to Output Delay
Max
25
25
30
35
tEHQZ
tDF
Chip Enable to Output High Z (Note 1)
Max
tGHQZ
tDF
Output Enable to Output High Z (Note 1)
Max
Latency Between Read and Write Operations
Min
Read
tOEH
Output Enable
Hold Time (Note 1)
tOH
Output Hold Time From Addresses, CE# or OE#,
Whichever Occurs First (Note 1)
16
ns
20
Min
0
Min
10
Min
0
de
d
Notes
1. Not 100% tested.
rN
Toggle and
Data# Polling
16
fo
tAXQX
es
D
ew
tSR/W
ig
n
tELQV
tGLQV
Unit
om
m
en
2. See Figure 13.1 on page 29 and DC Characteristics on page 27 for test specifications.
Figure 15.1 Read Operations Timings
tRC
Addresses Stable
ec
Addresses
tACC
R
CE#
tDF
tOE
ot
OE#
N
tSR/W
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0V
Document Number: 002-01233 Rev. *A
Page 30 of 49
S29AL008D
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
tREADY
RESET# Pin Low (During Embedded Algorithms) to
Read or Write (See Note)
Test Setup
All Speed Options
Unit
20
µs
Max
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
500
tRP
RESET# Pulse Width
500
tRH
RESET# High Time Before Read (See Note)
tRPD
RESET# Low to Standby Mode
20
µs
tRB
RY/BY# Recovery Time
0
ns
tREADY
ns
50
Min
ig
n
Note
Not 100% tested.
D
es
Figure 15.2 RESET# Timings
CE#, OE#
tRP
om
m
en
tReady
de
RESET#
d
fo
tRH
rN
ew
RY/BY#
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
ec
RY/BY#
ot
R
tRB
N
CE#, OE#
RESET#
tRP
Document Number: 002-01233 Rev. *A
Page 31 of 49
S29AL008D
Word/Byte Configuration (BYTE#)
Parameter
JEDEC
Speed Options
Std
Description
55
tELFL/tELFH
CE# to BYTE# Switching Low or High
Max
tFLQZ
BYTE# Switching Low to Output HIGH Z
Max
tFHQV
BYTE# Switching High to Output Active
Min
60
70
90
70
90
Unit
5
16
55
ns
60
Figure 15.3 BYTE# Timings for Read Operations
ig
n
CE#
es
OE#
ew
D
BYTE#
tELFL
Data Output
(DQ0–DQ14)
fo
rN
DQ0–DQ14
Data Output
(DQ0–DQ7)
Address
Input
DQ15
Output
DQ15/A-1
de
d
BYTE#
Switching
from word
to byte
mode
om
m
en
tFLQZ
tELFH
R
DQ0–DQ14
ot
BYTE#
Switching
from byte to
word mode
ec
BYTE#
N
DQ15/A-1
Data Output
(DQ0–DQ7)
Address
Input
Data Output
(DQ0–DQ14)
DQ15
Output
tFHQV
Document Number: 002-01233 Rev. *A
Page 32 of 49
S29AL008D
Figure 15.4 BYTE# Timings for Write Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS)
tHOLD (tAH)
es
Erase/Program Operations
Speed Options
Description
tAVAV
tWC
Write Cycle Time (Note 1)
tAVWL
tAS
Address Setup Time
tWLAX
tAH
Address Hold Time
tDVWH
tDS
Data Setup Time
tWHDX
tDH
Data Hold Time
tOES
Output Enable Setup Time
d
fo
35
de
tGHWL
55
60
60
Read Recovery Time Before Write
(OE# High to WE# Low)
tCS
CE# Setup Time
tCH
CE# Hold Time
tWLWH
tWP
Write Pulse Width
tWHWL
tWPH
Write Pulse Width High
tSR/W
Latency Between Read and Write Operations
ec
tELWL
tWHEH
tWHWH1
Programming Operation (Note 2)
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
R
tWHWH1
70
90
70
90
35
45
Unit
0
45
35
0
0
ns
Min
om
m
en
tGHWL
55
rN
Std
D
Parameter
JEDEC
ew
15.1
ig
n
Note
Refer to Erase/Program Operations on page 33 for tAS and tAH specifications.
Byte
0
0
0
35
30
20
ns
7
µs
Word
Typ
7
sec
VCC Setup Time (Note 1)
Min
50
µs
tRB
Recovery Time from RY/BY#
Min
0
Program/Erase Valid to RY/BY# Delay
Max
90
tBUSY
N
ot
0.7
tVCS
ns
Notes
1. Not 100% tested.
2. See Erase and Programming Performance on page 39 for more information.
Figure 15.5 Program Operation Timings
Notes
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode
Document Number: 002-01233 Rev. *A
Page 33 of 49
S29AL008D
Read Status Data (last two cycles)
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
555h
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
ig
n
tDS
tD
PD
Status
es
A0h
Data
tRB
ew
RY/BY#
D
tBUSY
DOUT
rN
VCC
fo
tVCS
de
d
Figure 15.6 Chip/Sector Erase Operation Timings
om
m
en
Erase Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data
2AAh
SA
555h for chip erase
VA
tAH
ec
CE#
VA
tCH
R
OE#
ot
tWP
N
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 21).
2. Illustration shows device in word mode.
Document Number: 002-01233 Rev. *A
Page 34 of 49
S29AL008D
Figure 15.7 Back to Back Read/Write Cycle Timing
tWC
Addresses
tRC
PA
RA
PA
tACC
tAH
tCPH
tCE
CE#
PA
tCP
tOE
tSR/W
OE#
tGHWL
tWP
tWDH
tDF
tDS
Data
tOH
tDH
Valid Out
Valid In
Valid Out
rN
ew
D
es
Valid In
ig
n
WE#
fo
Figure 15.8 Data# Polling Timings (During Embedded Algorithms)
Addresses
VA
VA
tCE
om
m
en
CE#
tCH
VA
de
tACC
d
tRC
tOE
OE#
tOEH
tDF
WE#
ec
tOH
DQ7
Complement
True
Valid Data
R
Complement
DQ0–DQ6
RY/BY#
Status Data
True
Valid Data
High Z
N
tBUS
ot
Status Data
High Z
Note
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle
Document Number: 002-01233 Rev. *A
Page 35 of 49
S29AL008D
Figure 15.9 Toggle Bit Timings (During Embedded Algorithms)
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
DQ6/DQ2
tBUS
Valid Status
Valid Status
(first read)
(second read)
Valid Status
Valid Data
(stops toggling)
es
RY/BY#
ig
n
High Z
ew
D
Note
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
Erase Suspend
Read
Erase
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
de
WE#
Enter Erase
Suspend Program
fo
Erase
Suspend
d
Enter
Embedded
Erasing
rN
Figure 15.10 DQ2 vs. DQ6
om
m
en
DQ6
DQ2
R
ec
Note
The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.
Parameter
JEDEC
Std
N
ot
Temporary Sector Unprotect
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
500
ns
tRSP
RESET# Setup Time for Temporary Sector
Unprotect
Min
4
µs
Note
Not 100% tested.
Document Number: 002-01233 Rev. *A
Page 36 of 49
S29AL008D
Figure 15.11 Temporary Sector Unprotect Timing Diagram
12 V
RESET#
0 or 3 V
0 or 3 V
tVIDR
tVIDR
Program or Erase Command Sequence
ig
n
CE#
WE#
D
es
tRSP
rN
ew
RY/BY#
Figure 15.12 Sector Protect/Unprotect Timing Diagram
d
fo
VID
de
VIH
om
m
en
RESET#
SA, A6,
Valid*
A1, A0
Data
CE#
60h
Valid*
Verify
40h
Status
Sector Protect: 150 µs
Sector Unprotect: 15 ms
N
ot
1 µs
R
60h
ec
Sector Protect/Unprotect
Valid*
WE#
OE#
Note
For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Document Number: 002-01233 Rev. *A
Page 37 of 49
S29AL008D
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
JEDEC
Std
tAVAV
tWC
Write Cycle Time (Note 1)
tAVEL
tAS
Address Setup Time
0
tELAX
tAH
Address Hold Time
45
tDVEH
tDS
Data Setup Time
tEHDX
tDH
Data Hold Time
tOES
Output Enable Setup Time
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
0
0
55
60
70
90
55
60
70
90
35
45
35
35
Unit
0
0
Min
tWS
WE# Setup Time
tWH
WE# Hold Time
tELEH
tCP
CE# Pulse Width
tEHEL
tCPH
CE# Pulse Width High
tSR/W
Latency Between Read and Write Operations
ig
n
tWLEL
tEHWH
ns
0
Programming Operation
(Note 2)
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
D
Word
Typ
ew
tWHWH1
Byte
rN
tWHWH1
es
35
Notes
1. Not 100% tested.
20
ns
7
µs
7
0.7
sec
N
ot
R
ec
om
m
en
de
d
2. See Erase and Programming Performance on page 39 for more information.
30
fo
tGHEL
Description
Document Number: 002-01233 Rev. *A
Page 38 of 49
S29AL008D
Figure 15.13 Alternate CE# Controlled Write Operation Timings
555 for program PA for program
SA for sector erase
2AA for erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
tWHWH1 or 2
tWS
es
tCP
tCPH
D
CE#
ig
n
OE#
tBUSY
ew
tDS
tDH
DQ7#
PD for program
30 for sector erase
10 for chip erase
fo
A0 for program
55 for erase
DOUT
d
tRH
rN
Data
om
m
en
de
RESET#
RY/BY#
Notes
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device.
ot
Erase and Programming Performance
Parameter
N
15.2
R
3. Word mode address used as an example.
ec
2. Figure indicates the last two bus cycles of command sequence.
Typ (Note 1)
Max (Note 2)
Unit
Sector Erase Time
0.7
10
s
Chip Erase Time
14
s
Byte Programming Time
7
210
µs
Word Programming Time
7
210
µs
Chip Programming Time
Byte Mode
8.4
25
s
(Note 3)
Word Mode
5.8
17
s
Comments
Excludes 00h programming
prior to erasure
Excludes system level
overhead (Note 5)
Notes
1. Typical program and erase times assume the following conditions: 25C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard
pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program
times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table on page 20 for further information on
command definitions.
6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles.
Document Number: 002-01233 Rev. *A
Page 39 of 49
S29AL008D
Latchup Characteristics
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
Description
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
–100 mA
+100 mA
VCC Current
Note
Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
Test Setup
CIN
Input Capacitance
VIN = 0
COUT
Output Capacitance
CIN2
Control Pin Capacitance
Package
Typ
Max
TSOP, SO
6
7.5
BGA
4.2
TSOP, SO
8.5
VOUT = 0
BGA
TSOP, SO
VIN = 0
12
pF
6.5
7.5
9
3.9
4.7
ew
BGA
5.4
Unit
5.0
es
Parameter Description
D
Parameter Symbol
ig
n
TSOP, SO, and BGA Pin Capacitance
rN
Notes
1. Sampled, not 100% tested.
N
ot
R
ec
om
m
en
de
d
fo
2. Test conditions TA = 25°C, f = 1.0 MHz.
Document Number: 002-01233 Rev. *A
Page 40 of 49
S29AL008D
16. Physical Dimensions
TS 048—48-Pin Standard TSOP
TS/TSR 48
JEDEC
MO-142 (B) DD
MIN
NOM
1.
MAX
R
SYMBOL
NOTES:
---
---
1.20
0.05
---
0.15
A2
0.95
1.00
b1
0.17
N
ot
A
A1
0.20
1.05
b
0.17
0.22
0.27
0.10
---
0.16
c
0.10
---
0.21
D
19.80
20.00
20.20
D1
18.30
18.40
18.50
E
11.90
12.00
12.10
L
0.50 BASIC
0.50
0.60
0˚
---
8
R
0.08
---
0.20
N
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
3.
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
4.
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS
ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
5.
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD
PROTUSION IS 0.15mm (.0059") PER SIDE.
6.
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR
PROTUSION SHALL BE 0.08mm (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT
LEAD TO BE 0.07mm (0.0028").
7.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm (.0039") AND 0.25mm (0.0098") FROM THE LEAD TIP.
8.
LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM
THE SEATING PLANE.
9.
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
0.70
Θ
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14.5M-1982)
2.
0.23
c1
e
ec
PACKAGE
om
m
en
de
d
fo
rN
ew
D
es
ig
n
16.1
48
3641 \ 16-038.10 \ 7.10.7
Note
For reference only. BSC is an ANSI standard for Basic Space Centering.
Document Number: 002-01233 Rev. *A
Page 41 of 49
S29AL008D
16.2
VBK 048—48 Ball Fine-Pitch Ball Grid Array (FBGA) 8.15 x 6.15 mm
0.10 (4X)
D
D1
A
6
5
e
7
4
E
SE
E1
3
2
1
INDEX MARK
10
6
B
F
E
fb
C
SD
f 0.08 M C
TOP VIEW
D
B
A
f 0.15 M C A B
A1 CORNER
7
es
PIN A1
CORNER
G
ig
n
H
SEATING PLANE
0.08 C
C
rN
A1
ew
A
D
BOTTOM VIEW
0.10 C
A2
d
fo
SIDE VIEW
de
NOTES:
PACKAGE
VBK 048
N/A
6.15 mm x 8.15 mm NOM
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.00
A1
0.18
---
---
A2
0.62
---
0.76
8.15 BSC.
NOTE
OVERALL THICKNESS
BALL HEIGHT
6.15 BSC.
5.60 BSC.
E1
4.00 BSC.
MD
8
ROW MATRIX SIZE D DIRECTION
6
ROW MATRIX SIZE E DIRECTION
ot
48
N
fb
BODY SIZE
R
E
N
0.35
---
2. ALL DIMENSIONS ARE IN MILLIMETERS.
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
4.
0.43
BALL FOOTPRINT
BALL FOOTPRINT
TOTAL BALL COUNT
BALL DIAMETER
e
0.80 BSC.
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
---
DEPOPULATED SOLDER BALLS
e
REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
BODY SIZE
D1
ME
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
BODY THICKNESS
ec
D
om
m
en
JEDEC
N IS THE TOTAL NUMBER OF SOLDER BALLS.
6
DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
7
SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3338 \ 16-038.25b
Document Number: 002-01233 Rev. *A
Page 42 of 49
S29AL008D
SO 044—44-Pin Small Outline Package
Dwg rev AC; 10/99
N
ot
R
ec
om
m
en
de
d
fo
rN
ew
D
es
ig
n
16.3
Document Number: 002-01233 Rev. *A
Page 43 of 49
S29AL008D
17. Revision History
Spansion Publication Number: S29AL008D_00
17.1
Revision A (September 8, 2004)
Initial release
17.2
Revision A 1 (February 18, 2005)
Global
ig
n
Updated Trademark
Ordering Information
es
Added Package type designator
D
Valid Combinations
ew
Changed Package Type, Material, and Temperature Range designator
Revision A2 (June 1, 2005)
fo
17.3
rN
Under Package Descriptions, change SSOP to SOP
Global
de
d
Updated status from Advance Information to Preliminary data sheet.
om
m
en
Distinctive Characteristics
Updated manufactured process technology. Updated high performance access time. Added extended temperature range. Added
cycling endurance information.
Production Selector Guide
ec
Added 55 ns speed option and column.
Ordering Information
ot
R
Added tube and tray packing types. Added extended temperature range Added model numbers.
Valid Combinations Table
N
Added speed option. Added packing types. Added model number. Added note for this table.
Operating Range
Added extended temperature range information.
Test Conditions
Added 55ns speed option.
AC Characteristics
Read Operation Table: Added 55ns speed option.
Word/Byte Configuration Table: Added 55 ns speed option.
Erase/Program Operation Table: Added 55ns speed option.
Alternate CE# Controlled Erase/Program Operation Table: Added 55 ns speed option.
Erase and Programming Performance: Changed Byte Programing Time values for Typical and Maximum.
Document Number: 002-01233 Rev. *A
Page 44 of 49
S29AL008D
17.4
Revision A3 (June 16, 2005)
Changed from Preliminary to full Data Sheet. Updated Valid Combinations table.
17.5
Revision A4 (February 16, 2006)
Corrected minor typo on page 1. Added cover page.
17.6
Revision A5 (May 22, 2006)
AC Characteristics
Revision A6 (September 6, 2006)
es
17.7
ig
n
Added tSR/W parameter to read and erase/program operations tables. Added back-to-back read/write cycle timing diagram.
Changed maximum value for tDF and tFLQZ.
D
Global
Revision A7 (October 31, 2006)
rN
17.8
ew
Added 60 ns speed option.
fo
Automatic Sleep Mode
17.9
om
m
en
Changed tBUSY to a maximum value.
de
AC Characteristics, Erase / Program Operations
d
Changed ICC4 to ICC5 in description.
Revision A8 (August 29, 2007)
TS048 Physical dimensions
R
ec
Changed Revision from AA to E: changed degrees (max) from 5 to 8
N
Product Selector Guide
ot
17.10 Revision A9 (September 19, 2007)
Changed TOE for 55ns access speed
Autoselect Codes Table
Changed part references to AL008D
Added A3 to A2 column
Command Definitions Table
Added F0 as an alternative 2nd cycle command for Unlock Bypass Reset
Test Specifications Table
Added CL = 30 pF under 60 ns access speed
Changed Input Pulse Levels, Input and Output timing measurement reference levels
Erase/Program Operations Table
Changed value of Programming Operation for Byte mode
Document Number: 002-01233 Rev. *A
Page 45 of 49
S29AL008D
Alternate CE# Controlled Erase/Program Operations Table
Changed values of Program Operation for both Byte & Word modes
Changed value of Sector Erase Operation
17.11 Revision A10 (November 27, 2007)
Figure: Input Waveforms and Measurement Levels
Updated figure
17.12 Revision A11 (February 27, 2009)
ig
n
Global
es
Added obsolescence information to Cover Sheet, Distinctive Characteristics, and Ordering Information sections of data sheet.
D
Document History Page
Orig. of
Change
**
-
BWHA
Submission
Date
Description of Change
rN
ECN No.
09/08/2004 Initial release
fo
Rev.
ew
Document Title:S29AL008D 8 Mbit (1M x 8-Bit/512 K x 16-Bit), 3 V Boot Sector Flash
Document Number: 002-01233
N
ot
R
ec
om
m
en
de
d
02/18/2005 Global:
Updated Trademark
Ordering Information
Added Package type designator
Valid Combinations
Changed Package Type, Material, and Temperature Range designator
Under Package Descriptions, change SSOP to SOP
Document Number: 002-01233 Rev. *A
Page 46 of 49
S29AL008D
Document History Page (Continued)
Document Title:S29AL008D 8 Mbit (1M x 8-Bit/512 K x 16-Bit), 3 V Boot Sector Flash
Document Number: 002-01233
ECN No.
Orig. of
Change
Submission
Date
Description of Change
06/01/2005 Global
Updated status from Advance Information to Preliminary data sheet.
Distinctive Characteristics
Updated manufactured process technology. Updated high performance
access time. Added extended
temperature range. Added cycling endurance information.
Production Selector Guide
Added 55 ns speed option and column.
Ordering Information
Added tube and tray packing types. Added extended temperature range
Added model numbers.
Valid Combinations Table
Added speed option. Added packing types. Added model number. Added
note for this table.
Operating Range
Added extended temperature range information.
Test Conditions
Added 55ns speed option.AC Characteristics
Read Operation Table: Added 55ns speed option.
Word/Byte Configuration Table: Added 55 ns speed option.
Erase/Program Operation Table: Added 55ns speed option.
Alternate CE# Controlled Erase/Program Operation Table: Added 55 ns
speed option.
Erase and Programming Performance: Changed Byte Programing Time values for Typical and Maximum.
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Rev.
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06/16/2005 Changed from Preliminary to full Data Sheet. Updated Valid Combinations
table.
R
02/16/2006 Corrected minor typo on page 1. Added cover page.
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05/22/2006 AC Characteristics
Added tSR/W parameter to read and erase/program operations tables.
Added back-to-back read/write cycle
timing diagram. Changed maximum value for tDF and tFLQZ.
**
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BWHA
09/06/2006 Global
Added 60 ns speed option.
10/31/2006 Automatic Sleep Mode
Changed ICC4 to ICC5 in description.
AC Characteristics, Erase / Program Operations
Changed tBUSY to a maximum value.
08/29/2007 TS048 Physical dimensions
Changed Revision from AA to E: changed degrees (max) from 5 to 8
Document Number: 002-01233 Rev. *A
Page 47 of 49
S29AL008D
Document History Page (Continued)
Document Title:S29AL008D 8 Mbit (1M x 8-Bit/512 K x 16-Bit), 3 V Boot Sector Flash
Document Number: 002-01233
ECN No.
Orig. of
Change
Submission
Date
Description of Change
09/19/2007 Product Selector Guide
Changed TOE for 55ns access speed
Autoselect Codes Table
Changed part references to AL008D
Added A3 to A2 column
Command Definitions Table
Added F0 as an alternative 2nd cycle command for Unlock Bypass Reset
Test Specifications Table
Added CL = 30 pF under 60 ns access speed
Changed Input Pulse Levels, Input and Output timing measurement
reference levels
Erase/Program Operations Table
Changed value of Programming Operation for Byte mode
Alternate CE# Controlled Erase/Program Operations Table
Changed values of Program Operation for both Byte & Word modes
Changed value of Sector Erase Operation
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BWHA
Figure: Input Waveforms and Measurement Levels
Updated figure
fo
11/27/2007
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Rev.
5043511
BWHA
12/09/2015 Updated to cypress template.
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02/27/2009 Global
Added obsolescence information to Cover Sheet, Distinctive
Characteristics, and Ordering Information
sections of data sheet.
Document Number: 002-01233 Rev. *A
Page 48 of 49
S29AL008D
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
PSoC® Solutions
Automotive..................................cypress.com/go/automotive
psoc.cypress.com/solutions
Clocks & Buffers ................................ cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Interface......................................... cypress.com/go/interface
Cypress Developer Community
Lighting & Power Control............ cypress.com/go/powerpsoc
Community | Forums | Blogs | Video | Training
Memory........................................... cypress.com/go/memory
Technical Support
PSoC ....................................................cypress.com/go/psoc
cypress.com/go/support
ig
n
Touch Sensing .................................... cypress.com/go/touch
USB Controllers....................................cypress.com/go/USB
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Wireless/RF .................................... cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 002-01233 Rev. *A
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Revised December 09, 2015
Page 49 of 49
Cypress , Spansion , MirrorBit , MirrorBit Eclipse™, ORNAND™, EcoRAM™, HyperBus™, HyperFlash™, and combinations thereof, are trademarks and registered trademarks of Cypress
Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their respective holders.
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