XMC1100 AA Errata Sheet

XMC1100 AA Errata Sheet
Errata Sheet
Rel. 1.10, 2015-06
Device
XMC1100
Marking/Step
EES-AA, ES-AA, AA
Package
PG-TSSOP-16/38, PG-VQFN-24/40
Overview
This “Errata Sheet” describes product deviations with respect to the user
documentation listed below.
Table 1
Current User Documentation
Document
Version Date
XMC1100 Reference Manual
V1.1
Apr 2014
XMC1100 Data Sheet
V1.4
May 2014
Make sure that you always use the latest documentation for this device listed in
category “Documents” at http://www.infineon.com/xmc1000.
Notes
1. The errata described in this sheet apply to all temperature and frequency
versions and to all memory size and configuration variants of affected
devices, unless explicitly noted otherwise.
2. Devices marked with EES or ES are engineering samples which may not be
completely tested in all functional and electrical characteristics, therefore
they must be used for evaluation only. The specific test conditions for EES
and ES are documented in a separate “Status Sheet”.
XMC1100, EES-AA, ES-AA, AA
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Errata Sheet
Conventions used in this Document
Each erratum is identified by Module_Marker.TypeNumber:
•
•
•
•
Module: Subsystem, peripheral, or function affected by the erratum.
Marker: Used only by Infineon internal.
Type: type of deviation
– (none): Functional Deviation
– P: Parametric Deviation
– H: Application Hint
– D: Documentation Update
Number: Ascending sequential number. As this sequence is used over
several derivatives, including already solved deviations, gaps inside this
enumeration can occur.
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Errata Sheet
History List / Change Summary
1
History List / Change Summary
Table 2
History List
Version
Date
Remark
1.10
2015-06
Renamed and updated CCU4_AI.002 to
CCU_AI.006 in
Table 3
Errata fixed in this step
Errata
Short Description
Change
- none Functional Deviations
Functional
Deviation
Short Description
XMC1100
Table 4
ADC_AI.003
Additonal bit to enable ADC function
X
ADC_AI.004
ADC Calibration Weakness
X
7
ADC_AI.008
Wait-for-Read condition for register
GLOBRES not detected in continuous
auto-scan sequence
X
8
ADC_AI.010
ADC Operating Range
X
9
ADC_AI.013
Sigma-Delta Loop
X
9
ADC_AI.015
Sporadic Result Errors when Operated
in Low Voltage Range
X
9
ADC_AI.016
No Channel Interrupt in Fast Compare
Mode with GLOBRES
X
10
CCU_AI.005
CCU4 and CCU8 External IP clock Usage X
10
CCU_AI.006
Value update not usable in period dither X Upd 12
mode
ated
XMC1100, EES-AA, ES-AA, AA
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Chg Pg
7
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Errata Sheet
History List / Change Summary
Functional Deviations (cont’d)
Functional
Deviation
Short Description
XMC1100
Table 4
CPU_CM.002
Watchpoint PC functions can report
false execution
X
12
CPU_CM.003
Prefetch faulting instructions can
erroneously trigger breakpoints
X
14
Firmware_CM.001 User routine _NvmProgVerify stalls the X
system bus for two to three maximum 10
µs periods
14
Firmware_CM.002 Calculate Target Level for Temperature X
Comparison User Routine returns zero
for valid temperature input parameter
15
NVM_CM.001
NVM Write access to trigger NVM erase X
operation must NOT be executed from
NVM
15
NVM_CM.002
Completion of NVM verify-only
X
operations do not trigger NVM interrupt
16
PORTS_CM.004
Outputs of CCU4, BCCU and ACMP
X
cannot be used to effectively control the
pull devices on Pin
16
SCU_CM.010
Handling of Master Reset via bit
RSTCON.MRSTEN
X
17
SCU_CM.011
Incomplete Initialisation after a System
Reset
X
17
SCU_CM.012
Calibrating DCO based on Temperature X
Sensor
17
SCU_CM.013
Brownout reset triggered by External
Brownout Detector (BDE)
X
18
SCU_CM.016
Usage of Offset Formulae for DCO
Calibration based on Temperature
X
18
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Errata Sheet
History List / Change Summary
Table 4
Functional Deviations (cont’d)
Short Description
SCU_CM.018
Accuracy of Temperature Sensor out of X
specification
19
SCU_CM.020
DCO nominal frequencies and accuracy X
based on Temperature Sensor
calibration
20
USIC_AI.014
No serial transfer possible while
running capture mode timer
X
21
USIC_AI.017
Clock phase of data shift in SSC slave
cannot be changed
X
21
USIC_AI.018
Clearing PSR.MSLS bit immediately
deasserts the SELOx output signal
X
21
Chg Pg
Chg Pg
Application Hints
Hint
Short Description
XMC1100
Table 5
XMC1100
Functional
Deviation
ADC_AI.H006
Ratio of Module Clock to Converter
Clock
X
23
ADC_AI.H007
Ratio of Sample Time tS to SHS Clock
fSH
X
23
ADC_AI.H009
ADC Operation with internal reference, X
lower supply voltage range
25
X
25
Firmware_CM.H002 Ensuring correct selection of RxD Pin X
in ASC Bootstrap Loader
27
Firmware_CM.H001 Switching to high baudrates in
enhanced ASC BSL
XMC1100, EES-AA, ES-AA, AA
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Errata Sheet
History List / Change Summary
Application Hints (cont’d)
Chg Pg
Hint
Short Description
XMC1100
Table 5
NVM_CM.H001
Adding a wait loop to stand-alone
verification sequences
X
28
SCU_CM.H001
Temperature Sensor Functionality
X
28
USIC_AI.H004
I2C slave transmitter recovery from
deadlock situation
X
29
Hint
Documentation Updates
Short Description
XMC1100
Table 6
Chg Pg
Firmware_CM.D001 Incorrect specification of length of
Chip Variant Identification Number
X
30
Firmware_CM.D002 Incorrect specification of value of
Status Indicators returned by NVM
routines
X
30
XMC1100, EES-AA, ES-AA, AA
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Errata Sheet
Functional Deviations
2
Functional Deviations
The errata in this section describe deviations from the documented functional
behavior.
ADC_AI.003 Additonal bit to enable ADC function
The analog section of ADC is not fully functioning when it is enabled by bit
SHSCFG.ANOFF.
Workaround
To enable the analog section of the ADC, write value 00000001H to register
address 40010500H in addition to the setup as mentioned above.
ADC_AI.004 ADC Calibration Weakness
The calibration mechanisms of the ADC show a problem with the offset
calibration.This leads to inaccurate result values and, therefore, requires
additional actions.
Workaround
Additional actions are recommended for ADC initialization and during
operation.
During ADC initialization and before start of calibration, the following sequence
is required:
•
•
•
•
Enable Analog Converter to normal mode, SHS0_SHSCFG.ANOFF = 0
Wait until Converter has turned on, SHS0_SHSCFG.ANRDY = 1
Add approximately 15 µsec for the ADC power to stabilize
Configure the sample and conversion time
Next, trigger the startup calibration and gain calibration loop:
•
Startup Calibration
a) Initiate start up calibration, GLOBCFG.SUCAL = 1
b) Disable Post calibration, GLOBCFG.DPCAL0 = 1
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Errata Sheet
Functional Deviations
•
c) Clear offset calibration values1) for 1920 calibration cycles while waiting
for start-up calibration to finish
Gain calibration workaround loop
a) Set calibration maximum timing by writing 3F100400H to register address
480340BCH
b) Setup group 0 channel for conversion.
c) Enable post calibration for group 1 and group 0, GLOBCFG.DPCAL1 =
GLOBCFG.DPCAL0 = 0
d) Clear offset calibration values.1)
e) Execute 9 x 2000 dummy conversions and clear offset calibration
values1) after each conversion.
f) Clear offset calibration values1) while waiting for the post calibration loop
to finish, SHS0_SHSCFG.STATE = 0
g) Reset the configuration used for dummy conversion.
After the end of the gain calibration workaround loop, configure the ADC for
user application.
During runtime:
•
•
Since a post calibration cycle is executed automatically after each
conversion cycle, it is sufficient to clear offset values1) after retrieving a
result value.
Calibration steps are automatically inserted when no conversions are
executed. To avoid miscalibration, ensure that the offset values are
cleared1) before a lapse of 1024 µs.
ADC_AI.008 Wait-for-Read condition for register GLOBRES not detected
in continuous auto-scan sequence
In the following scenario:
•
•
A continuous auto-scan is performed over several ADC groups and
channels by the Background Scan Source, using the global result register
(GLOBRES) as result target, and
The Wait-for-Read mode for GLOBRES is enabled (GLOBCR.WFR=1B),
1) Offset calibration values are cleared by writing value 00008000H to register
addresses 480340E0H and 480340E4H.
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Errata Sheet
Functional Deviations
each conversion of the auto-scan sequence has to wait for its start until the
result of the previous conversion has been read out of GLOBRES.
When the last channel of the auto-scan is converted and its result written to
GLOBRES, the auto-scan re-starts with the highest channel number of the
highest ADC group number. But the start of this channel does not wait until the
result of the lowest channel of the previous sequence has been read from
register GLOBRES, i.e. the result of the lowest channel may be lost.
Workaround
None.
ADC_AI.010 ADC Operating Range
ADC operation at 3.5 V to 5.5 V is covered by production test. Other range is
not yet covered by production test. Gain error may increase at 3.0 V to 3.5 V
and 1.8 V to 2.2 V.
Workaround
None.
ADC_AI.013 Sigma-Delta Loop
The sigma-delta loop does not operate as specified and, therefore, cannot be
used.
Workaround
None.
ADC_AI.015 Sporadic Result Errors when Operated in Low Voltage Range
When the ADC is operated in low voltage range (SHSCFG.AREF = 11B, internal
reference), the result values may be sporadically inaccurate.
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Errata Sheet
Functional Deviations
Workaround
Attenuate the noise created by these inaccurate results by averaging several
result values or using a filter. A median filter is suitable.
ADC_AI.016 No Channel Interrupt in Fast Compare Mode with GLOBRES
In fast compare mode, the compare value is taken from bitfield RESULT of the
global result register GLOBRES and the result of the comparison is stored in
the respective bit FCR.
The channel event indicating that the input becomes higher or lower than the
compare value, is not generated.
The comparison is executed correctly, the target bit is stored correctly, source
events and result events are generated.
Workaround
The result bit FCR can be evaluated if the input is higher or lower than the
compare value.
CCU_AI.005 CCU4 and CCU8 External IP clock Usage
Each CCU4/CCU8 module offers the possibility of selecting an external signal
to be used as the master clock for every timer inside the module Figure 1.
External signal in this context is understood as a signal connected to other
module/IP or connected to the device ports.
The user has the possibility after selecting what is the clock for the module
(external signal or the clock provided by the system), to also select if this clock
needs to be divided. The division ratios start from 1 (no frequency division) up
to 32768 (where the selected timer uses a frequency of the selected clock
divided by 32768).
This division is selected by the PSIV field inside of the CC4yPSC/CC8yPSC
register. Notice that each Timer Slice (CC4y/CC8y) have a specific PSIV field,
which means that each timer can operate in a different frequency.
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Errata Sheet
Functional Deviations
Currently is only possible to use an external signal as Timer Clock when a
division ratio of 2 or higher is selected. When no division is selected (divided by
1), the external signal cannot be used.
The user must program the PSIV field of each Timer Slice with a value different
from 0000B - minimum division value is /2.
This is only applicable if the Module Clock provided by the system (the normal
default configuration and use case scenario) is not being used. In the case that
the normal clock configured and programmed at system level is being used,
there is not any type of constraints.
One should not also confuse the usage of an external signal as clock for the
module with the usage of an external signal for counting. These two features
are completely unrelated and there are not any dependencies between both.
CCU4/CCU8
Module External
Signals
Module clock
from the system
/1
/2
Prescaler
CC40/CC80
...
...
Timer clock
CC4/80PSC.PSIV
/16384
/32768
CC41/CC81
...
Timer clock
CC4/81PSC.PSIV
CC42/CC82
...
Timer clock
CC4/82PSC.PSIV
CC43/CC83
...
Timer clock
CC4/83PSC.PSIV
Figure 1
Clock Selection Diagram for CCU4/CCU8
XMC1100, EES-AA, ES-AA, AA
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Errata Sheet
Functional Deviations
Workaround
None.
CCU_AI.006 Value update not usable in period dither mode
Each CCU4/CCU8 timer gives the possibility of enabling a dither function, that
can be applied to the duty cycle and/or period. The duty cycle dither is done to
increase the resolution of the PWM duty cycle over time. The period dither is
done to increase the resolution of the PWM switching frequency over time.
Each of the dither configurations is set via the DITHE field:
•
•
•
•
DITHE = 00B - dither disabled
DITHE = 01B - dither applied to the duty-cycle (compare value)
DITHE = 10B - dither applied to the period (period value)
DITHE = 11B - dither applied to the duty-cycle and period (compare an
period value)
Whenever the dither function is applied to the period (DITHE = 10B or DITHE =
11B ) and an update of the period value is done via a shadow transfer, the timer
can enter a stuck-at condition (stuck at 0).
Implication
Period value update via shadow transfer cannot be used if dither function is
applied to the period (DITHE programmed to 10B or 11B ).
Workaround
None
CPU_CM.002 Watchpoint PC functions can report false execution
In the presence of interrupts including those generated by the SVC instruction,
it is possible for both the data watchpoint unit's PC match facility and PC
sample-register to operate as though the instruction immediately following the
interrupted or SVC instruction had been executed.
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Errata Sheet
Functional Deviations
Conditions
Either:
1.
2.
3.
4.
5.
Halting debug is enabled via C_DEBUGEN = 1
Watchpoints are enabled via DWTENA = 1
A watchpoint is configured for PC sampling DWT_FUNCTION = 0x4
The same watchpoint is configured to match a `target instruction`
And either:
a) The `target instruction` is interrupted before execution, or
b) The `target instruction` is preceded by a taken SVC instruction
6. The DWT will unexpectedly match the `target instruction`
7. The processor will unexpectedly enter debug state once inside the
exception handler
Or:
1. The debugger performs a read access to the DWT_PCSR
2. A `non-committed instruction` is preceded by a taken SVC instruction
3. The DWT_PCSR value unexpectedly matches the `non-committed
instruction`
Implications
If halting debug is enabled and PC match watchpoints are being used, then
spurious entry into halted debug state may occur under the listed conditions.
If the DWT_PCSR is being used for coarse grain profiling, then it is possible that
the results can include hits for the address of an instruction immediately after
an SVC instruction, even if said instruction is never executed.
Workaround
This errata does not impact normal execution of the processor.
A debug agent may choose to handle the infrequent false positive Debug state
entry and erroneous PCSR values as spurious events.
XMC1100, EES-AA, ES-AA, AA
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Errata Sheet
Functional Deviations
CPU_CM.003
breakpoints
Prefetch faulting instructions can erroneously trigger
External prefetch aborts on instruction fetches on which a BPU breakpoint has
been configured, will cause entry to Debug state. This is prohibited by revision
C of the ARMv6-M Architecture Reference Manual. Under this condition, the
breakpoint should be ignored, and the processor should instead service the
prefetch-abort by entering the HardFault handler.
Conditions
1. Halting debug is enabled via CDEBUG_EN == '1'
2. A BPU breakpoint is configured on an instruction in the first 0.5GB of
memory
3. The fetch for said instruction aborts via an AHB Error response
4. The processor will erroneously enter Debug state rather than entering
HardFault.
Implications
If halting debug is enabled and a BPU breakpoint is placed on an instruction
with faults due to an external abort, then a non-compliant entry to Debug state
will occur.
Workaround
This errata does not impact normal execution of the processor.
A debug agent may choose to avoid placing BPU breakpoints on addresses that
generate AHB Error responses, or may simply handle the Debug state entry as
a spurious debug event.
Firmware_CM.001 User routine _NvmProgVerify stalls the system bus for
two to three maximum 10 µs periods
The user routine “Erase, Program and Verify Flash Page” (_NvmProgVerify) in
the Boot ROM stalls the system bus for two to three periods, the duration of
each period being maximum 10 µs. The bus stall is the result of accessing the
NVM while NVM is busy.
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Errata Sheet
Functional Deviations
During these periods when the bus is stalled, any interrupts generated will be
delayed until the bus becomes available again. This is the case even for
interrupts that have their handlers located in the SRAM, since all memory
accesses have to go through the system bus.
Workaround
None.
Firmware_CM.002 Calculate Target Level for Temperature Comparison
User Routine returns zero for valid temperature input parameter
In Calculate Target Level for Temperature Comparison User Routine in
Firmware, the temperature sensor threshold value is expected to be returned
for a valid range of temperature input parameter of 233K to 388K. This user
function typically returns zero value for input parameter out of the valid range,
also for some input parameters within the valid range.
Workaround
If user function returns zero for input parameter within the valid range, increase
or decrease the input parameter by 1 degree Kelvin in order to use this user
function.
NVM_CM.001 NVM Write access to trigger NVM erase operation must
NOT be executed from NVM
When the NVM write access to trigger an NVM erase operation is executed
from NVM, the erase operation is not always executed.
Implications
This issue only affects the NVM operation ERASE. The remaining NVM
operations WRITE and VERIFY are not affected.
XMC1100, EES-AA, ES-AA, AA
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Errata Sheet
Functional Deviations
Workaround
When implementing the Low-Level Programming Routines, the programmer
has to take care that the write access to the NVM that is triggering the ERASE
operation is not executed from NVM.
It is recommended to use always the NVM user routines provided in the ROM,
especially for NVM erase.
NVM_CM.002 Completion of NVM verify-only operations do not trigger
NVM interrupt
The completion of either one-shot or continuous verify-only operation
(NVMPROG.ACTION = D0H or E0H respectively) does not trigger the NVM
interrupt, contrary to specifications.
Implications
The NVM interrupt cannot be used to detect for the end of verify-only
operations.
Workaround
To detect for the end of verify-only operations, poll the register bit
NVMSTATUS.BUSY to be 0 after the specific verify-only operation has started.
PORTS_CM.004 Outputs of CCU4, BCCU and ACMP cannot be used to effectively control the pull devices on Pin
The outputs of BCCU0.OUTx, CCU40.OUTx and ACMPx.OUT can be used to
control the internal pull devices via the direct hardware control in the PORTS
module.
The intended behaviour is:
•
•
When output is `1`, pull-up device is enable and pull-down device is disable
When output is `0`, pull-up device is disable and pull-down device is enable
The actual behaviour is:
•
When output is `1`, pull-up device is enable and pull-down device is enable
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Errata Sheet
Functional Deviations
•
When output is `0`, pull-up device is disable and pull-down device is disable
Workaround
None
SCU_CM.010 Handling of Master Reset via bit RSTCON.MRSTEN
The reset initialisation sequence is incomplete when a Master Reset via bit
RSTCON.MRSTEN is triggered after a System Reset while some
RSTSTAT.RSTSTAT bit(s) indicating System reset - one or more out of bits
[9:2] - is still set.
Workaround
Clear the reset status bits in RSTSTAT.RSTSTAT
RSTCLR.RSCLR to 1 before triggering the Master Reset.
by
setting
bit
SCU_CM.011 Incomplete Initialisation after a System Reset
The reset initialisation is incomplete when a System Reset is triggered on
devices with Firmware version : FFFFFFFFH. The Firmware version is stored in
Flash Configuration Sector 0 (CS0), address 10000FECH .
The issue is solved for devices with a different Firmware version than
FFFFFFFFH.
Workaround
When a System Reset happens, it is recommended to trigger the Master Reset
via bit RSTCON.MRSTEN after clearing the reset status bits in
RSTSTAT.RSTSTAT via bit RSTCLR.RSCLR.
SCU_CM.012 Calibrating DCO based on Temperature Sensor
The function of calibrating DCO based on temperature is not supported in EES
and ES samples.
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Errata Sheet
Functional Deviations
Workaround
None.
SCU_CM.013 Brownout reset triggered by External Brownout Detector
(BDE)
Samples with the following marking and Firmware version does not support the
BDE brownout detection.
•
•
Package marking of GE247, GE248 or GE249
Firmware version : FFFFFFFFH (stored in CS0, address 10000FECH)
The brownout reset may not be triggered when VDDP drops below the VDDP
brownout reset voltage.
Workaround
None.
SCU_CM.014 Temperature Sensor User Routines in ROM
The Temperature sensor user routines in ROM cannot be used.
Workaround
Library functions are available and the details of these functions can be found
in the Temperature Sensor device guide.
SCU_CM.016 Usage of Offset Formulae for DCO Calibration based on
Temperature
In the productive device, DCO1 can be calibrated based on the measured
temperature using the temperature sensor(TSE). The offset value for the
calibration can be obtained based on the formulae below. The 4 constants are
stored in the flash configuration page, where constant d and e may have the
values of 0.
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Errata Sheet
Functional Deviations
(1)
(a – b)(c – d)
OFFSET [ steps ] = b + --------------------------------(e – d)
where :
OFFSET value is range from 0 to 8
c is the measured temperature [°C]
a is constant DCO_ADJLO_T2
b is constant DCO_ADJLO_T1
d is constant ANA_TSE_T1
e is constant ANA_TSE_T2
Workaround
If constant d is 0, set d to 25 in the formulae above. If constant e is 0, set e to
115, respectively.
SCU_CM.018 Accuracy of Temperature Sensor out of specification
The temperature sensor accuracy parameter TTSAL, does not fall within the
defined limits for the corresponding test conditions in the Temperature Sensor
Characteristics table in XMC1000 family Data Sheet V1.4. The deviation of the
accuracy is specified in Table 7.
Note: The abovementioned deviation does not affect the functionality of the
DCO1 calibration based on temperature sensor.
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Functional Deviations
Table 7
Temperature Sensor Characteristics
Parameter Parameter Values
Symbol
Sensor
Accuracy
TTSAL CC
Unit Test conditions
Min
Typ.
Max
-6
–
6
°C
-10
–
10
°C
−
+/-12
–
°C
−
+/-20
–
°C
TJ = 25°C,
TJ = 70°C,
TJ = 115°C
TJ = 0°C
TJ = -25°C
TJ = -40°C
Workaround
None.
SCU_CM.020 DCO nominal frequencies and accuracy based on Temperature Sensor calibration
The accuracy of DCO1 based on temperature sensor calibration parameter
ΔfLTT of the 64MHz DCO1 Characteristics table in XMC1000 family Data Sheet
V1.4 is not valid.
The min and max limits for fNOM of DCO1 and DCO2 under nominal conditions
after trimming are not valid. These limits are defined by the specified accuracy
parameter over temperature ΔfLT.
Workaround
To improve the accuracy of the DCO1 oscillator, refer to XMC1000 Oscillator
Handling Application Note.
XMC1100, EES-AA, ES-AA, AA
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Functional Deviations
USIC_AI.014 No serial transfer possible while running capture mode timer
When the capture mode timer of the baud rate generator is enabled
(BRG.TMEN = 1) to perform timing measurements, no serial transmission or
reception can take place.
Workaround
None.
USIC_AI.017 Clock phase of data shift in SSC slave cannot be changed
Setting PCR.SLPHSEL bit to 1 in SSC slave mode is intended to change the
clock phase of the data shift such that reception of data bits is done on the
leading SCLKIN clock edge and transmission on the other (trailing) edge.
However, in the current implementation, the feature is not working.
Workaround
None.
USIC_AI.018 Clearing PSR.MSLS bit immediately deasserts the SELOx
output signal
In SSC master mode, the transmission of a data frame can be stopped explicitly
by clearing bit PSR.MSLS, which is achieved by writing a 1 to the related bit
position in register PSCR.
This write action immediately clears bit PSR.MSLS and will deassert the slave
select output signal SELOx after finishing a currently running word transfer and
respecting the slave select trailing delay (Ttd) and next-frame delay (Tnf).
However in the current implementation, the running word transfer will also be
immediately stopped and the SELOx deasserted following the slave select
delays.
XMC1100, EES-AA, ES-AA, AA
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Functional Deviations
If the write to register PSCR occurs during the duration of the slave select
leading delay (Tld) before the start of a new word transmission, no data will be
transmitted and the SELOx gets deasserted following Ttd and Tnf.
Workaround
There are two possible workarounds:
•
•
Use alternative end-of-frame control mechanisms, for example, end-offrame indication with TSCR.EOF bit.
Check that any running word transfer is completed (PSR.TSIF flag = 1)
before clearing bit PSR.MSLS.
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Errata Sheet
Application Hints
3
Application Hints
The errata in this section describe application hints which must be regarded to
ensure correct operation under specific application conditions.
ADC_AI.H006 Ratio of Module Clock to Converter Clock
For back-to-back conversions, the ratio between the module clock fADC and the
converter clock fSH must meet the limits listed in Table 8.
Otherwise, when the internal bus clock fADC = fMCLK is too slow in relation to the
converter clock fSH, the internal result buffer may be overwritten with the result
of the next conversion c2 before the result of the previous conversion c1 has
been transferred to the specified result register.
Table 8
VADC: Ratio of Module Clock to Converter Clock
Conversion Type
fADC / fSH
(min.)
Example for fSH = fCONV = 32 MHz
(SHS0_SHSCFG.DIVS = 0)
10-bit Fast Compare
Mode (bitfield CMS /
CME = 101B)
3/7
fADC = fMCLK > 13.72 MHz
Other Conversion
Modes (8/10/12-bit)
1/3
fADC = fMCLK > 10.67 MHz
ADC_AI.H007 Ratio of Sample Time tS to SHS Clock fSH
The sample time tS is programmable to the requirements of the application.
To ensure proper operation of the internal control logic, tS must be at least four
cycles of the prescaled converter clock fSH, i.e. tS ≥ 4 tCONV x (DIVS+1).
(1) With SHS*_TIMCFGx.SST > 0, the sample time is defined by
tS = SST x tADC.
In this case, the following relation must be fulfilled:
•
SST ≥ 4 x tCONV/tADC x (DIVS+1), i.e. SST ≥ 4 x fADC/fCONV x (DIVS+1).
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Application Hints
– Example:
with the default setting DIVS=0 and fADC = fMCLK = 32 MHz, fSH = fCONV =
32 MHz (for DIVS = 0):
select SST ≥ 4.
(2) With SHS*_TIMCFGx.SST = 0, the sample time is defined by
tS = (2+STC) x tADCI, with tADCI = tADC x (DIVA+1)
In this case, the following relation must be fulfilled:
•
[(2+STC) x (DIVA+1)] / (DIVS+1) ≥ 4 x tCONV/tADC = 4 x fADC/fCONV.
– Example:
With the default settings STC=0, DIVA=1, DIVS=0 and fADC = fMCLK =
32 MHz, fSH = fCONV = 32 MHz (for DIVS = 0),
this relation is fulfilled.
Note: In addition, the condition fADC = fMCLK ≥ 0.55 fSH must be fulfilled.
Note that this requirement is more restrictive than the requirement in
ADC_AI.H006.
Definitions
DIVA: Divider Factor for the Analog Internal Clock, resulting from bit field
GLOBCFG.DIVA (range: 1..32D)
DIVS: Divider Factor for the SHS
SHS*_SHSCFG.DIVS (range: 1..16D)
Clock,
resulting
from
bit
field
STC: Additional clock cycles, resulting from bit field STCS/STCE in registers
GxICLASS*, GLOBICLACSSy (range: 0..256D)
SST: Short Sample Time factor, resulting from bit field SHS*_TIMCFGx.SST
(range: 1..63D)
Recommendation
Select the parameters such that the sample time tS is at least four cycles of the
prescaled converter clock fSH, as described above.
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Application Hints
ADC_AI.H009 ADC Operation with internal reference, lower supply voltage range
If the internal reference is used in the lower voltage range, write value 0CH to
the second byte of register address 480340BCH.
Firmware_CM.H001 Switching to high baudrates in enhanced ASC BSL
The ASC Bootstrap Loader allows the user to switch to baudrates higher than
the initial baudrate when the communication is established for faster
downloading of code/data.
With the current implementation (refer to the “Bootstrap Loaders and User
Routines” chapter in Reference Manual) the host device (e.g. a PC) may have
problem to switch the baudrate fast enough after sending the request
(BSL_STEP as of Figure 2) and is not able to receive the device acknowledge
(BSL_BR_OK) correctly with the changed ASC channel speed. If this happens,
the host will get some error condition - wrong response, start bit not detected,
etc. In such a case the host has to ignore the error and send the trailer Byte
(BSL_BR_OK) with the new baudrate. The correctness of the communication
speed settings will be then decided by the host upon the response from the
device after sending the length of code for downloading (refer to Figure 3).
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Errata Sheet
Application Hints
Listening
1-to-0 transition
on RXD
Starts BR
detection (Receive
zero byte)
0-to-1 transition
on RXD
Configure
fractional divider
Receive header
byte
Header byte =
BSL_ASC_F/H?
No
Header byte =
BSL_ENC_F/H?
No
Yes
Yes
Send BSL_ENC_ID and
BSL_PDIV
Send BSL_ID
Receive BSL_STEP
Reconfigure fractional divider
and send BSL_BR_OK
Receive trailer byte
Yes
Trailer byte =
BSL_BR_OK?
No
Request a system reset
Install AIRCR.SYSRESETREQ:=1
Proceed with main
BSL download
sequence
System reset –
new SSW execution
XMC1000-SBSL BR detection flow.vsd
Figure 2
Baud Rate configuration sequence during ASC BSL entry
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Application Hints
Host
BSL
4 Length Bytes (LSB first)
BSL_OK
Application program
stream
BSL_OK
Sunny day sequence
Host
SSW
4 Length Bytes (LSB first)
BSL_NOK
Rainy day sequence
ASC BSL Application Download .vsd 06.06.12
Figure 3
Standard ASC BSL: Application download protocol
Firmware_CM.H002 Ensuring correct selection of RxD Pin in ASC Bootstrap Loader
To provide flexible usage in application, USIC0 channel 0 or 1 are both checked
automatically as ASC Bootstrap Loader channel. To prevent possible
misidentification of an ASC BSL on the wrong RxD pin, the application must
ensure that only the intended pin is activated.
For example, having a capacitor on the pin of an unintended ASC BSL channel,
may result in a ramping signal and false detection as the selected ASC BSL
channel. Connecting a capacitor to P0.14 when P1.3 is the intended channel,
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Errata Sheet
Application Hints
or to P1.3 when P0.14 is the intended channel, must be avoided when using the
ASC Bootstrap Loader.
NVM_CM.H001 Adding a wait loop to stand-alone verification sequences
When a hardread level (NVMCONF.HRLEV = 01B or 10B) is selected for a
stand-alone verification sequence (NVMPROG.ACTION.VERIFY = 11B),
memory reads from the cell array and register write accesses should be
avoided during the transition from VerifyWait to RIdleV state for up to 10 µs,
else a bus stall will occur. The NVMSTATUS.BUSY bit remains cleared during
this time.
Therefore, it is recommended to insert a wait loop of 10 µs following the
completion of the verify sequence, before any write access to SFRs or
read/write access to cell array.
Alternatively, if the verify operation is intended following a write operation, it is
recommended to use the write operation with automatic verify
(NVMPROG.ACTION = 51H or 61H), instead of the stand-alone write and verify
operations. In this case, the BUSY bit always indicate the actual NVM status
and no wait loop will be necessary.
SCU_CM.H001 Temperature Sensor Functionality
EES samples are not temperature tested, therefore the temperature sensor
functionality is not supported.
Workaround
None
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Application Hints
USIC_AI.H004 I2C slave transmitter recovery from deadlock situation
While operating the USIC channel as an IIC slave transmitter, if the slave runs
out of data to transmit before a master-issued stop condition, it ties the SCL
infinitely low.
Recommendation
To recover and reinitialize the USIC IIC slave from such a deadlock situation,
the following software sequence can be used:
1. Switch the SCL and SDA port functions to be general port inputs for the
slave to release the SCL and SDA lines:
a) Write 0 to the two affected Pn_IOCRx.PCy bit fields.
2. Flush the FIFO buffer:
a) Write 1B to both USICx_CHy_TRBSCR.FLUSHTB and FLUSHRB bits.
3. Invalidate the internal transmit buffer TBUF:
a) Write 10B to USICx_CHy_FMR.MTDV.
4. Clear all status bits and reinitialize the IIC USIC channel if necessary.
5. Reprogram the Pn_IOCRx.PCy bit fields to select the SCL and SDA port
functions.
At the end of this sequence, the IIC slave is ready to communicate with the IIC
master again.
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Errata Sheet
Documentation Updates
4
Documentation Updates
The errata in this section contain updates to or completions of the user
documentation. These updates are subject to be taken over into upcoming user
documentation releases.
Firmware_CM.D001 Incorrect specification of length of Chip Variant Identification Number
In Flash data for SSW and user SW in XMC1100 Table of Reference Manual
v1.1, the length of Chip Variant Identification is incorrectly specified as 28B
starting from 1000’0F04H.
Documentation Update
The length of Chip Variant Identification should be corrected as 24B starting
from 1000’0F04H.
Firmware_CM.D002 Incorrect specification of value of Status Indicators
returned by NVM routines
These status indicators values returned by NVM routines in XMC1100 ROM
Table of Reference Manual v1.1 are incorrectly specified.
Table 9
Status indicators returned by NVM routines in XMC1100 ROM
Status Indicator
Symbolic name
Description
Value
NVM_E_DST_
80010005H
AREA_EXCEEDE
D
Destination data is not (completely) located
in NVM
NVM_E_DST_
ALIGNMENT
Destination data is not properly aligned
80010006H
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Documentation Updates
Table 9
Status indicators returned by NVM routines in XMC1100 ROM
Status Indicator
Symbolic name
Description
Value
NVM_E_NVM_FA 80010009H
IL
NVM module can not be physically accessed
NVM_E_VERIFY
Verification of the written page not
successful
80010010H
Documentation Update
The values of the status indicators should be corrected as per below.
Table 10
Status indicators returned by NVM routines in XMC1100 ROM
Status Indicator
Symbolic name
Description
Value
NVM_E_NVM_FA 80010005H NVM module can not be physically accessed
IL
NVM_E_VERIFY
80010006H Verification of the written page not successful
80010009H Destination data is not (completely) located in
NVM_E_DST_
AREA_EXCEEDE
NVM
D
NVM_E_DST_
ALIGNMENT
80010010H Destination data is not properly aligned
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