Bijlagen_DVI_to_Fiber_Pattern_generator

Bijlagen_DVI_to_Fiber_Pattern_generator
Schema zender
Bijlage 1
Print zender componenten
Bijlage 2
Print zender bottom layer
Bijlage 3
Print zender top layer
Bijlage 4
Schema ontvanger
Bijlage 5
Print ontvanger componenten
Bijlage 6
Print ontvanger bottom layer
Bijlage 7
Print ontvanger top layer
Bijlage 8
Block Node
CLK CLK
I/O
Type
CLK INPUT
uitgang OUTPUT
uitgang_frequentieLED
OUTPUT
Block
uitgang
863_teller
inst28
q[0]
clock
32MHz
Type...
ingang[12..0]INPUT
uitgang
OUTPUT
inst21
DFF
uitgang1
bus_gen[1]
D
7404
inst11
CLRN
inst9
comparator
Hsync[12..0]
Block Node
uitgang reset1
D
clock
I/O
Type
ingang[12..0]
INPUT
uitgang OUTPUT
inst4
comparator_lt_eq_6
Block
Bus
ingang[10..0]Vsync[10..0]
I/O...
Type...
ingang[10..0]
INPUT
Vsync[10..0]
uitgang
OUTPUT
sclr
q[10..0]
up counter
631_teller
DFF
7404
D
PRN
Q
inst12
reset2
CLRN
inst10
Block
Node
bus_gen bus_gen[0]
PRN
Q
Hsync
CLRN
inst14
DFF
D
7404
PRN
Q
inst18
CLRN
inst20
7404
inst1
7408
Block
Node
verticalblankingvertical_blanking
inst31
bus_gen[0]
I/O
Type
CLK
CLK
INPUT
bus_genOUTPUT
DFF
7404
inst13
Block
Bus
ingang[12..0]Hsync[12..0]
PRN
Q
test1
Block
Node
horizontalblanking
horizontal_blankinginst45
inst
reset1
clock
Hsync[12..0] I/O...
Hsync[12..0]
q[12..0]
Block Node
CLK CLK
comparator_lt_eq_31
up counter
inst6
Vsync[10..0]
INPUT
VCC
RESET HSYNC
clock
up counter
Block Node
uitgang uitgang1
horizontal_blanking
klokdeler
Node
uitgang_frequentieLED
inst22
Block
Bus
ingang[12..0]Hsync[12..0]
sclr
frequentieLED
DE
bus_gen[3]
inst8
7404
inst2
DFF
vertical_blanking
7404
D
PRN
Q
inst17
Block
Bus
Block
Node
ingang[10..0]Vsync[10..0]
uitgang vertical_sync
Block Node
comparator_gt_612
vertical_sync
uitgang reset2
I/O
Type
7404
ingang[10..0]
INPUT
inst16
uitgang OUTPUT
inst7
Beeldopmaak software schema
frequentieLED
CLRN
inst19
DFF
D
bus_gen[2]
PRN
Q
Vsync
CLRN
inst15
Bijlage 9
debouncer
CLK
Block Node
CLK CLK
drukknop_teller
debouncer_signaal
I/O... Type...
CLK INPUT
ingang INPUT
I/O
Type
CLK
INPUT
uitgang[2..0]
OUTPUT
ingang_patroon
INPUT
VCC
patroon
CLKColorShow
I/O
Type
CLK
INPUT
uitgang[23..0]
OUTPUT
Block Node
CLK CLK
inst26
Block
uitgang[23..0]
Block Node
CLK CLK
Block
Bus
Hsync[12..0]Hsync[12..0]
I/O...
Type...
CLK
INPUT
Vsync[10..0]
INPUT
Hsync[12..0]
INPUT
Vsync[10..0]
Block
Bus
Vsync[10..0]Vsync[10..0]
inst3
Block
uitgang[23..0]
Block Node
CLK CLK
I/O...
Type...
CLK
INPUT
Vsync[10..0]
INPUT
Hsync[12..0]
INPUT
Hsync[12..0]
Vsync[10..0]
Block
Bus
Vsync[10..0]Vsync[10..0]
Bus
uitgang_ColorShow[23..0]
sel
uitgangbusjoiner[15..0]
uitgangbusjoiner[31..0]
BUSMUX
dataa[]
datab[]
uitgangbusjoiner[31..16]
DFF
0
result[]
Block
Bus
uitgang[31..0] uitgangbusjoiner[31..0]
D
PRN
Q
OUTPUT
1
inst38
sel
MSB
inst41
keuze[0]
Parameter Value
WIDTH 16
CLRN
inst47
32MHz
NOT
inst43
OUTPUT
sturingsklok
sturing[15..0]
64MHz
Block
Bus
uitgang[23..0]bus_gen[27..4]
TX_ER
inst30
Block
Ingang1[23..0]
TX_ER
I/O
Type
OUTPUT
TX_ER
uitgangOUTPUT
Block Node
inst34
uitgangTX_ER
Bus
uitgang_kleurraster[23..0]
Block
Ingang2[23..0]
Bus
uitgang_Color_Mix[23..0]
Color_Mix
Block
Bus
Hsync[12..0]Hsync[12..0]
Block
Ingang0[23..0]
bus_joiner
Block
Bus
SELECT[2..0]
SELECT[2..0]
I/O...
Type...
Ingang0[23..0]
INPUT
Ingang1[23..0]
INPUT
Ingang2[23..0]
INPUT
SELECT[2..0]
INPUT
Bus
uitgang_kleurraster[23..0]
kleurraster
Hsync[12..0]
Bus
uitgang_ColorShow[23..0]
LSB
I/O
Type
keuze[27..1]
INPUT
uitgang[31..0]
OUTPUT
result[]
Data Barco-generator
demux_pattern
uitgang_kleurraster[23..0]
Node
ingang_patroon
Block
uitgang[23..0]
keuze[27..1]
keuze[27..0]
uitgang_ColorShow[23..0]
uitgang_Color_Mix[23..0]
Block
ingang
0
bus_barco[27..0]
datab[] 1
inst25
inst29
inst27
BUSMUX
bus_gen[27..0]
dataa[]
Block
Bus
uitgang[2..0]SELECT[2..0]
Block
Bus
keuze[27..1]
keuze[27..1]
keuze[27..0]
bus_gen[27..4]
Node
debouncer_signaal
Node
debouncer_signaal
SELECT[2..0]
Block
uitgang
Block
CLK
Zender specifiek software schema
Data eigen-generator
Parameter Value
WIDTH 28
Bus
uitgang_Color_Mix[23..0]
INPUT
VCC
clock_barco
TX_EN
bus_barco[0]
horizontal_sync_barco
INPUT
VCC
vertical_sync_barco
INPUT
VCC
data_enable_barco
INPUT
VCC
Kleur_barco[23..0]
INPUT
VCC
I/O
Type
uitgangOUTPUT
bus_barco[1]
inst35
bus_barco[2]
TX_EN
OUTPUT
TX_EN
Block Node
uitgangTX_EN
bus_barco[3]
bus_barco[27..4]
inst5
debouncer
CLK
I/O... Type...
CLK INPUT
ingang INPUT
Block Node
CLK CLK
wisselknop
Block
ingang
INPUT
VCC
ingang_wisselknop
inst24
Node
ingang_wisselknop
FlipFlop
I/O
uitgang
Block
uitgang
Type
OUTPUT
Node
uitgang_debouncer
JKFF
J
PRN
Q
OUTPUT
keuzeLED
uitgang5
Block Node
uitganguitgang5
K
CLRN
inst32
Bijlage 10
inst23
uitgang_debouncer
clock
Debouncer
INPUT
CLK
VCC
Switch2
OUTPUT
switch1_output
I/O... Type...
ingang INPUT
CLK INPUT
PIN_39
LED2
TFF
sclr
PIN_49
In1_Bus[0]
PRN
Q
antidender_uitgang T
Block
ingang
I/O... Type...
ingang[10..0]
INPUT
clockled OUTPUT
up counter
613_teller
teller_reset
inst27
Comparator_128
613_telle_output[10..0]
q[10..0]
Node
switch1_outputBlock
uitgang
In1_Bus[3..0]
LED1
PIN_48
Block Node
EDGE EDGE
Block Node
inst25
reset teller_reset
CLRN
inst26
clock_led
Block
Node
OUTPUT
clockledclock_led
TFP410_Settings
I/O Type
EDGE OUTPUT
DSEL OUTPUT
Node
antidender_uitgang
inst22
EDGE
OUTPUT
Parameter Value
WIDTH 28
EDGE
Block Node
DSEL DSEL
DSEL
OUTPUT
DSEL
Block
BusIN[15..0]
INPUT
VCC
inclk0
areset
inclk0 frequency: 64.000 MHz
Operation Mode: Normal
c0
locked
Block Node
SEL
SEL_DEMUX
Block
Bus
Block
Node
Block
Bus
BUS_IN2[15..0] BusDemux_Out2[15..0]
CLOCK_TO_DVI
SEL_DEMUX
SEL_DEMUX
BusOUT2[15..0] BusDemux_Out2[15..0]
OUTPUT
LED3
PIN_50
Clk RatioPh (dg)DC (%)
c0 1/2 90.00 50.00
inst23
Block
Bus
BUS_OUT[27..0]
In2_Bus[27..0]
SEL_DEMUX
CLK_Fiber
Block
Bus
I/O...
Type...
BusOUT1[15..0] BusDemux_Out1[15..0]BUS_IN1[15..0]
INPUT
BUS_IN2[15..0]
INPUT
BusDemux_Out2[15..0]
CLOCK_TO_DVI
INPUT
Block
Bus
BUS_IN1[15..0] BusDemux_Out1[15..0]
inst30
inst28
altpll0
PIN_10
2.5 V
Bus_Joiner
I/O...
Type...
BusIN[15..0]
INPUT
SEL
INPUT
Bus
BusOUT1[15..0]
OUTPUT
Bus_DEMUX_IN[15..0]
Cyclone
Block
Bus
Vsync[10..0]ingang2[10..0] Cross_Vieuw
ingang2[10..0]
ingang[12..0]
I/O...
Type...
CLK
INPUT
Block
Bus
Hsync[12..0]ingang[12..0]
Vsync[10..0]
INPUT
Hsync[12..0]
INPUT
Block Node
CLK
In1_Bus[0]
inst33
Block
Bus
Vsync[10..0]ingang2[10..0]
ColorGrid
ingang2[10..0]
ingang[12..0]
ingang2[10..0]
Block
In1_Bus[0]Bus
Hsync[12..0]ingang[12..0]
Block Node
CLK
In1_Bus[0]
ingang[12..0]
In1_Bus[0]
I/O...
Type...
CLK
INPUT
Vsync[10..0]
INPUT
Hsync[12..0]
INPUT
Block
uitgang[23..0]
Block
Bus
ingang1[23..0]
crossvieuwuitgang[23..0]
crossvieuwuitgang[23..0]
INPUT
VCC
Block Node
inst37
ingang ingangske
DrukknopTeller
I/O Type
Block Node
inst34
debouncer2CLK INPUT
CLK
In1_Bus[0]
drukknoptellerout[2..0]
uitgang[2..0]
OUTPUT
Block Node
inst38
uitgang debouncer2
Block
Bus
uitgang[2..0] drukknoptellerout[2..0]
uitgangsklok
Out_Bus[1]
OUTPUT
horizontal_sync
Out_Bus[2]
OUTPUT
data_enable
PIN_72
PIN_56
PIN_57
Out_Bus[3]
OUTPUT
verical_sync
Out_Bus[11..4]
OUTPUT
Out_Bus[19..12]
OUTPUT
Out_Bus[27..20]
OUTPUT
PIN_74
PIN_79
PIN_68
PIN_69
PIN_70
PIN_71
PIN_73
PIN_75
PIN_55
BLUE[7..0]
GREEN[7..0]
RED[7..0]
PIN_84
PIN_89
PIN_76
PIN_77
PIN_78
PIN_85
PIN_86
PIN_87
PIN_90
PIN_100
PIN_88
PIN_91
PIN_92
PIN_97
PIN_98
PIN_99
ColorMix
I/O...
Type...
CLK
INPUT
Hsync[12..0]
INPUT
Vsync[10..0]
INPUT
inst32
In1_Bus[27..4]
Block
Bus
uitgang[23..0]
In1_Bus[27..4]
inst36
ColorShow
I/O
Type
CLK
INPUT
uitgang[23..0]
OUTPUT
inst31
demux
Block
Bus
ingang3[23..0]cirkeluitgang[23..0]
Block
Bus
SELECT[2..0] drukknoptellerout[2..0]
I/O
Type
CLK
INPUT
uitgang[23..0]
OUTPUT
inst48
cirkeluitgang[23..0]
Block
Bus
uitgang[23..0] cirkeluitgang[23..0]
drukknoptellerout[2..0]
PIN_38
Block
Bus
In1_Bus[0]
Hsync[12..0]
ingang[12..0]
I/O...
Type...
CLK
INPUT
Hsync[12..0]
INPUT
Vsync[10..0]
INPUT
sel
Out_Bus[0]
OUTPUT
Bijlage 11
Switch1
I/O... Type...
ingang INPUT
ingangske
CLK INPUT
ingang2[10..0]
ingang[12..0]
inst21
ThreeBusToOneBus
Block
Bus
Vsync[10..0]ingang2[10..0] Cirkel
Block Node
CLK
debouncer2
result[]
Bus
crossvieuwuitgang[23..0]
Block
Bus
I/O...
Type...
ingang2[23..0] colorgriduitgang[23..0] ingang1[23..0]
INPUT
ingang2[23..0]
INPUT
colorgriduitgang[23..0]
ingang3[23..0]
INPUT
SELECT[2..0]
INPUT
cirkeluitgang[23..0]
Block
Bus
uitgang[23..0] colorgriduitgang[23..0]
inst35
Block Node
CLK
In1_Bus[0]
In1_Bus[0]
Debouncer
0
In1_Bus[27..4]
PIN_1
PIN_2
PIN_3
... ...
BusDemux_Out1[15..0]
Bus_DEMUX_IN[15..0]
INPUT
VCC
RX[15..0]
dataa[]
In1_Bus[27..0]datab[] 1
PIN_52
BusDemux
BUSMUX
PIN_54
Out_Bus[27..0]
inst24
In2_Bus[27..0]
In1_Bus[0]
Bus
613_telle_output[10..0]
Ontvanger specifiek software schema
Block
ingang[10..0]
Block Node
CLK
In1_Bus[0]
Beeldprogamma
Frequentieled
module frequentieLED
(
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
CLK, uitgang
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input CLK;
output uitgang;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
reg [23:0] counter1;
always @ (posedge CLK)begin
counter1 = counter1 + 1;
end
assign uitgang = (counter1[23] ) ? 1'b1 : 1'b0;
//assign uitgang1 = (counter1 <= 5000000 ) ? 1'b1 : 1'b0;
endmodule
Comparator ≤ 31
module comparator_lt_eq_31
(
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
ingang, uitgang, horizontalblanking
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input [12:0] ingang;
output uitgang, horizontalblanking;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
assign uitgang = (ingang <= 10) ? 1'b1 : 1'b0;
assign horizontalblanking = ( (ingang >= 835) | (ingang <= 35) ) ? 1'b1 : 1'b0;
endmodule
Bijlage 12
Comparator
module comparator
(
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
ingang, uitgang
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input [12:0] ingang;
output uitgang;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
assign uitgang = (ingang > 863) ? 1'b1 : 1'b0;
endmodule
Comparator ≤ 6
module comparator_lt_eq_6
(
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
ingang, uitgang, verticalblanking
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input [10:0] ingang;
output uitgang, verticalblanking;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
assign uitgang = (ingang <= 6) ? 1'b1 : 1'b0;
assign verticalblanking = ((ingang <= 18) | (ingang > 618)) ? 1'b1 : 1'b0;
endmodule
Comparator > 612
module comparator_gt_612
(
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
ingang, uitgang
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input [10:0] ingang;
output uitgang;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
assign uitgang = (ingang > 631) ? 1'b1 : 1'b0;
endmodule
Keuze van pattern
Bijlage 13
Debouncer
module Debouncer
(
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
ingang, CLK, uitgang
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input ingang;
input CLK;
output uitgang;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
// Register values start
reg [23:0] counter1;
reg uitgang;
// Register values end
always @ ( posedge CLK ) begin : COUNTER
if(ingang == 1'b0) begin
if(uitgang == 1'b0) begin
uitgang <= 1'b1;
end
end
if(uitgang == 1'b1) begin
counter1 <= counter1 + 1;
if(counter1 == 32'hFFFFFF) begin
uitgang <= 1'b0;
counter1 <= 32'h00000;
end
end
end
endmodule
//als de teller zijn waarde bereikt heeft
//dender voorbij
//reset teller
Drukknop Teller
module drukknop_teller
(
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
CLK, uitgang
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input CLK;
output [2:0] uitgang;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
reg [2:0] counter1;
//reg [26:0] counter2;
always @ (posedge CLK)begin //counter2 = counter2 + 1;
//always @ (posedge counter2[26])begin
counter1 = counter1 + 1;
if (counter1 > 2) counter1 = 0;
end
assign uitgang = counter1;
endmodule
Demux pattern
module demux_pattern
(
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
Ingang0, Ingang1, Ingang2, SELECT, uitgang
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input [23:0] Ingang0;
input [23:0] Ingang1;
input [23:0] Ingang2;
input [2:0] SELECT;
output [23:0] uitgang;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
reg [23:0] uitgang;
always @ (posedge Ingang0, posedge Ingang1, posedge Ingang2)begin
case (SELECT)
0: uitgang = Ingang0;
1: uitgang = Ingang1;
2: uitgang = Ingang2;
default: ;
endcase
end
endmodule
Pattern generators
Demux
module demux
(
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
CLK, uitgang
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input CLK;
output [23:0] uitgang;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
reg [23:0] klokdeler;
reg [4:0] select;
always @ (posedge CLK) klokdeler = klokdeler + 1;
always @ (posedge klokdeler[23]) begin
select = select + 1;
if(select == 24) select = 0;
end
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
assign
uitgang[0] = (select == 0) ? 1'b1 : 1'b0;
uitgang[1] = (select == 1) ? 1'b1 : 1'b0;
uitgang[2] = (select == 2) ? 1'b1 : 1'b0;
uitgang[3] = (select == 3) ? 1'b1 : 1'b0;
uitgang[4] = (select == 4) ? 1'b1 : 1'b0;
uitgang[5] = (select == 5) ? 1'b1 : 1'b0;
uitgang[6] = (select == 6) ? 1'b1 : 1'b0;
uitgang[7] = (select == 7) ? 1'b1 : 1'b0;
uitgang[8] = (select == 8) ? 1'b1 : 1'b0;
uitgang[9] = (select == 9) ? 1'b1 : 1'b0;
uitgang[10] = (select == 10) ? 1'b1 : 1'b0;
uitgang[11] = (select == 11) ? 1'b1 : 1'b0;
uitgang[12] = (select == 12) ? 1'b1 : 1'b0;
uitgang[13] = (select == 13) ? 1'b1 : 1'b0;
uitgang[14] = (select == 14) ? 1'b1 : 1'b0;
uitgang[15] = (select == 15) ? 1'b1 : 1'b0;
uitgang[16] = (select == 16) ? 1'b1 : 1'b0;
uitgang[17] = (select == 17) ? 1'b1 : 1'b0;
uitgang[18] = (select == 18) ? 1'b1 : 1'b0;
uitgang[19] = (select == 19) ? 1'b1 : 1'b0;
uitgang[20] = (select == 20) ? 1'b1 : 1'b0;
uitgang[21] = (select == 21) ? 1'b1 : 1'b0;
uitgang[22] = (select == 22) ? 1'b1 : 1'b0;
uitgang[23] = (select == 23) ? 1'b1 : 1'b0;
endmodule
Bijlage 14
Colorshow
module ColorShow
(
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
CLK, uitgang
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input CLK;
output [23:0] uitgang;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
reg [29:0] counter1;
//port data mapping
wire [7:0] kleurInfo;
always @ ( posedge CLK ) begin
// voer dit uit op de positieve edge van de klok
counter1 = counter1 + 1;
// tel er eentje bij
if((counter1[28] == 1) & (counter1[29] == 1)) counter1 = 0;
// synchrone reset van de
teller
end
assign kleurInfo[7:0] = counter1[27:20]; // kleurteller
assign uitgang[7:0] = ((counter1[28] == 0) & (counter1[29] == 0)) ? kleurInfo[7:0]: 8'h00;
// zet kleurteller op kleur 1
assign uitgang[15:8] = ((counter1[28] == 1) & (counter1[29] == 0)) ? kleurInfo[7:0]: 8'h00;
// zet kleurteller op kleur 2
assign uitgang[23:16] = ((counter1[28] == 0) & (counter1[29] == 1)) ? kleurInfo[7:0]: 8'h00;
// zet kleurteller op kleur 3
/*De teller in dit programma heeft 3 functies in 1. Er wordt gezorgd voor een klokdeler om
op een zichtbare frequentie de intensiteit te regelen. Dit gebeurt met bit 0 tot 19.
Hierna wordt de teller ook gebruikt om alle intensiteiten af te lopen, dit met bit 20 tot 27.
Ook kiezen we het kleur dat we willen afbeelden met de laatste twee bits. De reset gebeurt
wanneer beide kleurbits "1" zijn.
*/
endmodule
Colormix
module ColorMix
(
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
CLK, uitgang, Hsync, Vsync
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input CLK;
input [12:0] Hsync;
input [10:0] Vsync;
output [23:0] uitgang;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
wire [7:0] ROOD;
wire [7:0] GROEN;
wire [7:0] BLAUW;
// Rood kleurinfo
// Groen kleurinfo
// Blauw kleurinfo
reg [6:0] schuifteller;
reg [20:0] klokdeler;
reg [3:0] i;
// teller waarde van de schermvuller
reg
reg
reg
reg
reg
reg
//
//
//
//
//
//
regVR;
regVB;
regVG;
regHR;
regHB;
regHG;
Verticaal Rood register
"
Blauw "
"
Groen "
Horizontaal Rood register
"
Blauw "
"
Groen "
always @ (posedge CLK)begin
klokdeler = klokdeler + 1;
regHR = 0;
regHB = 0;
regHG = 0;
regVR = 0;
regVB = 0;
regVG = 0;
// tel bij de klokdeler 1'tje bij.
//
//
// Zet alle registers op "0" om vegen op het scherm te voorkomen.
// Anders bekomen we een wit scherm.
//
//
for (i = 0; i < 12; i = i + 1) begin
// we tellen tot 12 om het beeld verschillende keren te maken, enzo 800*600 pixels te vullen
// begin van de verticale lijnen
if (
( Hsync > ( 23 + ( i * 72 ) - schuifteller )) & ( Hsync <= ( 59 + ( i * 72 ) –
schuifteller ))
// maak een blok rood aan vanaf klokpuls 23 tot klokpuls 72; (3 blokken van
12 pixels)
) regHR = regHR | 1 ;
// Dit is een zeer belangrijke truc! We hebben een for lus die de vorige
waarde zou overschrijven mochten
// we dit willen schrijven "regHR = 1"; Dus moeten we de vorige waarde ook
in rekening brengen door de
// vorige waarden "OF" de huidige waarde op te slaan;
if (
( Hsync > ( 47 + ( i * 72 ) - schuifteller )) & ( Hsync <= ( 83 + ( i * 72 ) schuifteller ))
) regHB = regHB | 1;
if (
( Hsync > ( 71 + ( i * 72 ) - schuifteller )) & ( Hsync <= ( 107 + ( i * 72 ) schuifteller ))
) regHG = regHG | 1;
// einde van de verticale lijnen
// begin van de horizontale lijnen
if (
( Vsync > ( 6 + ( i * 72 ) - schuifteller )) & ( Vsync <= ( 42 + ( i * 72 ) schuifteller ))
) regVR = regVR | 1;
if (
( Vsync > ( 30 + ( i * 72 ) - schuifteller )) & ( Vsync <= ( 66 + ( i * 72 ) schuifteller ))
) regVB = regVB | 1;
if (
( Vsync > ( 54 + ( i * 72 ) - schuifteller )) & ( Vsync <= ( 90 + ( i * 72 ) schuifteller ))
) regVG = regVG | 1;
// einde horizontale lijnen
end
end
// einde for
// einde always
assign ROOD[7] = regHR ^ regVR;
assign BLAUW[7] = regHB ^ regVB;
assign GROEN[7] = regHG ^ regVG;
//
// voeg de lijnen samen om een raster te bekomen
//
always @ (posedge klokdeler[20])begin // een klokdeler maken
schuifteller = schuifteller + 1; // de gedeelde klok
if (schuifteller >= 72) schuifteller = 0; // reset klok
end
assign uitgang = {GROEN,ROOD,BLAUW}; // kleurinfo samenvoegen tot een bus.
endmodule
Crossvieuw
module Cross_Vieuw
(
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
CLK, uitgang, Vsync, Hsync
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input CLK;
input [10:0] Vsync;
input [12:0] Hsync;
output [23:0] uitgang;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
reg [6:0] counter1;
// de gedeelde klok
reg [20:0] counter3;// de klokdeler
wire [7:0] ROOD;
wire [7:0] GROEN;
wire [7:0] BLAUW;
reg [6:0] i;
reg regH;
reg regV;
//
//
//
// de 'for'-variabele
// De horizontale lijnen
// De verticale lijnen
always @ (posedge CLK)begin
counter3 = counter3 + 1;
regH = 0;
regV = 0;
Kleurinfo
// tel er 1'tje bij (klokdeler)
//
Zet de waarden op "0" om vegen op het scherm te voorkomen
// Anders krijgen we een wit scherm
for (i = 0; i < 70; i = i +1) begin
// voer dit een aantal keer uit om het scherm volledig
te vullen.
if ( Hsync == ( 35 + ( i * 12 ) - counter1)) regH = regH | 1;
// dit is dezelfde truk als bij ColorMix.v. De vorige waarde van regH "OF" deze waarde
van regH vormen de totale waarde.
if ( Vsync == (18 + (i * 12) - counter1)) regV = regV | 1;
end
end
// einde van for
// einde van always
assign ROOD[7] = regH | regV; //
assign GROEN[7] = regH | regV;
assign BLAUW[7] = regH | regV;
// horizontale lijnen en verticale samenvoegen
//
always @ (posedge counter3[20])begin // klokdeler
counter1 = counter1 + 1;
// gedeelde klok, tel er 1'tje bij
if (counter1 >= 72) counter1 = 0;
// reset de klok
end
assign uitgang = {ROOD,GROEN,BLAUW};
endmodule
// voeg alle kleuren samen in 1 uitgangsbus
ColorGrid
module ColorGrid
(
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
CLK, Vsync, Hsync, uitgang
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input CLK;
input [10:0] Vsync;
input [12:0] Hsync;
output [23:0] uitgang;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
reg [6:0] counter1;
// De gedeelde teller
reg [20:0] counter3; // De deel teller
wire [7:0] ROOD;
wire [7:0] GROEN;
wire [7:0] BLAUW;
//
// De kleurinfo
//
reg [3:0] i;
// de tellerwaarde om het scherm te
reg regVR;
reg regVB;
//
// De registers om de verschillende kleuren (verticaal en horizontaal) op te
slaan
//
//
//
//
reg
reg
reg
reg
regVG;
regHR;
regHB;
regHG;
always @ (posedge CLK)begin
counter3 = counter3 + 1;
regVR = 0;
regVB = 0;
regVG = 0;
regHR = 0;
regHB = 0;
regHG = 0;
//
// De waarden op "0" zetten om vegen op het scherm te voorkomen.
// Anders bekomen we een wit scherm.
//
//
//
for (i = 0; i < 12; i = i +1) begin
// de schermvulling. Doe dit 12 keer om de volledige
600*800 pixels te vullen
// Begin verticale lijnen
if (
( Hsync == ( 35 + ( i * 72 ) - counter1))|
//
( Hsync == ( 23 + ( i * 72 ) - counter1))|
// Teken 3 lijntjes.
( Hsync == ( 47 + ( i * 72 ) - counter1))
//
) regHR = regHR | 1;
// Dit is een zeer speciale truk. "regHR = regHR | 1" => De vorige waarde "OF"
// deze waarde is de waarde die we opslaan.
if (
( Hsync == ( 59 + ( i * 72 ) - counter1))|
( Hsync == ( 47 + ( i * 72 ) - counter1))|
( Hsync == ( 71 + ( i * 72 ) - counter1))
) regHB = regHB | 1;
if (
( Hsync == ( 83 + ( i * 72 ) - counter1))|
( Hsync == ( 71 + ( i * 72 ) - counter1))|
( Hsync == ( 95 + ( i * 72 ) - counter1))
) regHG = regHG | 1;
// Einde verticale lijnen
// Begin horizontale lijnen
if (
( Vsync == (24 + (i * 72) - counter1))| //statement 1
( Vsync == (12 + (i * 72) - counter1))| //statement 2
( Vsync == (36 + (i * 72) - counter1)) //statement 3
) regVR = regVR | 1;
if (
( Vsync == (48 + (i * 72) - counter1))| //statement 1
( Vsync == (36 + (i * 72) - counter1))| //statement 2
( Vsync == (60 + (i * 72) - counter1)) //statement 3
) regVB = regVB | 1;
if (
( Vsync == (72 + (i * 72) - counter1))| //statement 1
( Vsync == (60 + (i * 72) - counter1))| //statement 2
( Vsync == (84 + (i * 72) - counter1)) //statement 3
) regVG = regVG | 1;
// Einde horizontale lijnen.
end
end // einde for lus
// einde always
assign ROOD[7] = regVR | regHR;
assign BLAUW[7] = regVB | regHB;
assign GROEN[7] = regVG | regHG;
// Plaats de data op de kleurinfo
// We maken een OR van de verticale en horizontale
//
always @ (posedge counter3[20])begin
counter1 = counter1 + 1;
//
if (counter1 >= 72) counter1 = 0;
end
assign uitgang = {BLAUW,GROEN,ROOD};
endmodule
Cirkel
module Cirkel
(
// {{ALTERA_ARGS_BEGIN}} DO NOT REMOVE THIS LINE!
CLK, Vsync, Hsync, uitgang
// {{ALTERA_ARGS_END}} DO NOT REMOVE THIS LINE!
);
// Port Declaration
// {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
input CLK;
input [10:0] Vsync;
input [12:0] Hsync;
output [23:0] uitgang;
// {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
reg
reg
reg
reg
reg
reg
reg1;
reg2;
reg3;
reg4;
reg5;
reg6;
reg
reg
reg
reg
[6:0]
[5:0]
[5:0]
[6:0]
reg
reg
reg
reg
[6:0] size;
[21:0] counter3;
[5:0] counter1;
[6:0] counter2;
offsetVR ;
offsetH;
offsetV ;
offsetHG;
reg richting1;
reg richting2;
wire [7:0] ROOD;
wire [7:0] GROEN;
wire [7:0] BLAUW;
always @ (posedge CLK) begin
//Nulpunt = OffsetH = 33
//OffsetV = 27
offsetH = 63;
offsetV = 46;
offsetVR = ( 27 + counter1 );
offsetHG = ( 33 + counter2 );
size = 8;
counter3 = counter3 + 1;
if ( ( (Vsync <= (size+offsetVR))&(Vsync >=( 0 + offsetVR )))
& ( (Hsync >= (((size+1)+offsetH) -(Vsync-offsetVR))) & (Hsync <=
(((size+1)+offsetH) +(Vsync-offsetVR))) )
) reg1 = 1;
else if ( ((Vsync > (size+offsetVR))&(Vsync <= ((size*2)+offsetVR)))
& ((Hsync >= ((size+1+offsetH) -((size*2)-(Vsync-offsetVR))))
& (Hsync <= (((size+1)+offsetH) +((size*2)-(Vsync-offsetVR)))) ))
reg1 = 1;
else reg1 = 0;
if((Hsync >= (0 + offsetH + 3))
& (Hsync <= (size+4 + offsetH + 3))
& (Vsync >= (0 + offsetVR + 2))
& (Vsync <= (offsetVR + 2 + size+4))) reg2 = 1;
else reg2 = 0;
// EINDE 1 ---------------------------------------------if ( ( (Vsync <= (size+offsetV))&(Vsync >=( 0 + offsetV )))
& ( (Hsync >= (((size+1)+offsetHG) -(Vsync-offsetV))) & (Hsync <=
(((size+1)+offsetHG) +(Vsync-offsetV))) )
) reg3 = 1;
else if ( ((Vsync > (size+offsetV))&(Vsync <= ((size*2)+offsetV)))
& ((Hsync >= ((size+1+offsetHG) -((size*2)-(Vsync-offsetV))))
& (Hsync <= (((size+1)+offsetHG) +((size*2)-(Vsync-offsetV)))) )) reg3 = 1;
else reg3 = 0;
if((Hsync >= (0 + offsetHG + 3))
& (Hsync <= (size+4 + offsetHG + 3))
& (Vsync >= (0 + offsetV + 2))
& (Vsync <= (offsetV + 2 + size+4))) reg4 = 1;
else reg4 = 0;
// EINDE 2 ----------------------------------------------if ( ( (Vsync <= (size+offsetVR))&(Vsync >=( 0 + offsetVR )))
& ( (Hsync >= (((size+1)+offsetHG) -(Vsync-offsetVR))) & (Hsync <=
(((size+1)+offsetHG) +(Vsync-offsetVR))) )
) reg5 = 1;
else if ( ((Vsync > (size+offsetVR))&(Vsync <= ((size*2)+offsetVR)))
& ((Hsync >= ((size+1+offsetHG) -((size*2)-(Vsync-offsetVR))))
& (Hsync <= (((size+1)+offsetHG) +((size*2)-(Vsync-offsetVR)))) )) reg5 = 1;
else reg5 = 0;
if((Hsync >= (0 + offsetHG + 3))
& (Hsync <= (size+4 + offsetHG + 3))
& (Vsync >= (0 + offsetVR + 2))
& (Vsync <= (offsetVR + 2 + size+4))) reg6 = 1;
else reg6 = 0;
// EINDE 3 ----------------------------------------------
end
always @ (posedge counter3[19]) begin
if (richting1 == 0) counter1 = counter1 + 1;
else counter1 = counter1 - 1;
if (counter1 > 40) richting1 = 1;
if (counter1 <= 0) richting1 = 0;
// einde cirkel 1
if (richting2 == 0) counter2 = counter2 + 1;
else counter2 = counter2 - 1;
if (counter2 > 58) richting2 = 1;
if (counter2 <= 0) richting2 = 0;
end
assign ROOD[7] = reg1 & reg2;
assign GROEN[7] = reg3 & reg4;
assign BLAUW[7] = reg6 & reg5;
assign uitgang = {ROOD,GROEN,BLAUW};
endmodule
Bijlage 15
Pin Information for the Cyclone™ EP1C3T100 Device
Version 1.5
Bank
Number
VREFB
Group
Pin Name / Function
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
VREF0B1
VREF0B1
VREF0B1
VREF0B1
VREF0B1
VREF0B1
VREF1B1
VREF1B1
VREF1B1
VREF1B1
VREF1B1
VREF1B1
VREF1B1
VREF1B1
VREF1B1
VREF1B1
VREF1B1
VREF1B1
VREF1B1
VREF2B1
VREF2B1
VREF2B1
VREF2B1
VREF2B1
VREF2B1
VREF2B1
VREF2B1
VREF2B4
VREF2B4
VREF2B4
VREF2B4
VREF2B4
VREF2B4
VREF2B4
VREF2B4
VREF2B4
VREF2B4
VREF2B4
VREF1B4
VREF1B4
VREF1B4
VREF1B4
VREF0B4
VREF0B4
VREF0B4
VREF0B4
VREF0B4
VREF0B4
VREF0B4
VREF0B4
VREF0B4
VREF0B4
VREF2B3
VREF2B3
VREF2B3
VREF2B3
IO
IO
IO
IO
VCCIO1
GND
IO
IO
DATA0
nCONFIG
VCCA_PLL1
CLK0
GNDA_PLL1
nCEO
nCE
MSEL0
MSEL1
DCLK
IO
VCCIO1
GND
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GND
VCCIO4
GND
VCCINT
IO
IO
IO
IO
IO
IO
IO
IO
IO
GND
VCCINT
GND
VCCIO4
IO
IO
IO
IO
IO
IO
IO
IO
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B4
B3
B3
B3
B3
Optional Function(s) Configuration T100
Function
VREF0B1
DQS for x8 in the
T100
INIT_DONE
1
CRC_ERROR 2
CLKUSR
3
4
VREF1B1
nCSO
DATA0
nCONFIG
nCEO
nCE
MSEL0
MSEL1
DCLK
ASDO
VREF2B1
DPCLK7
VREF2B4
VREF1B4
VREF0B4
DPCLK6
PT-EP1C3T100-1.5
Copyright © 2006 Altera Corp.
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
DQ1B7
DQ1B6
DQ1B5
DQS1B
DQ1B4
DM1B
DQS0B
DQ1B3
DQ1B2
DQ1B1
DQ1B0
DQ0R7
DQ0R6
Page 1 of 6
EP1C3T100 Pin List
Pin Information for the Cyclone™ EP1C3T100 Device
Version 1.5
Bank
Number
VREFB
Group
Pin Name / Function
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B3
B2
B2
B2
B2
B2
B2
VREF2B3
VREF2B3
VREF2B3
VREF2B3
VREF2B3
VREF1B3
VREF1B3
VREF1B3
VREF1B3
VREF1B3
VREF1B3
VREF1B3
VREF1B3
VREF1B3
VREF0B3
VREF0B3
VREF0B3
VREF0B3
VREF0B3
VREF0B3
VREF0B3
VREF0B3
VREF0B3
VREF0B2
VREF0B2
VREF0B2
VREF0B2
VREF0B2
VREF0B2
VREF0B2
VREF0B2
VREF0B2
VREF0B2
VREF1B2
VREF1B2
VREF1B2
VREF1B2
VREF2B2
VREF2B2
VREF2B2
VREF2B2
VREF2B2
VREF2B2
VREF2B2
VREF2B2
VREF2B2
VREF2B2
VREF2B2
IO
IO
IO
GND
VCCIO3
CONF_DONE
nSTATUS
TCK
TMS
TDO
IO
CLK2
TDI
IO
IO
IO
IO
IO
GND
VCCIO3
IO
IO
IO
IO
IO
IO
IO
VCCIO2
GND
VCCINT
GND
IO
IO
IO
IO
IO
IO
IO
IO
IO
VCCINT
GND
VCCIO2
GND
IO
IO
IO
IO
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
B2
Optional Function(s) Configuration T100
Function
VREF2B3
VREF1B3
DPCLK4
55
56
57
58
59
CONF_DONE 60
nSTATUS
61
TCK
62
TMS
63
TDO
64
65
66
TDI
67
68
69
70
71
72
VREF0B3
DPCLK3
VREF0B2
VREF1B2
VREF2B2
DPCLK2
DEV_OE
DEV_CLRn
PT-EP1C3T100-1.5
Copyright © 2006 Altera Corp.
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DQS for x8 in the
T100
DQ0R5
DQ0R4
DM0R
DQ0R3
DQ0R2
DQ0R1
DQS0R
DQ0R0
DQ1T0
DQ1T1
DQ1T2
DQ1T3
DQS0T
DM1T
DQS1T
DQ1T4
DQ1T5
DQ1T6
DQ1T7
Page 2 of 6
EP1C3T100 Pin List
Pin Information for the Cyclone™ EP1C3T100 Device
Version 1.5
Pin Name
Pin Type (1st, 2nd, &
3rd Function)
VCCIO[1..4]
Power
VCCINT
GND
Power
Ground
VREF[0..2]B[1..4]
I/O, Input
VCCA_PLL1
GNDA_PLL1
NC
Power
Ground
No Connect
CONF_DONE
Bidirectional (opendrain)
Bidirectional (opendrain)
Pin Description
Supply and Reference Pins
These are I/O supply voltage pins for banks 1 through 4. Each bank can support a different voltage
level. VCCIO supplies power to the output buffers for all I/O standards. VCCIO also supplies power to
the input buffers used for the LVTTL, LVCMOS, 1.5-V, 1.8-V, 2.5-V, and 3.3-V PCI I/O standards.
These are internal logic array voltage supply pins. VCCINT also supplies power to the input buffers
used for the LVDS, SSTL2, and SSTL3 I/O standards.
Device ground pins. All GND pins should be connected to the board GND plane.
Input reference voltage for banks 1-4. If a bank uses a voltage-referenced I/O standard, then these
pins are used as the voltage-reference pins for the bank. If voltage reference I/O standards are not
used in the bank, the VREF pins are available as user I/O pins.
Analog power for PLL1. The designer must connect this pin to 1.5 V, even if the PLL is not used.
Analog ground for PLL1. The designer can connect this pin to the GND plane on the board.
No connect pins should not be connected on the board. They should be left floating.
Configuration and JTAG Pins
This is a dedicated configuration status pin; it is not available as a user I/O pin.
DCLK
DATA0
This is a dedicated configuration status pin; it is not available as a user I/O pin.
Dedicated configuration control input. A low transition resets the target device; a low-to-high transition
begins configuration. All I/O pins tri-state when nCONFIG is driven low.
Input
In passive serial configuration mode, DCLK is a clock input used to clock configuration data from an
external source into the Cyclone device. In active serial configuration mode, DCLK is a clock output
Input (PS mode), Output from the Cyclone device (the Cyclone device acts as master in this mode). This is a dedicated pin
(AS mode)
used for configuration.
Dedicated configuration data input pin.
Input
nCE
Input
nCEO
Output
nSTATUS
nCONFIG
ASDO
I/O, Output
nCSO
I/O, Output
CRC_ERROR
I/O, Output
Active-low chip enable. Dedicated chip enable input used to detect which device is active in a chain of
devices. When nCE is low, the device is enabled. When nCE is high, the device is disabled.
Output that drives low when device configuration is complete. During multi-device configuration, this
pin feeds a subsequent device’s nCE pin.
Active serial data output from the Cyclone device. This output pin is utilized during active serial
configuration mode. The Cyclone device controls configuration and drives address and control
information out on ASDO. In passive serial configuration, this pin is available as a user I/O pin.
Chip select output that enables/disables a serial configuration device. This output is utilized during
active serial configuration mode. The Cyclone device controls configuration and enables the serial
configuration device by driving nCSO low. In passive serial configuration, this pin is available as a
user I/O pin.
CLKUSR
Active high signal that indicates that the error detection circuit has detected errors in the configuration
SRAM bits. This pin is optional and is used when the CRC error detection circuit is enabled.
This is a dual-purpose pin and can be used as an I/O pin when not enabled as INIT_DONE. When
enabled, the pin indicates when the device has entered user mode. This pin can be used as a user I/O
I/O, Output (open-drain) pin after configuration.
Optional user-supplied clock input. Synchronizes the initialization of one or more devices. This pin can
be used as a user I/O pin after configuration.
I/O, Input
DEV_CLRn
I/O, Input
DEV_OE
MSEL[1..0]
TMS
TDI
TCK
TDO
I/O, Input
Input
Input
Input
Input
Output
CLK0
CLK2
Input
Input
INIT_DONE
Dual-purpose pin that can override all clears on all device registers. When this pin is driven low, all
registers are cleared; when this pin is driven high, all registers behave as defined in the design.
Dual-purpose pin that can override all tri-states on the device. When this pin is driven low, all I/O pins
are tri-stated; when this pin is driven high, all I/O pins behave as defined in the design.
Dedicated mode select control pins that set the configuration mode for the device.
This is a dedicated JTAG input pin.
This is a dedicated JTAG input pin.
This is a dedicated JTAG input pin.
This is a dedicated JTAG output pin.
Clock and PLL Pins
Dedicated global clock input.
Dedicated global clock input.
Page 3 of 6
PT-EP1C3T100-1.5
Copyright © 2006 Altera Corp.
Pin Definitions
Pin Information for the Cyclone™ EP1C3T100 Device
Version 1.5
Pin Name
Pin Type (1st, 2nd, &
3rd Function)
DPCLK[7, 6, 4, 3, 2]
I/O
DQS[0..1][L,R,T,B]
DQ[0..7][L,R,T,B]
DM[0..1][L,R,T,B]
I/O
I/O
I/O
Pin Description
Dual-purpose clock pins that can connect to the global clock network. These pins can be used for
high fan-out control signals, such as clocks, clears, IRDY, TRDY, or DQS signals. These pins are
also available as user I/O pins.
Dual-Purpose External Memory Interface Pins
Optional data strobe signal for use in external memory interfacing. These pins also function
as DPCLK pins; therefore, the DQS signals can connect to the global clock network. A
programmable delay chain is used to shift the DQS signals by 90 or 72 degrees.
Optional data signal for use in external memory interfacing.
Optional data mask output signal for use in external memory interfacing.
Page 4 of 6
PT-EP1C3T100-1.5
Copyright © 2006 Altera Corp.
Pin Definitions
Bijlage 16
Pin Information for Serial Configuration Device (EPCS1, EPCS4, EPCS16, EPCS64)
Version 1.0
Pin
Pin
Number in Number in
Pin Type
Description
Pin Name
16-Pin
8-Pin
SOIC
SOIC
Package Package
DATA
2
8
Output
The DATA output signal transfers data serially out of the serial
configuration device to the FPGA during read/configuration operation.
During a read/configuration operations, the serial configuration device is
enabled by pulling nCS low. The DATA signal transitions on the falling
edge of DCLK.
ASDI
5
15
Input
The AS data input signal is used to transfer data serially into the
serial configuration device. It receives the data that should be
programmed into the serial configuration device. Data is latched
in the rising edge of DCLK.
nCS
1
7
Input
The active low chip select input signal toggles at the beginning
and end of a valid instruction. When this signal is high, the
device is deselected and the DATA pin is tri-stated. When this
signal is low, it enables the device and puts the device in an
active mode. After power up, the serial configuration device
requires a falling edge on the nCS signal before beginning any
operation.
DCLK
6
16
Input
DCLK is provided by the FPGA. This signal provides the timing
of the serial interface. The data presented on ASDI is latched
to the serial configuration device, at the rising edge of DCLK.
Data on the DATA pin changes after the falling edge of DCLK
and is latched into the FPGA on the rising edge.
Vcc
3,7,8
1,2,9
Power
Power pins connect to 3.3 V.
GND
4
10
Gound
Ground pin.
NC
3,4,5,6,11 No
This pins can be left floating or connected to Vcc or GND, whichever is
,12,13,14 Connect more convenient on the board.
PT-EPCS-1.0
Copyright @ 2006 Altera Corp.
Bijlage 17
Agilent HFBR-53A5VEM/HFBR-53A5VFM
3.3 V 1 x 9 Fiber Optic Transceivers
for Gigabit Ethernet Low Voltage
Data Sheet
Description
The HFBR-53A5VM transceivers
from Agilent Technologies allow the
system designer to implement a
range of solutions for multimode
Gigabit Ethernet applications.
The overall Agilent transceiver
product consists of three sections:
the transmitter and receiver optical
subassemblies, an electrical
subassembly, and the package
housing which incorporates a
duplex SC connector receptacle.
Transmitter Section
The transmitter section of the
HFBR-53A5VEM/FM consists of an
850 nm Vertical Cavity Surface
Emitting Laser (VCSEL) in an
optical subassembly (OSA), which
mates to the fiber cable. The OSA is
driven by a custom, silicon bipolar
IC which converts differential PECL
compatible logic signals into an
analog laser diode drive current.
The high speed output lines are
internally ac-coupled and
differentially terminate with a 100 Ω
resistor.
Receiver Section
The receiver of the
HFBR-53A5VEM/FM includes a
GaAs PIN photo-diode mounted
together with a custom, silicon
bipolar transimpedance
preamplifier IC in an OSA. This
OSA is mated to a custom silicon
bipolar circuit that provides postamplification and quantization.
The post-amplifier also includes a
Signal Detect circuit which provides a TTL logic-high output
upon detection of a usable input
optical signal level. The high
speed output lines are internally
ac-coupled.
Features
• Compliant with specifications for
IEEE- 802.3z Gigabit Ethernet
• Industry standard mezzanine height
1 x 9 package style with integral
duplex SC connector
• Performance
HFBR-53A5VEM/FM:
220 m links in 62.5/125 µm MMF
160 MHz* km cables
275 m links in 62.5/125 µm MMF
200 MHz* km cables
500 m links in 50/125 µm MMF
400 MHz* km cables
550 m links in 50/125 µm MMF
500 MHz* km cables
• IEC 60825-1 Class 1/CDRH Class I
laser eye safe
• Single +3.3 V power supply
operation with PECL compatible
logic interfaces and TTL Signal
Detect
• Wave solder and aqueous wash
process compatible
Applications
• Switch to switch interface
• Switched backbone applications
• High speed interface for file servers
• High performance desktops
Related Products
• Physical layer ICs available for
optical or copper interface
(HDMP-1636A/1646A)
• Quad Serdes IC available for highdensity interface
• Versions of this transceiver module
also available for +5 V operation
(HFBR/HFCT-53D5)
• MT-RJ SFF fiber optic transceivers
for Gigabit Ethernet
(HFBR/HFCT-5912E)
• Gigabit Interface Converters (GBIC)
Gigabit Ethernet SX-HFBR-5601 /
LX-HFCT-5611
3.3 Vdc
+
VEET
LASER
DRIVER
CIRCUIT
9
8
VCC2 VEE2
TD+
50 Ω
TD-
TD+
PECL
INPUT
OUTPUT
DRIVER
100 Ω
TD- 7
VCCT
R13
150
L2
6
HFBR-53A5VEM/FM
FIBER-OPTIC
TRANSCEIVER
0.1
µF
1 µH
C2
0.1 µF
VCCR 5
+ C8
SIGNAL
DETECT
CIRCUIT
1 µH
10 µF
R12
150
PARALLEL
TO SERIAL
CIRCUIT
10
µF
C3
0.1
µF
SD 4
TO SIGNAL DETECT (SD)
INPUT AT UPPER-LEVEL-IC
RD- 3
50 Ω
RDR14
POSTAMPLIFIER
100
50 Ω
RD+ 2
1
V
CLOCK
SYNTHESIS
CIRCUIT
HDMP-1636A/-1646A
SERIAL/DE-SERIALIZER
(SERDES - 10 BIT
TRANSCEIVER)
3.3 V
+ C4
L1
C1
0.1
µF
PREAMPLIFIER
50 Ω
GND
EER
INPUT
BUFFER
RD+
CLOCK
RECOVERY
CIRCUIT
SERIAL TO
PARALLEL
CIRCUIT
SEE HDMP-1636A/-1646A DATA SHEET FOR
DETAILS ABOUT THIS TRANSCEIVER IC.
NOTES:
USE SURFACE-MOUNT COMPONENTS FOR OPTIMUM HIGH-FREQUENCY PERFORMANCE.
USE 50 Ω MICROSTRIP OR STRIPLINE FOR SIGNAL PATHS.
LOCATE 50 Ω TERMINATIONS AT THE INPUTS OF RECEIVING UNITS.
Figure 3. Recommended Gigabit/sec Ethernet HFBR-53A5VEM/FM Fiber-Optic Transceiver and HDMP-1636A/1646A SERDES Integrated Circuit
Transceiver Interface and Power Supply Filter Circuits.
(2X) ø
20.32
0.800
1.9 ± 0.1
0.075 ± 0.004
Ø0.000 M A
(9X) ø
20.32
0.800
0.8 ± 0.1
0.032 ± 0.004
Ø0.000 M A
(8X) 2.54
0.100
TOP VIEW
Figure 4. Recommended Board Layout Hole Pattern.
9
–A–
Table 1. Pinout Table
Pin
Symbol
Functional Description
Mounting Pins
The mounting pins are provided for transceiver mechanical attachment to the circuit board. They
are embedded in the nonconductive plastic housing and are not connected to the transceiver
internal circuit, nor is there a guaranteed connection to the metallized housing in the EM and FM
versions. They should be soldered into plated-through holes on the printed circuit board.
1
VEER
Receiver Signal Ground
Directly connect this pin to receiver signal ground plane. (For HFBR-53A5VM, VEER = VEET)
2
RD+
Receiver Data Out
AC coupled – PECL compatible.
3
RD–
Receiver Data Out Bar
AC coupled – PECL compatible.
4
SD
Signal Detect
Signal Detect is a single-ended TTL output. If Signal Detect output is not used, leave it
open-circuited.
Normal optical input levels to the receiver result in a logic “1” output, VOH, asserted.
Low input optical levels to the receiver result in a fault condition indicated by a logic “0” output
VOL, deasserted.
5
VCCR
Receiver Power Supply
Provide +3.3 Vdc via the recommended receiver power supply filter circuit.
Locate the power supply filter circuit as close as possible to the VCCR pin.
6
VCCT
Transmitter Power Supply
Provide +3.3 Vdc via the recommended transmitter power supply filter circuit.
Locate the power supply filter circuit as close as possible to the VCCT pin.
7
TD–
Transmitter Data In-Bar
AC coupled – PECL compatible. Internally terminated differentially with 100 Ω.
8
TD+
Transmitter Data In
AC coupled – PECL compatible. Internally terminated differentially with 100 Ω.
9
VEET
Transmitter Signal Ground
Directly connect this pin to the transmitter signal ground plane.
NORMALIZED AMPLITUDE
1 = VEER
2 = RD+
1.3
4 = SD
0.8
5 = VCCR
6 = VCCT
0.5
7 = TD-
0.2
8 = TD+
0
9 = VEET
0
0.22
0.375
0.625 0.78
NORMALIZED TIME
TX
NIC
TOP VIEW
1.0
Figure 1. Transmitter Optical Eye Diagram Mask.
8
RX
3 = RD-
1.0
-0.2
NIC
NIC = NO INTERNAL CONNECTION (MOUNTING PINS)
Figure 2. Pin-Out.
Bijlage 18
®
SiI 163B PanelLink Receiver
Data Sheet
March 2002
General Description
Features
The SiI 163B receiver uses PanelLink Digital technology
to support high-resolution (24 bit/pixel, 16M colors)
displays up to UXGA and beyond, with dual-link DVI for
a total bandwidth up to 330 megapixels per second.
•
Low Power Operation: 280mA max. current
consumption at 3.3V core operation
Sync Detect feature for Plug & Display
“Hot Plugging”
Cable Distance Support: over 5m with twisted-pair,
fiber-optics ready
Compliant with DVI 1.0
Low power standby mode
Automatic entry into standby mode with clock
detect circuitry
Dual-Link DVI support with two devices configured
as master and slave
•
All PanelLink products are designed on a scaleable
CMOS architecture, ensuring support for future
performance enhancements while maintaining the same
logical interface. System designers can be assured that
the interface will be stable through a number of
technology and performance generations.
•
•
•
•
QO1
QO0
HSYN C
VSYN C
DE
OGND
ODCK
OVCC
CTL3
CTL2
CTL1
GND
VCC
QE23
QE22
QE21
QE20
QE19
QE18
QE17
QE16
OVCC
OGND
QE15
QE14
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
EVEN 8-bits RED
51
25
QE13
QO3
52
24
QE12
QO4
53
23
QE11
QO5
54
22
QE10
QO6
55
21
QE9
QO7
56
20
QE8
OVCC
57
19
OGND
OGND
58
18
OVCC
QO8
59
17
QE7
QO9
60
16
QE6
QO10
61
15
QE5
QO11
62
14
QE4
QO12
63
13
QE3
QO13
64
12
QE2
QO14
65
11
QE1
QO15
66
10
QE0
VCC
67
9
PDO#
GND
68
8
69
7
QO17
70
6
SCDT
STAG_OUT#
/SYNC
VCC
QO18
71
5
GND
QO19
72
4
PIXS/M_S
QO20
73
3
ST
QO21
74
2
PD#
QO22
75
1
S_D
100 -Pin TQFP
96
E XT _RES
100
95
AVCC
O CK _INV#
94
RX C-
99
93
RXC+
RESE RVED
92
AG ND
98
91
RX0-
PG ND
90
RX0+
SIGNAL
97
89
AG ND
DIFFERENTIAL
PVCC
88
84
AVCC
AVCC
83
AG ND
87
82
AVCC
AG ND
81
RX2-
86
80
RX2+
RX1-
79
AG ND
85
78
O VCC
RX1+
76
77
QO 23
(Top View)
PLL
CONFIG. PINS
SiI 163B
EV EN 8-bits BLU E
QO2
QO16
ODD 8-bits RED
GPO
OGN D
ODD 8-bits GREEN
ODD 8-bits BLUE
CONTROLS
EVEN 8-bits GREEN
SiI 163B Pin Diagram
•
PWR
MANAGEMENT
OUTPU T CLOCK
PanelLink Digital technology simplifies PC and display
interface design by resolving many of the system level
issues associated with high-speed mixed signal design,
providing the system designer with a digital interface
solution that is quicker to market and lower in cost.
SiI-DS-0055-B
SiI 163B PanelLink Receiver
Data Sheet
Notes on previous table:
1. Guaranteed by design.
2. Jitter defined per DVI 1.0 Specification, Section 4.6 – Jitter Specification.
3. Jitter measured with Clock Recovery Unit per DVI 1.0 Specification, Section 4.7 – Electrical Measurement Procedures.
4. Output clock duty cycle is independent of the differential input clock duty cycle and the IDCK duty cycle.
5. Measured with transmitter powered down.
6. Value in parentheses is specified with OCK_INV#=1.
7. Skew between output data buses when two SiI 163B are wired in master-slave configuration for dual-link. See the
Receiver Layout section on page 30. The ‘minimum’ is the limit of Slave leading Master (slave data output earlier than
master data). The ‘maximum’ is the limit of Slave lagging Master (slave data output later than master data). When the
Slave lags the Master, then the setup time available fro Slave data to ODCK (from the Master) is reduced.
Setup and Hold Timings for Data Rates other than 165 MHz
The measurements shown above are minimum setup and hold timings based on the maximum data rate of 165 MHz.
To estimate the setup and hold times for slower data rates (for either different resolutions or two pixels per clock
mode), the following formula can be used:
Time (at new frequency) = Time (165 MHz) + (Clock Period at new frequency – Clock Period at 165 MHz)/2
For the case of high strength output (ST=1) with a 10 pf load, and using the standard ODCK (OCK_INV# = 0), Table
1 shows the minimum set up and hold times for other speeds as follows:
Table 1. Setup and Hold Times at Various Data Rates
Data Rate (MHz)
112
56
135
67.5
82.5
Clock (ns) Setup (ns)
8.9
17.9
7.4
14.8
12.1
2.3
6.8
1.6
5.3
3.9
Hold (ns)
4.1
8.6
3.4
7.1
5.7
SXGA one pixel per clock
SXGA two pixels per clock
SXGA+ one pixel per clock
SXGA+ two pixels per clock
UXGA two pixels per clock
Designers may want to check whether OCK+INV#=0 or OCK_INV#=1 provides better setup and hold time margin for
their dual-link design. If Slave data lags Master data, which is in part determined by the layout, then the setup time
from Slave to clock may be reduced, and the opposite ODCK edge may be more useful.
SiI-DS-0055-B
6
SiI 163B PanelLink Receiver
Data Sheet
Timing Diagrams
2.0 V
2.0 V
10pF / 5pF
SiI 163B
0.8 V
0.8 V
DLHT
DHLT
Figure 2. Digital Output Transition Times
Note:
1. 10pF loading used at ST=1 and 5pF loading using at ST=0
RCIP
R CIH
2.0 V
2.0 V
2.0 V
0.8 V
0.8 V
RCIL
Figure 3. Receiver Clock Cycle/High/Low Times
RX0
VDIFF=0V
RX1
TCCS
VDIFF=0V
RX2
Figure 4. Channel-to-Channel Skew Timing
7
SiI-DS-0055-B
SiI 163B PanelLink Receiver
Data Sheet
Output Timing
OCK_INV# = 1
OCK_INV# = 0
TSETUP
THOLD
QE[23:0], QO[23:0],
DE, CTL[3:1],
VSYNC, HSYNC
Figure 5. Output Setup/Hold Timings
Note
1. Output Data, DE and Control Signals Setup/Hold Times – to ODCK Falling Edge when OCK_INV# = 0, or to ODCK
Rising Edge when OCK_INV# = 1.
2. See also the description of layout guidelines which guarantee limited skew between master and slave outputs in
the Receiver Layout section on page 30.
TCLKPD
RXC+
..
...
.
Q[35:0], DE,
VSYNC, HSYNC,
CTL[3:1]
Figure 6. Output Signals Disabled Timing from Clock Inactive
TCLKPU + TFSC
RXC+
SCDT
Figure 7. Wake-Up on Clock Detect
PD#
VIL
TPDL
QE[23:0], QO[23:0],
DE, CTL[3:1],
VSYNC, HSYNC
Figure 8. Output Signals Disabled Timing from PD# Active
SiI-DS-0055-B
8
Bijlage 19
PanelBus SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002
D Digital Visual Interface (DVI) Compliant1
D Supports Resolutions From VGA to UXGA
D Enhanced Jitter Performance
(25 MHz – 165 MHz Pixel Rates)
D
D
D Universal Graphics Controller Interface
D
– 12-Bit, Dual-Edge and 24-Bit,
Single-Edge Input Modes
– Adjustable 1.1 V to 1.8 V and Standard
3.3 V CMOS Input Signal Levels
– Fully Differential and Single-Ended Input
Clocking Modes
– Standard Intel 12-Bit Digital Video Port
Compatible as on Intel 81x Chipsets
Enhanced PLL Noise Immunity
– On-Chip Regulators and Bypass
Capacitors for Reducing System Costs
D
D
D
D
– No HSYNC Jitter Anomaly
– Negligible Data-Dependent Jitter
Programmable Using I2C Serial Interface
Monitor Detection Through Hot-Plug and
Receiver Detection
Single 3.3-V Supply Operation
64-Pin TQFP Using TI’s PowerPAD
Package
TI’s Advanced 0.18 µm EPIC-5 CMOS
Process Technology
Pin Compatible With SiI164 DVI Transmitter
description
The TFP410 is a Texas Instruments PanelBus flat panel display product, part of a comprehensive family of
end-to-end DVI 1.0-compliant solutions, targeted at the PC and consumer electronics industry.
The TFP410 provides a universal interface to allow a glue-less connection to most commonly available graphics
controllers. Some of the advantages of this universal interface include selectable bus widths, adjustable signal
levels, and differential and single-ended clocking. The adjustable 1.1-V to 1.8-V digital interface provides a
low-EMI, high-speed bus that connects seamlessly with 12-bit or 24-bit interfaces. The DVI interface supports
flat panel display resolutions up to UXGA at 165 MHz in 24-bit true color pixel format.
The TFP410 combines PanelBus circuit innovation with TI’s advanced 0.18 µm EPIC-5 CMOS process
technology and TI’s ultralow ground inductance PowerPAD package. The result is a compact 64-pin TQFP
package providing a reliable, low-current, low-noise, high-speed digital interface solution.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either VCC or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for
Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Footnote:
1. The digital visual interface (DVI) specification is an industry standard developed by the digital display working group (DDWG) for high-speed
digital connection to digital displays and has been adopted by industry-leading PC and consumer electronics manufacturers. The TFP410
is compliant to the DVI Revision 1.0 specification.
PanelBus, PowerPAD, and EPIC-5 are trademarks of Texas Instruments.
VESA is a trademark of Video Electronics Standards Association.
Intel is a trademark of Intel Corporation.
Copyright  2002, Texas Instruments Incorporated
!"$#&"! % '$$!& % " ('&"! &
$"'&% "!"$# &" %(&"!% ($ & &$#% " )% !%&$'#!&%
%&!$ *$$!&+ $"'&"! ($"%%! "% !"& !%%$+ !'
&%&! " ($#&$%
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
PanelBus SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002
pin assignments
DGND
DATA12
DATA13
DATA14
DATA15
DATA16
DATA17
DATA18
DATA19
DATA20
DATA21
DATA22
DATA23
DKEN
RESERVED
DVDD
PAP PACKAGE
(TOP VIEW)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
32
49
50
31
51
30
52
29
53
28
54
27
55
26
56
25
57
24
58
23
59
22
60
21
61
20
62
19
63
18
64
1 2
3 4
5
17
6 7 8 9 10 11 12 13 14 15 16
DVDD
DE
VREF
HSYNC
VSYNC
CTL3/A3/DK3
CTL2/A2/DK2
CTL1/A1/DK1
EDGE/HTPLG
PD
MSEN/PO1
DVDD
ISEL/RST
DSEL/SDA
BSEL/SCL
DGND
NC
DATA11
DATA10
DATA9
DATA8
DATA7
DATA6
IDCK–
IDCK+
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
DGND
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TGND
TX2+
TX2–
TVDD
TX1+
TX1–
TGND
TX0+
TX0–
TVDD
TXC+
TXC–
TGND
TFADJ
PVDD
PGND
PanelBus SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002
functional block diagram
Universal Input
IDCK±
DATA[23:0]
DE
VSYNC
12/24 Bit
I/F
HSYNC
VREF
Data
Format
T.M.D.S. Transmitter
Encoder
Serializer
TX2±
Encoder
Serializer
TX1±
Encoder
Serializer
TX0±
Control
TXC±
EDGE/HTPLG
DKEN
MSEN
PD
ISEL/RST
CTL/A/DK[3:1]
TFADJ
I2C Slave I/F
For DDC
BSEL/SCL
DSEL/SDA
1.8-V Regulators
With Bypass
Capacitors
PLL
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
Input
DATA[23:12]
36–47
I
The upper 12 bits of the 24-bit pixel bus
In 24-bit, single-edge input mode (BSEL = high), this bus inputs the top half of the 24-bit pixel bus.
In 12-bit, dual-edge input mode (BSEL = low), these bits are not used to input pixel data. In this mode,
the state of DATA[23:16] is input to the I2C register CFG. This allows 8 bits of user configuration data to
be read by the graphics controller through the I2C interface (see the I2C register descriptions section).
Note: All unused data inputs should be tied to GND or VDD.
DATA[11:0]
50–55,
58–63
I
The lower 12 bits of the 24-bit pixel bus/12-bit pixel bus input
In 24-bit, single-edge input mode (BSEL = high), this bus inputs the bottom half of the 24-bit pixel bus.
In 12-bit, dual-edge input mode (BSEL = low), this bus inputs 1/2 a pixel (12 bits) at every latch edge
(both rising and falling) of the clock.
IDCK–
IDCK+
56
57
I
Differential clock input. The TFP410 supports both single-ended and fully differential clock input
modes. In the single-ended clock input mode, the IDCK+ input (pin 57) should be connected to the
single-ended clock source and the IDCK– input (pin 56) should be tied to GND. In the differential clock
input mode, the TFP410 uses the crossover point between the IDCK+ and IDCK– signals as the timing
reference for latching incoming data DATA[23:0], DE, HSYNC, & VSYNC. The differential clock input
mode is only available in the low signal swing mode.
DE
2
I
Data enable. As defined in DVI 1.0 specification, the DE signal allows the transmitter to encode pixel
data or control data on any given input clock cycle. During active video (DE = high), the transmitter
encodes pixel data, DATA[23:0]. During the blanking interval (DE = low), the transmitter encodes
HSYNC, VSYNC and CTL[3:1].
HSYNC
4
I
Horizontal sync input
VSYNC
5
I
Vertical sync input
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
PanelBus SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002
Terminal Functions (Continued)
TERMINAL
NAME
NO.
CTL3/A3/DK3
CTL2/A2/DK2
CTL1/A1/DK1
6
7
8
I/O
DESCRIPTION
I
The operation of these three multifunction inputs depends on the settings of the ISEL (pin 13) and
DKEN (pin 35) inputs. All three inputs support 3.3-V CMOS signal levels and contain weak pulldown
resistors so that if left unconnected they default to all low.
When the I2C bus is disabled (ISEL = low) and the de-skew mode is disabled (DKEN = low), these three
inputs become the control inputs, CTL[3:1], which can be used to send additional information across
the DVI link during the blanking interval (DE = low). The CTL3 input is reserved for HDCP compliant DVI
TXs (TFP510) and the CTL[2:1] inputs are reserved for future use.
When the I2C bus is disabled (ISEL = low) and the de-skew mode is enabled (DKEN = high), these
three inputs become the de-skew inputs DK[3:1], used to adjust the setup and hold times of the pixel
data inputs DATA[23:0], relative to the clock input IDCK±.
When the I2C bus is enabled (ISEL = high), these three inputs become the 3 LSBs of the I2C slave
address, A[3:1].
Monitor sense/programmable output 1. The operation of this pin depends on whether the I2C interface
is enabled or disabled. This pin has an open-drain output and is only 3.3-V tolerant. An external 5-kΩ
pullup resistor connected to VDD is required on this pin.
When I2C is disabled (ISEL = low), a low level indicates a powered on receiver is detected at the
differential outputs. A high level indicates a powered on receiver is not detected. This function is only
valid in dc-coupled systems.
When I2C is enabled (ISEL = high), this output is programmable through the I2C interface (see the I2C
register descriptions section).
I2C interface select/I2C RESET (active low, asynchronous)
Configuration/Programming
MSEN/PO1
11
O
ISEL/RST
13
I
BSEL/SCL
15
I
DSEL/SDA
14
I/O
EDGE/HTPLG
9
I
4
If ISEL is high, then the I2C interface is active. Default values for the I2C registers can be found in the
I2C register descriptions section.
If ISEL is low, then I2C is disabled and the chip configuration is specified by the configuration pins
(BSEL, DSEL, EDGE, VREF) and state pins (PD, DKEN).
If ISEL is brought low and then back high, the I2C state machine is reset. The register values are
changed to their default values and are not preserved from before the reset.
Input bus select/I2C clock input. The operation of this pin depends on whether the I2C interface is
enabled or disabled. This pin is only 3.3-V tolerant.
When I2C is disabled (ISEL = low), a high level selects 24-bit input, single-edge input mode. A low level
selects 12-bit input, dual-edge input mode.
When I2C is enabled (ISEL = high), this pin functions as the I2C clock input (see the I2C register
descriptions section). In this configuration, this pin has an open-drain output that requires an external
5-kΩ pullup resistor connected to VDD.
DSEL/I2C data. The operation of this pin depends on whether the I2C interface is enabled or disabled.
This pin is only 3.3-V tolerant.
When I2C is disabled (ISEL = low), this pin is used with BSEL and VREF to select the single-ended or
differential input clock mode (see the universal graphics controller interface modes section).
When I2C is enabled (ISEL = high), this pin functions as the I2C bidirectional data line. In this
configuration, this pin has an open-drain output that requires an external 5-kΩ pullup resistor
connected to VDD.
Edge select/hot plug input. The operation of this pin depends on whether the I2C interface is enabled or
disabled. This input is 3.3-V tolerant only.
When I2C is disabled (ISEL = low), a high level selects the primary latch to occur on the rising edge of
the input clock IDCK+. A low level selects the primary latch to occur on the falling edge of the input clock
IDCK+. This is the case for both single-ended and differential input clock modes.
When I2C is enabled (ISEL = high), this pin is used to monitor the hot plug detect signal (see the DVI or
VESA P&D and DFP standards). When used for hot-plug detection, this pin requires a series 1-KΩ
resistor.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PanelBus SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002
Terminal Functions (Continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
DKEN
35
I
Data de-skew enable. The de-skew function can be enabled either through I2C or by this pin when I2C
is disabled. When de-skew is enabled, the input clock to data setup/hold time can be adjusted in
discrete trim increments. The amount of trim per increment is defined by t(STEP).
When I2C is disabled (ISEL = low), a high level enables de-skew with the trim increment determined by
pins DK[3:1] (see the data de-skew section). A low level disables de-skew and the default trim setting is
used.
When I2C is enabled (ISEL = high), the value of DKEN and the trim increment are selected through I2C.
In this configuration, the DKEN pin should be tied to either GND or VDD to avoid a floating input.
VREF
3
I
Input reference voltage. Selects the swing range of the digital data inputs (DATA[23:0], DE, HSYNC,
VSYNC, and IDCK±).
For high-swing 3.3-V input signal levels, VREF should be tied to VDD.
For low-swing input signal levels, VREF should be set to half of the maximum input voltage level. See
the recommended operating conditions section for the allowable range for VREF.
The desired VREF voltage level is typically derived using a simple voltage-divider circuit.
PD
10
I
Power down (active low). In the powerdown state, only the digital I/O buffers and I2C interface remain
active.
When I2C is disabled (ISEL = low), a high level selects the normal operating mode. A low level selects
the powerdown mode.
When I2C is enabled (ISEL = high), the power-down state is selected through I2C. In this configuration,
the PD pin should be tied to GND.
Note: The default register value for PD is low, so the device is in powerdown mode when I2C is first
enabled or after an I2C RESET.
34
In
This pin is reserved and must be tied to GND for normal operation.
Reserved
RESERVED
DVI Differential Signal Output Pins
TX0+
TX0–
25
24
O
Channel 0 DVI differential output pair. TX0± transmits the 8-bit blue pixel data during active video and
HSYNC and VSYNC during the blanking interval.
TX1+
TX1–
28
27
O
Channel 1 DVI differential output pair. TX1± transmits the 8-bit green pixel data during active video and
CTL[1] during the blanking interval.
TX2+
TX2–
31
30
O
Channel 2 DVI differential output pair. TX2± transmits the 8-bit red pixel data during active video and
CTL[3:2] during the blanking interval.
TXC+
TXC–
22
21
O
DVI differential output clock.
TFADJ
19
I
Full-scale adjust. This pin controls the amplitude of the DVI output voltage swing, determined by the
value of the pullup resistor RTFADJ connected to TVDD.
Power and Ground Pins
DVDD
1, 12, 33
Power
Digital power supply. Must be set to 3.3 V nominal.
PVDD
TVDD
18
Power
PLL power supply. Must be set to 3.3 V nominal.
23, 29
Power
Transmitter differential output driver power supply. Must be set to 3.3 V nominal.
DGND
16, 48, 64
Ground
Digital ground
PGND
17
Ground
PLL ground
TGND
20, 26, 32
Ground
Transmitter differential output driver ground
49
NC
NC
No connection required. If connected, tie high.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
Bijlage 20
CFPS-32
Outline in mm
ISSUE 2; 28 JULY 2005
5.0 max
Delivery Options
■ Please contact our sales office for current leadtimes
Description
■ The CFPS-32 is a 2.5V low voltage, surface mount
oscillator with
a CMOS output
Pad Connections
1. Enable/Disable
2. GND
3. Output
4. +Vs
0.95±0.1
7.5 max
Output Compatibility
Tri-state CMOS
■ Drive Capability 15pF max
Solder pads layout
1.8
Frequency Range
1.8 to 160.0MHz
2
3
■
Frequency Stabilities
±25ppm, ±50ppm, ±100ppm (inclusive of supply
voltage & output load variations over the operating
temperature range)
■
4.2
2.6
1
4
2.0
5.08
Package Outline
■ 7.5 x 5.0mm SMD Ceramic Package
1.4
1.2
SURFACE MOUNT
SPXOs
■
5.08
Output Waveform
tf
+Vs
tr
90%Vs
Operating Temperature Ranges
-10 to 70°C (CFPS-32)
■ -40 to 85°C (CFPS-32I)
■
50%Vs
Storage Temperature Range
■ -55 to 125°C
10%Vs
Tri-state Operation
■ Logic ‘1’ to pad 1 enables oscillator output (>70% Vs)
■ Logic ‘0’ to pad 1 disables oscillator output; when the
oscillator output goes to the high impedance state
(< 30% Vs)
■ No connection to pad 1 enables oscillator output
■ Standby current 10 A max
t
0V
T
Duty cycle = t x 100(%)
T
Test Circuit - CMOS
Solder Conditions
For typical soldering conditions, please see the relevant
A
pages in Applications Notes
+Vs
Oscillator
4
3
1
2
Power
Supply
Marking
■ Model Number
■ Frequency
Frequency
Counter
+Vs
■
V
0.1 F
Oscilloscope
15pF *
Minimum Order Information Required
Frequency + Model Number + Operating Temperature
Code (if applicable) + Frequency Stability
■
* Inclusive of jigging & equipment capacitance
Europe Tel: +44 (0)1460 270200
Americas Tel: +1 919 941 9333
Asia
Tel: +86 755 8826 5991
Fax: +44 (0)1460 72578
Fax: +1 919 941 9371
Fax: +86 755 8826 5990
Website: www.cmac.com
Bijlage 21
LP38841
0.8A Ultra Low Dropout Linear Regulators
Stable with Ceramic Output Capacitors
General Description
Features
The LP38841 is a high current, fast response regulator
which can maintain output voltage regulation with minimum
input to output voltage drop. Fabricated on a CMOS process,
the device operates from two input voltages: Vbias provides
voltage to drive the gate of the N-MOS power transistor,
while Vin is the input voltage which supplies power to the
load. The use of an external bias rail allows the part to
operate from ultra low Vin voltages. Unlike bipolar regulators, the CMOS architecture consumes extremely low quiescent current at any output load current. The use of an
N-MOS power transistor results in wide bandwidth, yet minimum external capacitance is required to maintain loop stability.
n
n
n
n
n
n
n
n
n
n
n
The fast transient response of these devices makes them
suitable for use in powering DSP, Microcontroller Core voltages and Switch Mode Power Supply post regulators. The
parts are available in TO-220 and TO-263 packages.
Dropout Voltage: 75 mV (typ) @ 0.8A load current.
Applications
Quiescent Current: 30 mA (typ) at full load.
Shutdown Current: 30 nA (typ) when S/D pin is low.
Precision Output Voltage: 1.5% room temperature accuracy.
Ideal for conversion from 1.8V or 1.5V inputs
Designed for use with low ESR ceramic capacitors
0.8V, 1.2V and 1.5V standard voltages available
Ultra low dropout voltage (75mV @ 0.8A typ)
1.5% initial output accuracy
Load regulation of 0.1%/A (typical)
30nA quiescent current in shutdown (typical)
Low ground pin current at all loads
Over temperature/over current protection
Available in 5 lead TO220 and TO263 packages
−40˚C to +125˚C junction temperature range
n ASIC Power Supplies In:
- Desktops, Notebooks, and Graphics Cards, Servers
- Gaming Set Top Boxes, Printers and Copiers
n Server Core and I/O Supplies
n DSP and FPGA Power Supplies
n SMPS Post-Regulator
Typical Application Circuit
20102801
* Minimum value required if Tantalum capacitor is used (see Application Hints).
© 2004 National Semiconductor Corporation
DS201028
www.national.com
LP38841 0.8A Ultra Low Dropout Linear Regulators
Stable with Ceramic Output Capacitors
December 2004
LP38841
Connection Diagrams
20102802
20102803
TO-220, Top View
TO-263, Top View
Pin Description
Pin Name
BIAS
OUTPUT
Description
The bias pin is used to provide the low current bias voltage to the chip which operates the internal
circuitry and provides drive voltage for the N-FET.
The regulated output voltage is connected to this pin.
GND
This is both the power and analog ground for the IC. Note that both pin three and the tab of the
TO-220 and TO-263 packages are at ground potential. Pin three and the tab should be tied together
using the PC board copper trace material and connected to circuit ground.
INPUT
The high current input voltage which is regulated down to the nominal output voltage must be
connected to this pin. Because the bias voltage to operate the chip is provided seperately, the input
voltage can be as low as a few hundered millivolts above the output voltage.
SHUTDOWN
This provides a low power shutdown function which turns the regulated output OFF. Tie to VBIAS if
this function is not used.
Ordering Information
Order Number
Package Type
Package Drawing
Supplied As
LP38841S-0.8
TO263-5
TS5B
Rail
LP38841SX-0.8
TO263-5
TS5B
Tape and Reel
LP38841T-0.8
TO220-5
T05D
Rail
LP38841S-1.2
TO263-5
TS5B
Rail
LP38841SX-1.2
TO263-5
TS5B
Tape and Reel
LP38841T-1.2
TO220-5
T05D
Rail
LP38841S-1.5
TO263-5
TS5B
Rail
LP38841SX-1.5
TO263-5
TS5B
Tape and Reel
LP38841T-1.5
TO220-5
T05D
Rail
www.national.com
2
Bijlage 22
LP3872/LP3875
1.5A Fast Ultra Low Dropout Linear Regulators
General Description
Features
The LP3872/LP3875 series of fast ultra low-dropout linear
regulators operate from a +2.5V to +7.0V input supply. Wide
range of preset output voltage options are available. These
ultra low dropout linear regulators respond very quickly to
step changes in load, which makes them suitable for low
voltage microprocessor applications. The LP3872/LP3875
are developed on a CMOS process which allows low quiescent current operation independent of output load current.
This CMOS process also allows the LP3872/LP3875 to operate under extremely low dropout conditions.
Dropout Voltage: Ultra low dropout voltage; typically 38mV
at 150mA load current and 380mV at 1.5A load current.
Ground Pin Current: Typically 6mA at 1.5A load current.
n
n
n
n
n
n
n
n
n
n
n
n
Shutdown Mode: Typically 10nA quiescent current when
the shutdown pin is pulled low.
Applications
Error Flag: Error flag goes low when the output voltage
drops 10% below nominal value.
SENSE: Sense pin improves regulation at remote loads.
Precision Output Voltage: Multiple output voltage options
are available ranging from 1.8V to 5.0V with a guaranteed
accuracy of ± 1.5% at room temperature, and ± 3.0% over all
conditions (varying line, load, and temperature).
n
n
n
n
n
n
n
n
Ultra low dropout voltage
Low ground pin current
Load regulation of 0.06%
10nA quiescent current in shutdown mode
Guaranteed output current of 1.5A DC
Available in TO-263, TO-220 and SOT-223 packages
Output voltage accuracy ± 1.5%
Error flag indicates output status
Sense option improves load regulation
Minimum output capacitor requirements
Overtemperature/overcurrent protection
−40˚C to +125˚C junction temperature range
Microprocessor power supplies
GTL, GTL+, BTL, and SSTL bus terminators
Power supplies for DSPs
SCSI terminator
Post regulators
High efficiency linear regulators
Battery chargers
Other battery powered applications
Typical Application Circuits
20063301
*SD and ERROR pins must be pulled high through a 10kΩ pull-up resistor. Connect the ERROR pin to ground if this function is not used. See application hints
for more information.
© 2004 National Semiconductor Corporation
DS200633
www.national.com
LP3872/LP3875 1.5A Fast Ultra Low Dropout Linear Regulators
February 2004
LP3872/LP3875
Typical Application Circuits
(Continued)
20063345
*SD must be pulled high through a 10kΩ pull-up resistor. See application hints for more information.
Connection Diagrams
20063306
20063305
Top View
TO263-5 Package
Top View
TO220-5 Package
Bent, Staggered Leads
20063386
Top View
SOT223-5 Package
www.national.com
2
Bijlage 23
SLLS428F − JUNE 2000 − REVISED JANUARY 2004
D Hot Plug Protection
D 0.6 to 1.5 Gigabits Per Second (Gbps)
D On-Chip 8-Bit/10-Bit (8B/10B)
Serializer/Deserializer
D High-Performance 64-Pin VQFP Thermally
D
D
D
D
Enhanced Package (PowerPAD)
2.5 V Power Supply for Low Power
Operation
Programmable Voltage Output Swing on
Serial Output
Interfaces to Backplane, Copper Cables, or
Optical Converters
Rated for Industrial Temperature Range
D
D
D
D
D
Encoding/Decoding, Comma Alignment,
and Link Synchronization
On-Chip PLL Provides Clock Synthesis
From Low-Speed Reference
Receiver Differential Input Thresholds
200 mV Minimum
Typical Power: 250 mW
Loss of Signal (LOS) Detection
Ideal for High-Speed Backplane
Interconnect and Point-to-Point Data Link
description
The TLK1501 is a member of the transceiver family of multigigabit transceivers used in ultrahigh-speed
bidirectional point-to-point data transmission systems. The TLK1501 supports an effective serial interface
speed of 0.6 Gbps to 1.5 Gbps, providing up to 1.2 Gbps of data bandwidth. The TLK1501 is pin-for-pin
compatible with the TLK2500. The TLK1501 is both pin-for-pin compatible with and functionally identical to the
TLK2501, a 1.6 to 2.5 Gbps transceiver, providing a wide range of performance solutions with no required board
layout changes.
The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband
data transmission over controlled impedance media of approximately 50 Ω. The transmission media can be
printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is
dependent upon the attenuation characteristics of the media and the noise coupling to the environment.
This device can also be used to replace parallel data transmission architectures by providing a reduction in the
number of traces, connector terminals, and transmit/receive terminals. Parallel data loaded into the transmitter
is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance
backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power
and cost savings over current solutions, as well as scalability for higher data rate in the future.
The TLK1501 performs data conversion parallel-to-serial and serial-to-parallel. The clock extraction functions
as a physical layer interface device. The serial transceiver interface operates at a maximum speed of 1.5 Gbps.
The transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (GTX_CLK). The
16-bit parallel data is internally encoded into 20 bits using an 8-bit/10-bit (8B/10B) encoding format. The
resulting 20-bit word is then transmitted differentially at 20 times the reference clock (GTX_CLK) rate. The
receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit
wide parallel data to the extracted reference clock (RX_CLK). It then decodes the 20 bit wide data using
8-bit/10-bit decoding format resulting in 16 bits of parallel data at the receive data terminals (RXD0-15). The
outcome is an effective data payload of 480 Mbps to 1.2 Gbps (16 bits data x the GTX_CLK frequency).
The TLK1501 is housed in a high performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use
of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which
is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is
recommended that the TLK1501 PowerPAD be soldered to the thermal land on the board. All ac performance
specifications in this data sheet are measured with the PowerPAD soldered to the test board.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Copyright  2000 − 2004, Texas Instruments Incorporated
!#$&"(!$# !' )&&#( ' $ %)*!(!$# (
&$)(' $#$&" ($ '%!!(!$#' %& ( (&"' $ +' #'(&)"#('
'(#& ,&&#(- &$)(!$# %&$''!# $' #$( #''&!*- !#*)
('(!# $ ** %&"(&'
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SLLS428F − JUNE 2000 − REVISED JANUARY 2004
1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD
RXD3
RXD4
RXD5
RXD6
GND
RXD7
RX_CLK
RXD8
RXD9
VDD
RXD10
RXD11
RXD12
RXD13
GND
TXD14
GND
TXD15
TX_EN
LOOPEN
TX_ER
V DD
ENABLE
LCKREFN
PRBSEN
TESTEN
GND
RX_ER/PRBS_PASS
RX_DV/LOS
RXD15
RXD14
VDD
TXD3
TXD4
TXD5
GND
TXD6
TXD7
GTX_CLK
VDD
TXD8
TXD9
TXD10
GND
TXD11
TXD12
TXD13
RXD1
RXD2
TXD2
TXD1
TXD0
GNDA
DOUTTXP
DOUTTXN
GNDA
VDDA
RREF
VDDA
DINRXP
DINRXN
GNDA
RXD0
RCP PACKAGE
(TOP VIEW)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SLLS428F − JUNE 2000 − REVISED JANUARY 2004
Terminal Functions
TERMINAL
NAME
NO.
TYPE
DESCRIPTION
DINRXN
DINRXP
53
54
I
Serial receive inputs. DINRXP and DINRXN together are the differential serial input interface from a
copper or an optical I/F module.
DOUTTXN
DOUTTXP
59
60
O
Serial transmit outputs (Hi-Z on power up). DOUTTXP and DOUTTXN are differential serial outputs that
interface to copper or an optical I/F module. These terminals transmit NRZ data at a rate of 20 times the
GTX_CLK value. DOUTTXP and DOUTTXN are put in a high-impedance state when LOOPEN is high
and are active when LOOPEN is low. During power-on reset these terminals are high impedance.
ENABLE
24
I
Device enable (w/pullup). When this terminal is held low, the device is placed in power-down mode. Only
the signal detect circuit on the serial receive pair is active. When asserted high while the device is in
power-down mode, the transceiver goes into power-on reset before beginning normal operation.
GND
5, 13,
18, 28,
33, 43
Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.
GNDA
52, 58,
61
Analog ground. GNDA provides a ground reference for the high-speed analog circuits, RX and TX.
GTX_CLK
8
I
Reference clock. GTX_CLK is a continuous external input clock that synchronizes the transmitter
interface signals TX_EN, TX_ER and TXD. The frequency range of GTX_CLK is 30 MHz to 75 MHz.
The transmitter uses the rising edge of this clock to register the 16-bit input data (TXD) for serialization.
LCKREFN
25
I
Lock to reference (w/pullup). When LCKREFN is low, the receiver clock is frequency locked to
GTX_CLK. This places the device in a transmit only mode since the receiver is not tracking the data.
When LCKREFN is asserted low, the receive data bus terminals, RXD[0:15], RX_CLK and RX_ER,
RX_DV/LOS are in a high-impedance state.
When LCKREFN is deasserted high, the receiver is locked to the received data stream and must receive
valid codes from the synchronization state machine before the transmitter is enabled.
LOOPEN
21
I
Loop enable (w/pulldown). When LOOPEN is active high, the internal loop-back path is activated. The
transmitted serial data is directly routed internally to the inputs of the receiver. This provides a self-test
capability in conjunction with the protocol device. The DOUTTXP and DOUTTXN outputs are held in a
high-impedance state during the loop-back test. LOOPEN is held low during standard operational state
with external serial outputs and inputs active.
PRBSEN
26
I
PRBS test enable (w/pulldown). When asserted high results of pseudorandom bit stream (PRBS) tests
can be monitored on the RX_ER/PRBS_PASS terminal. A high on PRBS_PASS indicates that valid
PRBS is being received.
RREF
56
I
Reference resistor. The RREF terminal is used to connect to an external reference resistor. The other
side of the resistor is connected to analog VDD. The resistor is used to provide an accurate current
reference to the transmitter circuitry.
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
RXD8
RXD9
RXD10
RXD11
RXD12
RXD13
RXD14
RXD15
51
50
49
47
46
45
44
42
40
39
37
36
35
34
32
31
O
Receive data bus (Hi-Z on power up). These outputs carry 16-bit parallel data output from the transceiver
to the protocol device, synchronized to RX_CLK. The data is valid on the rising edge of RX_CLK as
shown in Figure 13. These terminals are in high-impedance state during power-on reset.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SLLS428F − JUNE 2000 − REVISED JANUARY 2004
Terminal Functions (Continued)
TERMINAL
NAME
NO.
TYPE
DESCRIPTION
RX_CLK
41
O
Recovered clock (low on power up). Output clock that is synchronized to RXD, RX_ER,
RX_DV/LOS. RX_CLK is the recovered serial data rate clock divided by 20. RX_CLK is held low
during power-on reset.
RX_ER/
PRBS_PASS
29
O
Receive error (Hi-Z on power up). When RX_ER and RX_DV/LOS are asserted, indicates that
an error was detected somewhere in the frame presently being output on the receive data bus.
When RX_ER is asserted and RX_DV/LOS is deasserted, indicates that carrier extension data
is being presented. RX_ER is in high-impedance state during power-on reset.
When PRBSEN= low (deasserted), this terminal is used to indicate receive error (RX_ER).
When PRBSEN = high (asserted), this terminal indicates status of the PRBS test results
(High=pass).
RX_DV/
LOS
30
O
Receive data valid. RX_DV/LOS is output by the transceiver to indicate that recovered and
decoded data is being output on the receive data bus. RX_DV/LOS is asserted continously from
the first recovered word of the frame through the final recovered word and is deasserted prior
to the first rising edge of RX_CLK that follows the final word. RX_DV/LOS is in high-impedance
state during power-on reset.
If, during normal operation, the differential signal amplitude on the serial receive pins is below
200 mV, RX_DV/LOS is asserted high along with RX_ER and the receive data bus to indicate
a loss of signal condition. If the device is in power-down mode, RX_DV/LOS is the output of the
signal detect circuit and is asserted low when a loss of signal condition is detected.
TESTEN
27
I
Test mode enable (w/pulldown). This terminal should be left unconnected or tied low.
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
TXD8
TXD9
TXD10
TXD11
TXD12
TXD13
TXD14
TXD15
62
63
64
2
3
4
6
7
10
11
12
14
15
16
17
19
I
Transmit data bus. These inputs carry the 16-bit parallel data output from a protocol device to
the transceiver for encoding, serialization, and transmission. This 16-bit parallel data is clocked
into the transceiver on the rising edge of GTX_CLK as shown in Figure 10.
TX_EN
20
I
Transmit enable (w/pulldown). TX_EN in combination with TX_ER indicates the protocol device
is presenting data on the transmit data bus for transmission. TX_EN must be asserted high with
the first word of the preamble and remain asserted while all words to be transmitted are
presented on the transmit data bus(TXD). TX_EN must be negated prior to the first rising edge
of GTX_CLK following the final word of a frame.
TX_ER
22
I
Transmit error coding (w/pulldown). When TX_ER and TX_EN are high, indicates that the
transceiver generates an error somewhere in the frame presently being transferred. When
TX_ER is asserted and TX_EN is deasserted, indicates the protocol device is presenting carrier
extension data. When TX_ER is deasserted with TX_EN asserted, indicates that normal data
is being presented.
VDD
1, 9,
23, 38,
48
Digital logic power. Provides power for all digital circuitry and digital I/O buffers.
VDDA
55, 57
Analog power. VDDA provides a supply reference for the high-speed analog circuits, receiver and
transmitter
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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