SAM L22 - Summary

SAM L22 - Summary
SMART ARM-based Microcontroller
SAM L22G / L22J / L22N Summary
DATASHEET SUMMARY
Introduction
®
Atmel | SMART SAM L22 is a series of Ultra low-power segment LCD
®
®
microcontrollers using the 32-bit ARM Cortex -M0+ processor, ranging from
48- to 100-pins with up to 256KB Flash and 32KB of SRAM and to drive up
to 320 LCD segments. The SAM L22 devices operate at a maximum
®
frequency of 32MHz and reach 2.46 CoreMark /MHz. With sophisticated
power management technologies the SAM L22 devices run down to
39µA/MHz (CPU running CoreMark) in active mode and down to 490nA in
ultra low-power backup mode with RTC.
Features
•
Processor
– ARM Cortex-M0+ CPU running at up to 32MHz
• Single-cycle hardware multiplier
• Micro Trace Buffer
• Memory Protection Unit (MPU)
•
Memories
– 64/128/256KB in-system self-programmable Flash
– 2/4/8KB Flash Read-While-Write section
– 8/16/32KB SRAM Main Memory
•
System
– Power-on reset (POR) and programmable brown-out detection
(BOD)
– Internal and external clock options
– External Interrupt Controller (EIC)
• 16 external interrupts that can use any I/O-Pin
–
•
• One non-maskable interrupt on one I/O-Pin
Two-pin Serial Wire Debug (SWD)
Low Power
– Idle, Standby, Backup, and Off sleep modes
– SleepWalking peripherals
Atmel-42402C-SAM L22_Datasheet_Summary-01/2016
–
–
–
–
–
–
–
•
Battery backup support
Two runtime selectable power/performance levels
Embedded Buck/LDO regulator supporting on-the-fly selection
Active mode: <50µA/MHz
Standby with full retention, RTC and LCD = 3.47µA
• 2.1µs wake-up time
Standby with full retention and RTC: 1.87µA
• 2.1µs wake-up time
Ultra low power Backup mode with RTC: 490nA
• 90µs wake-up time
Peripherals
– Segment LCD controller
• Up to 8 (4) common and 40 (44) segment terminals to drive 320 (176) segments
• Static, ½, 1/3, ¼ bias
• Internal charge pump able to generate VLCD higher than VDDIO
– 16-channel Direct Memory Access Controller (DMAC)
– 8-channel Event System
– Up to four 16-bit Timer/Counters (TC), each configurable as:
• 16-bit TC with two compare/capture channels
• 8-bit TC with two compare/capture channels
• 32-bit TC with two compare/capture channels, by using two TCs
– One 24-bit Timer/Counters for Control (TCC), with extended functions:
• Four compare channels with optional complementary output
• Generation of synchronized pulse width modulation (PWM) pattern across port pins
• Deterministic fault protection, fast decay and configurable dead-time between
complementary output
• Dithering that increase resolution with up to 5 bit and reduce quantization error
– Frequency Meter
– 32-bit Real Time Counter (RTC) with clock/calendar function
• 4x32-bit Backup Register
• Tamper Detection
– Watchdog Timer (WDT)
– CRC-32 generator
– One full-speed (12Mbps) Universal Serial Bus (USB) 2.0 Device
• Eight endpoints
• Crystal less operation
– Up to six Serial Communication Interfaces (SERCOM), each configurable as:
• USART with full-duplex and single-wire half-duplex configuration
• ISO7816
• I2C up to 3.4MHz1
• SPI
– One AES encryption engine
1
Max 1 high-speed mode and max 3 fast mode I2C
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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2
–
–
–
–
–
One True Random Generator (TRNG)
One Configurable Custom Logic (CCL)
One 12-bit, 1MSPS Analog-to-Digital Converter (ADC) with up to 20 channels
• Differential and single-ended input
• Oversampling and decimation in hardware to support 13-, 14-, 15-, or 16-bit resolution
Two Analog Comparators (AC) with window compare function
Peripheral Touch Controller (PTC)
• Up to 256-Channel capacitive touch sensing
–
–
•
Maximum Mutual-Cap up to 16x16 channels
Maximum Self-Cap up to 24 channels
Oscillators
– 32.768kHz crystal oscillator (XOSC32K)
– 0.4-32MHz crystal oscillator (XOSC)
– 32.768kHz ultra-low-power internal oscillator (OSCULP32K)
– 16/12/8/4MHz high-accuracy internal oscillator (OSC16M)
– 48MHz Digital Frequency Locked Loop (DFLL48M)
– 96MHz Fractional Digital Phased Locked Loop (FDPLL96M)
I/O
– Up to 82 programmable I/O pins
– Up to 52 segment LCD pins can be used as GPIO/GPI
– Up to 5 wake-up pins with optional debouncing
– Up to 5 tamper input pins
– 1 tamper output pin
•
•
•
Pin and code compatible with SAM D and SAM L Cortex-M0+ Families2
Packages
– 100-pin TQFP
– 64-pin TQFP, QFN
– 48-pin TQFP, QFN
•
Operating Voltage
– 1.62V – 3.63V
2
except the VLCD
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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Table of Contents
Introduction......................................................................................................................1
Features ......................................................................................................................... 1
1. Description.................................................................................................................6
2. Configuration Summary............................................................................................. 7
3. Ordering Information..................................................................................................9
3.1.
3.2.
3.3.
3.4.
SAM L22N.................................................................................................................................... 9
SAM L22J.....................................................................................................................................9
SAM L22G..................................................................................................................................10
Device Identification................................................................................................................... 10
4. Block Diagram..........................................................................................................11
5. Pinout.......................................................................................................................13
5.1.
5.2.
5.3.
SAM L22G..................................................................................................................................13
SAM L22J...................................................................................................................................13
SAM L22N.................................................................................................................................. 14
6. Signal Descriptions List .......................................................................................... 15
7. I/O Multiplexing and Considerations........................................................................ 18
7.1.
7.2.
Multiplexed Signals.....................................................................................................................18
Other Functions..........................................................................................................................20
8. Power Supply and Start-Up Considerations............................................................ 23
8.1.
8.2.
8.3.
Power Domain Overview............................................................................................................23
Power Supply Considerations.................................................................................................... 23
Power-Up....................................................................................................................................26
8.4.
8.5.
Power-On Reset and Brown-Out Detector................................................................................. 26
Performance Level Overview..................................................................................................... 27
9. Product Mapping......................................................................................................28
10. Memories.................................................................................................................29
10.1.
10.2.
10.3.
10.4.
10.5.
Embedded Memories................................................................................................................. 29
Physical Memory Map................................................................................................................ 29
NVM User Row Mapping............................................................................................................30
NVM Software Calibration Area Mapping...................................................................................31
Serial Number.............................................................................................................................31
11. Processor and Architecture..................................................................................... 32
11.1. Cortex M0+ Processor................................................................................................................32
11.2. Nested Vector Interrupt Controller..............................................................................................34
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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11.3. Micro Trace Buffer...................................................................................................................... 35
11.4. High-Speed Bus System............................................................................................................ 36
12. Packaging Information.............................................................................................40
12.1. Thermal Considerations............................................................................................................. 40
12.2. Package Drawings......................................................................................................................41
12.3. Soldering Profile......................................................................................................................... 46
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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5
1.
Description
Atmel | SMART SAM L22 is a series of Ultra low-power segment LCD microcontrollers using the 32-bit
ARM® Cortex®-M0+ processor, ranging from 48- to 100-pins with up to 256KB Flash and 32KB of SRAM
and can drive up to 320 LCD segments. The SAM L22 devices operate at a maximum frequency of
32MHz and reach 2.46 Coremark/MHz. They are designed for simple and intuitive migration with identical
peripheral modules, hex compatible code, identical linear address map and pin compatible migration
paths between all devices in the product series. All devices include intelligent and flexible peripherals,
Atmel Event System for inter-peripheral signaling, and support for capacitive touch button, slider and
wheel user interfaces.
The Atmel SAM L22 devices provide the following features: Segment LCD (SLCD) controller with up to 48
selectable SLCD pins from max. 52 pins to drive up to 320 segments, all SLCD Pins can be used also as
GPIOs (100-pin package: 8 of the SLCD pins can be used only as GP input), in-system programmable
Flash, sixteen-channel direct memory access (DMA) controller, 8 channel Event System, programmable
interrupt controller, up to 82 programmable I/O pins, 32-bit real-time clock and calendar, up to four 16-bit
Timer/Counters (TC) and one 24-bit Timer/Counters for Control (TCC), where each TC can be configured
to perform frequency and waveform generation, accurate program execution timing or input capture with
time and frequency measurement of digital signals. The TCs can operate in 8- or 16-bit mode, selected
TCs can be cascaded to form a 32-bit TC, and the TCC has extended functions optimized for motor,
lighting and other control applications. The series provide one full-speed USB 2.0 device interface; up to
six Serial Communication Modules (SERCOM) that each can be configured to act as an USART, UART,
SPI, I2C up to 3.4MHz, SMBus, PMBus, and ISO7816 smart card interface; up to twenty channel 1Msps
12-bit ADC with optional oversampling and decimation supporting up to 16-bit resolution, two analog
comparators with window mode, Peripheral Touch Controller supporting up to 256 buttons, sliders, wheels
and proximity sensing; programmable Watchdog Timer, brown-out detector and power-on reset and twopin Serial Wire Debug (SWD) program and debug interface.
All devices have accurate and low-power external and internal oscillators. All oscillators can be used as a
source for the system clock. Different clock domains can be independently configured to run at different
frequencies, enabling power saving by running each peripheral at its optimal clock frequency, and thus
maintaining a high CPU frequency while reducing power consumption.
The SAM L22 devices have four software-selectable sleep modes, idle, standby, backup and off. In idle
mode the CPU is stopped while all other functions can be kept running. In standby all clocks and
functions are stopped expect those selected to continue running. In this mode all RAMs and logic
contents are retained. The device supports SleepWalking. This feature allows the peripheral to wake up
from sleep based on predefined conditions, and thus allows some internal operation like DMA transfer
and/or the CPU to wake up only when needed, e.g. when a threshold is crossed or a result is ready. The
Event System supports synchronous and asynchronous events, allowing peripherals to receive, react to
and send events even in standby mode.
The SAM L22 devices have two software-selectable performance level (PL0 and PL2) allowing the user
to scale the lowest core voltage level that will support the operating frequency.
The Flash program memory can be reprogrammed in-system through the SWD interface. The same
interface can be used for nonintrusive on-chip debugging of application code. A boot loader running in the
device can use any communication interface to download and upgrade the application program in the
Flash memory.
The Atmel SAM L22 devices are supported with a full suite of program and system development tools,
including C compilers, macro assemblers, program debugger/simulators, programmers and evaluation
kits.
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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2.
Configuration Summary
SAM L22N
SAM L22J
SAM L22G
Pins
100
64
48
General Purpose I/Opins (GPIOs)
82
50
36
Flash
256/128/64KB
256/128/64KB
256/128/64KB
Flash RWW section
8/4/2KB
8/4/2KB
8/4/2KB
System SRAM
32/16/8KB
32/16/8KB
32/16/8KB
Segment LCD (SLCD)
Pins3
48 selectable from 52
31
23
Timer Counter (TC)
instances
4
4
4
Waveform output
channels per TC
instance
2
2
2
Timer Counter for
1
Control (TCC) instances
1
1
Waveform output
channels per TCC
4
4
4
DMA channels
16
16
16
USB interface
1
1
1
AES engine
1
1
1
Configurable Custom
Logic (CCL) (LUTs)
4
4
4
True Random Generator 1
(TRNG)
1
1
Serial Communication
Interface (SERCOM)
instances
6
4
3
Analog-to-Digital
Converter (ADC)
channels
20
16
10
4
2
Two Analog
4
Comparators (AC) with
number of external input
channels
3
All SLCD Pins can be configured also as GPIOs. For the 100-pin package, 44 SLCD Pins can be
configured as GPIOs, 8 SLCD Pins can be used as GP input.
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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SAM L22N
SAM L22J
SAM L22G
Tamper Input Pins
5
3
2
Wake-up Pins with
debouncing
5
3
2
Real-Time Counter
(RTC)
Yes
Yes
Yes
RTC alarms
1
1
1
RTC compare values
One 32-bit value or
One 32-bit value or
One 32-bit value or
two 16-bit values
two 16-bit values
two 16-bit values
External Interrupt lines
16
16
16
Peripheral Touch
Controller (PTC)
channels (X- x Y-lines)
for mutual capacitance4
256 (16x16)
182 (13x14)
132 (11x12)
Peripheral Touch
Controller (PTC)
channels for self
capacitance (Y-lines
only)5
24
19
15
Maximum CPU
frequency
32MHz
32MHz
32MHz
Packages
TQFP
QFN
QFN
TQFP
TQFP
Oscillators
32.768kHz crystal oscillator (XOSC32K)
0.4-32MHz crystal oscillator (XOSC)
32KHz ultra-low-power internal oscillator (OSCULP32K)
16/12/8/4MHz high-accuracy internal oscillator (OSC16M)
48MHz Digital Frequency Locked Loop (DFLL48M)
96MHz Fractional Digital Phased Locked Loop (FDPLL96M)
Event System channels
8
8
8
SW Debug Interface
Yes
Yes
Yes
Watchdog Timer (WDT)
Yes
Yes
Yes
4
5
The number of X- and Y-lines depends on the configuration of the device, as some I/O lines can be
configured as either X-lines or Y-lines.
The number of Y-lines depends on the configuration of the device, as some I/O lines can be
configured as either X-lines or Y-lines. The number given here is the maximum number of Y-lines
that can be obtained.
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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8
3.
Ordering Information
SAML 22 G 16 A - M U T
Product Family
Package Carrier
SAML = Low Power GP Microcontroller
T = Tape and Reel
Product Series
22 = Cortex M0 + CPU, Advanced Feature Set
+ DMA + USB + SLCD
Package Grade
U = 40 - 85 C Matte Sn Plating
O
Pin Count
Package Type
G = 48 Pins
J = 64 Pins
N = 100 Pins
A = TQFP
M = QFN
Flash Memory Density
18 = 256KB
17 = 128KB
16 = 64KB
Device Variant
A = Default Variant
Note: The Device Variant is independent of the Die Revision (Revision bit in the Device Identification
register of the Device Service Unit, DSU.DID.REVISION).
3.1.
SAM L22N
Table 3-1. SAM L22N Ordering Codes
Ordering Code
3.2.
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
ATSAML22N16A-AUT
64K
8K
TQFP100
Tape & Reel
ATSAML22N17A-AUT
128K
16K
TQFP100
Tape & Reel
ATSAML22N18A-AUT
256K
32K
TQFP100
Tape & Reel
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
64K
8K
TQFP64
Tape & Reel
SAM L22J
Table 3-2. SAM L22J Ordering Codes
Ordering Code
ATSAML22J16A-AUT
ATSAML22J16A-MUT
ATSAML22J17A-AUT
ATSAML22J17A-MUT
QFN64
128K
16K
TQFP64
Tape & Reel
QFN64
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
256K
32K
TQFP64
Tape & Reel
ATSAML22J18A-AUT
ATSAML22J18A-MUT
3.3.
QFN64
SAM L22G
Table 3-3. SAM L22G Ordering Codes
Ordering Code
ATSAML22G16A-AUT
FLASH (bytes)
SRAM (bytes)
Package
Carrier Type
64K
8K
TQFP48
Tape & Reel
ATSAML22G16A-MUT
ATSAML22G17A-AUT
QFN48
128K
16K
TQFP48
ATSAML22G17A-MUT
ATSAML22G18A-AUT
QFN48
256K
32K
TQFP48
ATSAML22G18A-MUT
3.4.
Tape & Reel
Tape & Reel
QFN48
Device Identification
The DSU - Device Service Unit peripheral provides the Device Selection bits in the Device Identification
register (DID.DEVSEL) in order to identify the device by software. The SAM L22 variants have a reset
value of DID=0x10820xxx, with the last digits identifying the variant:
Table 3-4. SAM L22 Device Identification Values
DSU DID.DEVSEL
Device
0x0
L22N18
0x1
L22N17
0x2
L22N16
0x3-0x4
Reserved
0x5
L22J18
0x6
L22J17
0x7
L22J16
0x8-0x9
Reserved
0xA
L22G18
0xB
L22G17
0xC
L22G16
0xD-0xFF
Reserved
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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10
Block Diagram
SERIAL
WIRE
EVENT
DEVICE
SERVICE
UNIT
32/16/8KB
RAM
NVM
CONTROLLER
Cache
SRAM
CONTROLLER
M
M
M
M
HIGH SPEED
BUS MATRIX
S
S
PERIPHERAL
ACCESS CONTROLLER
AHB-APB
BRIDGE B
S
S
USB FS
DEVICE
S
AHB-APB
BRIDGE A
DMA
EVENT
DP
DM
SOF-1KHz
AHB-APB
BRIDGE C
EVENT
CORTEX-M0+
PROCESSOR
Fmax 32MHz
256/128/64KB
8/4/2KB RWW
NVM
EVENT SYSTEM
MAIN CLOCKS
CONTROLLER
DMA
6/4/3x
6 x SERCOM
SERCOM
OSCILLATORS CONTROLLER
OSC16M
XIN
XOUT
XOSC
DFLL48M
FDPLL96M
DMA
4x TIMER / COUNTER
8 x Timer Counter
GCLK_IO[4..0]
GENERIC CLOCK
CONTROLLER
1x TIMER / COUNTER
FOR CONTROL
EXTERNAL INTERRUPT
CONTROLLER
POWER
MANAGER
WO0
WO1
EVENT
WO7
DMA
AIN[19..0]
20-CHANNEL
12-bit ADC 1MSPS
EVENT
XIN32
XOUT32
WO0
WO1
EVENT
DMA
WATCHDOG
TIMER
EXTINT[15..0]
NMI
PAD0
PAD1
PAD2
PAD3
PORT
SWCLK
SWDIO
MEMORY
TRACE BUFFER
IOBUS
PORT
4.
VREFA
VREFB
OSC32K CONTROLLER
XOSC32K
OSCULP32K
2 ANALOG
COMPARATORS
SUPPLY CONTROLLER
BOD33
AIN[3..0]
EVENT
VREF
DMA
SLCD
CONTROLLER
VREG
LP[51:0]
COM[7:0]
EVENT
RESETN
TAMPER[4:0]
RESET
CONTROLLER
REAL TIME
COUNTER
DMA
EVENT
EVENT
PERIPHERAL
TOUCH
CONTROLLER
XY[23..0]
X[31..24]
IN[11..0]
FREQUENCY
METER
4 x CCL
OUT[3..0]
EVENT
Note: Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
Atmel-42402C-SAM L22_Datasheet_Summary-01/2016
11
1.
Some device configurations have different number of SERCOM instances, Timer/Counter
instances, PTC signals and ADC signals. The number of PTC X and Y signals is configurable.
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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12
GNDANA
VDDCORE
RESET
PA27
PB23
PB22
40
39
38
37
VDDOUT
43
41
VDDIO
44
42
PA31
PA30
45
PB2
PA0
1
36
VDDIO
PA1
2
35
GND
PA2
3
34
PA25
PA3
4
33
PA24
32
PA23
31
PA22
30
PA21
29
PA20
GND
5
VDDANA
6
PB8
7
PB9
8
PA4
9
28
PA19
PA5
10
27
PA18
PA6
11
26
PA17
PA7
12
25
PA16
RESET
52
24
PA15
VDDCORE
53
23
PA14
GND
54
22
PA13
VDDOUT
55
21
PA12
VDDIO
56
20
PB11
PA30
57
19
VLCD
PA31
58
18
GND
59
17
VDDIO
PB31
PB30
60
PA11
PB0
61
16
PA10
PB1
62
15
14
PB2
63
PA9
PB3
64
PA8
13
SAM L22
48-pins
PA27
PB23
PB22
51
50
49
SAM L22J
PA0
1
48
VDDIO
PA1
2
47
GND
PA2
3
46
PA25
PA3
4
45
PA24
PB4
5
44
PA23
PB5
6
43
PA22
GNDANA
7
42
PA21
VDDA
8
41
PA20
PB6
9
40
PB17
PB7
10
39
PB16
PB8
11
38
PA19
PB9
12
37
PA18
PA4
13
36
PA17
PA5
14
35
PA16
PA6
15
34
VDDIO
PA7
16
33
GND
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PA9
PA10
PA11
VDDIO
GND
VLCD
PB11
PB12
PB13
PB14
PB15
PA12
PA13
PA14
PA15
SAM L22
64-pins
PA8
5.2.
46
SAM L22G
PB3
5.1.
47
Pinout
48
5.
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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13
PC25
PC24
PB25
PB24
PB23
83
82
81
80
79
GND
PC26
84
76
PC27
85
PB22
PC28
86
VDDIO
PA27
87
77
RESET
88
78
GND
VDDCORE
91
89
VDDOUT
92
90
PA30
VDDIO
93
PB31
96
PB30
PB0
97
PA31
PB1
98
94
PB2
99
95
PB3
100
SAM L22N
PA0
1
75
PA25
PA1
2
74
PA24
PC0
3
73
PA23
PC1
4
72
PA22
PC2
5
71
PA21
PC3
6
70
PA20
PA2
7
69
PB21
PA3
8
68
PB20
PB4
9
67
PB19
PB5
10
66
PB18
65
PB17
GND
11
VDDANA
12
PB6
13
PB7
14
PB8
15
SAM L22
100-pins
64
PB16
63
VDDIO
62
GND
61
PC21
PB9
16
60
PC20
PA4
17
59
PC19
PA5
18
58
PC18
PA6
19
57
PC17
PA7
20
56
PC16
PC5
21
55
PA19
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PC11
PC13
VDDIO
GND
VLCD
PB11
PB12
PB13
PB14
PB15
PC14
PC15
PA12
PA13
PA14
PA15
GND
PA11
PA10
PA9
PC12
VDDIO
32
VDDANA
31
PA16
51
PC10
52
25
PC9
24
30
GND
29
PA17
PC8
PA18
53
28
54
23
27
22
26
PC6
PC7
PA8
5.3.
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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6.
Signal Descriptions List
The following table gives details on signal names classified by peripheral.
Table 6-1. Signal Descriptions List
Signal Name
Function
Type
Active Level
Analog Comparators - AC
AIN[3:0]
AC Analog Inputs
Analog
CMP[1:0]
AC Analog Output
Analog
Analog Digital Converter - ADC
AIN[19:0]
ADC Analog Inputs
Analog
VREFA
ADC Voltage External Reference
A
Analog
VREFB
ADC Voltage External Reference
B
Analog
External Interrupt Controller - EIC
EXTINT[15:0]
External Interrupts inputs
Digital
NMI
External Non-Maskable Interrupt
input
Digital
Generic Clock Generator - GCLK
GCLK_IO[4:0]
Generic Clock (source clock
inputs or generic clock generator
output)
Digital
Custom Control Logic - CCL
IN[11:0]
Logic Inputs
Digital
OUT[3:0]
Logic Outputs
Digital
Supply Controller - SUPC
VBAT
External battery supply Inputs
Analog
PSOK
Main Power Supply OK input
Digital
OUT[1:0]
Logic Outputs
Digital
Reset input
Digital
Power Manager - PM
RESETN
Low
Serial Communication Interface - SERCOMx
PAD[3:0]
SERCOM Inputs/Outputs Pads
Digital
Oscillators Control - OSCCTRL
XIN
Crystal or external clock Input
Analog/Digital
XOUT
Crystal Output
Analog
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
Atmel-42402C-SAM L22_Datasheet_Summary-01/2016
15
Signal Name
Function
Type
Active Level
32KHz Oscillators Control - OSC32KCTRL
XIN32
32KHz Crystal or external clock
Input
Analog/Digital
XOUT32
32KHz Crystal Output
Analog
Waveform Outputs
Digital
Waveform Outputs
Digital
Timer Counter - TCx
WO[1:0]
Timer Counter - TCCx
WO[7:0]
Peripheral Touch Controller - PTC
X[7:0]
PTC Input/Output
Analog
Y[23:0]
PTC Input/Output
Analog
X[31:24]
PTC Output
Analog
General Purpose I/O - PORT
PA25 - PA00
Parallel I/O Controller I/O Port A
Digital
PA27
Parallel I/O Controller I/O Port A
Digital
PA31 - PA30
Parallel I/O Controller I/O Port A
Digital
PB09 - PB00
Parallel I/O Controller I/O Port B
Digital
PB25 - PB11
Parallel I/O Controller I/O Port B
Digital
PB31 - PB30
Parallel I/O Controller I/O Port B
Digital
PC03 - PC00
Parallel I/O Controller I/O Port C
Digital
PC07 - PC05
Parallel I/O Controller I/O Port C
Digital
PC17 - PC12
Parallel I/O Controller I/O Port C
Digital
PC28 - PC24
Parallel I/O Controller I/O Port C
Digital
General Purpose input - PORT
PC11 - PC08
Parallel I/O Controller input Port
C
Digital
PC21 - PC18
Parallel I/O Controller input Port
C
Digital
SLCD51 - SLCD00
Segment LCD
Analog
VLCD
Bias Voltage
Analog
Segment LCD
Universal Serial Bus - USB
DP
DP for USB
Digital
DM
DM for USB
Digital
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
Atmel-42402C-SAM L22_Datasheet_Summary-01/2016
16
Signal Name
Function
Type
SOF 1kHz
USB Start of Frame
Digital
Active Level
Real Timer Clock - RTC
RTC_IN[4:0]
Tamper or external wake-up pins
Digital
RTC_OUT
Tamper output
Digital
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
Atmel-42402C-SAM L22_Datasheet_Summary-01/2016
17
7.
I/O Multiplexing and Considerations
7.1.
Multiplexed Signals
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be
assigned a different peripheral functions. To enable a peripheral function on a pin, the Peripheral
Multiplexer Enable bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n =
0-31) in the PORT must be written to '1'. The selection of peripheral function A to I is done by writing to
the Peripheral Multiplexing Odd and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O)
of the PORT.
This table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 7-1. PORT Function Multiplexing
Function
-
Type
QFP48
(48)
QFP64
(64)
TQFP100
(100)
Pad Name EIC
A
B
Battery backup
1
1
1
PA00
EIC/EXTINT[0]
SERCOM1/
PAD[0]
2
2
2
PA01
EIC/EXTINT[1]
SERCOM1/
PAD[1]
3
PC00
EIC/EXTINT[8]
ADC/
AIN[16]
RTC/IN[3]
4
PC01
EIC/EXTINT[9]
ADC/
AIN[17]
RTC/IN[4]
5
PC02
EIC/EXTINT[10]
ADC/
AIN[18]
PTC/
XY[6]
6
PC03
EIC/EXTINT[11]
ADC/
AIN[19]
PTC/
XY[7]
ANAREF ADC
AC
PTC
SLCD
C
D
E
SERCOM
SERCOM
TC/TCC
F
TCC/RT COM/RTC
C
H
I
AC/
GCLK/
SUPC
CCL
3
3
7
PA02
EIC/EXTINT[2]
ADC/
VREFB
ADC/
AIN[0]
AC/
PTC/
AIN[0] XY[8]
4
4
8
PA03
EIC/EXTINT[3]
ADC/
VREFA
ADC/
AIN[1]
AC/
PTC/
AIN[1] XY[9]
RTC/IN[2]
5
9
PB04
EIC/EXTINT[4]
ADC/
AIN[12]
AC/
PTC/
AIN[2] XY[10]
6
10
PB05
EIC/EXTINT[5]
ADC/
AIN[13]
AC/
PTC/
AIN[3] XY[11]
9
13
PB06
EIC/EXTINT[6]
ADC/
AIN[14]
PTC/
XY[12]
SLCD/
LP[0]
CCL/IN[6]
10
14
PB07
EIC/EXTINT[7]
ADC/
AIN[15]
PTC/
XY[13]
SLCD/
LP[1]
CCL/IN[7]
7
11
15
PB08
EIC/EXTINT[8]
ADC/
AIN[2]
PTC/
XY[14]
SLCD/
LP[2]
SERCOM3/
PAD[0]
TC/0/
WO[0]
CCL/IN[8]
8
12
16
PB09
EIC/EXTINT[9]
ADC/
AIN[3]
PTC/
XY[15]
SLCD/
LP[3]
SERCOM3/
PAD[1]
TC/0/
WO[1]
CCL/
OUT[2]
9
13
17
PA04
EIC/EXTINT[4]
ADC/
AIN[4]
PTC/
X[24]
SLCD/
LP[4]
SERCOM0/
PAD[0]
TCC/
WO[0]
CCL/IN[0]
10
14
18
PA05
EIC/EXTINT[5]
ADC/
AIN[5]
PTC/
X[25]
SLCD/
LP[5]
SERCOM0/
PAD[1]
TCC/
WO[1]
CCL/IN[1]
11
15
19
PA06
EIC/EXTINT[6]
ADC/
AIN[6]
PTC/
X[26]
SLCD/
LP[6]
SERCOM0/
PAD[2]
CCL/IN[2]
12
16
20
PA07
EIC/EXTINT[7]
ADC/
AIN[7]
PTC/
X[27]
SLCD/
LP[7]
SERCOM0/
PAD[3]
CCL/
OUT[0]
21
PC05
EIC/EXTINT[13]
PTC/
XY[4]
SLCD/
LP[8]
22
PC06
EIC/EXTINT[14]
PTC/
XY[5]
SLCD/
LP[9]
23
PC07
EIC/EXTINT[15]
SLCD/
LP[10]
13
17
26
PA08
EIC/NMI
PTC/
XY[3]
SLCD/
LP[11]
SERCOM0/
PAD[0]
SERCOM4/
PAD[0]
TCC/
WO[0]
CCL/IN[3]
14
18
27
PA09
EIC/EXTINT[9]
PTC/
XY[2]
SLCD/
LP[12]
SERCOM0/
PAD[1]
SERCOM4/
PAD[1]
TCC/
WO[1]
15
19
28
PA10
EIC/EXTINT[10]
PTC/
XY[1]
SLCD/
LP[13]
SERCOM0/
PAD[2]
SERCOM4/
PAD[2]
TCC/
WO[2]
16
20
29
PA11
EIC/EXTINT[11]
PTC/
XY[0]
SLCD/
LP[14]
SERCOM0/
PAD[3]
SERCOM4/
PAD[3]
TCC/
WO[3]
CCL/IN[4]
GCLK/
IO[4]
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
Atmel-42402C-SAM L22_Datasheet_Summary-01/2016
CCL/IN[5]
CCL/
OUT[1]
18
Function
-
Type
QFP48
(48)
A
QFP64
(64)
digital: input only
B
ANAREF ADC
AC
PTC
SLCD
C
D
E
SERCOM
SERCOM
TC/TCC
TCC/RT COM/RTC
C
SERCOM3/
PAD[3]
TC/1/
WO[1]
TCC/
WO[5]
TQFP100
(100)
Pad Name EIC
30
PC08
EIC/EXTINT[0]
SLCD/
LP[15]
31
PC09
EIC/EXTINT[1]
SLCD/
LP[16]
32
PC10
EIC/EXTINT[2]
SLCD/
LP[17]
SERCOM1/
PAD[2]
33
PC11
EIC/EXTINT[3]
SLCD/
LP[18]
SERCOM1/
PAD[3]
34
PC12
EIC/EXTINT[4]
SLCD/
LP[19]
SERCOM1/
PAD[0]
35
PC13
EIC/EXTINT[5]
SLCD/
LP[20]
SERCOM1/
PAD[1]
F
H
I
AC/
GCLK/
SUPC
CCL
19
23
38
VLCD
20
24
39
PB11
EIC/EXTINT[11]
SLCD/
LP[21]
25
40
PB12
EIC/EXTINT[12]
SLCD/
LP[22]
SERCOM3/
PAD[0]
TC/0/
WO[0]
TCC/
WO[6]
26
41
PB13
EIC/EXTINT[13]
SLCD/
LP[23]
SERCOM3/
PAD[1]
TC/0/
WO[1]
TCC/
WO[7]
27
42
PB14
EIC/EXTINT[14]
SLCD/
LP[24]
SERCOM3/
PAD[2]
TC/1/
WO[0]
GCLK/
IO[0]
CCL/IN[9]
28
43
PB15
EIC/EXTINT[15]
SLCD/
LP[25]
SERCOM3/
PAD[3]
TC/1/
WO[1]
GCLK/
IO[1]
CCL/
IN[10]
44
PC14
EIC/EXTINT[6]
SLCD/
LP[26]
45
PC15
EIC/EXTINT[7]
SLCD/
LP[27]
I2C: full Fm+.
Limited currents
for Sm, Fm
CCL/
OUT[1]
I2C: Sm, Fm, Fm 21
+
29
46
PA12
EIC/EXTINT[12]
SLCD/
LP[28]
SERCOM4/
PAD[0]
SERCOM3/
PAD[0]
TCC/
WO[6]
AC/
CMP[0]
22
30
47
PA13
EIC/EXTINT[13]
SLCD/
LP[29]
SERCOM4/
PAD[1]
SERCOM3/
PAD[1]
TCC/
WO[7]
AC/
CMP[1]
23
31
48
PA14
EIC/EXTINT[14]
SLCD/
LP[30]
SERCOM4/
PAD[2]
SERCOM3/
PAD[2]
TCC/
WO[4]
GCLK/
IO[0]
24
32
49
PA15
EIC/EXTINT[15]
SLCD/
LP[31]
SERCOM4/
PAD[3]
SERCOM3/
PAD[3]
TCC/
WO[5]
GCLK/
IO[1]
25
35
52
PA16
EIC/EXTINT[0]
PTC/
X[28]
SLCD/
LP[32]
SERCOM1/
PAD[0]
SERCOM2/
PAD[0]
TCC/
WO[6]
GCLK/
IO[2]
CCL/IN[0]
26
36
53
PA17
EIC/EXTINT[1]
PTC/
X[29]
SLCD/
LP[33]
SERCOM1/
PAD[1]
SERCOM2/
PAD[1]
TCC/
WO[7]
GCLK/
IO[3]
CCL/IN[1]
27
37
54
PA18
EIC/EXTINT[2]
PTC/
X[30]
SLCD/
LP[34]
SERCOM1/
PAD[2]
SERCOM2/
PAD[2]
TCC/
WO[2]
AC/
CMP[0]
CCL/IN[2]
28
38
55
PA19
EIC/EXTINT[3]
PTC/
X[31]
SLCD/
LP[35]
SERCOM1/
PAD[3]
SERCOM2/
PAD[3]
TCC/
WO[3]
AC/
CMP[1]
CCL/
OUT[0]
56
PC16
EIC/EXTINT[8]
SLCD/
LP[36]
57
PC17
EIC/EXTINT[9]
SLCD/
LP[37]
58
PC18
EIC/EXTINT[10]
SLCD/
LP[38]
59
PC19
EIC/EXTINT[11]
SLCD/
LP[39]
60
PC20
EIC/EXTINT[12]
SLCD/
LP[40]
CCL/IN[9]
61
PC21
EIC/EXTINT[13]
SLCD/
LP[41]
CCL/
IN[10]
39
64
PB16
EIC/EXTINT[0]
SLCD/
LP[42]
SERCOM5/
PAD[0]
TC/2/
WO[0]
TCC/
WO[4]
GCLK/
IO[2]
CCL/
IN[11]
40
65
PB17
EIC/EXTINT[1]
SLCD/
LP[43]
SERCOM5/
PAD[1]
TC/2/
WO[1]
TCC/
WO[5]
GCLK/
IO[3]
CCL/
OUT[3]
66
PB18
EIC/EXTINT[2]
SLCD/
LP[44]
SERCOM5/
PAD[2]
SERCOM3/
PAD[2]
TCC/
WO[0]
67
PB19
EIC/EXTINT[3]
SLCD/
LP[45]
SERCOM5/
PAD[3]
SERCOM3/
PAD[3]
TCC/
WO[1]
68
PB20
EIC/EXTINT[4]
SLCD/
LP[46]
SERCOM3/
PAD[0]
SERCOM5/
PAD[0]
TCC/
WO[2]
69
PB21
EIC/EXTINT[5]
SLCD/
LP[47]
SERCOM3/
PAD[1]
SERCOM5/
PAD[1]
TCC/
WO[3]
digital: input only
29
41
70
PA20
EIC/EXTINT[4]
PTC/
XY[16]
SLCD/
LP[48]
SERCOM0/
PAD[0]
SERCOM2/
PAD[2]
TC/3/
WO[0]
TCC/
WO[6]
GCLK/
IO[4]
30
42
71
PA21
EIC/EXTINT[5]
PTC/
XY[17]
SLCD/
LP[49]
SERCOM0/
PAD[1]
SERCOM2/
PAD[3]
TC/3/
WO[1]
TCC/
WO[7]
I2C: Sm, Fm, Fm 31
+
43
72
PA22
EIC/EXTINT[6]
PTC/
XY[18]
SLCD/
LP[50]
SERCOM0/
PAD[2]
SERCOM2/
PAD[0]
TC/0/
WO[0]
TCC/
WO[4]
32
44
73
PA23
EIC/EXTINT[7]
PTC/
XY[19]
SLCD/
LP[51]
SERCOM0/
PAD[3]
SERCOM2/
PAD[1]
TC/0/
WO[1]
TCC/
WO[5]
USB/SOF_1KHZ
CCL/IN[7]
33
45
74
PA24
EIC/EXTINT[12]
SERCOM2/
PAD[2]
SERCOM5/
PAD[0]
TC/1/
WO[0]
TCC/
WO[0]
USB/DM
CCL/IN[8]
34
46
75
PA25
EIC/EXTINT[13]
SERCOM2/
PAD[3]
SERCOM5/
PAD[1]
TC/1/
WO[1]
TCC/
WO[1]
USB/DP
CCL/
OUT[2]
37
49
78
PB22
EIC/EXTINT[6]
SERCOM0/
PAD[2]
SERCOM5/
PAD[2]
TC/3/
WO[0]
TCC/
WO[2]
USB/SOF_1KHZ GCLK/
IO[0]
CCL/IN[0]
CCL/IN[6]
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
Atmel-42402C-SAM L22_Datasheet_Summary-01/2016
19
Function
-
Type
QFP48
(48)
QFP64
(64)
TQFP100
(100)
Pad Name EIC
A
38
50
79
PB23
80
B
C
D
E
H
I
SERCOM
SERCOM
TC/TCC
TCC/RT COM/RTC
C
AC/
GCLK/
SUPC
CCL
EIC/EXTINT[7]
SERCOM0/
PAD[3]
SERCOM5/
PAD[3]
TC/3/
WO[1]
TCC/
WO[3]
GCLK/
IO[1]
CCL/
OUT[0]
PB24
EIC/EXTINT[8]
SERCOM0/
PAD[0]
SERCOM4/
PAD[0]
TCC/
WO[6]
AC/
CMP[0]
81
PB25
EIC/EXTINT[9]
SERCOM0/
PAD[1]
SERCOM4/
PAD[1]
TCC/
WO[7]
AC/
CMP[1]
82
PC24
EIC/EXTINT[0]
SERCOM0/
PAD[2]
SERCOM4/
PAD[2]
TC/2/
WO[0]
TCC/
WO[0]
83
PC25
EIC/EXTINT[1]
SERCOM0/
PAD[3]
SERCOM4/
PAD[3]
TC/2/
WO[1]
TCC/
WO[1]
84
PC26
EIC/EXTINT[2]
TC/3/
WO[0]
TCC/
WO[2]
85
PC27
EIC/EXTINT[3]
TC/3/
WO[1]
TCC/
WO[3]
CCL/IN[4]
86
PC28
EIC/EXTINT[4]
PTC/
XY[20]
TCC/
WO[4]
CCL/IN[5]
EIC/EXTINT[15]
PTC/
XY[21]
ANAREF ADC
AC
PTC
SLCD
SERCOM1/
PAD[0]
SERCOM1/
PAD[1]
recommended for 39
GCLK IO
51
87
PA27
40
52
88
RESET_N
45
57
93
PA30
EIC/EXTINT[10]
PTC/
XY[22]
46
58
94
PA31
EIC/EXTINT[11]
PTC/
XY[23]
59
95
PB30
EIC/EXTINT[14]
SERCOM1/
PAD[0]
SERCOM5/
PAD[0]
TCC/
WO[0]
60
96
PB31
EIC/EXTINT[15]
SERCOM1/
PAD[1]
SERCOM5/
PAD[1]
TCC/
WO[1]
I2C: Sm, Fm, Fm
+, Hs
Battery backup
F
TCC/
WO[5]
TAL/BRK
GCLK/
IO[0]
SERCOM1/
PAD[2]
CORTEX_M0P/
SWCLK
GCLK/
IO[0]
SERCOM1/
PAD[3]
SWDIO
61
97
PB00
EIC/EXTINT[0]
ADC/
AIN[8]
SERCOM3/
PAD[2]
SERCOM5/
PAD[2]
TC/3/
WO[0]
62
98
PB01
EIC/EXTINT[1]
ADC/
AIN[9]
SERCOM3/
PAD[3]
SERCOM5/
PAD[3]
TC/3/
WO[1]
47
63
99
PB02
EIC/EXTINT[2]
ADC/
AIN[10]
SERCOM3/
PAD[0]
SERCOM5/
PAD[0]
TC/2/
WO[0]
48
64
100
PB03
EIC/EXTINT[3]
ADC/
AIN[11]
SERCOM3/
PAD[1]
SERCOM5/
PAD[1]
TC/2/
WO[1]
RTC/
IN[2]
CCL/IN[3]
CCL/
OUT[1]
RTC/IN[0]
SUPC/
PSOK
CCL/IN[1]
RTC/OUT
SUPC/
OUT[0]
CCL/IN[2]
RTC/IN[1]
SUPC/
OUT[1]
CCL/
OUT[0]
SUPC/
VBAT
Note: 1. All analog pin functions are on peripheral function B. Peripheral function B must be selected to
disable the digital control of the pin.
2. Only some pins can be used in SERCOM I2C mode. See the Type column for supported I2C
modes.
– Sm: Standard mode, up to 100kHz
– Fm: Fast mode, up to 400kHz
– Fm+: Fast mode Plus, up to 1MHz
– Hs: High-speed mode, up to 3.4MHz
3. These pins are High Sink pins and have different properties than regular pins:
PA12, PA13, PA22, PA23, PA27, PA31, PB30, PB31.
4. Clusters of multiple GPIO pins are sharing the same supply pin.
Related Links
Configuration Summary on page 7
SERCOM USART and I2C Configurations on page 21
7.2.
Other Functions
7.2.1.
Oscillator Pinout
The oscillators are not mapped to the normal PORT functions and their multiplexing is controlled by
registers in the Oscillators Controller (OSCCTRL) and in the 32K Oscillators Controller (OSC32KCTRL).
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
Atmel-42402C-SAM L22_Datasheet_Summary-01/2016
20
Table 7-2. Oscillator Pinout
Oscillator
Supply
Signal
I/O pin
XOSC
VDDIO
XIN
PB22
XOUT
PB23
XIN32
PA00
XOUT32
PA01
XOSC32K
VSWOUT
Note: In order to minimize the cycle-to-cycle jitter of the external oscillator, keep the neighboring pins as
steady as possible. For neighboring pin details, refer to the Oscillator Pinout section.
Table 7-3. XOSC32 Jitter Minimization
7.2.2.
Package Pin Count
Steady Signal Recommended
100
PB00, PB01, PB02, PB03, PC00, PC01
64
PB00, PB01, PB02, PB03, PA02, PA03
48
PB02, PB03, PA02, PA03
Serial Wire Debug Interface Pinout
Only the SWCLK pin is mapped to the normal PORT functions. A debugger cold-plugging or hot-plugging
detection will automatically switch the SWDIO port to the SWDIO function.
Table 7-4. Serial Wire Debug Interface Pinout
7.2.3.
Signal
Supply
I/O pin
SWCLK
VDDIO
PA30
SWDIO
VDDIO
PA31
SERCOM USART and I2C Configurations
The SAM L22 has up to six instances of the serial communication interface (SERCOM) peripheral. The
following table lists the supported communication protocols for each SERCOM instance.
Table 7-5. SERCOM USART and I2C Protocols
SERCOM Instance
Protocol
SERCOM0
SERCOM1
SERCOM2
SERCOM3
SERCOM4
SERCOM5
I2C
no
yes
yes
yes
yes
yes
I2C at
3.4MHz
no
yes
no
no
no
yes
USART
including
RS485 and
ISO 7816
yes
yes
yes
yes
yes
yes
SPI
yes
yes
yes
yes
yes
yes
Note: Not all available I2C pins support I2C mode at 3.4MHz.
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21
7.2.4.
GPIO Pin Clusters
Table 7-6. GPIO Clusters
Package Cluster GPIO
Supplies Pin connected to the cluster
100 pins
64 pins
48 pins
1
PA02, PA03, PB04, PB05, PC02, PC03
VDDANA pin12
GNDANA pin11
2
PA04, PA05, PA06, PA07, PB06, PB07, PB08, PB09, PC05, PC06, PC07
VDDANA pin12 VDDANA pin25 GNDANA pin11 GNDANA pin24
3
PA08, PA09, PA10, PA11, PC08, PC09, PC10, PC11, PC12, PC13
VDDIO pin36
GND pin37
4
PA12, PA13, PA14, PA15, PB11, PB12, PB13, PB14, PB15, PC14, PC15
VDDIO pin36 VDDIO pin51
GND pin37 GND pin50
5
PA16, PA17, PA18, PA19, PC16, PC17, PC18, PC19, PC20, PC21
VDDIO pin51 VDDIO pin63
GND pin50 GND pin62
6
PA20, PA21, PA22, PA23, PA24, PA25, PB16, PB17, PB18, PB19, PB20,
PB21
VDDIO pin63 VDDIO pin77
GND pin62 GND pin76
7
PA27, PB22, PB23, PB24, PB25, PC24, PC25, PC26, PC27, PC28
VDDIO pin77 VDDIO pin92
GND pin76 GND pin90
8
PA00, PA01, PA30, PA31, PB00, PB01, PB02, PB03, PB30, PB31,
PC00, PC01
VDDIO pin92
GND pin90
1
PA02, PA03, PA04, PA05, PA06, PA07, PB04, PB05, PB06, PB07, PB08,
PB09
VDDANA pin8
GNDANA pin7
2
PA08, PA09, PA10, PA11
VDDIO pin21
GND pin22
3
PA12, PA13, PA14, PA15, PB11, PB12, PB13, PB14, PB15
VDDIO pin21 VDDIO pin34
GND pin22 GND pin33
4
PA16, PA17, PA18, PA19, PA20, PA21, PA22, PA23, PA24, PA25, PB16,
PB17
VDDIO pin34 VDDIO pin48
GND pin33 GND pin47
5
PA27, PB22, PB23
VDDIO pin48 VDDIO pin56
GND pin47 GND pin54
6
PA00, PA01, PA30, PA31, PB00, PB01, PB02, PB03, PB30, PB31
VDDIO pin56
GND pin54
1
PA02, PA03, PA04, PA05, PA06, PA07, PB08, PB09
VDDANA pin6
GNDANA pin5
2
PA08, PA09, PA10, PA11
VDDIO pin17
GND pin18
3
PA12, PA13, PA14, PA15, PA16, PA17, PA18, PA19, PA20, PA21, PA22,
PA23, PA24, PA25, PB11,
VDDIO pin17 VDDIO pin36
GND pin18 GND pin35
4
PA27, PB22, PB23
VDDIO pin36 VDDIO pin44
GND pin35 GND pin42
5
PA00, PA01, PA30, PA31, PB02, PB03
VDDIO pin56
GND pin54
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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22
PB[9:4]
PC[3:2]
PC[7:5]
LCD
VOLTAGE
REGULATOR
BOD12
AC
ADC
PTC
VBAT (PB[3])
PB[31:11]
PA[31:8 ]
VBAT
VDDIO
VDDANA
PA[7:2]
PC[28:8]
VDDIO
VDDOUT
GND
VDDCORE
Power Domain Overview
VLCD
8.1.
GNDANA
Power Supply and Start-Up Considerations
VDDANA
8.
RTC, PM,
SUPC, RSTC
OSC16M
XOSC
VDDBU
VSWOUT
POR
VDDCORE
VOLTAGE
REGULATOR
PB[3:0]
BOD33
Digital Logic
OSCULP32K
CPU, Peripherals
PC[1:0]
XOSC32K
PA[1:0]
DFLL48M
FDPLL96M
The Atmel SAM L22 power domains are not independent of each other:
•
VDDCORE and VDDIO share GND, whereas VDDANA refers to GNDANA.
•
VDDCORE serves as the internal voltage regulator output.
•
VSWOUT and VDDBU are internal power domains.
8.2.
Power Supply Considerations
8.2.1.
Power Supplies
The Atmel SAM L22 has several different power supply pins:
•
VDDIO powers I/O lines and OSC16M, XOSC, the internal regulator for VDDCORE and the
Automatic Power Switch. Voltage is 1.62V to 3.63V
•
•
VDDANA powers I/O lines and the ADC, AC, LCD, and PTC. Voltage is 1.62V to 3.63V
VLCD has two alternative functions:
– Output of the LCD voltage pump when VLCD is generated internally. Output voltage is 2.5V to
3.5V.
– Supply input for the bias generator when VLCD is provided externally by the application. Input
voltage is 2.4 to 3.6V.
VBAT powers the Automatic Power Switch. Voltage is 1.62V to 3.63V
VDDCORE serves as the internal voltage regulator output. It powers the core, memories,
peripherals, DFLL48M and FDPLL96M. Voltage is 0.9V to 1.2V typical.
The Automatic Power Switch is a configurable switch that selects between VDDIO and VBAT as
supply for the internal output VSWOUT, see the figure in Power Domain Overview on page 23.
•
•
•
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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The same voltage must be applied to both VDDIO and VDDANA. This common voltage is referred to as
VDD in the datasheet.
The ground pins, GND, are common to VDDCORE, and VDDIO. The ground pin for VDDANA is
GNDANA.
For decoupling recommendations for the different power supplies, refer to the schematic checklist.
8.2.2.
Voltage Regulator
The SAM L22 internal Voltage Regulator has four different modes:
•
•
•
•
Linear mode : This is the default mode when CPU and peripherals are running. It does not require
an external inductor.
Switching mode. This is the most efficient mode when the CPU and peripherals are running. This
mode can be selected by software on the fly.
Low Power (LP) mode. This is the default mode used when the chip is in standby mode.
Shutdown mode. When the chip is in backup mode, the internal regulator is off.
Note that the Voltage Regulator modes are controlled by the Power Manager.
8.2.3.
Typical Powering Schematic
The SAM L22 uses a single supply from 1.62V to 3.63V.
The following figure shows the recommended power supply connection.
Figure 8-1. Power Supply Connection for Linear Mode Only
SAM L22
Main Supply
VDDANA
VBAT (PB03)
(1.62V — 3.63V)
VDDIO
VDDOUT
VDDCORE
GND
GNDANA
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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Figure 8-2. Power Supply Connection for Switching/Linear Mode
SAM L22
Main Supply
VBAT (PB03)
VDDANA
(1.62V — 3.63V)
VDDIO
VDDOUT
VDDCORE
GND
GNDANA
Figure 8-3. Power Supply Connection for Battery Backup
SAM L22
Main Supply
VBAT (PB03)
VDDANA
(1.62V — 3.63V)
VDDIO
VDDOUT
VDDCORE
GND
GNDANA
8.2.4.
Power-Up Sequence
8.2.4.1.
Supply Order
VDDIO and VDDANA must have the same supply sequence. Ideally, they must be connected together.
8.2.4.2.
Minimum Rise Rate
One integrated power-on reset (POR) circuits monitoring VDDIO requires a minimum rise rate.
8.2.4.3.
Maximum Rise Rate
The rise rate of the power supplies must not exceed the values described in Electrical Characteristics.
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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8.3.
Power-Up
This section summarizes the power-up sequence of the SAM L22. The behavior after power-up is
controlled by the Power Manager.
8.3.1.
Starting of Internal Regulator
After power-up, the device is set to its initial state and kept in Reset, until the power has stabilized
throughout the device. The default performance level after power-up is PL0.
The internal regulator provides the internal VDDCORE corresponding to this performance level. Once the
external voltage VDDIO and the internal VDDCORE reach a stable value, the internal Reset is released.
8.3.2.
Starting of Clocks
Once the power has stabilized and the internal Reset is released, the device will use a 4MHz clock by
default. The clock source for this clock signal is OSC16M, which is enabled and configured at 4MHz after
a reset by default. This is also the default time base for Generic Clock Generator 0. In turn, Generator 0
provides the main clock GCLK_MAIN which is used by the Power Manager (PM).
Some synchronous system clocks are active after Start-Up, allowing software execution. Refer to the
“Clock Mask Register” section in the PM-Power Manager documentation for the list of clocks that are
running by default. Synchronous system clocks that are running receive the 4MHz clock from Generic
Clock Generator 0. Other generic clocks are disabled.
8.3.3.
I/O Pins
After power-up, the I/O pins are tri-stated except PA30, which is pull-up enabled and configured as input.
8.3.4.
Fetching of Initial Instructions
After Reset has been released, the CPU starts fetching PC and SP values from the Reset address,
0x00000000. This points to the first executable address in the internal Flash memory. The code read from
the internal Flash can be used to configure the clock system and clock sources. See the related
peripheral documentation for details. Refer to the ARM Architecture Reference Manual for more
information on CPU startup (http://www.arm.com).
8.4.
Power-On Reset and Brown-Out Detector
The SAM L22 embeds three features to monitor, warn and/or reset the device:
•
POR: Power-on Reset on VSWOUT and VDDIO
•
BOD33: Brown-out detector on VSWOUT/VBAT
•
Brown-out detector internal to the voltage regulator for VDDCORE. BOD12 is calibrated in
production and its calibration parameters are stored in the NVM User Row. This data should not be
changed if the User Row is written to in order to assure correct behavior.
8.4.1.
Power-On Reset on VSWOUT
VSWOUT is monitored by POR. Monitoring is always activated, including startup and all sleep modes. If
VSWOUT goes below the threshold voltage, the entire chip is reset.
8.4.2.
Power-On Reset on VDDIO
VDDIO is monitored by POR. Monitoring is always activated, including startup and all sleep modes. If
VDDIO goes below the threshold voltage, all I/Os supplied by VDDIO are reset.
8.4.3.
Brown-Out Detector on VSWOUT/VBAT
BOD33 monitors VSWOUT or VBAT depending on configuration.
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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8.4.4.
Brown-Out Detector on VDDCORE
Once the device has started up, BOD12 monitors the internal VDDCORE.
8.5.
Performance Level Overview
By default, the device will start in Performance Level 0. This PL0 is aiming for the lowest power
consumption by limiting logic speeds and the CPU frequency. As a consequence, all GCLK will have
limited capabilities, and some peripherals and clock sources will not work or with limited capabilities:
List of peripherals/clock sources not available in PL0:
•
USB (limited by logic frequency)
•
DFLL48M
List of peripherals/clock sources with limited capabilities in PL0:
•
All AHB/APB peripherals are limited by CPU frequency
•
DPLL96M: may be able to generate 48MHz internally, but the output cannot be used by logic
•
GCLK: the maximum frequency is by factor 4 compared to PL2
•
SW interface: the maximum frequency is by factor 4 compared to PL2
•
TC: the maximum frequency is by factor 4 compared to PL2
•
TCC:the maximum frequency is by factor 4 compared to PL2
•
SERCOM: the maximum frequency is by factor 4 compared to PL2
List of peripherals/clock sources with full capabilities in PL0:
•
AC
•
ADC
•
EIC
•
OSC16M
•
PTC
•
All 32KHz clock sources and peripherals
Full functionality and capability will be ensured in PL2. When transitioning between performance levels,
the Supply Controller (SUPC) will provide a configurable smooth voltage scaling transition.
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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9.
Product Mapping
Figure 9-1. Atmel SAM L22 Product Mapping
Global Memory Space
0x00000000
Code
AHB-APB Bridge A
Code
0x00000000
0x00040000
0x20000000
SRAM
Internal
Flash
Reserved
0x1FFFFFFF
0x20008000
Reserved
0x40000000
Peripherals
Peripherals
0x40000000
0x60000000
Reserved
0x41000000
0x80000000
Undefined
0xE0000000
0xFFFFFFFF
System
0x42000000
AHB-APB
Bridge A
0x40000000
PM
0x40000800
MCLK
0x40000C00
RSTC
0x40001000
OSCTRL
0x40001400
OSC32KCTRL
EVSYS
0x42000400
SERCOM0
0x42000800
SERCOM1
0x42000C00
SERCOM2
0x42001000
SERCOM3
0x42001400
SERCOM4
0x42001800
SERCOM5
0x42001C00
TCC0
0x42002000
TC0
0x42002400
TC1
0x42002800
TC2
0x42002C00
TC3
USB
0x42003000
ADC
DSU
0x42003800
PTC
NVMCTRL
0x42003C00
SLCD
PORT
0x42004000
AES
DMAC
0x42004400
TRNG
MTB
0x42004800
CCL
HMATRIXHS
0x42004C00
Reserved
SUPC
0x40001C00
GCLK
0x40002000
0x40002400
0x40002800
0x40003000
0x40FFFFFF
WDT
RTC
EIC
FREQM
Reserved
AHB-APB
Bridge C
AHB-APB Bridge B
0x41000000
0x41002000
0x40004000
0x40006000
0x40008000
0x4000A000
0x4000C000
AHB-APB Bridge C
0x42000000
0x40001800
0x40002C00
AHB-APB
Bridge B
PAC
0x40000400
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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10.
Memories
10.1.
Embedded Memories
•
•
10.2.
Internal high-speed Flash with Read-While-Write (RWW) capability on a section of the array
Internal high-speed RAM, single-cycle access at full speed
Physical Memory Map
The high-speed bus is implemented as a bus matrix. All high-speed bus addresses are fixed, and they
are never remapped in any way, even during boot. The 32-bit physical address space is mapped as
follows:
Table 10-1. SAM L22 Physical Memory Map
Memory
Start address
Size [KB]
SAML22x18(1)
SAML22x17(1)
SAML22x16(1)
Embedded Flash
0x00000000
256
128
64
Embedded RWW section
0x00400000
8
4
2
Embedded SRAM
0x20000000
32
16
8
Peripheral Bridge A
0x40000000
64
64
64
Peripheral Bridge B
0x41000000
64
64
64
Peripheral Bridge C
0x42000000
64
64
64
IOBUS
0x60000000
0.5
0.5
0.5
Note: 1. x = G, J, or E.
Table 10-2. Flash Memory Parameters
Device
Flash size [KB]
Number of pages
Page size [Bytes]
SAML22x18(1)
256
4096
64
SAML22x17(1)
128
2048
64
SAML22x16(1)
64
1024
64
Note: 1. x = G, J, or E.
Table 10-3. RWW Section Parameters(1)
Device
Flash size [KB]
Number of pages
Page size [Bytes]
SAML22x18(1)
8
128
64
SAML22x17(1)
4
64
64
SAML22x16(1)
2
32
64
Note: 1. x = G, J, or E.
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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10.3.
NVM User Row Mapping
The Non Volatile Memory (NVM) User Row contains calibration data that are automatically read at device
power-on.
The NVM User Row can be read at address 0x00804000.
To write the NVM User Row refer to the documentation of the NVMCTRL - Non-Volatile Memory
Controller.
Note: When writing to the user row, the new values do not get loaded by the other modules on the
device until a device reset occurs.
Table 10-4. NVM User Row Mapping
Bit
Pos.
Name
Usage
Related Peripheral
Register
2:0
BOOTPROT
Used to select one of eight different bootloader sizes. NVMCTRL
3
Reserved
—
—
6:4
EEPROM
Used to select one of eight different EEPROM sizes.
NVMCTRL
7
Reserved
—
—
13:8
BOD33 Level
BOD33 threshold level at power-on.
SUPC.BOD33
14
BOD33 Disable
BOD33 Disable at power-on.
SUPC.BOD33
16:15
BOD33 Action
BOD33 Action at power-on.
SUPC.BOD33
22:17
BOD12 Level
BOD12 threshold level at power-on.
SUPC.BOD12
23
BOD12 Disable
BOD12 Disable at power-on.
SUPC.BOD12
25:24
BOD12 Action
BOD12 Action at power-on.
SUPC.BOD12
26
WDT Enable
WDT Enable at power-on.
WDT.CTRLA
27
WDT Always-On
WDT Always-On at power-on.
WDT.CTRLA
31:28
WDT Period
WDT Period at power-on.
WDT.CONFIG
35:32
WDT Window
WDT Window mode time-out at power-on.
WDT.CONFIG
39:36
WDT EWOFFSET WDT Early Warning Interrupt Time Offset at poweron.
WDT.EWCTRL
40
WDT WEN
WDT.CTRLA
41
BOD33 Hysteresis BOD33 Hysteresis configuration at power-on.
SUPC.BOD33
42
BOD12 Hysteresis BOD12 Hysteresis configuration at power-on.
SUPC.BOD12
47:43
Reserved
—
—
63:48
LOCK
NVM Region Lock Bits.
NVMCTRL
WDT Timer Window Mode Enable at power-on.
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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10.4.
NVM Software Calibration Area Mapping
The NVM Software Calibration Area contains calibration data that are determined and written during
production test. These calibration values should be read by the application software and written back to
the corresponding register.
The NVM Software Calibration Area can be read at address 0x00806020.
The NVM Software Calibration Area can not be written.
Table 10-5. NVM Software Calibration Area Mapping
10.5.
Bit Position Name
Description
2:0
ADC
LINEARITY
ADC Linearity Calibration. Should be written to CALIB register.
5:3
ADC BIASCAL
ADC Bias Calibration. Should be written to CALIB register.
12:6
Reserved
Reserved for future use.
17:13
USB TRANSN
USB TRANSN calibration value. Should be written to the USB PADCAL
register.
22:18
USB TRANSP
USB TRANSP calibration value. Should be written to the USB PADCAL
register.
25:23
USB TRIM
USB TRIM calibration value. Should be written to the USB PADCAL
register.
31:26
DFLL48M
COARSE CAL
DFLL48M Coarse calibration value. Should be written to the OSCCTRL
DFLLVAL register.
Serial Number
Each device has a unique 128-bit serial number which is a concatenation of four 32-bit words contained
at the following addresses:
Word 0: 0x0080A00C
Word 1: 0x0080A040
Word 2: 0x0080A044
Word 3: 0x0080A048
The uniqueness of the serial number is guaranteed only when using all 128 bits.
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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11.
Processor and Architecture
11.1.
Cortex M0+ Processor
®
™
The Atmel SAM L22 implements the ARM ARM Cortex -M0+ processor, based on the ARMv6
®
Architecture and Thumb -2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor,
the Cortex-M0 core, and upward compatible to Cortex-M3 and M4 cores. The implemented ARM CortexM0+ is revision r0p1. For more information refer to http://www.arm.com
11.1.1.
Cortex M0+ Configuration
Table 11-1. Cortex M0+ Configuration
Features
Cortex-M0+ options
SAM L22 configuration
Interrupts
External interrupts 0-32
27
Data endianness
Little-endian or big-endian
Little-endian
SysTick timer
Present or absent
Present
Number of watchpoint comparators
0, 1, 2
2
Number of breakpoint comparators
0, 1, 2, 3, 4
4
Halting debug support
Present or absent
Present
Multiplier
Fast or small
Fast (single cycle)
Single-cycle I/O port
Present or absent
Present
Wake-up interrupt controller
Supported or not supported
Not supported
Vector Table Offset Register
Present or absent
Present
Unprivileged/Privileged support
Present or absent
Present
Memory Protection Unit
Not present or 8-region
8-region
Reset all registers
Present or absent
Absent
Instruction fetch width
16-bit only or mostly 32-bit
32-bit
The ARM Cortex-M0+ core has two bus interfaces:
•
•
11.1.2.
Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all
system memory, which includes flash and RAM.
Single 32-bit I/O port bus interfacing to the PORT and DIVAS with 1-cycle loads and stores.
Cortex M0+ Peripherals
•
•
System Control Space (SCS)
– The processor provides debug through registers in the SCS. Refer to the Cortex-M0+
Technical Reference Manual for details (http://www.arm.com)
Nested Vectored Interrupt Controller (NVIC)
– External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts.
Software can set the priority of each interrupt. The NVIC and the Cortex-M0+ processor core
are closely coupled, providing low latency interrupt processing and efficient processing of late
Atmel SAM L22G / L22J / L22N Summary [DATASHEET]
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•
•
•
•
11.1.3.
arriving interrupts. Refer to NVIC-Nested Vector Interrupt Controller and the Cortex-M0+
Technical Reference Manual for details (http://www.arm.com).
Note: When the CPU frequency is much higher than the APB frequency it is recommended
to insert a memory read barrier after each CPU write to registers mapped on the APB. Failing
to do so in such conditions may lead to unexpected behavior such as e.g. re-entering a
peripheral interrupt handler just after leaving it.
System Timer (SysTick)
– The System Timer is a 24-bit timer clocked by CLK_CPU that extends the functionality of both
the processor and the NVIC. Refer to the Cortex-M0+ Technical Reference Manual for details
(http://www.arm.com).
System Control Block (SCB)
– The System Control Block provides system implementation information, and system control.
This includes configuration, control, and reporting of the system exceptions. Refer to the
Cortex-M0+ Devices Generic User Guide for details (http://www.arm.com).
Micro Trace Buffer (MTB)
– The CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the CortexM0+ processor. Refer to section MTB-Micro Trace Buffer and the CoreSight MTB-M0+
Technical Reference Manual for details (http://www.arm.com).
Memory Protection Unit (MPU)
– The Memory Protection Unit divides the memory map into a number of regions, and defines
the location, size, access permissions and memory attributes of each region. Refer to the
Cortex-M0+ Devices Generic User Guide for details (http://www.arm.com)
Cortex M0+ Address Map
Table 11-2. Cortex-M0+ Address Map
Address
Peripheral
0xE000E000
System Control Space (SCS)
0xE000E010
System Timer (SysTick)
0xE000E100
Nested Vectored Interrupt Controller (NVIC)
0xE000ED00
System Control Block (SCB)
0x41006000
Micro Trace Buffer (MTB)
Related Links
Product Mapping on page 28
11.1.4.
I/O Interface
®
™
The device allows direct access to PORT registers. Accesses to the AMBA AHB-Lite and the single
cycle I/O interface can be made concurrently, so the Cortex M0+ processor can fetch the next instructions
while accessing the I/Os. This enables single cycle I/O access to be sustained for as long as necessary.
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11.2.
Nested Vector Interrupt Controller
11.2.1.
Overview
The Nested Vectored Interrupt Controller (NVIC) in the SAM L22 supports 32 interrupts with four different
priority levels. For more details, refer to the Cortex-M0+ Technical Reference Manual (http://
www.arm.com).
11.2.2.
Interrupt Line Mapping
Each of the interrupt lines is connected to one peripheral instance, as shown in the table below. Each
peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear
(INTFLAG) register.
An interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be
individually enabled by writing a '1' to the corresponding bit in the peripheral’s Interrupt Enable Set
(INTENSET) register, and disabled by writing '1' to the corresponding bit in the peripheral’s Interrupt
Enable Clear (INTENCLR) register.
An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding
interrupt is enabled.
The interrupt requests for one peripheral are ORed together on system level, generating one interrupt
request for each peripheral. An interrupt request will set the corresponding interrupt pending bit in the
NVIC interrupt pending registers (SETPEND/CLRPEND bits in ISPR/ICPR).
For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/
CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for
each interrupt.
Table 11-3. Interrupt Line Mapping
Peripheral source
NVIC line
EIC NMI – External Interrupt Controller
NMI
PM – Power Manager
0
MCLK - Main Clock
OSCCTRL - Oscillators Controller
OSC32KCTRL - 32KHz Oscillators Controller
PAC - Peripheral Access Controller
SUPC - Supply Controller
WDT – Watchdog Timer
1
RTC – Real Time Counter
2
EIC – External Interrupt Controller
3
FREQM - Frequency Meter
4
USB - Universal Serial Bus
5
NVMCTRL – Non-Volatile Memory Controller
6
DMAC - Direct Memory Access Controller
7
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Peripheral source
NVIC line
EVSYS – Event System
8
SERCOM0 – Serial Communication Interface 0
9
SERCOM1 – Serial Communication Interface 1
10
SERCOM2 – Serial Communication Interface 2
11
SERCOM3 – Serial Communication Interface 3
12
SERCOM4 – Serial Communication Interface 4
13
SERCOM5 – Serial Communication Interface 5
14
TCC0 – Timer Counter for Control 0
15
TC0 – Timer Counter 0
16
TC1 – Timer Counter 1
17
TC2 – Timer Counter 2
18
TC3 – Timer Counter 3
19
ADC – Analog-to-Digital Converter
20
AC – Analog Comparator
21
PTC – Peripheral Touch Controller
22
SLCD - Segmented LCD Controller
23
AES - Advanced Encryption Standard module
24
TRNG - True Random Number Generator
25
11.3.
Micro Trace Buffer
11.3.1.
Features
•
•
•
•
11.3.2.
Program flow tracing for the Cortex-M0+ processor
MTB SRAM can be used for both trace and general purpose storage by the processor
The position and size of the trace buffer in SRAM is configurable by software
CoreSight compliant
Overview
When enabled, the MTB records the changes in program flow that are reported by the Cortex-M0+
processor over the execution trace interface. This interface is shared between the Cortex-M0+ processor
and the CoreSight MTB-M0+. The information is stored by the MTB in the SRAM as trace packets. An offchip debugger can extract the trace information using the Debug Access Port to read the trace
information from the SRAM. The debugger can then reconstruct the program flow from this information.
The MTB stores trace information into the SRAM and gives the processor access to the SRAM
simultaneously. The MTB ensures that trace write accesses have priority over processor accesses.
An execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects a
non-sequential change of the program pounter (PC) value. A non-sequential PC change can occur during
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branch instructions or during exception entry. See the CoreSight MTB-M0+ Technical Reference Manual
for more details on the MTB execution trace packet format.
Tracing is enabled when the MASTER.EN bit in the Master Trace Control Register is 1. There are various
ways to set the bit to 1 to start tracing, or to 0 to stop tracing. See the CoreSight Cortex-M0+ Technical
Reference Manual for more details on the Trace start and stop and for a detailed description of the MTB’s
MASTER register. The MTB can be programmed to stop tracing automatically when the memory fills to a
specified watermark level or to start or stop tracing by writing directly to the MASTER.EN bit. If the
watermark mechanism is not being used and the trace buffer overflows, then the buffer wraps around
overwriting previous trace packets.
The base address of the MTB registers is 0x41006000; this address is also written in the CoreSight ROM
Table. The offset of each register from the base address is fixed and as defined by the CoreSight MTBM0+ Technical Reference Manual. The MTB has four programmable registers to control the behavior of
the trace features:
•
POSITION: Contains the trace write pointer and the wrap bit
•
MASTER: Contains the main trace enable bit and other trace control fields
•
FLOW: Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits
•
BASE: Indicates where the SRAM is located in the processor memory map. This register is
provided to enable auto discovery of the MTB SRAM location by a debug agent
See the CoreSight MTB-M0+ Technical Reference Manual for a detailed description of these registers.
11.4.
High-Speed Bus System
11.4.1.
Overview
11.4.2.
Features
High-Speed Bus Matrix has the following features:
•
•
•
•
Symmetric crossbar bus switch implementation
Allows concurrent accesses from different masters to different slaves
32-bit data bus
Operation at a one-to-one clock frequency with the bus masters
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Configuration
Figure 11-1. Master-Slave Relations High-Speed Bus Matrix
Multi-Slave
MASTERS
CM0+
0
DSU DSU
1
DMAC
Data
DSU
MTB
2
USB
6
1
DMAC WB 1
2
DMAC WB 0
MASTER ID
1
0
DMAC Fetch 1
5
DMAC Fetch 0
AHB-APB Bridge C
3
DMAC Data
AHB-APB Bridge B
4
DSU
AHB-APB Bridge A
0
SRAM
CM0+
Internal Flash
High-Speed Bus SLAVES
3
4
5
6
7
8
SLAVE ID
SRAM PORT ID
2
DMAC Fetch 0
Privileged SRAM-access MASTERS
11.4.3.
DMAC DSU
Fetch 1
DMAC DSU
WB 0
DMAC WB 1
USB
DSU
MTB
DSU
Table 11-4. High Speed Bus Matrix Masters
High-Speed Bus Matrix Masters
Master ID
CM0+ - Cortex M0+ Processor
0
DSU - Device Service Unit
1
DMAC - Direct Memory Access Controller / Data
Access
2
Table 11-5. High-Speed Bus Matrix Slaves
High-Speed Bus Matrix Slaves
Slave ID
Internal Flash Memory
0
SRAM Port 0 - CM0+ Access
1
SRAM Port 1 - DSU Access
2
AHB-APB Bridge B
3
AHB-APB Bridge A
4
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11.4.4.
High-Speed Bus Matrix Slaves
Slave ID
AHB-APB Bridge C
5
SRAM Port 2 - DMAC Data Access
6
SRAM Quality of Service
To ensure that masters with latency requirements get sufficient priority when accessing RAM, priority
levels can be assigned to the masters for different types of access.
The Quality of Service (QoS) level is independently selected for each master accessing the RAM. For any
access to the RAM, the RAM also receives the QoS level. The QoS levels and their corresponding bit
values for the QoS level configuration is shown in the table below.
Table 11-6. Quality of Service
Value
Name
Description
0x0
DISABLE
Background (no sensitive
operation)
0x1
LOW
Sensitive Bandwidth
0x2
MEDIUM
Sensitive Latency
0x3
HIGH
Critical Latency
If a master is configured with QoS level DISABLE (0x0) or LOW (0x1) there will be a minimum latency of
one cycle for the RAM access.
The priority order for concurrent accesses are decided by two factors. First, the QoS level for the master
and second, a static priority given by the port ID. The lowest port ID has the highest static priority. See the
tables below for details.
The MTB has a fixed QoS level HIGH (0x3).
The CPU QoS level can be written/read, using 32-bit access only, at address 0x4100C114, bits [1:0]. Its
reset value is 0x3.
Refer to different master QOSCTRL registers for configuring QoS for the other masters (USB, DMAC).
Table 11-7. SRAM Port Connections QoS
SRAM Port
Connection
Port ID
Connection Type
QoS
default QoS
CM0+ - Cortex
M0+ Processor
0
Bus Matrix
0x4100C114,
bits[1:0](1)
0x3
DSU - Device
Service Unit
1
Bus Matrix
0x4100201C,
bits[1:0](1)
0x2
DMAC - Direct
Memory Access
Controller - Data
Access
2
Bus Matrix
IPQOSCTRL.DQOS
0x2
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SRAM Port
Connection
Port ID
Connection Type
QoS
default QoS
DMAC - Direct
Memory Access
Controller - Fetch
Access
3, 4
Direct
IPQOSCTRL.FQOS
0x2
DMAC - Direct
Memory Access
Controller - WriteBack Access
5, 6
Direct
IPQOSCTRL.WRBQ
OS
0x2
USB - Universal
Serial Bus
7
Direct
IP-QOSCTRL
0x3
MTB - Micro Trace
Buffer
8
Direct
STATIC-3
0x3
Note: 1. Using 32-bit access only.
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12.
Packaging Information
12.1.
Thermal Considerations
12.1.1.
Thermal Resistance Data
The following table summarizes the thermal resistance data depending on the package.
Table 12-1. Thermal Resistance Data
Package Type
θJA
θJC
48-pin TQFP
64.2°C/W
12.3°C/W
64-pin TQFP
60.8°C/W
12.0°C/W
100-pin TQFP
58.5°C/W
12.7°C/W
48-pin QFN
32.4°C/W
11.2°C/W
64-pin QFN
32.7°C/W
10.8°C/W
Related Links
Junction Temperature on page 40
12.1.2.
Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
1.
2.
TJ = TA + (PD x θJA)
TJ = TA + (PD x (θHEATSINK + θJC))
where:
•
•
•
•
•
θJA = Package thermal resistance, Junction-to-ambient (°C/W), see Thermal Resistance Data
θJC = Package thermal resistance, Junction-to-case thermal resistance (°C/W), see Thermal
Resistance Data
θHEATSINK = Thermal resistance (°C/W) specification of the external cooling device
PD = Device power consumption (W)
TA = Ambient temperature (°C)
From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling
device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be
used to compute the resulting average chip-junction temperature TJ in °C.
Related Links
Thermal Resistance Data on page 40
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12.2.
Package Drawings
12.2.1.
100 pin TQFP
Table 12-2. Device and Package Maximum Weight
520
mg
Table 12-3. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 12-4. Package Reference
JEDEC Drawing Reference
MS-026, variant AED
JESD97 Classification
e3
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12.2.2.
64 pin TQFP
Table 12-5. Device and Package Maximum Weight
300
mg
Table 12-6. Package Characteristics
Moisture Sensitivity Level
MSL3
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Table 12-7. Package Reference
12.2.3.
JEDEC Drawing Reference
MS-026
JESD97 Classification
E3
64 pin QFN
Note: The exposed die attach pad is not connected electrically inside the device.
Table 12-8. Device and Package Maximum Weight
200
mg
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Table 12-9. Package Charateristics
Moisture Sensitivity Level
MSL3
Table 12-10. Package Reference
12.2.4.
JEDEC Drawing Reference
MO-220
JESD97 Classification
E3
48 pin TQFP
Table 12-11. Device and Package Maximum Weight
140
mg
Table 12-12. Package Characteristics
Moisture Sensitivity Level
MSL3
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Table 12-13. Package Reference
12.2.5.
JEDEC Drawing Reference
MS-026
JESD97 Classification
E3
48 pin QFN
Note: The exposed die attach pad is not connected electrically inside the device.
Table 12-14. Device and Package Maximum Weight
140
mg
Table 12-15. Package Characteristics
Moisture Sensitivity Level
MSL3
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Table 12-16. Package Reference
12.3.
JEDEC Drawing Reference
MO-220
JESD97 Classification
E3
Soldering Profile
The following table gives the recommended soldering profile from J-STD-20.
Table 12-17. Profile Feature
Green Package
Average Ramp-up Rate (217°C to peak)
3°C/s max.
Preheat Temperature 175°C ±25°C
150-200°C
Time Maintained Above 217°C
60-150s
Time within 5°C of Actual Peak Temperature
30s
Peak Temperature Range
260°C
Ramp-down Rate
6°C/s max.
Time 25°C to Peak Temperature
8 minutes max.
A maximum of three reflow passes is allowed per component.
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