datasheet for rfPIC12F675F by Microchip Technology Inc.

datasheet for rfPIC12F675F by Microchip Technology Inc.
rfPIC12F675K/675F/675H
Data Sheet
20-Pin FLASH-Based 8-Bit
CMOS Microcontroller
with UHF ASK/FSK Transmitter
 2003 Microchip Technology Inc.
Preliminary
DS70091A
Note the following details of the code protection feature on Microchip devices:
•
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•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications. No
representation or warranty is given and no liability is assumed by
Microchip Technology Incorporated with respect to the accuracy
or use of such information, or infringement of patents or other
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Use of Microchip’s products as critical components in life
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Trademarks
The Microchip name and logo, the Microchip logo, KEELOQ,
MPLAB, PIC, PICmicro, PICSTART, PRO MATE and
PowerSmart are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Accuron, Application Maestro, dsPIC, dsPICDEM,
dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM,
fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC,
microPort, Migratable Memory, MPASM, MPLIB, MPLINK,
MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal,
PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark of
Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS70091A - page ii
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
FLASH-Based Microcontroller with ASK/FSK Transmitter
High Performance RISC CPU:
Peripheral Features:
• Memory
- 1024 x 14 words of FLASH program memory
- 128 x 8 bytes of EEPROM data memory
- 64 x 8 bytes of SRAM data memory
- 100,000 write FLASH endurance
- 1,000,000 write EEPROM endurance
- FLASH/data EEPROM retention: > 40 years
• Programmable code protection
• 6 I/O pins with individual direction control, weak
pull-ups, and interrupt-on-pin change
• High current sink/source for direct LED drive
• Analog comparator: 16 internal reference levels
• Analog-to-Digital Converter: 10 bits, 4 channels
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with 3-bit prescaler
• Timer1 can use LP oscillator in INTOSC mode
• 5 µs wake-up from SLEEP typical with VDD = 3V
• In-Circuit Serial ProgrammingTM (ICSPTM)
Low Power Features:
• Low power consumption: (typical with VDD = 3V)
- 14 mA transmitting +6 dBm at 434 MHz
- 4 mA transmitting -15 dBm at 434 MHz
- 500 µA, 4.0 MHz INTOSC
- 0.6 µA SLEEP with watchdog enabled
- 0.1 µA standby current
• Wide operating voltage range from 2.0 – 5.5V
• Industrial and Extended temperature range
 2003 Microchip Technology Inc.
SSOP
VDD
GP5/T1CKI/OSC1/CLKIN
GP4/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
RFXTAL
RFEN
REFCLK
PS
VDDRF
VSSRF
•1
2
3
4
5
6
7
8
9
10
rfPIC12F675K/F/H
• Only 35 instructions to learn
- All single cycle instructions except branches
• Operating speed:
- Precision Internal 4 MHz oscillator, factory
calibrated to ±1%
- DC - 20 MHz Resonator/Crystal/Clock modes
- DC - 20 MHz crystal oscillator/clock input
- DC - 4 MHz external RC oscillator
- DC - 4 MHz XT crystal oscillator
- External Oscillator modes
• Interrupt capability
• 8-level deep hardware stack
• Direct, Indirect and Relative Addressing modes
Pin Diagram:
20
19
18
17
16
15
14
13
12
11
VSS
GP0/CIN+/ICSPDAT
GP1/CIN-/ICSPCLK
GP2/T0CKI/INT/COUT
FSKOUT
DATAFSK
DATAASK
LF
VSSRF
ANT
UHF ASK/FSK Transmitter:
• Integrated crystal oscillator, VCO, loop filter and
power amp for minimum external components
• ASK data rate: 0 – 40 Kbps
• FSK data rate: 0 – 40 Kbps by crystal pulling
• Output power: +10 dBm to -12 dBm in 4 steps
• Adjustable transmitter power consumption
• Transmit frequency set by crystal multiplied by 32
• VCO phase locked to quartz crystal reference;
allows narrow band receivers to be used to
maximize range and interference immunity
• Crystal frequency divide by 4 available (REFCLK)
• Used in applications conforming to US FCC Part
15.231 and European EN 300 220 regulations
Applications:
•
•
•
•
•
•
•
•
•
Automotive Remote Keyless Entry (RKE) systems
Automotive alarm systems
Community gate and garage door openers
Burglar alarm systems
Building access
Low power telemetry
Meter reading
Tire pressure sensors
Wireless sensors
Device
Frequency
rfPIC12F675K
290-350 MHz
ASK/FSK
rfPIC12F675F
380-450 MHz
ASK/FSK
rfPIC12F675H
850-930 MHz
ASK/FSK
Preliminary
Modulation
DS70091A-page 1
rfPIC12F675
Table of Contents
1.0 Device Overview ............................................................................................................................................................................ 3
2.0 Memory Organization..................................................................................................................................................................... 5
3.0 GPIO Port ................................................................................................................................................................................... 17
4.0 Timer0 Module............................................................................................................................................................................ 25
5.0 Timer1 Module with Gate Control ............................................................................................................................................... 28
6.0 Comparator Module .................................................................................................................................................................... 33
7.0 Analog-to-Digital Converter (A/D) Module .................................................................................................................................. 39
8.0 Data EEPROM Memory.............................................................................................................................................................. 45
9.0 UHF ASK/FSK Transmitter ......................................................................................................................................................... 49
10.0 Special Features of the CPU ...................................................................................................................................................... 55
11.0 Instruction Set Summary ............................................................................................................................................................ 73
12.0 Development Support ................................................................................................................................................................. 81
13.0 Electrical Specifications .............................................................................................................................................................. 87
14.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 113
15.0 Packaging Information .............................................................................................................................................................. 123
Appendix A: Data Sheet Revision History.......................................................................................................................................... 125
Index ................................................................................................................................................................................................. 127
On-Line Support................................................................................................................................................................................ 131
Systems Information and Upgrade Hot Line ..................................................................................................................................... 131
Reader Response ............................................................................................................................................................................. 132
Product Identification System............................................................................................................................................................ 133
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To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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DS70091A-page 2
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
1.0
DEVICE OVERVIEW
be considered a complementary document to this Data
Sheet, and is highly recommended reading for a better
understanding of the device architecture and operation
of the peripheral modules.
This document contains device specific information for
the rfPIC12F675. Additional information may be found
in the PICmicroTM Mid-Range Reference Manual
(DS33023), which may be obtained from your local
Microchip Sales Representative or downloaded from
the Microchip web site. The Reference Manual should
FIGURE 1-1:
The rfPIC12F675 comes in a 20-pin SSOP package.
Figure 1-1 shows a block diagram of the rfPIC12F675
device. Table 1-1 shows the pinout description.
rfPIC12F675 BLOCK DIAGRAM
13
FLASH
Data Bus
Program Counter
Program
Memory
Program
Bus
GP0/AN0/CIN+
GP1/AN1/CIN-/VREF
GP2/AN2/T0CKI/INT/COUT
GP3/MCLR/VPP
GP4/AN3/T1G/OSC2/CLKOUT
GP5/T1CKI/OSC1/CLKIN
RAM
File
Registers
64 x 8
8-Level Stack
(13-bit)
1K x 14
8
14
RAM
Addr(1)
9
Addr MUX
Instruction Reg
7
Direct Addr
8
Indirect
Addr
FSR Reg
Internal
4 MHz
Oscillator
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
VDD, VSS
T1G
3
MUX
Power-up
Timer
ALU
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Detect
Crystal
Oscillator
RFXTAL
Phase/Freq
Detector
8
W Reg
Divide
by 32
Charge
Pump
LF
Voltage
Controlled
Oscillator
T1CKI
Timer0
Timer1
T0CKI
PS
DATAASK
Analog to Digital Converter
Analog
Comparator
and reference
EEDATA
8 128 bytes
DATA
EEPROM
EEADDR
CIN- CIN+ COUT
VREF
REFCLK
STATUS Reg
8
Instruction
Decode &
Control
Clock
Divider
RFEN
RF Power
Amplifier
RF
Control
Logic
ANT
VDDRF
VSSRF
VSSRF
DATAFSK
FSK Switch
FSKOUT
AN0 AN1 AN2 AN3
Note 1: Higher order bits are from STATUS register.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 3
rfPIC12F675
TABLE 1-1:
rfPIC12F675 PINOUT
BUFFER
IN
OUT
WEAK
PULL-UP
VDD
Direct
—
—
GP5
TTL
CMOS
Prog
T1CKI
OSC1
CLKIN
ST
Xtal
ST
—
—
—
—
Bias
—
GP4
TTL
CMOS
Prog
ST
Analog
—
—
—
—
Xtal
CMOS
—
—
Bias
—
GP3
TTL
—
MCLR
VPP
RFXTAL
RFEN
ST
HV
Xtal
TTL
—
—
Xtal
—
PIN
1
2
3
4
T1G
AN3
OSC2
CLKOUT
DESCRIPTION
Power Supply
General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
Timer1 clock
XTAL connection
External RC network or clock input
General purpose I/O. Individually controlled interrupt-on-change.
Individually enabled pull-up.
Timer1 gate
A/D Channel 3 input
XTAL connection
TOSC/4 reference clock
General purpose input. Individually controlled interrupt-onchange.
Master Clear Reset
Programming voltage
5
RF Crystal
6
RF Enable
Reference Clock/4 Output (on rfPIC12F675K/F)
7
REFCLK
—
CMOS
—
Reference Clock/8 Output (on rfPIC12F675H)
8
PS
Analog
—
Bias
Power Select
9
VDDRF
Direct
—
—
RF Power Supply
10
VSSRF
Direct
—
—
RF Ground Reference
11
ANT
—
OD
—
RF power amp output to antenna
12
VSSRF
Direct
—
—
RF Ground Reference
13
LF
Analog Analog
—
Loop Filter
TTL
—
—
ASK modulation data
14
DATAASK
15
DATAFSK
TTL
—
—
FSK modulation data
16
FSKOUT
—
OD
—
FSK output to modulate reference crystal
General purpose I/O. Individually controlled interrupt-on-change.
GP2
ST
CMOS
Prog
Individually enabled pull up.
AN2
Analog
—
—
A/D Channel 2 input
17
COUT
—
CMOS
—
Comparator output
T0CKI
ST
—
—
External clock for Timer0
INT
ST
—
—
External interrupt
General purpose I/O. Individually controlled interrupt-on-change.
GP1
TTL
CMOS
Prog
Individually enabled pull-up.
AN1
Analog
—
—
A/D Channel 1 input
18
CINAnalog
—
—
Comparator input - negative
VREF
Analog
—
—
External voltage reference
ICSPCLK
ST
—
—
Serial programming clock
General purpose I/O. Individually controlled interrupt-on-change.
GP0
TTL
CMOS
Prog
Individually enabled pull-up.
AN0
Analog
—
—
A/D Channel 0 input
19
CIN+
Analog
—
—
Comparator input - positive
ICSPDAT
TTL
CMOS
—
Serial Programming Data I/O
20
VSS
Direct
—
—
Ground reference
Legend:
TTL = TTL input buffer, ST = Schmitt Trigger input buffer, OD = Open Drain output
DS70091A-page 4
No
—
Bias
—
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
2.0
MEMORY ORGANIZATION
2.2
2.1
Program Memory Organization
The data memory (see Figure 2-2) is partitioned into
two banks, which contain the General Purpose registers and the Special Function registers. The Special
Function registers are located in the first 32 locations of
each bank. Register locations 20h-5Fh are General
Purpose registers, implemented as static RAM and are
mapped across both banks. All other RAM is
unimplemented and returns ‘0’ when read. RP0
(STATUS<5>) is the bank select bit.
The rfPIC12F675 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. Only the first 1K x 14 (0000h - 03FFh)
for the rfPIC12F675 devices is physically implemented.
Accessing a location above these boundaries will
cause a wrap around within the first 1K x 14 space. The
RESET vector is at 0000h and the interrupt vector is at
0004h (see Figure 2-1).
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
rfPIC12F675
PC<12:0>
CALL, RETURN
RETFIE, RETLW
Data Memory Organization
• RP0 = 0 Bank 0 is selected
• RP0 = 1 Bank 1 is selected
Note:
2.2.1
13
The IRP and RP1 bits STATUS<7:6> are
reserved and should always be maintained
as ‘0’s.
GENERAL PURPOSE REGISTER
FILE
The register file is organized as 64 x 8 in the
rfPIC12F675 devices. Each register is accessed, either
directly or indirectly, through the File Select Register
FSR (see Section 2.4).
Stack Level 1
Stack Level 2
Stack Level 8
RESET Vector
000h
Interrupt Vector
0004
0005
On-chip Program
Memory
03FFh
0400h
1FFFh
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 5
rfPIC12F675
2.2.2
SPECIAL FUNCTION REGISTERS
FIGURE 2-2:
The Special Function registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Table 2-1). These
registers are static RAM.
DATA MEMORY MAP OF
THE rfPIC12F675
File
Address
Indirect addr.(1)
TMR0
PCL
STATUS
FSR
GPIO
The special registers can be classified into two sets:
core and peripheral. The Special Function registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
CMCON
ADRESH
ADCON0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
General
Purpose
Registers
File
Address
Indirect addr.(1)
OPTION_REG
PCL
STATUS
FSR
TRISIO
PCLATH
INTCON
PIE1
PCON
OSCCAL
WPU
IOC
VRCON
EEDATA
EEADR
EECON1
EECON2(1)
ADRESL
ANSEL
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
accesses
20h-5Fh
64 Bytes
5Fh
60h
DFh
E0h
7Fh
Bank 0
1:
DS70091A-page 6
Preliminary
FFh
Bank 1
Unimplemented data memory locations, read as '0'.
Not a physical register.
 2003 Microchip Technology Inc.
rfPIC12F675
TABLE 2-1:
Address
SPECIAL FUNCTION REGISTERS SUMMARY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOD
Page
Bank 0
00h
INDF(1)
Addressing this Location uses Contents of FSR to Address Data Memory
0000 0000
16,63
01h
TMR0
Timer0 Module’s Register
xxxx xxxx
25
02h
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
15
03h
STATUS
04h
FSR
05h
GPIO
IRP(2)
RP1(2)
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
—
--xx xxxx
17
Unimplemented
—
—
07h
—
Unimplemented
—
—
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
---0 0000
15
0Bh
INTCON
0Ch
PIR1
0Dh
—
—
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
16
—
PCLATH
GPIO5
9
xxxx xxxx
06h
0Ah
—
0001 1xxx
—
—
Write Buffer for Upper 5 bits of Program Counter
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
11
EEIF
ADIF
—
—
CMIF
—
—
TMR1IF
00-- 0--0
13
—
—
0Eh
TMR1L
Unimplemented
Holding Register for the Least Significant Byte of the 16-bit Timer1
xxxx xxxx
28
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit Timer1
xxxx xxxx
28
10h
T1CON
-000 0000
30
11h
—
Unimplemented
—
—
12h
—
Unimplemented
—
—
13h
—
Unimplemented
—
—
14h
—
Unimplemented
—
—
15h
—
Unimplemented
—
—
16h
—
Unimplemented
—
—
17h
—
Unimplemented
—
—
18h
—
Unimplemented
—
—
-0-0 0000
33
19h
CMCON
—
—
TMR1GE
COUT
T1CKPS1
—
T1CKPS0
CINV
T1OSCEN
CIS
T1SYNC
CM2
TMR1CS
CM1
TMR1ON
CM0
1Ah
—
Unimplemented
—
—
1Bh
—
Unimplemented
—
—
1Ch
—
Unimplemented
—
—
1Dh
—
Unimplemented
—
—
1Eh
ADRESH
xxxx xxxx
40
1Fh
ADCON0
00-- 0000
41,63
Most Significant 8 bits of the Left Shifted A/D Result or 2 bits of the Right Shifted Result
ADFM
VCFG
—
—
CHS1
CHS0
GO/DONE
ADON
Legend:
— = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: This is not a physical register.
2: These bits are reserved and should always be maintained as ‘0’.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 7
rfPIC12F675
TABLE 2-1:
Address
SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PS1
PS0
Value on
POR, BOD
Page
0000 0000
16,63
1111 1111
10,26
0000 0000
15
9
Bank 1
80h
INDF(1)
81h
OPTION_REG
82h
PCL
83h
STATUS
84h
FSR
85h
TRISIO
Addressing this Location uses Contents of FSR to Address Data Memory
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
Program Counter's (PC) Least Significant Byte
(2)
IRP
RP0
(2)
RP1
TO
PD
Z
DC
C
0001 1xxx
xxxx xxxx
16
TRISIO4
TRISIO3
TRISIO2
TRISIO1
TRISIO0
--11 1111
17
Indirect Data Memory Address Pointer
—
—
TRISIO5
86h
—
Unimplemented
—
—
87h
—
Unimplemented
—
—
88h
—
Unimplemented
—
—
89h
—
Unimplemented
—
—
---0 0000
15
8Ah
PCLATH
8Bh
INTCON
8Ch
PIE1
8Dh
8Eh
—
—
—
—
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
11
EEIE
ADIE
—
—
CMIE
—
—
TMR1IE
00-- 0--0
12
—
—
—
—
—
—
—
POR
BOD
---- --0x
14
—
—
CAL4
CAL3
CAL2
CAL1
CAL0
—
—
1000 00--
14
Unimplemented
—
PCON
Write Buffer for Upper 5 bits of Program Counter
8Fh
—
90h
OSCCAL
91h
—
Unimplemented
—
—
92h
—
Unimplemented
—
—
93h
—
Unimplemented
—
—
94h
—
Unimplemented
—
—
95h
WPU
96h
IOC
Unimplemented
CAL5
—
—
WPU5
WPU4
—
WPU2
WPU1
WPU0
--11 -111
18
—
—
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
--00 0000
19
97h
—
Unimplemented
—
—
98h
—
Unimplemented
—
—
0-0- 0000
38
99h
VRCON
9Ah
EEDATA
9Bh
EEADR
VREN
—
VRR
—
VR3
VR2
VR1
VR0
Data EEPROM Data Register
—
Data EEPROM Address Register
0000 0000
45
-000 0000
45
9Ch
EECON1
---- x000
46
9Dh
EECON2(1)
EEPROM Control Register 2
---- ----
46
9Eh
ADRESL
Least Significant 2 bits of the Left Shifted A/D Result of 8 bits or the Right Shifted Result
xxxx xxxx
40
9Fh
ANSEL
-000 1111
42,63
—
—
—
ADCS2
—
ADCS1
—
ADCS0
WRERR
ANS3
WREN
ANS2
WR
ANS1
RD
ANS0
Legend:
— = unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: This is not a physical register.
2: These bits are reserved and should always be maintained as ‘0’.
DS70091A-page 8
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
2.2.2.1
STATUS Register
The STATUS register, shown in Register 2-1, contains:
• the arithmetic status of the ALU
• the RESET status
• the bank select bits for data memory (SRAM)
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect any STATUS bits. For other instructions not
affecting any STATUS bits, see the “Instruction Set
Summary”.
Note 1: Bits IRP and RP1 (STATUS<7:6>) are not
used by the rfPIC12F675 and should be
maintained as clear. Use of these bits is
not recommended, since this may affect
upward compatibility with future products.
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as 000u u1uu (where u = unchanged).
REGISTER 2-1:
STATUS — STATUS REGISTER (ADDRESS: 03h OR 83h)
Reserved Reserved
IRP
RP1
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
RP0
TO
PD
Z
DC
C
bit 7
bit 7
bit 0
IRP: This bit is reserved and should be maintained as ‘0’
bit 6
RP1: This bit is reserved and should be maintained as ‘0’
bit 5
RP0: Register Bank Select bit (used for direct addressing)
1 = Bank 1 (80h - FFh)
0 = Bank 0 (00h - 7Fh)
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
For borrow, the polarity is reversed.
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note:
For borrow the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
 2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS70091A-page 9
rfPIC12F675
2.2.2.2
OPTION Register
Note:
The OPTION register is a readable and writable
register, which contains various control bits to
configure:
•
•
•
•
To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT by
setting PSA bit to ‘1’ (OPTION<3>). See
Section 4.4.
TMR0/WDT prescaler
External GP2/INT interrupt
TMR0
Weak pull-ups on GPIO
REGISTER 2-2:
OPTION_REG — OPTION REGISTER (ADDRESS: 81h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
GPPU: GPIO Pull-up Enable bit
1 = GPIO pull-ups are disabled
0 = GPIO pull-ups are enabled by individual port latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of GP2/INT pin
0 = Interrupt on falling edge of GP2/INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on GP2/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on GP2/T0CKI pin
0 = Increment on low-to-high transition on GP2/T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the TIMER0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
DS70091A-page 10
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
 2003 Microchip Technology Inc.
rfPIC12F675
2.2.2.3
INTCON Register
Note:
The INTCON register is a readable and writable
register, which contains the various enable and flag bits
for TMR0 register overflow, GPIO port change and
external GP2/INT pin interrupts.
REGISTER 2-3:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
INTCON — INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
bit 7
bit 0
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4
INTE: GP2/INT External Interrupt Enable bit
1 = Enables the GP2/INT external interrupt
0 = Disables the GP2/INT external interrupt
bit 3
GPIE: Port Change Interrupt Enable bit(1)
1 = Enables the GPIO port change interrupt
0 = Disables the GPIO port change interrupt
bit 2
T0IF: TMR0 Overflow Interrupt Flag bit(2)
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INTF: GP2/INT External Interrupt Flag bit
1 = The GP2/INT external interrupt occurred (must be cleared in software)
0 = The GP2/INT external interrupt did not occur
bit 0
GPIF: Port Change Interrupt Flag bit
1 = When at least one of the GP5:GP0 pins changed state (must be cleared in software)
0 = None of the GP5:GP0 pins have changed state
Note 1: IOC register must also be enabled to enable an interrupt-on-change.
2: T0IF bit is set when TIMER0 rolls over. TIMER0 is unchanged on RESET and
should be initialized before clearing T0IF bit.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
 2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS70091A-page 11
rfPIC12F675
2.2.2.4
PIE1 Register
The PIE1 register contains the interrupt enable bits, as
shown in Register 2-4.
REGISTER 2-4:
Note:
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
PIE1 — PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
R/W-0
R/W-0
U-0
U-0
R/W-0
U-0
U-0
R/W-0
EEIE
ADIE
—
—
CMIE
—
—
TMR1IE
bit 7
bit 0
bit 7
EEIE: EE Write Complete Interrupt Enable bit
1 = Enables the EE write complete interrupt
0 = Disables the EE write complete interrupt
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5-4
Unimplemented: Read as ‘0’
bit 3
CMIE: Comparator Interrupt Enable bit
1 = Enables the comparator interrupt
0 = Disables the comparator interrupt
bit 2-1
Unimplemented: Read as ‘0’
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
DS70091A-page 12
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
 2003 Microchip Technology Inc.
rfPIC12F675
2.2.2.5
PIR1 Register
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-5.
REGISTER 2-5:
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
PIR1 — PERIPHERAL INTERRUPT REGISTER 1 (ADDRESS: 0Ch)
R/W-0
R/W-0
U-0
U-0
R/W-0
U-0
U-0
R/W-0
EEIF
ADIF
—
—
CMIF
—
—
TMR1IF
bit 7
bit 0
bit 7
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation has not completed or has not been started
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = The A/D conversion is complete (must be cleared in software)
0 = The A/D conversion is not complete
bit 5-4
Unimplemented: Read as ‘0’
bit 3
CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed (must be cleared in software)
0 = Comparator input has not changed
bit 2-1
Unimplemented: Read as ‘0’
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
 2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS70091A-page 13
rfPIC12F675
2.2.2.6
PCON Register
The Power Control (PCON) register contains flag bits
to differentiate between a:
•
•
•
•
Power-on Reset (POR)
Brown-out Detect (BOD)
Watchdog Timer Reset (WDT)
External MCLR Reset
The PCON Register bits are shown in Register 2-6.
REGISTER 2-6:
PCON — POWER CONTROL REGISTER (ADDRESS: 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-x
—
—
—
—
—
—
POR
BOD
bit 7
bit 0
bit 7-2
Unimplemented: Read as '0'
bit 1
POR: Power-on Reset STATUS bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOD: Brown-out Detect STATUS bit
1 = No Brown-out Detect occurred
0 = A Brown-out Detect occurred (must be set in software after a Brown-out Detect occurs)
Legend:
2.2.2.7
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
OSCCAL Register
The Oscillator Calibration register (OSCCAL) is used to
calibrate the internal 4 MHz oscillator. It contains 6 bits
to adjust the frequency up or down to achieve 4 MHz.
The OSCCAL register bits are shown in Register 2-7.
REGISTER 2-7:
OSCCAL — OSCILLATOR CALIBRATION REGISTER (ADDRESS: 90h)
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
U-0
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
—
—
bit 7
bit 0
bit 7-2
CAL5:CAL0: 6-bit Signed Oscillator Calibration bits
111111 = Maximum frequency
100000 = Center frequency
000000 = Minimum frequency
bit 1-0
Unimplemented: Read as '0'
Legend:
DS70091A-page 14
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
 2003 Microchip Technology Inc.
rfPIC12F675
2.3
PCL and PCLATH
2.3.2
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.
On any RESET, the PC is cleared. Figure 2-3 shows the
two situations for the loading of the PC. The upper
example in Figure 2-3 shows how the PC is loaded on
a write to PCL (PCLATH<4:0> → PCH). The lower
example in Figure 2-3 shows how the PC is loaded
during a CALL or GOTO instruction (PCLATH<4:3> →
PCH).
FIGURE 2-3:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
8
PCLATH<4:0>
5
Instruction with
PCL as
Destination
The rfPIC12F675 Family has an 8-level deep x 13-bit
wide hardware stack (see Figure 2-1). The stack space
is not part of either program or data space and the stack
pointer is not readable or writable. The PC is PUSHed
onto the stack when a CALL instruction is executed, or
an interrupt causes a branch. The stack is POPed in
the event of a RETURN,
RETLW or a RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1: There are no STATUS bits to indicate
stack overflow or stack underflow
conditions.
ALU result
PCLATH
PCH
12
11 10
PCL
8
STACK
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.
0
7
GOTO, CALL
PC
2
PCLATH<4:3>
11
Opcode <10:0>
PCLATH
2.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When performing a table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block). Refer to the
Application Note “Implementing a Table Read"
(AN556).
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 15
rfPIC12F675
2.4
Indirect Addressing, INDF and
FSR Registers
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 2-1.
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
EXAMPLE 2-1:
Indirect addressing is possible by using the INDF
register. Any instruction using the INDF register actually accesses data pointed to by the File Select register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a no
operation (although STATUS bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-4.
FIGURE 2-4:
movlw
movwf
clrf
incf
btfss
goto
NEXT
0x20
FSR
INDF
FSR
FSR,4
NEXT
CONTINUE
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
DIRECT/INDIRECT ADDRESSING rfPIC12F675
Direct Addressing
RP1(1) RP0
INDIRECT ADDRESSING
6
From Opcode
Indirect Addressing
IRP(1)
0
7
Bank Select
Bank Select Location Select
00
01
10
FSR Register
0
Location Select
11
00h
180h
Data
Memory
Not Used
7Fh
1FFh
Bank 0
Bank 1
Bank 2
Bank 3
For memory map detail see Figure 2-2.
Note 1: The RP1 and IRP bits are reserved; always maintain these bits clear.
DS70091A-page 16
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
3.0
GPIO PORT
register are maintained set when using them as analog
inputs. I/O pins configured as analog inputs always
read ‘0’.
There are as many as six general purpose I/O pins
available. Depending on which peripherals are
enabled, some or all of the pins may not be available as
general purpose I/O. In general, when a peripheral is
enabled, the associated pin may not be used as a
general purpose I/O pin.
Note:
3.1
Note:
Additional information on I/O ports may be
found in the PICmicro™ Mid-Range Reference Manual (DS33023)
EXAMPLE 3-1:
bcf
clrf
movlw
movwf
bsf
clrf
movlw
movwf
GPIO and the TRISIO Registers
GPIO is an 6-bit wide, bi-directional port. The
corresponding data direction register is TRISIO.
Setting a TRISIO bit (= 1) will make the corresponding
GPIO pin an input (i.e., put the corresponding output
driver in a Hi-impedance mode). Clearing a TRISIO bit
(= 0) will make the corresponding GPIO pin an output
(i.e., put the contents of the output latch on the selected
pin). The exception is GP3, which is input only and its
TRISIO bit will always read as ‘1’. Example 3-1 shows
how to initialize GPIO.
3.2
INITIALIZING GPIO
STATUS,RP0
GPIO
07h
CMCON
STATUS,RP0
ANSEL
0Ch
TRISIO
;Bank 0
;Init GPIO
;Set GP<2:0> to
;digital IO
;Bank 1
;Digital I/O
;Set GP<3:2> as inputs
;and set GP<5:4,1:0>
;as outputs
Additional Pin Functions
Every GPIO pin on the rfPIC12F675 has an interrupton-change option and every GPIO pin, except GP3,
has a weak pull-up option. The next two sections
describe these functions.
Reading the GPIO register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read,
this value is modified, and then written to the port data
latch. GP3 reads ‘0’ when MCLREN = 1.
3.2.1
WEAK PULL-UP
Each of the GPIO pins, except GP3, has an individually
configurable weak internal pull-up. Control bits WPUx
enable or disable each pull-up. Refer to Register 3-3.
Each weak pull-up is automatically turned off when the
port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset by the GPPU bit
(OPTION<7>).
The TRISIO register controls the direction of the
GP pins, even when they are being used as analog
inputs. The user must ensure the bits in the TRISIO
REGISTER 3-1:
The ANSEL (9Fh) and CMCON (19h)
registers (9Fh) must be initialized to
configure an analog channel as a digital
input. Pins configured as analog inputs will
read ‘0’.
GPIO — GPIO REGISTER (ADDRESS: 05h)
U-0
—
U-0
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
—
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
bit 7
bit 0
bit 7-6:
Unimplemented: Read as ’0’
bit 5-0:
GPIO<5:0>: General Purpose I/O pin.
1 = Port pin is >VIH
0 = Port pin is <VIL
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
 2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS70091A-page 17
rfPIC12F675
REGISTER 3-2:
TRISIO — GPIO TRISTATE REGISTER (ADDRESS: 85h)
U-0
—
U-0
R/W-x
R/W-x
R-1
—
TRISIO5
TRISIO4
TRISIO3
R/W-x
R/W-x
TRISIO2 TRISIO1
R/W-x
TRISIO0
bit 7
bit 0
bit 7-6:
Unimplemented: Read as ’0’
bit 5-0:
TRISIO<5:0>: General Purpose I/O Tri-State Control bit
1 = GPIO pin configured as an input (tri-stated)
0 = GPIO pin configured as an output.
Note:
TRISIO<3> always reads 1.
Legend:
REGISTER 3-3:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
WPU — WEAK PULL-UP REGISTER (ADDRESS: 95h)
U-0
U-0
R/W-1
R/W-1
U-0
R/W-1
R/W-1
R/W-1
—
—
WPU5
WPU4
—
WPU2
WPU1
WPU0
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
WPU<5:4>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
WPU<2:0>: Weak Pull-up Register bit
1 = Pull-up enabled
0 = Pull-up disabled
Note 1: Global GPPU must be enabled for individual pull-ups to be enabled.
2: The weak pull-up device is automatically disabled if the pin is in Output mode
(TRISIO = 0).
Legend:
DS70091A-page 18
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
 2003 Microchip Technology Inc.
rfPIC12F675
3.2.2
INTERRUPT-ON-CHANGE
Each of the GPIO pins is individually configurable as an
interrupt-on-change pin. Control bits IOC enable or
disable the interrupt function for each pin. Refer to
Register 3-4. The interrupt-on-change is disabled on a
Power-on Reset.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
GPIO. The ‘mismatch’ outputs of the last read are OR'd
together to set, the GP Port Change Interrupt flag bit
(GPIF) in the INTCON register.
REGISTER 3-4:
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
Any read or write of GPIO. This will end the
mismatch condition.
Clear the flag bit GPIF.
b)
A mismatch condition will continue to set flag bit GPIF.
Reading GPIO will end the mismatch condition and
allow flag bit GPIF to be cleared.
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF interrupt flag may not get set.
IOC — INTERRUPT-ON-CHANGE GPIO REGISTER (ADDRESS: 96h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5-0
IOC<5:0>: Interrupt-on-Change GPIO Control bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Note 1: Global interrupt enable (GIE) must be enabled for individual interrupts to be
recognized.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
 2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS70091A-page 19
rfPIC12F675
3.3
Pin Descriptions and Diagrams
FIGURE 3-1:
Each GPIO pin is multiplexed with other functions. The
pins and their combined functions are briefly described
here. For specific information about individual functions
such as the comparator or the A/D, refer to the
appropriate section in this Data Sheet.
3.3.1
GP0/AN0/CIN+
Data Bus
WR
WPU
BLOCK DIAGRAM OF GP0
AND GP1 PINS
Analog
Input Mode
D
CK
Q
VDD
Q
Weak
GPPU
RD
WPU
Figure 3-1 shows the diagram for this pin. The GP0 pin
is configurable to function as one of the following:
• a general purpose I/O
• an analog input for the A/D
• an analog input to the comparator
3.3.2
D
WR
PORT
as a general purpose I/O
an analog input for the A/D
an analog input to the comparator
a voltage reference input for the A/D
Q
I/O pin
GP1/AN1/CIN-/VREF
D
Figure 3-1 shows the diagram for this pin. The GP1 pin
is configurable to function as one of the following:
•
•
•
•
CK
VDD
Q
WR
TRISIO
CK
Q
Q
VSS
Analog
Input Mode
RD
TRISIO
RD
PORT
D
WR
IOC
CK
Q
Q
D
Q
EN
RD
IOC
Q
D
EN
Interrupt-on-Change
RD PORT
To Comparator
To A/D Converter
DS70091A-page 20
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
3.3.3
3.3.4
GP2/AN2/T0CKI/INT/COUT
GP3/MCLR/VPP
Figure 3-2 shows the diagram for this pin. The GP2 pin
is configurable to function as one of the following:
Figure 3-3 shows the diagram for this pin. The GP3 pin
is configurable to function as one of the following:
•
•
•
•
•
• a general purpose input
• as Master Clear Reset
a general purpose I/O
an analog input for the A/D
the clock input for TMR0
an external edge triggered interrupt
a digital output from the comparator
FIGURE 3-3:
Data Bus
FIGURE 3-2:
Data Bus
WR
WPU
D
CK
RD
TRISIO
Analog
Input Mode
VDD
Q
D
WR
PORT
WR
IOC
Q
Q
RD
IOC
VDD
Q
D
Q
Q
D
EN
CK
Q
COUT
Interrupt-on-Change
1
0
D
WR
TRISIO
CK
VSS
EN
Analog
Input
Mode
COUT
Enable
MCLRE
D
GPPU
RD
WPU
I/O pin
VSS
RD
PORT
Weak
MCLRE
RESET
BLOCK DIAGRAM OF GP2
Q
BLOCK DIAGRAM OF GP3
CK
I/O pin
RD PORT
Q
Q
VSS
Analog
Input Mode
RD
TRISIO
RD
PORT
D
WR
IOC
CK
Q
Q
D
Q
EN
RD
IOC
Q
Interrupt-on-Change
D
EN
RD PORT
To TMR0
To INT
To A/D Converter
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 21
rfPIC12F675
3.3.5
3.3.6
GP4/AN3/T1G/OSC2/CLKOUT
GP5/T1CKI/OSC1/CLKIN
Figure 3-4 shows the diagram for this pin. The GP4 pin
is configurable to function as one of the following:
Figure 3-5 shows the diagram for this pin. The GP5 pin
is configurable to function as one of the following:
•
•
•
•
•
•
•
•
•
a general purpose I/O
an analog input for the A/D
a TMR1 gate input
a crystal/resonator connection
a clock output
a general purpose I/O
a TMR1 clock input
a crystal/resonator connection
a clock input
FIGURE 3-5:
FIGURE 3-4:
Analog
Input Mode
Data Bus
WR
WPU
D
CK
BLOCK DIAGRAM OF GP5
BLOCK DIAGRAM OF GP4
INTOSC
Mode
CLK
Modes(1)
Q
Data Bus
TMR1LPEN(1)
D
Q
WR
WPU
Weak
CK
Weak
Q
GPPU
RD
WPU
GPPU
RD
WPU
Oscillator
Circuit
Oscillator
Circuit
OSC1
D
WR
PORT
CK
Q
FOSC/4
OSC2
VDD
CLKOUT
Enable
D
WR
PORT
1
0
CLKOUT
Enable
D
WR
TRISIO
CK
D
WR
TRISIO
INTOSC/
RC/EC(2)
CK
Q
Q
VSS
INTOSC
Mode
RD
TRISIO
Q
CLKOUT
Enable
(2)
RD
PORT
Analog
Input Mode
D
RD
PORT
CK
Q
Q
RD
TRISIO
D
CK
WR
IOC
Q
CK
Q
Q
RD
IOC
D
Q
EN
Q
Interrupt-on-Change
D
Q
EN
Q
RD
IOC
VDD
Q
I/O pin
I/O pin
Q
VSS
WR
IOC
VDD
Q
VDD
Q
D
D
EN
Interrupt-on-Change
EN
RD PORT
RD PORT
To TMR1 or CLKGEN
To TMR1 T1G
To A/D Converter
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2: With CLKOUT option.
DS70091A-page 22
Preliminary
Note
1: Timer1 LP Oscillator enabled
2: When using Timer1 with LP oscillator, the Schmitt
Trigger is by-passed.
 2003 Microchip Technology Inc.
rfPIC12F675
TABLE 3-1:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH GPIO
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOD
Value on all
other
RESETS
05h
GPIO
—
—
GP5
GP4
GP3
GP2
GP1
GP0
--xx xxxx
--uu uuuu
0Bh/8Bh
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
0000 000u
19h
CMCON
—
COUT
—
CINV
CIS
CM2
CM1
CM0
-0-0 0000
-0-0 0000
1111 1111
81h
OPTION_REG
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
85h
TRISIO
—
—
TRISIO5
TRISIO4
TRISIO3
TRISIO2
TRISIO1
TRISIO0
--11 1111
--11 1111
95h
WPU
—
—
WPU5
WPU4
—
WPU2
WPU1
WPU0
--11 -111
--11 -111
96h
IOC
—
—
IOC5
IOC4
IOC3
IOC2
IOC1
IOC0
--00 0000
--00 0000
9Fh
ANSEL
—
ADCS2
ADCS1
ADCS0
ANS3
ANS2
ANS1
ANS0
-000 1111
-000 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by GPIO.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 23
rfPIC12F675
NOTES:
DS70091A-page 24
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
4.0
TIMER0 MODULE
Counter mode is selected by setting the T0CS bit
(OPTION_REG<5>). In this mode, the Timer0 module
will increment either on every rising or falling edge of
pin GP2/T0CKI. The incrementing edge is determined
by
the
source
edge
(T0SE)
control
bit
(OPTION_REG<4>). Clearing the T0SE bit selects the
rising edge.
The Timer0 module timer/counter has the following
features:
•
•
•
•
•
•
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
Note:
Figure 4-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
Note:
4.1
4.2
Additional information on the Timer0
module is available in the PICmicroTM MidRange Reference Manual (DS33023).
Timer0 Interrupt
A Timer0 interrupt is generated when the TMR0
register timer/counter overflows from FFh to 00h. This
overflow sets the T0IF bit. The interrupt can be masked
by clearing the T0IE bit (INTCON<5>). The T0IF bit
(INTCON<2>) must be cleared in software by the
Timer0 module Interrupt Service Routine before reenabling this interrupt. The Timer0 interrupt cannot
wake the processor from SLEEP since the timer is
shut-off during SLEEP.
Timer0 Operation
Timer mode is selected by clearing the T0CS bit
(OPTION_REG<5>). In Timer mode, the Timer0
module will increment every instruction cycle (without
prescaler). If TMR0 is written, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
FIGURE 4-1:
Counter mode has specific external clock
requirements. Additional information on
these requirements is available in the
PICmicroTM Mid-Range Reference Manual
(DS33023).
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
CLKOUT
(= FOSC/4)
Data Bus
0
8
1
SYNC 2
Cycles
1
T0CKI
pin
0
T0SE
T0CS
8-bit
Prescaler
Set Flag bit T0IF
on Overflow
PSA
1
PSA
TMR0
0
8
PS0 - PS2
1
WDT
Time-out
Watchdog
Timer
0
PSA
WDTE
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 25
rfPIC12F675
4.3
Using Timer0 with an External
Clock
a small RC delay of 20 ns) and low for at least 2TOSC
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2TOSC (and
REGISTER 4-1:
Note:
The ANSEL (9Fh) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
OPTION_REG — OPTION REGISTER (ADDRESS: 81h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
GPPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
GPPU: GPIO Pull-up Enable bit
1 = GPIO pull-ups are disabled
0 = GPIO pull-ups are enabled by individual port latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of GP2/INT pin
0 = Interrupt on falling edge of GP2/INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on GP2/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on GP2/T0CKI pin
0 = Increment on low-to-high transition on GP2/T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the TIMER0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
DS70091A-page 26
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
 2003 Microchip Technology Inc.
rfPIC12F675
4.4
Prescaler
EXAMPLE 4-1:
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. For simplicity, this counter will be referred to as
“prescaler” throughout this Data Sheet. The prescaler
assignment is controlled in software by the control bit
PSA (OPTION_REG<3>). Clearing the PSA bit will
assign the prescaler to Timer0. Prescale values are
selectable via the PS2:PS0 bits (OPTION_REG<2:0>).
bcf
STATUS,RP0
clrwdt
clrf
TMR0
bsf
SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution). To avoid an unintended device
RESET,
the
following
instruction
sequence
(Example 4-1) must be executed when changing the
prescaler assignment from Timer0 to WDT.
To change prescaler from the WDT to the TMR0
module, use the sequence shown in Example 4-2. This
precaution must be taken even if the WDT is disabled.
EXAMPLE 4-2:
Address
CHANGING PRESCALER
(WDT→TIMER0)
clrwdt
;Clear WDT and
; postscaler
;Bank 1
bsf
STATUS,RP0
movlw
b’xxxx0xxx’ ;Select TMR0,
; prescale, and
; clock source
OPTION_REG ;
STATUS,RP0 ;Bank 0
movwf
bcf
TABLE 4-1:
STATUS,RP0
;Bank 0
;Clear WDT
;Clear TMR0 and
; prescaler
;Bank 1
movlw
b’00101111’ ;Required if desired
movwf
OPTION_REG ; PS2:PS0 is
clrwdt
; 000 or 001
;
movlw
b’00101xxx’ ;Set postscaler to
movwf
OPTION_REG ; desired WDT rate
bcf
STATUS,RP0 ;Bank 0
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing
to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer.
4.4.1
CHANGING PRESCALER
(TIMER0→WDT)
REGISTERS ASSOCIATED WITH TIMER0
Name
01h
TMR0
0Bh/8Bh
INTCON
Bit 7
Bit 6
Value on
POR, BOD
Value on
all other
RESETS
xxxx xxxx
uuuu uuuu
0000 0000
0000 000u
1111 1111
1111 1111
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111
--11 1111
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
T0IE
INTE
GPIE
T0IF
INTF
GPIF
T0CS
T0SE
PSA
PS2
PS1
PS0
Timer0 Module Register
GIE
PEIE
GPPU
INTEDG
—
—
81h
OPTION_REG
85h
TRISIO
Legend:
— = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown.
Shaded cells are not used by the Timer0 module.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 27
rfPIC12F675
5.0
TIMER1 MODULE WITH GATE
CONTROL
The Timer1 Control register (T1CON), shown in
Register 5-1, is used to enable/disable Timer1 and
select the various features of the Timer1 module.
The rfPIC12F675 devices have a 16-bit timer. Figure 5-1
shows the basic block diagram of the Timer1 module.
Timer1 has the following features:
•
•
•
•
•
•
•
•
Note:
Additional information on timer modules is
available in the PICmicroTM Mid-Range
Reference Manual (DS33023).
16-bit timer/counter (TMR1H:TMR1L)
Readable and writable
Internal or external clock selection
Synchronous or asynchronous operation
Interrupt on overflow from FFFFh to 0000h
Wake-up upon overflow (Asynchronous mode)
Optional external enable input (T1G)
Optional LP oscillator
FIGURE 5-1:
TIMER1 BLOCK DIAGRAM
TMR1ON
TMR1GE
T1G
TMR1ON
TMR1GE
Set Flag bit
TMR1IF on
Overflow
TMR1
Synchronized
Clock Input
0
TMR1H
TMR1L
1
LP Oscillator
T1SYNC
OSC1
OSC2
INTOSC
w/o CLKOUT
T1OSCEN
1
FOSC/4
Internal
Clock
Prescaler
1, 2, 4, 8
Synchronize
Detect
0
2
T1CKPS<1:0>
SLEEP Input
TMR1CS
LP
DS70091A-page 28
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
5.1
5.2
Timer1 Modes of Operation
The Timer1 register pair (TMR1H:TMR1L) increments
to FFFFh and rolls over to 0000h. When Timer1 rolls
over, the Timer1 interrupt flag bit (PIR1<0>) is set. To
enable the interrupt on rollover, you must set these bits:
Timer1 can operate in one of three modes:
• 16-bit timer with prescaler
• 16-bit synchronous counter
• 16-bit asynchronous counter
In Timer mode, Timer1 is incremented on every
instruction cycle. In Counter mode, Timer1 is
incremented on the rising edge of the external clock
input T1CKI. In addition, the Counter mode clock can
be synchronized to the microcontroller system clock
or run asynchronously.
• Timer1 interrupt Enable bit (PIE1<0>)
• PEIE bit (INTCON<6>)
• GIE bit (INTCON<7>).
The interrupt is cleared by clearing the TMR1IF in the
Interrupt Service Routine.
Note:
In Counter and Timer modules, the counter/timer clock
can be gated by the T1G input.
If an external clock oscillator is needed (and the
microcontroller is using the INTOSC w/o CLKOUT),
Timer1 can use the LP oscillator as a clock source.
Note:
In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge.
FIGURE 5-2:
Timer1 Interrupt
5.3
The TMR1H:TTMR1L register pair and the
TMR1IF bit should be cleared before
enabling interrupts.
Timer1 Prescaler
Timer1 has four prescaler options allowing 1, 2, 4, or 8
divisions of the clock input. The T1CKPS bits
(T1CON<5:4>) control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write
to TMR1H or TMR1L.
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the
clock.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 29
rfPIC12F675
REGISTER 5-1:
T1CON — TIMER1 CONTROL REGISTER (ADDRESS: 10h)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN
R/W-0
R/W-0
R/W-0
T1SYNC
TMR1CS
TMR1ON
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
TMR1GE: Timer1 Gate Enable bit
If TMR1ON = 0:
This bit is ignored
If TMR1ON = 1:
1 = Timer1 is on if T1G pin is low
0 = Timer1 is on
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale Value
10 = 1:4 Prescale Value
01 = 1:2 Prescale Value
00 = 1:1 Prescale Value
bit 3
T1OSCEN: LP Oscillator Enable Control bit
If INTOSC without CLKOUT oscillator is active:
1 = LP oscillator is enabled for Timer1 clock
0 = LP oscillator is off
Else:
This bit is ignored
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock.
bit 1
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from T1OSO/T1CKI pin (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
DS70091A-page 30
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
 2003 Microchip Technology Inc.
rfPIC12F675
5.4
5.5
Timer1 Operation in
Asynchronous Counter Mode
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow, which will wake-up
the processor. However, special precautions in
software are needed to read/write the timer
(Section 5.4.1).
Note:
5.4.1
The ANSEL (9Fh) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
Reading TMR1H or TMR1L, while the timer is running
from an external asynchronous clock, will ensure a
valid read (taken care of in hardware). However, the
user should keep in mind that reading the 16-bit timer
in two 8-bit values itself, poses certain problems, since
the timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write
contention may occur by writing to the timer registers,
while the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care.
Examples 12-2 and 12-3 in the PICmicro™ Mid-Range
MCU Family Reference Manual (DS33023) show how
to read and write Timer1 when it is running in
Asynchronous mode.
Address
Name
0Bh/8Bh INTCON
A crystal oscillator circuit is built-in between pins OSC1
(input) and OSC2 (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The
oscillator is a low power oscillator rated up to 37 kHz. It
will continue to run during SLEEP. It is primarily
intended for a 32 kHz crystal. Table 10-2 shows the
capacitor selection for the Timer1 oscillator.
The Timer1 oscillator is shared with the system LP
oscillator. Thus, Timer1 can use this mode only when
the system clock is derived from the internal oscillator.
As with the system LP oscillator, the user must provide
a software time delay to ensure proper oscillator
start-up.
While enabled, TRISIO4 and TRISIO5 are set. GP4
and GP5 read ‘0’ and TRISIO4 and TRISIO5 are read
‘1’.
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER MODE
TABLE 5-1:
Timer1 Oscillator
Note:
5.6
The oscillator requires a start-up and
stabilization time before use. Thus,
T1OSCEN should be set and a suitable
delay observed prior to enabling Timer1.
Timer1 Operation During SLEEP
Timer1 can only operate during SLEEP when setup in
Asynchronous Counter mode. In this mode, an external
crystal or clock source can be used to increment the
counter. To setup the timer to wake the device:
• Timer1 must be on (T1CON<0>)
• TMR1IE bit (PIE1<0>) must be set
• PEIE bit (INTCON<6>) must be set
The device will wake-up on an overflow. If the GIE bit
(INTCON<7>) is set, the device will wake-up and jump
to the Interrupt Service Routine on an overflow.
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Value on
all other
RESETS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOD
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000 0000 000u
EEIF
ADIF
—
—
CMIF
—
—
TMR1IF 00-- 0--0 00-- 0--0
0Ch
PIR1
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
10h
T1CON
—
TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -000 0000 -uuu uuuu
8Ch
PIE1
Legend:
x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module.
EEIE
ADIE
 2003 Microchip Technology Inc.
—
—
CMIE
Preliminary
—
—
TMR1IE 00-- 0--0 00-- 0--0
DS70091A-page 31
rfPIC12F675
NOTES:
DS70091A-page 32
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
6.0
COMPARATOR MODULE
be applied to an input of the comparator. In addition,
GP2 can be configured as the comparator output.
The Comparator Control Register (CMCON), shown
in Register 6-1, contains the bits to control the
comparator.
The rfPIC12F675 devices have one analog
comparator. The inputs to the comparator are
multiplexed with the GP0 and GP1 pins. There is an
on-chip Comparator Voltage Reference that can also
REGISTER 6-1:
CMCON — COMPARATOR CONTROL REGISTER (ADDRESS: 19h)
U-0
R-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
COUT
—
CINV
CIS
CM2
CM1
CM0
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
COUT: Comparator Output bit
When CINV = 0:
1 = VIN+ > VIN0 = VIN+ < VINWhen CINV = 1:
1 = VIN+ < VIN0 = VIN+ > VIN-
bit 5
Unimplemented: Read as ‘0’
bit 4
CINV: Comparator Output Inversion bit
1 = Output inverted
0 = Output not inverted
bit 3
CIS: Comparator Input Switch bit
When CM2:CM0 = 110 or 101:
1 = VIN- connects to CIN+
0 = VIN- connects to CIN-
bit 2-0
CM2:CM0: Comparator Mode bits
Figure 6-2 shows the Comparator modes and CM2:CM0 bit settings
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
 2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS70091A-page 33
rfPIC12F675
6.1
Comparator Operation
TABLE 6-1:
A single comparator is shown in Figure 6-1, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+ is less
than the analog input VIN-, the output of the comparator
is a digital low level. When the analog input at VIN+ is
greater than the analog input VIN-, the output of the
comparator is a digital high level. The shaded areas of
the output of the comparator in Figure 6-1 represent
the uncertainty due to input offsets and response time.
Note:
To use CIN+ and CIN- pins as analog
inputs, the appropriate bits must be
programmed in the CMCON (19h) register.
The polarity of the comparator output can be inverted
by setting the CINV bit (CMCON<4>). Clearing CINV
results in a non-inverted output. A complete table
showing the output state versus input conditions and
the polarity bit is shown in Table 6-1.
OUTPUT STATE VS. INPUT
CONDITIONS
Input Conditions
CINV
COUT
VIN- > VIN+
0
0
VIN- < VIN+
0
1
VIN- > VIN+
1
1
VIN- < VIN+
1
0
FIGURE 6-1:
SINGLE COMPARATOR
VIN+
+
VIN-
–
Output
VINVIN+
Output
Note:
DS70091A-page 34
Preliminary
CINV bit (CMCON<4>) is clear.
 2003 Microchip Technology Inc.
rfPIC12F675
6.2
Comparator Configuration
There are eight modes of operation for the comparator.
The CMCON register, shown in Register 6-1, is used to
select the mode. Figure 6-2 shows the eight possible
modes. The TRISIO register controls the data direction
of the comparator pins for each mode. If the
FIGURE 6-2:
Comparator mode is changed, the comparator output
level may not be valid for a specified period of time.
Refer to the specifications in Section 13.0.
Note:
Comparator interrupts should be disabled
during a Comparator mode change. Otherwise, a false interrupt may occur.
COMPARATOR I/O OPERATING MODES
Comparator Reset (POR Default Value - low power)
Comparator Off (Lowest power)
CM2:CM0 = 000
CM2:CM0 = 111
GP1/CIN-
A
GP0/CIN+
A
GP2/COUT
D
Off (Read as '0')
GP1/CIN-
D
GP0/CIN+
D
GP2/COUT
D
Off (Read as '0')
Comparator without Output
Comparator w/o Output and with Internal Reference
CM2:CM0 = 010
CM2:CM0 = 100
GP1/CIN-
A
GP0/CIN+
A
GP2/COUT
D
COUT
GP1/CIN-
A
GP0/CIN+
D
GP2/COUT
D
COUT
From CVREF Module
Comparator with Output and Internal Reference
Multiplexed Input with Internal Reference and Output
CM2:CM0 = 011
CM2:CM0 = 101
GP1/CIN-
A
GP0/CIN+
D
GP2/COUT
D
COUT
GP1/CIN-
A
GP0/CIN+
A
GP2/COUT
D
CIS = 0
CIS = 1
COUT
From CVREF Module
From CVREF Module
Comparator with Output
Multiplexed Input with Internal Reference
CM2:CM0 = 001
CM2:CM0 = 110
GP1/CIN-
A
GP0/CIN+
A
GP2/COUT
D
COUT
GP1/CIN-
A
GP0/CIN+
A
GP2/COUT
D
CIS = 0
CIS = 1
COUT
From CVREF Module
A = Analog Input, ports always reads ‘0’
D = Digital Input
CIS = Comparator Input Switch (CMCON<3>)
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 35
rfPIC12F675
6.3
Analog Input Connection
Considerations
range by more than 0.6V in either direction, one of the
diodes is forward biased and a latchup may occur. A
maximum
source
impedance
of
10 kΩ
is
recommended for the analog sources. Any external
component connected to an analog input pin, such as
a capacitor or a Zener diode, should have very little
leakage current.
A simplified circuit for an analog input is shown in
Figure 6-3. Since the analog pins are connected to a
digital output, they have reverse biased diodes to VDD
and VSS. The analog input, therefore, must be between
VSS and VDD. If the input voltage deviates from this
FIGURE 6-3:
ANALOG INPUT MODE
VDD
VT = 0.6V
Rs < 10K
RIC
AIN
CPIN
5 pF
VA
Leakage
±500 nA
VT = 0.6V
Vss
Legend:
6.4
CPIN
VT
ILEAKAGE
RIC
RS
VA
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to Various Junctions
= Interconnect Resistance
= Source Impedance
= Analog Voltage
Comparator Output
The TRISIO<2> bit functions as an output enable/
disable for the GP2 pin while the comparator is in an
Output mode.
The comparator output, COUT, is read through the
CMCON register. This bit is read-only. The comparator
output may also be directly output to the GP2 pin in
three of the eight possible modes, as shown in
Figure 6-2. When in one of these modes, the output on
GP2 is asynchronous to the internal clock. Figure 6-4
shows the comparator output block diagram.
Note 1: When reading the GPIO register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
TTL input specification.
2: Analog levels on any pin that is defined as
a digital input, may cause the input buffer
to consume more current than is
specified.
FIGURE 6-4:
MODIFIED COMPARATOR OUTPUT BLOCK DIAGRAM
GP0/CIN+
GP1/CIN-
To GP2/T0CKI pin
To Data Bus
Q
RD CMCON
Set CMIF bit
CVREF
D
EN
Q
CINV
CM2:CM0
D
RD CMCON
EN
RESET
DS70091A-page 36
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
6.5
Comparator Reference
The following equations determine the output voltages:
The comparator module also allows the selection of an
internally generated voltage reference for one of the
comparator inputs. The internal reference signal is
used for four of the eight Comparator modes. The
VRCON register, Register 6-2, controls the voltage
reference module shown in Figure 6-5.
6.5.1
CONFIGURING THE VOLTAGE
REFERENCE
The voltage reference can output 32 distinct voltage
levels, 16 in a high range and 16 in a low range.
FIGURE 6-5:
VRR = 1 (low range): CVREF = (VR3:VR0 / 24) x VDD
VRR = 0 (high range): CVREF = (VDD / 4) + (VR3:VR0 x
VDD / 32)
6.5.2
VOLTAGE REFERENCE
ACCURACY/ERROR
The full range of VSS to VDD cannot be realized due to
the construction of the module. The transistors on the
top and bottom of the resistor ladder network
(Figure 6-5) keep CVREF from approaching VSS or
VDD. The Voltage Reference is VDD derived and therefore, the CVREF output changes with fluctuations in
VDD. The tested absolute accuracy of the Comparator
Voltage Reference can be found in Section 13.0.
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
16 Stages
8R
R
R
R
R
VDD
8R
VRR
16-1 Analog
MUX
VREN
CVREF to
Comparator
Input
VR3:VR0
6.6
Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output is ensured to have a valid level. If
the internal reference is changed, the maximum delay
of the internal voltage reference must be considered
when using the comparator outputs. Otherwise, the
maximum delay of the comparators should be used
(Table 13-7).
6.7
Operation During SLEEP
Both the comparator and voltage reference, if enabled
before entering SLEEP mode, remain active during
SLEEP. This results in higher SLEEP currents than
shown in the power-down specifications. The
additional current consumed by the comparator and the
voltage reference is shown separately in the specifications. To minimize power consumption while in SLEEP
mode, turn off the comparator, CM2:CM0 = 111, and
voltage reference, VRCON<7> = 0.
 2003 Microchip Technology Inc.
While the comparator is enabled during SLEEP, an
interrupt will wake-up the device. If the device wakes
up from SLEEP, the contents of the CMCON and
VRCON registers are not affected.
6.8
Effects of a RESET
A device RESET forces the CMCON and VRCON
registers to their RESET states. This forces the
comparator module to be in the Comparator Reset
mode, CM2:CM0 = 000 and the voltage reference to its
off state. Thus, all potential inputs are analog inputs
with the comparator and voltage reference disabled to
consume the smallest current possible.
Preliminary
DS70091A-page 37
rfPIC12F675
REGISTER 6-2:
VRCON — VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VREN
—
VRR
—
VR3
VR2
VR1
VR0
bit 7
bit 0
bit 7
VREN: CVREF Enable bit
1 = CVREF circuit powered on
0 = CVREF circuit powered down, no IDD drain
bit 6
Unimplemented: Read as '0'
bit 5
VRR: CVREF Range Selection bit
1 = Low range
0 = High range
bit 4
Unimplemented: Read as '0'
bit 3-0
VR3:VR0: CVREF value selection 0 ≤ VR [3:0] ≤ 15
When VRR = 1: CVREF = (VR3:VR0 / 24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR3:VR0 / 32) * VDD
Legend:
6.9
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Comparator Interrupts
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
The comparator interrupt flag is set whenever there is
a change in the output value of the comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<3>, is the comparator interrupt flag.
This bit must be reset in software by clearing it to ‘0’.
Since it is also possible to write a '1' to this register, a
simulated interrupt may be initiated.
a)
Any read or write of CMCON. This will end the
mismatch condition.
Clear flag bit CMIF.
b)
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition, and
allow flag bit CMIF to be cleared.
Note:
The CMIE bit (PIE1<3>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt. In
addition, the GIE bit must also be set. If any of these
bits are cleared, the interrupt is not enabled, though the
CMIF bit will still be set if an interrupt condition occurs.
TABLE 6-2:
x = Bit is unknown
If a change in the CMCON register (COUT)
should occur when a read operation is
being executed (start of the Q2 cycle), then
the CMIF (PIR1<3>) interrupt flag may not
get set.
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOD
Value on
all other
RESETS
INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
0000 000u
0Ch
PIR1
EEIF
ADIF
—
—
CMIF
—
—
TMR1IF
00-- 0--0
00-- 0--0
19h
CMCON
—
COUT
—
CINV
CIS
CM2
CM1
CM0
-0-0 0000
-0-0 0000
—
—
CMIE
—
—
TMR1IE
00-- 0--0
00-- 0--0
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0
--11 1111
--11 1111
0-0- 0000
0-0- 0000
Address
0Bh/8Bh
8Ch
PIE1
EEIE
ADIE
85h
TRISIO
—
—
99h
VRCON
VREN
—
Legend:
VRR
—
VR3
VR2
VR1
VR0
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the comparator module.
DS70091A-page 38
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
7.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The output of the sample and hold is connected to the
input of the converter. The converter generates a
binary result via successive approximation and stores
the result in a 10-bit register. The voltage reference
used in the conversion is software selectable to either
VDD or a voltage applied by the VREF pin. Figure 7-1
shows the block diagram of the A/D.
The analog-to-digital converter (A/D) allows conversion
of an analog input signal to a 10-bit binary representation of that signal. The rfPIC12F675 has four analog
inputs, multiplexed into one sample and hold circuit.
FIGURE 7-1:
A/D BLOCK DIAGRAM
VDD
VCFG = 0
VREF
VCFG = 1
GP0/AN0
GP1/AN1/VREF
ADC
GP2/AN2
10
GO/DONE
GP4/AN3
ADFM
CHS1:CHS0
10
ADON
ADRESH
ADRESL
VSS
7.1
A/D Configuration and Operation
There are two registers available to control the
functionality of the A/D module:
1.
2.
7.1.4
ADCON0 (Register 7-1)
ANSEL (Register 7-2)
7.1.1
ANALOG PORT PINS
The ANS3:ANS0 bits (ANSEL<3:0>) and the TRISIO
bits control the operation of the A/D port pins. Set the
corresponding TRISIO bits to set the pin output driver
to its high impedance state. Likewise, set the
corresponding ANS bit to disable the digital input
buffer.
Note:
7.1.2
Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
CHANNEL SELECTION
There are four analog channels, AN0 through AN3. The
CHS1:CHS0 bits (ADCON0<3:2>) control which
channel is connected to the sample and hold circuit.
7.1.3
controls the voltage reference selection. If VCFG is set,
then the voltage on the VREF pin is the reference;
otherwise, VDD is the reference.
CONVERSION CLOCK
The A/D conversion cycle requires 11 TAD. The source
of the conversion clock is software selectable via the
ADCS bits (ANSEL<6:4>). There are seven possible
clock options:
•
•
•
•
•
•
•
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal RC oscillator)
For correct conversion, the A/D conversion clock
(1/TAD) must be selected to ensure a minimum TAD of
1.6 µs. Table 7-1 shows a few TAD calculations for
selected frequencies.
VOLTAGE REFERENCE
There are two options for the voltage reference to the
A/D converter: either VDD is used, or an analog voltage
applied to VREF is used. The VCFG bit (ADCON0<6>)
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 39
rfPIC12F675
TABLE 7-1:
TAD vs. DEVICE OPERATING FREQUENCIES
A/D Clock Source (TAD)
Device Frequency
Operation
ADCS2:ADCS0
20 MHz
5 MHz
4 MHz
1.25 MHz
2 TOSC
000
100 ns(2)
400 ns(2)
500 ns(2)
1.6 µs
4 TOSC
100
200 ns(2)
800 ns(2)
1.0 µs(2)
3.2 µs
8 TOSC
001
400 ns(2)
1.6 µs
2.0 µs
6.4 µs
(2)
800 ns
3.2 µs
4.0 µs
12.8 µs(3)
16 TOSC
101
(3)
8.0 µs
25.6 µs(3)
32 TOSC
010
1.6 µs
6.4 µs
(3)
(3)
64 TOSC
110
3.2 µs
12.8 µs
16.0 µs
51.2 µs(3)
A/D RC
x11
2 - 6 µs(1,4)
2 - 6 µs(1,4)
2 - 6 µs(1,4)
2 - 6 µs(1,4)
Legend: Shaded cells are outside of recommended range.
Note 1: The A/D RC source has a typical TAD time of 4 µs for VDD > 3.0V.
2: These values violate the minimum required TAD time.
3: For faster conversion times, the selection of another clock source is recommended.
4: When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the
conversion will be performed during SLEEP.
7.1.5
STARTING A CONVERSION
previous conversion. After an aborted conversion, a
2 TAD delay is required before another acquisition can
be initiated. Following the delay, an input acquisition is
automatically started on the selected channel.
The A/D conversion is initiated by setting the
GO/DONE bit (ADCON0<1>). When the conversion is
complete, the A/D module:
Note:
• Clears the GO/DONE bit
• Sets the ADIF flag (PIR1<6>)
• Generates an interrupt (if enabled).
7.1.6
If the conversion must be aborted, the GO/DONE bit
can be cleared in software. The ADRESH:ADRESL
registers will not be updated with the partially complete
A/D
conversion
sample.
Instead,
the
ADRESH:ADRESL registers will retain the value of the
FIGURE 7-2:
The GO/DONE bit should not be set in the
same instruction that turns on the A/D.
CONVERSION OUTPUT
The A/D conversion can be supplied in two formats: left
or right shifted. The ADFM bit (ADCON0<7>) controls
the output format. Figure 7-2 shows the output formats.
10-BIT A/D RESULT FORMAT
ADRESH
(ADFM = 0)
ADRESL
MSB
LSB
Bit 7
Bit 0
Bit 7
10-bit A/D Result
(ADFM = 1)
Unimplemented: Read as ‘0’
MSB
Bit 7
LSB
Bit 0
Unimplemented: Read as ‘0
DS70091A-page 40
Bit 0
Preliminary
Bit 7
Bit 0
10-bit A/D Result
 2003 Microchip Technology Inc.
rfPIC12F675
REGISTER 7-1:
ADCON0 — A/D CONTROL REGISTER (ADDRESS: 1Fh)
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
VCFG
—
—
CHS1
CHS0
GO/DONE
ADON
bit 7
bit 0
bit 7
ADFM: A/D Result Formed Select bit
1 = Right justified
0 = Left justified
bit 6
VCFG: Voltage Reference bit
1 = VREF pin
0 = VDD
bit 5-4
Unimplemented: Read as zero
bit 3-2
CHS1:CHS0: Analog Channel Select bits
00 = Channel 00 (AN0)
01 = Channel 01 (AN1)
10 = Channel 02 (AN2)
11 = Channel 03 (AN3)
bit 1
GO/DONE: A/D Conversion STATUS bit
1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress
bit 0
ADON: A/D Conversion STATUS bit
1 = A/D converter module is operating
0 = A/D converter is shut-off and consumes no operating current
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
 2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS70091A-page 41
rfPIC12F675
REGISTER 7-2:
ANSEL — ANALOG SELECT REGISTER (ADDRESS: 9Fh)
U-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
—
ADCS2
ADCS1
ADCS0
ANS3
ANS2
ANS1
ANS0
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’.
bit 6-4
ADCS<2:0>: A/D Conversion Clock Select bits
000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64
bit 3-0
ANS3:ANS0: Analog Select bits
(Between analog or digital function on pins AN<3:0>, respectively.)
1 = Analog input; pin is assigned as analog input(1)
0 = Digital I/O; pin is assigned to port or special function
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry,
weak pull-ups, and interrupt-on-change. The corresponding TRISIO bit must be set
to Input mode in order to allow external control of the voltage on the pin.
Legend:
DS70091A-page 42
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
 2003 Microchip Technology Inc.
rfPIC12F675
7.2
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 7-3. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
Figure 7-3. The maximum recommended impedance for analog sources is 10 kΩ. As the impedance
is decreased, the acquisition time may be decreased.
EQUATION 7-1:
TACQ
TC
TACQ
After the analog input channel is selected (changed),
this acquisition must be done before the conversion
can be started.
To calculate the minimum acquisition time,
Equation 7-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D).
The 1/2 LSb error is the maximum error allowed for
the A/D to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PICmicro™ Mid-Range Reference Manual
(DS33023).
ACQUISITION TIME
= Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
=
=
=
=
=
=
=
TAMP + TC + TCOFF
2µs + TC + [(Temperature -25°C)(0.05µs/°C)]
CHOLD (RIC + RSS + RS) In(1/2047)
- 120pF (1kΩ + 7kΩ + 10kΩ) In(0.0004885)
16.47µs
2µs + 16.47µs + [(50°C -25°C)(0.05µs/°C)
19.72µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin
leakage specification.
FIGURE 7-3:
ANALOG INPUT MODEL
VDD
RS
ANx
VA
CPIN
5 pF
VT = 0.6V
VT = 0.6V
Sampling
Switch
RIC ≤ 1K SS RSS
CHOLD
= DAC capacitance
= 120 pF
I LEAKAGE
± 500 nA
VSS
= input capacitance
Legend CPIN
VT
= threshold voltage
I LEAKAGE = leakage current at the pin due to
various junctions
= interconnect resistance
RIC
SS
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
 2003 Microchip Technology Inc.
Preliminary
6V
5V
VDD 4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
(kΩ)
DS70091A-page 43
rfPIC12F675
7.3
A/D Operation During SLEEP
The A/D converter module can operate during SLEEP.
This requires the A/D clock source to be set to the
internal RC oscillator. When the RC clock source is
selected, the A/D waits one instruction before starting
the conversion. This allows the SLEEP instruction to be
executed, thus eliminating much of the switching noise
from the conversion. When the conversion is complete,
the GO/DONE bit is cleared, and the result is loaded
into the ADRESH:ADRESL registers. If the A/D
interrupt is enabled, the device awakens from SLEEP.
If the A/D interrupt is not enabled, the A/D module is
turned off, although the ADON bit remains set.
TABLE 7-2:
Address
05h
Name
GPIO
When the A/D clock source is something other than
RC, a SLEEP instruction causes the present conversion
to be aborted, and the A/D module is turned off. The
ADON bit remains set.
7.4
Effects of RESET
A device RESET forces all registers to their RESET
state. Thus the A/D module is turned off and any
pending conversion is aborted. The ADRESH:ADRESL
registers are unchanged.
SUMMARY OF A/D REGISTERS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOD
Value on
all other
RESETS
—
—
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
--xx xxxx
--uu uuuu
0Bh, 8Bh INTCON
GIE
PEIE
T0IE
INTE
GPIE
T0IF
INTF
GPIF
0000 0000
0000 000u
0Ch
PIR1
EEIF
ADIF
—
—
CMIF
—
—
TMR1IF
00-- 0--0
00-- 0--0
1Eh
ADRESH Most Significant 8 bits of the Left Shifted A/D result or 2 bits of the Right Shifted Result
xxxx xxxx
uuuu uuuu
1Fh
ADCON0
00-- 0000
00-- 0000
85h
TRISIO
--11 1111
--11 1111
8Ch
PIE1
9Eh
ADRESL
ADFM
VCFG
—
—
CHS1
—
—
TRISIO5
TRISIO4
TRISIO3
EEIE
ADIE
—
—
CMIE
CHS0
GO
ADON
TRISIO2 TRISIO1 TRISIO0
—
—
TMR1IE
Least Significant 2 bits of the Left Shifted A/D Result or 8 bits of the Right Shifted Result
00-- 0--0
00-- 0--0
xxxx xxxx
uuuu uuuu
-000 1111
-000 1111
9Fh
ANSEL
Legend:
x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D converter module.
DS70091A-page 44
—
ADCS2
ADCS1
ADCS0
ANS3
Preliminary
ANS2
ANS1
ANS0
 2003 Microchip Technology Inc.
rfPIC12F675
8.0
DATA EEPROM MEMORY
The EEPROM data memory is readable and writable
during normal operation (full VDD range). This memory
is not directly mapped in the register file space.
Instead, it is indirectly addressed through the Special
Function Registers. There are four SFRs used to read
and write this memory:
The EEPROM data memory allows byte read and write.
A byte write automatically erases the location and
writes the new data (erase before write). The EEPROM
data memory is rated for high erase/write cycles. The
write time is controlled by an on-chip timer. The write
time will vary with voltage and temperature as well as
from chip to chip. Please refer to AC Specifications for
exact limits.
•
•
•
•
EECON1
EECON2 (not a physically implemented register)
EEDATA
EEADR
When the data memory is code protected, the CPU
may continue to read and write the data EEPROM
memory. The device programmer can no longer access
this memory.
EEDATA holds the 8-bit data for read/write, and
EEADR holds the address of the EEPROM location
being accessed. The rfPIC12F675 devices have 128
bytes of data EEPROM with an address range from 0h
to 7Fh.
Additional information on the Data EEPROM is
available in the PICmicro™ Mid-Range Reference
Manual (DS33023).
REGISTER 8-1:
EEDAT — EEPROM DATA REGISTER (ADDRESS: 9Ah)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EEDAT7
EEDAT6
EEDAT5
EEDAT4
EEDAT3
R/W-0
R/W-0
EEDAT2 EEDAT1
R/W-0
EEDAT0
bit 7
bit 7-0
bit 0
EEDATn: Byte value to write to or read from Data EEPROM
Legend:
REGISTER 8-2:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
EEADR — EEPROM ADDRESS REGISTER (ADDRESS: 9Bh)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
EADR6
EADR5
EADR4
EADR3
EADR2
EADR1
EADR0
bit 7
bit 0
bit 7
Unimplemented: Should be set to '0'
bit 6-0
EEADR: Specifies one of 128 locations for EEPROM Read/Write Operation
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
 2003 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS70091A-page 45
rfPIC12F675
8.1
EEADR
The EEADR register can address up to a maximum of
128 bytes of data EEPROM. Only seven of the eight
bits in the register (EEADR<6:0>) are required. The
MSb (bit 7) is ignored.
The upper bit should always be ‘0’ to remain upward
compatible with devices that have more data EEPROM
memory.
8.2
EECON1 AND EECON2
REGISTERS
EECON1 is the control register with four low order bits
physically implemented. The upper four bits are nonimplemented and read as '0's.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
REGISTER 8-3:
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal operation. In these situations, following RESET, the user can
check the WRERR bit, clear it, and rewrite the location.
The data and address will be cleared, therefore, the
EEDATA and EEADR registers will need to be reinitialized.
Interrupt flag bit EEIF in the PIR1 register is set when
write is complete. This bit must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the Data EEPROM write sequence.
EECON1 — EEPROM CONTROL REGISTER (ADDRESS: 9Ch)
U-0
U-0
U-0
U-0
R/W-x
R/W-0
R/S-0
R/S-0
—
—
—
—
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7-4
Unimplemented: Read as ‘0’
bit 3
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
normal operation or BOD detect)
0 = The write operation completed
bit 2
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
bit 1
WR: Write Control bit
1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit
can only be set, not cleared, in software.)
0 = Write cycle to the data EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit
can only be set, not cleared, in software.)
0 = Does not initiate an EEPROM read
Legend:
S = Bit can only be set
DS70091A-page 46
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
 2003 Microchip Technology Inc.
rfPIC12F675
8.3
READING THE EEPROM DATA
MEMORY
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
To read a data memory location, the user must write
the address to the EEADR register and then set
control bit RD (EECON1<0>), as shown in
Example 8-1. The data is available, in the very next
cycle, in the EEDATA register. Therefore, it can be
read in the next instruction. EEDATA holds this value
until another read, or until it is written to by the user
(during a write operation).
EXAMPLE 8-1:
bsf
movlw
movwf
bsf
movf
8.4
8.5
;Bank 1
;
;Address to read
;EE Read
;Move data to W
EXAMPLE 8-3:
WRITING TO THE EEPROM DATA
MEMORY
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then the user must follow a
specific sequence to initiate the write for each byte, as
shown in Example 8-2.
EXAMPLE 8-2:
Required
Sequence
WRITE VERIFY
bcf
:
bsf
movf
STATUS,RP0
bsf
EECON1,RD
STATUS,RP0
EEDATA,W
xorwf EEDATA,W
btfss STATUS,Z
goto
WRITE_ERR
:
;Bank 0
;Any code
;Bank 1 READ
;EEDATA not changed
;from previous write
;YES, Read the
;value written
;Is data the same
;No, handle error
;Yes, continue
DATA EEPROM WRITE
8.5.1
bsf
bsf
bcf
movlw
movwf
movlw
movwf
bsf
bsf
WRITE VERIFY
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM should be verified (see Example 8-3) to the
desired value to be written.
DATA EEPROM READ
STATUS,RP0
CONFIG_ADDR
EEADR
EECON1,RD
EEDATA,W
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit
(PIR<7>) register must be cleared by software.
STATUS,RP0
EECON1,WREN
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
INTCON,GIE
;Bank 1
;Enable write
;Disable INTs
;Unlock write
;
;
;
;Start the write
;Enable INTS
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
prevent the data from being written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware.
 2003 Microchip Technology Inc.
USING THE DATA EEPROM
The data EEPROM is a high-endurance, byte addressable array that has been optimized for the storage of
frequently changing information (e.g., program
variables or other data that are updated often).
Frequently changing values will typically be updated
more often than specifications D120 or D120A. If this is
not the case, an array refresh must be performed. For
this reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
FLASH program memory.
8.6
PROTECTION AGAINST
SPURIOUS WRITE
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been built in. On power-up, WREN is cleared. Also, the
Power-up Timer (72 ms duration) prevents
EEPROM write.
The write initiate sequence and the WREN bit together
help prevent an accidental write during:
• brown-out
• power glitch
• software malfunction
Preliminary
DS70091A-page 47
rfPIC12F675
8.7
DATA EEPROM OPERATION
DURING CODE PROTECT
Data memory can be code protected by programming
the CPD bit to ‘0’.
When the data memory is code protected, the CPU is
able to read and write data to the Data EEPROM. It is
recommended to code protect the program memory
when code protecting data memory. This prevents
anyone from programming zeroes over the existing
code (which will execute as NOPs) to reach an added
routine, programmed in unused program memory,
which outputs the contents of data memory.
Programming unused locations to ‘0’ will also help
prevent data memory code protection from becoming
breached.
TABLE 8-1:
Address
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
EEIF
ADIF
—
—
CMIF
—
—
0Ch
PIR1
9Ah
EEDATA
9Bh
EEADR
—
9Ch
EECON1
—
9Dh
EECON2(1) EEPROM Control Register 2
Bit 0
0000 0000 0000 0000
EEPROM Address Register
—
Value on all
other
RESETS
TMR1IF 00-- 0--0 00-- 0--0
EEPROM Data Register
—
Value on
POR, BOD
—
-000 0000 -000 0000
WRERR WREN
WR
RD
---- x000 ---- q000
---- ---- ---- ----
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition.
Shaded cells are not used by Data EEPROM module.
Note 1: EECON2 is not a physical register.
DS70091A-page 48
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
9.0
UHF ASK/FSK TRANSMITTER
9.1
Transmitter Operation
FIGURE 9-1:
The transmitter is a fully integrated UHF ASK/FSK
transmitter consisting of crystal oscillator, PhaseLocked Loop (PLL), Power Amplifier (PA) with opencollector output, and mode control logic. There are 3
variations of this device to optimize its performance for
the most commonly used frequency bands.
TABLE 9-1:
TRANSMITTER BLOCK
DIAGRAM
Clock
Divider
REFCLK
Crystal
Oscillator
RFXTAL
FREQUENCY BANDS
Device
Frequency
Modulation
rfPIC12F675K
290-350 MHz
ASK/FSK
rfPIC12F675F
390-450 MHz
ASK/FSK
rfPIC12F675H
850-930 MHz
ASK/FSK
Phase/Freq
Detector
Divide
by 32
LF
The internal structure of the transmitter is shown in
Figure 9-1. A Colpitts oscillator generates the
reference frequency set by the attached crystal. The
voltage controlled oscillator (VCO) converts the voltage
on the LF pin to a frequency. This frequency is divided
by 32 and compared to the crystal reference. If the
frequency or phase does not match the reference, the
charge pump corrects the voltage on the LF pin. The
VCO output signal is also amplified by the PA, whose
single ended output drives the user’s antenna.
The external components required are a crystal to set
the transmit frequency, a supply bypass capacitor, and
two to seven biasing/impedance matching components
to get maximum power to the antenna. The two control
signals from the microcontroller are connected externally for maximum design flexibility. The rfPIC12F675
is capable of transmitting data by Amplitude Shift
Keying (ASK) or Frequency Shift Keying (FSK).
The rfPIC12F675 is a radio frequency (RF) emitting
device. Wireless RF devices are governed by a
country’s regulating agency. For example, in the United
States it is the Federal Communications Committee
(FCC) and in Europe it is the European Conference of
Postal and Telecommunications Administrations
(CEPT). It is the responsibility of the designer to ensure
that their end product conforms to rules and regulations
of the country of use and/or sale.
RF devices require correct board level implementation in order to meet regulatory requirements. Layout
considerations are listed at the end of each subsection. It is required to place a ground plane on the PCB
to reduce unwanted radio frequency emissions.
 2003 Microchip Technology Inc.
Charge
Pump
Voltage
Controlled
Oscillator
PS
DATAASK
RFEN
RF Power
Amplifier
RF
Control
Logic
ANT
VDDRF
VSSRF
VSSRF
DATAFSK
FSK Switch
9.2
FSKOUT
Supply Voltage (VDDRF, VSSRF)
Pins VDDRF and VSSRF supply power and ground
respectively to the transmitter. These power pins are
separate from power supply pins VDD and VSS to the
microcontroller. Both VSSRF pins should be tied to the
ground plane with the shortest possible traces. The
microcontroller ground should be tied to the same RF
ground potential. However, the VDDRF supply can be at
a different potential than the microcontroller as long as
the RFEN and DATA input levels are within specification limits.
Layout Considerations - Provide low impedance
power and ground traces to minimize spurious
emissions. A two-sided PCB with a ground plane on
the bottom layer is highly recommended. Separate
bypass capacitors should be connected as close as
possible to each of the supply pins VDD and VDDRF.
Connect both VSSRF pins to the ground plane using
multiple PCB vias adjacent to the VSSRF pads. Do not
share these PCB vias with other ground traces. Filter
the VDDRF with an RC filter if the microcontroller noise
spurs exceed regulatory limits.
Preliminary
DS70091A-page 49
rfPIC12F675
9.3
9.4
Crystal Oscillator
The transmitter crystal oscillator is a Colpitts oscillator
that provides the reference frequency to the PLL. It is
independent of the microcontroller oscillator. An
external crystal or AC coupled reference signal is
connected to the XTAL pin. The transmit frequency is
fixed and determined by the crystal frequency
according to the formula:
f transmit = f
× 32
RFXTAL
Due to the flexible selection of transmit frequency, the
resulting crystal frequency may not be a standard offthe-shelf value. Therefore, for some carrier frequencies
the designer will have to consult a crystal manufacturer
and have a custom crystal manufactured. For
background information on crystal selection see
Application Note AN588, PICmicro® Microcontroller
Oscillator Design Guide, and AN826 Crystal Oscillator
Basics and Crystal Selection for rfPIC™ and
PICmicro® Devices.
ASK Modulation
In ASK modulation the data is transmitted by varying
the output power. The DATAASK pin enables the PA,
toggling the pin turns the RF output signal on and off. A
simple receiver using a tuned filter and peak detector
diode can capture the data. A more advanced superheterodyne receiver such as the rfRXD0420 can
greatly increase the range and reduce susceptibility to
interference.
In ASK mode the DATAFSK and FSKOUT pins are not
used and should both be tied to ground. An example of
a typical ASK circuit is shown in Figure 9-5. The C1
capacitor can be replaced by a short to simplify the
transmitter if the receiver has a wide enough
bandwidth. For a very narrowband receiver the C1
capacitor may need to be replaced by a trimmer cap to
tune the transmitter to the exact frequency.
FIGURE 9-2:
For ASK modulation the crystal can be connected
directly from RFXTAL to ground, or in series with an
additional capacitor to trim the frequency. Figure 9-2
shows how the crystal is connected and Table 9-2
shows how the frequency of a typical crystal changes
with capacitance.
XTAL
X1
The oscillator is enabled when the RFEN input is high.
It takes the crystal approximately 1 ms to start oscillating. Higher frequency crystals start-up faster than
lower frequencies. The crystal oscillator start time
(TON) is listed in Table 13-11, Transmitter AC
Characteristics. This start-up time is mainly due to the
crystal building up an oscillation, but also includes the
time for the PLL to lock on the crystal frequency.
TABLE 9-2:
ASK CRYSTAL CIRCUIT
rfPIC12F675K/F/H
C1
XTAL OSC APPROXIMATE FREQ. VS. CAPACITANCE (ASK MODE) (1)
Predicted Frequency
(MHz)
PPM from 13.55 MHz
Transmit Frequency (MHz)
(32 * fXTAL)
22 pF
13.551438
+106
433.646
39 pF
13.550563
+42
433.618
C1
100 pF
13.549844
-12
433.595
150 pF
13.549672
-24
433.5895
470 pF
13.549548
-33
433.5856
1000 pF
13.549344
-48
433.579
Note 1: Standard Operating Conditions (unless otherwise stated) TA = 25°C, RFEN = 1, VDDRF = 3V,
fXTAL = 13.55 MHz
DS70091A-page 50
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
9.5
FSK Modulation
In FSK modulation the transmit data is sent by varying
the output frequency. This is done by loading the
reference crystal with extra capacitance to pull it to a
slightly lower frequency which the PLL then tracks.
Switching the capacitance in and out with the data
signal toggles the transmitter between two frequencies.
These two crystal based frequencies are then
multiplied by 32 for the RF transmit frequency.
In FSK mode the DATAASK pin should be tied high to
enable the PA. The FSK circuit is shown in Figure 9-6.
Use accurate crystals for narrow bandwidth systems
and large values for C1 to reduce frequency drift.
FIGURE 9-3:
FSK CRYSTAL CIRCUIT
XTAL
Unlike the ASK transmit frequency the FSK center
frequency is not actually transmitted. It is the artificial
point half way between the two transmitted
frequencies, calculated with this formula.
fc =
X1
C2
f max + f min
2
FSKOUT
C1
The other important parameter in FSK is the frequency
deviation of the transmit frequency. This measures how
far the frequency will swing from the center frequency.
Single ended deviation is calculated with this formula.
∆f =
f max − f min
2
FIGURE 9-4:
An FSK receiver will specify its optimal value of
deviation. The single ended deviation must be greater
than data rate/4. The minimum deviation is usually
limited by the frequency accuracy of the transmitter and
receiver components. The maximum deviation is usually
limited by the pulling characteristics of the transmitter
crystal.
FREQUENCY PULLING
Fmax
Frequency
(MHz)
An extra capacitor and the internal switch are added to
the ASK design to build an FSK transmitter as shown
in Figure 9-3. The C1 capacitor in series with the crystal
determines the maximum frequency.
Fmin
With the DATAFSK pin high the FSKOUT pin is open and
the C2 capacitor does not affect the frequency. When
the DATAFSK pin goes low, FSKOUT shorts to ground,
and the C2 is thrown in parallel with C1. The sum of the
two caps pulls the oscillation frequency lower as shown
in Figure 9-4.
TABLE 9-3:
rfPIC12F675K/F/H
C1
C1||C2
DATAFSK = 1 DATAFSK = 0
Load Capacitance (pF)
TYPICAL TRANSMIT CENTER FREQUENCY AND DEVIATION (FSK MODE) (1)
C2 = 1000 pF
C2 = 100 pF
C2 = 47 pF
C1 (pF)
Freq (MHz) / Dev (kHz)
Freq (MHz) / Dev (kHz)
Freq (MHz) / Dev (kHz)
22
433.612 / 34
433.619 / 27
433.625 / 21
33
433.604 / 25
433.610 / 19
433.614 / 14
39
433.598 / 20
433.604 / 14
433.608 / 10
47
433.596 / 17
433.601 / 11.5
433.604 / 8
68
433.593 / 13
433.598 / 9
433.600 / 5.5
100
433.587 / 8
—
—
Note 1: Standard Operating Conditions, TA = 25°C, RFEN = 1, VDDRF = 3V, fXTAL = 13.55 MHz
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 51
rfPIC12F675
FIGURE 9-5:
TYPICAL ASK TRANSMITTER SCHEMATIC
+V
C3
0.1 µF
X1
C1
R1
C4
100 pF
1
2
3
4
5
6
7
8
9
10
20
VDD
VSS
19
GP5/T1CKI/OSC1/CLKIN
GP0/AN0/CIN+/ICSPDAT
18
GP4/AN3/T1G/OSC2/CLKOUT
GP1/AN1/CIN-/VREF/ICSPCLK
17
GP3/MCLR/VPP
GP2/AN2/T0CKI/INT/COUT
16
RFXTAL
FSKOUT
15
DATAFSK
RFENIN
14
DATAASK
CLKOUT
13
LF
PS
12
U1
VSSRF
VDDRF
11
rfPIC12F675K
VSSRF
ANT
SW2
SW1
C1 can be shorted
R1 can be omitted
+V
L1
120 nH
R2
4.7 kΩ
C5
100 pF
+V
C6
5 pF
+
-
BT1
CR2032
3V Lithium Cell
Loop Antenna
C7
4 pF
FIGURE 9-6:
TYPICAL FSK TRANSMITTER SCHEMATIC
+V
C3
0.1 µF
X1
13.55 MHz
C1
39 pF
R1
220 kΩ
C4
100 pF
1
2
3
4
5
6
7
8
9
10
VDD
VSS
GP0/AN0/CIN+/ICSPDAT
GP5/T1CKI/OSC1/CLKIN
GP1/AN1/CIN-/VREF/ICSPCLK
GP4/AN3/T1G/OSC2/CLKOUT
GP3/MCLR/VPP
GP2/AN2/T0CKI/INT/COUT
RFXTAL
FSKOUT
DATAFSK
RFENIN
DATAASK
CLKOUT
PS
LF
U1
VSSRF
VDDRF
rfPIC12F675K
VSSRF
ANT
20
19
18
17
16
15
14
13
12
11
+V
SW2
SW1
C2
1000 pF
+V
C5
100 pF
L1
120 nH
R2
4.7 kΩ
+V
C6
5 pF
+
-
BT1
CR2032
3V Lithium Cell
Loop Antenna
C7
4 pF
DS70091A-page 52
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
9.6
Clock Output
9.8
The clock output is available to the microcontroller or
other circuits requiring an accurate reference
frequency. This signal would typically be used to
correct the internal RC oscillator for system designs
that require accurate bit synchronization or tight time
division multiplexing. The REFCLK output can
connect directly to the T0CKI or T1CKI.
The PLL output feeds the power amplifier (PA) which
drives the open-collector ANT output. The output
should be DC biased with an inductor to the VDDRF
supply. The output impedance must be matched to the
load impedance to deliver the maximum power. This is
typically done with a transformer or tapped capacitor
circuit. Failure to match the impedance may cause
excessive spurious and harmonic emissions. For more
information on transformer matching see Application
Note AN831, Matching Small Loop Antennas to rfPIC™
Devices. For more information on tapped capacitor
matching see Application Note AN242 Designing an
FCC Approved ASK rfPIC™ Transmitter.
The REFCLK output frequency is the crystal oscillator
divided by 4 on the rfPIC12F675K and rfPIC12F675F.
For the rfPIC12F675H the crystal oscillator is divided
by 8.
Layout considerations - Keep the clock trace short
and narrow yet as far as possible from other traces to
reduce capacitance and the associated current draw.
If the REFCLK trace must pass near the crystal and
LF nodes then shield them with ground traces.
9.7
Power Amplifier
The transmit output power can be adjusted in five
discrete steps from +9 dBm to -70 dBm by varying the
voltage on the PS pin. Since the PS pin has an internal
8 µA source the voltage can be set with a resistor from
the PS pin to ground as shown in Figure 9-7. Some
possible resistor values to set the current are shown in
Table 9-4.
Phase-Locked Loop Filter
The LF pin connects to an internal node on the PLL
filter. Typically the pin should not be connected. In
specialized cases it may be necessary to load this pin
with extra capacitance to ground. Adding capacitance
reduces the loop filter bandwidth which trades off an
increase in phase noise for a reduction in clock spurs.
It is usually desirable to select the lowest power level
step that does not compromise communications reliablity. The most important benefit is the conservation of
battery power. Another reason is to make it easier to
pass regulatory limits. And a third reason is to reduce
interference to other communications in the shared RF
spectrum. Small inefficient antennas will require higher
power level settings than larger efficient antennas.
Useful diagnostic measurements can be taken on the
LF pin with a high impedance, low capacitance probe.
Measuring the time from RFEN going high until the LF
voltage stabilizes will determine the minimum delay
before the start of a transmission. For more information
on PLL filters refer to Application Note AN846 Basic
PLL Filters for the rfPIC™/rfHCS.
FIGURE 9-7:
.POWER SELECT CIRCUIT
rfPIC12F675
VPS
IPS = 8 µA
Layout considerations - Keep traces short and if the
optional loop filter capacitor is required, place it as
close as possible to the LF pin with its own via to the
ground plane.
PS
To power
select
circuitry
R1
TABLE 9-4:
POWER SELECT RESISTOR SELECTION (1,2)
Power Step
Output Power
(dBm)
PS Voltage
(Volts)
R1 Resistance
(Ω)
RF Transmitter
Current (mA)
4
9
1.6
open
10.7
(3)
3
2
0.8
2
-4
0.4
47k
(3)
4.7
1
-12
0.2
3.5
0
-70
0.1
22k (3)
short
100k
6.5
2.7
Note 1: Standard Operating Conditions, TA = 25°C, RFEN = 1, VDDRF = 3V, fTRANSMIT = 433.92 MHz
2: Typical values, for complete specifications see data sheet Section 13.0.
3: R1 resistor variations plus IPS current supply variations must not exceed VPS step limits.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 53
rfPIC12F675
9.9
Digital Control Signals
The mode control logic pin RFEN controls the
operation of the transmitter. When RFEN goes high,
the crystal oscillator starts up. The voltage on the LF
pin ramps up proportionally to the RF frequency. The
PLL can lock onto the frequency faster than the starting up crystal can stabilize. When the LF pin reaches
0.8V, the RF frequency is close to locked on the crystal frequency. This initiates a 150 microsecond delay
to ensure that the PLL settles. After the delay, the PS
bias current and power amplifier are enabled to start
transmitting when DATAASK goes high.
When RFEN is low, the transmitter goes into a very
low power Standby mode. The power amplifier is
disabled and the crystal oscillator stops. The RFEN
pin has an internal pull-down resistor.
9.10
Low Voltage Output Disable
The rfPIC12F675 transmitter has a built in low voltage
disable centered at about 1.85V. If the supply voltage
drops below this voltage the power amplifier is
disabled to prevent uncontrolled transmissions.
DS70091A-page 54
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
10.0
SPECIAL FEATURES OF THE
CPU
Certain special circuits that deal with the needs of real
time applications are what sets a microcontroller apart
from other processors. The rfPIC12F675 Family has a
host of such features intended to:
• maximize system reliability
• minimize cost through elimination of external
components
• provide power saving operating modes and offer
code protection.
These features are:
• Oscillator selection
• RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Detect (BOD)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code protection
• ID Locations
• In-Circuit Serial Programming
 2003 Microchip Technology Inc.
The rfPIC12F675 has a Watchdog Timer that is
controlled by configuration bits. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), intended to keep the
chip in RESET until the crystal oscillator is stable. The
other is the Power-up Timer (PWRT), which provides a
fixed delay of 72 ms (nominal) on power-up only,
designed to keep the part in RESET while the power
supply stabilizes. There is also circuitry to reset the
device if a brown-out occurs, which can provide at least
a 72 ms RESET. With these three functions on-chip,
most applications need no external RESET circuitry.
The SLEEP mode is designed to offer a very low
current Power-down mode. The user can wake-up from
SLEEP through:
• External RESET
• Watchdog Timer wake-up
• An interrupt
Several oscillator options are also made available to
allow the part to fit the application. The INTOSC option
saves system cost while the LP crystal option saves
power. A set of configuration bits are used to select
various options (see Register 10-1).
Preliminary
DS70091A-page 55
rfPIC12F675
10.1
Configuration Bits
Note:
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1') to select various
device configurations, as shown in Register 10-1.
These bits are mapped in program memory location
2007h.
REGISTER 10-1:
R/P-1 R/P-1
BG1
bit 13
bit 13-12
bit 11-9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
CONFIG — CONFIGURATION WORD (ADDRESS: 2007h)
U-0
U-0
U-0
R/P-1
R/P-1
—
—
—
CPD
CP
BG0
Address 2007h is beyond the user program
memory space. It belongs to the special
configuration memory space (2000h 3FFFh), which can be accessed only during
programming. See rfPIC12F675 Programming Specification for more information.
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
R/P-1
BODEN MCLRE PWRTE WDTE F0SC2 F0SC1 F0SC0
bit 0
BG1:BG0: Bandgap Calibration bits for BOD and POR voltage(1)
00 = Lowest bandgap voltage
11 = Highest bandgap voltage
Unimplemented: Read as ‘0’
CPD: Data Code Protection bit(2)
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
CP: Code Protection bit(3)
1 = Program Memory code protection is disabled
0 = Program Memory code protection is enabled
BODEN: Brown-out Detect Enable bit(4)
1 = BOD enabled
0 = BOD disabled
MCLRE: GP3/MCLR pin function select(5)
1 = GP3/MCLR pin function is MCLR
0 = GP3/MCLR pin function is digital I/O, MCLR internally tied to VDD
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
FOSC2:FOSC0: Oscillator Selection bits
111 = RC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN
110 = RC oscillator: I/O function on GP4/OSC2/CLKOUT pin, RC on GP5/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN
100 = INTOSC oscillator: I/O function on GP4/OSC2/CLKOUT pin, I/O function on GP5/OSC1/CLKIN
011 = EC: I/O function on GP4/OSC2/CLKOUT pin, CLKIN on GP5/OSC1/CLKIN
010 = HS oscillator: High speed crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
001 = XT oscillator: Crystal/resonator on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
000 = LP oscillator: Low power crystal on GP4/OSC2/CLKOUT and GP5/OSC1/CLKIN
Note 1: The Bandgap Calibration bits are factory programmed and must be read and saved prior to erasing
the device as specified in the rfPIC12F675 Programming Specification. These bits are reflected in
an export of the configuration word. Microchip Development Tools maintain all calibration bits to
factory settings.
2: The entire data EEPROM will be erased when the code protection is turned off.
3: The entire program memory will be erased, including OSCCAL value, when the code protection is
turned off.
4: Enabling Brown-out Detect does not automatically enable Power-up Timer.
5: When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
Legend:
P = Programmed using ICSP
R = Readable bit
-n = Value at POR
DS70091A-page 56
W = Writable bit
1 = bit is set
Preliminary
U = Unimplemented bit, read as ‘0’
0 = bit is cleared
x = bit is unknown
 2003 Microchip Technology Inc.
rfPIC12F675
10.2
Oscillator Configurations
10.2.1
FIGURE 10-2:
OSCILLATOR TYPES
The rfPIC12F675 can be operated in eight different
Oscillator Option modes. The user can program three
configuration bits (FOSC2 through FOSC0) to select
one of these eight modes:
•
•
•
•
•
•
Note:
TABLE 10-1:
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (see Figure 10-1). The rfPIC12F675
oscillator design requires the use of a parallel cut
crystal. Use of a series cut crystal may yield a
frequency outside of the crystal manufacturers
specifications. When in XT, LP or HS modes, the
device can have an external clock source to drive the
OSC1 pin (see Figure 10-2).
CRYSTAL OPERATION (OR
CERAMIC RESONATOR)
HS, XT OR LP OSC
CONFIGURATION
To Internal
Logic
XTAL
(3)
RF
Mode
Freq
OSC1(C1)
OSC2(C2)
XT
455 kHz
2.0 MHz
4.0 MHz
68 - 100 pF
15 - 68 pF
15 - 68 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time. These values are for design
guidance only. Since each resonator has
its own characteristics, the user should
consult the resonator manufacturer for
appropriate values of external
components.
TABLE 10-2:
Freq
OSC1(C1)
OSC2(C2)
LP
32 kHz
68 - 100 pF
68 - 100 pF
XT
100 kHz
2 MHz
4 MHz
68 - 150 pF
15 - 30 pF
15 - 30 pF
150 - 200 pF
15 - 30 pF
15 - 30 pF
HS
8 MHz
10 MHz
20 MHz
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
SLEEP
1:
2:
3:
RS(2)
PIC12F629/675
See Table 10-1 and Table 10-2 for recommended
values of C1 and C2.
A series resistor may be required for AT strip cut
crystals.
RF varies with the Oscillator mode selected
(Approx. value = 10 MΩ).
 2003 Microchip Technology Inc.
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Mode
OSC2
C2(1)
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
Ranges Characterized:
OSC1
C1(1)
OSC2(1)
Note 1: Functions as GP4 in EC Osc mode.
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
FIGURE 10-1:
OSC1
Open
Additional information on oscillator configurations is available in the PICmicroTM
Mid-Range
Reference
Manual,
(DS33023)
10.2.2
Clock from
External System
PIC12F629/675
LP
Low Power Crystal
XT
Crystal/Resonator
HS
High Speed Crystal/Resonator
RC
External Resistor/Capacitor (2 modes)
INTOSC Internal Oscillator (2 modes)
EC
External Clock In
Note
EXTERNAL CLOCK INPUT
OPERATION (HS, XT, EC,
OR LP OSC
CONFIGURATION)
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time. These values are for design
guidance only. Rs may be required in HS
mode as well as XT mode to avoid
overdriving crystals with low drive level
specification. Since each crystal has its
own characteristics, the user should
consult the crystal manufacturer for
appropriate values of external
components.
Preliminary
DS70091A-page 57
rfPIC12F675
10.2.3
10.2.5
EXTERNAL CLOCK IN
For applications where a clock is already available
elsewhere, users may directly drive the rfPIC12F675
provided that this external clock source meets the AC/
DC timing requirements listed in Section 13.0.
Figure 10-2 shows how an external clock circuit
should be configured.
Note:
10.2.4
The microcontroller oscillator is independent of the RF peripheral oscillator. An
accurate time-base is still possible with
only one crystal. Use the RF crystal on
transmitter and tie the REFCLK signal
back into T0CKI or T1CKI to correct the
RC, INTOSC, or EC clocks. Since REFCLK is only active when RFEN=1, it is not
a suitable source for CLKIN.
RC OSCILLATOR
For applications where precise timing is not a requirement, the RC oscillator option is available. The
operation and functionality of the RC oscillator is
dependent upon a number of variables. The RC
oscillator frequency is a function of:
INTERNAL 4 MHZ OSCILLATOR
When calibrated, the internal oscillator provides a fixed
4 MHz (nominal) system clock. See Electrical
Specifications, Section 13.0, for information on
variation over voltage and temperature.
Two options are available for this Oscillator mode
which allow GP4 to be used as a general purpose I/O
or to output FOSC/4.
10.2.5.1
Calibrating the Internal Oscillator
A calibration instruction is programmed into the last
location of program memory. This instruction is a
RETLW XX, where the literal is the calibration value.
The literal is placed in the OSCCAL register to set the
calibration of the internal oscillator. Example 10-1
demonstrates how to calibrate the internal oscillator.
For best operation, decouple (with capacitance) VDD
and VSS as close to the device as possible.
Note:
• Supply voltage
• Resistor (REXT) and capacitor (CEXT) values
• Operating temperature
Erasing the device will also erase the preprogrammed internal calibration value for
the internal oscillator. The calibration value
must be saved prior to erasing part as
specified in the rfPIC12F675 Programming
specification. Microchip Development
Tools maintain all calibration bits to factory
settings.
The oscillator frequency will vary from unit to unit due
to normal process parameter variation. The difference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
CEXT values. The user also needs to account for the
tolerance of the external R and C components.
Figure 10-3 shows how the R/C combination is
connected.
EXAMPLE 10-1:
Two options are available for this Oscillator mode
which allow GP4 to be used as a general purpose I/O
or to output FOSC/4.
10.2.6
FIGURE 10-3:
RC OSCILLATOR MODE
VDD
bsf
call
movwf
bcf
CALIBRATING THE
INTERNAL OSCILLATOR
STATUS, RP0
3FFh
OSCCAL
STATUS, RP0
;Bank 1
;Get the cal value
;Calibrate
;Bank 0
CLKOUT
The rfPIC12F675 devices can be configured to provide
a clock out signal in the INTOSC and RC oscillator
modes. When configured, the oscillator frequency
divided by four (FOSC/4) is output on the GP4/OSC2/
CLKOUT pin. FOSC/4 can be used for test purposes or
to synchronize other logic.
PIC12F629/675
REXT
GP5/OSC1/
CLKIN
Internal
Clock
CEXT
VSS
FOSC/4
GP4/OSC2/CLKOUT
DS70091A-page 58
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
10.3
RESET
The rfPIC12F675 differentiates between various kinds
of RESET:
a)
b)
c)
d)
e)
f)
Power-on Reset (POR)
WDT Reset during normal operation
WDT Reset during SLEEP
MCLR Reset during normal operation
MCLR Reset during SLEEP
Brown-out Detect (BOD)
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 10-4.
Some registers are not affected in any RESET
condition; their status is unknown on POR and
unchanged in any other RESET. Most other registers
are reset to a “RESET state” on:
•
•
•
•
•
They are not affected by a WDT wake-up, since this is
viewed as the resumption of normal operation. TO and
PD bits are set or cleared differently in different RESET
situations as indicated in Table 10-4. These bits are
used in software to determine the nature of the RESET.
See Table 10-7 for a full description of RESET states of
all registers.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table 13-4 in Electrical
Specifications Section for pulse width specification.
Power-on Reset
MCLR Reset
WDT Reset
WDT Reset during SLEEP
Brown-out Detect (BOD) Reset
FIGURE 10-4:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/
VPP pin
WDT
WDT
Module
SLEEP
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Detect
BODEN
S
Q
R
Q
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter
OSC1/
CLKIN
pin
PWRT
On-chip(1)
RC OSC
10-bit Ripple Counter
Enable PWRT
See Table 10-3 for time-out situations.
Enable OST
Note
1:
This is a separate oscillator from the INTOSC/EC oscillator.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 59
rfPIC12F675
10.3.1
10.3.3
MCLR
The rfPIC12F675 devices have a noise filter in the
MCLR Reset path. The filter will detect and ignore
small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from previous devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR Resets and excessive current
beyond the device specification during the ESD event.
For this reason, Microchip recommends that the MCLR
pin no longer be tied directly to VDD. The use of an RC
network, as shown in Figure 10-5, is suggested.
An internal MCLR option is enabled by setting the
MCLRE bit in the configuration word. When enabled,
MCLR is internally tied to VDD. No internal pull-up
option is available for the MCLR pin.
The Power-up Timer provides a fixed 72 ms (nominal)
time-out on power-up only, from POR or Brown-out
Detect. The Power-up Timer operates on an internal
RC oscillator. The chip is kept in RESET as long as
PWRT is active. The PWRT delay allows the VDD to
rise to an acceptable level. A configuration bit, PWRTE
can disable (if set) or enable (if cleared or
programmed) the Power-up Timer. The Power-up
Timer should always be enabled when Brown-out
Detect is enabled.
The Power-up Time delay will vary from chip to chip
and due to:
• VDD variation
• Temperature variation
• Process variation
See DC parameters for details (Section 13.0).
10.3.4
FIGURE 10-5:
RECOMMENDED MCLR
CIRCUIT
VDD
POWER-UP TIMER (PWRT)
OSCILLATOR START-UP TIMER
(OST)
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
PIC12F629/675
R1
1 kΩ (or greater)
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
MCLR
C1
0.1 µf
(optional, not critical)
10.3.2
POWER-ON RESET (POR)
The on-chip POR circuit holds the chip in RESET until
VDD has reached a high enough level for proper
operation. To take advantage of the POR, simply tie the
MCLR pin through a resistor to VDD. This will eliminate
external RC components usually needed to create
Power-on Reset. A maximum rise time for VDD is
required. See Electrical Specifications for details (see
Section 13.0).
Note:
The POR circuit does not produce an
internal RESET when VDD declines.
When the device starts normal operation (exits the
RESET condition), device operating parameters (i.e.,
voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating
conditions are met.
For additional information, refer to Application Note
AN607 “Power-up Trouble Shooting”.
DS70091A-page 60
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
10.3.5
BROWN-OUT DETECT (BOD)
On any RESET (Power-on, Brown-out, Watchdog,
etc.), the chip will remain in RESET until VDD rises
above BVDD (see Figure 10-6). The Power-up Timer
will now be invoked, if enabled, and will keep the chip
in RESET an additional 72 ms.
The rfPIC12F675 members have on-chip Brown-out
Detect circuitry. A configuration bit, BODEN, can
disable (if clear/programmed) or enable (if set) the
Brown-out Detect circuitry. If VDD falls below VBOD for
greater than parameter (TBOD) in Table 13-4 (see
Section 13.0), the Brown-out situation will reset the
device. This will occur regardless of VDD slew-rate. A
RESET is not guaranteed to occur if VDD falls below
VBOD for less than parameter (TBOD).
FIGURE 10-6:
Note:
A Brown-out Detect does not enable the
Power-up Timer if the PWRTE bit in the
configuration word is set.
If VDD drops below BVDD while the Power-up Timer is
running, the chip will go back into a Brown-out Detect
and the Power-up Timer will be re-initialized. Once VDD
rises above BVDD, the Power-up Timer will execute a
72 ms RESET.
BROWN-OUT SITUATIONS
VDD
VBOD
Internal
RESET
72 ms(1)
VDD
VBOD
Internal
RESET
<72 ms
72 ms(1)
VDD
VBOD
Internal
RESET
72 ms(1)
Note 1: 72 ms delay only if PWRTE bit is programmed to ‘0’.
10.3.6
10.3.7
TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired.
Then, OST is activated. The total time-out will vary
based on oscillator configuration and PWRTE bit
status. For example, in EC mode with PWRTE bit
erased (PWRT disabled), there will be no time-out at
all. Figure 10-7, Figure 10-8 and Figure 10-9 depict
time-out sequences.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 10-8). This is useful for testing purposes or
to synchronize more than one rfPIC12F675 device
operating in parallel.
Table 10-6 shows the RESET conditions for some
special registers, while Table 10-7 shows the RESET
conditions for all the registers.
 2003 Microchip Technology Inc.
POWER CONTROL (PCON) STATUS
REGISTER
The power CONTROL/STATUS
(address 8Eh) has two bits.
register,
PCON
Bit0 is BOD (Brown-out). BOD is unknown on Poweron Reset. It must then be set by the user and checked
on subsequent RESETS to see if BOD = 0, indicating
that a brown-out has occurred. The BOD STATUS bit is
a don’t care and is not necessarily predictable if the
brown-out circuit is disabled (by setting BODEN bit = 0
in the Configuration word).
Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent RESET, if POR is ‘0’, it will indicate that a
Power-on Reset must have occurred (i.e., VDD may
have gone too low).
Preliminary
DS70091A-page 61
rfPIC12F675
TABLE 10-3:
TIME-OUT IN VARIOUS SITUATIONS
Power-up
Brown-out Detect
Oscillator Configuration
Wake-up
from SLEEP
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
XT, HS, LP
TPWRT +
1024•TOSC
1024•TOSC
TPWRT +
1024•TOSC
1024•TOSC
1024•TOSC
RC, EC, INTOSC
TPWRT
—
TPWRT
—
—
TABLE 10-4:
STATUS/PCON BITS AND THEIR SIGNIFICANCE
POR
BOD
TO
PD
0
u
1
1
Power-on Reset
1
0
1
1
Brown-out Detect
u
u
0
u
WDT Reset
u
u
0
0
WDT Wake-up
u
u
u
u
MCLR Reset during normal operation
u
u
1
0
MCLR Reset during SLEEP
Legend: u = unchanged, x = unknown
TABLE 10-5:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Value on
POR, BOD
Value on all
other
RESETS(1)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
03h
STATUS
IRP
RP1
RPO
TO
PD
Z
DC
C
0001 1xxx 000q quuu
8Eh
PCON
—
—
—
—
—
—
POR
BOD
---- --0x ---- --uq
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect and Watchdog Timer Reset during
normal operation.
TABLE 10-6:
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- --0x
MCLR Reset during normal operation
000h
000u uuuu
---- --uu
MCLR Reset during SLEEP
000h
0001 0uuu
---- --uu
WDT Reset
000h
0000 uuuu
---- --uu
PC + 1
uuu0 0uuu
---- --uu
000h
0001 1uuu
---- --10
uuu1 0uuu
---- --uu
Condition
WDT Wake-up
Brown-out Detect
Interrupt Wake-up from SLEEP
PC +
1(1)
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and global enable bit GIE is set, the PC is loaded with the
interrupt vector (0004h) after execution of PC+1.
DS70091A-page 62
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
TABLE 10-7:
Register
W
INITIALIZATION CONDITION FOR REGISTERS
Address
—
Power-on
Reset
xxxx xxxx
—
• MCLR Reset during
normal operation
• MCLR Reset during SLEEP
• WDT Reset
• Brown-out Detect(1)
• Wake-up from SLEEP
through interrupt
• Wake-up from SLEEP
through WDT time-out
uuuu uuuu
uuuu uuuu
—
—
INDF
00h/80h
TMR0
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h/82h
0000 0000
0000 0000
PC + 1(3)
STATUS
03h/83h
0001 1xxx
000q quuu(4)
uuuq quuu(4)
FSR
04h/84h
xxxx xxxx
uuuu uuuu
uuuu uuuu
GPIO
05h
--xx xxxx
--uu uuuu
--uu uuuu
PCLATH
0Ah/8Ah
---0 0000
---0 0000
---u uuuu
INTCON
0Bh/8Bh
0000 0000
0000 000u
uuuu uuqq(2)
PIR1
0Ch
00-- 0--0
00-- 0--0
qq-- q--q(2,5)
T1CON
10h
-000 0000
-uuu uuuu
-uuu uuuu
CMCON
19h
-0-0 0000
-0-0 0000
-u-u uuuu
ADRESH
1Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
1Fh
00-- 0000
00-- 0000
uu-- uuuu
OPTION_REG
81h
1111 1111
1111 1111
uuuu uuuu
TRISIO
85h
--11 1111
--11 1111
--uu uuuu
PIE1
8Ch
00-- 0--0
00-- 0--0
uu-- u--u
PCON
8Eh
---- --0x
---- --uu(1,6)
---- --uu
OSCCAL
90h
1000 00--
1000 00--
uuuu uu--
WPU
95h
--11 -111
--11 -111
uuuu uuuu
IOC
96h
--00 0000
--00 0000
--uu uuuu
VRCON
99h
0-0- 0000
0-0- 0000
u-u- uuuu
EEDATA
9Ah
0000 0000
0000 0000
uuuu uuuu
EEADR
9Bh
-000 0000
-000 0000
-uuu uuuu
EECON1
9Ch
---- x000
---- q000
---- uuuu
EECON2
9Dh
---- ----
---- ----
---- ----
ADRESL
9Eh
xxxx xxxx
uuuu uuuu
uuuu uuuu
ANSEL
9Fh
-000 1111
-000 1111
-uuu uuuu
Legend:
Note 1:
2:
3:
u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.
If VDD goes too low, Power-on Reset will be activated and registers will be affected differently.
One or more bits in INTCON and/or PIR1 will be affected (to cause wake-up).
When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
4: See Table 10-6 for RESET value for specific condition.
5: If wake-up was due to data EEPROM write completing, Bit 7 = 1; A/D conversion completing, Bit 6 = 1;
Comparator input changing, bit 3 = 1; or Timer1 rolling over, bit 0 = 1. All other interrupts generating a
wake-up will cause these bits to = u.
6: If RESET was due to brown-out, then bit 0 = 0. All other RESETS will cause bit 0 = u.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 63
rfPIC12F675
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
FIGURE 10-7:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal RESET
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 10-8:
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal RESET
FIGURE 10-9:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
Internal POR
TPWRT
PWRT Time-out
TOST
OST Time-out
Internal RESET
DS70091A-page 64
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
10.4
Interrupts
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
The rfPIC12F675 has 7 sources of interrupt:
•
•
•
•
•
•
•
External Interrupt GP2/INT
TMR0 Overflow Interrupt
GPIO Change Interrupts
Comparator Interrupt
A/D Interrupt
TMR1 Overflow Interrupt
EEPROM Data Write Interrupt
Note 1: Individual interrupt flag bits are set,
regardless of the status of their
corresponding mask bit or the GIE bit.
The Interrupt Control register (INTCON) and Peripheral
Interrupt register (PIR) record individual interrupt
requests in flag bits. The INTCON register also has
individual and global interrupt enable bits.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts which were
ignored are still pending to be serviced
when the GIE bit is set again.
A global interrupt enable bit, GIE (INTCON<7>) enables
(if set) all unmasked interrupts, or disables (if cleared) all
interrupts. Individual interrupts can be disabled through
their corresponding enable bits in INTCON register and
PIE register. GIE is cleared on RESET.
The return from interrupt instruction, RETFIE, exits
interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the
INTCON register:
• INT pin interrupt
• GP port change interrupt
• TMR0 overflow interrupt
The peripheral interrupt flags are contained in the
special register PIR1. The corresponding interrupt
enable bit is contained in Special Register PIE1.
The following interrupt flags are contained in the PIR
register:
•
•
•
•
EEPROM data write interrupt
A/D interrupt
Comparator interrupt
Timer1 overflow interrupt
When an interrupt is serviced:
• The GIE is cleared to disable any further interrupt
• The return address is pushed onto the stack
• The PC is loaded with 0004h
Once in the Interrupt Service Routine, the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in
software before re-enabling interrupts to avoid GP2/
INT recursive interrupts.
For external interrupt events, such as the INT pin, or
GP port change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 10-11). The latency is the same for one or twocycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 65
rfPIC12F675
FIGURE 10-10:
INTERRUPT LOGIC
IOC-GP0
IOC0
IOC-GP1
IOC1
IOC-GP2
IOC2
IOC-GP3
IOC3
IOC-GP4
IOC4
IOC-GP5
IOC5
TMR1IF
TMR1IE
CMIF
CMIE
ADIF
ADIE
T0IF
T0IE
Wake-up (If in SLEEP mode)
INTF
INTE
GPIF
GPIE
Interrupt to CPU
PEIE
GIE
EEIF
EEIE
DS70091A-page 66
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
10.4.1
GP2/INT INTERRUPT
10.4.3
External interrupt on GP2/INT pin is edge-triggered;
either rising if INTEDG bit (OPTION<6>) is set, of
falling, if INTEDG bit is clear. When a valid edge
appears on the GP2/INT pin, the INTF bit
(INTCON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The GP2/INT
interrupt can wake-up the processor from SLEEP if the
INTE bit was set prior to going into SLEEP. The status
of the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up. See
Section 10.9 for details on SLEEP and Figure 10-13 for
timing of wake-up from SLEEP through GP2/INT
interrupt.
Note:
10.4.2
GPIO INTERRUPT
An input change on GPIO change sets the GPIF
(INTCON<0>) bit. The interrupt can be enabled/
disabled by setting/clearing the GPIE (INTCON<3>)
bit. Plus individual pins can be configured through the
IOC register.
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the GPIF interrupt flag may not get set.
10.4.4
COMPARATOR INTERRUPT
See Section 6.9 for description of comparator interrupt.
10.4.5
A/D CONVERTER INTERRUPT
After a conversion is complete, the ADIF flag (PIR<6>)
is set. The interrupt can be enabled/disabled by setting
or clearing ADIE (PIE<6>).
The ANSEL (9Fh) and CMCON (19h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
See Section 7.0 for operation of the A/D converter
interrupt.
TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will
set the T0IF (INTCON<2>) bit. The interrupt can
be enabled/disabled by setting/clearing T0IE
(INTCON<5>) bit. For operation of the Timer0 module,
see Section 4.0.
FIGURE 10-11:
INT PIN INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT 3
4
INT pin
1
1
INTF Flag
(INTCON<1>)
Interrupt Latency 2
5
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
PC
PC
Instruction
Fetched
Inst (PC)
Instruction
Executed
Inst (PC-1)
PC+1
PC+1
Inst (PC+1)
Inst (PC)
—
Dummy Cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
Note 1: INTF flag is sampled here (every Q1).
2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency
is the same whether Inst (PC) is a single cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC Oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set any time during the Q4-Q1 cycles.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 67
rfPIC12F675
TABLE 10-8:
Address
SUMMARY OF INTERRUPT REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0Bh, 8Bh INTCON
GIE
PEIE
T0IE
0Ch
PIR1
8Ch
PIE1
EEIF
EEIE
ADIF
ADIE
—
—
INTE
GPIE
T0IF
INTF
—
—
CMIF
CMIE
—
—
—
—
Value on all
other
RESETS
Bit 0
Value on
POR, BOD
GPIF
0000 0000 0000 000u
TMR1IF 00-- 0--0 00-- 0--0
TMR1IE 00-- 0--0 00-- 0--0
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition.
Shaded cells are not used by the Interrupt module.
10.5
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt, (e.g., W register and
STATUS register). This must be implemented in
software.
Example 10-2 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be defined
in both banks and must be defined at the same offset
from the bank base address (i.e., W_TEMP is defined
at 0x20 in Bank 0 and it must also be defined at 0xA0
in Bank 1). The user register, STATUS_TEMP, must be
defined in Bank 0. The Example 10-2:
•
•
•
•
Stores the W register
Stores the STATUS register in Bank 0
Executes the ISR code
Restores the STATUS (and bank select bit
register)
• Restores the W register
EXAMPLE 10-2:
MOVWF
W_TEMP
SWAPF
BCF
STATUS,W
STATUS,RP0
SAVING THE STATUS AND
W REGISTERS IN RAM
;copy W to temp register,
could be in either bank
;swap status to be saved into W
;change to bank 0 regardless of
current bank
;save status to bank 0 register
Watchdog Timer (WDT)
The Watchdog Timer is a free running, on-chip RC
oscillator, which requires no external components. This
RC oscillator is separate from the external RC oscillator
of the CLKIN pin and INTOSC. That means that the
WDT will run, even if the clock on the OSC1 and OSC2
pins of the device has been stopped (for example, by
execution of a SLEEP instruction). During normal
operation, a WDT time-out generates a device RESET.
If the device is in SLEEP mode, a WDT time-out
causes the device to wake-up and continue with normal
operation. The WDT can be permanently disabled by
programming the configuration bit WDTE as clear
(Section 10.1).
10.6.1
MOVWF STATUS_TEMP
:
:(ISR)
:
SWAPF STATUS_TEMP,W;swap STATUS_TEMP register into
W, sets bank to original state
MOVWF STATUS
;move W into STATUS register
SWAPF W_TEMP,F
;swap W_TEMP
SWAPF W_TEMP,W
;swap W_TEMP into W
DS70091A-page 68
10.6
WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (see
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the prescaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
10.6.2
WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worst case
conditions (i.e., VDD = Min., Temperature = Max., Max.
WDT prescaler) it may take several seconds before a
WDT time-out occurs.
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
FIGURE 10-12:
WATCHDOG TIMER BLOCK DIAGRAM
CLKOUT
(= FOSC/4)
Data Bus
0
8
1
SYNC 2
Cycles
1
T0CKI
pin
0
T0CS
T0SE
TMR0
0
8-bit
Prescaler
Set Flag bit T0IF
on Overflow
PSA
1
8
PSA
1
PS0 - PS2
WDT
Time-out
Watchdog
Timer
0
PSA
WDTE
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the Option register.
TABLE 10-9:
Address
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
81h
OPTION_REG GPPU INTEDG
2007h
Config. bits
CP
Value on all
other
RESETS
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOD
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111 1111 1111
F0SC2
F0SC1
F0SC0
uuuu uuuu uuuu uuuu
BODEN MCLRE PWRTE WDTE
Legend: u = Unchanged, shaded cells are not used by the Watchdog Timer.
10.7
10.8
ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during Program/Verify. Only the
Least Significant 7 bits of the ID locations are used.
 2003 Microchip Technology Inc.
Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
Note:
Preliminary
The entire data EEPROM and FLASH
program memory will be erased when the
code protection is turned off. The INTOSC
calibration data is also erased. See
rfPIC12F675 Programming Specification
for more information.
DS70091A-page 69
rfPIC12F675
10.9
Power-Down Mode (SLEEP)
The Power-down mode is entered by executing a
SLEEP instruction.
If the Watchdog Timer is enabled:
•
•
•
•
•
External RESET input on MCLR pin
Watchdog Timer Wake-up (if WDT was enabled)
Interrupt from GP2/INT pin, GPIO change, or a
peripheral interrupt.
The first event will cause a device RESET. The two
latter events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device RESET.
The PD bit, which is set on power-up, is cleared when
SLEEP is invoked. TO bit is cleared if WDT Wake-up
occurred.
WDT will be cleared but keeps running
PD bit in the STATUS register is cleared
TO bit is set
Oscillator driver is turned off
I/O ports maintain the status they had before
SLEEP was executed (driving high, low, or
hi-impedance).
For lowest current consumption in this mode, all I/O
pins should be either at VDD, or VSS, with no external
circuitry drawing current from the I/O pin and the
comparators and CVREF should be disabled. I/O pins
that are hi-impedance inputs should be pulled high or
low externally to avoid switching currents caused by
floating inputs. The T0CKI input should also be at VDD
or VSS for lowest current consumption. The contribution from on-chip pull-ups on GPIO should be
considered.
The MCLR pin must be at a logic high level (VIHMC).
Note:
1.
2.
3.
When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction, then branches to the interrupt
address (0004h). In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have an NOP after the SLEEP instruction.
Note:
It should be noted that a RESET generated
by a WDT time-out does not drive MCLR
pin low.
10.9.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
FIGURE 10-13:
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the corresponding interrupt flag bits set, the device will
immediately wake-up from SLEEP. The
SLEEP instruction is completely executed.
The WDT is cleared when the device wakes up from
SLEEP, regardless of the source of wake-up.
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
Inst(PC) = SLEEP
Inst(PC - 1)
PC+1
PC+2
PC+2
Inst(PC + 1)
Inst(PC + 2)
SLEEP
Inst(PC + 1)
PC + 2
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
XT, HS or LP Oscillator mode assumed.
TOST = 1024TOSC (drawing not to scale). Approximately 1 µs delay will be there for RC Osc mode. See Section 12 for wake-up from
SLEEP delay in INTOSC mode.
GIE = '1' assumed. In this case after wake-up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
CLKOUT is not available in XT, HS, LP or EC Osc modes, but shown here for timing reference.
DS70091A-page 70
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
FIGURE 10-14:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
FIGURE 10-15:
PARALLEL DIP SOCKET
FOR EMULATION
8
1
2
rfPIC12F675
3
+5V
VDD
0V
VSS
VPP
GP3/MCLR/VPP
CLK
GP1
Data I/O
GP0
PIC12F675
External
Connector
Signals
To Normal
Connections
10.10 In-Circuit Serial Programming
VDD
VSS
GP5
GP0
GP4
GP1
GP3
GP2
rfPIC12F675
To Normal
Connections
6
5
4
VDD
7
The rfPIC12F675 microcontrollers can be serially
programmed while in the end application circuit. This is
done with two lines for clock and data, and three lines
for power, ground, and programming voltage.
This allows customers to manufacture boards with
unprogrammed devices, and then program the
microcontroller before shipping the product. This also
allows the most recent firmware or custom firmware to
be programmed.
The device is placed into a Program/Verify mode by
holding the GP0 and GP1 pins low, while raising the
MCLR (VPP) pin from VIL to VIHH (see Programming
Specification). GP0 becomes the programming data
and GP1 becomes the programming clock. Both GP0
and GP1 are Schmitt Trigger inputs in this mode.
After RESET, to place the device into Programming/
Verify mode, the program counter (PC) is at location
00h. A 6-bit command is then supplied to the device.
Depending on the command, 14-bits of program data
are then supplied to or from the device, depending on
whether the command was a load or a read. For
complete details of serial programming, please refer to
the Programming Specifications document.
A typical In-Circuit Serial Programming connection is
shown in Figure 10-14. The programming connections
are isolated from conflicting outputs and capacitive
loads by the 3 resistors. The VDD connection on MCLR
may not be required if the pin is configured as GP3. Do
not place sensitive circuitry on the GP3/MCLR pin
without protection since the VPP signal goes well above
VDD during programming.
 2003 Microchip Technology Inc.
10.11 In-Circuit Debugging
Since in-circuit debugging requires the loss of clock,
data and MCLR pins, MPLAB® ICD 2 development with
an 8-pin microcontroller is not practical. Since the
MPLAB ICE 2000 emulation module leads would be
too long for the RF signals the following debug/emulation strategy is recommended.
Build a prototype board with all your digital, analog, and
RF circuitry. Add an 8 pin DIP socket for the PIC12F675
debugging. Connect the socket as shown in Figure 1015. When soldering the rfPIC12F675 down bend up
pins 1-4 and 17-20 so that they do not contact the
board. A PIC12F675 or emulation/debugging development tool can be plugged into the socket as in
Figure 10-16.
This test method encourages RF development to start
early, as soon as the firmware can toggle the RF enable
and data lines. The socket can even be left in the final
layout for in-circuit production programming. A simple
method for programming is to solder all the
rfPIC12F675 pins to the board and move the 8-pin DIP
socket to the back side of the board. Then use the 8-pin
standoff from the MPLAB ICE 2000 emulator to
connect the PCB to a programmer such as the Pro
Mate® II or PICkit™ 1 as in Figure 10-17.
There is an ICD 2 header inteface board for the
PIC12F675, part number AC162050. This special ICD
module is mounted on the top of a header and its
Preliminary
DS70091A-page 71
rfPIC12F675
TABLE 10-10: DEBUGGER RESOURCES
signals are routed to the MPLAB ICD 2 connector. On
the bottom of the header is an 8-pin socket that plugs
into the user’s target via the 8-pin standoff connector.
When the ICD pin on the PIC12F675-ICD device is held
low, the In-Circuit Debugger functionality is enabled.
This function allows simple debugging functions when
used with MPLAB ICD 2. When the microcontroller has
this feature enabled, some of the resources are not
available for general use. Table 10-10 shows resources
consumed by the background debugger:
FIGURE 10-16:
I/O pins
ICDCLK, ICDDATA
Stack
1 level
Program Memory
Address 0h must be NOP
300h - 3FEh
For more information, see 8-Pin MPLAB ICD 2 Header
Information Sheet (DS51292) available on Microchip’s
website (www.microchip.com).
IN-CIRCUIT DEBUGGING USING THE PARALLEL DIP SOCKET
DVA12XP081
or
AC162050
To MPLAB ICE 2000
PCM12XB0
Standoff
rfPIC12F675
FIGURE 10-17:
Socket
IN-CIRCUIT PROGRAMMING USING THE PARALLEL DIP SOCKET
rfPIC12F675
Socket
Standoff
Programmer
DS70091A-page 72
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
11.0
INSTRUCTION SET SUMMARY
The rfPIC12F675 instruction set is highly orthogonal
and is comprised of three basic categories:
• Byte-oriented operations
• Bit-oriented operations
For example, a CLRF GPIO instruction will read GPIO,
clear all the data bits, then write the result back to
GPIO. This example would have the unintended result
that the condition that sets the GPIF flag would be
cleared.
TABLE 11-1:
• Literal and control operations
Each rfPIC12F675 instruction is a 14-bit word divided
into an opcode, which specifies the instruction type,
and one or more operands, which further specify the
operation of the instruction. The formats for each of the
categories is presented in Figure 11-1, while the
various opcode fields are summarized in Table 11-1.
Table 11-2 lists the instructions recognized by the
MPASMTM assembler. A complete description of
each instruction is also available in the PICmicro™
Mid-Range Reference Manual (DS33023).
For byte-oriented instructions, ‘f’ represents a file
register designator and ‘d’ represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the
operation, while ‘f’ represents the address of the file in
which the bit is located.
Field
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don't care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC
Program Counter
TO
Time-out bit
PD
Power-down bit
FIGURE 11-1:
One instruction cycle consists of four oscillator periods;
for an oscillator frequency of 4 MHz, this gives a normal
instruction execution time of 1 µs. All instructions are
executed within a single instruction cycle, unless a
conditional test is true, or the program counter is
changed as a result of an instruction. When this occurs,
the execution takes two instruction cycles, with the
second cycle executed as a NOP.
To maintain upward compatibility with
future products, do not use the OPTION
and TRISIO instructions.
All instruction examples use the format ‘0xhh’ to
represent a hexadecimal number, where ‘h’ signifies
a hexadecimal digit.
11.1
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
0
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
READ-MODIFY-WRITE
OPERATIONS
CALL and GOTO instructions only
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
 2003 Microchip Technology Inc.
Description
f
For literal and control operations, ‘k’ represents an
8-bit or 11-bit constant, or literal value.
Note:
OPCODE FIELD
DESCRIPTIONS
Preliminary
13
11
OPCODE
10
0
k (literal)
k = 11-bit immediate value
DS70091A-page 73
rfPIC12F675
TABLE 11-2:
rfPIC12F675 INSTRUCTION SET
Mnemonic,
Operands
14-Bit Opcode
Description
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1 (2)
1 (2)
01
01
01
01
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023).
DS70091A-page 74
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
11.2
Instruction Descriptions
ADDLW
Add Literal and W
BCF
Bit Clear f
Syntax:
[label] ADDLW
Syntax:
[label] BCF
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
(W) + k → (W)
0 ≤ f ≤ 127
0≤b≤7
Status Affected:
C, DC, Z
Operation:
0 → (f<b>)
Description:
The contents of the W register
are added to the eight-bit literal 'k'
and the result is placed in the W
register.
Status Affected:
None
Description:
Bit 'b' in register 'f' is cleared.
ADDWF
Add W and f
BSF
Bit Set f
Syntax:
[label] ADDWF
Operands:
k
f,b
Syntax:
[label] BSF
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
(W) + (f) → (destination)
Operation:
1 → (f<b>)
Status Affected:
C, DC, Z
Status Affected:
None
Description:
Add the contents of the W register
with register 'f'. If 'd' is 0, the result
is stored in the W register. If 'd' is
1, the result is stored back in
register 'f'.
Description:
Bit 'b' in register 'f' is set.
ANDLW
AND Literal with W
BTFSS
Bit Test f, Skip if Set
Syntax:
[label] ANDLW
Syntax:
[label] BTFSS f,b
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
(W) .AND. (k) → (W)
0 ≤ f ≤ 127
0≤b<7
Status Affected:
Z
Operation:
skip if (f<b>) = 1
Description:
The contents of W register are
AND’ed with the eight-bit literal
'k'. The result is placed in the W
register.
Status Affected:
None
Description:
If bit 'b' in register 'f' is '0', the next
instruction is executed.
If bit 'b' is '1', then the next
instruction is discarded and a NOP
is executed instead, making this a
2TCY instruction.
BTFSC
Bit Test, Skip if Clear
Syntax:
[label] BTFSC f,b
f,d
k
f,b
ANDWF
AND W with f
Syntax:
[label] ANDWF
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
(W) .AND. (f) → (destination)
Operation:
skip if (f<b>) = 0
Status Affected:
Z
Status Affected:
None
Description:
AND the W register with register
'f'. If 'd' is 0, the result is stored in
the W register. If 'd' is 1, the result
is stored back in register 'f'.
Description:
If bit 'b' in register 'f' is '1', the next
instruction is executed.
If bit 'b', in register 'f', is '0', the
next instruction is discarded, and
a NOP is executed instead, making
this a 2TCY instruction.
 2003 Microchip Technology Inc.
f,d
Preliminary
DS70091A-page 75
rfPIC12F675
CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRWDT
Operands:
0 ≤ k ≤ 2047
Operands:
None
Operation:
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Operation:
Status Affected:
None
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Description:
Call Subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven-bit immediate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALL is
a two-cycle instruction.
Status Affected:
TO, PD
Description:
CLRWDT instruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT.
STATUS bits TO and PD are set.
CLRF
Clear f
COMF
Complement f
Syntax:
[label] CLRF
Syntax:
[ label ] COMF
Operands:
0 ≤ f ≤ 127
Operands:
Operation:
00h → (f)
1→Z
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) → (destination)
Status Affected:
Z
Status Affected:
Z
Description:
The contents of register 'f' are
cleared and the Z bit is set.
Description:
The contents of register 'f' are
complemented. If 'd' is 0, the
result is stored in W. If 'd' is 1, the
result is stored back in register 'f'.
CLRW
Clear W
DECF
Decrement f
f
f,d
Syntax:
[ label ] CLRW
Syntax:
[label] DECF f,d
Operands:
None
Operands:
Operation:
00h → (W)
1→Z
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination)
Status Affected:
Z
Status Affected:
Z
Description:
W register is cleared. Zero bit (Z)
is set.
Description:
Decrement register 'f'. If 'd' is 0,
the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
DS70091A-page 76
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination);
skip if result = 0
Operation:
(f) + 1 → (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
The contents of register 'f' are
decremented. If 'd' is 0, the result
is placed in the W register. If 'd' is
1, the result is placed back in
register 'f'.
If the result is 1, the next instruction is executed. If the result is 0,
then a NOP is executed instead,
making it a 2TCY instruction.
Description:
The contents of register 'f' are
incremented. If 'd' is 0, the result is
placed in the W register. If 'd' is 1,
the result is placed back in
register 'f'.
If the result is 1, the next instruction is executed. If the result is 0,
a NOP is executed instead, making
it a 2TCY instruction.
GOTO
Unconditional Branch
IORLW
INCFSZ f,d
Inclusive OR Literal with W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 2047
Operands:
0 ≤ k ≤ 255
Operation:
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Operation:
(W) .OR. k → (W)
Status Affected:
Z
Status Affected:
None
Description:
Description:
GOTO is an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a twocycle instruction.
The contents of the W register are
OR’ed with the eight-bit literal 'k'.
The result is placed in the W
register.
INCF
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) + 1 → (destination)
Operation:
(W) .OR. (f) → (destination)
Status Affected:
Z
Status Affected:
Z
Description:
The contents of register 'f' are
incremented. If 'd' is 0, the result
is placed in the W register. If 'd' is
1, the result is placed back in
register 'f'.
Description:
Inclusive OR the W register with
register 'f'. If 'd' is 0, the result is
placed in the W register. If 'd' is 1,
the result is placed back in
register 'f'.
GOTO k
INCF f,d
 2003 Microchip Technology Inc.
Preliminary
IORLW k
IORWF
f,d
DS70091A-page 77
rfPIC12F675
MOVF
Move f
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
MOVF f,d
NOP
No Operation
Syntax:
[ label ]
Operands:
None
Operation:
No operation
NOP
Operation:
(f) → (destination)
Status Affected:
None
Status Affected:
Z
Description:
No operation.
Description:
The contents of register f are
moved to a destination dependant
upon the status of d. If d = 0,
destination is W register. If d = 1,
the destination is file register f itself.
d = 1 is useful to test a file register,
since status flag Z is affected.
MOVLW
Move Literal to W
RETFIE
Return from Interrupt
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
None
Operation:
k → (W)
Operation:
Status Affected:
None
TOS → PC,
1 → GIE
Description:
The eight-bit literal 'k' is loaded
into W register. The don’t cares
will assemble as 0’s.
Status Affected:
None
MOVWF
Move W to f
RETLW
Return with Literal in W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
Operands:
0 ≤ k ≤ 255
Operation:
(W) → (f)
Operation:
Status Affected:
None
k → (W);
TOS → PC
Description:
Move data from W register to
register 'f'.
Status Affected:
None
Description:
The W register is loaded with the
eight-bit literal 'k'. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
DS70091A-page 78
MOVLW k
MOVWF
f
Preliminary
RETFIE
RETLW k
 2003 Microchip Technology Inc.
rfPIC12F675
RLF
Rotate Left f through Carry
SLEEP
Syntax:
[ label ] RLF
Syntax:
[ label ] SLEEP
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
None
Operation:
00h → WDT,
0 → WDT prescaler,
1 → TO,
0 → PD
Status Affected:
TO, PD
Description:
The power-down STATUS bit,
PD is cleared. Time-out STATUS
bit, TO is set. Watchdog Timer
and its prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
f,d
Operation:
See description below
Status Affected:
C
Description:
The contents of register 'f' are rotated
one bit to the left through the Carry
Flag. If 'd' is 0, the result is placed in
the W register. If 'd' is 1, the result is
stored back in register 'f'.
C
Register f
RETURN
Return from Subroutine
SUBLW
Subtract W from Literal
Syntax:
[ label ]
Syntax:
[ label ] SUBLW k
Operands:
None
Operands:
0 ≤ k ≤ 255
k - (W) → (W)
RETURN
Operation:
TOS → PC
Operation:
Status Affected:
None
Status Affected: C, DC, Z
Description:
Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
Description:
The W register is subtracted (2’s
complement method) from the
eight-bit literal 'k'. The result is
placed in the W register.
RRF
Rotate Right f through Carry
SUBWF
Subtract W from f
Syntax:
[ label ]
Syntax:
[ label ] SUBWF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
RRF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
See description below
Operation:
(f) - (W) → (destination)
Status Affected:
C
The contents of register 'f' are
rotated one bit to the right through
the Carry Flag. If 'd' is 0, the result
is placed in the W register. If 'd' is
1, the result is placed back in
register 'f'.
Status
Affected:
C, DC, Z
Description:
Description:
Subtract (2’s complement method)
W register from register 'f'. If 'd' is 0,
the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
C
 2003 Microchip Technology Inc.
Register f
Preliminary
DS70091A-page 79
rfPIC12F675
SWAPF
Swap Nibbles in f
XORWF
Exclusive OR W with f
Syntax:
[ label ] SWAPF f,d
Syntax:
[label]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Operation:
(W) .XOR. (f) → (destination)
Status Affected:
Z
Status Affected:
None
Description:
Description:
The upper and lower nibbles of
register 'f' are exchanged. If 'd' is
0, the result is placed in the W
register. If 'd' is 1, the result is
placed in register 'f'.
Exclusive OR the contents of the
W register with register 'f'. If 'd' is
0, the result is stored in the W
register. If 'd' is 1, the result is
stored back in register 'f'.
XORLW
Exclusive OR Literal with W
Syntax:
[label]
Operands:
0 ≤ k ≤ 255
Operation:
(W) .XOR. k → (W)
Status Affected:
Z
Description:
The contents of the W register
are XOR’ed with the eight-bit
literal 'k'. The result is placed in
the W register.
DS70091A-page 80
XORWF
f,d
XORLW k
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
12.0
DEVELOPMENT SUPPORT
12.1
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB C30 C Compiler
- MPLAB ASM30 Assembler/Linker/Library
• Simulators
- MPLAB SIM Software Simulator
- MPLAB dsPIC30 Software Simulator
• Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- MPLAB ICE 4000 In-Circuit Emulator
• In-Circuit Debugger
- MPLAB ICD 2
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Development Programmer
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM.netTM Demonstration Board
- PICDEM 2 Plus Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 4 Demonstration Board
- PICDEM 17 Demonstration Board
- PICDEM 18R Demonstration Board
- PICDEM LIN Demonstration Board
- PICDEM USB Demonstration Board
• Evaluation Kits
- KEELOQ®
- PICDEM MSC
- microID®
- CAN
- PowerSmart®
- Analog
MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16-bit
microcontroller market. The MPLAB IDE is a Windows®
based application that contains:
• An interface to debugging tools
- simulator
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor with color coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High level source code debugging
• Mouse over variable inspection
• Extensive on-line help
The MPLAB IDE allows you to:
• Edit your source files (either assembly or C)
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools
(automatically updates all project information)
• Debug using:
- source files (assembly or C)
- absolute listing file (mixed assembly and C)
- machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost effective
simulators, through low cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increasing flexibility
and power.
12.2
MPASM Assembler
The MPASM assembler is a full-featured, universal
macro assembler for all PICmicro MCUs.
The MPASM assembler generates relocatable object
files for the MPLINK object linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and
generated machine code and COFF files for
debugging.
The MPASM assembler features include:
• Integration into MPLAB IDE projects
• User defined macros to streamline assembly code
• Conditional assembly for multi-purpose source
files
• Directives that allow complete control over the
assembly process
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 81
rfPIC12F675
12.3
12.6
MPLAB C17 and MPLAB C18
C Compilers
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI C compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use not found with other compilers.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
12.4
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can link
relocatable objects from pre-compiled libraries, using
directives from a linker script.
The MPLIB object librarian manages the creation and
modification of library files of pre-compiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
12.5
MPLAB C30 C Compiler
MPLAB C30 is distributed with a complete ANSI C
standard library. All library functions have been
validated and conform to the ANSI C library standard.
The library includes functions for string manipulation,
dynamic memory allocation, data conversion,
timekeeping, and math functions (trigonometric,
exponential and hyperbolic). The compiler provides
symbolic information for high level source debugging
with the MPLAB IDE.
DS70091A-page 82
MPLAB ASM30 assembler produces relocatable
machine code from symbolic assembly language for
dsPIC30F devices. MPLAB C30 compiler uses the
assembler to produce it’s object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
•
•
•
•
•
•
Support for the entire dsPIC30F instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
12.7
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code
development in a PC hosted environment by simulating
the PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any pin. The execution can be performed in Single-Step, Execute Until
Break, or Trace mode.
The MPLAB SIM simulator fully supports symbolic
debugging using the MPLAB C17 and MPLAB C18
C Compilers, as well as the MPASM assembler. The
software simulator offers the flexibility to develop and
debug code outside of the laboratory environment,
making it an excellent, economical software
development tool.
12.8
The MPLAB C30 C compiler is a full-featured, ANSI
compliant, optimizing compiler that translates standard
ANSI C programs into dsPIC30F assembly language
source. The compiler also supports many commandline options and language extensions to take full
advantage of the dsPIC30F device hardware capabilities, and afford fine control of the compiler code
generator.
MPLAB ASM30 Assembler, Linker,
and Librarian
MPLAB SIM30 Software Simulator
The MPLAB SIM30 software simulator allows code
development in a PC hosted environment by simulating
the dsPIC30F series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user defined key press, to any of the pins.
The MPLAB SIM30 simulator fully supports symbolic
debugging using the MPLAB C30 C Compiler and
MPLAB ASM30 assembler. The simulator runs in either
a Command Line mode for automated tasks, or from
MPLAB IDE. This high speed simulator is designed to
debug, analyze and optimize time intensive DSP
routines.
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
12.9
12.11 MPLAB ICD 2 In-Circuit Debugger
MPLAB ICE 2000
High Performance Universal
In-Circuit Emulator
The MPLAB ICE 2000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for
PICmicro microcontrollers. Software control of the
MPLAB ICE 2000 in-circuit emulator is advanced by
the MPLAB Integrated Development Environment,
which allows editing, building, downloading and source
debugging from a single environment.
The MPLAB ICE 2000 is a full-featured emulator
system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow
the system to be easily reconfigured for emulation of
different processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE 2000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft® Windows 32-bit operating system were
chosen to best make these features available in a
simple, unified application.
12.10 MPLAB ICE 4000
High Performance Universal
In-Circuit Emulator
The MPLAB ICE 4000 universal in-circuit emulator is
intended to provide the product development engineer
with a complete microcontroller design tool set for highend PICmicro microcontrollers. Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment, which
allows editing, building, downloading and source
debugging from a single environment.
The MPLAB ICD 4000 is a premium emulator system,
providing the features of MPLAB ICE 2000, but with
increased emulation memory and high speed performance for dsPIC30F and PIC18XXXX devices. Its
advanced emulator features include complex triggering
and timing, up to 2 Mb of emulation memory, and the
ability to view variables in real-time.
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a
powerful, low cost, run-time development tool,
connecting to the host PC via an RS-232 or high speed
USB interface. This tool is based on the FLASH
PICmicro MCUs and can be used to develop for these
and other PICmicro microcontrollers. The MPLAB
ICD 2 utilizes the in-circuit debugging capability built
into the FLASH devices. This feature, along with
Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM)
protocol, offers cost effective in-circuit FLASH debugging from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by setting
breakpoints, single-stepping and watching variables,
CPU status and peripheral registers. Running at full
speed enables testing hardware and applications in
real-time. MPLAB ICD 2 also serves as a development
programmer for selected PICmicro devices.
12.12 PRO MATE II Universal Device
Programmer
The PRO MATE II is a universal, CE compliant device
programmer with programmable voltage verification at
VDDMIN and VDDMAX for maximum reliability. It features
an LCD display for instructions and error messages
and a modular detachable socket assembly to support
various package types. In Stand-Alone mode, the
PRO MATE II device programmer can read, verify, and
program PICmicro devices without a PC connection. It
can also set code protection in this mode.
12.13 PICSTART Plus Development
Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It
connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient. The
PICSTART Plus development programmer supports
most PICmicro devices up to 40 pins. Larger pin count
devices, such as the PIC16C92X and PIC17C76X,
may be supported with an adapter socket. The
PICSTART Plus development programmer is CE
compliant.
The MPLAB ICE 4000 in-circuit emulator system has
been designed as a real-time emulation system with
advanced features that are typically found on more
expensive development tools. The PC platform and
Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple,
unified application.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 83
rfPIC12F675
12.14 PICDEM 1 PICmicro
Demonstration Board
12.17 PICDEM 3 PIC16C92X
Demonstration Board
The PICDEM 1 demonstration board demonstrates the
capabilities of the PIC16C5X (PIC16C54 to
PIC16C58A), PIC16C61, PIC16C62X, PIC16C71,
PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All
necessary hardware and software is included to run
basic demo programs. The sample microcontrollers
provided with the PICDEM 1 demonstration board can
be programmed with a PRO MATE II device programmer, or a PICSTART Plus development programmer.
The PICDEM 1 demonstration board can be connected
to the MPLAB ICE in-circuit emulator for testing. A
prototype area extends the circuitry for additional
application components. Features include an RS-232
interface, a potentiometer for simulated analog input,
push button switches and eight LEDs.
The PICDEM 3 demonstration board supports the
PIC16C923 and PIC16C924 in the PLCC package. All
the necessary hardware and software is included to run
the demonstration programs.
12.15 PICDEM.net Internet/Ethernet
Demonstration Board
The PICDEM.net demonstration board is an Internet/
Ethernet demonstration board using the PIC18F452
microcontroller and TCP/IP firmware. The board
supports any 40-pin DIP device that conforms to the
standard pinout used by the PIC16F877 or
PIC18C452. This kit features a user friendly TCP/IP
stack, web server with HTML, a 24L256 Serial
EEPROM for Xmodem download to web pages into
Serial EEPROM, ICSP/MPLAB ICD 2 interface
connector, an Ethernet interface, RS-232 interface,
and a 16 x 2 LCD display. Also included is the book and
CD-ROM “TCP/IP Lean, Web Servers for Embedded
Systems,” by Jeremy Bentham
12.16 PICDEM 2 Plus
Demonstration Board
The PICDEM 2 Plus demonstration board supports
many 18-, 28-, and 40-pin microcontrollers, including
PIC16F87X and PIC18FXX2 devices. All the necessary hardware and software is included to run the demonstration programs. The sample microcontrollers
provided with the PICDEM 2 demonstration board can
be programmed with a PRO MATE II device programmer, PICSTART Plus development programmer, or
MPLAB ICD 2 with a Universal Programmer Adapter.
The MPLAB ICD 2 and MPLAB ICE in-circuit emulators
may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area extends the
circuitry for additional application components. Some
of the features include an RS-232 interface, a 2 x 16
LCD display, a piezo speaker, an on-board temperature
sensor, four LEDs, and sample PIC18F452 and
PIC16F877 FLASH microcontrollers.
DS70091A-page 84
12.18 PICDEM 4 8/14/18-Pin
Demonstration Board
The PICDEM 4 can be used to demonstrate the capabilities of the 8-, 14-, and 18-pin PIC16XXXX and
PIC18XXXX MCUs, including the PIC16F818/819,
PIC16F87/88, PIC16F62XA and the PIC18F1320
Family of microcontrollers. PICDEM 4 is intended to
showcase the many features of these low pin count
parts, including LIN and Motor Control using ECCP.
Special provisions are made for low power operation
with the supercapacitor circuit, and jumpers allow onboard hardware to be disabled to eliminate current
draw in this mode. Included on the demo board are provisions for Crystal, RC or Canned Oscillator modes, a
five volt regulator for use with a nine volt wall adapter
or battery, DB-9 RS-232 interface, ICD connector for
programming via ICSP and development with MPLAB
ICD 2, 2x16 liquid crystal display, PCB footprints for HBridge motor driver, LIN transceiver and EEPROM.
Also included are: header for expansion, eight LEDs,
four potentiometers, three push buttons and a prototyping area. Included with the kit is a PIC16F627A and
a PIC18F1320. Tutorial firmware is included along with
the User’s Guide.
12.19 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. A
programmed sample is included. The PRO MATE II
device programmer, or the PICSTART Plus development programmer, can be used to reprogram the
device for user tailored application development. The
PICDEM 17 demonstration board supports program
download and execution from external on-board
FLASH memory. A generous prototype area is
available for user hardware expansion.
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
12.20 PICDEM 18R PIC18C601/801
Demonstration Board
12.23 PICDEM USB PIC16C7X5
Demonstration Board
The PICDEM 18R demonstration board serves to assist
development of the PIC18C601/801 family of Microchip
microcontrollers. It provides hardware implementation
of both 8-bit Multiplexed/De-multiplexed and 16-bit
Memory modes. The board includes 2 Mb external
FLASH memory and 128 Kb SRAM memory, as well as
serial EEPROM, allowing access to the wide range of
memory types supported by the PIC18C601/801.
The PICDEM USB Demonstration Board shows off the
capabilities of the PIC16C745 and PIC16C765 USB
microcontrollers. This board provides the basis for
future USB products.
12.21 PICDEM LIN PIC16C43X
Demonstration Board
The powerful LIN hardware and software kit includes a
series of boards and three PICmicro microcontrollers.
The small footprint PIC16C432 and PIC16C433 are
used as slaves in the LIN communication and feature
on-board LIN transceivers. A PIC16F874 FLASH
microcontroller serves as the master. All three microcontrollers are programmed with firmware to provide
LIN bus communication.
12.22 PICkitTM 1 FLASH Starter Kit
A complete "development system in a box", the PICkit
FLASH Starter Kit includes a convenient multi-section
board for programming, evaluation, and development
of 8/14-pin FLASH PIC® microcontrollers. Powered via
USB, the board operates under a simple Windows GUI.
The PICkit 1 Starter Kit includes the user's guide (on
CD ROM), PICkit 1 tutorial software and code for various applications. Also included are MPLAB® IDE (Integrated Development Environment) software, software
and hardware "Tips 'n Tricks for 8-pin FLASH PIC®
Microcontrollers" Handbook and a USB Interface
Cable. Supports all current 8/14-pin FLASH PIC
microcontrollers, as well as many future planned
devices.
 2003 Microchip Technology Inc.
12.24 Evaluation and
Programming Tools
In addition to the PICDEM series of circuits, Microchip
has a line of evaluation kits and demonstration software
for these products.
• KEELOQ evaluation and programming tools for
Microchip’s HCS Secure Data Products
• CAN developers kit for automotive network
applications
• Analog design boards and filter design software
• PowerSmart battery charging evaluation/
calibration kits
• IrDA® development kit
• microID development and rfLabTM development
software
• SEEVAL® designer kit for memory evaluation and
endurance calculations
• PICDEM MSC demo boards for Switching mode
power supply, high power IR driver, delta sigma
ADC, and flow rate sensor
Check the Microchip web page and the latest Product
Line Card for the complete list of demonstration and
evaluation kits.
Preliminary
DS70091A-page 85
rfPIC12F675
NOTES:
DS70091A-page 86
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
13.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings†
Ambient temperature under bias........................................................................................................... -40 to +125°C
Storage temperature ........................................................................................................................ -65°C to +150°C
Voltage on VDD with respect to VSS ....................................................................................................... -0.3 to +6.5V
Voltage on VDDRF with respect to VSSRF ............................................................................................... -0.3 to +7.0V
Voltage on MCLR with respect to Vss...................................................................................................-0.3 to +13.5V
Voltage on all GPIO pins with respect to VSS............................................................................ -0.3V to (VDD + 0.3V)
Voltage on all other RF Transmitter pins with respect to VSSRF .............................................-0.3V to (VDDRF + 0.3V)
Total power dissipation(1) ............................................................................................................................... 800 mW
Maximum current out of VSS pin ..................................................................................................................... 300 mA
Maximum current into VDD pin ........................................................................................................................ 250 mA
Input clamp current, IIK (VI < 0 or VI > VDD)...............................................................................................................± 20 mA
Output clamp current, IOK (Vo < 0 or Vo >VDD).........................................................................................................± 20 mA
Maximum output current sunk by any GPIO pin ............................................................................................... 25 mA
Maximum output current sourced by any GPIO pin .......................................................................................... 25 mA
Maximum total current sunk by all GPIO pins ................................................................................................. 125 mA
Maximum total current sourced all GPIO pins................................................................................................. 125 mA
Note 1: Power dissipation is calculated as follows:
PDIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL) + VDDRF x {IDDRF - ∑ IOHRF} + ∑ {(VDDRFVOHRF) x IOHRF} + ∑(VOLRF x IOLRF)
† NOTICE: Stresses above those listed under ‘Absolute Maximum Ratings’ may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note:
Voltage spikes below VSS at the MCLR pin, inducing currents greater than 80 mA, may cause latchup. Thus,
a series resistor of 50-100 Ω should be used when applying a "low" level to the MCLR pin, rather than pulling
this pin directly to VSS.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 87
rfPIC12F675
FIGURE 13-1:
rfPIC12F675 WITH A/D DISABLED VOLTAGE-FREQUENCY GRAPH,
-40°C ≤ TA ≤ +125°C
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
4
8
10
12
16
20
Microcontroller Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
FIGURE 13-2:
rfPIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH,
-40°C ≤ TA ≤ +125°C
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.0
0
4
8
10
12
16
20
Microcontroller Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
DS70091A-page 88
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
FIGURE 13-3:
rfPIC12F675 WITH A/D ENABLED VOLTAGE-FREQUENCY GRAPH,
0°C ≤ TA ≤ +125°C
5.5
5.0
4.5
VDD
(Volts)
4.0
3.5
3.0
2.5
2.2
2.0
0
4
8
10
12
16
20
Microcontroller Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 89
rfPIC12F675
13.1
DC Characteristics: rfPIC12F675-I (Industrial), rfPIC12F675-E (Extended)
DC CHARACTERISTICS
Param
No.
Sym
VDD
Characteristic
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Min
Typ†
Max
Units
Conditions
2.0
2.2
2.5
3.0
4.5
—
—
—
—
—
5.5
5.5
5.5
5.5
5.5
V
V
V
V
V
FOSC < = 4 MHz:
rfPIC12F675 with A/D off
rfPIC12F675 with A/D on, 0°C to +125°C
rfPIC12F675 with A/D on, -40°C to +125°C
4 MHZ < FOSC < = 10 MHz
FOSC > 10 MHz
1.5*
—
—
V
Device in SLEEP mode
V
See section on Power-on Reset for details
Supply Voltage
D001
D001A
D001B
D001C
D001D
D002
VDR
RAM Data Retention
Voltage(1)
D003
VPOR
VDD Start Voltage to
ensure internal Power-on
Reset signal
—
VSS
—
D004
SVDD
VDD Rise Rate to ensure
internal Power-on Reset
signal
0.05*
—
—
D005
VBOD
—
2.1
—
V
2.0
3.0
4.0
5.0
—
—
—
—
5.5
5.5
5.5
5.5
V
V
V
V
Output Power = 4 dBm
Output Power = 7.5 dBm
Output Power = 8.5 dBm
Output Power = 9 dBm
1.8
1.85
1.9
V
TA =+23°C, RFEN = VDDRF
D006
D006A
D006B
D006C
D007
VDDRF RF Transmitter Supply
Voltage
VLVD
RF Low Voltage Disable
V/ms See section on Power-on Reset for details
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
DS70091A-page 90
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
13.2
DC Characteristics: rfPIC12F675-I (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Conditions
Param
No.
Device Characteristics
D010
Supply Current (IDD)(3)
Min
Typ†
Max
Units
VDD
D011
D012
D013
D014
D015
D016
D017
—
9
16
µA
2.0
—
18
28
µA
3.0
—
34
54
µA
5.0
—
110
150
µA
2.0
—
190
280
µA
3.0
—
330
450
µA
5.0
—
220
280
µA
2.0
—
370
650
µA
3.0
—
0.6
1.4
mA
5.0
—
70
110
µA
2.0
—
140
250
µA
3.0
—
260
390
µA
5.0
—
180
250
µA
2.0
—
320
470
µA
3.0
—
580
850
µA
5.0
—
340
450
µA
2.0
—
500
700
µA
3.0
—
0.8
1.1
mA
5.0
—
180
250
µA
2.0
—
320
450
µA
3.0
—
580
800
µA
5.0
—
2.1
2.95
mA
4.5
—
2.4
3.0
mA
5.0
Note
FOSC = 32 kHz
LP Oscillator Mode
FOSC = 1 MHz
XT Oscillator Mode
FOSC = 4 MHz
XT Oscillator Mode
FOSC = 1 MHz
EC Oscillator Mode
FOSC = 4 MHz
EC Oscillator Mode
FOSC = 4 MHz
INTOSC Mode
FOSC = 4 MHz
EXTRC Mode
FOSC = 20 MHz
HS Oscillator Mode
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave,
from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have
an impact on the current consumption.
3: Total device current is the sum of IDD from VDD and IDDRF from VDDRF.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 91
rfPIC12F675
13.3
DC Characteristics: rfPIC12F675-I (Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
Param
No.
D020
Conditions
Device Characteristics
Power-down Current
(IPD)(3)
D021
D022
D023
D024
D025
D026
D027
Power-down RF Current
(IPDRF)(3)
Min
—
Typ†
0.99
Max
700
Units
nA
VDD
Note
2.0
WDT, BOD, Comparators, VREF, and
T1OSC disabled
—
1.2
770
nA
3.0
—
2.9
995
nA
5.0
—
0.3
1.5
µA
2.0
—
1.8
3.5
µA
3.0
—
8.4
17
µA
5.0
—
58
70
µA
3.0
—
109
130
µA
5.0
—
3.3
6.5
µA
2.0
—
6.1
8.5
µA
3.0
—
11.5
16
µA
5.0
—
58
70
µA
2.0
—
85
100
µA
3.0
—
138
160
µA
5.0
—
4.0
6.5
µA
2.0
—
4.6
7.0
µA
3.0
—
6.0
10.5
µA
5.0
—
1.2
775
nA
3.0
—
2.2
1.0
mA
5.0
—
0.050
TBD
µA
3.0
WDT Current(1)
BOD Current(1)
Comparator Current(1)
CVREF Current(1)
T1 OSC Current(1)
A/D Current(1)
RF Transmitter with RFEN=0
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral ∆ current can be determined by subtracting the base IDD or IPD
current from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD.
3: Total device current is the sum of IPD from VDD and IPDRF from VDDRF.
DS70091A-page 92
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
13.4
DC Characteristics: rfPIC12F675-E (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +125°C for extended
Conditions
Param
No.
Device Characteristics
D010E
Supply Current (IDD)(3)
Min
Typ†
Max
Units
VDD
D011E
D012E
D013E
D014E
D015E
D016E
D017E
—
9
16
µA
2.0
—
18
28
µA
3.0
—
35
54
µA
5.0
—
110
150
µA
2.0
—
190
280
µA
3.0
—
330
450
µA
5.0
—
220
280
µA
2.0
—
370
650
µA
3.0
—
0.6
1.4
mA
5.0
—
70
110
µA
2.0
—
140
250
µA
3.0
—
260
390
µA
5.0
—
180
250
µA
2.0
—
320
470
µA
3.0
—
580
850
µA
5.0
—
340
450
µA
2.0
—
500
780
µA
3.0
—
0.8
1.1
mA
5.0
—
180
250
µA
2.0
—
320
450
µA
3.0
—
580
800
µA
5.0
—
2.1
2.95
mA
4.5
—
2.4
3.0
mA
5.0
Note
FOSC = 32 kHz
LP Oscillator Mode
FOSC = 1 MHz
XT Oscillator Mode
FOSC = 4 MHz
XT Oscillator Mode
FOSC = 1 MHz
EC Oscillator Mode
FOSC = 4 MHz
EC Oscillator Mode
FOSC = 4 MHz
INTOSC Mode
FOSC = 4 MHz
EXTRC Mode
FOSC = 20 MHz
HS Oscillator Mode
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The test conditions for all IDD measurements in Active Operation mode are: OSC1 = external square wave,
from rail to rail; all I/O pins tri-stated, pulled to VDD; MCLR = VDD; WDT disabled.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have
an impact on the current consumption.
3: Total device current is the sum of IDD from VDD and IDDRF from VDDRF.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 93
rfPIC12F675
13.5
DC Characteristics: rfPIC12F675-E (Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +125°C for extended
Param
No.
D020E
Conditions
Device Characteristics
Power-down Current
(IPD)(3)
D021E
D022E
D023E
D024E
D025E
D026E
D027E
Power-down RF Current
(IPDRF)(3)
Min
—
Typ†
0.0011
Max
Units
3.5
µA
VDD
Note
2.0
WDT, BOD, Comparators, VREF, and
T1OSC disabled
—
0.0012
4.0
µA
3.0
—
0.0022
8.0
µA
5.0
—
0.3
6.0
µA
2.0
—
1.8
9.0
µA
3.0
—
8.4
20
µA
5.0
—
58
70
µA
3.0
—
109
130
µA
5.0
—
3.3
10
µA
2.0
—
6.1
13
µA
3.0
—
11.5
24
µA
5.0
—
58
70
µA
2.0
—
85
100
µA
3.0
—
138
165
µA
5.0
—
4.0
10
µA
2.0
—
4.6
12
µA
3.0
—
6.0
20
µA
5.0
—
0.0012
6.0
µA
3.0
—
0.0022
8.5
µA
5.0
—
0.050
TBD
µA
3.0
WDT Current(1)
BOD Current(1)
Comparator Current(1)
CVREF Current(1)
T1 OSC Current(1)
A/D Current(1)
RF Transmitter, RFEN=VSSRF
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: The peripheral current is the sum of the base IDD or IPD and the additional current consumed when this
peripheral is enabled. The peripheral ∆ current can be determined by subtracting the base IDD or IPD current
from this limit. Max values should be used when calculating total current consumption.
2: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD.
3: Total device current is the sum of IPD from VDD and IPDRF from VDDRF.
DS70091A-page 94
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
13.6
DC Characteristics: rfPIC12F675K
Standard Operating Conditions (unless otherwise stated)
Operating temperature
TA = +23°C
Operating Frequency
fc = 315 MHz
Param
No.
D018A
D018B
Conditions
Device Characteristics
Min
Typ
Max
Units
VDD
RF Transmitter Current
(IDDRF)(2)
D018C
2.0
2.7
5.0
mA
3.0
Note
2.9
3.5
7.0
mA
3.0
Power Step 0, RFEN=DATAASK=1
Power Step 1, RFEN=DATAASK=1
3.2
4.7
7.9
mA
3.0
Power Step 2, RFEN=DATAASK=1
Power Step 3, RFEN=DATAASK=1
Power Step 4, RFEN=DATAASK=1
D018D
4.5
6.5
11
mA
3.0
D018E
7.0
10.7
16
mA
3.0
Note 1: The supply current is mainly a function of the operating voltage and frequency. Other factors such as output
loading and temperature also have an impact on the current consumption.
2: Total device current is the sum of IDD from VDD and IDDRF from VDDRF.
13.7
DC Characteristics: rfPIC12F675F
Standard Operating Conditions (unless otherwise stated)
Operating temperature
TA = +23°C
Operating Frequency
fc = 434 MHz
Param
No.
D018A
D018B
Conditions
Device Characteristics
Min
Typ
Max
Units
VDD
RF Transmitter Current
(IDDRF)(2)
D018C
Note
2.0
2.7
5.0
mA
3.0
2.9
3.5
7.0
mA
3.0
Power Step 0, RFEN=DATAASK=1
Power Step 1, RFEN=DATAASK=1
3.2
4.7
7.9
mA
3.0
Power Step 2, RFEN=DATAASK=1
Power Step 3, RFEN=DATAASK=1
Power Step 4, RFEN=DATAASK=1
D018D
4.5
6.5
11
mA
3.0
D018E
7.0
10.7
16
mA
3.0
Note 1: The supply current is mainly a function of the operating voltage and frequency. Other factors such as output
loading and temperature also have an impact on the current consumption.
2: Total device current is the sum of IDD from VDD and IDDRF from VDDRF.
13.8
DC Characteristics: rfPIC12F675H
Standard Operating Conditions (unless otherwise stated)
Operating temperature
TA = +23°C
Operating Frequency
fc = 868 MHz
Param
No.
D018A
D018B
Conditions
Device Characteristics
Min
Typ
Max
Units
VDD
RF Transmitter Current
(IDDRF)(2)
2.6
4.0
6.5
mA
3.0
3.5
5.3
8.5
mA
3.0
Note
Power Step 0, RFEN=DATAASK=1
Power Step 1, RFEN=DATAASK=1
D018C
4.5
6.7
11
mA
3.0
Power Step 2, RFEN=DATAASK=1
D018D
6.0
9.0
14
mA
3.0
D018E
9.0
14.0
20
mA
3.0
Power Step 3, RFEN=DATAASK=1
Power Step 4, RFEN=DATAASK=1
Note 1: The supply current is mainly a function of the operating voltage and frequency. Other factors such as output
loading and temperature also have an impact on the current consumption.
2: Total device current is the sum of IDD from VDD and IDDRF from VDDRF.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 95
rfPIC12F675
13.9
DC Characteristics: rfPIC12F675-I (Industrial), rfPIC12F675-E (Extended)
DC CHARACTERISTICS
Param
Sym
No.
VIL
D030
D030A
D031
D032
D033
D033A
D034
VIH
D040
D040A
D041
D042
D043
D043A
D043B
D044
D070 IPUR
D071
D072
D060
IIL
D060A
D060B
D061
D063
D080
D083
VOL
D090
D092
VOH
Characteristic
Input Low Voltage
I/O ports
with TTL buffer
with Schmitt Trigger buffer
MCLR, OSC1 (RC mode)
OSC1 (XT and LP modes)
OSC1 (HS mode)
DATAASK, DATAFSK, RFEN
Input High Voltage
I/O ports
with TTL buffer
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Min
Typ†
Max
Units
VSS
VSS
VSS
VSS
VSS
VSS
VSS
—
0.8
0.15 VDD
0.2 VDD
0.2 VDD
0.3
0.3 VDD
0.3 VDDRF
V
V
V
V
V
V
V
4.5V ≤ VDD ≤ 5.5V
Otherwise
Entire range
V
V
4.5V ≤ VDD ≤ 5.5V
otherwise
entire range
250
1.5
2.0
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDRF
400*
12*
20*
V
V
V
V
V
µA
µA
µA
—
± 0.1
±1
µA
—
—
± 0.1
± 0.1
± 0.1
± 0.1
±1
±1
±5
±5
µA
µA
µA
µA
Output Low Voltage
I/O ports
OSC2/CLKOUT (RC mode)
—
—
—
—
0.6
0.6
V
V
IOL = 8.5 mA, VDD = 4.5V (Ind.)
IOL = 1.6 mA, VDD = 4.5V (Ind.)
IOL = 1.2 mA, VDD = 4.5V (Ext.)
Output High Voltage
I/O ports
OSC2/CLKOUT (RC mode)
VDD - 0.7
VDD - 0.7
—
—
—
—
V
V
IOH = -3.0 mA, VDD = 4.5V (Ind.)
IOH = -1.3 mA, VDD = 4.5V (Ind.)
IOH = -1.0 mA, VDD = 4.5V (Ext.)
—
—
—
—
—
(Note 1)
(Note 1)
—
2.0
(0.25 VDD+0.8)
with Schmitt Trigger buffer
0.8 VDD
MCLR
0.8 VDD
OSC1 (XT and LP modes)
1.6
OSC1 (HS mode)
0.7 VDD
OSC1 (RC mode)
0.9 VDD
DATAASK, DATAFSK, RFEN
0.7 VDD
GPIO Weak Pull-up Current
50*
DATAASK Weak Pull-up
0.1*
RFENIN Weak Pull-down
0.2*
Input Leakage Current(3)
GPIO ports, DATAASK,
DATAFSK, RFEN
Analog inputs
VREF
MCLR(2)
OSC1
—
Conditions
—
—
—
—
—
—
—
—
—
—
(Note 1)
(Note 1)
VDD = 5.0V, VPIN = VSS
VDDRF = RFEN = 3.0V
VDDRF = RFEN = 3.0V
VSS ≤ VPIN ≤ VDD,
Pin at hi-impedance
VSS ≤ VPIN ≤ VDD
VSS ≤ VPIN ≤ VDD
VSS ≤ VPIN ≤ VDD
VSS ≤ VPIN ≤ VDD, XT, HS and
LP osc configuration
These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
*
Note 1: In RC oscillator configuration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended to use
an external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS70091A-page 96
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
13.10 DC Characteristics: rfPIC12F675-I (Industrial), rfPIC12F675-E (Extended) (Cont.)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
DC CHARACTERISTICS
Param
No.
Sym
Characteristic
Capacitive Loading Specs
on Output Pins
OSC2 pin
Min
Typ†
Max
Units
Conditions
—
—
15*
pF
In XT, HS and LP modes when
external clock is used to drive
OSC1
—
—
50*
pF
100K
10K
VMIN
1M
100K
—
—
—
5.5
D100
COSC2
D101
CIO
D120
D120A
D121
ED
ED
VDRW
D122
D123
TDEW Erase/Write cycle time
TRETD Characteristic Retention
—
40
5
—
6
—
D124
TREF
1M
10M
—
D130
D130A
D131
EP
ED
VPR
10K
1K
VMIN
100K
10K
—
—
—
5.5
D132
D133
D134
VPEW VDD for Erase/Write
TPEW Erase/Write cycle time
TRETD Characteristic Retention
4.5
—
40
—
2
—
5.5
2.5
—
—
1
20
—
60
—
D150
D151
RON
ROFF
VPS
All I/O pins
Data EEPROM Memory
Byte Endurance
Byte Endurance
VDD for Read/Write
Number of Total Erase/Write
Cycles before Refresh(1)
Program FLASH Memory
Cell Endurance
Cell Endurance
VDD for Read
RF Transmitter(2)
FSK Switch On resistance
FSK Switch Off resistance
RF Power Select
Voltage
E/W -40°C ≤ TA ≤ +85°C
E/W +85°C ≤ TA ≤ +125°C
V
Using EECON to read/write
VMIN = Minimum operating
voltage
ms
Year Provided no other specifications
are violated
E/W -40°C ≤ TA ≤ +85°C
E/W -40°C ≤ TA ≤ +85°C
E/W +85°C ≤ TA ≤ +125°C
V
VMIN = Minimum operating
voltage
V
ms
Year Provided no other specifications
are violated
Ω
MΩ
DATAFSK=0, RFEN=1
DATAFSK=1, RFEN=1
D152A
VSSRF
V Power Level Step 0
0.1
—
D152B
0.14
V Power Level Step 1
0.24
—
D152C
0.28
V Power Level Step 2
0.51
—
D152D
V Power Level Step 3
1.18
—
0.57
D152E
V Power Level Step 4
VDDRF
—
1.23
D153
IPS
Power Select Current
6
8
11
µA RFEN=1
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: See Section 8.5.1 for additional information.
2: These limits are tested at room temperature.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 97
rfPIC12F675
13.11 TIMING PARAMETER SYMBOLOGY
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
FIGURE 13-4:
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
LOAD CONDITIONS
Load Condition 1
Load Condition 2
VDD/2
RL
CL
Pin
CL
Pin
VSS
VSS
RL = 464Ω
CL = 50 pF
15 pF
DS70091A-page 98
for all pins
for OSC2 output
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
13.12 AC CHARACTERISTICS: rfPIC12F675 (INDUSTRIAL, EXTENDED)
FIGURE 13-5:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
1
3
4
3
4
2
CLKOUT
TABLE 13-1:
Param
No.
Sym
FOSC
EXTERNAL CLOCK TIMING REQUIREMENTS
Characteristic
Min
Typ†
Max
Units
External CLKIN Frequency(1)
DC
DC
DC
DC
5
—
DC
0.1
1
—
—
—
—
—
4
—
—
—
37
4
20
20
37
—
4
4
20
kHz
MHz
MHz
MHz
kHz
MHz
MHz
MHz
MHz
LP Osc mode
XT mode
HS mode
EC mode
LP Osc mode
INTOSC mode
RC Osc mode
XT Osc mode
HS Osc mode
27
50
50
250
27
—
250
250
50
—
—
—
—
250
—
—
—
∞
∞
∞
∞
200
—
—
10,000
1,000
µs
ns
ns
ns
µs
ns
ns
ns
ns
LP Osc mode
HS Osc mode
EC Osc mode
XT Osc mode
LP Osc mode
INTOSC mode
RC Osc mode
XT Osc mode
HS Osc mode
200
2*
20*
TCY
—
—
DC
—
—
ns
µs
ns
TCY = 4/FOSC
LP oscillator, TOSC L/H duty cycle
HS oscillator, TOSC L/H duty
cycle
XT oscillator, TOSC L/H duty cycle
LP oscillator
XT oscillator
HS oscillator
Oscillator Frequency(1)
1
TOSC
External CLKIN Period(1)
Oscillator Period(1)
2
TCY
3
TosL,
TosH
4
Instruction Cycle Time(1)
External CLKIN (OSC1) High
External CLKIN Low
Conditions
100 *
—
—
ns
—
—
50*
ns
—
—
25*
ns
—
—
15*
ns
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
TosR,
TosF
External CLKIN Rise
External CLKIN Fall
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at ‘min’ values with an external
clock applied to OSC1 pin. When an external clock input is used, the ‘max’ cycle time limit is ‘DC’ (no clock)
for all devices.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 99
rfPIC12F675
TABLE 13-2:
Param
No.
F10
F14
Sym
PRECISION INTERNAL OSCILLATOR PARAMETERS
Characteristic
FOSC Internal Calibrated
INTOSC Frequency
Freq
Min
Tolerance
Typ†
Max
Units
MHz VDD = 3.5V, 25°C
MHz 2.5V ≤ VDD ≤ 5.5V
0°C ≤ TA ≤ +85°C
MHz 2.0V ≤ VDD ≤ 5.5V
-40°C ≤ TA ≤ +85°C (IND)
-40°C ≤ TA ≤ +125°C (EXT)
µs VDD = 2.0V, -40°C to +85°C
µs VDD = 3.0V, -40°C to +85°C
µs VDD = 5.0V, -40°C to +85°C
±1
±2
3.96
3.92
4.00
4.00
4.04
4.08
±5
3.80
4.00
4.20
—
—
—
—
SLEEP start-up time*
—
—
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise
only and are not tested.
6
4
3
TIOSC Oscillator Wake-up from
ST
DS70091A-page 100
8
6
5
Conditions
stated. These parameters are for design guidance
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
FIGURE 13-6:
CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
22
23
CLKOUT
13
12
19
14
18
16
I/O pin
(Input)
15
17
I/O pin
(Output)
New Value
Old Value
20, 21
TABLE 13-3:
Param
No.
CLKOUT AND I/O TIMING REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
10
TosH2ckL OSC1↑ to CLKOUT↓
—
75
200
ns
(Note 1)
11
TosH2ckH OSC1↑ to CLKOUT↑
—
75
200
ns
(Note 1)
12
TckR
CLKOUT rise time
—
35
100
ns
(Note 1)
13
TckF
CLKOUT fall time
—
35
100
ns
(Note 1)
14
TckL2ioV
CLKOUT↓ to Port out valid
—
—
20
ns
(Note 1)
15
TioV2ckH
Port in valid before CLKOUT↑
TOSC + 200
ns
—
—
ns
(Note 1)
16
TckH2ioI
Port in hold after CLKOUT↑
0
—
—
ns
(Note 1)
17
TosH2ioV
OSC1↑ (Q1 cycle) to Port out valid
—
50
150 *
ns
18
TosH2ioI
OSC1↑ (Q2 cycle) to Port input
invalid (I/O in hold time)
19
—
—
300
ns
100
—
—
ns
TioV2osH Port input valid to OSC1↑
(I/O in setup time)
0
—
—
ns
20
TioR
Port output rise time
—
10
40
ns
21
TioF
Port output fall time
—
10
40
ns
22
Tinp
INT pin high or low time
25
—
—
ns
Trbp
GPIO change INT high or low time
TCY
—
—
ns
23
*
†
These parameters are characterized but not tested.
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4xTOSC.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 101
rfPIC12F675
FIGURE 13-7:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
Reset
34
31
34
I/O Pins
FIGURE 13-8:
BROWN-OUT DETECT TIMING AND CHARACTERISTICS
VDD
BVDD
(Device not in Brown-out Detect)
(Device in Brown-out Detect)
35
RESET (due to BOD)
72 ms time-out(1)
Note 1: 72 ms delay only if PWRTE bit in configuration word is programmed to ‘0’.
DS70091A-page 102
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
TABLE 13-4:
Param
No.
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT DETECT REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
30
TMCL
MCLR Pulse Width (low)
2
TBD
—
TBD
—
TBD
µs
ms
VDD = 5V, -40°C to +85°C
Extended temperature
31
TWDT
Watchdog Timer Time-out
Period
(No Prescaler)
10
10
17
17
25
30
ms
ms
VDD = 5V, -40°C to +85°C
Extended temperature
32
TOST
Oscillation Start-up Timer
Period
—
1024TOSC
—
—
TOSC = OSC1 period
33*
TPWRT
Power-up Timer Period
28*
TBD
72
TBD
132*
TBD
ms
ms
VDD = 5V, -40°C to +85°C
Extended Temperature
34
TIOZ
I/O Hi-impedance from MCLR
Low or Watchdog Timer Reset
—
—
2.0
µs
BVDD
Brown-out Detect Voltage
2.025
—
2.175
V
Brown-out Hysteresis
TBD
—
—
—
Brown-out Detect Pulse Width
100*
—
—
µs
35
TBOD
VDD ≤ BVDD (D005)
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 103
rfPIC12F675
FIGURE 13-9:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
T0CKI
40
41
42
T1CKI
45
46
48
47
TMR0 or
TMR1
TABLE 13-5:
Param
No.
40*
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Sym
Tt0H
Characteristic
Min
T0CKI High Pulse Width
No Prescaler
0.5 TCY + 20
—
—
ns
With Prescaler
No Prescaler
10
0.5 TCY + 20
—
—
—
—
ns
ns
10
—
—
—
—
ns
ns
0.5 TCY + 20
15
—
—
—
—
ns
ns
30
0.5 TCY + 20
—
—
—
—
ns
ns
15
—
—
ns
41*
Tt0L
T0CKI Low Pulse Width
42*
Tt0P
T0CKI Period
45*
Tt1H
T1CKI High Time Synchronous, No Prescaler
With Prescaler
Greater of:
20 or TCY + 40
N
Synchronous,
with Prescaler
46*
Tt1L
T1CKI Low Time
Asynchronous
Synchronous, No Prescaler
Synchronous,
with Prescaler
47*
48
Asynchronous
30
—
—
ns
Synchronous
Greater of:
30 or TCY + 40
N
—
—
ns
Asynchronous
60
DC
—
—
—
200*
ns
kHz
2 TOSC*
—
7
TOSC*
—
Tt1P
T1CKI Input
Period
Ft1
Timer1 oscillator input frequency range
(oscillator enabled by setting bit T1OSCEN)
TCKEZtmr1 Delay from external clock edge to timer increment
*
†
Typ† Max Units
Conditions
N = prescale value
(2, 4, ..., 256)
N = prescale value
(1, 2, 4, 8)
These parameters are characterized but not tested.
Data in ‘Typ’ column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
DS70091A-page 104
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
TABLE 13-6:
COMPARATOR SPECIFICATIONS
Comparator Specifications
Sym
Characteristics
Standard Operating Conditions
-40°C to +125°C (unless otherwise stated)
Min
Typ
Max
Units
VOS
Input Offset Voltage
—
± 5.0
± 10
mV
VCM
Input Common Mode Voltage
0
—
VDD - 1.5
V
CMRR
Common Mode Rejection Ratio
+55*
—
—
db
TRT
Response Time(1)
—
150
400*
ns
TMC2COV Comparator Mode Change to
Output Valid
—
—
10*
µs
*
Comments
These parameters are characterized but not tested.
Note 1: Response time measured with one comparator input at (VDD - 1.5)/2 while the other input transitions from
VSS to VDD - 1.5V.
TABLE 13-7:
COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS
Voltage Reference Specifications
Sym
*
Characteristics
Standard Operating Conditions
-40°C to +125°C (unless otherwise stated)
Min
Typ
Max
Units
Comments
Resolution
—
—
VDD/24*
VDD/32
—
—
LSb
LSb
Low Range (VRR = 1)
High Range (VRR = 0)
Absolute Accuracy
—
—
—
—
± 1/2
± 1/2*
LSb
LSb
Low Range (VRR = 1)
High Range (VRR = 0)
Unit Resistor Value (R)
—
2k*
—
Ω
Settling Time(1)
—
—
10*
µs
These parameters are characterized but not tested.
Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 105
rfPIC12F675
TABLE 13-8:
Param
No.
rfPIC12F675 A/D CONVERTER CHARACTERISTICS:
Sym
Characteristic
Min
Typ†
Max
Units
bit
Conditions
A01
NR
Resolution
—
—
10 bits
A02
EABS
Total Absolute
Error*
—
—
±1
LSb VREF = 5.0V
A03
EIL
Integral Error
—
—
±1
LSb VREF = 5.0V
A04
EDL
Differential Error
—
—
±1
LSb No missing codes to 10 bits
VREF = 5.0V
A05
EFS
Full Scale Range
2.2*
—
5.5*
A06
EOFF
Offset Error
—
—
±1
LSb VREF = 5.0V
A07
EGN
Gain Error
—
—
±1
LSb VREF = 5.0V
(3)
A10
—
Monotonicity
—
A20
A20A
VREF
Reference Voltage
2.0
2.5
—
A21
VREF
Reference V High
(VDD or VREF)
VSS
A25
VAIN
Analog Input
Voltage
A30
ZAIN
A50
IREF
V
—
—
—
VDD + 0.3
V
—
VDD
V
VSS
—
VREF
V
Recommended
Impedance of
Analog Voltage
Source
—
—
10
kΩ
VREF Input
Current(2)
10
—
1000
µA
—
—
10
µA
guaranteed
VSS ≤ VAIN ≤ VREF+
Absolute minimum to ensure 10-bit
accuracy
During VAIN acquisition.
Based on differential of VHOLD to VAIN.
During A/D conversion cycle.
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: When A/D is off, it will not consume any current other than leakage current. The power-down current spec
includes any such leakage from the A/D module.
2: VREF current is from External VREF or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.
DS70091A-page 106
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
FIGURE 13-10:
rfPIC12F675 A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
134
1 TCY
(TOSC/2)(1)
131
Q4
130
A/D CLK
9
A/D DATA
8
7
6
3
2
1
0
NEW_DATA
OLD_DATA
ADRES
1 TCY
ADIF
GO
SAMPLE
DONE
SAMPLING STOPPED
132
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 13-9:
Param
No.
130
130
Sym
TAD
TAD
rfPIC12F675 A/D CONVERSION REQUIREMENTS
Characteristic
A/D Clock Period
A/D Internal RC
Oscillator Period
131
TCNV
Conversion Time
(not including
Acquisition Time)(1)
132
TACQ
Acquisition Time
134
TGO
Q4 to A/D Clock
Start
Min
Typ†
Max
Units
Conditions
1.6
—
—
µs
TOSC based, VREF ≥ 3.0V
3.0*
—
—
µs
TOSC based, VREF full range
3.0*
6.0
9.0*
µs
ADCS<1:0> = 11 (RC mode)
At VDD = 2.5V
2.0*
4.0
6.0*
µs
At VDD = 5.0V
—
11
—
TAD
Set GO bit to new data in A/D result
register
(Note 2)
11.5
—
µs
5*
—
—
µs
The minimum time is the amplifier
settling time. This may be used if the
“new” input voltage has not changed
by more than 1 LSb (i.e., 4.1 mV @
4.096V) from the last sampled
voltage (as stored on CHOLD).
—
TOSC/2
—
—
If the A/D clock source is selected as
RC, a time of TCY is added before
the A/D clock starts. This allows the
SLEEP instruction to be executed.
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 7.1 for minimum conditions.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 107
rfPIC12F675
FIGURE 13-11:
rfPIC12F675 A/D CONVERSION TIMING (SLEEP MODE)
BSF ADCON0, GO
134
(TOSC/2 + TCY)(1)
1 TCY
131
Q4
130
A/D CLK
9
A/D DATA
8
7
3
6
2
1
NEW_DATA
OLD_DATA
ADRES
0
ADIF
1 TCY
GO
DONE
SAMPLE
SAMPLING STOPPED
132
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 13-10: rfPIC12F675 A/D CONVERSION REQUIREMENTS (SLEEP MODE)
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
1.6
—
—
µs
VREF ≥ 3.0V
3.0*
—
—
µs
VREF full range
3.0*
6.0
9.0*
µs
ADCS<1:0> = 11 (RC mode)
At VDD = 2.5V
2.0*
4.0
6.0*
µs
At VDD = 5.0V
—
11
—
TAD
(Note 2)
11.5
—
µs
5*
—
—
µs
The minimum time is the amplifier
settling time. This may be used if
the “new” input voltage has not
changed by more than 1 LSb (i.e.,
4.1 mV @ 4.096V) from the last
sampled voltage (as stored on
CHOLD).
—
TOSC/2 + TCY
—
—
If the A/D clock source is selected
as RC, a time of TCY is added
before the A/D clock starts. This
allows the SLEEP instruction to be
executed.
130
TAD
A/D Clock Period
130
TAD
A/D Internal RC
Oscillator Period
131
TCNV
Conversion Time
(not including
Acquisition Time)(1)
132
TACQ
Acquisition Time
134
TGO
*
†
Q4 to A/D Clock
Start
Conditions
These parameters are characterized but not tested.
Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 7.1 for minimum conditions.
DS70091A-page 108
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
TABLE 13-11: rfPIC12F675K RF TRANSMITTER SPECIFICATIONS (315 MHz)
RF Transmitter Specifications
Sym
Characteristics
Standard Operating Conditions
TA = +23°C (unless otherwise stated)
VDDRF = 3.0V (unless otherwise stated)
FC = 315 MHz (unless otherwise stated)
Min
Typ
Max
Units
Comments
FC
VCO Frequency
290
—
350
MHz
32 x FRFXTAL
FXTAL
Crystal Frequency
9.06
—
10.94
MHz
Fundamental mode
FREF
Reference Frequency
2.265
—
2.735
MHz
FRFXTAL / 4
CL
Load Capacitance
10
—
15
pF
CO
Static Capacitance
—
—
7
pF
RS
Series Resistance
—
—
70
Ω
ASPUR
Spurious response
—
—
-10
dB
∆FVDD
Frequency Stability vs VDDRF
—
—
±3
ppm
For FSK operation
∆FTA
Frequency Stability vs Temp
—
—
±10
ppm
Crystal temp constant
∆F
FSK Deviation
±5
—
±80
kHz
Depends on crystal
parameters
RFSK
FSK Data Rate
—
—
40
Kbit/s
NRZ
NRZ
RASK
ASK Data Rate
—
—
40
Kbit/s
TON
RFEN High to Transmit
—
1.2
1.5
ms
POFF
RF Output Power in Step 0
—
—
-70
dBm
RFEN=1
P1
RF Output Power in Step 1
—
-12
—
dBm
RFEN=1
P2
RF Output Power in Step 2
—
-4
—
dBm
RFEN=1
P3
RF Output Power in Step 3
—
2
—
dBm
RFEN=1
P4
RF Output Power in Step 4
—
4
—
dBm
RFEN=1, VDDRF=2.0V
—
7.5
—
dBm
RFEN=1, VDDRF=3.0V
—
8.5
9.5
dBm
RFEN=1, VDDRF=4.0V
dBm
RFEN=1, VDDRF=5.0V
—
9.0
10.5
L(FM)
Phase Noise
—
-86
—
PSPUR
Spurious Emissions
—
—
-54
dBm
47 MHz < f < 74 MHZ
87.5 MHz < f < 118 MHZ
174 MHz < f < 230 MHZ
470 MHz < f < 862 MHZ
RBW = 100 kHz
—
—
-36
dBm
f < 1 GHZ
RBW = 100 kHz
—
—
-30
dBm
f > 1 GHZ
RBW = 1 MHz
 2003 Microchip Technology Inc.
Preliminary
dBc/Hz 200 kHz offset
DS70091A-page 109
rfPIC12F675
TABLE 13-12: rfPIC12F675F RF TRANSMITTER SPECIFICATIONS (434 MHz)
RF Transmitter Specifications
Sym
Characteristics
Standard Operating Conditions
TA = +23°C (unless otherwise stated)
VDDRF = 3.0V (unless otherwise stated)
FC = 433.92 MHz (unless otherwise stated)
Min
Typ
Max
Units
Comments
FC
VCO Frequency
380
—
450
MHz
32 x FRFXTAL
FXTAL
Crystal Frequency
11.88
—
14.06
MHz
Fundamental mode
FREF
Reference Frequency
2.97
—
3.515
MHz
FRFXTAL / 4
CL
Load Capacitance
10
—
15
pF
CO
Static Capacitance
—
—
7
pF
RS
Series Resistance
—
—
70
Ω
ASPUR
Spurious response
—
—
-10
dB
∆FVDD
Frequency Stability vs VDDRF
—
—
±3
ppm
For FSK operation
∆FTA
Frequency Stability vs Temp
—
—
±10
ppm
Crystal temp constant
∆F
FSK Deviation
±5
—
±80
kHz
Depends on crystal
parameters
RFSK
FSK Data Rate
—
—
40
Kbit/s
NRZ
NRZ
RASK
ASK Data Rate
—
—
40
Kbit/s
TON
RFEN High to Transmit
—
0.8
1.2
ms
POFF
RF Output Power in Step 0
—
—
-70
dBm
RFEN=1
P1
RF Output Power in Step 1
—
-12
—
dBm
RFEN=1
P2
RF Output Power in Step 2
—
-4
—
dBm
RFEN=1
P3
RF Output Power in Step 3
—
2
—
dBm
RFEN=1
P4
RF Output Power in Step 4
—
4
—
dBm
RFEN=1, VDDRF=2.0V
—
7.5
—
dBm
RFEN=1, VDDRF=3.0V
—
8.5
9.5
dBm
RFEN=1, VDDRF=4.0V
dBm
RFEN=1, VDDRF=5.0V
—
9.0
10.5
L(FM)
Phase Noise
—
-86
—
PSPUR
Spurious Emissions
—
—
-54
dBm
47 MHz < f < 74 MHZ
87.5 MHz < f < 118 MHZ
174 MHz < f < 230 MHZ
470 MHz < f < 862 MHZ
RBW = 100 kHz
—
—
-36
dBm
f < 1 GHZ
RBW = 100 kHz
—
—
-30
dBm
f > 1 GHZ
RBW = 1 MHz
DS70091A-page 110
Preliminary
dBc/Hz 200 kHz offset
 2003 Microchip Technology Inc.
rfPIC12F675
TABLE 13-13: rfPIC12F675H RF TRANSMITTER SPECIFICATIONS (868/915 MHz)
RF Transmitter Specifications
Sym
Characteristics
Standard Operating Conditions
TA = +23°C (unless otherwise stated)
VDDRF = 3.0V (unless otherwise stated)
FC = 868.3 MHz (unless otherwise stated)
Min
Typ
Max
Units
Comments
FC
VCO Frequency
850
—
930
MHz
32 x FRFXTAL
FXTAL
Crystal Frequency
26.56
—
29.06
MHz
Fundamental mode
FREF
Reference Frequency
3.32
—
3.63
MHz
FRFXTAL / 8
CL
Load Capacitance
10
—
15
pF
CO
Static Capacitance
—
—
7
pF
RS
Series Resistance
—
—
50
Ω
ASPUR
Spurious response
—
—
-10
dB
∆FVDD
Frequency Stability vs VDDRF
—
—
±3
ppm
For FSK operation
∆FTA
Frequency Stability vs Temp
—
—
±10
ppm
Crystal temp constant
∆F
FSK Deviation
±5
—
±80
kHz
Depends on crystal
parameters
RFSK
FSK Data Rate
—
—
40
Kbit/s
NRZ
NRZ
RASK
ASK Data Rate
—
—
40
Kbit/s
TON
RFEN High to Transmit
—
0.6
1.0
ms
POFF
RF Output Power in Step 0
—
—
-70
dBm
RFEN=1
P1
RF Output Power in Step 1
—
-12
—
dBm
RFEN=1
P2
RF Output Power in Step 2
—
-4
—
dBm
RFEN=1
P3
RF Output Power in Step 3
—
2
—
dBm
RFEN=1
P4
RF Output Power in Step 4
—
4
—
dBm
RFEN=1, VDDRF=2.0V
—
7.5
—
dBm
RFEN=1, VDDRF=3.0V
—
8.5
9.5
dBm
RFEN=1, VDDRF=4.0V
dBm
RFEN=1, VDDRF=5.0V
—
9.0
10.5
L(FM)
Phase Noise
—
-82
—
PSPUR
Spurious Emissions
—
—
-54
dBm
47 MHz < f < 74 MHZ
87.5 MHz < f < 118 MHZ
174 MHz < f < 230 MHZ
470 MHz < f < 862 MHZ
RBW = 100 kHz
—
—
-36
dBm
f < 1 GHZ
RBW = 100 kHz
—
—
-30
dBm
f > 1 GHZ
RBW = 1 MHz
 2003 Microchip Technology Inc.
Preliminary
dBc/Hz 200 kHz offset
DS70091A-page 111
rfPIC12F675
NOTES:
DS70091A-page 112
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
14.0
DC AND AC CHARACTERISTICS GRAPHS AND TABLES
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD
range). This is for information only and devices are ensured to operate properly only within the specified range.
The data presented in this section is a statistical summary of data collected on units from different lots over a period
of time and matrix samples. 'Typical' represents the mean of the distribution at 25°C. 'Max' or 'min' represents
(mean + 3σ) or (mean - 3σ) respectively, where σ is standard deviation, over the whole temperature range.
FIGURE 14-1:
TYPICAL IPD vs. VDD OVER TEMP (-40°C TO +25°C)
Typical Baseline IPD
6.0E-09
5.0E-09
IPD (A)
4.0E-09
-40
3.0E-09
0
25
2.0E-09
1.0E-09
0.0E+00
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
FIGURE 14-2:
TYPICAL IPD vs. VDD OVER TEMP (+85°C)
Typical Baseline IPD
3.5E-07
3.0E-07
IPD (A)
2.5E-07
2.0E-07
85
1.5E-07
1.0E-07
5.0E-08
0.0E+00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 113
rfPIC12F675
FIGURE 14-3:
TYPICAL IPD vs. VDD OVER TEMP (+125°C)
Typical Baseline IPD
4.0E-06
3.5E-06
IPD (A)
3.0E-06
2.5E-06
125
2.0E-06
1.5E-06
1.0E-06
5.0E-07
0.0E+00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 14-4:
MAXIMUM IPD vs. VDD OVER TEMP (-40°C TO +25°C)
Maximum Baseline IPD
1.0E-07
9.0E-08
IPD (A)
8.0E-08
7.0E-08
6.0E-08
-40
5.0E-08
0
4.0E-08
25
3.0E-08
2.0E-08
1.0E-08
0.0E+00
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
DS70091A-page 114
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
FIGURE 14-5:
MAXIMUM IPD vs. VDD OVER TEMP (+85°C)
Maximum Baseline IPD
9.0E-07
8.0E-07
IPD (A)
7.0E-07
6.0E-07
5.0E-07
4.0E-07
85
3.0E-07
2.0E-07
1.0E-07
0.0E+00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
FIGURE 14-6:
MAXIMUM IPD vs. VDD OVER TEMP (+125°C)
Maximum Baseline IPD
9.0E-06
8.0E-06
7.0E-06
IPD (A)
6.0E-06
5.0E-06
125
4.0E-06
3.0E-06
2.0E-06
1.0E-06
0.0E+00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 115
rfPIC12F675
FIGURE 14-7:
TYPICAL IPD WITH BOD ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)
Typical BOD IPD
130
120
110
IPD (uA)
-40
100
0
90
25
80
85
125
70
60
50
3
3.5
4
4.5
5
5.5
VDD(V)
FIGURE 14-8:
TYPICAL IPD WITH CMP ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)
Typical Comparator IPD
1.8E-05
1.6E-05
1.4E-05
-40
IPD (A)
1.2E-05
0
1.0E-05
25
8.0E-06
85
6.0E-06
125
4.0E-06
2.0E-06
0.0E+00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS70091A-page 116
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
FIGURE 14-9:
TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (-40°C TO +25°C)
IPD (A)
Typical A/D IPD
5.0E-09
4.5E-09
4.0E-09
3.5E-09
3.0E-09
2.5E-09
2.0E-09
1.5E-09
1.0E-09
5.0E-10
0.0E+00
-40
0
25
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
FIGURE 14-10:
TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+85°C)
Typical A/D IPD
3.5E-07
3.0E-07
IPD (A)
2.5E-07
2.0E-07
85
1.5E-07
1.0E-07
5.0E-08
0.0E+00
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 117
rfPIC12F675
FIGURE 14-11:
TYPICAL IPD WITH A/D ENABLED vs. VDD OVER TEMP (+125°C)
Typical A/D IPD
3.5E-06
IPD (A)
3.0E-06
2.5E-06
2.0E-06
125
1.5E-06
1.0E-06
5.0E-07
0.0E+00
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
FIGURE 14-12:
TYPICAL IPD WITH T1 OSC ENABLED vs. VDD OVER TEMP (-40°C TO +125°C),
32 KHZ, C1 AND C2=50 pF)
Typical T1 IPD
1.20E-05
1.00E-05
-40
IPD (A)
8.00E-06
0
25
6.00E-06
85
4.00E-06
125
2.00E-06
0.00E+00
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
DS70091A-page 118
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
FIGURE 14-13:
TYPICAL IPD WITH CVREF ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)
Typical CVREF IPD
160
140
IPD (uA)
-40
120
0
25
100
85
80
125
60
40
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
FIGURE 14-14:
TYPICAL IPD WITH WDT ENABLED vs. VDD OVER TEMP (-40°C TO +125°C)
Typical WDT IPD
16
IPD (uA)
14
12
-40
10
0
8
25
6
85
4
125
2
0
2
2.5
3
3.5
4
4.5
5
5.5
VDD (V)
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 119
rfPIC12F675
FIGURE 14-15:
MAXIMUM AND MINIMUM INTOSC FREQ vs. TEMPERATURE WITH 0.1µF AND
0.01µF DECOUPLING (VDD = 3.5V)
Internal Oscillator
Frequency vs Temperature
4.20E+06
Frequency (Hz)
4.15E+06
4.10E+06
4.05E+06
-3sigma
4.00E+06
average
3.95E+06
+3sigma
3.90E+06
3.85E+06
3.80E+06
-40°C
0°C
25°C
85°C
125°C
Temperature (°C)
FIGURE 14-16:
MAXIMUM AND MINIMUM INTOSC FREQ vs. VDD WITH 0.1µF AND 0.01µF
DECOUPLING (+25°C)
Internal Oscillator
Frequency vs VDD
Frequency (Hz)
4.20E+06
4.15E+06
4.10E+06
4.05E+06
4.00E+06
-3sigma
3.95E+06
3.90E+06
+3sigma
average
3.85E+06
3.80E+06
2.0V
2.5V
3.0V
3.5V
4.0V
4.5V
5.0V
5.5V
VDD (V)
DS70091A-page 120
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
FIGURE 14-17:
TYPICAL WDT PERIOD vs. VDD (-40°C TO +125°C)
WDT Time-out
Time (mS)
50
45
40
35
-40
30
25
0
20
15
10
5
85
25
125
0
2
2.5
3
3.5
4
4.5
5
5.5
V DD (V)
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 121
rfPIC12F675
NOTES:
DS70091A-page 122
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
15.0
PACKAGING INFORMATION
15.1
Package Marking Information
20-Lead SSOP
Example
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Legend:
Note:
*
XX...X
Y
YY
WW
NNN
rfPIC™
12F675H
0314CBP
Customer specific information*
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 123
rfPIC12F675
Package Type: 20-Lead SSOP
20-Lead Plastic Shrink Small Outline (SS) - 209 mil, 5.30 mm (SSOP)
E
E1
p
D
B
2
1
n
α
c
A2
A
φ
L
A1
β
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Foot Length
Lead Thickness
Foot Angle
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
A
A2
A1
E
E1
D
L
c
φ
B
α
β
MIN
.068
.064
.002
.299
.201
.278
.022
.004
0
.010
0
0
INCHES*
NOM
20
.026
.073
.068
.006
.309
.207
.284
.030
.007
4
.013
5
5
MAX
.078
.072
.010
.322
.212
.289
.037
.010
8
.015
10
10
MILLIMETERS
NOM
20
0.65
1.73
1.85
1.63
1.73
0.05
0.15
7.59
7.85
5.11
5.25
7.06
7.20
0.56
0.75
0.10
0.18
0.00
101.60
0.25
0.32
0
5
0
5
MIN
MAX
1.98
1.83
0.25
8.18
5.38
7.34
0.94
0.25
203.20
0.38
10
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072
DS70091A-page 124
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
APPENDIX A:
DATA SHEET
REVISION HISTORY
Revision A
This is a new data sheet.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 125
rfPIC12F675
NOTES:
DS70091A-page 126
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
INDEX
A
A/D ...................................................................................... 39
Acquisition Requirements ........................................... 43
Block Diagram............................................................. 39
Calculating Acquisition Time....................................... 43
Configuration and Operation....................................... 39
Effects of a RESET ..................................................... 44
Internal Sampling Switch (Rss) Impedance ................ 43
Operation During SLEEP ............................................ 44
PIC12F675 Converter Characteristics ...................... 106
Source Impedance...................................................... 43
Summary of Registers ................................................ 44
Absolute Maximum Ratings ................................................ 87
AC Characteristics
Industrial and Extended .............................................. 99
Additional Pin Functions ..................................................... 17
Interrupt-on-Change.................................................... 19
Weak Pull-up............................................................... 17
Analog Input Connection Considerations............................ 36
Analog-to-Digital Converter. See A/D
Assembler
MPASM Assembler..................................................... 81
B
Block Diagram
TMR0/WDT Prescaler................................................. 25
Block Diagrams
Analog Input Mode...................................................... 36
Analog Input Model ..................................................... 43
Comparator Output ..................................................... 36
Comparator Voltage Reference .................................. 37
GP0 and GP1 Pins...................................................... 20
GP2............................................................................. 21
GP3............................................................................. 21
GP4............................................................................. 22
GP5............................................................................. 22
On-Chip Reset Circuit ................................................. 59
RC Oscillator Mode..................................................... 58
Timer1......................................................................... 28
Watchdog Timer.......................................................... 69
Brown-out
Associated Registers .................................................. 62
Brown-out Detect (BOD) ..................................................... 61
Brown-out Detect Timing and Characteristics................... 102
Operation.................................................................... 34
Operation During SLEEP............................................ 37
Output......................................................................... 36
Reference ................................................................... 37
Response Time .......................................................... 37
Comparator Specifications................ 105, 108, 109, 110, 111
Comparator Voltage Reference Specifications................. 105
Configuration Bits ............................................................... 56
Configuring the Voltage Reference..................................... 37
Crystal Operation................................................................ 57
Crystal Oscillator................................................................. 50
D
Data EEPROM Memory
Associated Registers/Bits........................................... 48
Code Protection.......................................................... 48
EEADR Register......................................................... 45
EECON1 Register ...................................................... 45
EECON2 Register ...................................................... 45
EEDATA Register....................................................... 45
Data Memory Organization................................................... 5
DC Characteristics
Extended and Industrial.............................................. 96
Industrial ..................................................................... 90
Demonstration Boards
PICDEM 1................................................................... 84
PICDEM 17................................................................. 84
PICDEM 18R PIC18C601/801 ................................... 85
PICDEM 2 Plus........................................................... 84
PICDEM 3 PIC16C92X............................................... 84
PICDEM 4................................................................... 84
PICDEM LIN PIC16C43X ........................................... 85
PICDEM USB PIC16C7X5 ......................................... 85
PICDEM.net Internet/Ethernet.................................... 84
Development Support ......................................................... 81
Device Overview................................................................... 3
E
EEPROM Data Memory
Reading ...................................................................... 47
Spurious Write ............................................................ 47
Write Verify ................................................................. 47
Writing ........................................................................ 47
Electrical Specifications ...................................................... 87
Errata .................................................................................... 2
Evaluation and Programming Tools.................................... 85
C
F
C Compilers
MPLAB C17 ................................................................ 82
MPLAB C18 ................................................................ 82
MPLAB C30 ................................................................ 82
Calibrated Internal RC Frequencies.................................. 100
CLKOUT ............................................................................. 58
Code Examples
Changing Prescaler .................................................... 27
Data EEPROM Read .................................................. 47
Data EEPROM Write .................................................. 47
Initializing GPIO .......................................................... 17
Saving STATUS and W Registers in RAM ................. 68
Write Verify ................................................................. 47
Code Protection .................................................................. 69
Comparator ......................................................................... 33
Associated Registers .................................................. 38
Configuration............................................................... 35
Effects of a RESET ..................................................... 37
I/O Operating Modes................................................... 35
Interrupts..................................................................... 38
Firmware Instructions ......................................................... 73
 2003 Microchip Technology Inc.
G
General Purpose Register File ............................................. 5
GPIO
Associated Registers.................................................. 23
GPIO Port ........................................................................... 17
GPIO, TRISIO Registers..................................................... 17
I
ID Locations........................................................................ 69
In-Circuit Debugger............................................................. 71
In-Circuit Serial Programming............................................. 71
Indirect Addressing, INDF and FSR Registers ................... 16
Instruction Format............................................................... 73
Instruction Set..................................................................... 73
ADDLW....................................................................... 75
ADDWF ...................................................................... 75
ANDLW....................................................................... 75
ANDWF ...................................................................... 75
BCF ............................................................................ 75
Preliminary
DS70091A-page 127
rfPIC12F675
BSF ............................................................................. 75
BTFSC ........................................................................ 75
BTFSS ........................................................................ 75
CALL ........................................................................... 76
CLRF........................................................................... 76
CLRW ......................................................................... 76
CLRWDT..................................................................... 76
COMF ......................................................................... 76
DECF .......................................................................... 76
DECFSZ...................................................................... 77
GOTO ......................................................................... 77
INCF............................................................................ 77
INCFSZ ....................................................................... 77
IORLW ........................................................................ 77
IORWF ........................................................................ 77
MOVF.......................................................................... 78
MOVLW ...................................................................... 78
MOVWF ...................................................................... 78
NOP ............................................................................ 78
RETFIE ....................................................................... 78
RETLW ....................................................................... 78
RETURN ..................................................................... 79
RLF ............................................................................. 79
RRF............................................................................. 79
SLEEP ........................................................................ 79
SUBLW ....................................................................... 79
SUBWF ....................................................................... 79
SWAPF ....................................................................... 80
XORLW ....................................................................... 80
XORWF....................................................................... 80
Summary Table........................................................... 74
Internal 4 MHz Oscillator..................................................... 58
Internal Sampling Switch (Rss) Impedance ........................ 43
Interrupts ............................................................................. 65
A/D Converter ............................................................. 67
Comparator ................................................................. 67
Context Saving............................................................ 68
GP2/INT ...................................................................... 67
GPIO ........................................................................... 67
Summary of Registers ................................................ 68
TMR0 .......................................................................... 67
M
MCLR .................................................................................. 60
Memory Organization
Data EEPROM Memory .............................................. 45
Mode Control Logic ............................................................. 54
MPLAB ASM30 Assembler, Linker, Librarian ..................... 82
MPLAB ICD 2 In-Circuit Debugger...................................... 83
MPLAB ICE 2000 High Performance Universal
In-Circuit Emulator .............................................................. 83
MPLAB ICE 4000 High Performance Universal
In-Circuit Emulator .............................................................. 83
MPLAB Integrated Development Environment
Software .............................................................................. 81
MPLINK Object Linker/MPLIB Object Librarian .................. 82
O
OPCODE Field Descriptions ............................................... 73
Oscillator Configurations ..................................................... 57
Oscillator Start-up Timer (OST) .......................................... 60
P
Package Marking Information ........................................... 123
Packaging Information ...................................................... 123
PCL and PCLATH ............................................................... 15
Computed GOTO ........................................................ 15
Stack ........................................................................... 15
DS70091A-page 128
Phase-Locked Loop (PLL) .................................................. 53
PICkit 1 FLASH Starter Kit.................................................. 85
PICSTART Plus Development Programmer....................... 83
Pin Descriptions and Diagrams .......................................... 20
Power Amplifier................................................................... 53
Power Control/Status Register (PCON).............................. 61
Power Select (Table) .......................................................... 53
Power-Down Mode (SLEEP) .............................................. 70
Power-on Reset (POR)....................................................... 60
Power-up Timer (PWRT) .................................................... 60
Prescaler............................................................................. 27
Switching Prescaler Assignment ................................ 27
PRO MATE II Universal Device Programmer ..................... 83
Program Memory Organization............................................. 5
Programming, Device Instructions...................................... 73
R
RC Oscillator....................................................................... 58
READ-MODIFY-WRITE OPERATIONS ............................. 73
Registers
ADCON0 (A/D Control)............................................... 41
ANSEL (Analog Select) .............................................. 42
CMCON (Comparator Control) ................................... 33
CONFIG (Configuration Word) ................................... 56
EEADR (EEPROM Address) ...................................... 45
EECON1 (EEPROM Control) ..................................... 46
EEDAT (EEPROM Data) ............................................ 45
INTCON (Interrupt Control)......................................... 11
IOCB (Interrupt-on-Change GPIO) ............................. 19
Maps
PIC12F629 ........................................................... 6
PIC12F675 ........................................................... 6
OPTION_REG (Option) ........................................ 10, 26
OSCCAL (Oscillator Calibration) ................................ 14
PCON (Power Control) ............................................... 14
PIE1 (Peripheral Interrupt Enable 1)........................... 12
PIR1 (Peripheral Interrupt 1)....................................... 13
STATUS ....................................................................... 9
T1CON (Timer1 Control) ............................................ 30
VRCON (Voltage Reference Control) ......................... 38
WPU (Weak Pull-up)................................................... 18
RESET................................................................................ 59
Revision History................................................................ 125
S
Software Simulator (MPLAB SIM) ...................................... 82
Software Simulator (MPLAB SIM30) .................................. 82
Special Features of the CPU .............................................. 55
Special Function Registers ................................................... 6
Special Functions Registers Summary................................. 7
T
Time-out Sequence ............................................................ 61
Timer0................................................................................. 25
Associated Registers .................................................. 27
External Clock............................................................. 26
Interrupt ...................................................................... 25
Operation .................................................................... 25
T0CKI ......................................................................... 26
Timer1
Associated Registers .................................................. 31
Asynchronous Counter Mode ..................................... 31
Reading and Writing ........................................... 31
Interrupt ...................................................................... 29
Modes of Operations .................................................. 29
Operation During SLEEP............................................ 31
Oscillator..................................................................... 31
Prescaler .................................................................... 29
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
Timer1 Module with Gate Control ....................................... 28
Timing Diagrams
CLKOUT and I/O....................................................... 101
External Clock............................................................. 99
INT Pin Interrupt.......................................................... 67
PIC12F675 A/D Conversion (Normal Mode)............. 107
PIC12F675 A/D Conversion Timing
(SLEEP Mode) .......................................................... 108
RESET, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer ....................................... 102
Time-out Sequence on Power-up (MCLR not Tied to
VDD)/
Case 1 ................................................................ 64
Case 2 ................................................................ 64
Time-out Sequence on Power-up (MCLR Tied
to VDD) ........................................................................ 64
Timer0 and Timer1 External Clock ........................... 104
Timer1 Incrementing Edge.......................................... 29
Timing Parameter Symbology............................................. 98
U
UHF ASK/FSK Transmitter
CEPT .......................................................................... 49
FCC............................................................................. 49
Radio Frequency......................................................... 49
Transmitter.................................................................. 49
V
Voltage Reference Accuracy/Error ..................................... 37
W
Watchdog Timer
Summary of Registers ................................................ 69
Watchdog Timer (WDT) ...................................................... 68
WWW, On-Line Support ....................................................... 2
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 129
rfPIC12F675
NOTES:
DS70091A-page 130
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape® or Microsoft®
Internet Explorer. Files are also available for FTP
download from our FTP site.
Connecting to the Microchip Internet Web Site
SYSTEMS INFORMATION AND
UPGRADE HOT LINE
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive the most current upgrade kits.The Hot Line
Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
The Microchip web site is available at the following
URL:
092002
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A
variety of Microchip specific business information is
also available, including listings of Microchip sales
offices, distributors and factory representatives. Other
data available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 131
rfPIC12F675
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
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Would you like a reply?
Device: rfPIC12F675
Y
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Literature Number: DS70091A
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
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6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS70091A-page 132
Preliminary
 2003 Microchip Technology Inc.
rfPIC12F675
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
Temperature
Range
/XX
XXX
Package
Pattern
Device
: Standard VDD range
T: (Tape and Reel)
Temperature Range
I
E
Package
SS
Pattern
3-Digit Pattern Code for QTP (blank otherwise)
=
=
Examples:
a)
rfPIC12F675F – E/SS 301 = Extended Temp.,
SSOP package, 434 MHz, QTP pattern #301
b)
rfPIC12F675HT – I/SS = Industrial Temp.,
SSOP package, 868 MHz, Tape and Reel
-40°C to +85°C
-40°C to +125°C
=
SSOP
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
 2003 Microchip Technology Inc.
Preliminary
DS70091A-page 133
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
Japan
Corporate Office
Australia
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Microchip Technology Australia Pty Ltd
Marketing Support Division
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Microchip Technology Japan K.K.
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Tel: 81-45-471- 6166 Fax: 81-45-471-6122
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China - Beijing
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848 Fax: 978-692-3821
Microchip Technology Consulting (Shanghai)
Co., Ltd., Beijing Liaison Office
Unit 915
Bei Hai Wan Tai Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100 Fax: 86-10-85282104
Chicago
China - Chengdu
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
Microchip Technology Consulting (Shanghai)
Co., Ltd., Chengdu Liaison Office
Rm. 2401-2402, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: 86-28-86766200 Fax: 86-28-86766599
Boston
Dallas
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423 Fax: 972-818-2924
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Kokomo
2767 S. Albright Road
Kokomo, Indiana 46902
Tel: 765-864-8360 Fax: 765-864-8387
Los Angeles
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
Phoenix
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966 Fax: 480-792-4338
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
China - Fuzhou
Microchip Technology Consulting (Shanghai)
Co., Ltd., Fuzhou Liaison Office
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Fuzhou 350001, China
Tel: 86-591-7503506 Fax: 86-591-7503521
China - Hong Kong SAR
Microchip Technology Hongkong Ltd.
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
China - Shanghai
Microchip Technology Consulting (Shanghai)
Co., Ltd.
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
China - Shenzhen
Microchip Technology Consulting (Shanghai)
Co., Ltd., Shenzhen Liaison Office
Rm. 1812, 18/F, Building A, United Plaza
No. 5022 Binhe Road, Futian District
Shenzhen 518033, China
Tel: 86-755-82901380 Fax: 86-755-82966626
China - Qingdao
Rm. B505A, Fullhope Plaza,
No. 12 Hong Kong Central Rd.
Qingdao 266071, China
Tel: 86-532-5027355 Fax: 86-532-5027205
India
Microchip Technology Inc.
India Liaison Office
Marketing Support Division
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Microchip Technology (Barbados) Inc.,
Taiwan Branch
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Austria
Microchip Technology Austria GmbH
Durisolstrasse 2
A-4600 Wels
Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
Microchip Technology Nordic ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
France
Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Microchip Technology GmbH
Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy
Microchip Technology SRL
Via Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
Tel: 39-0331-742611 Fax: 39-0331-466781
United Kingdom
Microchip Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
03/25/03
DS70091A-page 134
Preliminary
 2003 Microchip Technology Inc.
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