K8D3216UBC

K8D3216UBC
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
Document Title
32M Bit (4M x8/2M x16) Dual Bank NOR Flash Memory
Revision History
Revision No. History
Draft Date
Remark
Preliminary
0.0
Initial Draft
June 18, 2002
1.0
Final Specification
November 13, 2002
1.1
Not support 48TSOP1 Package
Not support 16M/16M BANK partition
November 18, 2003 Final
1.2
Support 48TSOP1 Package
July 16, 2004
1.3
Support 48TSOP1 Lead Free Package
1.4
Support 48FBGA Leaded/Lead Free Package
September 16,
2004
March 16, 2005
1.5
Complement status flag check algorithm
June 2, 2005
1
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
32M Bit (4M x8/2M x16) Dual Bank NOR Flash Memory
FEATURES
GENERAL DESCRIPTION
• Single Voltage, 2.7V to 3.6V for Read and Write operations
• Organization
4,194,304 x 8 bit (Byte mode) / 2,097,152 x 16 bit (Word mode)
• Fast Read Access Time : 70ns
• Read While Program/Erase Operation
• Dual Bank architectures
Bank 1 / Bank 2 : 8Mb / 24Mb
• Secode(Security Code) Block : Extra 64K Byte block
• Power Consumption (typical value @5MHz)
- Read Current : 14mA
- Program/Erase Current : 15mA
- Read While Program or Read While Erase Current : 25mA
- Standby Mode/Auto Sleep Mode : 5µA
• WP/ACC input pin
- Allows special protection of two outermost boot blocks at VIL,
regardless of block protect status
- Removes special protection of two outermost boot block at VIH,
the two blocks return to normal block protect status
- Program time at VHH : 9µs/word
• Erase Suspend/Resume
• Unlock Bypass Program
• Hardware RESET Pin
• Command Register Operation
• Block Group Protection / Unprotection
• Supports Common Flash Memory Interface
• Industrial Temperature : -40°C to 85°C
• Endurance : 100,000 Program/Erase Cycles Minimum
• Data Retention : 10 years
• Package : 48 Pin TSOP1 : 12 x 20 mm / 0.5 mm Pin pitch
48 Ball TBGA : 6 x 8.5 mm / 0.8 mm Ball pitch
48 Ball FBGA : 6 x 8.5 mm / 0.8 mm Ball pitch
The K8D3216U featuring single 3.0V power supply, is a 32Mbit
NOR-type Flash Memory organized as 4Mx8 or 2M x16. The
memory architecture of the device is designed to divide its
memory arrays into 71 blocks to be protected by the block
group. This block architecture provides highly flexible erase and
program capability. The K8D3216U NOR Flash consists of two
banks. This device is capable of reading data from one bank
while programming or erasing in the other bank. Access times
of 70ns, 80ns and 90ns are available for the device. The
device′s fast access times allow high speed microprocessors to
operate without wait states. The device performs a program
operation in units of 8 bits (Byte) or 16 bits (Word) and erases in
units of a block. Single or multiple blocks can be erased. The
block erase operation is completed within typically 0.7 sec. The
device requires 15mA as program/erase current in the standard
and industrial temperature ranges.
The K8D3216U NOR Flash Memory is created by using Samsung's advanced CMOS process technology. This device is
available in 48 pin TSOP1 and 48 ball TBGA, FBGA packages.
The device is compatible with EPROM applications to require
high-density and cost-effective nonvolatile read/write storage
solutions.
PIN DESCRIPTION
Pin Name
A0 - A20
PIN CONFIGURATION
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
RESET
N.C
WP/ACC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-pin TSOP1
Standard Type
12mm x 20mm
DQ0 - DQ14
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DQ15/A-1
A16
BYTE
Vss
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
Vss
CE
A0
BYTE
Address Inputs
Data Inputs / Outputs
DQ15 Data Input / Output
A-1 LSB Address
Word / Byte Selection
CE
Chip Enable
OE
Output Enable
RESET
Hardware Reset Pin
RY/BY
Ready/Busy Output
WE
WP/ACC
Note :
Please refer to the package dimension.
Pin Function
Write Enable
Hardware Write Protection/Program
Acceleration
Vcc
Power Supply
VSS
Ground
N.C
No Connection
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
2
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
48 Ball TBGA/FBGA TOP VIEW (BALL DOWN)
1
2
3
4
5
6
A
A3
A7
RY/BY
WE
A9
A13
B
A4
A17
WP/
ACC
RESET
A8
A12
C
A2
A6
A18
N.C
A10
A14
D
A1
A5
A20
A19
A11
A15
E
A0
DQ0
DQ2
DQ5
DQ7
A16
F
CE
DQ8
DQ10
DQ12
DQ14
BYTE
G
OE
DQ9
DQ11
VCC
DQ13
DQ15/
A-1
H
VSS
DQ1
DQ3
DQ4
DQ6
VSS
FUNCTIONAL BLOCK DIAGRAM
Bank1
Address
Vcc
Vss
X
Dec
Bank1
Cell Array
Y Dec
CE
OE
WE
BYTE
RESET
RY/BY
WP/ACC
Latch &
Control
Bank1 Data-In/Out
I/O
Interface
&
Bank
Control
Bank2 Data-In/Out
Y Dec
Bank2
Address
X
Dec
Latch &
Control
Bank2
Cell Array
A0~A20
Erase
Control
DQ15/A-1
DQ0~DQ14
Program
Control
3
High
Voltage
Gen.
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
ORDERING INFORMATION
K 8 D 3x 1 6 U T C - T I 0 7
Access Time
07 = 70 ns
08 = 80 ns
09 = 90 ns
Samsung
NOR Flash Memory
Device Type
Dual Bank Boot Block
Operating Temperature Range
C = Commercial Temp. (0 °C to 70 °C)
I = Industrial Temp. (-40 °C to 85 °C)
Package
P = 48TSOP1(Lead-Free) Y = 48 TSOP1
D : FBGA(Lead Free)
F : FBGA
L : TBGA(Lead Free)
T : TBGA
Bank Division
32 = 8Mbits + 24Mbits
Organization
x8/x16 Selectable
Version
C = 4th Generation
Operating Voltage Range
2.7V to 3.6V
Block Architecture
T = Top Boot Block
B = Bottom Boot Block
Table 1. PRODUCT LINE-UP
Part No.
-7
-8
Vcc
-9
2.7V~3.6V
Max. Address Access Time (ns)
70ns
80ns
90ns
Max. CE Access Time (ns)
70ns
80ns
90ns
Max. OE Access Time (ns)
25ns
25ns
35ns
Table 2. K8D3216U DEVICE BANK DIVISIONS
Device
Part Number
K8D3216U
Bank 1
Bank 2
Mbit
Block Sizes
Mbit
Block Sizes
8 Mbit
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
24 Mbit
Forty-eight
64 Kbyte/32 Kword
4
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
Table 3. Top Boot Block Address (K8D3216UT)
Block Address
K8D3216UT
Bank1
Bank2
Address Range
A20
A19
A18
A17
A16
A15
A14
A13
A12
Block Size
(KB/KW)
BA70
1
1
1
1
1
1
1
1
1
8/4
3FE000H-3FFFFFH
1FF000H-1FFFFFH
BA69
1
1
1
1
1
1
1
1
0
8/4
3FC000H-3FDFFFH
1FE000H-1FEFFFH
Block
Byte Mode
Word Mode
BA68
1
1
1
1
1
1
1
0
1
8/4
3FA000H-3FBFFFH
1FD000H-1FDFFFH
BA67
1
1
1
1
1
1
1
0
0
8/4
3F8000H-3F9FFFH
1FC000H-1FCFFFH
BA66
1
1
1
1
1
1
0
1
1
8/4
3F6000H-3F7FFFH
1FB000H-1FBFFFH
BA65
1
1
1
1
1
1
0
1
0
8/4
3F4000H-3F5FFFH
1FA000H-1FAFFFH
BA64
1
1
1
1
1
1
0
0
1
8/4
3F2000H-3F3FFFH
1F9000H-1F9FFFH
BA63
1
1
1
1
1
1
0
0
0
8/4
3F0000H-3F1FFFH
1F8000H-1F8FFFH
BA62
1
1
1
1
1
0
X
X
X
64/32
3E0000H-3EFFFFH
1F0000H-1F7FFFH
BA61
1
1
1
1
0
1
X
X
X
64/32
3D0000H-3DFFFFH
1E8000H-1EFFFFH
BA60
1
1
1
1
0
0
X
X
X
64/32
3C0000H-3CFFFFH
1E0000H-1E7FFFH
BA59
1
1
1
0
1
1
X
X
X
64/32
3B0000H-3BFFFFH
1D8000H-1DFFFFH
BA58
1
1
1
0
1
0
X
X
X
64/32
3A0000H-3AFFFFH
1D0000H-1D7FFFH
BA57
1
1
1
0
0
1
X
X
X
64/32
390000H-39FFFFH
1C8000H-1CFFFFH
BA56
1
1
1
0
0
0
X
X
X
64/32
380000H-38FFFFH
1C0000H-1C7FFFH
BA55
1
1
0
1
1
1
X
X
X
64/32
370000H-37FFFFH
1B8000H-1BFFFFH
BA54
1
1
0
1
1
0
X
X
X
64/32
360000H-36FFFFH
1B0000H-1B7FFFH
BA53
1
1
0
1
0
1
X
X
X
64/32
350000H-35FFFFH
1A8000H-1AFFFFH
BA52
1
1
0
1
0
0
X
X
X
64/32
340000H-34FFFFH
1A0000H-1A7FFFH
BA51
1
1
0
0
1
1
X
X
X
64/32
330000H-33FFFFH
198000H-19FFFFH
BA50
1
1
0
0
1
0
X
X
X
64/32
320000H-32FFFFH
190000H-197FFFH
BA49
1
1
0
0
0
1
X
X
X
64/32
310000H-31FFFFH
188000H-18FFFFH
BA48
1
1
0
0
0
0
X
X
X
64/32
300000H-30FFFFH
180000H-187FFFH
BA47
1
0
1
1
1
1
X
X
X
64/32
2F0000H-2FFFFFH
178000H-17FFFFH
BA46
1
0
1
1
1
0
X
X
X
64/32
2E0000H-2EFFFFH
170000H-177FFFH
BA45
1
0
1
1
0
1
X
X
X
64/32
2D0000H-2DFFFFH
168000H-16FFFFH
BA44
1
0
1
1
0
0
X
X
X
64/32
2C0000H-2CFFFFH
160000H-167FFFH
BA43
1
0
1
0
1
1
X
X
X
64/32
2B0000H-2BFFFFH
158000H-15FFFFH
BA42
1
0
1
0
1
0
X
X
X
64/32
2A0000H-2AFFFFH
150000H-157FFFH
BA41
1
0
1
0
0
1
X
X
X
64/32
290000H-29FFFFH
148000H-14FFFFH
BA40
1
0
1
0
0
0
X
X
X
64/32
280000H-28FFFFH
140000H-147FFFH
BA39
1
0
0
1
1
1
X
X
X
64/32
270000H-27FFFFH
138000H-13FFFFH
BA38
1
0
0
1
1
0
X
X
X
64/32
260000H-26FFFFH
130000H-137FFFH
BA37
1
0
0
1
0
1
X
X
X
64/32
250000H-25FFFFH
128000H-12FFFFH
BA36
1
0
0
1
0
0
X
X
X
64/32
240000H-24FFFFH
120000H-127FFFH
BA35
1
0
0
0
1
1
X
X
X
64/32
230000H-23FFFFH
118000H-11FFFFH
5
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
Table 3. Top Boot Block Address (K8D3216UT)
Block Address
K8D3216UT
Bank2
Address Range
A20
A19
A18
A17
A16
A15
A14
A13
A12
Block Size
(KB/KW)
Byte Mode
Word Mode
BA34
1
0
0
0
1
0
X
X
X
64/32
220000H-22FFFFH
110000H-117FFFH
BA33
1
0
0
0
0
1
X
X
X
64/32
210000H-21FFFFH
108000H-10FFFFH
BA32
1
0
0
0
0
0
X
X
X
64/32
200000H-20FFFFH
100000H-107FFFH
BA31
0
1
1
1
1
1
X
X
X
64/32
1F0000H-1FFFFFH
0F8000H-0FFFFFH
BA30
0
1
1
1
1
0
X
X
X
64/32
1E0000H-1EFFFFH
0F0000H-0F7FFFH
BA29
0
1
1
1
0
1
X
X
X
64/32
1D0000H-1DFFFFH
0E8000H-0EFFFFH
BA28
0
1
1
1
0
0
X
X
X
64/32
1C0000H-1CFFFFH
0E0000H-0E7FFFH
BA27
0
1
1
0
1
1
X
X
X
64/32
1B0000H-1BFFFFH
0D8000H-0DFFFFH
BA26
0
1
1
0
1
0
X
X
X
64/32
1A0000H-1AFFFFH
0D0000H-0D7FFFH
BA25
0
1
1
0
0
1
X
X
X
64/32
190000H-19FFFFH
0C8000H-0CFFFFH
BA24
0
1
1
0
0
0
X
X
X
64/32
180000H-18FFFFH
0C0000H-0C7FFFH
BA23
0
1
0
1
1
1
X
X
X
64/32
170000H-17FFFFH
0B8000H-0BFFFFH
BA22
0
1
0
1
1
0
X
X
X
64/32
160000H-16FFFFH
0B0000H-0B7FFFH
BA21
0
1
0
1
0
1
X
X
X
64/32
150000H-15FFFFH
0A8000H-0AFFFFH
BA20
0
1
0
1
0
0
X
X
X
64/32
140000H-14FFFFH
0A0000H-0A7FFFH
BA19
0
1
0
0
1
1
X
X
X
64/32
130000H-13FFFFH
098000H-09FFFFH
BA18
0
1
0
0
1
0
X
X
X
64/32
120000H-12FFFFH
090000H-097FFFH
BA17
0
1
0
0
0
1
X
X
X
64/32
110000H-11FFFFH
088000H-08FFFFH
BA16
0
1
0
0
0
0
X
X
X
64/32
100000H-10FFFFH
080000H-087FFFH
BA15
0
0
1
1
1
1
X
X
X
64/32
0F0000H-0FFFFFH
078000H-07FFFFH
BA14
0
0
1
1
1
0
X
X
X
64/32
0E0000H-0EFFFFH
070000H-077FFFH
BA13
0
0
1
1
0
1
X
X
X
64/32
0D0000H-0DFFFFH
068000H-06FFFFH
BA12
0
0
1
1
0
0
X
X
X
64/32
0C0000H-0CFFFFH
060000H-067FFFH
BA11
0
0
1
0
1
1
X
X
X
64/32
0B0000H-0BFFFFH
058000H-05FFFFH
BA10
0
0
1
0
1
0
X
X
X
64/32
0A0000H-0AFFFFH
050000H-057FFFH
BA9
0
0
1
0
0
1
X
X
X
64/32
090000H-09FFFFH
048000H-04FFFFH
BA8
0
0
1
0
0
0
X
X
X
64/32
080000H-08FFFFH
040000H-047FFFH
BA7
0
0
0
1
1
1
X
X
X
64/32
070000H-07FFFFH
038000H-03FFFFH
BA6
0
0
0
1
1
0
X
X
X
64/32
060000H-06FFFFH
030000H-037FFFH
BA5
0
0
0
1
0
1
X
X
X
64/32
050000H-05FFFFH
028000H-02FFFFH
BA4
0
0
0
1
0
0
X
X
X
64/32
040000H-04FFFFH
020000H-027FFFH
BA3
0
0
0
0
1
1
X
X
X
64/32
030000H-03FFFFH
018000H-01FFFFH
BA2
0
0
0
0
1
0
X
X
X
64/32
020000H-02FFFFH
010000H-017FFFH
BA1
0
0
0
0
0
1
X
X
X
64/32
010000H-01FFFFH
008000H-00FFFFH
BA0
0
0
0
0
0
0
X
X
X
64/32
000000H-00FFFFH
000000H-007FFFH
Block
Note : The address range is A20 ∼ A-1 in the byte mode ( BYTE = VIL ) or A20 ∼ A0 in the word mode ( BYTE = VIH ).
The bank address bits is A20 ∼ A19 for K8D3216UT.
Table 4. Secode Block Addresses for Top Boot Devices
Device
Block Address
A20-A12
Block
Size
(X8)
Address Range
(X16)
Address Range
K8D3216UT
111111xxx
64/32
3F0000H-3FFFFFH
1F8000H-1FFFFFH
6
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
Table 5. Bottom Boot Block Address (K8D3216UB)
Block Address
K8D3216UB
Bank2
Address Range
A20
A19
A18
A17
A16
A15
A14
A13
A12
Block Size
(KB/KW)
Byte Mode
Word Mode
BA70
1
1
1
1
1
1
X
X
X
64/32
3F0000H-3FFFFFH
1F8000H-1FFFFFH
BA69
1
1
1
1
1
0
X
X
X
64/32
3E0000H-3EFFFFH
1F0000H-1F7FFFH
BA68
1
1
1
1
0
1
X
X
X
64/32
3D0000H-3DFFFFH
1E8000H-1EFFFFH
Block
BA67
1
1
1
1
0
0
X
X
X
64/32
3C0000H-3CFFFFH
1E0000H-1E7FFFH
BA66
1
1
1
0
1
1
X
X
X
64/32
3B0000H-3BFFFFH
1D8000H-1DFFFFH
BA65
1
1
1
0
1
0
X
X
X
64/32
3A0000H-3AFFFFH
1D0000H-1D7FFFH
BA64
1
1
1
0
0
1
X
X
X
64/32
390000H-39FFFFH
1C8000H-1CFFFFH
BA63
1
1
1
0
0
0
X
X
X
64/32
380000H-38FFFFH
1C0000H-1C7FFFH
BA62
1
1
0
1
1
1
X
X
X
64/32
370000H-37FFFFH
1B8000H-1BFFFFH
BA61
1
1
0
1
1
0
X
X
X
64/32
360000H-36FFFFH
1B0000H-1B7FFFH
BA60
1
1
0
1
0
1
X
X
X
64/32
350000H-35FFFFH
1A8000H-1AFFFFH
BA59
1
1
0
1
0
0
X
X
X
64/32
340000H-34FFFFH
1A0000H-1A7FFFH
BA58
1
1
0
0
1
1
X
X
X
64/32
330000H-33FFFFH
198000H-19FFFFH
BA57
1
1
0
0
1
0
X
X
X
64/32
320000H-32FFFFH
190000H-197FFFH
BA56
1
1
0
0
0
1
X
X
X
64/32
310000H-31FFFFH
188000H-18FFFFH
BA55
1
1
0
0
0
0
X
X
X
64/32
300000H-30FFFFH
180000H-187FFFH
BA54
1
0
1
1
1
1
X
X
X
64/32
2F0000H-2F1FFFH
178000H-17FFFFH
BA53
1
0
1
1
1
0
X
X
X
64/32
2E0000H-2EFFFFH
170000H-177FFFH
BA52
1
0
1
1
0
1
X
X
X
64/32
2D0000H-2DFFFFH
168000H-16FFFFH
BA51
1
0
1
1
0
0
X
X
X
64/32
2C0000H-2CFFFFH
160000H-167FFFH
BA50
1
0
1
0
1
1
X
X
X
64/32
2B0000H-2BFFFFH
158000H-15FFFFH
BA49
1
0
1
0
1
0
X
X
X
64/32
2A0000H-2AFFFFH
150000H-157FFFH
BA48
1
0
1
0
0
1
X
X
X
64/32
290000H-29FFFFH
148000H-14FFFFH
BA47
1
0
1
0
0
0
X
X
X
64/32
280000H-28FFFFH
140000H-147FFFH
BA46
1
0
0
1
1
1
X
X
X
64/32
270000H-27FFFFH
138000H-13FFFFH
BA45
1
0
0
1
1
0
X
X
X
64/32
260000H-26FFFFH
130000H-137FFFH
BA44
1
0
0
1
0
1
X
X
X
64/32
250000H-25FFFFH
128000H-12FFFFH
BA43
1
0
0
1
0
0
X
X
X
64/32
240000H-24FFFFH
120000H-127FFFH
X
64/32
230000H-23FFFFH
118000H-11FFFFH
X
64/32
220000H-22FFFFH
110000H-117FFFH
BA42
BA41
1
1
0
0
0
0
0
0
1
1
1
0
X
X
X
X
BA40
1
0
0
0
0
1
X
X
X
64/32
210000H-21FFFFH
108000H-10FFFFH
BA39
1
0
0
0
0
0
X
X
X
64/32
200000H-20FFFFH
100000H-107FFFH
BA38
0
1
1
1
1
1
X
X
X
64/32
1F0000H-1FFFFFH
0F8000H-0FFFFFH
BA37
0
1
1
1
1
0
X
X
X
64/32
1E0000H-1EFFFFH
0F0000H-0F7FFFH
BA36
0
1
1
1
0
1
X
X
X
64/32
1D0000H-1DFFFFH
0E8000H-0EFFFFH
BA35
0
1
1
1
0
0
X
X
X
64/32
1C0000H-1CFFFFH
0E0000H-0E7FFFH
7
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
Table 5. Bottom Block Address (K8D3216UB)
Block Address
K8D3216UB
Address Range
A20
A19
A18
A17
A16
A15
A14
A13
A12
Block Size
(KB/KW)
Byte Mode
Word Mode
BA34
0
1
1
0
1
1
X
X
X
64/32
1B0000H-1BFFFFH
0D8000H-0DFFFFH
BA33
0
1
1
0
1
0
X
X
X
64/32
1A0000H-1AFFFFH
0D0000H-0D7FFFH
BA32
0
1
1
0
0
1
X
X
X
64/32
190000H-19FFFFH
0C8000H-0CFFFFH
BA31
0
1
1
0
0
0
X
X
X
64/32
180000H-18FFFFH
0C0000H-0C7FFFH
BA30
0
1
0
1
1
1
X
X
X
64/32
170000H-17FFFFH
0B8000H-0BFFFFH
BA29
0
1
0
1
1
0
X
X
X
64/32
160000H-16FFFFH
0B0000H-0B7FFFH
BA28
0
1
0
1
0
1
X
X
X
64/32
150000H-15FFFFH
0A8000H-0AFFFFH
BA27
0
1
0
1
0
0
X
X
X
64/32
140000H-14FFFFH
0A0000H-0A7FFFH
BA26
0
1
0
0
1
1
X
X
X
64/32
130000H-13FFFFH
098000H-09FFFFH
Block
Bank2
Bank1
BA25
0
1
0
0
1
0
X
X
X
64/32
120000H-12FFFFH
090000H-097FFFH
BA24
0
1
0
0
0
1
X
X
X
64/32
110000H-11FFFFH
088000H-08FFFFH
BA23
0
1
0
0
0
0
X
X
X
64/32
100000H-10FFFFH
080000H-087FFFH
BA22
0
0
1
1
1
1
X
X
X
64/32
0F0000H-0FFFFFH
078000H-07FFFFH
BA21
0
0
1
1
1
0
X
X
X
64/32
0E0000H-0EFFFFH
070000H-077FFFH
BA20
0
0
1
1
0
1
X
X
X
64/32
0D0000H-0DFFFFH
068000H-06FFFFH
BA19
0
0
1
1
0
0
X
X
X
64/32
0C0000H-0CFFFFH
060000H-067FFFH
BA18
0
0
1
0
1
1
X
X
X
64/32
0B0000H-0BFFFFH
058000H-05FFFFH
BA17
0
0
1
0
1
0
X
X
X
64/32
0A0000H-0AFFFFH
050000H-057FFFH
BA16
0
0
1
0
0
1
X
X
X
64/32
090000H-09FFFFH
048000H-04FFFFH
BA15
0
0
1
0
0
0
X
X
X
64/32
080000H-08FFFFH
040000H-047FFFH
BA14
0
0
0
1
1
1
X
X
X
64/32
070000H-07FFFFH
038000H-03FFFFH
BA13
0
0
0
1
1
0
X
X
X
64/32
060000H-06FFFFH
030000H-037FFFH
BA12
0
0
0
1
0
1
X
X
X
64/32
050000H-05FFFFH
028000H-02FFFFH
BA11
0
0
0
1
0
0
X
X
X
64/32
040000H-04FFFFH
020000H-027FFFH
BA10
0
0
0
0
1
1
X
X
X
64/32
030000H-03FFFFH
018000H-01FFFFH
BA9
0
0
0
0
1
0
X
X
X
64/32
020000H-02FFFFH
010000H-017FFFH
BA8
0
0
0
0
0
1
X
X
X
64/32
010000H-01FFFFH
008000H-00FFFFH
BA7
0
0
0
0
0
0
1
1
1
8/4
00E000H-00FFFFH
007000H-007FFFH
BA6
0
0
0
0
0
0
1
1
0
8/4
00C000H-00DFFFH
006000H-006FFFH
BA5
0
0
0
0
0
0
1
0
1
8/4
00A000H-00BFFFH
005000H-005FFFH
BA4
0
0
0
0
0
0
1
0
0
8/4
008000H-009FFFH
004000H-004FFFH
BA3
0
0
0
0
0
0
0
1
1
8/4
006000H-007FFFH
003000H-003FFFH
BA2
0
0
0
0
0
0
0
1
0
8/4
004000H-005FFFH
002000H-002FFFH
BA1
0
0
0
0
0
0
0
0
1
8/4
002000H-003FFFH
001000H-001FFFH
BA0
0
0
0
0
0
0
0
0
0
8/4
000000H-001FFFH
000000H-000FFFH
Note : The address range is A20 ∼ A-1 in the byte mode ( BYTE = VIL ) or A20 ∼ A0 in the word mode ( BYTE = VIH ).
The bank address bits is A20 ∼ A19 for K8D3216UB.
Table 6. Secode Block Addresses for Bottom Boot Devices
Device
Block Address
A20-A12
Block
Size
(X8)
Address Range
(X16)
Address Range
K8D3216UB
000000xxx
64/32
000000H-00FFFFH
000000H-007FFFH
8
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
PRODUCT INTRODUCTION
The K8D3216U is a 32Mbit (33,554,432 bits) NOR-type Flash memory. The device features single voltage power supply operating
within the range of 2.7V to 3.6V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is
used to program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flexible erase and program capability, the device adapts a block memory architecture that divides its memory array into 71 blocks (64Kbyte x 63 , 8-Kbyte x 8). Programming is done in units of 8 bits (Byte) or 16 bits (Word). All bits of data in one or multiple blocks can
be erased simultaneously when the device executes the erase operation. To prevent the device from accidental erasing or over-writing the programmed data, 71 memory blocks can be hardware protected by the block group. Byte/Word modes are available for read
operation. These modes can be selected via BYTE pin. The device provides read access times of 70ns, 80ns and 90ns supporting
high speed microprocessors to operate without any wait states.
The command set of K8D3216U is fully compatible with standard Flash devices. The device is controlled by chip enable (CE), output
enable (OE) and write enable (WE). Device operations are executed by selective command codes. The command codes to be combined wih addresses and data are sequentially written to the command registers using microprocessor write timing. The command
codes serve as inputs to an internal state machine which controls the program/erase circuitry. Register contents also internally latch
addresses and data necessary to execute the program and erase operations. The K8D3216U is implemented with Internal Program/
Erase Algorithms to execute the program/erase operations. The Internal Program/Erase Algorithms are invoked by program/erase
command sequences. The Internal Program Algorithm automatically programs and verifies data at specified addresses. The Internal
Erase Algorithm automatically pre-programs the memory cell which is not programmed and then executes the erase operation. The
K8D3216U has means to indicate the status of completion of program/erase operations. The status can be indicated via the RY/BY
pin, Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automatically resets itself to
the read mode. The device requires only 14 mA as active read current and 15 mA for program/erase operations.
Table 7. Operations Table
Operation
word
CE
OE
WE
BYTE
L
L
H
H
Read
WP/
ACC
A9
A6
A1
A0
DQ15/
A-1
DQ8/
DQ14
DQ0/
DQ7
RESET
A9
A6
A1
A0
DQ15
DOUT
DOUT
H
A9
A6
A1
A0
A-1
High-Z
DOUT
H
L/H
byte
L
L
H
L
Vcc ±
0.3V
X
X
X
(2)
X
X
X
X
High-Z
High-Z
High-Z
(2)
Output Disable
L
H
H
X
L/H
X
X
X
X
High-Z
High-Z
High-Z
H
Reset
X
X
X
X
L/H
X
X
X
X
High-Z
High-Z
High-Z
L
word
L
H
L
H
byte
L
H
L
L
Enable Block Group
Protect (3)
L
H
L
X
Enable Block Group
Unprotect (3)
L
H
L
Temporary Block
Group
X
X
Auto Select
Manufacturer ID (5)
L
Auto Select
Device Code (5)
L
Stand-by
A9
A6
A1
A0
DIN
DIN
DIN
H
A9
A6
A1
A0
A-1
High-Z
DIN
H
L/H
X
L
H
L
X
X
DIN
VID
X
(4)
X
H
H
L
X
X
DIN
VID
X
X
(4)
X
X
X
X
X
X
X
VID
L
H
X
L/H
VID
L
L
L
X
X
L
H
X
L/H
VID
L
L
H
X
X
Write
(4)
Code(See
Table 9)
Code(See
Table 9)
H
H
Notes :
1. L = VIL (Low), H = VIH (High), VID = 8.5V~12.5V, DIN = Data in, DOUT = Data out, X = Don't care.
2. WP/ACC and RESET pin are asserted at Vcc±0.3 V or Vss±0.3 V in the Stand-by mode.
3. Addresses must be composed of the Block address (A12 - A20).
The Block Protect and Unprotect operations may be implemented via programming equipment too.
Refer to the "Block Group Protection and Unprotection".
4. If WP/ACC=VIL, the two outermost boot blocks is protected. If WP/ACC=VIH, the two outermost boot block protection depends on whether those
blocks were last protected or unprotected using the method described in "Block Group Protection and Unprotection". If WP/ACC=VHH, all blocks
will be temporarily unprotected.
5. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 9.
9
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
COMMAND DEFINITIONS
The K8D3216U operates by selecting and executing its operational modes. Each operational mode has its own command set. In
order to select a certain mode, a proper command with specific address and data sequences must be written into the command register. Writing incorrect information which include address and data or writing an improper command will reset the device to the read
mode. The defined valid register command sequences are stated in Table 8. Note that Erase Suspend (B0H) and Erase Resume
(30H) commands are valid only while the Block Erase Operation is in progress.
Table 8. Command Sequences
1st Cycle
Command Sequence
Word
Addr
Read
Autoselect
Block Group
Protect Verify
(2,3)
Auto Select
Secode Block
Factory Protect
Verify (2,3)
Enter Secode
Block Region
Exit Secode
Block Region
3rd Cycle
4th Cycle
Word
Byte
Word
Byte
Word
Byte
5th Cycle
6th Cycle
2AAH
555H
DA/
555H
DA/
AAAH
DA/
X00H
DA/
X00H
Word
Byte
Word
Byte
2AAH
555H
555H
AAAH
RA
1
RD
Addr
XXXH
1
Data
Autoselect
Device Code
(2,3)
Byte
Data
Reset
Autoselect
Manufacturer
ID (2,3)
2nd Cycle
Cycle
F0H
555H
Addr
AAAH
4
Data
AAH
Addr
555H
55H
AAAH
2AAH
555H
4
Data
AAH
Addr
555H
55H
AAAH
2AAH
555H
4
Data
AAH
Addr
555H
AAAH
2AAH
555H
AAH
Addr
555H
2AAH
555H
DA/
AAAH
90H
DA/
555H
55H
AAAH
DA/
AAAH
90H
DA/
555H
55H
4
Data
90H
DA/
555H
DA/
AAAH
90H
555H
ECH
DA/
X01H
DA/
X02H
(See Table 9)
BA /
X02H
BA/
X04H
(See Table 9)
DA /
X03H
DA/
X06H
(See Table 9)
AAAH
3
Data
AAH
Addr
555H
55H
AAAH
2AAH
555H
88H
555H
AAAH
XXXH
4
Data
AAH
Addr
Program
555H
55H
AAAH
2AAH
555H
90H
555H
00H
AAAH
PA
4
Data
AAH
Addr
Unlock Bypass
555H
55H
AAAH
2AAH
555H
A0H
555H
PD
AAAH
3
Data
AAH
55H
Unlock Bypass
Program
Addr
XXXH
PA
A0H
PD
Unlock Bypass
Reset
Addr
XXXH
XXXH
20H
2
Data
2
Data
90H
Addr
Chip Erase
555H
00H
AAAH
2AAH
555H
555H
AAAH
555H
AAAH
6
Data
AAH
Addr
Block Erase
555H
55H
AAAH
2AAH
555H
80H
555H
AAAH
AAH
555H
AAAH
55H
2AAH
10H
555H
BA
6
Data
AAH
55H
80H
AAH
55H
30H
XXXH
Block Erase
Suspend (4, 5)
Addr
Data
B0H
Block Erase
Resume
Addr
XXXH
1
1
Data
30H
Addr
CFI Query (6)
55H
AAH
1
Data
98H
10
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
Notes :
FLASH MEMORY
1. RA : Read Address, PA : Program Address, RD : Read Data, PD : Program Data
DA : Dual Bank Address (A19 - A20), BA : Block Address (A12 - A20), X = Don’t care .
2. To terminate the Autoselect Mode, it is necessary to write Reset command to the register.
3. The 4th cycle data of Autoselect mode is output data.
The 3rd and 4th cycle bank addresses of Autoselect mode must be same.
4. The Read / Program operations at non-erasing blocks and the autoselect mode are allowed in the Erase Suspend mode.
5. The Erase Suspend command is applicable only to the Block Erase operation.
6. Command is valid when the device is in read mode or Autoselect mode.
7. DQ8 - DQ15 are don’t care in command sequence, but RD and PD is excluded.
8. A11 - A20 are also don’t care, except for the case of special notice.
Table 9. K8D3216U Autoselect Codes, (High Voltage Method)
DQ8 to DQ15
CE
OE
WE
A20
to
A12
A11
to
A10
A9
A8
to
A7
A6
A5
to
A2
A1
A0
Manufacturer ID
L
L
H
DA
X
VID
X
L
X
L
Device Code K8D3216UT
(Top Boot Block)
L
L
H
DA
X
VID
X
L
X
Device Code K8D3216UB
(Bottom Boot Block)
L
L
H
DA
X
VID
X
L
Block Protection
Verification
L
L
H
BA
X
VID
X
Secode Block (2)
Indicator Bit (DQ7)
L
L
H
DA
X
VID
X
Description
Notes :
DQ7
to
DQ0
BYTE
=VIH
BYTE
=VIL
L
X
X
ECH
L
H
22H
X
A0H
X
L
H
22H
X
A2H
L
X
H
L
X
X
01H (Protected),
00H (Unprotected)
L
X
H
H
X
X
80H (Factory locked),
00H (Not factory locked)
1. L=Logic Low=VIL, H=Logic High=VIH, DA=Dual Bank Address, BA=Block Address, X=Don’t care.
2. Secode Block : Security Code Block.
11
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
DEVICE OPERATION
Byte/Word Mode
If the BYTE pin is set at logical "1" , the device is in word mode, DQ0-DQ15 are active. Otherwise the BYTE pin is set at logical "0" ,
the device is in byte mode, DQ0-DQ7 are active. DQ8-DQ14 are in the High-Z state and DQ15 pin is used as an input for the LSB
(A-1) address pin.
Read Mode
The K8D3216U is controlled by Chip Enable (CE), Output Enable (OE) and Write Enable (WE). When CE and OE are low and WE
is high, the data stored at the specified address location,will be the output of the device. The outputs are in high impedance state
whenever CE or OE is high.
Standby Mode
The K8D3216U features Stand-by Mode to reduce power consumption. This mode puts the device on hold when the device is deselected by making CE high (CE = VIH). Refer to the DC characteristics for more details on stand-by modes.
Output Disable
The device outputs are disabled when OE is High (OE = VIH). The output pins are in high impedance state.
Automatic Sleep Mode
K8D3216U features Automatic Sleep Mode to minimize the device power consumption. Since the device typically draws 5µA of the
current in Automatic Sleep Mode, this feature plays an extremely important role in battery-powered applications. When addresses
remain steady for tAA+50ns, the device automatically activates the Automatic Sleep Mode. In the sleep mode, output data is latched
and always available to the system. When addresses are changed, the device provides new data without wait time.
tAA + 50ns
Address
Outputs
Data
Data
Data
Data
Data
Data
Auto Sleep Mode
Figure 1. Auto Sleep Mode Operation
Autoselect Mode
The K8D3216U offers the Autoselect Mode to identify manufacturer and device type by reading a binary code. The Autoselect Mode
allows programming equipment to automatically match the device to be programmed with its corresponding programming algorithm.
In addition, this mode allows the verification of the status of write protected blocks. This mode is used by two method. The one is high
voltage method to be required VID (8.5V~12.5V) on address pin A9. When A9 is held at VID and the bank address or block address is
asserted, the device outputs the valid data via DQ pins(see Table 9 and Figure 2). The rest of addresses except A0, A1 and A6 are
Don′t Care. The other is autoselect command method that the autoselect code is accessible by the commamd sequence without VID.
The manufacturer and device code may also be read via the command register. The Command Sequence is shown in Table 8 and
Figure 3. The autoselect operation of block protect verification is initiated by first writing two unlock cycle. The third cycle must contain the bank address and autoselect command (90H). If Block address while (A6, A1, A0) = (0,1,0) is finally asserted on the address
pin, it will produce a logical "1" at the device output DQ0 to indicate a write protected block or a logical "0" at the device output DQ0
to indicate a write unprotected block. To terminate the autoselect operation, write Reset command (F0H) into the command register.
12
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
VID
V = VIH or VIL
A9
A6,A1,A0*
01H
00H
22A0H
or
22A2H
ECH
DQ15-DQ0
Manufacturer
Code
Device Code
(K8D3216U)
Return to
Read Mode
Note : The addresses other than A0 , A1 and A6 are Don′t care. Please refer to Table 9 for device code.
Figure 2. Autoselect Operation ( by high voltage method )
WE
A20∼A0(x16)/*
A20∼A-1(x8)
DQ15∼DQ0
2AAH/
555H
555H/
AAAH
01H/
02H
22A0H
or
22A2H
ECH
90H
55H
AAH
00H/
00H
555H/
AAAH
Manufacturer
Code
F0H
Device Code
(K8D3216U)
Return to
Read Mode
Note : The 3rd Cycle and 4th Cycle address must include the same bank address. Please refer to Table 9 for device code.
Figure 3. Autoselect Operation ( by command sequence method )
Write (Program/Erase) Mode
The K8D3216U executes its program/erase operations by writing commands into the command register. In order to write the commands to the register, CE and WE must be low and OE must be high. Addresses are latched on the falling edge of CE or WE (whichever occurs last) and the data are latched on the rising edge of CE or WE (whichever occurs first). The device uses standard
microprocessor write timing.
Program
The K8D3216U can be programmed in units of a word or a byte. Programming is writing 0's into the memory array by executing the
Internal Program Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first
two cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the memory location and the data to be programmed at that location are written. The device automatically generates adequate program
pulses and verifies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is
not required to provide further controls or timings.
During the Internal Program Routine, commands written to the device will be ignored. Note that a hardware reset during a program
operation will cause data corruption at the corresponding location.
WE
A20∼A0(x16)/
A20∼A-1(x8)
DQ15-DQ0
555H/
AAAH
2AAH/
555H
555H/
AAAH
AAH
55H
Program
Address
A0H
Program
Data
Program
Start
RY/BY
Figure 4. Program Command Sequence
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FLASH MEMORY
Unlock Bypass
The K8D3216U provides the unlock bypass mode to save its program time for program operation. The mode is invoked by the unlock
bypass command sequence. Then, the unlock bypass program command sequence is required to program the device.
Unlike the standard program command sequence that contains four bus cycles, the unlock bypass program command sequence
comprises only two bus cycles.
The unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. Writing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H). Once the device is in the unlock
bypass mode, the unlock bypass program command sequence is necessary to program in this mode. The unlock bypass program
command sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the program address and data. This command sequence is the only valid one for programming the device in the unlock bypass mode.
The unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock
bypass reset command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains
only the data (00H). Then, the device returns to the read mode.
Chip Erase
To erase a chip is to write 1′s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus
cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two
more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the
entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE or CE pulse
in the command sequence and terminates when DQ7 is "1". After that the device returns to the read mode.
WE
A20∼A0(x16)/
A20∼A-1(x8)
DQ15-DQ0
555H/
AAAH
2AAH/
555H
AAH
555H/
AAAH
55H
555H
AAAH
80H
2AAH/
555H
AAH
555H/
AAAH
55H
10H
Chip Erase
Start
RY/BY
Figure 5. Chip Erase Command Sequence
Block Erase
To erase a block is to write 1′s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six
bus cycles to write the command sequence shown in Table 8. After the first two "unlock" cycles, the erase setup command (80H) is
written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine
automatically pre-programs and verifies the entire memory prior to erasing it. The block address is latched on the falling edge of WE
or CE, while the Block Erase command is latched on the rising edge of WE or CE.
Multiple blocks can be erased sequentially by writing the six bus-cycle operation in Figure 6. Upon completion of the last cycle for the
Block Erase, additional block address and the Block Erase command (30H) can be written to perform the Multi-Block Erase. An 50µs
(typical) "time window" is required between the Block Erase command writes. The Block Erase command must be written within the
50µs "time window", otherwise the Block Erase command will be ignored. The 50µs "time window" is reset when the falling edge of
the WE occurs within the 50µs of "time window" to latch the Block Erase command. During the 50µs of "time window", any command
other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After the 50µs of
"time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase
address and command following the exceeded "time window" may or may not be accepted. No other commands will be recognized
except the Erase Suspend command during Block Erase operation.
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FLASH MEMORY
WE
A20∼A0(x16)/
A20∼A-1(x8)
555H/
AAAH
DQ15-DQ0
2AAH/
555H
AAH
555H/
AAAH
555H/
AAAH
80H
55H
2AAH/
555H
AAH
Block
Address
55H
30H
Block Erase
Start
RY/BY
Figure 6. Block Erase Command Sequence
Erase Suspend / Resume
The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. The Erase Suspend command is only valid during the Block Erase operation including the time window of 50µs. The Erase Suspend command is
not valid while the Chip Erase or the Internal Program Routine sequence is running.
When the Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 20µs to suspend
the erase operation. But, when the Erase Suspend command is written during the block erase time window (50µs) , the device immediately terminates the block erase time window and suspends the erase operation.
After the erase operation has been suspended, the device is availble for reading or programming data in a block that is not being
erased. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode.
When the Erase Resume command is executed, the Block Erase operation will resume. When the Erase Suspend or Erase Resume
command is executed, the addresses are in Don't Care state.
WE
A20∼A0(x16)/
A20∼A-1(x8)
DQ15-DQ0
555H/
AAAH
Block
Address
AAH
Block Erase
Command Sequence
XXXH
30H
XXXH
B0H
Block Erase
Start
Erase
Suspend
30H
Erase
Resume
Figure 7. Erase Suspend/Resume Command Sequence
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FLASH MEMORY
Read While Write
The K8D3216U provides dual bank memory architecture that divides the memory array into two banks. The device is capable of
reading data from one bank and writing data to the other bank simultaneously. This is so called the Read While Write operation with
dual bank architecture; this feature provides the capability of executing the read operation during Program/Erase or Erase-SuspendProgram operation.
The Read While Write operation is prohibited during the chip erase operation. It is also allowed during erase operation when either
single block or multiple blocks from same bank are loaded to be erased. It means that the Read While Write operation is prohibited
when blocks from Bank1 and another blocks from Bank2 are loaded all together for the multi-block erase operation.
Block Group Protection & Unprotection
The K8D3216U feature hardware block group protection. This feature will disable both program and erase operations in any combination of twenty five block groups of memory. Please refer to Tables 10 and 11. The block group protection feature is enabled using
programming equipment at the user’s site. The device is shipped with all block groups unprotected.
This feature can be hardware protected or unprotected. If a block is protected, program or erase command in the protected block will
be ignored by the device. The protected block can only be read. This is useful method to preserve an important program data. The
block group unprotection allows the protected blocks to be erased or programed. All blocks must be protected before unprotect operation is executing. The block group protection and unprotection can be implemented by two methods.
The first method needs the following conditions.
Operation
CE
OE
WE
BYTE
A9
A6
A1
DQ15/
A-1
A0
DQ8/
DQ14
DQ0/
DQ7
RESET
Block Group Protect
L
H
L
X
X
L
H
L
X
X
DIN
VID
Block Group Unprotect
L
H
L
X
X
H
H
L
X
X
DIN
VID
Address must be inputted to the block group address (A12~A20) during block group protection operation. Please refer to Figure 9
(Algorithm) and Switching Waveforms of Block Group Protect & Unprotect Operations.
The second method needs the following conditions in order to keep backward compatibility. Please refer to Figure 8.
Operation
BYTE
A9
A6
A1
A0
DQ15/
A-1
DQ8/
DQ14
DQ0/
DQ7
RESET
VID
X
VID
L
H
L
X
X
X
H
VID
X
VID
H
H
L
X
X
X
H
CE
OE
Block Group Protect
L
Block Group Unprotect
L
WE
The K8D3216U needs the recovery time (20µs) from the rising edge of WE in order to execute its program, erase and read operations.
500ns
Block Group Protect:150µs
Block Group Unprotect:500ms
500ns
VID
A9
Don't Care
VID
Don't Care
OE
WE
Address
Low
Block Group Address*
Notes : * Block Group Address is Don't Care during Block Group Unprotection.
Figure 8. Block Group Protect Sequence (The second method)
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FLASH MEMORY
START
COUNT = 1
RESET=VID
Wait 1µs
First Write
Cycle=60h?
No
Temporary Block Group
Unprotect Mode
Yes
Yes
Block Group
Protection ?
No
Block Protect
Algorithm
No
Set up Block Group
address
All Block Groups
Protected ?
Block Unprotect
Algorithm
Yes
Block Group <i>, i= 0
Block Group Unprotect
Write 60H
with
A6=1,A1=1
A0=0
Block Group Protect:
Write 60H to Block
Group address with
A6=0,A1=1
A0=0
Wait 15ms
Wait 150µs
Reset
COUNT=1
Verify Block Group
Protect:Write 40H to
Block Group address
with A6=0,
A1=1,A0=0
Increment
COUNT
Increment
COUNT
Read from
Block Group address
with A6=1,
A1=1,A0=0
Read from
Block Group address
with A6=0,
A1=1,A0=0
No
COUNT
=1000?
Data=01h?
No
Data=00h?
Yes
Yes
Yes
Yes
Device failed
Protect another
Block Group?
Set up next Block
Group address
No
No
COUNT
=25?
Verify Block Group
Unprotect:Write 40H to
Block Group address
with A6=1,
A1=1,A0=0
Device failed
Last Block Group
verified ?
No
Yes
Yes
Remove VID
from RESET
No
Remove VID
from RESET
Write RESET
command
Write RESET
command
END
END
Note : All blocks must be protected before unprotect operation is executing.
Figure 9. Block Group Protection & Unprotection Algorithms
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FLASH MEMORY
Table 10. Flash Memory Block Group Address (Top Boot Block)
Block Address
Block Group
Block
A20
A19
A18
A17
A16
A15
A14
A13
A12
BGA0
0
0
0
0
0
0
X
X
X
BA0
0
1
BGA1
0
0
0
0
1
0
X
X
X
BA1 to BA3
1
1
X
X
X
X
X
BA4 to BA7
BGA2
0
0
0
1
BGA3
0
0
1
0
X
X
X
X
X
BA8 to BA11
BGA4
0
0
1
1
X
X
X
X
X
BA12 to BA15
BGA5
0
1
0
0
X
X
X
X
X
BA16 to BA19
BGA6
0
1
0
1
X
X
X
X
X
BA20 to BA23
BGA7
0
1
1
0
X
X
X
X
X
BA24 to BA27
BGA8
0
1
1
1
X
X
X
X
X
BA28 to BA31
BGA9
1
0
0
0
X
X
X
X
X
BA32 to BA35
BGA10
1
0
0
1
X
X
X
X
X
BA36 to BA39
BGA11
1
0
1
0
X
X
X
X
X
BA40 to BA43
BGA12
1
0
1
1
X
X
X
X
X
BA44 to BA47
BGA13
1
1
0
0
X
X
X
X
X
BA48 to BA51
BGA14
1
1
0
1
X
X
X
X
X
BA52 to BA55
BGA15
1
1
1
0
X
X
X
X
X
BA56 to BA59
0
0
0
1
X
X
X
BA60 to BA62
1
0
BGA16
1
1
1
1
BGA17
1
1
1
1
1
1
0
0
0
BA63
BGA18
1
1
1
1
1
1
0
0
1
BA64
BGA19
1
1
1
1
1
1
0
1
0
BA65
BGA20
1
1
1
1
1
1
0
1
1
BA66
BGA21
1
1
1
1
1
1
1
0
0
BA67
BGA22
1
1
1
1
1
1
1
0
1
BA68
BGA23
1
1
1
1
1
1
1
1
0
BA69
BGA24
1
1
1
1
1
1
1
1
1
BA70
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FLASH MEMORY
Table 11. Flash Memory Block Group Address (Bottom Boot Block)
Block Address
Block Group
Block
A20
A19
A18
A17
A16
A15
A14
A13
A12
BGA0
0
0
0
0
0
0
0
0
0
BA0
BGA1
0
0
0
0
0
0
0
0
1
BA1
BGA2
0
0
0
0
0
0
0
1
0
BA2
BGA3
0
0
0
0
0
0
0
1
1
BA3
BGA4
0
0
0
0
0
0
1
0
0
BA4
BGA5
0
0
0
0
0
0
1
0
1
BA5
BGA6
0
0
0
0
0
0
1
1
0
BA6
BGA7
0
0
0
0
0
0
1
1
1
BA7
0
1
1
0
X
X
X
BA8 to BA10
1
1
BGA8
0
0
0
0
BGA9
0
0
0
1
X
X
X
X
X
BA11 to BA14
BGA10
0
0
1
0
X
X
X
X
X
BA15 to BA18
BGA11
0
0
1
1
X
X
X
X
X
BA19 to BA22
BGA12
0
1
0
0
X
X
X
X
X
BA23 to BA26
BGA13
0
1
0
1
X
X
X
X
X
BA27 to BA30
BGA14
0
1
1
0
X
X
X
X
X
BA31 to BA34
BGA15
0
1
1
1
X
X
X
X
X
BA35 to BA38
BGA16
1
0
0
0
X
X
X
X
X
BA39 to BA42
BGA17
1
0
0
1
X
X
X
X
X
BA43 to BA46
BGA18
1
0
1
0
X
X
X
X
X
BA47 to BA50
BGA19
1
0
1
1
X
X
X
X
X
BA51 to BA54
BGA20
1
1
0
0
X
X
X
X
X
BA55 to BA58
BGA21
1
1
0
1
X
X
X
X
X
BA59 to BA62
BGA22
1
1
1
0
X
X
X
X
X
BA63 to BA66
0
0
BGA23
1
1
1
1
0
1
X
X
X
BA67 to BA69
1
0
1
1
X
X
X
BA70
BGA24
1
1
1
1
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FLASH MEMORY
Temporary Block Group Unprotect
The protected blocks of the K8D3216U can be temporarily unprotected by applying high voltage (VID = 8.5V~12.5V) to the RESET
pin. In this mode, previously protected blocks can be programmed or erased with the program or erase command routines. When the
RESET pin goes high (RESET = VIH), all the previously protected blocks will be protected again. If the WP/ACC pin is asserted at VIL
, the two outermost boot blocks remain protected.
VID
V = VIH or VIL
RESET
CE
Program & Erase Operation
at Protected Block
WE
Figure 10. Temporary Block Group Unprotect Sequence
Write Protect (WP)
The WP/ACC pin has two useful functions. The one is that certain boot block is protected by the hardware method not to use VID.
The other is that program operation is accelerated to reduce the program time (Refer to Accelerated program Operation Paragraph).
When the WP/ACC pin is asserted at VIL, the device can not perform program and erase operation in the two "outermost" 8K byte
boot blocks independently of whether those blocks were protected or unprotected using the method described in "Block Group protection/Unprotection".
The write protected blocks can only be read. This is useful method to preserve an important program data.
The two outermost 8K byte boot blocks are the two blocks containing the lowest addresses in a bottom-boot-configured device, or
the two blocks containing the highest addresses in a top-boot-congfigured device.
(K8D3216UT : BA69 and BA70, K8D3216UB : BA0 and BA1)
When the WP/ACC pin is asserted at VIH, the device reverts to whether the two outermost 8K byte boot blocks were last set to be
protected or unprotected. That is, block protection or unprotection for these two blocks depends on whether they were last protected
or unprotected using the method described in "Block Group protection/unprotection".
Recommend that the WP/ACC pin must not be in the state of floating or unconnected, or the device may be led to malfunction.
Secode(Security Code) Block Region
The Secode Block feature provides a Flash memory region to be stored unique and permanent identification code, that is, Electronic
Serial Number (ESN), customer code and so on. This is primarily intended for customers who wish to use an Electronic Serial Number (ESN) in the device with the ESN protected against modification. Once the Secode Block region is protected, any further modification of that region is impossible. This ensures the security of the ESN once the product is shipped to the field.
The Secode Block is factory locked or customer lockable. Before the device is shipped, the factory locked Secode Block is written on
the special code and it is protected. The Secode Indicator bit (DQ7) is permanently fixed at "1" and it is not changed. The customer
lockable Secode Block is unprotected, therefore it is programmed and erased. The Secode Indicator bit (DQ7) of it is permanently
fixed at "0" and it is not changed. But once it is protected, there is no procedure to unprotect and modify the Secode Block.
The Secode Block region is 64K bytes in length and is accessed through a new command sequence (see Table 8). After the system
has written the Enter Secode Block command sequence, the system may read the Secode Block region by using the same
addresses of the boot blocks (8KBx8). The K8D3216UT occupies the address of the byte mode 3F0000H to 3FFFFFH (word mode
1F8000H to 1FFFFFH) and the K8D3216UB type occupies the address of the byte mode 000000H to 00FFFFH (word mode
000000H to 007FFFH). This mode of operation continues until the system issues the Exit Secode Block command sequence, or until
power is removed from the device. On power-up, or following a hardware reset, the device reverts to read mode.
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FLASH MEMORY
Accelerated Program Operation
Accelerated program operation reduces the program time. This is one of two functions provided by the WP/ACC pin. When the WP/
ACC pin is asserted as VHH, the device automatically enters the aforementioned Unlock Bypass mode, temporarily unprotecting any
protected blocks, and reduces the program operation time. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing VHH from the WP/ACC pin returns the device to normal operation. Recommend
that the WP/ACC pin must not be asserted at VHH except accelerated program operation, or the device may be damaged. In
addition, the WP/ACC pin must not be in the state of floating or unconnected, otherwise the device may be led to malfunction.
Software Reset
The reset command provides that the bank is reseted to read mode or erase-suspend-read mode. The addresses are in Don't Care
state. The reset command is vaild between the sequence cycles in an erase command sequence before erasing begins, or in a program command sequence before programming begins. This resets the bank in which was operating to read mode. if the device is be
erasing or programming, the reset command is invalid until the operation is completed. Also, the reset command is valid between the
sequence cycles in an autoselect command sequence. In the autoselect mode, the reset command returns the bank to read mode.
If a bank entered the autoselect mode in the Erase Suspend mode, the reset command returns the bank to erase-suspend-read
mode. If DQ5 is high on erase or program operation, the reset command return the bank to read mode or erase-suspend-read mode
if the bank was in the Erase Suspend state.
Hardware Reset
The K8D3216U offers a reset feature by driving the RESET pin to VIL. The RESET pin must be kept low (VIL) for at least 500ns.
When the RESET pin is driven low, any operation in progress will be terminated and the internal state machine will be reset to the
standby mode after 20µs. If a hardware reset occurs during a program operation, the data at that particular location will be lost.
Once the RESET pin is taken high, the device requires 200ns of wake-up time until outputs are valid for read access. Also, note that
all the data output pins are tri-stated for the duration of the RESET pulse.
The RESET pin may be tied to the system reset pin. If a system reset occurs during the Internal Program and Erase Routine, the
device will be automatically reset to the read mode ; this will enable the systems microprocessor to read the boot-up firmware from
the Flash memory.
Power-up Protection
To avoid initiation of a write cycle during Vcc Power-up, RESET low must be asserted during power-up. After RESET goes high, the
device is reset to the read mode.
Low Vcc Write Inhibit
To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than 1.8V. If Vcc <
VLKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the device
will reset itself to the read mode. Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the user′s responsibility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above 1.8V.
Write Pulse Glitch Protection
Noise pulses of less than 5ns(typical) on CE, OE, or WE will not initiate a write cycle.
Logical Inhibit
Writing is inhibited under any one of the following conditions : OE = VIL, CE = VIH or WE = VIH. To initiate a write, CE and WE must
be "0", while OE is "1".
Commom Flash Memory Interface
Common Flash Momory Interface is contrived to increase the compatibility of host system software. It provides the specific information of the device, such as memory size, byte/word configuration, and electrical features. Once this information has been obtained,
the system software will know which command sets to use to enable flash writes, block erases, and control the flash component.
When the system writes the CFI command(98H) to address 55H in word mode(or address AAH in byte mode), the device enters the
CFI mode. And then if the system writes the address shown in Table 12, the system can read the CFI data. Query data are always
presented on the lowest-order data outputs(DQ0-7) only. In word(x16) mode, the upper data outputs(DQ8-15) is 00h. To terminate
this operation, the system must write the reset command.
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FLASH MEMORY
Table 12. Common Flash Memory Interface Code
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
Query Unique ASCII string "QRY"
10H
11H
12H
20H
22H
24H
0051H
0052H
0059H
Primary OEM Command Set
13H
14H
26H
28H
0002H
0000H
Address for Primary Extended Table
15H
16H
2AH
2CH
0040H
0000H
Alternate OEM Command Set (00h = none exists)
17H
18H
2EH
30H
0000H
0000H
Address for Alternate OEM Extended Table (00h = none exists)
19H
1AH
32H
34H
0000H
0000H
Vcc Min. (write/erase)
D7-D4: volt, D3-D0: 100 millivolt
1BH
36H
0027H
Vcc Max. (write/erase)
D7-D4: volt, D3-D0: 100 millivolt
1CH
38H
0036H
Vpp Min. voltage(00H = no Vpp pin present)
1DH
3AH
0000H
Vpp Max. voltage(00H = no Vpp pin present)
1EH
3CH
0000H
Typical timeout per single byte/word write 2 us
1FH
3EH
0004H
Typical timeout for Min. size buffer write 2N us(00H = not supported)
20H
40H
0000H
Description
N
Typical timeout per individual block erase 2N ms
21H
42H
000AH
Typical timeout for full chip erase 2N ms(00H = not supported)
22H
44H
0000H
23H
46H
0005H
24H
48H
0000H
25H
4AH
0004H
Max. timeout for full chip erase 2 times typical(00H = not supported)
26H
4CH
0000H
Device Size = 2N byte
27H
4EH
0016H
Flash Device Interface description
28H
29H
50H
52H
0002H
0000H
Max. number of byte in multi-byte write = 2N
2AH
2BH
54H
56H
0000H
0000H
Number of Erase Block Regions within device
2CH
58H
0002H
Erase Block Region 1 Information
2DH
2EH
2FH
30H
5AH
5CH
5EH
60H
0007H
0000H
0020H
0000H
Erase Block Region 2 Information
31H
32H
33H
34H
62H
64H
66H
68H
003EH
0000H
0000H
0001H
Erase Block Region 3 Information
35H
36H
37H
38H
6AH
6CH
6EH
70H
0000H
0000H
0000H
0000H
Erase Block Region 4 Information
39H
3AH
3BH
3CH
72H
74H
76H
78H
0000H
0000H
0000H
0000H
N
Max. timeout for byte/word write 2 times typical
N
Max. timeout for buffer write 2 times typical
N
Max. timeout per individual block erase 2 times typical
N
22
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
Table 12. Common Flash Memory Interface Code
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
Query-unique ASCII string "PRI"
40H
41H
42H
80H
82H
84H
0050H
0052H
0049H
Major version number, ASCII
43H
86H
0033H
Minor version number, ASCII
44H
88H
0033H
Address Sensitive Unlock(Bits 1-0)
0 = Required, 1= Not Required
Silcon Revision Number(Bits 7-2)
45H
8AH
0000H
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
46H
8CH
0002H
Block Protect
0 = Not Supported, 1 = Number of blocks in per group
47H
8EH
0001H
Block Temporary Unprotect 00 = Not Supported, 01 = Supported
48H
90H
0001H
Block Protect/Unprotect scheme 04=K8D1x16U mode
49H
92H
0004H
Simultaneous Operation (1)
00 = Not Supported, XX = Number of Blocks in Bank2
4AH
94H
00XXH
Burst Mode Type 00 = Not Supported, 01 = Supported
4BH
96H
0000H
Page Mode Type
00 = Not Supported, 01 = 4 Word Page 02 = 8 Word Page
4CH
98H
0000H
ACC(Acceleration) Supply Minimum
00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV
4DH
9AH
0085H
ACC(Acceleration) Supply Maximum
00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV
4EH
9CH
00C5H
Top/Bottom Boot Block Flag
02H = Bottom Boot Device, 03H = Top Boot Device
4FH
9EH
000XH
Description
Note :
1. The number of blocks in Bank2 is device dependent.
K8D3216U(8Mb/24Mb) = 30h (48blocks)
23
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
DEVICE STATUS FLAGS
The K8D3216U has means to indicate its status of operation in the bank where a program or erase operation is in processes.
Address must include bank address being excuted internal routine operation. The status is indicated by raising the device status flag
via corresponding DQ pins or the RY/ BY pin. The corresponding DQ pins are DQ7, DQ6, DQ5, DQ3 and DQ2. The statuses are as
follows :
Table 13. Hardware Sequence Flags
Status
Programming
Block Erase or Chip Erase
DQ6
DQ5
DQ3
DQ2
RY/BY
DQ7
Toggle
0
0
1
0
0
Toggle
0
1
Toggle
0
1
1
0
0
Toggle
(Note 1)
1
Erase Suspend Read
Erase Suspended
Block
Erase Suspend Read
Non-Erase Suspended Block
Data
Data
Data
Data
Data
1
Erase Suspend
Program
Non-Erase Suspended Block
DQ7
Toggle
0
0
1
0
DQ7
Toggle
1
0
No
Toggle
0
0
Toggle
1
1
(Note 2)
0
0
No
Toggle
0
In Progress
Programming
Exceeded
Time Limits
DQ7
Block Erase or Chip Erase
Erase Suspend Program
DQ7
Toggle
1
Notes :
1. DQ2 will toggle when the device performs successive read operations from the erase suspended block.
2. If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle.
DQ7 : Data Polling
When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as
an indication of the Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data
written to DQ7. When a user attempts to read the device during the Erase operation, DQ7 will be low. If the device is placed in the
Erase Suspend Mode, the status can be detected via the DQ7 pin. If the system tries to read an address which belongs to a block
that is being erased, DQ7 will be high. If a non-erased block address is read, the device will produce the true data to DQ7. If an
attempt is made to program a protected block, DQ7 outputs complements the data for approximately 1µs and the device then returns
to the Read Mode without changing data in the block. If an attempt is made to erase a protected block, DQ7 outputs complement
data in approximately 100us and the device then returns to the Read Mode without erasing the data in the block.
DQ6 : Toggle Bit
Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state,
DQ6 will toggle. Toggling DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase Suspend Mode,
an attempt to read an address that belongs to a block that is being erased will produce a high output of DQ6. If an address belongs
to a block that is not being erased, toggling is halted and valid data is produced at DQ6.
If an attempt is made to program a protected block, DQ6 toggles for approximately 1us and the device then returns to the Read
Mode without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for approximately 100µs
and the device then returns to the Read Mode without erasing the data in the block.
DQ5 : Exceed Timing Limits
If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure.
24
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
DQ3 : Block Erase Timer
The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50µs of the block erase time window expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write
commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block erase
time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been
accepted, the software may check the status of DQ3 following each block erase command.
DQ2 : Toggle Bit 2
The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase Suspend is in progress. When the device
executes the Internal Erase Routine, DQ2 toggles only if an erasing block is read. Although the Internal Erase Routine is in the
Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the Erase
Suspend mode, DQ2 toggles only if an address in the erasing block is read. If a non-erasing block address is read during the Erase
Suspend mode, then DQ2 will produce valid data. DQ2 will go High if the user tries to program a non-erase suspend block while the
device is in the Erase Suspend mode. Combination of the status in DQ6 and DQ2 can be used to distinguish the erase operation
from the program operation.
RY/BY : Ready/Busy
The K8D3216U has a Ready / Busy output that indicates either the completion of an operation or the status of Internal Algorithms. If
the output is Low, the device is busy with either a program or an erase operation. If the output is High, the device is ready to accept
any read/write or erase operation. When the RY/ BY pin is low, the device will not accept any additional program or erase commands
with the exception of the Erase Suspend command. If the K8D3216U is placed in an Erase Suspend mode, the RY/ BY output will be
High. For programming, the RY/ BY is valid (RY/ BY = 0) after the rising edge of the fourth WE pulse in the four write pulse
sequence. For Chip Erase, RY/ BY is also valid after the rising edge of WE pulse in the six write pulse sequence. For Block Erase,
RY/ BY is also valid after the rising edge of the sixth WE pulse.
The pin is an open drain output, allowing two or more Ready/ Busy outputs to be OR-tied. An appropriate pull-up resistor is required
for proper operation.
Rp
VccF
Rp =
VccF (Max.) - VOL (Max.)
IOL +
Σ IL
3.2V
=
2.1mA + Σ IL
Ready / Busy
open drain output
where Σ IL is the sum of the input currents of all devices tied to the
Ready / Busy ball.
Vss
Device
25
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
Start
Read(DQ0~DQ7)
Valid Address
Start
Read(DQ0~DQ7)
Valid Address
Read(DQ0~DQ7)
Valid Address
DQ6 = Toggle ?
DQ7 = Data ?
No
Yes
Yes
No
No
No
DQ5 = 1 ?
DQ5 = 1 ?
Yes
Yes
Read twice(DQ0~DQ7)
Valid Address
Read(DQ0~DQ7)
Valid Address
No
Yes
DQ6 = Toggle ?
DQ7 = Data ?
Yes
No
Fail
Fail
Pass
Pass
Figure 12. Toggle Bit Algorithms
Figure 11. Data Polling Algorithms
Start
RESET=VID
(Note 1)
Perform Erase or
Program Operations
RESET=VIH
Temporary Block
Unprotect Completed
(Note 2)
Notes :
1. All protected block groups are unprotected.
( If WP/ACC = VIL , the two outermost boot blocks remain protected )
2. All previously protected block groups are protected once again.
Figure 13. Temporary Block Group Unprotect Routine
26
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Vcc
Voltage on any pin relative to VSS
Rating
Vcc
-0.5 to +4.0
A9, OE , RESET
-0.5 to +12.5
VIN
WP/ACC
V
-0.5 to +12.5
All Other Pins
Temperature Under Bias
Unit
-0.5 to +4.0
Commercial
-10 to +125
Tbias
Industrial
°C
-40 to +125
Storage Temperature
Tstg
-65 to +150
°C
Short Circuit Output Current
IOS
5
mA
Operating Temperature
TA (Commercial Temp.)
0 to +70
°C
TA (Industrial Temp.)
-40 to + 85
°C
Notes :
1. Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC voltage on
input / output pins is Vcc+0.5V which, during transitions, may overshoot to Vcc+2.0V for periods <20ns.
2. Minimum DC voltage is -0.5V on A9, OE, RESET and WP/ACC pins. During transitions, this level may fall to -2.0V for periods <20ns. Maximum DC
voltage on A9, OE, RESET pins is 12.5V which, during transitions, may overshoot to 14.0V for periods <20ns.
3. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS ( Voltage reference to Vss )
Symbol
Min
Typ.
Max
Unit
Supply Voltage
Parameter
VCC
2.7
3.0
3.6
V
Supply Voltage
VSS
0
0
0
V
DC CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
− 1.0
-
+ 1.0
µA
Input Leakage Current
ILI
VIN=VSS to VCC, VCC=VCCmax
A9,OE,RESET Input Leakage
Current
ILIT
VCC=VCCmax, A9,OE,RESET=12.5V
-
-
35
µA
WP/ACC Input Leakage Current
ILIW
VCC=VCCmax, WP/ACC=12.5V
-
-
35
µA
Output Leakage Current
ILO
VOUT=VSS to VCC,VCC=VCCmax,OE=VIH
µA
− 1.0
-
+ 1.0
5MHz
-
14
20
1MHz
-
3
6
Active Read Current (1)
ICC1
CE=VIL, OE=VIH
Active Write Current (2)
ICC2
CE=VIL, OE=VIH, WE=VIL
-
15
30
mA
Read While Program Current (3)
ICC3
CE=VIL, OE=VIH
-
25
50
mA
Read While Erase Current (3)
ICC4
CE=VIL, OE=VIH
-
25
50
mA
Program While Erase Suspend
Current
ICC5
CE=VIL, OE=VIH
-
15
35
mA
ACC Accelerated Program
Current
IACC
CE=VIL, OE=VIH
ACC Pin
-
5
10
Vcc Pin
-
15
30
Standby Current
ISB1
VCC=VCCmax,CE, RESET=VCC±0.3V
WP/ACC= VCC± 0.3V or Vss±0.3V
-
5
18
µA
Standby Current During Reset
ISB2
VCC=VCCmax, RESET=Vss± 0.3V,
WP/ACC=VCC± 0.3V or Vss±0.3V
-
5
18
µA
Automatic Sleep Mode
ISB3
VIH=VCC±0.3V, VIL=VSS±0.3V,
OE=VIL, IOL=IOH=0
-
5
18
µA
Input Low Level
VIL
-0.5
-
0.8
V
Input High Level
VIH
0.7xVcc
-
VCC+0.3
V
Voltage for WP/ACC Block Temporarily Unprotect and Program Acceleration (4)
VHH
8.5
-
12.5
V
VCC = 3.0V ± 0.3V
27
mA
mA
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
Parameter
FLASH MEMORY
Symbol
Voltage for Autoselect and
Block Protect (4)
Test Conditions
VID
VCC = 3.0V ± 0.3V
Output Low Level
VOL
IOL=100µA, VCC=VCCmin
Output High Level
VOH
IOH=-100µA, Vcc = VCCmin
Low Vcc Lock-out Voltage (5)
VLKO
Min
Typ
Max
Unit
8.5
-
12.5
V
-
-
0.4
V
VCC-0.4
-
-
V
1.8
-
2.5
V
Notes :
1. The ICC current listed includes both the DC operating current and the frequency dependent component(at 5 MHz).
The read current is typically 14 mA (@ VCC=3.0V , OE at VIH.)
2. ICC active during Internal Routine(program or erase) is in progress.
3. ICC active during Read while Write is in progress.
4. The high voltage ( VHH or VID ) must be used in the range of Vcc = 3.0V ± 0.3V
5. Not 100% tested.
6. Typical value are measured at Vcc = 3.0V,TA=25°C , Not 100% tested.
CAPACITANCE(TA = 25 °C, VCC = 3.3V, f = 1.0MHz)
Item
Symbol
Test Condition
Min
Max
Unit
CIN
VIN=0V
-
10
pF
Output Capacitance
COUT
VOUT=0V
-
10
pF
Control Pin Capacitance
CIN2
VIN=0V
-
10
pF
Input Capacitance
Note : Capacitance is periodically sampled and not 100% tested.
AC TEST CONDITION
Parameter
Value
Input Pulse Levels
0V to Vcc
Input Rise and Fall Times
5ns
Input and Output Timing Levels
Vcc/2
Output Load
CL = 30pF
Device
Vcc
Input & Output
Test Point
Vcc/2
Vcc/2
* CL= 30pF including Scope
and Jig Capacitance
CL
0V
Input Pulse and Test Point
Output Load
AC CHARACTERISTICS
Read Operations
VCC=2.7V~3.6V
Parameter
Read Cycle Time (1)
Symbol
-7
-8
Unit
-9
Min
Max
Min
Max
Min
Max
tRC
70
-
80
-
90
-
ns
Address Access Time
tAA
-
70
-
80
-
90
ns
Chip Enable Access Time
tCE
-
70
-
80
-
90
ns
Output Enable Time
tOE
-
25
-
25
-
35
ns
CE & OE Disable Time (1)
tDF
-
16
-
16
-
16
ns
Output Hold Time from Address, CE or OE (1)
tOH
0
-
0
-
0
-
ns
Note : 1. Not 100% tested.
28
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
AC CHARACTERISTICS
Write(Erase/Program)Operations
Alternate WE Controlled Write
VCC=2.7V~3.6V
Parameter
-7
Symbol
Write Cycle Time (1)
tWC
Address Setup Time
-8
-9
Unit
Min
Max
Min
Max
Min
Max
70
-
80
-
90
-
ns
tAS
0
-
0
-
0
-
ns
tASO
55
-
55
-
55
-
ns
tAH
45
-
45
-
45
-
ns
tAHT
0
-
0
-
0
-
ns
Data Setup Time
tDS
35
-
35
-
45
-
ns
Data Hold Time
tDH
0
-
0
-
0
-
ns
Address Hold Time
tOES
0
-
0
-
0
-
ns
Read (1)
tOEH1
0
-
0
-
0
-
ns
Toggle and Data Polling (1)
tOEH2
10
-
10
-
10
-
ns
CE Setup Time
tCS
0
-
0
-
0
-
ns
CE Hold Time
tCH
0
-
0
-
0
-
ns
Write Pulse Width
tWP
35
-
35
-
45
-
ns
Write Pulse Width High
tWPH
25
-
25
-
30
-
ns
Output Enable Setup Time (1)
Output
Enable
Hold Time
Programming Operation
Accelerated Programming
Operation
Word
Byte
Word
Byte
tPGM
14(typ.)
14(typ.)
14(typ.)
µs
9(typ.)
9(typ.)
9(typ.)
µs
tACCPGM
9(typ.)
9(typ.)
9(typ.)
µs
7(typ.)
7(typ.)
7(typ.)
µs
0.7(typ.)
0.7(typ.)
0.7(typ.)
sec
Block Erase Operation (2)
tBERS
VCC Set Up Time
tVCS
50
-
50
-
50
-
µs
Write Recovery Time from RY/BY
tRB
0
-
0
-
0
-
ns
RESET High Time Before Read
tRH
50
-
50
-
50
-
ns
RESET to Power Down Time
tRPD
20
-
20
-
20
-
µs
Program/Erase Valid to RY/BY Delay
tBUSY
90
-
90
-
90
-
ns
tVID
500
-
500
-
500
-
ns
RESET Pulse Width
tRP
500
-
500
-
500
-
ns
RESET Low to RY/BY High
tRRB
-
20
-
20
-
20
µs
VID Rising and Falling Time
RESET Setup Time for Temporary Unprotect
tRSP
1
-
1
-
1
-
µs
RESET Low Setup Time
tRSTS
500
-
500
-
500
-
ns
RESET High to Address Valid
tRSTW
200
-
200
-
200
-
ns
Read Recovery Time Before Write
tGHWL
0
-
0
-
0
-
ns
CE High during toggling bit polling
tCEPH
20
-
20
-
20
-
ns
OE High during toggling bit polling
tOEPH
20
-
20
-
20
-
ns
Notes : 1. Not 100% tested.
2. The duration of the Program or Erase operation varies and is calculated in the internal algorithms.
29
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
AC CHARACTERISTICS
Write(Erase/Program)Operations
Alternate CE Controlled Writes
VCC=2.7V~3.6V
Parameter
Symbol
Write Cycle Time (1)
-7
-8
-9
Unit
Min
Max
Min
Max
Min
Max
70
-
80
-
90
-
tWC
ns
Address Setup Time
tAS
0
-
0
-
0
-
ns
Address Hold Time
tAH
45
-
45
-
45
-
ns
Data Setup Time
tDS
35
-
35
-
45
-
ns
Data Hold Time
tDH
0
-
0
-
0
-
ns
tOES
0
-
0
-
0
-
ns
Read (1)
tOEH1
0
-
0
-
0
-
ns
Toggle and Data Polling (1)
tOEH2
10
-
10
-
10
-
ns
WE Setup Time
tWS
0
-
0
-
0
-
ns
WE Hold Time
tWH
0
-
0
-
0
-
ns
CE Pulse Width
tCP
35
-
35
-
45
-
ns
CE Pulse Width High
tCPH
25
-
25
-
30
-
ns
Output Enable Setup Time (1)
Output
Enable
Hold Time
Programming Operation
Accelerated Programming
Operation
Word
tPGM
Byte
Word
14(typ.)
14(typ.)
14(typ.)
µs
9(typ.)
9(typ.)
9(typ.)
µs
9(typ.)
9(typ.)
9(typ.)
µs
7(typ.)
7(typ.)
7(typ.)
µs
tACCPGM
Byte
Block Erase Operation (2)
tBERS
BYTE Switching Low to Output HIGH-Z
tFLQZ
0.7(typ.)
25
0.7(typ.)
-
25
0.7(typ.)
-
30
sec
-
ns
Notes : 1. Not 100% tested.
2.This does not include the preprogramming time.
ERASE AND PROGRAM PERFORMANCE
Limits
Parameter
Unit
Min
Typ
Max
Block Erase Time
-
0.7
15
sec
Chip Erase Time
-
49
-
sec
Word Programming Time
-
14
330
µs
Chip Programming Time
Erase/Program Endurance
Excludes 00H programming
prior to erasure
Excludes system-level overhead
-
9
210
µs
Excludes system-level overhead
Word Mode
-
9
210
µs
Excludes system-level overhead
Excludes system-level overhead
Byte Programming Time
Accelerated Byte/Word
Program Time
Comments
Byte Mode
-
7
150
µs
Word Mode
-
28
84
sec
Byte Mode
-
36
108
sec
100,000
-
-
cycles
Excludes system-level overhead
Minimum 100,000 cycles guaranteed
Notes : 1. 25 °C, VCC = 3.0V 100,000 cycles, typical pattern.
2. System-level overhead is defined as the time required to execute the four bus cycle command necessary to program each byte.
In the preprogramming step of the Internal Erase Routine, all bytes are programmed to 00H before erasure.
30
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
SWITCHING WAVEFORMS
Read Operations
tRC
Address Stable
Address
tAA
CE
tOE
tDF
OE
tOEH1
WE
tCE
tOH
HIGH-Z
Outputs
HIGH-Z
Output Valid
HIGH
RY/BY
Parameter
-7
Symbol
-8
-9
Unit
Min
Max
Min
Max
Min
Max
tRC
70
-
80
-
90
-
ns
Address Access Time
tAA
-
70
-
80
-
90
ns
Chip Enable Access Time
tCE
-
70
-
80
-
90
ns
Output Enable Time
tOE
-
25
-
25
-
35
ns
CE & OE Disable Time (1)
tDF
-
16
-
16
-
16
ns
tOH
0
-
0
-
0
-
ns
tOEH1
0
-
0
-
0
-
ns
Read Cycle Time
Output Hold Time from Address, CE or OE
OE Hold Time
Note : 1. Not 100% tested.
31
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
SWITCHING WAVEFORMS
Hardware Reset/Read Operations
tRC
Address Stable
Address
tAA
CE
tRH
tRP
tRH
tCE
RESET
tOH
High-Z
Outputs
Parameter
Output Valid
-7
Symbol
-8
-9
Unit
Min
Max
Min
Max
Min
Max
tRC
70
-
80
-
90
-
ns
Address Access Time
tAA
-
70
-
80
-
90
ns
Chip Enable Access Time
tCE
-
70
-
80
-
90
ns
Read Cycle Time
Output Hold Time from Address, CE or OE
tOH
0
-
0
-
0
-
ns
RESET Pulse Width
tRP
500
-
500
-
500
-
ns
RESET High Time Before Read
tRH
50
-
50
-
50
-
ns
32
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
SWITCHING WAVEFORMS
Alternate WE Controlled Program Operations
tAS
PA
555H
Address
Data Polling
PA
tRC
tAH
CE
tOES
OE
tWC
tCH
tPGM
tWP
WE
tWPH
tCS
tDF
tDH
A0H
DATA
tOE
PD
Status
DOUT
tBUSY
tDS
tCE
tRB
tOH
RY/BY
Notes : 1. DQ7 is the output of the complement of the data written to the device.
2. DOUT is the output of the data written to the device.
3. PA : Program Address, PD : Program Data
4. The illustration shows the last two cycles of the program command sequence.
Parameter
Symbol
-7
Min
-8
Max
Min
-9
Max
Min
Max
Unit
Write Cycle Time
tWC
70
-
80
-
90
-
ns
Address Setup Time
tAS
0
-
0
-
0
-
ns
Address Hold Time
tAH
45
-
45
-
45
-
ns
Data Setup Time
tDS
35
-
35
-
45
-
ns
Data Hold Time
tDH
0
-
0
-
0
-
ns
CE Setup Time
tCS
0
-
0
-
0
-
ns
CE Hold Time
tCH
0
-
0
-
0
-
ns
OE Setup Time
tOES
0
-
0
-
0
-
ns
Write Pulse Width
tWP
35
-
35
-
45
-
ns
Write Pulse Width High
tWPH
25
-
25
-
30
-
ns
Programming Operation
Accelerated Programming
Operation
Word
Byte
Word
Byte
tPGM
14(typ.)
14(typ.)
14(typ.)
us
9(typ.)
9(typ.)
9(typ.)
us
9(typ.)
9(typ.)
9(typ.)
µs
7(typ.)
7(typ.)
7(typ.)
µs
tACCPGM
Read Cycle Time
tRC
70
-
80
-
90
-
ns
Chip Enable Access Time
tCE
-
70
-
80
-
90
ns
Output Enable Time
tOE
-
25
-
25
-
35
ns
CE & OE Disable Time
tDF
-
16
-
16
-
16
ns
Output Hold Time from Address, CE or OE
Program/Erase Valide to RY/BY Delay
Recovery Time from RY/BY
tOH
0
-
0
-
0
-
ns
tBUSY
90
-
90
-
90
-
ns
tRB
0
-
0
-
0
-
ns
33
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
SWITCHING WAVEFORMS
Alternate CE Controlled Program Operations
tAS
555H
Address
Data Polling
PA
PA
tAH
WE
tOES
OE
tWC
tPGM
tCP
CE
tCPH
tWS
tDH
PD
A0H
DATA
DOUT
Status
tDS
tBUSY
tRB
RY/BY
Notes :
1. DQ7 is the output of the complement of the data written to the device.
2. DOUT is the output of the data written to the device.
3. PA : Program Address, PD : Program Data
4. The illustration shows the last two cycles of the program command sequence.
Parameter
Symbol
Write Cycle Time
tWC
-7
-8
-9
Min
Max
Min
Max
Min
Max
70
-
80
-
90
-
Unit
ns
Address Setup Time
tAS
0
-
0
-
0
-
ns
Address Hold Time
tAH
45
-
45
-
45
-
ns
Data Setup Time
tDS
35
-
35
-
45
-
ns
Data Hold Time
tDH
0
-
0
-
0
-
ns
OE Setup Time
tOES
0
-
0
-
0
-
ns
WE Setup Time
tWS
0
-
0
-
0
-
ns
WE Hold Time
tWH
0
-
0
-
0
-
ns
CE Pulse Width
tCP
35
-
35
-
45
-
ns
tCPH
25
-
25
-
30
-
CE Pulse Width High
Programming Operation
Accelerated Programming
Operation
Word
Byte
Word
Byte
Program/Erase Valide to RY/BY Delay
Recovery Time from RY/BY
tPGM
µs
9(typ.)
9(typ.)
µs
9(typ.)
9(typ.)
µs
14(typ.)
9(typ.)
9(typ.)
tACCPGM
7(typ.)
ns
14(typ.)
14(typ.)
7(typ.)
µs
7(typ.)
tBUSY
90
-
90
-
90
-
ns
tRB
0
-
0
-
0
-
ns
34
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
SWITCHING WAVEFORMS
Word to Byte Timing Diagram for Read Operation
tCE
CE
OE
BYTE
tELFL
Data Output
(DQ0-DQ7)
DQ0-DQ7
DQ8-DQ14
Data Output
(DQ8-DQ14)
DQ15/A-1
Data Output
(DQ15)
Address Input (A-1)
tFLQZ
Byte to Word Timing Diagram for Read Operation
tCE
CE
OE
BYTE
tELFH
Data Output
(DQ0-DQ7)
DQ0-DQ7
Data Output
(DQ8-DQ14)
DQ8-DQ14
Address Input
(A-1)
DQ15/A-1
Data Output
(DQ15)
tFHQV
BYTE Timing Diagram for Write Operation
CE
The falling edge of the last WE signal
WE
BYTE
tSET
(tAS)
Parameter
tHOLD(tAH)
-7
Symbol
-8
-9
Min
Max
Min
Max
Min
Max
Unit
tCE
-
70
-
80
-
90
ns
tELFL/tELFH
-
5
-
5
-
5
ns
BYTE Switching Low to Output HIGH-Z
tFLQZ
-
25
-
25
-
30
ns
BYTE Switching High to Output Active
tFHQV
-
25
-
25
-
35
ns
Chip Enable Access Time
CE to BYTE Switching Low or High
35
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
SWITCHING WAVEFORMS
Chip/Block Erase Operations
tAS
555H
Address
555H for Chip Erase
2AAH
555H
555H
2AAH
BA
tAH
tRC
CE
tOES
OE
tWC
tWP
WE
tWPH
tCS
tDH
AAH
DATA
10H for Chip Erase
55H
80H
AAH
55H
30H
tDS
RY/BY
Vcc
tVCS
Note : BA : Block Address
Parameter
Symbol
-7
-8
-9
Min
Max
Min
Max
Min
Max
Unit
Write Cycle Time
tWC
70
-
80
-
90
-
ns
Address Setup Time
tAS
0
-
0
-
0
-
ns
Address Hold Time
tAH
45
-
45
-
45
-
ns
Data Setup Time
tDS
35
-
35
-
45
-
ns
Data Hold Time
tDH
0
-
0
-
0
-
ns
OE Setup Time
tOES
0
-
0
-
0
-
ns
CE Setup Time
tCS
0
-
0
-
0
-
ns
Write Pulse Width
tWP
35
-
35
-
45
-
ns
Write Pulse Width High
tWPH
25
-
25
-
30
-
ns
Read Cycle Time
tRC
70
-
80
-
90
-
ns
VCC Set Up Time
tVCS
50
-
50
-
50
-
µs
36
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
SWITCHING WAVEFORMS
Read While Write Operations
Read
Command
Read
Command
Read
Read
tRC
tWC
tRC
tWC
tRC
tRC
DA1
DA2
(PA)
Address
DA2
(555H)
DA1
tAS
DA2
(PA)
DA1
tAH
tAS
tAA
tAHT
tCE
CE
tOE
tCEPH
OE
tDF
tOES
tOEH2
tWP
WE
tDF
tDH
tDS
Valid
Output
DQ
Valid
Input
Valid
Output
Valid
Input
(A0H)
Valid
Output
Status
(PD)
Note : This is an example in the program-case of the Read While Write function.
DA1 : Address of Bank1, DA2 : Address of Bank 2
PA = Program Address at one bank , RA = Read Address at the other bank, PD = Program Data In , RD = Read Data Out
Parameter
Symbol
-7
-8
-9
Unit
Min
Max
Min
Max
Min
Max
tWC
70
-
80
-
90
-
ns
Write Pulse Width
tWP
35
-
35
-
45
-
ns
Write Pulse Width High
tWPH
25
-
25
-
30
-
ns
Write Cycle Time
Address Setup Time
tAS
0
-
0
-
0
-
ns
Address Hold Time
tAH
45
-
45
-
45
-
ns
Data Setup Time
tDS
35
-
35
-
45
-
ns
Data Hold Time
tDH
0
-
0
-
0
-
ns
Read Cycle Time
tRC
70
-
80
-
90
-
ns
Chip Enable Access Time
tCE
-
70
-
80
-
90
ns
Address Access Time
tAA
-
70
-
80
-
90
ns
Output Enable Access Time
tOE
-
25
-
25
-
35
ns
OE Setup Time
tOES
0
-
0
-
0
-
ns
OE Hold Time
tOEH2
10
-
10
-
10
-
ns
CE & OE Disable Time
tDF
-
16
-
16
-
16
ns
Address Hold Time
tAHT
0
-
0
-
0
-
ns
CE High during toggle bit polling
tCEPH
20
-
20
-
20
-
ns
37
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
SWITCHING WAVEFORMS
Data Polling During Internal Routine Operation
CE
tDF
tOE
OE
tOEH2
WE
tCE
tOH
DQ7
Data In
DQ7
HIGH-Z
*DQ7 = Valid Data
tPGM or tBERS
DQ0-DQ6
Data In
HIGH-Z
Valid Data
Status Data
Note : *DQ7=Vaild Data (The device has completed the internal operation).
RY/BY Timing Diagram During Program/Erase Operation
CE
The rising edge of the last WE signal
WE
Entire progrming
or erase operation
RY/BY
tBUSY
Parameter
Program/Erase Valid to RY/BY Delay
-7
Symbol
Min
-8
Max
Min
-9
Max
Min
Max
Unit
tBUSY
90
-
90
-
90
-
ns
Chip Enable Access Time
tCE
-
70
-
80
-
90
ns
Output Enable Time
tOE
-
25
-
25
-
35
ns
CE & OE Disable Time
tDF
-
16
-
16
-
16
ns
Output Hold Time from Address, CE or OE
OE Hold Time
tOH
0
-
0
-
0
-
ns
tOEH2
10
-
10
-
10
-
ns
38
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
SWITCHING WAVEFORMS
Toggle Bit During Internal Routine Operation
tAS
tAHT
Address*
tAHT
tASO
CE
tOEH2
tCEPH
WE
tOEPH
OE
tDH
tOE
Status
Data
Status
Data
Status
Data
Data In
DQ6/DQ2
Array Data Out
RY/BY
Note : Address for the write operation must include a bank address (A19~A20) where the data is written.
Enter
Embedded
Erasing
Erase
Suspend
Erase
WE
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Resume
Erase
Suspend
Program
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Toggle
DQ2 and DQ6
with OE or CE
Note : DQ2 is read from the erase-suspended block.
Parameter
Symbol
-7
-8
-9
Unit
Min
Max
Min
Max
Min
Max
tOE
-
25
-
25
-
35
ns
OE Hold Time
tOEH2
10
-
10
-
10
-
ns
Address Hold Time
tAHT
0
-
0
-
0
-
ns
Address Setup
tASO
55
-
55
-
55
-
ns
Address Setup Time
tAS
0
-
0
-
0
-
ns
Output Enable Access Time
tDH
0
-
0
-
0
-
ns
CE High during toggle bit polling
tCEPH
20
-
20
-
20
-
ns
OE High during toggle bit polling
tOEPH
20
-
20
-
20
-
ns
Data Hold Time
39
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
SWITCHING WAVEFORMS
RESET Timing Diagram
High
RY/BY
CE or OE
tRH
RESET
tRP
tREADY
Reset Timings NOT during Internal Routine
tREADY
RY/BY
tRB
CE or OE
tRP
RESET
Reset Timings during Internal Routine
Power-up and RESET Timing Diagram
tRSTS
RESET
Vcc
Address
DATA
tAA
Parameter
RESET Pulse Width
Symbol
-7
-8
-9
Min
Max
Min
Max
Min
Max
Unit
tRP
500
-
500
-
500
-
ns
RESET Low to Valid Data
(During Internal Routine)
tREADY
-
20
-
20
-
20
µs
RESET Low to Valid Data
(Not during Internal Routine)
tREADY
-
500
-
500
-
500
ns
tRH
50
-
50
-
50
-
ns
RESET High Time Before Read
RY/BY Recovery Time
tRB
0
-
0
-
0
-
ns
RESET High to Address Valid
tRSTW
200
-
200
-
200
-
ns
RESET Low Set-up Time
tRSTS
500
-
500
-
500
-
ns
40
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
SWITCHING WAVEFORMS
Block Group Protect & Unprotect Operations
VID
RESET
Vss,VIL,
or VIH
Vss,VIL,
or VIH
BGA,A6
A1,A0
Valid
Valid
Block Group Protect / Unprotect
DATA
60H
Valid
Verify
40H
60H
Status*
Block Group Protect:150µs
Block Group UnProtect:15ms
1µs
CE
WE
tRB
OE
tBUSY
RY/BY
Notes : Block Group Protect (A6=VIL , A1=VIH , A0=VIL) , Status=01H
Block Group Unprotect (A6=VIH , A1=VIH, A0=VIL) , Status=00H
BGA = Block Group Address (A12 ~ A20)
Temporary Block Group Unprotect
VID
RESET
Vss,VIL,
or VIH
Vss,VIL,
or VIH
CE
WE
tVID
tRSP
Program or Erase Command Sequence
tRRB
tVID
RY/BY
41
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)
Unit :mm/Inch
0.10
MAX
0.004
48 - TSOP1 - 1220F
#48
#24
#25
0.50
0.0197
12.40
0.488 MAX
( 0.25 )
0.010
#1
12.00
0.472
+0.003
0.008-0.001
0.20 -0.03
+0.07
20.00±0.20
0.787±0.008
1.00±0.05
0.039±0.002
0.05
0.002 MIN
+0.075
0~8’C
0.45~0.75
0.018~0.030
+0.003
0.005-0.001
18.40±0.10
0.724±0.004
0.125 -0.035
0.25
0.010 TYP
1.20
0.047MAX
( 0.50 )
0.020
42
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
PACKAGE DIMENSIONS
48-Ball Tape Ball Grid Array Package (measured in millimeters)
Top View
Bottom View
6.00±0.10
A
6.00±0.10
0.80 x 5=4.00
6
(Datum A)
5
4
3
2
B
1
0.80
A
B
0.80x7=5.60
8.50±0.10
C
D
E
2.80
F
8.50±0.10
(Datum B)
0.80
#A1
G
H
48-∅ 0.45±0.05
∅ 0.20 M A B
2.00
0.90±0.10
0.45±0.05
0.32±0.05
Side View
0.08MAX
8.50±0.10
43
Revision 1.5
June 2005
K8D3x16UTC / K8D3x16UBC
FLASH MEMORY
PACKAGE DIMENSIONS
48-Ball Fine Ball Grid Array Package (measured in millimeters)
Top View
Bottom View
6.00±0.10
A
6.00±0.10
0.80 x 5=4.00
6
(Datum A)
5
4
3
2
B
1
0.80
A
B
0.80x7=5.60
8.50±0.10
C
D
E
2.80
F
8.50±0.10
(Datum B)
0.80
#A1
G
H
48-∅ 0.45±0.05
∅ 0.20 M A B
2.00
0.90±0.10
0.45±0.05
0.32±0.05
Side View
0.08MAX
8.50±0.10
44
Revision 1.5
June 2005
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