datasheet for PUMA2SV16000 by Apta Group

datasheet for PUMA2SV16000 by Apta Group
512K x 32 SRAM MODULE
PUMA 2/77SV16000/A - 020/025/35
Issue 1.1 : April 2001
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
Description
16,777,216 bit CMOS High Speed Static RAM
Available in PGA (PUMA 2 ) and Gullwing (PUMA 77) Features
footprints, the PUMA **SV16000 is a 3.3V 16 MBit • 16MBit Fast SRAM Module.
SRAM module user configurable as 512K x 32, 1M x 16 • Fast Access times of 20/25/35ns.
or 2M x 8. The device is available with fast access times
• Configurable as 8 / 16 / 32 bit wide output.
of 20, 25 and 30ns. The device may be screened in
• Operating Power 1330 / 1800 / 2850 mW (max).
accordance with MIL-STD-883.
Standby CMOS 795mW (max).
• Single 3.3V±10% Power supply.
• TTL compatible inputs and outputs.
• May be screened in accordance with MIL-STD-883.
• PUMA 2 - 66 pin ceramic PGA
• PUMA77 - 68 pin ceramic Gullwing
Block Diagram
Block Diagram
PUMA 2SV16000 , 77SV16000A,77SV16000B
PUMA 77SV16000
A0~A18
A0~A18
OE
WE
OE
WE4
WE3
WE2
WE1
512K x 8
512K x 8
SRAM
512K x 8
512K x 8
512K x 8
SRAM
SRAM
SRAM
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
SRAM
512K x 8
SRAM
512K x 8
512K x 8
SRAM
SRAM
CS1
CS2
CS3
CS4
D0~7
D8~15
D16~23
D24~31
Pin Functions
A0~A18
CS1~4
WE1~4
VCC
Address Inputs
Chip Select
Write Enable
Power (+5V)
D0~D31
OE
NC
GND
Data Inputs/Outputs
Output Enable
No Connect
Ground
PUMA 2/77SV16000 - 020/025/35
Issue 1.1 : April 2001
DC OPERATING CONDITIONS
Absolute Maximum Ratings (1)
Voltage on any pin relative to Vss (2)
Power Dissipation
Storage Temperature
Notes
VT
-0.5V to +4.6
PD
4
TSTG -55 to +150
V
W
°
C
(1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
min
Supply Voltage
V CC
3.0
Input High Voltage
VIH
2.0
Input Low Voltage
VIL
-0.3
Operating Temperature
TA
0
TAI
-40
TAM
-55
typ
3.3
-
max
3.6
VCC+0.3
0.8
70
85
125
units
V
V
V
°
C
°
C (Suffix I)
°
C (Suffix M, MB)
DC Electrical Characteristics (VCC=3.3V±10%,TA=-55°C to +125°C)
Parameter
Symbol Test Condition
Input Leakage Current Address,OE
WE, CS
Output Leakage Current
ILI1
ILI2
ILO
VIN = 0V to VCC
VIN = 0V to VCC
CS(2) = VIH or OE = VIH, VI/O = 0V to VCC
min
typ(1)
max Unit
-8
-2
-8
-
8
2
8
µA
µA
µA
-
790
500
370
mA
mA
mA
WE(2) = VIL
Average Supply Current
32 bit
ICC32
CS(2)=VIL, Minumum cycle, II/O = 0mA
WE(2)=VIL or WE(2)=OE=VIH, 100% duty.
16 bit
8 bit
Standby Supply Current
Output Voltage Low
Output Voltage High
TTL levels
ICC16
ICC8
As above
-
ISB
CS(2) = VIH ,VCC=5.5V
-
-
240
mA
VOL
VOH
IOH = -4.0 mA
2.4
-
0.4
-
V
V
As above
IOL = 8.0 mA
Notes: (1) Typical values are at VCC=3.3V,TA=25°C and specified loading.
(2) CS and WE above are accessed through CS1~4 and WE1~4 respectively. These inputs must be operated
simultaneously for 32 bit mode, in pairs for 16 bit mode and singly for 8 bit mode.
2
PUMA 2/77SV16000 - 020/025/35
Issue 1.1 : April 2001
Capacitance (VCC=3.3V±10%,TA=25°C) Note: These parameters are calculated and not measured.
Parameter
Symbol
Input Capacitance Address, OE
WE1~4, CS1~4
I/O Capacitance
D0~31
CIN1
CIN2
CI/O
Test Condition
typ
max
VIN =0V
VIN =0V
VI/O=0V
-
34
6
42
Unit
pF
pF
pF (8 bit mode)
Operating Modes
The Table below shows the logic inputs required to control the operating modes of each of the SRAMs on the
device.
Mode
CS
OE
WE
Not Selected
1
X
X
Output Disable
0
1
Read
0
Write
0
VCC Current
I/O Pin
Reference Cycle
ISB1,ISB2
High Z
Power Down
1
ICC
High Z
0
1
ICC
DOUT
Read cycle
X
0
ICC
DIN
Write Cycle
1 = VIH,
0 = VIL,
X = Don't Care
Note: CS above is accessed through CS1~4 and WE is accessed through WE1~4. For correct operation, CS1~ 4 and
WE1~4 must operate simultaneously for 32 bit operation, in pairs for 16 bit operation, or singly for 8 bit operation.
AC Test Conditions
Output Load
I/O Pin
*Input pulse levels: 0.0V to 3.0V
*Input rise and fall times: 3 ns
*Input and Output timing reference levels: 1.5V
*Vcc=3.3V±10%
*PUMA module is tested in 32 bit mode.
166 Ω
1.76V
30pF
3
PUMA 2/77SV16000 - 020/025/35
Issue 1.1 : April 2001
AC OPERATING CONDITIONS
Read Cycle
Parameter
Symbol
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to Output in High Z(3)
Output Disable to Output in High Z(3)
tRC
tAA
tACS
tOE
tOH
tCLZ
tOLZ
tCHZ
tOHZ
020
min max
025
min max
min
20
5
5
5
0
25
5
5
0
0
0
35
5
5
0
0
0
20
20
10
10
10
25
25
15
10
10
35
max
35
35
15
10
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
020
Symbol min max
tWC
tCW
tAW
tAS
tWP
tWR
tWHZ
tDW
tDH
tOW
20
15
15
0
15
0
0
10
0
5
10
-
4
025
min max
min
25
15
15
0
15
0
0
10
0
5
35
15
15
0
15
0
0
10
0
5
10
-
35
max Unit
10
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PUMA 2/77SV16000 - 020/025/35
Issue 1.1 : April 2001
Read Cycle Timing Waveform (1,2)
t
RC
Address
t AA
OE
t OE
t OH
t OLZ
t CLZ
CS1~4
t ACS
t CHZ(3)
t OHZ(3)
High-Z
D0~31
Data Valid
Notes:
(1) During the Read Cycle, WE is high for the module.
(2) Address valid prior to or coincident with CS transition Low.
(3) tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced
to output voltage levels. These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
t WC
A0~A18
OE
t AS(3)
t AW
tWR
t CW(4)
(2)
(6)
CS1~4
t WP(1)
WE1~4
t OHZ(3,9)
D0~31out
D0~31in
t OW
High-Z
t DW
High-Z
5
t DH
PUMA 2/77SV16000 - 020/025/35
Issue 1.1 : April 2001
Write Cycle No.2 Timing Waveform (5)
t WC
A0~A18
tCW
CS1~4
(4)
(6)
t AW
t WR(2)
t WP(1)
WE1~4
t AS(3)
t OH
t WHZ(3,9)
t OW
D0~31out
t DW
D0~31in
(8)
(7)
High-Z
tDH
High-Z
AC Characteristics Notes
(1) A write occurs during the overlap (tWP) of a low CS and a low WE.
(2) tWR is measured from the earlier of CS or WE going high to the end of write cycle.
(3) During this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(4) If the CS low transition occurs simultaneously with the WE low transition or after the WE low transition, outputs remain
in a high impedance state.
(5) OE is continuously low. (OE=VIL)
(6) DOUT is in the same phase as written data of this write cycle.
(7) DOUT is the read data of next address.
(8) If CS is low during this period, I/O pins are in the output state. Input signals out of phase must not be applied.
(9) tWHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to
output voltage levels. These parameters are sampled and not 100% tested.
6
PUMA 2/77SV16000 - 020/025/35
Issue 1.1 : April 2001
Package Details
PUMA 77SV16000
25.15 (0.990) sq.
24.67 (0.970) sq.
24.13 (0.950) sq.
23.62 (0.930) sq.
1.27
(0.050)
0.43
(0.017)
20.57 (0.810) sq.
20.10 (0.790) sq.
0.76
(0.030)
1.78
(0.070)
22.61 (0.890) sq.
22.10 (0.870) sq.
5.44
(0.214) max
0.10 (0.004)
PUMA 2SV16000
27.69 (1.090) square
2.54 (0.010)
4.83 (0.190)
4.32 (0.170)
27.08 (1.066) square
15.24 (0.60) typ
3.81 (0.150) ref
0.53 (0.021)
0.38 (0.015)
1.27 (0.050)
1.27 (0.050)
1.66 (0.026)
LEAD FINISH IS 300 INCH MINIMUM
SOLDER OVER 50 TO 350 INCH NICKEL
6.86 (0.270) max
1.52 (0.060)
1.02 (0.040)
7
2.54 (0.010)
10.67 (0.420)
10.16 (0.400)
Pin Definitions
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
A10
Vcc
A9
A8
A7
CS4
WE1
A6
GND
A5
CS3
A4
A2
A3
NC
A0
A1
A10
Vcc
A9
A8
PUMA 77SV16000A
A7
CS4
WE
A6
GND
A5
CS3
A2
A3
A4
NC
A0
A1
PUMA 77SV16000
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
D0
10
60
D16
D0
10
60
D16
D1
11
59
D17
D1
11
59
D17
D2
12
58
D18
D2
12
58
D18
D3
13
57
D19
D3
13
57
D19
D4
14
56
D20
55
D21
54
D22
53
D23
52
GND
51
D24
D25
D4
14
56
D20
D5
15
55
D21
D5
15
D6
16
17
54
53
D22
D6
16
VIEW
D23
D7
17
52
GND
GND
FROM
18
51
D24
D8
19
D25
D9
20
50
D7
VIEW
FROM
GND
18
D8
19
D9
20
50
D10
21
49
D26
D10
21
49
D26
D11
22
48
D27
D12
23
47
D28
D13
24
46
D29
D14
25
45
D30
D15
26
44
D31
D11
22
48
D27
D12
23
47
D28
D13
24
46
D29
D14
25
45
D30
44
D31
NC
GND
A18
WE3
WE4
A17
WE2
OE
CS2
CS1
A16
Vcc
A11
PUMA 77SV16000B
A15
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC
GND
A18
NC
NC
NC
A17
OE
CS2
A16
CS1
A15
A14
A13
A12
Vcc
A11
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A14
26
A13
D15
ABOVE
A12
ABOVE
NC
A0
A1
A2
A3
A4
A5
CS3
GND
CS4
WE1
A6
A7
A8
A9
A10
Vcc
PUMA 2SV16000
WE2
WE3
WE4
A18
NC
NC
A17
VIEW
FROM
ABOVE
Vcc
A11
A12
A13
A14
A15
A16
CS1
OE
CS2
D0
D1
D2
D3
D4
D5
D6
D7
GND
D8
D9
D10
D11
D12
D13
D14
D15
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
D16
D17
D18
D19
D20
D21
D22
D23
GND
D24
D25
D26
D27
D28
D29
D30
D31
1
12
23
34
45
56
D8
2
WE2
13
D15
24
D24
35
VCC
46
D31
57
D9
3
CS2
14
D14
25
D25
36
D10
4
GND
15
D13
26
D26
37
CS4
47
WE4
48
D30
58
D29
59
A13
5
D11
16
D12
27
A6
38
D27
49
D28
60
A14
6
A10
17
OE
28
A7
39
A3
50
A0
61
A15
A11
18
A17
29
NC
40
A4
51
A1
62
A16
8
A12
WE1
19
30
A8
41
A5
52
A18
9
VCC
20
31
A9
42
WE3
53
A2
63
D23
64
D0
10
CS1
21
D1
NC
D5
D16
43
D17
CS3
54
GND
D22
65
D21
11
22
33
D2
D3
D4
44
D18
55
D19
66
D20
7
D7
D6
32
VIEW
FROM
ABOVE
Military Screening Procedure
MultiChip Screening Flow for high reliability product in accordance with Mil-883 method 5004 shown below
MB MULTICHIP MODULE SCREENING FLOW
SCREEN
TEST METHOD
LEVEL
2017 Condition B or manufacturers equivalent
1010 Condition B (10 Cycles,-55°C to +125°C)
2001 Condition E (Y1 only) (10,000g)
100%
100%
100%
Pre-Burn-in electrical
Burn-in
Per applicable device specifications at TA=+25°C
Method 1015,Condition D,TA=+125°C,160hrs min
100%
100%
Final Electrical Tests
Per applicable Device Specification
Static (dc)
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Functional
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Switching (ac)
a) @ TA=+25°C and power supply extremes
b) @ temperature and power supply extremes
100%
100%
Percent Defective allowable (PDA)
Calculated at post burn-in at TA=+25°C
10%
Visual and Mechanical
Internal visual
Temperature cycle
Constant acceleration
Burn-In
Hermeticity
1014
Fine
Gross
Condition A
Condition C
100%
100%
Quality Conformance
Per applicable Device Specification
Sample
External Visual
2009 Per vendor or customer specification
100%
PUMA 2/77SV16000 - 020/025/35
Issue 1.1 : April 2001
Ordering Information
PUMA 2SV16000AMB-020
Speed
020
025
35
=
=
=
20 ns
25 ns
35 ns
Temp. range/screeningBlank
I
M
MB
=
=
=
=
Commercial Temperature
Industrial Temperature
Military Temperature
Processed in accordance with
MIL-STD-883
WE Option
=
Single WE (PUMA 77 only)
WE1~4 (PUMA 2 only)
WE1~4 (PUMA 77 only)
Blank
Organisation
Technology
Package
A
=
B
=
Pinout Variant
16000
=
512Kx 32, user confiurable as
1M x 16 and 2M x 8
SV
=
SRAM Memory, 3.3V + 10% VCC
PUMA 2
=
JEDEC 66 Pin Ceramic PGA
package
PUMA 77
=
JEDEC 68 Leaded Gull Wing
Ceramic Surface Mount package
Note :
Although this data is believed to be accurate, the information contained herein is not intended to and does not create any
warranty of merchantibility or fitness for a particular purpose.
Our products are subject to a constant process of development. Data may be changed at any time without notice.
Products are not authorised for use as critical components in life support devices without the express written approval of
a company director.
10
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