A fully integrated 2.45GHz 0.25um CMOS power amplifier

A fully integrated 2.45GHz 0.25um CMOS power amplifier
Ellie Cijvat and Henrik Sjolund
Dept. of Electroscience, Lund University, PO Box 118,221 00 Lund, Sweden
ellie.cijvat@es.lth.se,henrik.sjoland@es.lth.se+46-46 222 3020
A fully integrated differential class-AB power amplifier
has been designed in a 0.25um CMOS technology. It is
intended for medium output power ranges such as Bluetooth class I, and has an operating frequency of 2.45GHz.
By using two parallel output stages that can he switched
on or off, a high efficiency can be achieved for both high
and low output power levels. The simulated maximum
output power is 22.7 dBm, while the maximum poweradded efficiency is 22%.
With the recent emergence of shon-range communication
standards such as Bluetooth, the research interest for
highly integrated power amplifiers (PAS)has increased [I131. For frequencies up to several GHz and low to
medium output power, CMOS may be an alternative to
stand-alone power amplifiers, offering a higher level of
integration in a relatively cheap technology, in exchange
for less efficiency and a lower maximum output power.
In most communication systems transmitter output
power control is required. In order to increase the battery
lifetime, it is important to have a relatively high efficiency
over the whole PA output power range, i.e. for both lower
and higher output power, since the PA is more likely to
operate at lower than higher output power.
For the Bluetooth standard the highest output power is
20 dBm (class I, 1141) which is feasible for CMOS implementation (see [1-131). Moreover, a constant envelope
modulation scheme is used, implying that linearity of the
PA is not a critical issue for this standard.
In this work a class-AB power amplifier is described
that consists of two stages, with the output stage comprising two parallel blocks that may be switched on or off(see
fig. 2). In this way the efficiency may he optimized for different output power settings. The output impedance transformation network is fully integrated.
The paper is structured as follows: First some PA theory
is described, then the design itself is presented. Simulation
results are shown in Section 4, and finally conclusions are
R.pt n
Figure 1. Principle of impedance transformation.
In fig. 1 a current source with impedance transformation
network T i s shown. This serves as a model for an ideal
output stage, where the transistor operates as a controlled
current source driving Rapt,the transformed load impedance R,. The maximum signal amplitude is VDD, and the
ideal maximum output power is given by
Thus, for a given VDD,Rapt determines Pout,,, assuming a maximum voltage swing. For
= 22 dBm and
V,, = 3.3 V, the optimum load resistance hPt
is equal to
The power added efficiency (PAE) is defined as
where PDc is the power supplied by the battery, which is
signal-dependent for most types of PAS. The PAE typically is maximum for an output power close to Po,,,,,
and decreasing fast for lower output powers [ 5 ] . Therefore, for a high average efficiency, the PA may he
designed to have different
by changing hPt
VDD In this work the former strategy is used.
For high voltage swings the transistor will enter the linear
region, and no longer behave as an ideal current source.
This is commonly modeled with the knee voltage V,,
[15]. The output voltage swing is reduced to VDD - V,,,
and the maximum output power may he written as
0-7803-8163-7/03/$17.00 Q 2003 IEEE
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Assuming an output stage with an integrated currentsupplying inductor and a switch at VDD. allowing the
whole stage to be turned on or off,other non-idealities
may he identified such as the series resistance of the
inductor and the on-resistance of the supply switch, both
reducing the bias voltage at the drain. Moreover, the finite
output impedance of the transistor and the finite quality
factor Q of the passives in the matching network will
cause power loss. To compensate for these losses, a PA is
generally designed for a higher Poutmarby reducing Rap,
in Eq. 3.
A fully integrated 2.45 GHz PA was implemented in a
0.25um CMOS technology. In order to implement different output power settings and increase the average efficiency, two parallel output blocks were used (see fig. 2).
Due to die size considerations the number of parallel
blocks was limited to two.
The matching network was chosen so that a maximum
output power of 22 dBm was achieved with both blocks
on. When one stage is off,the matching network provides
a higher hPt
and thus a lower Pout,- In this way a relatively high average efficiency over the total PA output
power range can be achieved.
Figure 2. Simplified single-ended schematic of the PA
with two parallel output stages.
For the output stage no casccde transistors are used, since
this would increase the knee voltage and thus decrease
A switch in the signal path at the output would
also have a negative impact on the output power and thns
on the efficiency, and was therefore avoided as well.
The input capacitance of the output stage forms a large
part of the total capacitance at the drain of M2 which is
parallel to LD, see fig. 2. When switching offone stage (by
changing the gate bias to VDD and opening the VDD
switch), the input capacitance will change significantly. In
order to decrease the impact on input stage tuning, a rather
small AC coupling capacitance is used between the inputand output stage.
By connecting the two output nodes as shown in fig. 2,
the two parallel stages share I,,, C3 and Lbw Only C,,
and C2 are available to separately design kp,
for each
stage. Moreover, due to numzmus parasitic capacitances
and size restrictions of integrated passives, the impedance
transformation ratio cannot he varied ovix a wide range.
Generally when parallel output stages are used, power
combining is implemented either through a transformer
[3] or transmission lines [5].In this design, however, the
two stages are not isolated, meaning that the network of
one stage has an impact on the impedance transformation
of the other.
The matching network for one output stage may be
drawn as shown in fig. 3. The two output stages are connected at point P.
Figure 3. The matching network for one stage, with the
FET represented as an ideal current souce.
When for example the lower stage in fig. 2 is switched off,
FET Mb is brought into the linear region, thus providing a
low impedance. Assuming this to he a !short, one can see.
from fig. 2 that the equivalent capacitmce parallel to C3
will he larger. This decreases the transfixmation ratio for
which is desirable
the upper stage, thus increasing hpt,
when only one stage is on.
The two stages are unequal, having different FET
widths and different capacitance and inductance values,
and thus different transformation ratios and gains.
Comparing fig. 2 with fig. 3 one can see that the matching
network includes parasitic capacitance at the drain of the
FET (incorporated in C2), as well as the on-chip output
node (in C3).
The 5M1P 0.25um CMOS technology offers thickmetal inductors with quality factors ranging from approximately 5 to 15. For L2 and Ls inductors provided by the
manufacturer were used. L, and L, were designed using
Fast Henry [16] and ASITIC [17]. For the integrated
matching network, MOM (metal-oxidemetal) capacitors
with highest quality (Q) factor available in this technology
were used. The FETs M, and M, in fig. 2 do not have
minimum gate length, but 0.32pm, and have a higher
breakdown voltage.
The above described design was simulated using
SpectreRF, with BSIM3v3 models. Post-layout parasitics
were taken into account. The layout is shown in fig. 4.
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that an output power of 22.7 dBm may be achieved with a
maximum PAE of 22%. The average efficiency has been
improved by using two parallel output stages.
Table 1. Simulation results, summary
Pout (differential)
22.7 dBm
power gain
total die area
I P,,(stagel
including pads
1 17.2dBm I PAE=IS.S% I
Figure 4. Plot of the PA layout
A large area is occupied by the integrated passives, and
a substantial area saving may be achieved by using differential inductors [18].
In fig. 5 some simulation results are shown.
The authors are grateful to Niklas Troedsson, MSc (Dept.
of Electroscience, Lund University) for help with integrated inductor design and modeling.
Figure 5. Simulation results, a). Frequency response, b).
Poutas a function of Pin.
The maximum PAE (22 %) is achieved for Pout slightly
below Pout,, (which is about 23 dBm, see fig. 5.b). The
center frequency for both cases (stage 1+2 and stage 1
only) is approximately 2.45GHz. The simulation results
are summarized in table 1.
From table 2 a comparison can be made between this
PA and previously published work. It can be seen that the
PA presented in this work performs quite well, given the
limitations of an on-chip matching network and class-AB.
Moreover, the PA includes measures to improve the average efficiency.
A 2.45 GHz power amplifier has been designed in a
0.25urn CMOS technology. The PA is fully integrated,
including output matching network. Simulations show
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Pout (dBm)
efficiency (max)
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1s (@p.ldB)
<30% (rl)
lum CMOS
23.5 (max)
35% (PAE)
0.35 um (Bi)CMOS
33.4 (@max PAE)
31% (PAE)
0.35um (Bi)CMOS
30% (PAE)
49% (PAE)
0.25um CMOS
43% (PAE)
0.2um CMOS
45% (PAE)
0.35um CMOS
0.8um CMOS
44% 01)
0.25um CMOS
17.5 (max)
16.4% (PAE)
0.35um CMOS
partly on-chip
42% (PAE)
0.18um CMOS
62% (PAE max)
0.3Sum CMOS
9 (@P.5dB)
16% (P.5dB)
30% (PAE max)
0.6um CMOS
22% (PAE max)
0.25urn CMOS
18.6(@maxPAE) 0.9
Authorized licensed use limited to: Lunds Universitetsbibliotek. Downloaded on October 8, 2008 at 08:36 from IEEE Xplore. Restrictions apply.
steps, 5dB
1 I 1 ;I
1 i?I
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