Stratix V Device Datasheet

Stratix V Device Datasheet
Stratix V Device Datasheet
SV53001-3.6
This document covers the electrical and switching characteristics for Stratix® V
devices. Electrical characteristics include operating conditions and power
consumption. Switching characteristics include transceiver specifications, core, and
periphery performance. This document also describes I/O timing, including
programmable I/O element (IOE) delay and programmable output buffer delay.
f For information regarding the densities and packages of devices in the Stratix V
family, refer to the Stratix V Device Overview.
Electrical Characteristics
The following sections describe the electrical characteristics of Stratix V devices.
Operating Conditions
When you use Stratix V devices, they are rated according to a set of defined
parameters. To maintain the highest possible performance and reliability of Stratix V
devices, you must consider the operating requirements described in this chapter.
Stratix V devices are offered in commercial and industrial temperature grades.
Commercial devices are offered in –1 (fastest), –2, –3, and –4 core speed grades.
Industrial devices are offered in –2, –3, and –4 core speed grades. Stratix V E devices
are offered based on core speed grades while Stratix V GX, GS, and GT devices are
also offered in -1, -2, and -3 transceiver speed grades.
Table 1 lists the industrial and commercial speed grades for the Stratix V GX and
Stratix V GS devices.
Table 1. Stratix V GX and GS Commercial and Industrial Speed Grade Offering
1
GX channel—14.1 Gbps
2
GX channel—12.5 Gbps
December 2015
(Part 1 of 2)
Core Speed Grade
Transceiver Speed
Grade
101 Innovation Drive
San Jose, CA 95134
www.altera.com
(1), (2), (3)
C1
C2, C2L
C3
C4
I2, I2L
I3, I3L
I3YY
I4
Yes
Yes
—
—
Yes
—
—
—
Yes
Yes
Yes
—
Yes
Yes
—
—
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respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor
products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use
of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are
advised to obtain the latest version of device specifications before relying on any published information and before placing orders
for products or services.
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Page 2
Electrical Characteristics
Table 1. Stratix V GX and GS Commercial and Industrial Speed Grade Offering
(1), (2), (3)
(Part 2 of 2)
Core Speed Grade
Transceiver Speed
Grade
3
GX channel—8.5 Gbps
C1
C2, C2L
C3
C4
I2, I2L
I3, I3L
I3YY
I4
—
Yes
Yes
Yes
—
Yes
Yes (4)
Yes
Notes to Table 1:
(1) C = Commercial temperature grade; I = Industrial temperature grade.
(2) Lower number refers to faster speed grade.
(3) C2L, I2L, and I3L speed grades are for low-power devices.
(4) I3YY speed grades can achieve up to 10.3125 Gbps.
Table 2 lists the industrial and commercial speed grades for the Stratix V GT devices.
Table 2. Stratix V GT Commercial and Industrial Speed Grade Offering
(1), (2)
Core Speed Grade
Transceiver Speed Grade
C1
C2
I2
I3
Yes
Yes
—
—
Yes
Yes
Yes
Yes
2
GX channel—12.5 Gbps
GT channel—28.05 Gbps
3
GX channel—12.5 Gbps
GT channel—25.78 Gbps
Notes to Table 2:
(1) C = Commercial temperature grade; I = Industrial temperature grade.
(2) Lower number refers to faster speed grade.
Absolute Maximum Ratings
Absolute maximum ratings define the maximum operating conditions for Stratix V
devices. The values are based on experiments conducted with the devices and
theoretical modeling of breakdown and damage mechanisms. The functional
operation of the device is not implied for these conditions.
c Conditions other than those listed in Table 3 may cause permanent damage to the
device. Additionally, device operation at the absolute maximum ratings for extended
periods of time may have adverse effects on the device.
Table 3. Absolute Maximum Ratings for Stratix V Devices (Part 1 of 2)
Symbol
Description
Minimum
Maximum
Unit
VCC
Power supply for core voltage and periphery circuitry
–0.5
1.35
V
VCCPT
Power supply for programmable power technology
–0.5
1.8
V
VCCPGM
Power supply for configuration pins
–0.5
3.9
V
VCC_AUX
Auxiliary supply for the programmable power technology
–0.5
3.4
V
VCCBAT
Battery back-up power supply for design security volatile key register
–0.5
3.9
V
VCCPD
I/O pre-driver power supply
–0.5
3.9
V
VCCIO
I/O power supply
–0.5
3.9
V
Stratix V Device Datasheet
December 2015
Altera Corporation
Electrical Characteristics
Page 3
Table 3. Absolute Maximum Ratings for Stratix V Devices (Part 2 of 2)
Symbol
Description
Minimum
Maximum
Unit
VCCD_FPLL
PLL digital power supply
–0.5
1.8
V
VCCA_FPLL
PLL analog power supply
–0.5
3.4
V
VI
DC input voltage
–0.5
3.8
V
TJ
Operating junction temperature
–55
125
°C
TSTG
Storage temperature (No bias)
–65
150
°C
Table 4 lists the absolute conditions for the transceiver power supply for Stratix V GX,
GS, and GT devices.
Table 4. Transceiver Power Supply Absolute Conditions for Stratix V GX, GS, and GT Devices
Symbol
Description
Devices
Minimum
Maximum
Unit
GX, GS, GT
–0.5
3.75
V
VCCA_GXBL
Transceiver channel PLL power supply (left side)
VCCA_GXBR
Transceiver channel PLL power supply (right side)
GX, GS
–0.5
3.75
V
VCCA_GTBR
Transceiver channel PLL power supply (right side)
GT
–0.5
3.75
V
VCCHIP_L
Transceiver hard IP power supply (left side)
GX, GS, GT
–0.5
1.35
V
VCCHIP_R
Transceiver hard IP power supply (right side)
GX, GS, GT
–0.5
1.35
V
VCCHSSI_L
Transceiver PCS power supply (left side)
GX, GS, GT
–0.5
1.35
V
VCCHSSI_R
Transceiver PCS power supply (right side)
GX, GS, GT
–0.5
1.35
V
VCCR_GXBL
Receiver analog power supply (left side)
GX, GS, GT
–0.5
1.35
V
VCCR_GXBR
Receiver analog power supply (right side)
GX, GS, GT
–0.5
1.35
V
VCCR_GTBR
Receiver analog power supply for GT channels (right side)
GT
–0.5
1.35
V
VCCT_GXBL
Transmitter analog power supply (left side)
GX, GS, GT
–0.5
1.35
V
VCCT_GXBR
Transmitter analog power supply (right side)
GX, GS, GT
–0.5
1.35
V
VCCT_GTBR
Transmitter analog power supply for GT channels (right side)
GT
–0.5
1.35
V
VCCL_GTBR
Transmitter clock network power supply (right side)
GT
–0.5
1.35
V
VCCH_GXBL
Transmitter output buffer power supply (left side)
GX, GS, GT
–0.5
1.8
V
VCCH_GXBR
Transmitter output buffer power supply (right side)
GX, GS, GT
–0.5
1.8
V
Maximum Allowed Overshoot and Undershoot Voltage
During transitions, input signals may overshoot to the voltage shown in Table 5 and
undershoot to –2.0 V for input currents less than 100 mA and periods shorter than
20 ns.
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 4
Electrical Characteristics
Table 5 lists the maximum allowed input overshoot voltage and the duration of the
overshoot voltage as a percentage of device lifetime. The maximum allowed
overshoot duration is specified as a percentage of high time over the lifetime of the
device. A DC signal is equivalent to 100% of the duty cycle. For example, a signal that
overshoots to 3.95 V can be at 3.95 V for only ~21% over the lifetime of the device; for
a device lifetime of 10 years, the overshoot duration amounts to ~2 years.
Table 5. Maximum Allowed Overshoot During Transitions
Symbol
Vi (AC)
Stratix V Device Datasheet
Description
AC input voltage
Condition (V)
Overshoot Duration as %
@ TJ = 100°C
Unit
3.8
100
%
3.85
64
%
3.9
36
%
3.95
21
%
4
12
%
4.05
7
%
4.1
4
%
4.15
2
%
4.2
1
%
December 2015
Altera Corporation
Electrical Characteristics
Page 5
Recommended Operating Conditions
This section lists the functional operating limits for the AC and DC parameters for
Stratix V devices. Table 6 lists the steady-state voltage and current values expected
from Stratix V devices. Power supply ramps must all be strictly monotonic, without
plateaus.
Table 6. Recommended Operating Conditions for Stratix V Devices (Part 1 of 2)
Description
Condition
Min (4)
Typ
Max (4)
Unit
Core voltage and periphery circuitry power
supply (C1, C2, I2, and I3YY speed grades)
—
0.87
0.9
0.93
V
Core voltage and periphery circuitry power
supply (C2L, C3, C4, I2L, I3, I3L, and I4
speed grades) (3)
—
0.82
0.85
0.88
V
VCCPT
Power supply for programmable power
technology
—
1.45
1.50
1.55
V
VCC_AUX
Auxiliary supply for the programmable
power technology
—
2.375
2.5
2.625
V
I/O pre-driver (3.0 V) power supply
—
2.85
3.0
3.15
V
I/O pre-driver (2.5 V) power supply
—
2.375
2.5
2.625
V
I/O buffers (3.0 V) power supply
—
2.85
3.0
3.15
V
I/O buffers (2.5 V) power supply
—
2.375
2.5
2.625
V
I/O buffers (1.8 V) power supply
—
1.71
1.8
1.89
V
I/O buffers (1.5 V) power supply
—
1.425
1.5
1.575
V
I/O buffers (1.35 V) power supply
—
1.283
1.35
1.45
V
I/O buffers (1.25 V) power supply
—
1.19
1.25
1.31
V
I/O buffers (1.2 V) power supply
—
1.14
1.2
1.26
V
Symbol
VCC
VCCPD (1)
VCCIO
Configuration pins (3.0 V) power supply
—
2.85
3.0
3.15
V
Configuration pins (2.5 V) power supply
—
2.375
2.5
2.625
V
Configuration pins (1.8 V) power supply
—
1.71
1.8
1.89
V
VCCA_FPLL
PLL analog voltage regulator power supply
—
2.375
2.5
2.625
V
VCCD_FPLL
PLL digital voltage regulator power supply
—
1.45
1.5
1.55
V
(2)
Battery back-up power supply (For design
security volatile key register)
—
1.2
—
3.0
V
VI
DC input voltage
—
–0.5
—
3.6
V
VO
Output voltage
VCCPGM
VCCBAT
TJ
December 2015
Operating junction temperature
Altera Corporation
—
0
—
VCCIO
V
Commercial
0
—
85
°C
Industrial
–40
—
100
°C
Stratix V Device Datasheet
Page 6
Electrical Characteristics
Table 6. Recommended Operating Conditions for Stratix V Devices (Part 2 of 2)
Symbol
tRAMP
Description
Power supply ramp time
Condition
Min (4)
Typ
Max (4)
Unit
Standard POR
200 µs
—
100 ms
—
Fast POR
200 µs
—
4 ms
—
Notes to Table 6:
(1) VCCPD must be 2.5 V when VCCIO is 2.5, 1.8, 1.5, 1.35, 1.25 or 1.2 V. VCCPD must be 3.0 V when VCCIO is 3.0 V.
(2) If you do not use the design security feature in Stratix V devices, connect VCCBAT to a 1.2- to 3.0-V power supply. Stratix V power-on-reset (POR)
circuitry monitors VCCBAT. Stratix V devices will not exit POR if VCCBAT stays at logic low.
(3) C2L and I2L can also be run at 0.90 V for legacy boards that were designed for the C2 and I2 speed grades.
(4) The power supply value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance
requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
Table 7 lists the transceiver power supply recommended operating conditions for
Stratix V GX, GS, and GT devices.
Table 7. Recommended Transceiver Power Supply Operating Conditions for Stratix V GX, GS, and GT Devices
(Part 1 of 2)
Symbol
VCCA_GXBL
(1), (3)
VCCA_GXBR
(1), (3)
VCCA_GTBR
VCCHIP_L
VCCHIP_R
VCCHSSI_L
VCCHSSI_R
VCCR_GXBL
(2)
Description
Devices
Transceiver channel PLL power supply (left
side)
GX, GS, GT
Transceiver channel PLL power supply (right
side)
GX, GS
Transceiver channel PLL power supply (right
side)
Minimum (4)
Typical
Maximum (4)
2.85
3.0
3.15
2.375
2.5
2.625
Unit
V
2.85
3.0
3.15
2.375
2.5
2.625
GT
2.85
3.0
3.15
V
Transceiver hard IP power supply (left side;
C1, C2, I2, and I3YY speed grades)
GX, GS, GT
0.87
0.9
0.93
V
Transceiver hard IP power supply (left side;
C2L, C3, C4, I2L, I3, I3L, and I4 speed
grades)
GX, GS, GT
0.82
0.85
0.88
V
Transceiver hard IP power supply (right side;
C1, C2, I2, and I3YY speed grades)
GX, GS, GT
0.87
0.9
0.93
V
Transceiver hard IP power supply (right side;
C2L, C3, C4, I2L, I3, I3L, and I4 speed
grades)
GX, GS, GT
0.82
0.85
0.88
V
Transceiver PCS power supply (left side;
C1, C2, I2, and I3YY speed grades)
GX, GS, GT
0.87
0.9
0.93
V
Transceiver PCS power supply (left side;
C2L, C3, C4, I2L, I3, I3L, and I4 speed
grades)
GX, GS, GT
0.82
0.85
0.88
V
Transceiver PCS power supply (right side;
C1, C2, I2, and I3YY speed grades)
GX, GS, GT
0.87
0.9
0.93
V
Transceiver PCS power supply (right side;
C2L, C3, C4, I2L, I3, I3L, and I4 speed
grades)
GX, GS, GT
0.82
0.85
0.88
V
Receiver analog power supply (left side)
Stratix V Device Datasheet
GX, GS, GT
0.82
0.85
0.88
0.87
0.90
0.93
0.97
1.0
1.03
1.03
1.05
1.07
December 2015
V
V
Altera Corporation
Electrical Characteristics
Page 7
Table 7. Recommended Transceiver Power Supply Operating Conditions for Stratix V GX, GS, and GT Devices
(Part 2 of 2)
Symbol
VCCR_GXBR
(2)
VCCR_GTBR
VCCT_GXBL
(2)
VCCT_GXBR
(2)
Description
Receiver analog power supply (right side)
Devices
GX, GS, GT
Receiver analog power supply for GT
channels (right side)
Transmitter analog power supply (left side)
Transmitter analog power supply (right side)
GT
GX, GS, GT
GX, GS, GT
Minimum (4)
Typical
Maximum (4)
0.82
0.85
0.88
0.87
0.90
0.93
0.97
1.0
1.03
1.03
1.05
1.07
1.02
1.05
1.08
0.82
0.85
0.88
0.87
0.90
0.93
0.97
1.0
1.03
1.03
1.05
1.07
0.82
0.85
0.88
0.87
0.90
0.93
0.97
1.0
1.03
1.03
1.05
1.07
Unit
V
V
V
V
VCCT_GTBR
Transmitter analog power supply for GT
channels (right side)
GT
1.02
1.05
1.08
V
VCCL_GTBR
Transmitter clock network power supply
GT
1.02
1.05
1.08
V
VCCH_GXBL
Transmitter output buffer power supply (left
side)
GX, GS, GT
1.425
1.5
1.575
V
VCCH_GXBR
Transmitter output buffer power supply
(right side)
GX, GS, GT
1.425
1.5
1.575
V
Notes to Table 7:
(1) This supply must be connected to 3.0 V if the CMU PLL, receiver CDR, or both, are configured at a base data rate > 6.5 Gbps. Up to 6.5 Gbps,
you can connect this supply to either 3.0 V or 2.5 V.
(2) Refer to Table 8 to select the correct power supply level for your design.
(3) When using ATX PLLs, the supply must be 3.0 V.
(4) This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to
the PDN tool for the additional budget for the dynamic tolerance requirements.
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 8
Electrical Characteristics
Table 8 shows the transceiver power supply voltage requirements for various
conditions.
Table 8. Transceiver Power Supply Voltage Requirements
Conditions
Core Speed Grade
VCCR_GXB &
VCCT_GXB (2)
All
1.05
VCCA_GXB
VCCH_GXB
Unit
1.5
V
If BOTH of the following
conditions are true:
■
Data rate > 10.3 Gbps.
■
DFE is used.
If ANY of the following
conditions are true (1):
3.0
■
ATX PLL is used.
■
Data rate > 6.5Gbps.
■
1.0
DFE (data rate 
10.3 Gbps), AEQ, or
EyeQ feature is used.
If ALL of the following
conditions are true:
■
ATX PLL is not used.
■
Data rate  6.5Gbps.
■
All
C1, C2, I2, and I3YY
0.90
2.5
C2L, C3, C4, I2L, I3, I3L, and I4
0.85
2.5
DFE, AEQ, and EyeQ are
not used.
Notes to Table 8:
(1) Choose this power supply voltage requirement option if you plan to upgrade your design later with any of the listed conditions.
(2) If the VCCR_GXB and VCCT_GXB supplies are set to 1.0 V or 1.05 V, they cannot be shared with the VCC core supply. If the VCCR_GXB and
VCCT_GXB are set to either 0.90 V or 0.85 V, they can be shared with the VCC core supply.
DC Characteristics
This section lists the supply current, I/O pin leakage current, input pin capacitance,
on-chip termination tolerance, and hot socketing specifications.
Supply Current
Supply current is the current drawn from the respective power rails used for power
budgeting. Use the Excel-based Early Power Estimator (EPE) to get supply current
estimates for your design because these currents vary greatly with the resources you
use.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
Stratix V Device Datasheet
December 2015
Altera Corporation
Electrical Characteristics
Page 9
I/O Pin Leakage Current
Table 9 lists the Stratix V I/O pin leakage current specifications.
Table 9. I/O Pin Leakage Current for Stratix V Devices (1)
Symbol
Description
Conditions
Min
Typ
Max
Unit
II
Input pin
VI = 0 V to VCCIOMAX
–30
—
30
µA
IOZ
Tri-stated I/O pin
VO = 0 V to VCCIOMAX
–30
—
30
µA
Note to Table 9:
(1) If VO = VCCIO to VCCIOMax, 100 µA of leakage current per I/O is expected.
Bus Hold Specifications
Table 10 lists the Stratix V device family bus hold specifications.
Table 10. Bus Hold Parameters for Stratix V Devices
VCCIO
Parameter Symbol
1.2 V
Conditions
1.5 V
1.8 V
2.5 V
3.0 V
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
22.5
—
25.0
—
30.0
—
50.0
—
70.0
—
µA
–22.5
—
–25.0
—
–30.0
—
–50.0
—
–70.0
—
µA
Low
sustaining
current
ISUSL
High
sustaining
current
ISUSH
Low
overdrive
current
IODL
0V < VIN <
VCCIO
—
120
—
160
—
200
—
300
—
500
µA
High
overdrive
current
IODH
0V < VIN <
VCCIO
—
–120
—
–160
—
–200
—
–300
—
–500
µA
Bus-hold
trip point
VTRIP
—
0.45
0.95
0.50
1.00
0.68
1.07
0.70
1.70
0.80
2.00
V
VIN > VIL
(maximum)
VIN < VIH
(minimum)
On-Chip Termination (OCT) Specifications
If you enable OCT calibration, calibration is automatically performed at power-up for
I/Os connected to the calibration block. Table 11 lists the Stratix V OCT termination
calibration accuracy specifications.
Table 11. OCT Calibration Accuracy Specifications for Stratix V Devices (1) (Part 1 of 2)
Calibration Accuracy
Symbol
25- RS
December 2015
Description
Internal series termination
with calibration (25-
setting)
Altera Corporation
Conditions
VCCIO = 3.0, 2.5,
1.8, 1.5, 1.2 V
Unit
C1
C2,I2
C3,I3,
I3YY
C4,I4
±15
±15
±15
±15
%
Stratix V Device Datasheet
Page 10
Electrical Characteristics
Table 11. OCT Calibration Accuracy Specifications for Stratix V Devices (1) (Part 2 of 2)
Calibration Accuracy
Symbol
Description
Conditions
Unit
C1
C2,I2
C3,I3,
I3YY
C4,I4
50- RS
Internal series termination
with calibration (50-
setting)
VCCIO = 3.0, 2.5,
1.8, 1.5, 1.2 V
±15
±15
±15
±15
%
34- and
40- RS
Internal series termination
with calibration (34- and
40- setting)
VCCIO = 1.5, 1.35,
1.25, 1.2 V
±15
±15
±15
±15
%
VCCIO = 1.2 V
±15
±15
±15
±15
%
Internal series termination
48--
with calibration (48-
80-and
60-80-and -
240-RS
setting)
Internal parallel
termination with
calibration (50- setting)
VCCIO = 2.5, 1.8,
1.5, 1.2 V
–10 to +40 –10 to +40 –10 to +40 –10 to +40
%
Internal parallel
20-, 30-,
termination with
40-,60-
calibration (20-, 30-
and
40-60-and 120-
120- RT
setting)
VCCIO = 1.5, 1.35,
1.25 V
–10 to +40 –10 to +40 –10 to +40 –10 to +40
%
–10 to +40 –10 to +40 –10 to +40 –10 to +40
%
50- RT
60- and
120-RT
Internal parallel
termination with
calibration (60- and
120- setting)
VCCIO = 1.2
25-
RS_left_shift
Internal left shift series
termination with
calibration (25-
RS_left_shift setting)
VCCIO = 3.0, 2.5,
1.8, 1.5, 1.2 V
±15
±15
±15
±15
%
Note to Table 11:
(1) OCT calibration accuracy is valid at the time of calibration only.
Table 12 lists the Stratix V OCT without calibration resistance tolerance to PVT
changes.
Table 12. OCT Without Calibration Resistance Tolerance Specifications for Stratix V Devices (Part 1 of 2)
Resistance Tolerance
Symbol
Description
Conditions
Unit
C1
C2,I2
C3, I3,
I3YY
C4, I4
25- R, 50- RS
Internal series termination
without calibration (25-
setting)
VCCIO = 3.0 and 2.5 V
±30
±30
±40
±40
%
25- RS
Internal series termination
without calibration (25-
setting)
VCCIO = 1.8 and 1.5 V
±30
±30
±40
±40
%
25- RS
Internal series termination
without calibration (25-
setting)
VCCIO = 1.2 V
±35
±35
±50
±50
%
Stratix V Device Datasheet
December 2015
Altera Corporation
Electrical Characteristics
Page 11
Table 12. OCT Without Calibration Resistance Tolerance Specifications for Stratix V Devices (Part 2 of 2)
Resistance Tolerance
Symbol
Description
Conditions
Unit
C1
C2,I2
C3, I3,
I3YY
C4, I4
50- RS
Internal series termination
without calibration (50-
setting)
VCCIO = 1.8 and 1.5 V
±30
±30
±40
±40
%
50- RS
Internal series termination
without calibration (50-
setting)
VCCIO = 1.2 V
±35
±35
±50
±50
%
100- RD
Internal differential
termination (100- setting)
VCCIO = 2.5 V
±25
±25
±25
±25
%
Calibration accuracy for the calibrated series and parallel OCTs are applicable at the
moment of calibration. When voltage and temperature conditions change after
calibration, the tolerance may change.
OCT calibration is automatically performed at power-up for OCT-enabled I/Os.
Table 13 lists the OCT variation with temperature and voltage after power-up
calibration. Use Table 13 to determine the OCT variation after power-up calibration
and Equation 1 to determine the OCT variation without recalibration.
Equation 1. OCT Variation Without Recalibration for Stratix V Devices (1),
(2), (3), (4), (5), (6)
dR
dR
R OCT = R SCAL  1 +  -------  T   -------  V 


dT
dV
Notes to Equation 1:
(1) The ROCT value shows the range of OCT resistance with the variation of temperature and VCCIO.
(2) RSCAL is the OCT resistance value at power-up.
(3) T is the variation of temperature with respect to the temperature at power-up.
(4) V is the variation of voltage with respect to the VCCIO at power-up.
(5) dR/dT is the percentage change of RSCAL with temperature.
(6) dR/dV is the percentage change of RSCAL with voltage.
Table 13 lists the on-chip termination variation after power-up calibration.
Table 13. OCT Variation after Power-Up Calibration for Stratix V Devices (Part 1 of 2) (1)
Symbol
dR/dV
December 2015
Altera Corporation
Description
OCT variation with voltage without
recalibration
VCCIO (V)
Typical
3.0
0.0297
2.5
0.0344
1.8
0.0499
1.5
0.0744
1.2
0.1241
Unit
%/mV
Stratix V Device Datasheet
Page 12
Electrical Characteristics
Table 13. OCT Variation after Power-Up Calibration for Stratix V Devices (Part 2 of 2) (1)
Symbol
dR/dT
Description
VCCIO (V)
Typical
3.0
0.189
2.5
0.208
1.8
0.266
1.5
0.273
1.2
0.317
OCT variation with temperature
without recalibration
Unit
%/°C
Note to Table 13:
(1) Valid for a VCCIO range of ±5% and a temperature range of 0° to 85°C.
Pin Capacitance
Table 14 lists the Stratix V device family pin capacitance.
Table 14. Pin Capacitance for Stratix V Devices
Symbol
Description
Value
Unit
CIOTB
Input capacitance on the top and bottom I/O pins
6
pF
CIOLR
Input capacitance on the left and right I/O pins
6
pF
COUTFB
Input capacitance on dual-purpose clock output and feedback pins
6
pF
Hot Socketing
Table 15 lists the hot socketing specifications for Stratix V devices.
Table 15. Hot Socketing Specifications for Stratix V Devices
Symbol
Description
Maximum
IIOPIN (DC)
DC current per I/O pin
300 A
IIOPIN (AC)
AC current per I/O pin
8 mA (1)
IXCVR-TX (DC)
DC current per transceiver transmitter pin
100 mA
IXCVR-RX (DC)
DC current per transceiver receiver pin
50 mA
Note to Table 15:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is the I/O pin
capacitance and dv/dt is the slew rate.
Stratix V Device Datasheet
December 2015
Altera Corporation
Electrical Characteristics
Page 13
Internal Weak Pull-Up Resistor
Table 16 lists the weak pull-up resistor values for Stratix V devices.
Table 16. Internal Weak Pull-Up Resistor for Stratix V Devices (1),
Symbol
RPU
Description
(2)
VCCIO Conditions
(V) (3)
Value (4)
Unit
3.0 ±5%
25
k
2.5 ±5%
25
k
1.8 ±5%
25
k
1.5 ±5%
25
k
1.35 ±5%
25
k
1.25 ±5%
25
k
1.2 ±5%
25
k
Value of the I/O pin pull-up resistor before
and during configuration, as well as user
mode if you enable the programmable
pull-up resistor option.
Notes to Table 16:
(1) All I/O pins have an option to enable the weak pull-up resistor except the configuration, test, and JTAG pins.
(2) The internal weak pull-down feature is only available for the JTAG TCK pin. The typical value for this internal weak
pull-down resistor is approximately 25 k
(3) The pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
(4) These specifications are valid with a ±10% tolerance to cover changes over PVT.
I/O Standard Specifications
Table 17 through Table 22 list the input voltage (VIH and VIL), output voltage (VOH and
VOL), and current drive characteristics (IOH and IOL) for various I/O standards
supported by Stratix V devices. These tables also show the Stratix V device family I/O
standard specifications. The VOL and VOH values are valid at the corresponding IOH
and IOL, respectively.
For an explanation of the terms used in Table 17 through Table 22, refer to “Glossary”
on page 65. For tolerance calculations across all SSTL and HSTL I/O standards, refer
to Altera knowledge base solution rd07262012_486.
Table 17. Single-Ended I/O Standards for Stratix V Devices
I/O
Standard
LVTTL
VCCIO (V)
VIL (V)
VIH (V)
VOL (V)
VOH (V)
IOH
(mA)
Min
Typ
Max
Min
Max
Min
Max
Max
Min
IOL
(mA)
2.85
3
3.15
–0.3
0.8
1.7
3.6
0.4
2.4
2
–2
LVCMOS
2.85
3
3.15
–0.3
0.8
1.7
3.6
0.2
VCCIO – 0.2
0.1
–0.1
2.5 V
2.375
2.5
2.625
–0.3
0.7
1.7
3.6
0.4
2
1
–1
1.8 V
1.71
1.8
1.89
–0.3
0.35 *
VCCIO
0.65 *
VCCIO
VCCIO +
0.3
0.45
VCCIO –
0.45
2
–2
1.5 V
1.425
1.5
1.575
–0.3
0.35 *
VCCIO
0.65 *
VCCIO
VCCIO +
0.3
0.25 *
VCCIO
0.75 *
VCCIO
2
–2
1.2 V
1.14
1.2
1.26
–0.3
0.35 *
VCCIO
0.65 *
VCCIO
VCCIO +
0.3
0.25 *
VCCIO
0.75 *
VCCIO
2
–2
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 14
Electrical Characteristics
Table 18. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications for Stratix V Devices
VCCIO (V)
I/O Standard
VREF (V)
VTT (V)
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
SSTL-2
Class I, II
2.375
2.5
2.625
0.49 *
VCCIO
0.5 * VCCIO
0.51 *
VCCIO
VREF –
0.04
VREF
VREF +
0.04
SSTL-18
Class I, II
1.71
1.8
1.89
0.833
0.9
0.969
VREF –
0.04
VREF
VREF +
0.04
SSTL-15
Class I, II
1.425
1.5
1.575
0.49 *
VCCIO
0.5 * VCCIO
0.51 *
VCCIO
0.49 *
VCCIO
0.5 *
VCCIO
0.51 *
VCCIO
SSTL-135
Class I, II
1.283
1.35
1.418
0.49 *
VCCIO
0.5 * VCCIO
0.51 *
VCCIO
0.49 *
VCCIO
0.5 *
VCCIO
0.51 *
VCCIO
SSTL-125
Class I, II
1.19
1.25
1.26
0.49 *
VCCIO
0.5 * VCCIO
0.51 *
VCCIO
0.49 *
VCCIO
0.5 *
VCCIO
0.51 *
VCCIO
SSTL-12
Class I, II
1.14
1.20
1.26
0.49 *
VCCIO
0.5 * VCCIO
0.51 *
VCCIO
0.49 *
VCCIO
0.5 *
VCCIO
0.51 *
VCCIO
HSTL-18
Class I, II
1.71
1.8
1.89
0.85
0.9
0.95
—
VCCIO/2
—
HSTL-15
Class I, II
1.425
1.5
1.575
0.68
0.75
0.9
—
VCCIO/2
—
HSTL-12
Class I, II
1.14
1.2
1.26
0.47 *
VCCIO
0.5 * VCCIO
0.53 *
VCCIO
—
VCCIO/2
—
HSUL-12
1.14
1.2
1.3
0.49 *
VCCIO
0.5 * VCCIO
0.51 *
VCCIO
—
—
—
Table 19. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Stratix V Devices (Part 1 of 2)
I/O Standard
VIL(DC) (V)
VIH(DC) (V)
VIL(AC) (V)
VIH(AC) (V)
VOL (V)
VOH (V)
Iol (mA)
Ioh
(mA)
Min
Max
Min
Max
Max
Min
Max
Min
SSTL-2
Class I
–0.3
VREF –
0.15
VREF +
0.15
VCCIO +
0.3
VREF –
0.31
VREF + 0.31
VTT –
0.608
VTT +
0.608
8.1
–8.1
SSTL-2
Class II
–0.3
VREF –
0.15
VREF +
0.15
VCCIO +
0.3
VREF –
0.31
VREF + 0.31
VTT –
0.81
VTT +
0.81
16.2
–16.2
SSTL-18
Class I
–0.3
VREF –
0.125
VREF +
0.125
VCCIO +
0.3
VREF –
0.25
VREF + 0.25
VTT –
0.603
VTT +
0.603
6.7
–6.7
SSTL-18
Class II
–0.3
VREF –
0.125
VREF +
0.125
VCCIO +
0.3
VREF –
0.25
VREF + 0.25
0.28
VCCIO –
0.28
13.4
–13.4
SSTL-15
Class I
—
VREF –
0.1
VREF +
0.1
—
VREF –
0.175
VREF +
0.175
0.2 *
VCCIO
0.8 *
VCCIO
8
–8
SSTL-15
Class II
—
VREF –
0.1
VREF +
0.1
—
VREF –
0.175
VREF +
0.175
0.2 *
VCCIO
0.8 *
VCCIO
16
–16
SSTL-135
Class I, II
—
VREF –
0.09
VREF +
0.09
—
VREF –
0.16
VREF + 0.16
0.2 *
VCCIO
0.8 *
VCCIO
—
—
SSTL-125
Class I, II
—
VREF –
0.85
VREF +
0.85
—
VREF –
0.15
VREF + 0.15
0.2 *
VCCIO
0.8 *
VCCIO
—
—
SSTL-12
Class I, II
—
VREF –
0.1
VREF +
0.1
—
VREF –
0.15
VREF + 0.15
0.2 *
VCCIO
0.8 *
VCCIO
—
—
Stratix V Device Datasheet
December 2015
Altera Corporation
Electrical Characteristics
Page 15
Table 19. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications for Stratix V Devices (Part 2 of 2)
VIL(DC) (V)
I/O Standard
VIH(DC) (V)
VIL(AC) (V)
VIH(AC) (V)
VOL (V)
VOH (V)
Iol (mA)
Ioh
(mA)
Min
Max
Min
Max
Max
Min
Max
Min
HSTL-18
Class I
—
VREF –
0.1
VREF +
0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO –
0.4
8
–8
HSTL-18
Class II
—
VREF –
0.1
VREF +
0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO –
0.4
16
–16
HSTL-15
Class I
—
VREF –
0.1
VREF +
0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO –
0.4
8
–8
HSTL-15
Class II
—
VREF –
0.1
VREF +
0.1
—
VREF – 0.2
VREF + 0.2
0.4
VCCIO –
0.4
16
–16
HSTL-12
Class I
–0.15
VREF –
0.08
VREF +
0.08
VCCIO +
0.15
VREF –
0.15
VREF + 0.15
0.25*
VCCIO
0.75*
VCCIO
8
–8
HSTL-12
Class II
–0.15
VREF –
0.08
VREF +
0.08
VCCIO +
0.15
VREF –
0.15
VREF + 0.15
0.25*
VCCIO
0.75*
VCCIO
16
–16
HSUL-12
—
VREF –
0.13
VREF +
0.13
—
VREF –
0.22
VREF + 0.22
0.1*
VCCIO
0.9*
VCCIO
—
—
Table 20. Differential SSTL I/O Standards for Stratix V Devices
VCCIO (V)
I/O Standard
VSWING(DC) (V)
VX(AC) (V)
VSWING(AC) (V)
Min
Typ
Max
Min
Max
Min
Typ
Max
Min
Max
SSTL-2 Class
I, II
2.375
2.5
2.625
0.3
VCCIO +
0.6
VCCIO/2 –
0.2
—
VCCIO/2 +
0.2
0.62
VCCIO +
0.6
SSTL-18 Class
I, II
1.71
1.8
1.89
0.25
VCCIO +
0.6
VCCIO/2 –
0.175
—
VCCIO/2 +
0.175
0.5
VCCIO +
0.6
SSTL-15 Class
I, II
1.425
1.5
1.575
0.2
(1)
VCCIO/2 –
0.15
—
VCCIO/2 +
0.15
0.35
—
SSTL-135
Class I, II
1.283
1.35
1.45
0.2
(1)
VCCIO/2 –
0.15
VCCIO/2
VCCIO/2 +
0.15
2(VIH(AC) VREF)
2(VIL(AC)
- VREF)
SSTL-125
Class I, II
1.19
1.25
1.31
0.18
(1)
VCCIO/2 –
0.15
VCCIO/2
VCCIO/2 +
0.15
2(VIH(AC) VREF)
—
SSTL-12
Class I, II
1.14
1.2
1.26
0.18
—
VREF
–0.15
VCCIO/2
VREF +
0.15
–0.30
0.30
Note to Table 20:
(1) The maximum value for VSWING(DC) is not defined. However, each single-ended signal needs to be within the respective single-ended limits
(VIH(DC) and VIL(DC)).
Table 21. Differential HSTL and HSUL I/O Standards for Stratix V Devices (Part 1 of 2)
I/O
Standard
VCCIO (V)
VDIF(DC) (V)
VX(AC) (V)
VCM(DC) (V)
VDIF(AC) (V)
Min
Typ
Max
Min
Max
Min
Typ
Max
Min
Typ
Max
Min
Max
HSTL-18
Class I, II
1.71
1.8
1.89
0.2
—
0.78
—
1.12
0.78
—
1.12
0.4
—
HSTL-15
Class I, II
1.425
1.5
1.575
0.2
—
0.68
—
0.9
0.68
—
0.9
0.4
—
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 16
Electrical Characteristics
Table 21. Differential HSTL and HSUL I/O Standards for Stratix V Devices (Part 2 of 2)
I/O
Standard
VCCIO (V)
VDIF(DC) (V)
VX(AC) (V)
VCM(DC) (V)
VDIF(AC) (V)
Min
Typ
Max
Min
Max
Min
Typ
Max
Min
Typ
Max
Min
Max
HSTL-12
Class I, II
1.14
1.2
1.26
0.16
VCCIO
+ 0.3
—
0.5*
VCCIO
—
0.4*
VCCIO
0.5*
VCCIO
0.6*
VCCIO
0.3
VCCIO
+ 0.48
HSUL-12
1.14
1.2
1.3
0.26
0.26
0.5*VCCIO
– 0.12
0.5*
VCCIO
0.5*VCCIO
+ 0.12
0.4*
VCCIO
0.5*
VCCIO
0.6*
VCCIO
0.44
0.44
VOCM (V)
(6)
Table 22. Differential I/O Standard Specifications for Stratix V Devices (7)
I/O
Standard
Min
Typ
(10)
Max
VID (mV) (8)
Min
Condition
VICM(DC) (V)
Max
Min
Condition
VOD (V)
Max
Min
(6)
Typ Max
Min
Typ
Max
Transmitter, receiver, and input reference clock pins of the high-speed transceivers use the PCML I/O standard. For
transmitter, receiver, and reference clock I/O pin specifications, refer to Table 23 on page 18.
PCML
2.5 V
LVDS
VCCIO (V)
2.375
(1)
BLVDS (5)
2.5
2.375 2.5
2.625
—
0.05
DMAX 
700 Mbps
1.8
0.247
—
0.6
1.125
1.25
1.375
—
1.05
DMAX >
700 Mbps
1.55
0.247
—
0.6
1.125
1.25
1.375
100
—
—
—
—
—
—
—
—
—
—
—
2.625
100
VCM =
1.25 V
—
0.3
—
1.4
0.1
0.2
0.6
0.5
1.2
1.4
2.5
2.625
200
—
600
0.4
—
1.325
0.25
—
0.6
1
1.2
1.4
—
—
—
—
—
—
0.6
DMAX 
700 Mbps
1.8
—
—
—
—
—
—
—
—
—
—
—
—
1
DMAX >
700 Mbps
1.6
—
—
—
—
—
—
RSDS
(HIO) (2)
2.375
2.5
MiniLVDS
(HIO)
2.375
2.625
100
VCM =
1.25 V
(3)
LVPECL (4
), (9)
Notes to Table 22:
(1) For optimized LVDS receiver performance, the receiver voltage input range must be between 1.0 V to 1.6 V for data rates above 700 Mbps, and 0 V to 1.85
V for data rates below 700 Mbps.
(2) For optimized RSDS receiver performance, the receiver voltage input range must be between 0.25 V to 1.45 V.
(3) For optimized Mini-LVDS receiver performance, the receiver voltage input range must be between 0.3 V to 1.425 V.
(4) For optimized LVPECL receiver performance, the receiver voltage input range must be between 0.85 V to 1.75 V for data rate above 700 Mbps and 0.45 V
to 1.95 V for data rate below 700 Mbps.
(5) There are no fixed VICM, VOD, and VOCM specifications for BLVDS. They depend on the system topology.
(6) RL range: 90  RL  110  .
(7) The 1.4-V and 1.5-V PCML transceiver I/O standard specifications are described in “Transceiver Performance Specifications” on page 18.
(8) The minimum VID value is applicable over the entire common mode range, VCM.
(9) LVPECL is only supported on dedicated clock input pins.
(10) Differential inputs are powered by VCCPD which requires 2.5 V.
Power Consumption
Altera offers two ways to estimate power consumption for a design—the Excel-based
Early Power Estimator and the Quartus® II PowerPlay Power Analyzer feature.
Stratix V Device Datasheet
December 2015
Altera Corporation
Electrical Characteristics
1
Page 17
You typically use the interactive Excel-based Early Power Estimator before designing
the FPGA to get a magnitude estimate of the device power. The Quartus II PowerPlay
Power Analyzer provides better quality estimates based on the specifics of the design
after you complete place-and-route. The PowerPlay Power Analyzer can apply a
combination of user-entered, simulation-derived, and estimated signal activities that,
when combined with detailed circuit models, yields very accurate power estimates.
f For more information about power estimation tools, refer to the PowerPlay Early Power
Estimator User Guide and the PowerPlay Power Analysis chapter in the Quartus II
Handbook.
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 18
Switching Characteristics
Switching Characteristics
This section provides performance characteristics of the Stratix V core and periphery
blocks.
These characteristics can be designated as Preliminary or Final.
■
Preliminary characteristics are created using simulation results, process data, and
other known parameters. The title of these tables show the designation as
“Preliminary.”
■
Final numbers are based on actual silicon characterization and testing. The
numbers reflect the actual performance of the device under worst-case silicon
process, voltage, and junction temperature conditions. There are no designations
on finalized tables.
Transceiver Performance Specifications
This section describes transceiver performance specifications.
Table 23 lists the Stratix V GX and GS transceiver specifications.
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
Symbol/
Description
Conditions
Transceiver Speed
Grade 1
Min
Typ
Max
(1)
(Part 1 of 7)
Transceiver Speed
Grade 2
Min
Typ
Max
Transceiver Speed
Grade 3
Min
Typ
Unit
Max
Reference Clock
Supported I/O
Standards
Dedicated
reference
clock pin
1.2-V PCML, 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, Differential LVPECL, LVDS, and
HCSL
RX reference
clock pin
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
Input Reference
Clock Frequency
(CMU PLL) (8)
—
40
—
710
40
—
710
40
—
710
MHz
Input Reference
Clock Frequency
(ATX PLL) (8)
—
100
—
710
100
—
710
100
—
710
MHz
Rise time
Measure at
±60 mV of
differential
signal (26)
—
—
400
—
—
400
—
—
400
Fall time
Measure at
±60 mV of
differential
signal (26)
—
—
400
—
—
400
—
—
400
—
45
—
55
45
—
55
45
—
55
%
PCI Express®
(PCIe®)
30
—
33
30
—
33
30
—
33
kHz
Duty cycle
Spread-spectrum
modulating clock
frequency
Stratix V Device Datasheet
ps
December 2015
Altera Corporation
Switching Characteristics
Page 19
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
Symbol/
Description
Conditions
Transceiver Speed
Grade 1
Min
Spread-spectrum
downspread
Typ
0 to
(1)
(Part 2 of 7)
Transceiver Speed
Grade 2
Max
Min
—
—
Typ
0 to
Transceiver Speed
Grade 3
Max
Min
—
—
Typ
0 to
Unit
Max
—
%
100
—

—
1.6
PCIe
—
—
—
100
—
—
100
—
—
Dedicated
reference
clock pin
—
—
1.6
—
—
1.6
—
RX reference
clock pin
—
—
1.2
—
—
1.2
—
—
1.2
Absolute VMIN
—
–0.4
—
—
–0.4
—
—
–0.4
—
—
V
Peak-to-peak
differential input
voltage
—
200
—
1600
200
—
1600
200
—
1600
mV
On-chip
termination
resistors (21)
Absolute VMAX (5)
Dedicated
reference
clock pin
VICM (AC
coupled) (3)
Transmitter
REFCLK Phase
Noise
(622 MHz) (20)
Transmitter
REFCLK Phase
Jitter
(100 MHz) (17)
RREF
(19)
–0.5
–0.5
V
1050/1000/900/850
RX reference
clock pin
VICM (DC coupled)
–0.5
(2)
1050/1000/900/850
1.0/0.9/0.85 (4)
(2)
1050/1000/900/850
1.0/0.9/0.85 (4)
(2)
1.0/0.9/0.85 (4)
mV
V
HCSL I/O
standard for
PCIe
reference
clock
250
—
550
250
—
550
250
—
550
mV
100 Hz
—
—
-70
—
—
-70
—
—
-70
dBc/Hz
1 kHz
—
—
-90
—
—
-90
—
—
-90
dBc/Hz
10 kHz
—
—
-100
—
—
-100
—
—
-100
dBc/Hz
100 kHz
—
—
-110
—
—
-110
—
—
-110
dBc/Hz
≥1 MHz
—
—
-120
—
—
-120
—
—
-120
dBc/Hz
10 kHz to
1.5 MHz
(PCIe)
—
—
3
—
—
3
—
—
3
ps
(rms)
—
—
1800
±1%
—
—
1800
±1%
—
—
180
0
±1%
—

PCIe
Receiver
Detect
—
100
or
125
—
—
100
or
125
—
—
100
or
125
—
MHz
Transceiver Clocks
fixedclk clock
frequency
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 20
Switching Characteristics
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
Symbol/
Description
Conditions
Reconfiguration
clock
(mgmt_clk_clk)
frequency
—
Transceiver Speed
Grade 1
(1)
(Part 3 of 7)
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
100
—
125
100
—
125
100
—
125
Unit
MHz
Receiver
Supported I/O
Standards
—
Data rate
(Standard PCS)
—
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
600
—
12200
600
—
12200
600
—
8500/
10312.5
(9), (23)
Data rate
(10G PCS) (9),
Mbps
(24)
—
(23)
600
—
14100
600
—
12500
600
—
8500/
10312.5
Mbps
(24)
Absolute VMAX for
a receiver pin (5)
—
—
—
1.2
—
—
1.2
—
—
1.2
V
Absolute VMIN for
a receiver pin
—
–0.4
—
—
–0.4
—
—
–0.4
—
—
V
Maximum peakto-peak
differential input
voltage VID (diff pp) before device
configuration (22)
—
—
—
1.6
—
—
1.6
—
—
1.6
V
VCCR_GXB =
1.0 V/1.05 V
(VICM =
0.70 V)
—
—
2.0
—
—
2.0
—
—
2.0
V
—
—
2.4
—
—
2.4
—
—
2.4
V
—
—
2.4
—
—
2.4
—
—
2.4
V
85
—
—
85
—
—
85
—
—
mV
Maximum peakto-peak
differential input
VCCR_GXB =
voltage VID (diff p0.90 V
p) after device
(VICM = 0.6 V)
(18)
configuration ,
(22)
VCCR_GXB =
0.85 V
(VICM = 0.6 V)
Minimum
differential eye
opening at
receiver serial
input pins (6), (22),
—
(27)
Stratix V Device Datasheet
December 2015
Altera Corporation
Switching Characteristics
Page 21
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
Symbol/
Description
Differential onchip termination
resistors (21)
VICM
(AC and DC
coupled)
tLTR
(11)
tLTD
(12)
tLTD_manual
(13)
tLTR_LTD_manual
(14)
Run Length
Programmable
equalization
(AC Gain) (10)
December 2015
Conditions
Transceiver Speed
Grade 1
(1)
(Part 4 of 7)
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
85 setting
—
85 ±
30%
—
—
85 ±
30%
—
—
85 ±
30%
—

100
setting
—
100
±
30%
—
—
100
±
30%
—
—
100
±
30%
—

120
setting
—
120
±
30%
—
—
120
±
30%
—
—
120
±
30%
—

150-
setting
—
150
±
30%
—
—
150
±
30%
—
—
150
±
30%
—

VCCR_GXB =
0.85 V or 0.9
V
full
bandwidth
—
600
—
—
600
—
—
600
—
mV
VCCR_GXB =
0.85 V or 0.9
V
half
bandwidth
—
600
—
—
600
—
—
600
—
mV
VCCR_GXB =
1.0 V/1.05 V
full
bandwidth
—
700
—
—
700
—
—
700
—
mV
VCCR_GXB =
1.0 V
half
bandwidth
—
750
—
—
750
—
—
750
—
mV
—
—
—
10
—
—
10
—
—
10
µs
—
4
—
—
4
—
—
4
—
—
µs
—
4
—
—
4
—
—
4
—
—
µs
—
15
—
—
15
—
—
15
—
—
µs
—
—
—
200
—
—
200
—
—
200
UI
—
—
16
—
—
16
—
—
16
dB
Full
bandwidth
(6.25 GHz)
Half
bandwidth
(3.125 GHz)
Altera Corporation
Stratix V Device Datasheet
Page 22
Switching Characteristics
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
Symbol/
Description
Conditions
Programmable
DC gain
Transceiver Speed
Grade 1
(1)
(Part 5 of 7)
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
DC Gain
Setting = 0
—
0
—
—
0
—
—
0
—
dB
DC Gain
Setting = 1
—
2
—
—
2
—
—
2
—
dB
DC Gain
Setting = 2
—
4
—
—
4
—
—
4
—
dB
DC Gain
Setting = 3
—
6
—
—
6
—
—
6
—
dB
DC Gain
Setting = 4
—
8
—
—
8
—
—
8
—
dB
—
8500/
10312.5
Mbps
Transmitter
Supported I/O
Standards
—
Data rate
(Standard PCS)
—
Data rate
(10G PCS)
—
1.4-V and 1.5-V PCML
600
—
12200
600
—
12200
600
(24)
600
—
14100
600
—
12500
600
—
8500/
10312.5
Mbps
(24)
85-
setting
—
85 ±
20%
—
—
85 ±
20%
—
—
85 ±
20%
—

100-
setting
—
100
±
20%
—
—
100
±
20%
—
—
100
±
20%
—

120-
setting
—
120
±
20%
—
—
120
±
20%
—
—
120
±
20%
—

150-
setting
—
150
±
20%
—
—
150
±
20%
—
—
150
±
20%
—

VOCM (AC
coupled)
0.65-V
setting
—
650
—
—
650
—
—
650
—
mV
VOCM (DC
coupled)
—
—
650
—
—
650
—
—
650
—
mV
20% to 80%
30
—
160
30
—
160
30
—
160
ps
80% to 20%
30
—
160
30
—
160
30
—
160
ps
Intra-differential
pair skew
Tx VCM =
0.5 V and
slew rate of
15 ps
—
—
15
—
—
15
—
—
15
ps
Intra-transceiver
block transmitter
channel-tochannel skew
x6 PMA
bonded mode
—
—
120
—
—
120
—
—
120
ps
Differential onchip termination
resistors
Rise time
Fall time
(7)
(7)
Stratix V Device Datasheet
December 2015
Altera Corporation
Switching Characteristics
Page 23
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
Symbol/
Description
Conditions
Transceiver Speed
Grade 1
(1)
(Part 6 of 7)
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
xN PMA
bonded mode
—
—
500
—
—
500
—
—
500
ps
Supported Data
Range
—
600
—
12500
600
—
12500
600
—
8500/
10312.5
Mbps
tpll_powerdown (15)
—
1
—
—
1
—
—
1
—
—
µs
—
—
—
10
—
—
10
—
—
10
µs
VCO
post-divider
L=2
8000
—
14100
8000
—
12500
8000
—
8500/
10312.5
Mbps
L=4
4000
—
7050
4000
—
6600
4000
—
6600
Mbps
L=8
2000
—
3525
2000
—
3300
2000
—
3300
Mbps
L=8,
Local/Central
Clock Divider
=2
1000
—
1762.5
1000
—
1762.5
1000
—
1762.5
Mbps
—
1
—
—
1
—
—
1
—
—
µs
—
—
—
10
—
—
10
—
—
10
µs
Supported Data
Range
—
600
—
3250/
3125 (25)
600
—
3250/
3125 (25)
600
—
3250/
3125 (25)
Mbps
tpll_powerdown (15)
—
1
—
—
1
—
—
1
—
—
µs
Inter-transceiver
block transmitter
channel-tochannel skew
CMU PLL
tpll_lock
(16)
(24)
ATX PLL
Supported Data
Rate Range
tpll_powerdown
tpll_lock
(15)
(16)
(24)
fPLL
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 24
Switching Characteristics
Table 23. Transceiver Specifications for Stratix V GX and GS Devices
Symbol/
Description
tpll_lock (16)
Conditions
—
Transceiver Speed
Grade 1
(1)
(Part 7 of 7)
Transceiver Speed
Grade 2
Transceiver Speed
Grade 3
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
—
—
10
—
—
10
—
—
10
Unit
µs
Notes to Table 23:
(1) Speed grades shown in Table 23 refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the
Core/PCS speed grade. Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination
offered. For more information about device ordering codes, refer to the Stratix V Device Overview.
(2) The reference clock common mode voltage is equal to the VCCR_GXB power supply level.
(3) This supply must be connected to 1.0 V if the transceiver is configured at a data rate > 6.5 Gbps, and to 1.05 V if configured at a data rate >
10.3 Gbps when DFE is used. For data rates up to 6.5 Gbps, you can connect this supply to 0.85 V.
(4) This supply follows VCCR_GXB.
(5) The device cannot tolerate prolonged operation at this absolute maximum.
(6) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver
Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(7) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.
(8) The input reference clock frequency options depend on the data rate and the device speed grade.
(9) The line data rate may be limited by PCS-FPGA interface speed grade.
(10) Refer to Figure 1 for the GX channel AC gain curves. The total effective AC gain is the AC gain minus the DC gain.
(11) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
(12) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
(13) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is
functioning in the manual mode.
(14) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when the
CDR is functioning in the manual mode.
(15) tpll_powerdown is the PLL powerdown minimum pulse width.
(16) tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset.
(17) To calculate the REFCLK rms phase jitter requirement for PCIe at reference clock frequencies other than 100 MHz, use the following formula:
REFCLK rms phase jitter at f(MHz) = REFCLK rms phase jitter at 100 MHz × 100/f.
(18) The maximum peak to peak differential input voltage VID after device configuration is equal to 4 × (absolute VMAX for receiver pin - VICM).
(19) For ES devices, RREF is 2000 ±1%.
(20) To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f(MHz)
= REFCLK phase noise at 622 MHz + 20*log(f/622).
(21) SFP/+ optical modules require the host interface to have RD+/- differentially terminated with 100 . The internal OCT feature is available after
the Stratix V FPGA configuration is completed. Altera recommends that FPGA configuration is completed before inserting the optical module.
Otherwise, minimize unnecessary removal and insertion with unconfigured devices.
(22) Refer to Figure 1.
(23) For oversampling designs to support data rates less than the minimum specification, the CDR needs to be in LTR mode only.
(24) I3YY devices can achieve data rates up to 10.3125 Gbps.
(25) When you use fPLL as a TXPLL of the transceiver.
(26) REFCLK performance requires to meet transmitter REFCLK phase noise specification.
(27) Minimum eye opening of 85 mV is only for the unstressed input eye condition.
Stratix V Device Datasheet
December 2015
Altera Corporation
Switching Characteristics
Page 25
Table 24 shows the maximum transmitter data rate for the clock network.
Table 24. Clock Network Maximum Data Rate Transmitter Specifications
(1)
CMU PLL (2)
ATX PLL
fPLL
Nonbonded
Mode
(Gbps)
Bonded
Mode
(Gbps)
Channel
Span
Nonbonded
Mode
(Gbps)
Bonded
Mode
(Gbps)
Channel
Span
Nonbonded
Mode
(Gbps)
Bonded
Mode
(Gbps)
Channel
Span
x1 (3)
14.1
—
6
12.5
—
6
3.125
—
3
x6 (3)
—
14.1
6
—
12.5
6
—
3.125
6
—
12.5
Sidewide
—
—
—
—
5.0
8
—
—
—
7.99
Up to 13
channels
above
and
below
PLL
3.125
Up to 13
channels
above
and
below
PLL
Clock Network
x6 PLL
Feedback (4)
—
14.1
Sidewide
xN (PCIe)
—
8.0
8
8.0
Up to 13
channels
above
and
below
PLL
8.01 to
9.8304
Up to 7
channels
above
and
below
PLL
8.0
xN (Native PHY IP)
—
7.99
3.125
Notes to Table 24:
(1) Valid data rates below the maximum specified in this table depend on the reference clock frequency and the PLL counter settings. Check the
MegaWizard message during the PHY IP instantiation.
(2) ATX PLL is recommended at 8 Gbps and above data rates for improved jitter performance.
(3) Channel span is within a transceiver bank.
(4) Side-wide channel bonding is allowed up to the maximum supported by the PHY IP.
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 26
Switching Characteristics
Table 25 shows the approximate maximum data rate using the standard PCS.
Table 25. Stratix V Standard PCS Approximate Maximum Date Rate
Mode
(2)
Transceiver
Speed Grade
1
2
FIFO
3
1
2
Register
3
(1), (3)
PMA Width
20
20
16
16
10
10
8
8
PCS/Core Width
40
20
32
16
20
10
16
8
C1, C2, C2L, I2, I2L
core speed grade
12.2
11.4
9.76
9.12
6.5
5.8
5.2
4.72
C1, C2, C2L, I2, I2L
core speed grade
12.2
11.4
9.76
9.12
6.5
5.8
5.2
4.72
C3, I3, I3L
core speed grade
9.8
9.0
7.84
7.2
5.3
4.7
4.24
3.76
C1, C2, C2L, I2, I2L
core speed grade
8.5
8.5
8.5
8.5
6.5
5.8
5.2
4.72
I3YY
core speed grade
10.3125
10.3125
7.84
7.2
5.3
4.7
4.24
3.76
C3, I3, I3L
core speed grade
8.5
8.5
7.84
7.2
5.3
4.7
4.24
3.76
C4, I4
core speed grade
8.5
8.2
7.04
6.56
4.8
4.2
3.84
3.44
C1, C2, C2L, I2, I2L
core speed grade
12.2
11.4
9.76
9.12
6.1
5.7
4.88
4.56
C1, C2, C2L, I2, I2L
core speed grade
12.2
11.4
9.76
9.12
6.1
5.7
4.88
4.56
C3, I3, I3L
core speed grade
9.8
9.0
7.92
7.2
4.9
4.5
3.96
3.6
C1, C2, C2L, I2, I2L
core speed grade
10.3125
10.3125
10.3125
10.3125
6.1
5.7
4.88
4.56
I3YY
core speed grade
10.3125
10.3125
7.92
7.2
4.9
4.5
3.96
3.6
C3, I3, I3L
core speed grade
8.5
8.5
7.92
7.2
4.9
4.5
3.96
3.6
C4, I4
core speed grade
8.5
8.2
7.04
6.56
4.4
4.1
3.52
3.28
Notes to Table 25:
(1) The maximum data rate is in Gbps.
(2) The Phase Compensation FIFO can be configured in FIFO mode or register mode. In the FIFO mode, the pointers are not fixed, and the latency
can vary. In the register mode the pointers are fixed for low latency.
(3) The maximum data rate is also constrained by the transceiver speed grade. Refer to Table 1 for the transceiver speed grade.
Stratix V Device Datasheet
December 2015
Altera Corporation
Switching Characteristics
Page 27
Table 26 shows the approximate maximum data rate using the 10G PCS.
Table 26. Stratix V 10G PCS Approximate Maximum Data Rate
Mode
(2)
PMA Width
64
40
40
40
32
32
PCS Width
64
66/67
50
40
64/66/67
32
C1, C2, C2L, I2, I2L
core speed grade
14.1
14.1
10.69
14.1
13.6
13.6
C1, C2, C2L, I2, I2L
core speed grade
12.5
12.5
10.69
12.5
12.5
12.5
C3, I3, I3L
core speed grade
12.5
12.5
10.69
12.5
10.88
10.88
Transceiver
Speed Grade
1
2
FIFO or
Register
(1)
C1, C2, C2L, I2, I2L
core speed grade
3
C3, I3, I3L
core speed grade
8.5 Gbps
C4, I4
core speed grade
I3YY
core speed grade
10.3125 Gbps
Notes to Table 26:
(1) The maximum data rate is in Gbps.
(2) The Phase Compensation FIFO can be configured in FIFO mode or register mode. In the FIFO mode, the pointers are not fixed, and the latency
can vary. In the register mode the pointers are fixed for low latency.
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 28
Switching Characteristics
Table 27
shows the VOD settings for the GX channel.
Table 27. Typical VOD Setting for GX Channel, TX Termination = 100  (2)
Symbol
VOD differential peak to peak
typical (3)
VOD Value
(mV)
VOD Setting
VOD Setting
VOD Value
(mV)
0 (1)
0
32
640
1 (1)
20
33
660
2 (1)
40
34
680
3 (1)
60
35
700
4 (1)
80
36
720
5 (1)
100
37
740
6
120
38
760
7
140
39
780
8
160
40
800
9
180
41
820
10
200
42
840
11
220
43
860
12
240
44
880
13
260
45
900
14
280
46
920
15
300
47
940
16
320
48
960
17
340
49
980
18
360
50
1000
19
380
51
1020
20
400
52
1040
21
420
53
1060
22
440
54
1080
23
460
55
1100
24
480
56
1120
25
500
57
1140
26
520
58
1160
27
540
59
1180
28
560
60
1200
29
580
61
1220
30
600
62
1240
31
620
63
1260
Note to Table 27:
(1) If TX termination resistance = 100this VOD setting is illegal.
(2) The tolerance is +/-20% for all VOD settings except for settings 2 and below.
(3) Refer to Figure 1.
Stratix V Device Datasheet
December 2015
Altera Corporation
Switching Characteristics
Page 29
Figure 1 shows the differential transmitter output waveform.
Figure 1. Differential Transmitter Output Waveform
Single-Ended Waveform
Positive Channel (p)
VOD /VID (single-ended)
Negative Channel (n)
VCM
Ground
Differential Waveform
VOD/VID (differential peak to peak typical) = 2 x VOD/VID (single-ended)
VOD /VID (single-ended)
VOD /VID (single-ended)
Figure 2 shows the Stratix V AC gain curves for GX channels.
Figure 2. AC Gain Curves for GX Channels (full bandwidth)
1
Stratix V GT devices contain both GX and GT channels. All transceiver specifications
for the GX channels not listed in Table 28 are the same as those listed in Table 23.
Table 28 lists the Stratix V GT transceiver specifications.
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 30
Switching Characteristics
Table 28. Transceiver Specifications for Stratix V GT Devices (Part 1 of 5) (1)
Symbol/
Description
Transceiver
Speed Grade 2
Conditions
Min
Typ
Transceiver
Speed Grade 3
Max
Min
Typ
Unit
Max
Reference Clock
Supported I/O
Standards
Dedicated
reference
clock pin
1.2-V PCML, 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, Differential LVPECL, LVDS,
and HCSL
RX reference
clock pin
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
Input Reference Clock
Frequency (CMU
PLL) (6)
—
40
—
710
40
—
710
MHz
Input Reference Clock
Frequency (ATX PLL) (6)
—
100
—
710
100
—
710
MHz
Rise time
20% to 80%
—
—
400
—
—
400
Fall time
80% to 20%
—
—
400
—
—
400
—
45
—
55
45
—
55
%
Spread-spectrum
modulating clock
frequency
PCI Express
(PCIe)
30
—
33
30
—
33
kHz
Spread-spectrum
downspread
PCIe
—
0 to –0.5
—
—
0 to –0.5
—
%
—
—
100
—
—
100
—

Dedicated
reference
clock pin
—
—
1.6
—
—
1.6
RX reference
clock pin
—
—
1.2
—
—
1.2
Absolute VMIN
—
-0.4
—
—
-0.4
—
—
V
Peak-to-peak
differential input
voltage
—
200
—
1600
200
—
1600
mV
Duty cycle
On-chip termination
resistors (19)
Absolute VMAX
(3)
VICM (AC coupled)
VICM (DC coupled)
Stratix V Device Datasheet
ps
V
Dedicated
reference
clock pin
1050/1000 (2)
1050/1000 (2)
mV
RX reference
clock pin
1.0/0.9/0.85 (22)
1.0/0.9/0.85 (22)
V
HCSL I/O
standard for
PCIe
reference
clock
250
—
550
250
—
550
December 2015
mV
Altera Corporation
Switching Characteristics
Page 31
Table 28. Transceiver Specifications for Stratix V GT Devices (Part 2 of 5) (1)
Symbol/
Description
Transmitter REFCLK
Phase Noise (622
MHz) (18)
Transmitter REFCLK
Phase Jitter (100
MHz) (15)
Transceiver
Speed Grade 2
Conditions
Min
Typ
100 Hz
—
—
1 kHz
—
10 kHz
Transceiver
Speed Grade 3
Min
Typ
-70
—
—
-70
—
-90
—
—
-90
—
—
-100
—
—
-100
100 kHz
—
—
-110
—
—
-110
≥ 1 MHz
—
—
-120
—
—
-120
10 kHz to
1.5 MHz
(PCIe)
—
—
3
—
—
3
ps (rms)
—
—
—
—
—

PCIe
Receiver
Detect
—
100 or
125
—
—
100 or
125
—
MHz
—
100
—
125
100
—
125
MHz
RREF (17)
1800
± 1%
Max
Unit
1800
± 1%
Max
dBc/Hz
Transceiver Clocks
fixedclk clock
frequency
Reconfiguration clock
(mgmt_clk_clk)
frequency
Receiver
Supported I/O
Standards
—
1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS
Data rate
(Standard PCS) (21)
GX channels
600
—
8500
600
—
8500
Mbps
Data rate
(10G PCS) (21)
GX channels
600
—
12,500
600
—
12,500
Mbps
Data rate
GT channels
19,600
—
28,050
19,600
—
25,780
Mbps
Absolute VMAX for a
receiver pin (3)
GT channels
—
—
1.2
—
—
1.2
V
Absolute VMIN for a
receiver pin
GT channels
–0.4
—
—
–0.4
—
—
V
GT channels
—
—
1.6
—
—
1.6
V
—
2.2
V
—
—
mV
Maximum peak-to-peak
differential input
voltage VID (diff p-p)
before device
configuration (20)
(8)
GX channels
GT channels
Maximum peak-to-peak
differential input
voltage VID (diff p-p)
after device
configuration (16), (20)
VCCR_GTB =
1.05 V
(VICM =
0.65 V)
—
—
2.2
(8)
GX channels
Minimum differential
eye opening at receiver
serial input pins (4), (20)
December 2015
GT channels
GX channels
Altera Corporation
—
200
—
—
200
(8)
Stratix V Device Datasheet
Page 32
Switching Characteristics
Table 28. Transceiver Specifications for Stratix V GT Devices (Part 3 of 5) (1)
Symbol/
Description
Differential on-chip
termination resistors (7)
Differential on-chip
termination resistors
for GX channels (19)
VICM (AC coupled)
VICM (AC and DC
coupled) for GX
Channels
tLTR (9)
tLTD
(10)
tLTD_manual
(11)
tLTR_LTD_manual (12)
Run Length
CDR PPM
Programmable
equalization
(AC Gain) (5)
Programmable
DC gain (6)
Differential on-chip
termination resistors (7)
Transceiver
Speed Grade 2
Conditions
Transceiver
Speed Grade 3
Unit
Min
Typ
Max
Min
Typ
Max
GT channels
—
100
—
—
100
—

85-setting
—
85 ± 30%
—
—
—

100-
setting
—
—
—
—

120-
setting
—
—
—
—

150-
setting
—
—
—
—

GT channels
—
650
—
—
650
—
mV
VCCR_GXB =
0.85 V or
0.9 V
—
600
—
—
600
—
mV
VCCR_GXB =
1.0 V full
bandwidth
—
700
—
—
700
—
mV
VCCR_GXB =
1.0 V half
bandwidth
—
750
—
—
750
—
mV
—
—
—
10
—
—
10
µs
—
4
—
—
4
—
—
µs
100
± 30%
120
± 30%
150
± 30%
85
± 30%
100
± 30%
120
± 30%
150
± 30%
—
4
—
—
4
—
—
µs
—
15
—
—
15
—
—
µs
GT channels
—
—
72
—
—
72
CID
—
1000
± PPM
—
14
dB
—
7.5
dB
100
—

(8)
GX channels
GT channels
—
—
1000
GX channels
GT channels
—
—
14
—
—
7.5
—
(8)
GX channels
GT channels
—
(8)
GX channels
GT channels
—
(8)
—
100
—
—
Transmitter
Supported I/O
Standards
—
1.4-V and 1.5-V PCML
Data rate
(Standard PCS)
GX channels
600
—
8500
600
—
8500
Mbps
Data rate
(10G PCS)
GX channels
600
—
12,500
600
—
12,500
Mbps
Stratix V Device Datasheet
December 2015
Altera Corporation
Switching Characteristics
Page 33
Table 28. Transceiver Specifications for Stratix V GT Devices (Part 4 of 5) (1)
Symbol/
Description
Transceiver
Speed Grade 2
Conditions
Transceiver
Speed Grade 3
Min
Typ
Max
Min
Typ
Max
19,600
—
25,780
Mbps
—
100
—

500
—
mV
15
—
ps
Data rate
GT channels
19,600
—
28,050
Differential on-chip
termination resistors
GT channels
—
100
—
VOCM (AC coupled)
—
500
—
—
(8)
GX channels
GT channels
Rise/Fall time
(8)
GX channels
GT channels
Unit
—
15
—
—
GX channels
(8)
Intra-differential pair
skew
GX channels
(8)
Intra-transceiver block
transmitter channelto-channel skew
GX channels
(8)
Inter-transceiver block
transmitter channelto-channel skew
GX channels
(8)
CMU PLL
Supported Data Range
tpll_powerdown
tpll_lock
—
600
—
12500
600
—
8500
Mbps
—
1
—
—
1
—
—
µs
—
—
—
10
—
—
10
µs
VCO postdivider L=2
8000
—
12500
8000
—
8500
Mbps
L=4
4000
—
6600
4000
—
6600
Mbps
L=8
2000
—
3300
2000
—
3300
Mbps
L=8,
Local/Central
Clock Divider
=2
1000
—
1762.5
1000
—
1762.5
Mbps
VCO postdivider L=2
9800
—
14025
9800
—
12890
Mbps
(13)
(14)
ATX PLL
Supported Data Rate
Range for GX Channels
Supported Data Rate
Range for GT Channels
tpll_powerdown (13)
—
1
—
—
1
—
—
µs
tpll_lock (14)
—
—
—
10
—
—
10
µs
Supported Data Range
—
600
—
3250/
3.125 (23)
600
—
3250/
3.125 (23)
Mbps
tpll_powerdown (13)
—
1
—
—
1
—
—
µs
fPLL
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 34
Switching Characteristics
Table 28. Transceiver Specifications for Stratix V GT Devices (Part 5 of 5) (1)
Symbol/
Description
tpll_lock (14)
Transceiver
Speed Grade 2
Conditions
—
Transceiver
Speed Grade 3
Unit
Min
Typ
Max
Min
Typ
Max
—
—
10
—
—
10
µs
Notes to Table 28:
(1) Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS
speed grade. Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For
more information about device ordering codes, refer to the Stratix V Device Overview.
(2) The reference clock common mode voltage is equal to the VCCR_GXB power supply level.
(3) The device cannot tolerate prolonged operation at this absolute maximum.
(4) The differential eye opening specification at the receiver input pins assumes that receiver equalization is disabled. If you enable receiver
equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
(5) Refer to Figure 4 for the GT channel AC gain curves. The total effective AC gain is the AC gain minus the DC gain.
(6) Refer to Figure 5 for the GT channel DC gain curves.
(7) CFP2 optical modules require the host interface to have the receiver data pins differentially terminated with 100 . The internal OCT feature is
available after the Stratix V FPGA configuration is completed. Altera recommends that FPGA configuration is completed before inserting the
optical module. Otherwise, minimize unnecessary removal and insertion with unconfigured devices.
(8) Specifications for this parameter are the same as for Stratix V GX and GS devices. See Table 23 for specifications.
(9) tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.
(10) tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
(11) tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the
CDR is functioning in the manual mode.
(12) tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtoref signal goes high when
the CDR is functioning in the manual mode.
(13) tpll_powerdown is the PLL powerdown minimum pulse width.
(14) tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset.
(15) To calculate the REFCLK rms phase jitter requirement for PCIe at reference clock frequencies other than 100 MHz, use the following formula:
REFCLK rms phase jitter at f(MHz) = REFCLK rms phase jitter at 100 MHz × 100/f.
(16) The maximum peak to peak differential input voltage VID after device configuration is equal to 4 × (absolute VMAX for receiver pin - VICM).
(17) For ES devices, RREF is 2000 ±1%.
(18) To calculate the REFCLK phase noise requirement at frequencies other than 622 MHz, use the following formula: REFCLK phase noise at f(MHz)
= REFCLK phase noise at 622 MHz + 20*log(f/622).
(19) SFP/+ optical modules require the host interface to have RD+/- differentially terminated with 100 . The internal OCT feature is available after
the Stratix V FPGA configuration is completed. Altera recommends that FPGA configuration is completed before inserting the optical module.
Otherwise, minimize unnecessary removal and insertion with unconfigured devices.
(20) Refer to Figure 3.
(21) For oversampling design to support data rates less than the minimum specification, the CDR needs to be in LTR mode only.
(22) This supply follows VCCR_GXB for both GX and GT channels.
(23) When you use fPLL as a TXPLL of the transceiver.
Stratix V Device Datasheet
December 2015
Altera Corporation
Switching Characteristics
Page 35
Table 29 shows the VOD settings for the GT channel.
Table 29. Typical VOD Setting for GT Channel, TX Termination = 100 
VOD Setting
Symbol
VOD differential peak to peak typical (1)
VOD Value (mV)
0
0
1
200
2
400
3
600
4
800
5
1000
Note:
(1) Refer to Figure 3.
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 36
Switching Characteristics
Figure 3 shows the differential transmitter output waveform.
Figure 3. Differential Transmitter/Receiver Output/Input Waveform
Single-Ended Waveform
Positive Channel (p)
VOD /VID (single-ended)
Negative Channel (n)
VCM
Ground
Differential Waveform
VOD/VID (differential peak to peak typical) = 2 x VOD/VID (single-ended)
VOD /VID (single-ended)
VOD /VID (single-ended)
Figure 4 shows the Stratix V AC gain curves for GT channels.
Figure 4. AC Gain Curves for GT Channels
Stratix V Device Datasheet
December 2015
Altera Corporation
Switching Characteristics
Page 37
Figure 5 shows the Stratix V DC gain curves for GT channels.
Figure 5. DC Gain Curves for GT Channels
Transceiver Characterization
This section summarizes the Stratix V transceiver characterization results for
compliance with the following protocols:
December 2015
■
Interlaken
■
40G (XLAUI)/100G (CAUI)
■
10GBase-KR
■
QSGMII
■
XAUI
■
SFI
■
Gigabit Ethernet (Gbe / GIGE)
■
SPAUI
■
Serial Rapid IO (SRIO)
■
CPRI
■
OBSAI
■
Hyper Transport (HT)
■
SATA
■
SAS
■
CEI
Altera Corporation
Stratix V Device Datasheet
Page 38
Switching Characteristics
■
XFI
■
ASI
■
HiGig/HiGig+
■
HiGig2/HiGig2+
■
Serial Data Converter (SDC)
■
GPON
■
SDI
■
SONET
■
Fibre Channel (FC)
■
PCIe
■
QPI
■
SFF-8431
Download the Stratix V Characterization Report Tool to view the characterization
report summary for these protocols.
Core Performance Specifications
This section describes the clock tree, phase-locked loop (PLL), digital signal
processing (DSP), memory blocks, configuration, and JTAG specifications.
Clock Tree Specifications
Table 30 lists the clock tree specifications for Stratix V devices.
Table 30. Clock Tree Performance for Stratix V Devices
(1)
Performance
Symbol
Unit
C1, C2, C2L, I2, and
I2L
C3, I3, I3L, and
I3YY
C4, I4
Global and
Regional Clock
717
650
580
MHz
Periphery Clock
550
500
500
MHz
Note to Table 30:
(1) The Stratix V ES devices are limited to 600 MHz core clock tree performance.
Stratix V Device Datasheet
December 2015
Altera Corporation
Switching Characteristics
Page 39
PLL Specifications
Table 31 lists the Stratix V PLL specifications when operating in both the commercial
junction temperature range (0° to 85°C) and the industrial junction temperature range
(–40° to 100°C).
Table 31. PLL Specifications for Stratix V Devices (Part 1 of 3)
Symbol
Parameter
Min
Typ
Max
Unit
Input clock frequency (C1, C2, C2L, I2, and I2L speed
grades)
5
—
800 (1)
MHz
Input clock frequency (C3, I3, I3L, and I3YY speed
grades)
5
—
800 (1)
MHz
Input clock frequency (C4, I4 speed grades)
5
—
650 (1)
MHz
fINPFD
Input frequency to the PFD
5
—
325
MHz
fFINPFD
Fractional Input clock frequency to the PFD
50
—
160
MHz
PLL VCO operating range (C1, C2, C2L, I2, I2L speed
grades)
600
—
1600
MHz
PLL VCO operating range (C3, I3, I3L, I3YY speed
grades)
600
—
1600
MHz
PLL VCO operating range (C4, I4 speed grades)
600
—
1300
MHz
Input clock or external feedback clock input duty cycle
40
—
60
%
Output frequency for an internal global or regional
clock (C1, C2, C2L, I2, I2L speed grades)
—
—
717 (2)
MHz
Output frequency for an internal global or regional
clock (C3, I3, I3L speed grades)
—
—
650
(2)
MHz
Output frequency for an internal global or regional
clock (C4, I4 speed grades)
—
—
580 (2)
MHz
Output frequency for an external clock output (C1, C2,
C2L, I2, I2L speed grades)
—
—
800 (2)
MHz
Output frequency for an external clock output (C3, I3,
I3L speed grades)
—
—
667
(2)
MHz
Output frequency for an external clock output (C4, I4
speed grades)
—
—
553
(2)
MHz
tOUTDUTY
Duty cycle for a dedicated external clock output (when
set to 50%)
45
50
55
%
tFCOMP
External feedback clock compensation time
—
—
10
ns
fDYCONFIGCLK
Dynamic Configuration Clock used for mgmt_clk and
scanclk
—
—
100
MHz
tLOCK
Time required to lock from the end-of-device
configuration or deassertion of areset
—
—
1
ms
tDLOCK
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
—
—
1
ms
PLL closed-loop low bandwidth
—
0.3
—
MHz
—
1.5
—
MHz
—
4
—
MHz
fIN
fVCO (9)
tEINDUTY
fOUT
fOUT_EXT
fCLBW
PLL closed-loop medium bandwidth
PLL closed-loop high bandwidth
(7)
tPLL_PSERR
Accuracy of PLL phase shift
—
—
±50
ps
tARESET
Minimum pulse width on the areset signal
10
—
—
ns
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 40
Switching Characteristics
Table 31. PLL Specifications for Stratix V Devices (Part 2 of 3)
Symbol
Min
Typ
Max
Unit
Input clock cycle-to-cycle jitter (fREF ≥ 100 MHz)
—
—
0.15
UI (p-p)
Input clock cycle-to-cycle jitter (fREF < 100 MHz)
–750
—
+750
ps (p-p)
Period Jitter for dedicated clock output (fOUT ≥
100 MHz)
—
—
175
(1)
ps (p-p)
Period Jitter for dedicated clock output (fOUT <
100 MHz)
—
—
17.5
(1)
mUI (p-p)
Period Jitter for dedicated clock output in fractional
PLL (fOUT  100 MHz)
—
—
250 (11),
175 (12)
ps (p-p)
Period Jitter for dedicated clock output in fractional
PLL (fOUT < 100 MHz)
—
—
25 (11),
17.5 (12)
mUI (p-p)
Cycle-to-Cycle Jitter for a dedicated clock output
(fOUT ≥ 100 MHz)
—
—
175
ps (p-p)
Cycle-to-Cycle Jitter for a dedicated clock output
(fOUT < 100 MHz)
—
—
17.5
mUI (p-p)
Cycle-to-cycle Jitter for a dedicated clock output in
fractional PLL (fOUT  100 MHz)
—
—
250 (11),
175 (12)
ps (p-p)
Cycle-to-cycle Jitter for a dedicated clock output in
fractional PLL (fOUT < 100 MHz)+
—
—
25 (11),
17.5 (12)
mUI (p-p)
Period Jitter for a clock output on a regular I/O in
integer PLL (fOUT ≥ 100 MHz)
—
—
600
ps (p-p)
Period Jitter for a clock output on a regular I/O
(fOUT < 100 MHz)
—
—
60
mUI (p-p)
Period Jitter for a clock output on a regular I/O in
fractional PLL (fOUT  100 MHz)
—
—
600 (10)
ps (p-p)
Period Jitter for a clock output on a regular I/O in
fractional PLL (fOUT < 100 MHz)
—
—
60 (10)
mUI (p-p)
Cycle-to-cycle Jitter for a clock output on a regular I/O
in integer PLL (fOUT  100 MHz)
—
—
600
ps (p-p)
Cycle-to-cycle Jitter for a clock output on a regular I/O
in integer PLL (fOUT < 100 MHz)
—
—
60 (10)
mUI (p-p)
Cycle-to-cycle Jitter for a clock output on a regular I/O
in fractional PLL (fOUT  100 MHz)
—
—
600 (10)
ps (p-p)
Cycle-to-cycle Jitter for a clock output on a regular I/O
in fractional PLL (fOUT < 100 MHz)
—
—
60
mUI (p-p)
Period Jitter for a dedicated clock output in cascaded
PLLs (fOUT ≥ 100 MHz)
—
—
175
ps (p-p)
Period Jitter for a dedicated clock output in cascaded
PLLs (fOUT < 100 MHz)
—
—
17.5
mUI (p-p)
fDRIFT
Frequency drift after PFDENA is disabled for a duration
of 100 µs
—
—
±10
%
dKBIT
Bit number of Delta Sigma Modulator (DSM)
8
24
32
Bits
kVALUE
Numerator of Fraction
128
8388608
2147483648
—
tINCCJ
(3), (4)
(5)
tOUTPJ_DC
tFOUTPJ_DC
tOUTCCJ_DC
(5)
(5)
tFOUTCCJ_DC (5)
tOUTPJ_IO
(5),
(8)
tFOUTPJ_IO (5),
(8), (11)
tOUTCCJ_IO
(5),
(8)
tFOUTCCJ_IO (5),
(8), (11)
tCASC_OUTPJ_DC
(5), (6)
Parameter
Stratix V Device Datasheet
December 2015
Altera Corporation
Switching Characteristics
Page 41
Table 31. PLL Specifications for Stratix V Devices (Part 3 of 3)
Symbol
fRES
Parameter
Resolution of VCO frequency (fINPFD = 100 MHz)
Min
Typ
Max
Unit
390625
5.96
0.023
Hz
Notes to Table 31:
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(2) This specification is limited by the lower of the two: I/O fMAX or fOUT of the PLL.
(3) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source < 120 ps.
(4) fREF is fIN/N when N = 1.
(5) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a
different measurement method and are available in Table 44 on page 52.
(6) The cascaded PLL specification is only applicable with the following condition:
a. Upstream PLL: 0.59Mhz  Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
(7) High bandwidth PLL settings are not supported in external feedback mode.
(8) The external memory interface clock output jitter specifications use a different measurement method, which is available in Table 42 on page 50.
(9) The VCO frequency reported by the Quartus II software in the PLL Usage Summary section of the compilation report takes into consideration
the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(10) This specification only covers fractional PLL for low bandwidth. The fVCO for fractional value range 0.05 - 0.95 must be 1000 MHz, while fVCO
for fractional value range 0.20 - 0.80 must be  1200 MHz.
(11) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.05-0.95 must be  1000 MHz.
(12) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.20-0.80 must be  1200 MHz.
DSP Block Specifications
Table 32 lists the Stratix V DSP block performance specifications.
Table 32. Block Performance Specifications for Stratix V DSP Devices (Part 1 of 2)
Peformance
Mode
C1
C2, C2L
I2, I2L
C3
I3, I3L,
I3YY
Unit
C4
I4
Modes using one DSP
Three 9 x 9
600
600
600
480
480
420
420
MHz
One 18 x 18
600
600
600
480
480
420
400
MHz
Two partial 18 x 18 (or 16 x 16)
600
600
600
480
480
420
400
MHz
One 27 x 27
500
500
500
400
400
350
350
MHz
One 36 x 18
500
500
500
400
400
350
350
MHz
One sum of two 18 x 18(One sum of
2 16 x 16)
500
500
500
400
400
350
350
MHz
One sum of square
500
500
500
400
400
350
350
MHz
One 18 x 18 plus 36 (a x b) + c
500
500
500
400
400
350
350
MHz
Modes using two DSPs
Three 18 x 18
500
500
500
400
400
350
350
MHz
One sum of four 18 x 18
475
475
475
380
380
300
300
MHz
One sum of two 27 x 27
465
465
450
380
380
300
290
MHz
One sum of two 36 x 18
475
475
475
380
380
300
300
MHz
One complex 18 x 18
500
500
500
400
400
350
350
MHz
One 36 x 36
475
475
475
380
380
300
300
MHz
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 42
Switching Characteristics
Table 32. Block Performance Specifications for Stratix V DSP Devices (Part 2 of 2)
Peformance
Mode
C1
C2, C2L
I2, I2L
Unit
I3, I3L,
I3YY
C3
C4
I4
Modes using Three DSPs
One complex 18 x 25
425
425
415
340
340
275
265
MHz
380
300
290
MHz
Modes using Four DSPs
One complex 27 x 27
465
465
465
380
Memory Block Specifications
Table 33 lists the Stratix V memory block specifications.
Table 33. Memory Block Performance Specifications for Stratix V Devices (1),
Resources Used
Memory
MLAB
(2)
(Part 1 of 2)
Performance
ALUTs
Memory
C1
C2,
C2L
C3
C4
I2, I2L
I3,
I3L,
I3YY
I4
Single port, all
supported widths
0
1
450
450
400
315
450
400
315
MHz
Simple dual-port,
x32/x64 depth
0
1
450
450
400
315
450
400
315
MHz
Simple dual-port, x16
depth (3)
0
1
675
675
533
400
675
533
400
MHz
ROM, all supported
widths
0
1
600
600
500
450
600
500
450
MHz
Mode
Stratix V Device Datasheet
December 2015
Unit
Altera Corporation
Switching Characteristics
Page 43
Table 33. Memory Block Performance Specifications for Stratix V Devices (1),
Resources Used
(Part 2 of 2)
Performance
ALUTs
Memory
C1
C2,
C2L
C3
C4
I2, I2L
I3,
I3L,
I3YY
I4
Single-port, all
supported widths
0
1
700
700
650
550
700
500
450
MHz
Simple dual-port, all
supported widths
0
1
700
700
650
550
700
500
450
MHz
Simple dual-port with
the read-during-write
option set to Old Data,
all supported widths
0
1
525
525
455
400
525
455
400
MHz
Simple dual-port with
ECC enabled, 512 × 32
0
1
450
450
400
350
450
400
350
MHz
Simple dual-port with
ECC and optional
pipeline registers
enabled, 512 × 32
0
1
600
600
500
450
600
500
450
MHz
True dual port, all
supported widths
0
1
700
700
650
550
700
500
450
MHz
ROM, all supported
widths
0
1
700
700
650
550
700
500
450
MHz
Memory
M20K
Block
(2)
Mode
Unit
Notes to Table 33:
(1) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL
set to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes.
(2) When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in FMAX.
(3) The FMAX specification is only achievable with Fitter options, MLAB Implementation In 16-Bit Deep Mode enabled.
Temperature Sensing Diode Specifications
Table 34 lists the internal TSD specification.
Table 34. Internal Temperature Sensing Diode Specification
Temperature
Range
–40°C to 100°C
Accuracy
Offset
Calibrated
Option
±8°C
No
Sampling Rate
Conversion
Time
Resolution
Minimum
Resolution
with no
Missing Codes
1 MHz, 500 KHz
< 100 ms
8 bits
8 bits
Table 35 lists the specifications for the Stratix V external temperature sensing diode.
Table 35. External Temperature Sensing Diode Specifications for Stratix V Devices
Description
Min
Typ
Max
Unit
Ibias, diode source current
8
—
200
A
Vbias, voltage across diode
0.3
—
0.9
V
Series resistance
—
—
<1

1.006
1.008
1.010
—
Diode ideality factor
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 44
Switching Characteristics
Periphery Performance
This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfaces, such as the LVDS high-speed
I/O interface, external memory interface, and the PCI/PCI-X bus interface.
General-purpose I/O standards such as 3.3-, 2.5-, 1.8-, and 1.5-LVTTL/LVCMOS are
capable of a typical 167 MHz and 1.2-LVCMOS at 100 MHz interfacing frequency
with a 10 pF load.
1
The actual achievable frequency depends on design- and system-specific factors.
Ensure proper timing closure in your design and perform HSPICE/IBIS simulations
based on your specific design and system setup to determine the maximum
achievable frequency in your system.
High-Speed I/O Specification
Table 36 lists high-speed I/O timing for Stratix V devices.
Table 36. High-Speed I/O Specifications for Stratix V Devices (1),
C1
Symbol
(2)
(Part 1 of 4)
C2, C2L, I2, I2L
C3, I3, I3L, I3YY
C4,I4
Conditions
Unit
Min Typ
Max
Min Typ
Max Min Typ
Max
Min Typ
Max
fHSCLK_in (input
clock
frequency)
Clock boost factor
True
W = 1 to 40 (4)
Differential
I/O Standards
5
—
800
5
—
800
5
—
625
5
—
525
MHz
fHSCLK_in (input
clock
Clock boost factor
frequency)
W = 1 to 40 (4)
Single Ended
I/O
Standards (3)
5
—
800
5
—
800
5
—
625
5
—
525
MHz
fHSCLK_in (input
clock
Clock boost factor
frequency)
W = 1 to 40 (4)
Single Ended
I/O Standards
5
—
520
5
—
520
5
—
420
5
—
420
MHz
fHSCLK_OUT
(output clock
frequency)
5
—
800
5
—
800
5
—
5
—
Stratix V Device Datasheet
—
625
(5)
December 2015
525
(5)
MHz
Altera Corporation
Switching Characteristics
Page 45
Table 36. High-Speed I/O Specifications for Stratix V Devices (1),
C1
Symbol
(2)
(Part 2 of 4)
C2, C2L, I2, I2L
C3, I3, I3L, I3YY
C4,I4
Conditions
Unit
Min Typ
Max
Min Typ
Max Min Typ
Max
Min Typ
Max
Transmitter
SERDES factor J
= 3 to 10 (9), (11),
(6)
—
1600
(6)
—
1434
(6)
—
1250
(6)
—
1050
Mbps
(6)
—
1600
(6)
—
1600
(6)
—
1600
(6)
—
1250
Mbps
SERDES factor J
= 2,
uses DDR
Registers
(6)
—
(7)
(6)
—
(7)
(6)
—
(7)
(6)
—
(7)
Mbps
SERDES factor J
= 1,
uses SDR
Register
(6)
—
(7)
(6)
—
(7)
(6)
—
(7)
(6)
—
(7)
Mbps
SERDES factor J
= 4 to 10 (17)
(6)
—
1100
(6)
—
1100
(6)
—
840
(6)
—
840
Mbps
Total Jitter for
Data Rate
600 Mbps 1.25 Gbps
—
—
160
—
—
160
—
—
160
—
—
160
ps
Total Jitter for
Data Rate
< 600 Mbps
—
—
0.1
—
—
0.1
—
—
0.1
—
—
0.1
UI
Total Jitter for
Data Rate
600 Mbps - 1.25
Gbps
—
—
300
—
—
300
—
—
300
—
—
325
ps
Total Jitter for
Data Rate
< 600 Mbps
—
—
0.2
—
—
0.2
—
—
0.2
—
—
0.25
UI
(12), (13), (14), (15),
(16)
SERDES factor J
4
True
Differential
I/O Standards
- fHSDR (data
rate)
Emulated
Differential
I/O Standards
with Three
External
Output
Resistor
Networks fHSDR (data
rate) (10)
tx Jitter - True
Differential
I/O Standards
tx Jitter Emulated
Differential
I/O Standards
with Three
External
Output
Resistor
Network
December 2015
LVDS TX with
DPA (12), (14), (15),
(16)
Altera Corporation
Stratix V Device Datasheet
Page 46
Switching Characteristics
Table 36. High-Speed I/O Specifications for Stratix V Devices (1),
C1
Symbol
tRISE & tFALL
TCCS
(Part 3 of 4)
C2, C2L, I2, I2L
C3, I3, I3L, I3YY
C4,I4
Conditions
Unit
Min Typ
tDUTY
(2)
Max
Min Typ
Max Min Typ
Max
Min Typ
Max
Transmitter
output clock duty
cycle for both
True and
Emulated
Differential I/O
Standards
45
50
55
45
50
55
45
50
55
45
50
55
%
True Differential
I/O Standards
—
—
160
—
—
160
—
—
200
—
—
200
ps
Emulated
Differential I/O
Standards with
three external
output resistor
networks
—
—
250
—
—
250
—
—
250
—
—
300
ps
True Differential
I/O Standards
—
—
150
—
—
150
—
—
150
—
—
150
ps
Emulated
Differential I/O
Standards
—
—
300
—
—
300
—
—
300
—
—
300
ps
150
—
1434
150
—
1434 150
—
1250
150
—
1050
Mbps
150
—
1600
150
—
1600 150
—
1600
150
—
1250
Mbps
SERDES factor J
= 2,
uses DDR
Registers
(6)
—
(7)
(6)
—
(7)
(6)
—
(7)
(6)
—
(7)
Mbps
SERDES factor J
= 1,
uses SDR
Register
(6)
—
(7)
(6)
—
(7)
(6)
—
(7)
(6)
—
(7)
Mbps
Receiver
SERDES factor J
= 3 to 10 (11), (12),
(13), (14), (15), (16)
SERDES factor J
4
True
Differential
I/O Standards
- fHSDRDPA
(data rate)
LVDS RX with
DPA (12), (14), (15),
(16)
Stratix V Device Datasheet
December 2015
Altera Corporation
Switching Characteristics
Page 47
Table 36. High-Speed I/O Specifications for Stratix V Devices (1),
C1
Symbol
(2)
(Part 4 of 4)
C2, C2L, I2, I2L
C3, I3, I3L, I3YY
C4,I4
Conditions
Unit
Min Typ
fHSDR (data
rate)
Max
Min Typ
Max Min Typ
Max
Min Typ
Max
SERDES factor J
= 3 to 10
(6)
—
(8)
(6)
—
(8)
(6)
—
(8)
(6)
—
(8)
Mbps
SERDES factor J
= 2,
uses DDR
Registers
(6)
—
(7)
(6)
—
(7)
(6)
—
(7)
(6)
—
(7)
Mbps
SERDES factor J
= 1,
uses SDR
Register
(6)
—
(7)
(6)
—
(7)
(6)
—
(7)
(6)
—
(7)
Mbps
—
—
—
1000
0
—
—
1000
0
—
—
1000
0
—
—
1000
0
UI
—
—
—
300
—
—
300
—
—
300
—
—
300
±
PPM
—
—
—
300
—
—
300
—
—
300
—
—
300
ps
DPA Mode
DPA run
length
Soft CDR mode
Soft-CDR
PPM
tolerance
Non DPA Mode
Sampling
Window
Notes to Table 36:
(1) When J = 3 to 10, use the serializer/deserializer (SERDES) block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) This only applies to DPA and soft-CDR modes.
(4) Clock Boost Factor (W) is the ratio between the input data rate to the input clock rate.
(5) This is achieved by using the LVDS clock network.
(6) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional,
or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
(7) The maximum ideal frequency is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing
and the signal integrity simulation is clean.
(8) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board
skew margin, transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
(9) If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(10) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew
margin, transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
(11) The FMAX specification is based on the fast clock used for serial data. The interface FMAX is also dependent on the parallel clock domain which
is design-dependent and requires timing analysis.
(12) Stratix V RX LVDS will need DPA. For Stratix V TX LVDS, the receiver side component must have DPA.
(13) Stratix V LVDS serialization and de-serialization factor needs to be x4 and above.
(14) Requires package skew compensation with PCB trace length.
(15) Do not mix single-ended I/O buffer within LVDS I/O bank.
(16) Chip-to-chip communication only with a maximum load of 5 pF.
(17) When using True LVDS RX channels for emulated LVDS TX channel, only serialization factors 1 and 2 are supported.
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 48
Switching Characteristics
Figure 6 shows the dynamic phase alignment (DPA) lock time specifications with the
DPA PLL calibration option enabled.
Figure 6. DPA Lock Time Specification with DPA PLL Calibration Enabled
rx_reset
DPA Lock Time
rx_dpa_locked
256 data
transitions
96 slow
clock cycles
256 data
transitions
96 slow
clock cycles
256 data
transitions
Table 37 lists the DPA lock time specifications for Stratix V devices.
Table 37. DPA Lock Time Specifications for Stratix V GX Devices Only (1),
Training Pattern
Number of Data
Transitions in One
Repetition of the
Training Pattern
Number of
Repetitions per 256
Data Transitions (4)
Maximum
00000000001111111111
2
128
640 data transitions
00001111
2
128
640 data transitions
10010000
4
64
640 data transitions
10101010
8
32
640 data transitions
01010101
8
32
640 data transitions
Standard
SPI-4
(2), (3)
Parallel Rapid I/O
Miscellaneous
Notes to Table 37:
(1) The DPA lock time is for one channel.
(2) One data transition is defined as a 0-to-1 or 1-to-0 transition.
(3) The DPA lock time stated in this table applies to both commercial and industrial grade.
(4) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
Figure 7 shows the LVDS soft-clock data recovery (CDR)/DPA sinusoidal jitter
tolerance specification for a data rate  1.25 Gbps. Table 38 lists the LVDS
soft-CDR/DPA sinusoidal jitter tolerance specification for a data rate  1.25 Gbps.
Figure 7. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate  1.25 Gbps
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification
Jitter Amphlitude (UI)
25
8.5
0.35
0.1
F1
F2
F3
F4
Jitter Frequency (Hz)
Stratix V Device Datasheet
December 2015
Altera Corporation
Switching Characteristics
Page 49
Table 38. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for a Data Rate  1.25 Gbps
Jitter Frequency (Hz)
Sinusoidal Jitter (UI)
F1
10,000
25.000
F2
17,565
25.000
F3
1,493,000
0.350
F4
50,000,000
0.350
Figure 8 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for a
data rate < 1.25 Gbps.
Figure 8. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate < 1.25 Gbps
Sinusoidal Jitter Amplitude
20db/dec
0.1 UI
P-P
Frequency
baud/1667
20 MHz
DLL Range, DQS Logic Block, and Memory Output Clock Jitter Specifications
Table 39 lists the DLL range specification for Stratix V devices. The DLL is always in
8-tap mode in Stratix V devices.
Table 39. DLL Range Specifications for Stratix V Devices
(1)
C1
C2, C2L, I2, I2L
C3, I3, I3L, I3YY
C4,I4
Unit
300-933
300-933
300-890
300-890
MHz
Note to Table 39:
(1) Stratix V devices support memory interface frequencies lower than 300 MHz, although the reference clock that feeds the DLL must be at least
300 MHz. To support interfaces below 300 MHz, multiply the reference clock feeding the DLL to ensure the frequency is within the supported
range of the DLL.
Table 40 lists the DQS phase offset delay per stage for Stratix V devices.
Table 40. DQS Phase Offset Delay Per Setting for Stratix V Devices
December 2015
Altera Corporation
(1), (2)
(Part 1 of 2)
Speed Grade
Min
Max
Unit
C1
8
14
ps
C2, C2L, I2, I2L
8
14
ps
C3,I3, I3L, I3YY
8
15
ps
Stratix V Device Datasheet
Page 50
Switching Characteristics
(1), (2)
Table 40. DQS Phase Offset Delay Per Setting for Stratix V Devices
(Part 2 of 2)
Speed Grade
Min
Max
Unit
C4,I4
8
16
ps
Notes to Table 40:
(1) The typical value equals the average of the minimum and maximum values.
(2) The delay settings are linear with a cumulative delay variation of 40 ps for all speed grades. For example, when
using a –2 speed grade and applying a 10-phase offset setting to a 90° phase shift at 400 MHz, the expected
average cumulative delay is [625 ps + (10 × 10 ps) ± 20 ps] = 725 ps ± 20 ps.
Table 41 lists the DQS phase shift error for Stratix V devices.
Table 41. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Stratix V Devices (1)
Number of DQS Delay
Buffers
C1
C2, C2L, I2, I2L
C3, I3, I3L, I3YY
C4,I4
Unit
1
28
28
30
32
ps
2
56
56
60
64
ps
3
84
84
90
96
ps
4
112
112
120
128
ps
Notes to Table 41:
(1) This error specification is the absolute maximum and minimum error. For example, skew on three DQS delay buffers in a –2 speed grade
is ±78 ps or ±39 ps.
Table 42 lists the memory output clock jitter specifications for Stratix V devices.
Table 42. Memory Output Clock Jitter Specification for Stratix V Devices (1), (Part 1 of 2) (2),
Clock
Network
Regional
Global
C1
Parameter
C2, C2L, I2, I2L
Symbol
(3)
C3, I3, I3L,
I3YY
C4,I4
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Clock period jitter
tJIT(per)
–50
50
–50
50
–55
55
–55
55
ps
Cycle-to-cycle period
jitter
tJIT(cc)
–100
100
–100
100
–110
110
–110
110
ps
Duty cycle jitter
tJIT(duty)
–50
50
–50
50
–82.5
82.5
–82.5
82.5
ps
Clock period jitter
tJIT(per)
–75
75
–75
75
–82.5
82.5
–82.5
82.5
ps
Cycle-to-cycle period
jitter
tJIT(cc)
–150
150
–150
150
–165
165
–165
165
ps
Duty cycle jitter
tJIT(duty)
–75
75
–75
75
–90
90
–90
90
ps
Stratix V Device Datasheet
December 2015
Altera Corporation
Switching Characteristics
Page 51
Table 42. Memory Output Clock Jitter Specification for Stratix V Devices (1), (Part 2 of 2) (2),
C1
Clock
Network
PHY
Clock
Parameter
(3)
C3, I3, I3L,
I3YY
C2, C2L, I2, I2L
Symbol
C4,I4
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Clock period jitter
tJIT(per)
–25
25
–25
25
–30
30
–35
35
ps
Cycle-to-cycle period
jitter
tJIT(cc)
–50
50
–50
50
–60
60
–70
70
ps
Duty cycle jitter
tJIT(duty)
–37.5
37.5
–37.5
37.5
–45
45
–56
56
ps
Notes to Table 42:
(1) The clock jitter specification applies to the memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a
PLL output routed on a PHY, regional, or global clock network as specified. Altera recommends using PHY clock networks whenever possible.
(2) The clock jitter specification applies to the memory output clock pins clocked by an integer PLL.
(3) The memory output clock jitter is applicable when an input jitter of 30 ps peak-to-peak is applied with bit error rate (BER) -12, equivalent to 14
sigma.
OCT Calibration Block Specifications
Table 43 lists the OCT calibration block specifications for Stratix V devices.
Table 43. OCT Calibration Block Specifications for Stratix V Devices
Symbol
Description
Min
Typ
Max
Unit
OCTUSRCLK
Clock required by the OCT calibration blocks
—
—
20
MHz
TOCTCAL
Number of OCTUSRCLK clock cycles required for OCT RS/RT
calibration
—
1000
—
Cycles
TOCTSHIFT
Number of OCTUSRCLK clock cycles required for the OCT
code to shift out
—
32
—
Cycles
TRS_RT
Time required between the dyn_term_ctrl and oe signal
transitions in a bidirectional I/O buffer to dynamically switch
between OCT RS and RT (Figure 9)
—
2.5
—
ns
Figure 9 shows the timing diagram for the oe and dyn_term_ctrl signals.
Figure 9. Timing Diagram for oe and dyn_term_ctrl Signals
Tristate
RX
Tristate
TX
RX
oe
dyn_term_ctrl
TRS_RT
December 2015
Altera Corporation
TRS_RT
Stratix V Device Datasheet
Page 52
Configuration Specification
Duty Cycle Distortion (DCD) Specifications
Table 44 lists the worst-case DCD for Stratix V devices.
Table 44. Worst-Case DCD on Stratix V I/O Pins (1)
C1
C3, I3, I3L,
I3YY
C2, C2L, I2, I2L
Symbol
Output Duty Cycle
C4,I4
Unit
Min
Max
Min
Max
Min
Max
Min
Max
45
55
45
55
45
55
45
55
%
Note to Table 44:
(1) The DCD numbers do not cover the core clock network.
Configuration Specification
POR Delay Specification
Power-on reset (POR) delay is defined as the delay between the time when all the
power supplies monitored by the POR circuitry reach the minimum recommended
operating voltage to the time when the nSTATUS is released high and your device is
ready to begin configuration.
f For more information about the POR delay, refer to the Hot Socketing and Power-On
Reset in Stratix V Devices chapter.
Table 45 lists the fast and standard POR delay specification.
Table 45. Fast and Standard POR Delay Specification
POR Delay
(1)
Minimum
Fast
Standard
Maximum
4 ms
12 ms
100 ms
300 ms
Note to Table 45:
(1) You can select the POR delay based on the MSEL settings as described in the MSEL Pin Settings section of the
“Configuration, Design Security, and Remote System Upgrades in Stratix V Devices” chapter.
JTAG Configuration Specifications
Table 46 lists the JTAG timing parameters and values for Stratix V devices.
Table 46. JTAG Timing Parameters and Values for Stratix V Devices
Symbol
Min
Max
Unit
tJCP
TCK clock period (2)
30
—
ns
tJCP
TCK clock period (2)
167
—
ns
14
—
ns
14
—
ns
tJCH
Stratix V Device Datasheet
Description
TCK clock high
time (2)
time (2)
tJCL
TCK clock low
tJPSU (TDI)
TDI JTAG port setup time
2
—
ns
tJPSU (TMS)
TMS JTAG port setup time
3
—
ns
December 2015
Altera Corporation
Configuration Specification
Page 53
Table 46. JTAG Timing Parameters and Values for Stratix V Devices
Symbol
Description
tJPH
Min
Max
Unit
5
—
ns
JTAG port hold time
tJPCO
JTAG port clock to output
—
11
(1)
ns
ns
ns
tJPZX
JTAG port high impedance to valid output
—
14
(1)
tJPXZ
JTAG port valid output to high impedance
—
14
(1)
Notes to Table 46:
(1) A 1 ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 12 ns if VCCIO of the TDO
I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.
(2) The minimum TCK clock period is 167 ns if VCCBAT is within the range 1.2V-1.5V when you perform the volatile
key programming.
Raw Binary File Size
For the POR delay specification, refer to the “POR Delay Specification” section of the
“Configuration, Design Security, and Remote System Upgrades in Stratix V Devices”.
Table 47 lists the uncompressed raw binary file (.rbf) sizes for Stratix V devices.
Table 47. Uncompressed .rbf Sizes for Stratix V Devices
Family
Device
Configuration .rbf Size (bits)
H35, F40, F35 (2)
213,798,880
562,392
H29, F35 (3)
137,598,880
564,504
5SGXA4
—
213,798,880
563,672
5SGXA5
—
269,979,008
562,392
5SGXA7
—
269,979,008
562,392
5SGXA9
—
342,742,976
700,888
5SGXA3
Stratix V GX
Stratix V GT
5SGXAB
—
342,742,976
700,888
5SGXB5
—
270,528,640
584,344
5SGXB6
—
270,528,640
584,344
5SGXB9
—
342,742,976
700,888
5SGXBB
—
342,742,976
700,888
5SGTC5
—
269,979,008
562,392
5SGTC7
—
269,979,008
562,392
5SGSD3
—
137,598,880
564,504
F1517
213,798,880
563,672
—
137,598,880
564,504
5SGSD5
—
213,798,880
563,672
5SGSD6
—
293,441,888
565,528
5SGSD8
—
293,441,888
565,528
5SGSD4
Stratix V GS
December 2015
IOCSR .rbf Size (bits) (4),
Package
Altera Corporation
(5)
Stratix V Device Datasheet
Page 54
Configuration Specification
Table 47. Uncompressed .rbf Sizes for Stratix V Devices
Family
Stratix V E (1)
IOCSR .rbf Size (bits) (4),
Device
Package
Configuration .rbf Size (bits)
5SEE9
—
342,742,976
700,888
5SEEB
—
342,742,976
700,888
(5)
Notes to Table 47:
(1) Stratix V E devices do not have PCI Express (PCIe) hard IP. Stratix V E devices do not support the CvP configuration scheme.
(2) 36-transceiver devices.
(3) 24-transceiver devices.
(4) File size for the periphery image.
(5) The IOCSR .rbf size is specifically for the CvP feature.
Use the data in Table 47 to estimate the file size before design compilation. Different
configuration file formats, such as a hexadecimal (.hex) or tabular text file (.ttf)
format, have different file sizes. For the different types of configuration file and file
sizes, refer to the Quartus II software. However, for a specific version of the Quartus II
software, any design targeted for the same device has the same uncompressed
configuration file size. If you are using compression, the file size can vary after each
compilation because the compression ratio depends on your design.
f For more information about setting device configuration options, refer to
Configuration, Design Security, and Remote System Upgrades in Stratix V Devices. For
creating configuration files, refer to the Quartus II Help.
Table 48 lists the minimum configuration time estimates for Stratix V devices.
Table 48. Minimum Configuration Time Estimation for Stratix V Devices
Active Serial (1)
Variant
Member
Code
Fast Passive Parallel (2)
Width
DCLK (MHz)
Min Config
Time (s)
Width
DCLK (MHz)
Min Config
Time (s)
4
100
0.534
32
100
0.067
4
100
0.344
32
100
0.043
A4
4
100
0.534
32
100
0.067
A5
4
100
0.675
32
100
0.084
A7
4
100
0.675
32
100
0.084
A9
4
100
0.857
32
100
0.107
AB
4
100
0.857
32
100
0.107
B5
4
100
0.676
32
100
0.085
B6
4
100
0.676
32
100
0.085
B9
4
100
0.857
32
100
0.107
BB
4
100
0.857
32
100
0.107
C5
4
100
0.675
32
100
0.084
C7
4
100
0.675
32
100
0.084
A3
GX
GT
Stratix V Device Datasheet
December 2015
Altera Corporation
Configuration Specification
Page 55
Table 48. Minimum Configuration Time Estimation for Stratix V Devices
Active Serial (1)
Variant
Width
DCLK (MHz)
Min Config
Time (s)
Width
DCLK (MHz)
Min Config
Time (s)
D3
4
100
0.344
32
100
0.043
4
100
0.534
32
100
0.067
4
100
0.344
32
100
0.043
D5
4
100
0.534
32
100
0.067
D6
4
100
0.741
32
100
0.093
D8
4
100
0.741
32
100
0.093
D4
GS
E
Fast Passive Parallel (2)
Member
Code
E9
4
100
0.857
32
100
0.107
EB
4
100
0.857
32
100
0.107
Notes to Table 48:
(1) DCLK frequency of 100 MHz using external CLKUSR.
(2) Max FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
Fast Passive Parallel Configuration Timing
This section describes the fast passive parallel (FPP) configuration timing parameters
for Stratix V devices.
DCLK-to-DATA[] Ratio for FPP Configuration
FPP configuration requires a different DCLK-to-DATA[]ratio when you enable the
design security, decompression, or both features. Table 49 lists the DCLK-to-DATA[]ratio
for each combination.
Table 49. DCLK-to-DATA[] Ratio
Configuration
Scheme
FPP ×8
FPP ×16
December 2015
Altera Corporation
(1)
(Part 1 of 2)
Decompression
Design Security
DCLK-to-DATA[]
Ratio
Disabled
Disabled
1
Disabled
Enabled
1
Enabled
Disabled
2
Enabled
Enabled
2
Disabled
Disabled
1
Disabled
Enabled
2
Enabled
Disabled
4
Enabled
Enabled
4
Stratix V Device Datasheet
Page 56
Configuration Specification
Table 49. DCLK-to-DATA[] Ratio
Configuration
Scheme
FPP ×32
(1)
(Part 2 of 2)
Decompression
DCLK-to-DATA[]
Ratio
Design Security
Disabled
Disabled
1
Disabled
Enabled
4
Enabled
Disabled
8
Enabled
Enabled
8
Note to Table 49:
(1) Depending on the DCLK-to-DATA[] ratio, the host must send a DCLK frequency that is r times the data rate in bytes
per second (Bps), or words per second (Wps). For example, in FPP ×16 when the DCLK-to-DATA[] ratio is 2, the
DCLK frequency must be 2 times the data rate in Wps. Stratix V devices use the additional clock cycles to decrypt
and decompress the configuration data.
1
If the DCLK-to-DATA[] ratio is greater than 1, at the end of configuration, you can only
stop the DCLK (DCLK-to-DATA[] ratio – 1) clock cycles after the last data is latched into
the Stratix V device.
Figure 10 shows the configuration interface connections between the Stratix V device
and a MAX II or MAX V device for single device configuration.
Figure 10. Single Device FPP Configuration Using an External Host
Memory
ADDR DATA[7..0]
VCCPGM (1) VCCPGM (1)
Stratix V Device
MSEL[4..0]
(3)
CONF_DONE
External Host
(MAX II Device,
MAX V Device, or
Microprocessor)
nSTATUS
nCEO
nCE
GND
N.C. (2)
DATA[31..0] (4)
nCONFIG
DCLK
Notes to Figure 10:
(1) Connect the resistor to a supply that provides an acceptable input signal for the Stratix V device. VCCPGM must be high
enough to meet the VIH specification of the I/O on the device and the external host. Altera recommends powering up
all configuration system I/Os with VCCPGM.
(2) You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed another device's nCE pin.
(3) The MSEL pin settings vary for different data width, configuration voltage standards, and POR delay. To connect MSEL,
refer to the MSEL Pin Settings section of the “Configuration, Design Security, and Remote System Upgrades in Stratix
V Devices” chapter.
(4) If you use FPP ×8, use DATA[7..0]. If you use FPP ×16, use DATA[15..0].
Stratix V Device Datasheet
December 2015
Altera Corporation
Configuration Specification
Page 57
FPP Configuration Timing when DCLK-to-DATA [] = 1
Figure 11 shows the timing waveform for FPP configuration when using a MAX II or
MAX V device as an external host. This waveform shows timing when the DCLK-toDATA[] ratio is 1.
Figure 11. FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is 1
(1), (2)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (3)
tSTATUS
tCF2ST0
t
(7)
CLK
CONF_DONE (4)
tCF2CD
tST2CK
tCH tCL
(5)
DCLK
tDH
DATA[31..0](6)
Word 0 Word 1 Word 2 Word 3
User Mode
Word n-2 Word n-1
tDSU
User I/O
High-Z
User Mode
INIT_DONE (8)
tCD2UM
Notes to Figure 11:
(1) Use this timing waveform when the DCLK-to-DATA[] ratio is 1.
(2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic-high levels. When
nCONFIG is pulled low, a reconfiguration cycle begins.
(3) After power-up, the Stratix V device holds nSTATUS low for the time of the POR delay.
(4) After power-up, before and during configuration, CONF_DONE is low.
(5) Do not leave DCLK floating after configuration. DCLK is ignored after configuration is complete. It can toggle high or low if required.
(6) For FPP ×16, use DATA[15..0]. For FPP ×8, use DATA[7..0]. DATA[31..0] are available as a user I/O pin after configuration. The state of this
pin depends on the dual-purpose pin settings.
(7) To ensure a successful configuration, send the entire configuration data to the Stratix V device. CONF_DONE is released high when the Stratix V
device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin initialization
and enter user mode.
(8) After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low.
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 58
Configuration Specification
Table 50 lists the timing parameters for Stratix V devices for FPP configuration when
the DCLK-to-DATA[] ratio is 1.
Table 50. FPP Timing Parameters for Stratix V Devices (1)
Symbol
Parameter
Minimum
Maximum
Units
tCF2CD
nCONFIG low to CONF_DONE low
—
600
ns
tCF2ST0
nCONFIG low to nSTATUS low
—
600
ns
tCFG
nCONFIG low pulse width
2
—
s
268
1,506 (2)
s
s
tSTATUS
nSTATUS low pulse width
nCONFIG high to nSTATUS high
—
1,506 (3)
tCF2CK (6) nCONFIG high to first rising edge on DCLK
1,506
—
s
tST2CK (6) nSTATUS high to first rising edge of DCLK
2
—
s
5.5
—
ns
0
—
ns
tCF2ST1
tDSU
DATA[] setup time before rising edge on DCLK
tDH
DATA[] hold time after rising edge on DCLK
tCH
DCLK high time
0.45  1/fMAX
—
s
tCL
DCLK low time
0.45  1/fMAX
—
s
tCLK
DCLK period
1/fMAX
—
s
DCLK frequency (FPP 8/16)
—
125
MHz
DCLK frequency (FPP 32)
—
100
MHz
175
437
s
—
—
—
—
fMAX
(4)
tCD2UM
CONF_DONE high to user mode
tCD2CU
CONF_DONE high to CLKUSR enabled
tCD2UMC
CONF_DONE high to user mode with CLKUSR option on
4 × maximum
DCLK period
tCD2CU +
(17,408  CLKUSR
period) (5)
Notes to Table 50:
(1) Use these timing parameters when the decompression and design security features are disabled.
(2) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(3) This value is applicable if you do not delay configuration by externally holding the nSTATUS low.
(4) The minimum and maximum numbers apply only if you chose the internal oscillator as the clock source for initializing the device.
(5) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to the
Initialization section of the “Configuration, Design Security, and Remote System Upgrades in Stratix V Devices” chapter.
(6) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
FPP Configuration Timing when DCLK-to-DATA [] > 1
Figure 12 shows the timing waveform for FPP configuration when using a MAX II
device, MAX V device, or microprocessor as an external host. This waveform shows
timing when the DCLK-to-DATA[]ratio is more than 1.
Stratix V Device Datasheet
December 2015
Altera Corporation
Configuration Specification
Page 59
Figure 12. FPP Configuration Timing Waveform When the DCLK-to-DATA[] Ratio is >1
(1), (2)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (3)
tSTATUS
tCF2ST0
CONF_DONE (4)
tCF2CD
DCLK (6)
tCL
tST2CK
(8)
tCH
1
2
r
1
2
r
(7)
1
r
1
(5)
2
tCLK
Word 0
DATA[31..0] (8)
tDSU
tDH
Word 1
Word 3
User Mod
Word (n-1)
tDH
User Mod
High-Z
User I/O
INIT_DONE (9)
tCD2UM
Notes to Figure 12:
(1) Use this timing waveform and parameters when the DCLK-to-DATA[]ratio is >1. To find out the DCLK-to-DATA[] ratio for your system, refer
to Table 49 on page 55.
(2) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels.
When nCONFIG is pulled low, a reconfiguration cycle begins.
(3) After power-up, the Stratix V device holds nSTATUS low for the time as specified by the POR delay.
(4) After power-up, before and during configuration, CONF_DONE is low.
(5) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(6) “r” denotes the DCLK-to-DATA[] ratio. For the DCLK-to-DATA[] ratio based on the decompression and the design security feature enable
settings, refer to Table 49 on page 55.
(7) If needed, pause DCLK by holding it low. When DCLK restarts, the external host must provide data on the DATA[31..0] pins prior to sending
the first DCLK rising edge.
(8) To ensure a successful configuration, send the entire configuration data to the Stratix V device. CONF_DONE is released high after the Stratix V
device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin
initialization and enter user mode.
(9) After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low.
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 60
Configuration Specification
Table 51 lists the timing parameters for Stratix V devices for FPP configuration when
the DCLK-to-DATA[]ratio is more than 1.
Table 51. FPP Timing Parameters for Stratix V Devices When the DCLK-to-DATA[] Ratio is >1 (1)
Symbol
Parameter
Minimum
Maximum
Units
tCF2CD
nCONFIG low to CONF_DONE low
—
600
ns
tCF2ST0
nCONFIG low to nSTATUS low
—
600
ns
tCFG
nCONFIG low pulse width
2
—
s
268
1,506 (2)
s
s
tSTATUS
nSTATUS low pulse width
nCONFIG high to nSTATUS high
—
1,506 (2)
tCF2CK (5) nCONFIG high to first rising edge on DCLK
1,506
—
s
tST2CK (5) nSTATUS high to first rising edge of DCLK
2
—
s
—
ns
—
s
tCF2ST1
tDSU
DATA[] setup time before rising edge on DCLK
5.5
(5)
tDH
DATA[] hold time after rising edge on DCLK
N–1/fDCLK
tCH
DCLK high time
0.45  1/fMAX
—
s
tCL
DCLK low time
0.45  1/fMAX
—
s
tCLK
DCLK period
1/fMAX
—
s
DCLK frequency (FPP 8/16)
—
125
MHz
DCLK frequency (FPP 32)
—
100
MHz
tR
Input rise time
—
40
ns
tF
Input fall time
—
40
ns
175
437
s
4 × maximum
DCLK period
—
—
tCD2CU +
(17,408  CLKUSR
period) (4)
—
—
fMAX
(3)
tCD2UM
CONF_DONE high to user mode
tCD2CU
CONF_DONE high to CLKUSR enabled
tCD2UMC
CONF_DONE high to user mode with CLKUSR option on
Notes to Table 51:
(1) Use these timing parameters when you use the decompression and design security features.
(2) You can obtain this value if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(3) The minimum and maximum numbers apply only if you use the internal oscillator as the clock source for initializing the device.
(4) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to the
Initialization section of the “Configuration, Design Security, and Remote System Upgrades in Stratix V Devices” chapter.
(5) N is the DCLK-to-DATA ratio and fDCLK is the DCLK frequency the system is operating.
(6) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
Stratix V Device Datasheet
December 2015
Altera Corporation
Configuration Specification
Page 61
Active Serial Configuration Timing
Table 52 lists the DCLK frequency specification in the AS configuration scheme.
Table 52. DCLK Frequency Specification in the AS Configuration Scheme (1),
(2)
Minimum
Typical
Maximum
Unit
5.3
7.9
12.5
MHz
10.6
15.7
25.0
MHz
21.3
31.4
50.0
MHz
42.6
62.9
100.0
MHz
Notes to Table 52:
(1) This applies to the DCLK frequency specification when using the internal oscillator as the configuration clock
source.
(2) The AS multi-device configuration scheme does not support DCLK frequency of 100 MHz.
Figure 13 shows the single-device configuration setup for an AS ×1 mode.
Figure 13. AS Configuration Timing
tCF2ST1
nCONFIG
nSTATUS
CONF_DONE
nCSO
DCLK
tCO
tDH
Read Address
AS_DATA0/ASDO
tSU
AS_DATA1 (1)
bit 0
bit 1
bit (n − 2) bit (n − 1)
tCD2UM (2)
INIT_DONE (3)
User I/O
User Mode
Notes to Figure 13:
(1) If you are using AS ×4 mode, this signal represents the AS_DATA[3..0] and EPCQ sends in 4-bits of data for each DCLK cycle.
(2) The initialization clock can be from internal oscillator or CLKUSR pin.
(3) After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low.
Table 53 lists the timing parameters for AS 1 and AS 4 configurations in Stratix V
devices.
Table 53. AS Timing Parameters for AS 1 and AS 4 Configurations in Stratix V Devices (1),
Symbol
Parameter
(2)
(Part 1 of 2)
Minimum
Maximum
Units
tCO
DCLK falling edge to AS_DATA0/ASDO output
—
2
ns
tSU
Data setup time before falling edge on DCLK
1.5
—
ns
tH
Data hold time after falling edge on DCLK
0
—
ns
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 62
Configuration Specification
Table 53. AS Timing Parameters for AS 1 and AS 4 Configurations in Stratix V Devices (1),
Symbol
Parameter
(2)
(Part 2 of 2)
Minimum
Maximum
Units
175
437
s
(3)
tCD2UM
CONF_DONE high to user mode
tCD2CU
CONF_DONE high to CLKUSR enabled
4 × maximum DCLK
period
—
—
tCD2UMC
CONF_DONE high to user mode with CLKUSR option on
tCD2CU + (17,408 
CLKUSR period)
—
—
Notes to Table 53:
(1) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
(2) tCF2CD, tCF2ST0, tCFG, tSTATUS, and tCF2ST1 timing parameters are identical to the timing parameters for PS mode listed in Table 54 on page 63.
(3) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on this pin, refer to the
Initialization section of the “Configuration, Design Security, and Remote System Upgrades in Stratix V Devices” chapter.
Passive Serial Configuration Timing
Figure 14 shows the timing waveform for a passive serial (PS) configuration when
using a MAX II device, MAX V device, or microprocessor as an external host.
Figure 14. PS Configuration Timing Waveform
(1)
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
t
(6)
CLK
CONF_DONE (3)
tCF2CD
tST2CK
tCH tCL
(4)
DCLK
tDH
DATA0
Bit 0 Bit 1 Bit 2 Bit 3
(5)
Bit (n-1)
tDSU
User I/O
High-Z
User Mode
INIT_DONE (7)
tCD2UM
Notes to Figure 14:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When
nCONFIG is pulled low, a reconfiguration cycle begins.
(2) After power-up, the Stratix V device holds nSTATUS low for the time of the POR delay.
(3) After power-up, before and during configuration, CONF_DONE is low.
(4) Do not leave DCLK floating after configuration. You can drive it high or low, whichever is more convenient.
(5) DATA0 is available as a user I/O pin after configuration. The state of this pin depends on the dual-purpose pin settings in the Device and Pins
Option.
(6) To ensure a successful configuration, send the entire configuration data to the Stratix V device. CONF_DONE is released high after the Stratix V
device receives all the configuration data successfully. After CONF_DONE goes high, send two additional falling edges on DCLK to begin
initialization and enter user mode.
(7) After the option bit to enable the INIT_DONE pin is configured into the device, the INIT_DONE goes low.
Stratix V Device Datasheet
December 2015
Altera Corporation
Configuration Specification
Page 63
Table 54 lists the PS configuration timing parameters for Stratix V devices.
Table 54. PS Timing Parameters for Stratix V Devices
Symbol
Parameter
Minimum
Maximum
Units
tCF2CD
nCONFIG low to CONF_DONE low
—
600
ns
tCF2ST0
nCONFIG low to nSTATUS low
—
600
ns
tCFG
nCONFIG low pulse width
2
—
s
s
tSTATUS
nSTATUS low pulse width
268
1,506 (1)
tCF2ST1
nCONFIG high to nSTATUS high
—
1,506 (2)
s
tCF2CK (5)
nCONFIG high to first rising edge on DCLK
1,506
—
s
nSTATUS high to first rising edge of DCLK
2
—
s
5.5
—
ns
0
—
ns
tST2CK
(5)
tDSU
DATA[] setup time before rising edge on DCLK
tDH
DATA[] hold time after rising edge on DCLK
tCH
DCLK high time
0.45  1/fMAX
—
s
tCL
DCLK low time
0.45  1/fMAX
—
s
tCLK
DCLK period
fMAX
DCLK frequency
tCD2UM
CONF_DONE high to user mode
tCD2CU
CONF_DONE high to CLKUSR enabled
tCD2UMC
CONF_DONE high to user mode with CLKUSR option on
(3)
1/fMAX
—
s
—
125
MHz
175
437
s
4 × maximum
DCLK period
—
—
tCD2CU +
(17,408  CLKUSR
period) (4)
—
—
Notes to Table 54:
(1) This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
(2) This value is applicable if you do not delay configuration by externally holding the nSTATUS low.
(3) The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for initializing the device.
(4) To enable the CLKUSR pin as the initialization clock source and to obtain the maximum frequency specification on these pins, refer to the
“Initialization” section.
(5) If nSTATUS is monitored, follow the tST2CK specification. If nSTATUS is not monitored, follow the tCF2CK specification.
Initialization
Table 55 lists the initialization clock source option, the applicable configuration
schemes, and the maximum frequency.
Table 55. Initialization Clock Source Option and the Maximum Frequency
Initialization Clock
Source
Internal Oscillator
CLKUSR
DCLK
Configuration Schemes
Maximum
Frequency
AS, PS, FPP
12.5 MHz
AS, PS, FPP
PS, FPP
(2)
125 MHz
Minimum Number of Clock
Cycles (1)
17,408
125 MHz
Notes to Table 55:
(1) The minimum number of clock cycles required for device initialization.
(2) To enable CLKUSR as the initialization clock source, turn on the Enable user-supplied start-up clock (CLKUSR)
option in the Quartus II software from the General panel of the Device and Pin Options dialog box.
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 64
I/O Timing
Remote System Upgrades
Table 56 lists the timing parameter specifications for the remote system upgrade
circuitry.
Table 56. Remote System Upgrade Circuitry Timing Specifications
Parameter
tRU_nCONFIG
Minimum
Maximum
Unit
250
—
ns
250
—
ns
(1)
tRU_nRSTIMER
(2)
Notes to Table 56:
(1) This is equivalent to strobing the reconfiguration input of the ALTREMOTE_UPDATE megafunction high for the
minimum timing specification. For more information, refer to the Remote System Upgrade State Machine section
of the “Configuration, Design Security, and Remote System Upgrades in Stratix V Devices” chapter.
(2) This is equivalent to strobing the reset_timer input of the ALTREMOTE_UPDATE megafunction high for the
minimum timing specification. For more information, refer to the User Watchdog Timer section of the
“Configuration, Design Security, and Remote System Upgrades in Stratix V Devices” chapter.
User Watchdog Internal Circuitry Timing Specification
Table 57 lists the operating range of the 12.5-MHz internal oscillator.
Table 57. 12.5-MHz Internal Oscillator Specifications
Minimum
Typical
Maximum
Units
5.3
7.9
12.5
MHz
I/O Timing
Altera offers two ways to determine I/O timing—the Excel-based I/O Timing and the
Quartus II Timing Analyzer.
Excel-based I/O timing provides pin timing performance for each device density and
speed grade. The data is typically used prior to designing the FPGA to get an estimate
of the timing budget as part of the link timing analysis. The Quartus II Timing
Analyzer provides a more accurate and precise I/O timing data based on the specifics
of the design after you complete place-and-route.
f You can download the Excel-based I/O Timing spreadsheet from the Stratix V
Devices Documentation web page.
Programmable IOE Delay
Table 58 lists the Stratix V IOE programmable delay settings.
Table 58. IOE Programmable Delay for Stratix V Devices (Part 1 of 2)
Fast Model
Min
Parameter Available
Offset
(1)
Settings
(2)
Industrial Commercial
Slow Model
C1
C2
C3
C4
I2
I3,
I3YY
I4
Unit
D1
64
0
0.464
0.493
0.838
0.838
0.924 1.011 0.844 0.921 1.006
ns
D2
32
0
0.230
0.244
0.415
0.415
0.459 0.503 0.417 0.456 0.500
ns
Stratix V Device Datasheet
December 2015
Altera Corporation
Glossary
Page 65
Table 58. IOE Programmable Delay for Stratix V Devices (Part 2 of 2)
Fast Model
Min
Parameter Available
Offset
(1)
Settings
(2)
Industrial Commercial
Slow Model
C1
C2
C3
C4
I3,
I3YY
I2
I4
Unit
D3
8
0
1.587
1.699
2.793
2.793
2.992 3.192 2.811 3.047 3.257
ns
D4
64
0
0.464
0.492
0.838
0.838
0.924 1.011 0.843 0.920 1.006
ns
D5
64
0
0.464
0.493
0.838
0.838
0.924 1.011 0.844 0.921 1.006
ns
D6
32
0
0.229
0.244
0.415
0.415
0.458 0.503 0.418 0.456 0.499
ns
Notes to Table 58:
(1) You can set this value in the Quartus II software by selecting D1, D2, D3, D5, and D6 in the Assignment Name column of Assignment Editor.
(2) Minimum offset does not include the intrinsic delay.
Programmable Output Buffer Delay
Table 59 lists the delay chain settings that control the rising and falling edge delays of
the output buffer. The default delay is 0 ps.
Table 59. Programmable Output Buffer Delay for Stratix V Devices (1)
Symbol
DOUTBUF
Parameter
Rising and/or falling edge
delay
Typical
Unit
0 (default)
ps
25
ps
50
ps
75
ps
Note to Table 59:
(1) You can set the programmable output buffer delay in the Quartus II software by setting the Output Buffer Delay
Control assignment to either positive, negative, or both edges, with the specific values stated here (in ps) for the
Output Buffer Delay assignment.
Glossary
Table 60 lists the glossary for this chapter.
Table 60. Glossary (Part 1 of 4)
Letter
Subject
Definitions
—
—
D
—
—
E
—
—
A
B
C
F
fHSCLK
Left and right PLL input clock frequency.
fHSDR
High-speed I/O block—Maximum and minimum LVDS data transfer rate
(fHSDR = 1/TUI), non-DPA.
fHSDRDPA
High-speed I/O block—Maximum and minimum LVDS data transfer rate
(fHSDRDPA = 1/TUI), DPA.
December 2015
Altera Corporation
Stratix V Device Datasheet
Page 66
Glossary
Table 60. Glossary (Part 2 of 4)
Letter
Subject
Definitions
—
—
G
H
I
J
High-speed I/O block—Deserialization factor (width of parallel data bus).
JTAG Timing Specifications:
TMS
TDI
J
t JCP
JTAG Timing
Specifications
t JCH
t JCL
t JPH
t JPSU
TCK
tJPZX
t JPXZ
t JPCO
TDO
K
L
M
—
—
N
O
Diagram of PLL Specifications
(1)
CLKOUT Pins
Switchover
fOUT_EXT
4
CLK
fIN
N
fINPFD
PFD
CP
LF
VCO fVCO
Core Clock
P
Counters
C0..C17
fOUT
PLL
Specifications
GCLK
RCLK
Delta Sigma
Modulator
Key
Reconfigurable in User Mode
External Feedback
Note:
(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.
Q
R
—
RL
Stratix V Device Datasheet
—
Receiver differential input discrete resistor (external to the Stratix V device).
December 2015
Altera Corporation
Glossary
Page 67
Table 60. Glossary (Part 3 of 4)
Letter
Subject
SW (sampling
window)
Definitions
Timing Diagram—the period of time during which the data must be valid in order to capture
it correctly. The setup and hold times determine the ideal strobe position within the sampling
window, as shown:
Bit Time
0.5 x TCCS
RSKM
Sampling Window
(SW)
RSKM
0.5 x TCCS
The JEDEC standard for SSTL and HSTL I/O defines both the AC and DC input signal values.
The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input has crossed the AC value, the
receiver changes to the new logic state.
The new logic state is then maintained as long as the input stays beyond the DC threshold.
This approach is intended to provide predictable receiver timing in the presence of input
waveform ringing:
S
Single-Ended Voltage Referenced I/O Standard
Single-ended
voltage
referenced I/O
standard
VCCIO
VOH
VIH (AC )
VIH(DC)
VREF
VIL(DC)
VIL(AC )
VOL
VSS
High-speed receiver and transmitter input and output clock period.
tC
The timing difference between the fastest and slowest output edges, including tCO variation
TCCS (channeland clock skew, across channels driven by the same PLL. The clock is included in the TCCS
to-channel-skew)
measurement (refer to the Timing Diagram figure under SW in this table).
High-speed I/O block—Duty cycle on the high-speed transmitter output clock.
Timing Unit Interval (TUI)
tDUTY
The timing budget allowed for skew, propagation delays, and the data sampling window.
(TUI = 1/(receiver input clock frequency multiplication factor) = tC/w)
T
tFALL
Signal high-to-low transition time (80-20%)
tINCCJ
Cycle-to-cycle jitter tolerance on the PLL clock input.
tOUTPJ_IO
Period jitter on the general purpose I/O driven by a PLL.
tOUTPJ_DC
Period jitter on the dedicated clock output driven by a PLL.
tRISE
Signal low-to-high transition time (20-80%)
U
December 2015
—
Altera Corporation
—
Stratix V Device Datasheet
Page 68
Document Revision History
Table 60. Glossary (Part 4 of 4)
Letter
V
W
Subject
Definitions
VCM(DC)
DC common mode input voltage.
VICM
Input common mode voltage—The common mode of the differential signal at the receiver.
VID
Input differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the receiver.
VDIF(AC)
AC differential input voltage—Minimum AC input differential voltage required for switching.
VDIF(DC)
DC differential input voltage— Minimum DC input differential voltage required for switching.
VIH
Voltage input high—The minimum positive voltage applied to the input which is accepted by
the device as a logic high.
VIH(AC)
High-level AC input voltage
VIH(DC)
High-level DC input voltage
VIL
Voltage input low—The maximum positive voltage applied to the input which is accepted by
the device as a logic low.
VIL(AC)
Low-level AC input voltage
VIL(DC)
Low-level DC input voltage
VOCM
Output common mode voltage—The common mode of the differential signal at the
transmitter.
VOD
Output differential voltage swing—The difference in voltage between the positive and
complementary conductors of a differential transmission at the transmitter.
VSWING
Differential input voltage
VX
Input differential cross point voltage
VOX
Output differential cross point voltage
W
High-speed I/O block—clock boost factor
X
Y
—
—
Z
Document Revision History
Table 61 lists the revision history for this chapter.
Table 61. Document Revision History (Part 1 of 4)
Date
Version
December
December 2015
Stratix V Device Datasheet
3.6
3.5
Changes
■
Added a footnote to the “High-Speed I/O Specifications for Stratix V Devices” table.
■
Changed the transmitter, receiver, and ATX PLL data rate specifications in the
“Transceiver Specifications for Stratix V GX and GS Devices” table.
■
Changed the configuration .rbf sizes in the “Uncompressed .rbf Sizes for Stratix V
Devices” table.
December 2015
Altera Corporation
Document Revision History
Page 69
Table 61. Document Revision History (Part 2 of 4)
Date
Version
Changes
■
July 2015
December 2015
■
“Transceiver Specifications for Stratix V GX and GS Devices”
■
“Stratix V Standard PCS Approximate Maximum Date Rate”
■
“Stratix V 10G PCS Approximate Maximum Data Rate”
■
Changed the conditions for reference clock rise and fall time, and added a note to the
“Transceiver Specifications for Stratix V GX and GS Devices” table.
■
Added a note to the “Minimum differential eye opening at receiver serial input pins”
specification in the “Transceiver Specifications for Stratix V GX and GS Devices” table.
■
Changed the tCO maximum value in the “AS Timing Parameters for AS ´1 and AS ´4
Configurations in Stratix V Devices” table.
■
Removed the CDR ppm tolerance specification from the “Transceiver Specifications for
Stratix V GX and GS Devices” table.
3.4
Altera Corporation
Changed the data rate specification for transceiver speed grade 3 in the following tables:
Stratix V Device Datasheet
Page 70
Document Revision History
Table 61. Document Revision History (Part 3 of 4)
Date
Version
November 2014
3.3
Changes
■
Added the I3YY speed grade and changed the data rates for the GX channel in Table 1.
■
Added the I3YY speed grade to the VCC description in Table 6.
■
Added the I3YY speed grade to VCCHIP_L, VCCHIP_R, VCCHSSI_L, and VCCHSSI_R descriptions in
Table 7.
■
Added 240-to Table 11.
■
Changed CDR PPM tolerance in Table 23.
■
Added additional max data rate for fPLL in Table 23.
■
Added the I3YY speed grade and changed the data rates for transceiver speed grade 3 in
Table 25.
■
Added the I3YY speed grade and changed the data rates for transceiver speed grade 3 in
Table 26.
■
Changed CDR PPM tolerance in Table 28.
■
Added additional max data rate for fPLL in Table 28.
■
Changed the mode descriptions for MLAB and M20K in Table 33.
■
Changed the Max value of fHSCLK_OUT for the C2, C2L, I2, I2L speed grades in Table 36.
■
Changed the frequency ranges for C1 and C2 in Table 39.
■
Changed the .rbf file sizes for 5SGSD6 and 5SGSD8 in Table 47.
■
Added note about nSTATUS to Table 50, Table 51, Table 54.
■
Changed the available settings in Table 58.
■
Changed the note in “Periphery Performance”.
■
Updated the “I/O Standard Specifications” section.
■
Updated the “Raw Binary File Size” section.
■
Updated the receiver voltage input range in Table 22.
■
Updated the max frequency for the LVDS clock network in Table 36.
■
Updated the DCLK note to Figure 11.
■
Updated Table 23 VOCM (DC Coupled) condition.
■
Updated Table 6 and Table 7.
■
Added the DCLK specification to Table 55.
■
Updated the notes for Table 47.
■
Updated the list of parameters for Table 56.
November 2013
3.2
■
Updated Table 28
November 2013
3.1
■
Updated Table 33
November 2013
3.0
■
Updated Table 23 and Table 28
October 2013
2.9
■
Updated the “Transceiver Characterization” section
■
Updated Table 3, Table 12, Table 14, Table 19, Table 20, Table 23, Table 24, Table 28,
Table 30, Table 31, Table 32, Table 33, Table 36, Table 39, Table 40, Table 41, Table 42,
Table 47, Table 53, Table 58, and Table 59
■
Added Figure 1 and Figure 3
■
Added the “Transceiver Characterization” section
■
Removed all “Preliminary” designations.
October 2013
Stratix V Device Datasheet
2.8
December 2015
Altera Corporation
Document Revision History
Page 71
Table 61. Document Revision History (Part 4 of 4)
Date
Version
May 2013
2.7
February 2013
December 2012
June 2012
2.5
Updated Table 2, Table 6, Table 7, Table 20, Table 23, Table 27, Table 47, Table 60
■
Added Table 24, Table 48
■
Updated Figure 9, Figure 10, Figure 11, Figure 12
■
Updated Table 7, Table 9, Table 20, Table 23, Table 27, Table 30, Table 31, Table 35,
Table 46
■
Updated “Maximum Allowed Overshoot and Undershoot Voltage”
■
Updated Table 3, Table 6, Table 7, Table 8, Table 23, Table 24, Table 25, Table 27,
Table 30, Table 32, Table 35
■
Added Table 33
■
Added “Fast Passive Parallel Configuration Timing”
■
Added “Active Serial Configuration Timing”
■
Added “Passive Serial Configuration Timing”
■
Added “Remote System Upgrades”
■
Added “User Watchdog Internal Circuitry Timing Specification”
■
Added “Initialization”
■
Added “Raw Binary File Size”
■
Added Figure 1, Figure 2, and Figure 3.
■
Updated Table 1, Table 2, Table 3, Table 6, Table 11, Table 22, Table 23, Table 27,Table 29,
Table 30, Table 31, Table 32, Table 35, Table 38, Table 39, Table 40, Table 41, Table 43,
Table 56, and Table 59.
■
Various edits throughout to fix bugs.
■
Changed title of document to Stratix V Device Datasheet.
■
Removed document from the Stratix V handbook and made it a separate document.
■
Updated Table 1–22, Table 1–29, Table 1–31, and Table 1–31.
■
Added Table 2–31.
■
Updated Table 2–28 and Table 2–34.
■
Added Table 2–2 and Table 2–21 and updated Table 2–5 with information about
Stratix V GT devices.
■
Updated Table 2–11, Table 2–13, Table 2–20, and Table 2–25.
■
Various edits throughout to fix SPRs.
■
Updated Table 2–4, Table 2–18, Table 2–19, Table 2–21, Table 2–22, Table 2–23, and
Table 2–24.
■
Updated the “DQ Logic Block and Memory Output Clock Jitter Specifications” title.
■
Chapter moved to Volume 1.
■
Minor text edits.
■
Updated Table 1–2, Table 1–4, Table 1–19, and Table 1–23.
■
Converted chapter to the new template.
■
Minor text edits.
2.4
2.3
December 2011
2.2
November 2011
May 2011
2.1
2.0
December 2010
December 2015
■
2.6
February 2012
July 2010
Changes
1.1
1.0
Altera Corporation
Initial release.
Stratix V Device Datasheet
Page 72
Stratix V Device Datasheet
Document Revision History
December 2015
Altera Corporation
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