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M25P32
32 Mbit, Low Voltage, Serial Flash Memory
With 50MHz SPI Bus Interface
FEATURES SUMMARY
■
32Mbit of Flash Memory
■
■
■
■
■
■
■
■
■
■
Page Program (up to 256 Bytes) in 1.4ms
(typical)
Sector Erase (512Kbit)
Bulk Erase (32Mbit)
2.7 to 3.6V Single Supply Voltage
SPI Bus Compatible Serial Interface
50MHz Clock Rate (maximum)
Deep Power-down Mode 1
µ
A (typical)
Electronic Signatures
– JEDEC Standard Two-Byte Signature
(2016h)
– RES Instruction, One-Byte, Signature
(15h), for backward compatibility
More than 100,000 Erase/Program Cycles per
Sector
More than 20 Year Data Retention
Figure 1. Packages
VDFPN8 (ME)
8x6mm (MLP8)
SO16 (MF)
300 mil width
October 2004 1/39
M25P32
TABLE OF CONTENTS
2/39
M25P32
Figure 12.Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence . . . . . . . 16
Figure 14.Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence . . . . . . . . . . . 19
Figure 15.Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence 20
3/39
M25P32
Figure 28.MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Outline . . . . . . . 35
Table 15. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Mechanical Data35
Figure 29.SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, Package Outline . . . . 36
Table 16. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, Mechanical Data. . . . 36
4/39
SUMMARY DESCRIPTION
The M25P32 is a 32Mbit (4M x 8) Serial Flash
Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The memory is organized as 64 sectors, each containing 256 pages. Each page is 256 bytes wide.
Thus, the whole memory can be viewed as consisting of 16384 pages, or 4,194,304 bytes.
The whole memory can be erased using the Bulk
Erase instruction, or a sector at a time, using the
Sector Erase instruction.
Figure 2. Logic Diagram
VCC
Figure 3. VDFPN Connections
M25P32
S
Q
W
VSS
1
2
3
4
8
7
6
VCC
HOLD
C
5 D
AI08518
M25P32
W
HOLD
D
C
S M25P32
VSS
Table 1. Signal Names
D
Q
S
Serial Data Input
Serial Data Output
Chip Select
HOLD Hold
V
CC
Supply Voltage
V
SS
Ground
Q
AI07483
Note: 1. There is an exposed die paddle on the underside of the
MLP8 package. This is pulled, internally, to V
SS
, and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See
section for package dimensions, and how to identify pin-1.
Figure 4. SO Connections
HOLD
VCC
DU
DU
DU
DU
S
Q
M25P32
6
7
8
3
4
1
2
5
16
15
14
13
12
11
10
9
AI07484B
C
D
DU
DU
DU
DU
VSS
W
Note: 1. DU = Don’t Use
2. See
section for package dimensions, and how to identify pin-1.
5/39
M25P32
SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of
Serial Clock (C).
Serial Clock (C). This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
Chip Select (S). When this input signal is High, the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby Power mode (this is not the Deep Power-down mode).
Driving Chip Select (S) Low enables the device, placing it in the Active Power mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
Hold (HOLD). The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
Write Protect (W). The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2,
BP1 and BP0 bits of the Status Register).
6/39
M25P32
SPI MODES
These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown in
, is the clock polarity when the bus master is in Stand-by mode and not transferring data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
Figure 5. Bus Master and Memory Devices on the SPI Bus
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
Bus Master
(ST6, ST7, ST9,
ST10, Others)
CS3 CS2 CS1
SDO
SDI
SCK
C Q D C Q D C Q D
S
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
W HOLD
S
W HOLD
S
W HOLD
AI03746D
Note: The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 6. SPI Modes Supported
CPOL CPHA
0 0
1 1
C
C
D
Q
MSB
MSB
AI01438B
7/39
M25P32
OPERATING FEATURES
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration t
PP
).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory.
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all
1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk
Erase (BE) instruction. This starts an internal
Erase cycle (of duration t
SE
or t
BE
).
The Erase instruction must be preceded by a Write
Enable (WREN) instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status
Register (WRSR), Program (PP) or Erase (SE or
BE) can be achieved by not waiting for the worst case delay (t
W
, t
PP
, t
SE
, or t
BE
). The Write In
Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous
Write cycle, Program cycle or Erase cycle is complete.
Active Power, Standby Power and Deep
Power-Down Modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active Power mode until all internal cycles have completed (Program,
Erase, Write Status Register). The device then goes in to the Standby Power mode. The device consumption drops to I
CC1
.
The Deep Power-down mode is entered when the specific instruction (the Deep Power-down (DP) instruction) is executed. The device consumption drops further to I
CC2
. The device remains in this mode until another specific instruction (the Release from Deep Power-down and Read Electronic Signature (RES) instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions.
Status Register
The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions.
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
BP2, BP1, BP0 bits. The Block Protect (BP2,
BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against
Program and Erase instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits.
8/39
M25P32
Protection Modes
The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P32 features the following data protection mechanisms:
■
■
Power On Reset and an internal timer (t
PUW can provide protection against inadvertant
) changes while the power supply is outside the operating specification.
Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution.
■
All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state by the following events:
– Power-up
– Write Disable (WRDI) instruction completion
■
■
■
– Write Status Register (WRSR) instruction completion
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as readonly. This is the Software Protected Mode
(SPM).
The Write Protect (W) signal allows the Block
Protect (BP2, BP1, BP0) bits and Status
Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected
Mode (HPM).
In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertant
Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the Release from Deep Powerdown instruction).
Table 2. Protected Area Sizes
Status Register
Content
BP2
Bit
BP1
Bit
BP0
Bit
Protected Area
Memory Content
Unprotected Area
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
Upper 64th (Sector 63)
Upper 32nd (two sectors: 62 and 63)
Upper sixteenth (four sectors: 60 to 63)
Upper eighth (eight sectors: 56 to 63)
Upper quarter (sixteen sectors: 48 to 63)
Upper half (thirty-two sectors: 32 to 63)
All sectors
1
(64 sectors: 0 to 63)
Lower 63/64ths (63 sectors: 0 to 62)
Lower 31/32nds (62 sectors: 0 to 61)
Lower 15/16ths (60 sectors: 0 to 59)
Lower seven-eighths (56 sectors: 0 to 55)
Lower three-quarters (48 sectors: 0 to 47)
Lower half (32 sectors: 0 to 31)
1 1 1 All sectors (64 sectors: 0 to 63) none
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
9/39
M25P32
Hold Condition
The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status
Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the
Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low (as shown in
The Hold condition ends on the rising edge of the
Hold (HOLD) signal, provided that this coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial
Clock (C) being Low, the Hold condition starts after Serial Clock (C) next goes Low. Similarly, if the
Figure 7. Hold Condition Activation
rising edge does not coincide with Serial Clock (C) being Low, the Hold condition ends after Serial
Clock (C) next goes Low. (This is shown in
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D) and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip
Select (S) driven Low, for the whole duration of the
Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive
Hold (HOLD) High, and then to drive Chip Select
(S) Low. This prevents the device from going back to the Hold condition.
C
HOLD
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
AI02029D
10/39
MEMORY ORGANIZATION
The memory is organized as:
■
4,194,304 bytes (8 bits each)
■
■
64 sectors (512Kbits, 65536 bytes each)
16384 pages (256 bytes each).
Figure 8. Block Diagram
M25P32
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable.
HOLD
W
S
C
D
Q
Control Logic
Address Register and Counter
High Voltage
Generator
I/O Shift Register
256 Byte
Data Buffer
3FFFFFh
Status
Register
Size of the read-only memory area
00000h
256 Bytes (Page Size)
X Decoder
000FFh
AI08519
11/39
M25P32
Table 3. Memory Organization
63
62
3F0000h
3E0000h
61
60
3D0000h
3C0000h
59 3B0000h
55
54
53
52
58 3A0000h
57 390000h
56 380000h
370000h
360000h
350000h
340000h
51 330000h
50 320000h
49 310000h
48 300000h
47 2F0000h
46 2E0000h
45
44
2D0000h
2C0000h
43 2B0000h
42 2A0000h
41 290000h
40 280000h
39
38
37
36
270000h
260000h
250000h
240000h
35 230000h
34 220000h
33 210000h
32 200000h
33FFFFh
32FFFFh
31FFFFh
30FFFFh
2FFFFFh
2EFFFFh
2DFFFFh
2CFFFFh
2BFFFFh
2AFFFFh
29FFFFh
28FFFFh
27FFFFh
26FFFFh
25FFFFh
24FFFFh
23FFFFh
22FFFFh
21FFFFh
20FFFFh
3FFFFFh
3EFFFFh
3DFFFFh
3CFFFFh
3BFFFFh
3AFFFFh
39FFFFh
38FFFFh
37FFFFh
36FFFFh
35FFFFh
34FFFFh
31
30
1F0000h
1E0000h
29
28
1D0000h
1C0000h
27 1B0000h
23
22
21
26 1A0000h
25 190000h
24 180000h
170000h
160000h
150000h
20 140000h
19 130000h
18 120000h
17 110000h
16 100000h
15
14
0F0000h
0E0000h
13
12
0D0000h
0C0000h
11 0B0000h
10 0A0000h
9 090000h
8 080000h
7
6
5
070000h
060000h
050000h
4 040000h
3 030000h
2 020000h
1 010000h
0 000000h
14FFFFh
13FFFFh
12FFFFh
11FFFFh
10FFFFh
0FFFFFh
0EFFFFh
0DFFFFh
0CFFFFh
0BFFFFh
0AFFFFh
09FFFFh
08FFFFh
07FFFFh
06FFFFh
05FFFFh
04FFFFh
03FFFFh
02FFFFh
01FFFFh
00FFFFh
1FFFFFh
1EFFFFh
1DFFFFh
1CFFFFh
1BFFFFh
1AFFFFh
19FFFFh
18FFFFh
17FFFFh
16FFFFh
15FFFFh
12/39
M25P32
INSTRUCTIONS
All instructions, addresses and data are shifted in and out of the device, most significant bit first.
Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of Serial Clock (C).
The instruction set is listed in
Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read
Data Bytes at Higher Speed (Fast_Read), Read
Status Register (RDSR), Read Identification
(RDID) or Release from Deep Power-down, and
Read Electronic Signature (RES) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven
High after any bit of the data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase
(SE), Bulk Erase (BE), Write Status Register
(WRSR), Write Enable (WREN), Write Disable
(WRDI) or Deep Power-down (DP) instruction,
Chip Select (S) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of eight.
All attempts to access the memory array during a
Write Status Register cycle, Program cycle or
Erase cycle are ignored, and the internal Write
Status Register cycle, Program cycle or Erase cycle continues unaffected.
Table 4. Instruction Set
Instruction Description
WREN
WRDI
RDID
RDSR
Write Enable
Write Disable
Read Identification
Read Status Register
WRSR
READ
Write Status Register
Read Data Bytes
FAST_READ Read Data Bytes at Higher Speed
PP Page Program
BE
DP
RES
Bulk Erase
Deep Power-down
Release from Deep Power-down, and Read Electronic Signature
Release from Deep Power-down
One-byte Instruction Code
0000 0110
0000 0100
1001 1111
0000 0101
0000 0001
0000 0011
0000 1011
0000 0010
1100 0111
1011 1001
01h
03h
0Bh
02h
D8h
C7h
B9h
06h
04h
9Fh
05h
1010 1011 ABh
Address
Bytes
0
0
0
0
3
3
0
3
Dummy
Bytes
0
0
0
0
1
0
0
0
Data
Bytes
0
0
1 to 3
1 to
∞
1
1 to
∞
1 to
∞
1 to 256
3 0 0
0 0 0
0 0 0
0 3
∞
0 0 0
13/39
M25P32
Write Enable (WREN)
The Write Enable (WREN) instruction (
sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register
(WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S)
High.
Figure 9. Write Enable (WREN) Instruction Sequence
S
0 1 2 3 4 5 6 7
C
Instruction
D
High Impedance
Q
AI02281E
Write Disable (WRDI)
The Write Disable (WRDI) instruction ( Figure 10.
resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
Figure 10. Write Disable (WRDI) Instruction Sequence
– Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction completion
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
S
C
D
Q
0 1 2 3 4 5 6 7
Instruction
High Impedance
AI03750D
14/39
M25P32
Read Identification (RDID)
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. The manufacturer identification is assigned by JEDEC, and has the value 20h for STMicroelectronics. The device identification is assigned by the device manufacturer, and indicates the memory type in the first byte (20h), and the memory capacity of the device in the second byte (16h).
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress.
The device is first selected by driving Chip Select
(S) Low. Then, the 8-bit instruction code for the instruction is shifted in. This is followed by the 24-bit device identification, stored in the memory, being shifted out on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial
Clock (C).
The instruction sequence is shown in
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in the
Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
Table 5. Read Identification (RDID) Data-Out Sequence
Manufacturer Identification
Memory Type
Device Identification
Memory Capacity
20h 20h 16h
Figure 11. Read Identification (RDID) Instruction Sequence and Data-Out Sequence
S
C
D
Q
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 16 18 28 29 30 31
Instruction
High Impedance
Manufacturer Identification
MSB
15 14 13
MSB
Device Identification
3 2 1 0
AI06809
15/39
M25P32
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status
Register may be read at any time, even while a
Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress
(WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in
Table 6. Status Register Format
b7 b0
SRWD 0 0 BP2 BP1 BP0 WEL WIP
Status Register
Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
The status and control bits of the Status Register are as follows:
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or
Erase instruction is accepted.
BP2, BP1, BP0 bits. The Block Protect (BP2,
BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against
Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or more of the Block Protect
(BP2, BP1, BP0) bits is set to 1, the relevant memory area (as defined in
ed against Page Program (PP) and Sector Erase
(SE) instructions. The Block Protect (BP2, BP1,
BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk
Erase (BE) instruction is executed if, and only if, all
Block Protect (BP2, BP1, BP0) bits are 0.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware
Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Write Protect
(W) is driven Low). In this mode, the non-volatile bits of the Status Register (SRWD, BP2, BP1,
BP0) become read-only bits and the Write Status
Register (WRSR) instruction is no longer accepted for execution.
Figure 12. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
S
C
D
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
Q
High Impedance
Status Register Out Status Register Out
7 6 5 4 3 2 1 0
MSB
7
MSB
6 5 4 3 2 1 0 7
AI02031E
16/39
M25P32
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low, followed by the instruction code and the data byte on Serial
Data Input (D).
The instruction sequence is shown in
The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the Status Register. b6 and b5 are always read as 0.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Write Status Register cycle
Figure 13. Write Status Register (WRSR) Instruction Sequence
(whose duration is t
W
) is initiated. While the Write
Status Register cycle is in progress, the Status
Register may still be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Write Status
Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable
Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the Block
Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as de-
(WRSR) instruction also allows the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect (W) signal.
The Status Register Write Disable (SRWD) bit and
Write Protect (W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write
Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered.
S
C
D
Q
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
High Impedance
7 6 5 4 3 2
1
0
MSB
Status
Register In
AI02282D
17/39
M25P32
Table 7. Protection Modes
W
Signal
SRWD
Bit
Mode
Write Protection of the
Status Register
Memory Content
Protected Area
1
Unprotected Area
1
1
0
1
0
0
0
1
1
Software
Protected
(SPM)
Status Register is Writable
(if the WREN instruction has set the WEL bit)
The values in the SRWD,
BP2, BP1 and BP0 bits can be changed
Protected against Page
Program, Sector Erase and Bulk Erase
Hardware
Protected
(HPM)
Status Register is
Hardware write protected
The values in the SRWD,
BP2, BP1 and BP0 bits cannot be changed
Protected against Page
Program, Sector Erase and Bulk Erase
Ready to accept Page
Program and Sector Erase instructions
Ready to accept Page
Program and Sector Erase instructions
Note: 1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
.
The protection features of the device are summa-
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial delivery state), it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless of the whether Write Protect
(W) is driven High or Low.
Status Register are rejected, and are not accepted for execution). As a consequence, all the data bytes in the memory area that are software protected (SPM) by the Block Protect
(BP2, BP1, BP0) bits of the Status Register, are also hardware protected against data modification.
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be entered:
– by setting the Status Register Write Disable
(SRWD) bit after driving Write Protect (W) Low
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two cases need to be considered, depending on the state of
Write Protect (W):
– If Write Protect (W) is driven High, it is possible to write to the Status Register provided that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
– If Write Protect (W) is driven Low, it is not possible to write to the Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the
– or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull Write Protect (W)
High.
If Write Protect (W) is permanently tied High, the
Hardware Protected Mode (HPM) can never be activated, and only the Software Protected Mode
(SPM), using the Block Protect (BP2, BP1, BP0) bits of the Status Register, can be used.
18/39
M25P32
Read Data Bytes (READ)
The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum frequency f
R
, during the falling edge of
Serial Clock (C).
The instruction sequence is shown in
The first byte addressed can be at any location.
The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction.
When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip Select
(S) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 14. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction 24-Bit Address
D
Q
High Impedance
23 22 21
MSB
3 2 1 0
Data Out 1
7 6 5 4 3 2
MSB
1
0
7
Data Out 2
AI03748D
Note: Address bits A23 to A22 are Don’t Care.
19/39
M25P32
Read Data Bytes at Higher Speed
(FAST_READ)
The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that address, is shifted out on Serial
Data Output (Q), each bit being shifted out, at a maximum frequency f
C
, during the falling edge of
Serial Clock (C).
The instruction sequence is shown in
The first byte addressed can be at any location.
The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed
(FAST_READ) instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed
(FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any Read
Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 15. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out
Sequence
S
C
D
Q
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31
Instruction 24 BIT ADDRESS
23 22 21 3 2 1 0
High Impedance
S
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
47
C
D
Q
Dummy Byte
7 6 5 4 3 2 1 0
DATA OUT 1
7 6 5 4 3 2
1
MSB
DATA OUT 2
0 7 6 5 4 3 2 1 0
MSB
7
MSB
AI04006
Note: Address bits A23 to A22 are Don’t Care.
20/39
M25P32
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory (changing bits from
1 to 0). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, three address bytes and at least one data byte on Serial Data Input (D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero).
Chip Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed cor-
Figure 16. Page Program (PP) Instruction Sequence
rectly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page.
Chip Select (S) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the selftimed Page Program cycle (whose duration is t
PP
) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the selftimed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1,
BP0) bits (see
) is not executed.
S
C
D
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
Instruction 24-Bit Address Data Byte 1
23 22 21
MSB
3 2 1 0 7 6 5 4 3 2
1
0
MSB
S
C
D
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data Byte 2 Data Byte 3 Data Byte 256
7 6 5 4 3 2
1
0 7 6 5 4 3 2
1
0
MSB MSB
7 6 5 4 3 2 1 0
MSB
AI04082B
Note: Address bits A23 to A22 are Don’t Care.
21/39
M25P32
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the
Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code, and three address bytes on Serial
Data Input (D). Any address inside the Sector (see
) is a valid address for the Sector Erase
(SE) instruction. Chip Select (S) must be driven
Low for the entire duration of the sequence.
The instruction sequence is shown in
Figure 17. Sector Erase (SE) Instruction Sequence
Chip Select (S) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (S) is driven
High, the self-timed Sector Erase cycle (whose duration is t
SE
) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (BP2, BP1,
BP0) bits (see
) is not executed.
S
C
D
0 1 2 3 4 5 6 7 8 9
Instruction
29 30 31
23 22
MSB
24 Bit Address
2
1
0
AI03751D
Note: Address bits A23 to A22 are Don’t Care.
22/39
M25P32
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1
(FFh). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched
Figure 18. Bulk Erase (BE) Instruction Sequence
in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S) is driven High, the self-timed Bulk Erase cycle (whose duration is t
BE
) is initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the selftimed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The
Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.
S
C
D
0 1 2 3 4 5 6 7
Instruction
AI03752D
23/39
M25P32
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the lowest consumption mode (the Deep Power-down mode). It can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all Write,
Program and Erase instructions.
Driving Chip Select (S) High deselects the device, and puts the device in the Standby Power mode (if there is no internal cycle currently in progress). But this mode is not the Deep Power-down mode. The
Deep Power-down mode can only be entered by executing the Deep Power-down (DP) instruction, subsequently reducing the standby current (from
I
CC1
to I
CC2
).
Once the device has entered the Deep Powerdown mode, all instructions are ignored except the
Release from Deep Power-down and Read Electronic Signature (RES) instruction. This releases the device from this mode. The Release from
Deep Power-down and Read Electronic Signature
(RES) instruction also allows the Electronic Signa-
Figure 19. Deep Power-down (DP) Instruction Sequence
ture of the device to be output on Serial Data Output (Q).
The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in the Standby Power mode.
The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as Chip Select (S) is driven High, it requires a delay of t
DP
before the supply current is reduced to I
CC2
and the Deep
Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an
Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.
S
C
D
0 1 2 3 4 5 6 7
Instruction t
DP
Stand-by Mode Deep Power-down Mode
AI03753D
24/39
M25P32
Release from Deep Power-down and Read
Electronic Signature (RES)
Once the device has entered the Deep Powerdown mode, all instructions are ignored except the
Release from Deep Power-down and Read Electronic Signature (RES) instruction. Executing this instruction takes the device out of the Deep Power-down mode.
The instruction can also be used to read, on Serial
Data Output (Q), the old-style 8-bit Electronic Signature, whose value for the M25P32 is 15h.
Please note that this is not the same as, or even a subset of, the JEDEC 16-bit Electronic Signature that is read by the Read Identifier (RDID) instruction. The old-style Electronic Signature is supported for reasons of backward compatibility, only, and should not be used for new designs. New designs should, instead, make use of the JEDEC 16-bit
Electronic Signature, and the Read Identifier
(RDID) instruction.
Except while an Erase, Program or Write Status
Register cycle is in progress, the Release from
Deep Power-down and Read Electronic Signature
(RES) instruction always provides access to the old-style 8-bit Electronic Signature of the device, and can be applied even if the Deep Power-down mode has not been entered.
Any Release from Deep Power-down and Read
Electronic Signature (RES) instruction while an
Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress.
The device is first selected by driving Chip Select
(S) Low. The instruction code is followed by 3 dummy bytes, each bit being latched-in on Serial
Data Input (D) during the rising edge of Serial
Clock (C). Then, the old-style 8-bit Electronic Signature, stored in the memory, is shifted out on Serial Data Output (Q), each bit being shifted out during the falling edge of Serial Clock (C).
The instruction sequence is shown in
The Release from Deep Power-down and Read
Electronic Signature (RES) instruction is terminated by driving Chip Select (S) High after the Electronic Signature has been read at least once.
Sending additional clock cycles on Serial Clock
(C), while Chip Select (S) is driven Low, cause the
Electronic Signature to be output repeatedly.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Standby Power mode is immediate. If the device was previously in the Deep Power-down mode, though, the transition to the
Standby Power mode is delayed by t
RES2
, and
Chip Select (S) must remain High for at least t
RES2
(max), as specified in Table 14.
Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
Figure 20. Release from Deep Power-down and Read Electronic Signature (RES) Instruction
Sequence and Data-Out Sequence
S
0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38
C
D
Q
Instruction 3 Dummy Bytes
High Impedance
23 22 21
MSB
3 2 1 0
Electronic Signature Out
7 6 5 4 3 2
1
0
MSB
Deep Power-down Mode t
RES2
Stand-by Mode
AI04047C
Note: The value of the 8-bit Electronic Signature, for the M25P32, is 15h.
25/39
M25P32
Figure 21. Release from Deep Power-down (RES) Instruction Sequence
S
0 1 2 3 4 5 6 7 t
RES1
C
Instruction
D
High Impedance
Q
Driving Chip Select (S) High after the 8 bit instruction byte has been received by the device, but before the whole of the 8-bit Electronic Signature has been transmitted for the first time (as shown in
), still ensures that the device is put into
Standby Power mode. If the device was not previously in the Deep Power-down mode, the transition to the Standby Power mode is immediate. If
Deep Power-down Mode Stand-by Mode
AI04078B the device was previously in the Deep Powerdown mode, though, the transition to the Standby
Power mode is delayed by t
RES1
, and Chip Select
(S) must remain High for at least t
RES1
(max), as specified in
. Once in the Standby Power mode, the device waits to be selected, so that it can receive, decode and execute instructions.
26/39
M25P32
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on V
CC
) until V
CC
reaches the correct value:
– V
CC
(min) at Power-up, and then for a further delay of t
VSL
– V
SS
at Power-down
Usually a simple pull-up resistor on Chip Select (S) can be used to ensure safe and proper Power-up and Power-down.
To avoid data corruption and inadvertent write operations during Power-up, a Power On Reset
(POR) circuit is included. The logic inside the device is held reset while V
CC
is less than the Power
On Reset (POR) threshold voltage, V
WI
– all operations are disabled, and the device does not respond to any instruction.
Moreover, the device ignores all Write Enable
(WREN), Page Program (PP), Sector Erase (SE),
Bulk Erase (BE) and Write Status Register
(WRSR) instructions until a time delay of t
PUW
has elapsed after the moment that V
CC
rises above the
V
WI
threshold. However, the correct operation of the device is not guaranteed if, by this time, V
CC
is still below V
CC
(min). No Write Status Register,
Program or Erase instructions should be sent until the later of:
– t
PUW
after V
CC
passed the V
WI
threshold
– t
VSL
after V
CC
passed the V
CC
(min) level
These values are specified in Table 8.
If the delay, t
VSL
, has elapsed, after V
CC
has risen above V
CC
(min), the device can be selected for
READ instructions even if the t
PUW
delay is not yet fully elapsed.
At Power-up, the device is in the following state:
– The device is in the Standby Power mode (not the Deep Power-down mode).
– The Write Enable Latch (WEL) bit is reset.
Normal precautions must be taken for supply rail decoupling, to stabilize the V
CC
supply. Each device in a system should have the V
CC
rail decoupled by a suitable capacitor close to the package pins. (Generally, this capacitor is of the order of
0.1µF).
At Power-down, when V
CC
drops from the operating voltage, to below the Power On Reset (POR) threshold voltage, V
WI
, all operations are disabled and the device does not respond to any instruction. (The designer needs to be aware that if a
Power-down occurs while a Write, Program or
Erase cycle is in progress, some data corruption can result.)
Figure 22. Power-up Timing
VCC
VCC(max)
Program, Erase and Write Commands are Rejected by the Device
Chip Selection Not Allowed
VCC(min) tVSL Read Access allowed
Reset State of the
Device
VWI tPUW
Device fully accessible time
AI04009C
27/39
M25P32
Table 8. Power-Up Timing and V
WI
Threshold
Symbol Parameter
t
VSL
1
V
CC
(min) to S low t
PUW
1 Time delay to Write instruction
V
WI
1
Write Inhibit Voltage
Note: 1. These parameters are characterized only.
Min.
30
1
1.5
Max.
10
2.5
Unit
µs ms
V
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains
FFh). The Status Register contains 00h (all Status
Register bits are 0).
28/39
M25P32
MAXIMUM RATING
Stressing the device outside the ratings listed in
may cause permanent damage to the de-
vice. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the Operating sections of this specification, is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Table 9. Absolute Maximum Ratings
Symbol Parameter Min.
Max.
Unit
T
STG
Storage Temperature –65 150 °C
T
LEAD
Lead Temperature during Soldering
See note
1
°C
V
IO
Input and Output Voltage (with respect to Ground) –0.6
4.0
V
V
CC
Supply Voltage –0.6
4.0
V
V
ESD
Electrostatic Discharge Voltage (Human Body model)
2
–2000 2000 V
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK
®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500
Ω
, R2=500
Ω
)
29/39
M25P32
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measure-
Table 10. Operating Conditions
Symbol Parameter
V
CC
T
A
Supply Voltage
Ambient Operating Temperature
Table 11. AC Measurement Conditions
Symbol Parameter
C
L
Load Capacitance
Input Rise and Fall Times
Input Pulse Voltages
Input Timing Reference Voltages
Output Timing Reference Voltages
Note: Output Hi-Z is defined as the point where data out is no longer driven.
Figure 23. AC Measurement I/O Waveform
ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters.
Min.
2.7
–40
Max.
3.6
85
Min.
Max.
30
5
0.2V
CC
to 0.8V
CC
0.3V
CC
to 0.7V
CC
V
CC
/ 2
Unit
V
°C
Unit
pF ns
V
V
V
Input Levels
0.8VCC
0.2VCC
Input and Output
Timing Reference Levels
0.7VCC
0.5VCC
0.3VCC
AI07455
Table 12. Capacitance
Symbol
C
OUT
Parameter
Output Capacitance (Q)
Test Condition
V
OUT
= 0V
C
IN
Input Capacitance (other pins) V
IN
= 0V
Note: Sampled only, not 100% tested, at T
A
=25°C and a frequency of 20MHz.
Min .
Max .
8
6
Unit
pF pF
30/39
M25P32
Table 13. DC Characteristics
Symbol
I
LI
I
LO
I
CC1
I
CC2
Parameter
Input Leakage Current
Output Leakage Current
Standby Current
Deep Power-down Current
I
CC3
Operating Current (READ)
I
CC4
I
CC5
I
CC6
I
CC7
V
IL
V
IH
V
OL
V
OH
Operating Current (PP)
Operating Current (WRSR)
Operating Current (SE)
Operating Current (BE)
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Test Condition
(in addition to those in
)
S = V
S = V
CC
, V
IN
= V
SS
or V
CC
CC
I
I
, V
OL
OH
IN
= V
S = V
S = V
S = V
CC
SS
or V
CC
C = 0.1V
CC
/ 0.9.V
CC
at 50MHz,
Q = open
C = 0.1V
CC
/ 0.9.V
CC
at 20MHz,
Q = open
S = V
CC
CC
CC
= 1.6mA
= –100
µ
A
Min.
Max.
± 2
± 2
50
10
8
Unit
µA
µA
µA
µA mA
4 mA
15
15
15 mA mA mA
15 mA
– 0.5
0.3V
CC
V
0.7V
CC
V
CC
+0.4
V
V
CC
–0.2
0.4
V
V
Table 14. AC Characteristics
Test conditions specified in Table 10.
Symbol Alt.
Min.
f
C f
C
Parameter
Clock Frequency for the following instructions:
FAST_READ, PP, SE, BE, DP, RES,
WREN, WRDI, RDID, RDSR, WRSR
D.C.
t
SLCH t
CHSL t
DVCH t
CHDX t
CHSH t
SHCH t
SHSL f
R t
CH
1 t
CL
1 t
CLCH
2 t
CHCL
2 t
CLH t
CLL t
CSS t
DSU t
DH t
CSH
Clock Frequency for READ instructions
Clock High Time
Clock Low Time
Clock Rise Time
3
(peak to peak)
Clock Fall Time
3
(peak to peak)
S Active Setup Time (relative to C)
S Not Active Hold Time (relative to C)
Data In Setup Time
Data In Hold Time
S Active Hold Time (relative to C)
S Not Active Setup Time (relative to C)
S Deselect Time
D.C.
9
9
0.1
0.1
5
5
2
5
5
5
100
Typ.
Max.
50
20
Unit
MHz
MHz ns ns
V/ns
V/ns ns ns ns ns ns ns ns
31/39
M25P32
Symbol
t
SHQZ
2 t
CLQV t
CLQX t
HLCH t
CHHH t
HHCH t
CHHL t
HHQX
2 t
HLQZ
2 t
WHSL
4 t
SHWL
4 t
DP
2 t
Alt.
t t t
DIS t
V
HO
LZ
HZ
Test conditions specified in Table 10.
and Table 11.
Output Disable Time
Clock Low to Output Valid
Output Hold Time
Parameter
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
HOLD Setup Time (relative to C)
HOLD Hold Time (relative to C)
HOLD to Output Low-Z
HOLD to Output High-Z
Write Protect Setup Time
Write Protect Hold Time
S High to Deep Power-down Mode t t
RES1
2
RES2
2
S High to Standby Power mode without
Electronic Signature Read
S High to Standby Power mode with Electronic
Signature Read t
W t
PP
Write Status Register Cycle Time
Page Program Cycle Time t
SE
Sector Erase Cycle Time t
BE
Bulk Erase Cycle Time
Note: 1. t
CH
+ t
CL
must be greater than or equal to 1/ f
C
(max)
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
Min.
0
5
5
5
5
20
100
Typ.
5
1.4
1
34
Max.
8
8
8
8
3
30
30
15
5
3
80
µ s ms ms s s
Unit
ns ns ns ns ns ns ns ns ns ns ns
µ s
µ s
32/39
Figure 24. Serial Input Timing
S
C tCHSL
D tDVCH
MSB IN tCHDX
High Impedance
Q tSLCH tCHSH tCLCH
LSB IN tSHSL tSHCH tCHCL
AI01447C
Figure 25. Write Protect Setup and Hold Timing during WRSR when SRWD=1
W tWHSL
S
C tSHWL
M25P32
D
Q
High Impedance
AI07439
33/39
M25P32
Figure 26. Hold Timing
S
C
Q
D
HOLD
Figure 27. Output Timing
S
C tCLQV tCLQX
Q tCLQX
D
ADDR.LSB IN tCLQV tCHHL tHLQZ tHLCH tHHCH tCHHH tHHQX
AI02032 tCH tCL tQLQH tQHQL
LSB OUT tSHQZ
AI01449D
34/39
PACKAGE MECHANICAL
Figure 28. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Outline
M25P32
D
E
A
A1
E2 ddd
L
D2
VDFPN-02
L1 e b
Note: Drawing is not to scale.
Table 15. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Mechanical Data mm inches
Symb.
Typ.
Min.
Max.
Typ.
Min.
Max.
A
A1
0.85
0.00
1.00
0.05
0.0335
0.0000
0.0394
0.0020
K
L
L1
N b
D
D2 ddd
E
E2 e
0.40
8.00
6.40
6.00
4.80
1.27
0.50
0.35
–
0.20
0.45
8
0.48
0.05
–
0.60
0.15
0.0157
0.3150
0.2520
0.2362
0.1890
0.0500
0.0197
0.0138
–
0.0079
0.0177
8
0.0189
0.0020
–
0.0236
0.0059
35/39
M25P32
Figure 29. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, Package Outline
D h x 45˚
16 9
C
E H
1 8
θ
A2 A A1 L ddd
B
SO-H
Note: Drawing is not to scale.
e
Table 16. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, Mechanical Data mm inches
Symb.
Typ.
Min.
Max.
Typ.
Min.
Max.
h
L e
H q ddd
C
D
E
A
A1
B
1.27
–
10.00
0.25
0.40
0
2.35
0.10
0.33
0.23
10.10
7.40
–
10.65
0.75
1.27
8
0.10
2.65
0.30
0.51
0.32
10.50
7.60
0.050
–
0.394
0.010
0.016
0
0.093
0.004
0.013
0.009
0.398
0.291
–
0.419
0.030
0.050
8
0.004
0.104
0.012
0.020
0.013
0.413
0.299
36/39
M25P32
PART NUMBERING
Table 17. Ordering Information Scheme
Example: M25P32
Device Type
M25P = Serial Flash Memory for Code Storage
Device Function
32 = 32Mbit (4M x 8)
Operating Voltage
V = V
CC
= 2.7 to 3.6V
Package
MF = SO16 (300 mil width)
ME = VDFPN8 8x6mm (MLP8)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
P = Lead-Free and RoHS compliant
G = Lead-Free, RoHS compliant, Sb
2
O
3
-free and TBBA-free
For a list of available options (speed, package, etc.) or for further information on any aspect of this
– V MF 6 T P device, please contact your nearest ST Sales Office.
37/39
M25P32
REVISION HISTORY
Table 18. Document Revision History
Date Rev.
Description of Revision
28-Apr-2003 0.1
Target Specification Document written in brief form
15-May-2003 0.2
Target Specification Document written in full
20-Jun-2003 0.3
8x6 MLP8 and SO16(300 mil) packages added
18-Jul-2003 0.4
t
PP
, t
SE
and t
BE
revised
24-Sep-2003 0.5
SO16 package code changed. Output Timing Reference Voltage changed.
04-Dec-2003 0.6
Table of contents, warning about exposed paddle on MLP8, and Pb-free options added.
Value of t
VSL
(min) V
WI
, t
PP
(typ) and t
BE
(typ) changed. Change of naming for VDFPN8 package.
10-Dec-2003 1.0
Document promoted to Product Preview
01-Apr-2004 2.0
Document promoted to Preliminary Data. Soldering temperature information clarified for RoHS compliant devices. Device grade information clarified
05-Aug-2004 3.0
Device grade information further clarified
01-Oct-2004 4.0
Document promoted to mature datasheet. Footnotes removed from P and G options in
Ordering Information table. Minor wording improvements made.
38/39
M25P32
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
39/39
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Table of contents
- 1 FEATURES SUMMARY
- 1 Figure 1. Packages
- 5 SUMMARY DESCRIPTION
- 5 Figure 2. Logic Diagram
- 5 Table 1. Signal Names
- 5 Figure 3. VDFPN Connections
- 5 Figure 4. SO Connections
- 6 SIGNAL DESCRIPTION
- 6 Serial Data Output (Q)
- 6 Serial Data Input (D)
- 6 Serial Clock (C)
- 6 Chip Select (S)
- 6 Hold (HOLD)
- 6 Write Protect (W)
- 7 SPI MODES
- 7 Figure 5. Bus Master and Memory Devices on the SPI Bus
- 7 Figure 6. SPI Modes Supported
- 8 OPERATING FEATURES
- 8 Page Programming
- 8 Sector Erase and Bulk Erase
- 8 Polling During a Write, Program or Erase Cycle
- 8 Active Power, Standby Power and Deep Power-Down Modes
- 8 Status Register
- 8 WIP bit
- 8 WEL bit
- 8 BP2, BP1, BP0 bits
- 8 SRWD bit
- 9 Protection Modes
- 9 Table 2. Protected Area Sizes
- 10 Hold Condition
- 10 Figure 7. Hold Condition Activation
- 11 MEMORY ORGANIZATION
- 11 Figure 8. Block Diagram
- 12 Table 3. Memory Organization
- 13 INSTRUCTIONS
- 13 Table 4. Instruction Set
- 14 Write Enable (WREN)
- 14 Figure 9. Write Enable (WREN) Instruction Sequence
- 14 Write Disable (WRDI)
- 14 Figure 10. Write Disable (WRDI) Instruction Sequence
- 15 Read Identification (RDID)
- 15 Table 5. Read Identification (RDID) Data-Out Sequence
- 15 Figure 11. Read Identification (RDID) Instruction Sequence and Data-Out Sequence
- 16 Read Status Register (RDSR)
- 16 Table 6. Status Register Format
- 16 WIP bit
- 16 WEL bit
- 16 BP2, BP1, BP0 bits
- 16 SRWD bit
- 16 Figure 12. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
- 17 Write Status Register (WRSR)
- 17 Figure 13. Write Status Register (WRSR) Instruction Sequence
- 18 Table 7. Protection Modes
- 19 Read Data Bytes (READ)
- 19 Figure 14. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
- 20 Read Data Bytes at Higher Speed (FAST_READ)
- 20 Figure 15. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence and Data-Out Sequence
- 21 Page Program (PP)
- 21 Figure 16. Page Program (PP) Instruction Sequence
- 22 Sector Erase (SE)
- 22 Figure 17. Sector Erase (SE) Instruction Sequence
- 23 Bulk Erase (BE)
- 23 Figure 18. Bulk Erase (BE) Instruction Sequence
- 24 Deep Power-down (DP)
- 24 Figure 19. Deep Power-down (DP) Instruction Sequence
- 25 Release from Deep Power-down and Read Electronic Signature (RES)
- 25 Figure 20. Release from Deep Power-down and Read Electronic Signature (RES) Instruction Sequence ...
- 26 Figure 21. Release from Deep Power-down (RES) Instruction Sequence
- 27 POWER-UP AND POWER-DOWN
- 27 Figure 22. Power-up Timing
- 28 Table 8. Power-Up Timing and VWI Threshold
- 28 INITIAL DELIVERY STATE
- 29 MAXIMUM RATING
- 29 Table 9. Absolute Maximum Ratings
- 30 DC AND AC PARAMETERS
- 30 Table 10. Operating Conditions
- 30 Table 11. AC Measurement Conditions
- 30 Figure 23. AC Measurement I/O Waveform
- 30 Table 12. Capacitance
- 31 Table 13. DC Characteristics
- 31 Table 14. AC Characteristics
- 33 Figure 24. Serial Input Timing
- 33 Figure 25. Write Protect Setup and Hold Timing during WRSR when SRWD=1
- 34 Figure 26. Hold Timing
- 34 Figure 27. Output Timing
- 35 PACKAGE MECHANICAL
- 35 Figure 28. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Outline
- 35 Table 15. MLP8, 8-lead Very thin Dual Flat Package No lead, 8x6mm, Package Mechanical Data
- 36 Figure 29. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, Package Outline
- 36 Table 16. SO16 wide – 16-lead Plastic Small Outline, 300 mils body width, Mechanical Data
- 37 PART NUMBERING
- 37 Table 17. Ordering Information Scheme
- 38 REVISION HISTORY
- 38 Table 18. Document Revision History