Erase Susp AN

Erase Susp AN
Simultaneous Read/Write versus Erase
Suspend/Resume
Application Note
1. Introduction
By their nature some operations on flash memory take a relatively long time. A typical Write Buffer Program
operation takes 400 µs. A typical Sector Erase operation takes 180 ms to 800 ms, depending on the flash
family. During one of these embedded operations, reads from the flash return status information. Many
systems require access to read data stored in the flash memory before these operations complete. Spansion®
offers two flash features to solve this problem: Simultaneous Read/Write and Suspend/Resume.
Simultaneous Read/Write devices are designed to allow reading from a flash device at the same time an
embedded erase (or program) operation is being executed. The Erase Suspend/Resume and Program
Suspend/Resume features allow the user to interrupt an embedded (erase or program) operation in order to
read data from the flash device. The application designer will need to take several performance factors into
account when deciding which of these methods is correct for the application.
2. Simultaneous Read/Write versus Suspend/Resume Flash Features
Flash devices with the Simultaneous Read/Write feature consist of several independent banks. Each bank
encompasses many sectors. One of these devices with an active erase or program operation will only report
status for reads from the same bank. Data from other banks are available for reading immediately, regardless
of the embedded operation in progress. This design requires a careful division of the flash memory between
banks used for code storage and banks used for data storage. The Suspend/Resume feature usually still
exists in these multi-bank devices. However, it is only useful when reading data from the same bank where an
embedded operation is ongoing.
Single bank devices have a simpler implementation. Because there is only one bank in the whole device,
there is no Simultaneous Read/Write feature available. The Suspend/Resume feature must be used to read
array data out of the flash during an embedded operation. This allows the application to read data that is
anywhere in the device as long as it is not in the sector being erased or programmed. But there is a latency
between issuing the suspend operation and when the flash is ready for reading array data. For example, the
S29GL01GS has Erase Suspend Latency (tESL) defined in the device data sheet as 40 µs, as of this writing.
Please consult the data sheet for the most up-to-date information.
3. Simultaneous Read/Write versus Suspend/Resume Timing
Most systems that use either the Simultaneous Read/Write feature or Suspend/Resume feature do so
because of interrupt-driven events that could require access to the flash device during an erase or program.
When the Suspend/Resume feature is used, the applicable interrupt service routines must be designed to
consider the maximum suspend latency. This latency is not an issue when using a Simultaneous Read/Write
device.
When the Suspend/Resume feature is used to handle an interrupt, the erase or program operation is paused
while reading takes place. This serial sequence can significantly increase the total time of the erase operation
(see Figure 3.1 for details). Erase operations take longer than programs, so they are the main concern for
system latency, and are the focus of our examples here.
Publication Number Erase_Susp_AN
Revision 04
Issue Date July 25, 2011
A pplication
Note
Figure 3.1 Simultaneous Read/Write vs. Erase Suspend/Resume Timing
Erase
Erase
complete
Erase active
Simultaneous Read/Write
Read
resume
resume
resume
resume
Erase
suspend
Erase Suspend for Read
suspend
suspend
suspend
Read
4. Simultaneous Read/Write versus Erase Suspend/Resume Performance
As the number of Erase Suspend/Resume cycles increases, the sector erase operation becomes less
efficient. During an erase, the flash device issues a number of erase pulses to the memory array. The
completion of a given erase pulse is required in order to progress to the next erase pulse. When an erase is
suspended, any erase pulse that was not complete must be restarted (see Figure 4.1). Thus, if Erase
Suspend/Resume commands are issued in rapid succession, the device will restart many of the erase pulses.
This will greatly degrade the performance of the erase function, and possibly extend the total erase time
beyond the specified maximum value. Each device requires a minimum time between the beginning of an
erase (or resume) command and the suspend command. Please consult the device data sheet for the
required delay between resume and suspend. Another solution is to use flash with the Simultaneous Read/
Write feature instead of Suspend/Resume.
Figure 4.1 Incomplete Internal Erase Pulses Get Restarted
terminated pulses
Internal
Pulses
Erase
2
1
3
resume
4
resume
5
resume
6
7 8 9
resume
Operation
suspend
2
suspend
suspend
Simultaneous Read/Write versus Erase Suspend/Resume
suspend
July 25, 2011
Ap pl ic atio n
No t e
5. How Often Can an Erase be Suspended?
Erase operations can be suspended any number of times on MirrorBit® technology flash. However, these
devices still require complete erase pulses for progress on an erase operation.
6. Conclusion
For systems that need to suspend embedded operations occasionally, such as interrupt-driven controllers or
computer systems, the Suspend/Resume feature provides for adequate overall performance. But if a system
is real-time and will frequently need to read from the device, or must have immediate access to flash
contents, a flash device with the Simultaneous Read/Write feature could achieve optimal erase performance
and minimum read latencies.
July 25, 2011
Characteristic
Simultaneous Read/Write
Suspend/Resume with
multi-bank Flash
Suspend/Resume with
single-bank Flash
Location for Flash Array Reads
Any sector in a different bank
Different sector in same bank
Any other sector
Read Latency
None
See data sheet,
typically 20-40 µsec
See data sheet,
typically 20-40 µsec
Performance Impact
None
Embedded operation
completion delayed.
Application impact varies by
application
Embedded operation
completion delayed.
Application impact varies by
application
Chip Complexity
Complex
Complex
Simple
Simultaneous Read/Write versus Erase Suspend/Resume
3
A pplication
Note
7. Revision History
Section
Description
Revision A0 (July 6, 2004)
Initial Release.
Revision A1 (July 7, 2004)
Changed “Read/Write Operation” to “Read/Write Feature”.
Global
Replaced “Flash” with “Flash devices”.
Changed “Erase Suspend/Resume Operation” to “Erase/Suspend Resume feature”.
Deleted paragraph number two (“The required length...”) added first sentence to paragraph number
one “Regardless of the type”.
Simultaneous Read/Write vs. Erase
Suspend/Resume Performance
Paragraph 2 - Deleted “(10ms between the beginning of an erase (or resume) command and the
suspend command, or to use the Simultaneous Read/Write feature for the Erase Suspend/Resume
latency)” and added (10ms erase pulses)”.
Updated last paragraph for language consistency.
Erase Time Multiple vs. Frequency of
Erase Suspends
Updated horizontal axis of drawing for accuracy.
Updated paragraph for language consistency.
How Often Can an Erase be
Suspended?
Changed “MirrorBit Devices” to “Devices based on MirrorBit™ technology”.
Changed “BDD” to Am29BDD”.
Deleted “(assuming the number of suspends is limited to under 5,980)” and added “(assuming this
erase command is limited to under 5,980 suspends)”.
Conclusion
Updated paragraph for language consistency.
Revision 03 (March 7, 2011)
Global
Updated to new format.
Complete rewrite.
Revision 04 (July 25, 2011)
Simultaneous Read/Write versus Erase
Suspend/Resume Performance
4
Updated paragraph.
Simultaneous Read/Write versus Erase Suspend/Resume
July 25, 2011
App l ic atio n
No t e
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
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any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
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The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
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damages of any kind arising out of the use of the information in this document.
Copyright © 2004-2011 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™
and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names
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July 25, 2011
Simultaneous Read/Write versus Erase Suspend/Resume
5
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