ガイド:組込み機器向けインテル®プロセッサー・モジュール (EMBMOD133) POS 熱設計ガイド

ガイド:組込み機器向けインテル®プロセッサー・モジュール (EMBMOD133) POS 熱設計ガイド
Point of Sale Terminal Design
Guide
Application Note
May 1998
Order Number: 273170-001
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not
intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel’s website at http://www.intel.com.
Copyright © Intel Corporation, 1998
*Third-party brands and names are the property of their respective owners.
Application Note
Point of Sale Terminal Design Guide
Contents
1.0
Introduction .................................................................................................................. 5
1.1
1.2
2.0
POS Terminal Design Overview ........................................................................... 6
2.1
2.2
3.0
Design Overview ................................................................................................... 5
POS Terminal Design Features ............................................................................ 5
Core Components ................................................................................................. 7
2.1.1 Intel Embedded Processor Module EMBMOD133 ................................... 7
2.1.2 Intel 82371SB PCI ISA IDE Xcelerator..................................................... 7
2.1.3 Dynamic Random Access Memory (DRAM) ............................................ 7
2.1.4 Flash BIOS ............................................................................................... 7
Peripheral components ......................................................................................... 8
2.2.1 Video Controller........................................................................................ 8
2.2.2 PS/2 Keyboard ......................................................................................... 8
2.2.3 RTC/NVRAM ............................................................................................ 8
2.2.4 Application Flash Memory ........................................................................ 8
2.2.5 Serial and Parallel Ports........................................................................... 9
2.2.6 IDE Port.................................................................................................... 9
2.2.7 PCMCIA Interface .................................................................................... 9
2.2.8 PS/2 Mouse Port ...................................................................................... 9
POS Terminal Design Details ..............................................................................10
3.1
3.2
3.3
3.4
3.5
3.6
3.7
Intel Embedded Processor Module (EMBMOD133)............................................10
Intel 82371SB PCI ISA IDE Xcelerator................................................................10
PCMCIA Connector.............................................................................................10
3.3.1 PCMCIA Host Adapter ...........................................................................10
3.3.2 PCMCIA Voltage Control........................................................................11
Serial and Parallel Communications ...................................................................11
Application Flash .................................................................................................12
Video Controller...................................................................................................12
Power ..................................................................................................................12
4.0
Design Considerations ..........................................................................................13
5.0
Summary......................................................................................................................13
6.0
Related Documents .................................................................................................13
7.0
Contact Information ................................................................................................14
A
Bill of Materials .........................................................................................................15
B
BIOS Checklist ..........................................................................................................19
C
Schematics .................................................................................................................21
C.1
Application Note
POS Terminal Reference Design Schematics ....................................................21
iii
Point of Sale Terminal Design Guide
Figures
1
POS Terminal Design Block Diagram ................................................................... 6
1
2
3
4
5
6
7
8
9
Intel Documents .................................................................................................. 13
Third Party Vendor Documents ........................................................................... 14
POS Design Guide Bill of Materials .................................................................... 15
Hardware Design Specification ........................................................................... 19
Items connected to Super I/O ............................................................................. 19
Onboard Peripherals ........................................................................................... 20
PCI Routing Information ...................................................................................... 20
Connectors.......................................................................................................... 20
Software Design Specification – Feature List ..................................................... 20
Tables
iv
Application Note
Point of Sale Terminal Design Guide
1.0
Introduction
The point of sale (POS) terminal is an embedded PC platform with custom features designed for a
retail and service environment. The major difference between a POS terminal and a normal PC is
that a POS terminal is a cost-effective custom design, with unneeded PC features removed.
More and more industries are switching to POS terminals to replace cash registers, causing the
market for POS terminal systems to grow enormously. Because POS terminal systems are usually
connected to a network and often require a graphical user interface, high performance POS
terminal systems are in demand.
The design described in this document was created to reduce the development cycle for point of
sale terminal designers. This design provides a head-start in product development which can result
in faster time to market.
Caution:
1.1
The design has not been implemented in hardware. This document is for reference only. Customers
are responsible for validating designs created using the information in this document.
Design Overview
This design is based on the Intel Embedded Processor Module. The processor used in the
Embedded Processor Module is either a 133 MHz Intel® Pentium® processor with VRT
technology (for the EMBMOD133) or a 166 MHz Intel ® Pentium® processor with MMX™
technology (for the EMBMOD166). The EMBMOD133 module is used in this design.
The design closely emulates a PC environment and uses common, standard components. Four
serial ports support peripherals, such as barcode scanners, digital scales, card readers and customer
price displays. A printer and cash drawer can be connected using the parallel port and a keyboard
can be connected using the PS/2 connector provided in the design.
Designers should check for device availability before designing-in any of the components included
in the document. This document describes the operation of the POS terminal design from a
hardware perspective. BIOS and operating system operation is not discussed. The design has not
been implemented in hardware.
This design guide is meant to be used together with the Intel 430HX PCIset Design Guide (order
number 297467) and AP-757, Intel Embedded Processor Module Design Guide (order number
273120). Design issues covered in those documents are not repeated here. See “Related
Documents” on page 13 for more information on how to obtain documents referenced in this
document. The schematics for this design are provided in Appendix B, “Schematics.” They are
also available in OrCAD format from the Intel Developer’s web site at www.intel.com.
1.2
POS Terminal Design Features
Key features of the POS terminal described in this design include:
•
•
•
•
Application Note
Intel Embedded Processor Module (EMBMOD133)
4-Mbyte application flash memory
64-bit video graphics controller with 2 Mbytes of DRAM
Four serial ports
5
Point of Sale Terminal Design Guide
• One parallel port
• PCMCIA socket
The Intel Embedded Processor Module contains:
•
•
•
•
•
2.0
133 MHz Intel Pentium processor with VRT technology
82439HX System Controller
256 Kbytes of L2 cache
Clock generator
Voltage regulator
POS Terminal Design Overview
Figure 1 is the block diagram for the POS terminal design.
Figure 1. POS Terminal Design Block Diagram
66 MHz
Clock Generator
66, 33 MHz
ITP
Cache
Tag
72-Bit DIMM
Voltage
Regulator
Data Bus
Control
Address Bus
82439HX
System Controller
Intel Embedded
Processor Module
72-Bit DIMM
Pentium®
Processor
Control
DRAM Bus
PCI
Connector
PCI
Bus
Video Subsystem
USB
PIIX3
Bus Master IDE
Boot
Flash
XD Bus
COM3/COM4
Application
Flash
ISA Bus
ISA
Connector
PS/2 Mouse
PS/2 Keyboard
PCMCIA
National 87307
Super I/O*
Floppy Drive
IEEE 1284 Parallel Port
6
COM1
COM2
Application Note
Point of Sale Terminal Design Guide
2.1
Core Components
The core components of this POS terminal design are:
•
•
•
•
2.1.1
Intel Embedded Processor Module, EMBMOD133
Intel 82371SB PCI ISA IDE Xcelerator
DRAM
BIOS ROM
Intel Embedded Processor Module EMBMOD133
The Intel Embedded Processor Module EMBMOD133 is a high performance subsystem for use in
embedded, industrial and communication applications where flexibility and the ability to upgrade
is important.
The Intel Embedded Processor Module contains a Pentium processor, an 82439HX system
controller (TXC), a 256 Kbyte L2 cache, a clock generator and a voltage regulator for the Pentium
processor, all incorporated in a single board.
2.1.2
Intel 82371SB PCI ISA IDE Xcelerator
The Intel 82371SB is the PCI south bridge. It connects to the Embedded Processor Module via the
PCI bus. It integrates many common I/O functions found in ISA-based PC systems:
•
•
•
•
2.1.3
Seven-channel DMA controller
Two 82C59 interrupt controllers
8254 timer/counter
Power management support
Dynamic Random Access Memory (DRAM)
The POS terminal in this design provides two connectors for two 168-pin JEDEC, DRAM DIMM
modules. The DRAM DIMMs will either be 3.3 V FPM or 3.3 V EDO type memory. The DIMM
will provide a 64-bit or 72-bit interface directly to the Embedded Processor Module.
2.1.4
Flash BIOS
Flash BIOS is used to boot the POS terminal during power-up. The system flash BIOS is a
128 Kbyte, 12 V programmable flash device. The system is set up for in-circuit reprogramming of
the BIOS, and the flash device is socketed and writable. This device is addressable on the XD bus
extension of the ISA bus. The ROM is controlled by the Intel 82371SB PCI to ISA bridge chip.
Application Note
7
Point of Sale Terminal Design Guide
2.2
Peripheral components
The peripheral components in this POS terminal design include:
•
•
•
•
•
•
•
•
•
•
•
Video controller
PS/2 keyboard
RTC/NVRAM
Application flash memory
Four serial ports
One parallel port
PCI connector
ISA connector
IDE port
PCMCIA socket
PS/2 mouse port
This design is modular. Peripherals can be easily removed if they are not required in the final
design.
2.2.1
Video Controller
The Cirrus Logic CL-GD7555* Video and Graphics Controller is capable of controlling a CRT,
TFT, DSTN or TV display. It connects directly to the 32-bit PCI (v2.1) host bus with a 33 MHz
clock rate.
2.2.2
PS/2 Keyboard
Keyboard support is provided by the National Semiconductor 87307 Super I/O* device. The
keyboard connectors are PS/2 type.
2.2.3
RTC/NVRAM
The RTC and NVRAM is contained within the National Semiconductor 87307 Super I/O device.
CMOS backup is provided by a 3 V battery.
2.2.4
Application Flash Memory
There are 4 Mbytes of application flash memory on the POS terminal motherboard. This flash
memory serves as non-volatile memory. The operating system and POS software can be stored in
this flash device. To use the application flash as a disk, appropriate software must be installed. To
boot from a flash device, changes may be needed in the BIOS or the flash driver software.
8
Application Note
Point of Sale Terminal Design Guide
The design’s application flash memory consists of one Intel 28F320S5 from the Word-Wide
FlashFile™ Memory Family. This 16-bit, word-wide FlashFile memory provides high-density,
low-cost, nonvolatile, read/write storage solutions for a wide range of applications. Key
enhancements include:
•
•
•
•
2.2.5
Common Flash Interface (CFI) support
Scalable Command Set (SCS) support
S5 technology
Enhanced suspend capabilities
Serial and Parallel Ports
There are four serial ports in the POS terminal design. COM1 and COM2 are generated and
supported by the National Semiconductor 87307 Super I/O device. COM3 and COM4 are
generated and controlled by the Exar ST16C452* Dual Asynchronous Receiver/Transmitter.
GD 75232* drivers/receivers from Texas Instruments provide the interface between the UART and
the communication ports. This device provides a low-cost solution for this function and allows
easy interconnection of the UART and communication ports. It also complies with the
requirements of the EIA/TIA-232-E and ITU standards.
The parallel port on the POS terminal design is generated and controlled by the National
Semiconductor 87307 Super I/O device. The parallel port uses a DB25 connector.
2.2.6
IDE Port
Two standard IDE interfaces are provided by the 82371SB. One 40-pin IDE connector is included
in the design. This allows up to two IDE devices (one master and one slave) to be supported in a
single connector.
2.2.7
PCMCIA Interface
The Cirrus Logic CL-PD6720* is used as the host adapter chip to control two PCMCIA sockets.
Only one socket is implemented in this design. The chip is fully PCMCIA (v2.1) and JEIDA (v4.1)
compliant. The CL-PD6720 provides fully buffered PCMCIA interfaces. No external logic is
required for buffering signals to or from the interface. Power consumption can be controlled by
limiting signal transitions on the PCMCIA bus.
2.2.8
PS/2 Mouse Port
A PS/2-type mouse port is provided by the National Semiconductor 87307 Super I/O device.
Application Note
9
Point of Sale Terminal Design Guide
3.0
POS Terminal Design Details
For more information about the POS terminal design, please refer to the schematics located in
Appendix B, “Schematics.”
3.1
Intel Embedded Processor Module (EMBMOD133)
The Embedded Processor Module has two connectors and a heat sink for the Pentium processor.
The two connectors carry power, clocks, the DRAM memory interface and the 33 MHz PCI
interface. 3 V and 5 V power is provided to the Embedded Processor Module. The module
generates the core voltage. This core voltage is provided to the POS terminal baseboard for the
power-on sequencing circuitry.
For more information, please refer to the Intel Embedded Processor Module datasheet (order
number 273105) and AP-757, Embedded Processor Module Design Guide (order number 273120).
3.2
Intel 82371SB PCI ISA IDE Xcelerator
The Intel 82371SB requests control of the PCI bus by asserting the PHOLD# signal, and becomes
the PCI master upon receipt of the PHOLDA# signal from the Embedded Processor Module. The
Intel 82371SB contains the PCI and ISA interrupt controller, along with various ISA legacy
functions such as a DMA controller, a bus master IDE Interface, an ISA bus interface, an ISA bus
clock control, an XD bus control, a USB interface and a BIOS ROM interface.
For more information on the Intel 82371SB PCI ISA IDE Xcelerator, please refer to the Intel
82371FB (PIIX) and 82371SB (PIIX3) PCI-TO-ISA/IDE Xcelerator datasheet (order number
290550) and the Intel 82371SB PCI-TO-ISA/IDE Xcelerator (PIIX3) Timing Specification (order
number 272963).
3.3
PCMCIA Connector
The PCMCIA connector has three main components:
• PCMCIA host adapter (CL-PD6710)
• PCMCIA connector
• Analog power controller circuit
3.3.1
PCMCIA Host Adapter
The Cirrus Logic PCMCIA host adapter (CL-PD6720) is a single chip capable of controlling two
PCMCIA sockets. One PCMCIA socket is implemented in the design. The CL-PD6720 is fully
compliant with the PCMCIA (v2.1) and JEIDA (v4.1) specifications and is optimized for use in
palmtops and laptops, in which the main design objectives are reduced form-factor and low-power
consumption. This chip also provides fully buffered PCMCIA interfaces. No external logic is
required for buffering signals to or from the interface, and power consumption can be controlled by
limiting signal transitions on the PCMCIA bus.
10
Application Note
Point of Sale Terminal Design Guide
The chip also supports fully mixed voltage operation, a key feature for low power system design
and low-power card operation. The core, ISA interface, and the PCMCIA socket interface can all
operate independent of each other at either 3.3 V or 5 V.
The design can support either 3.3 V or 5 V operation and can be switched back and forth between
3.3 V and 5 V operation. Automatic voltage sensing has not been implemented in this design; the
correct voltage must be set by the driver.
3.3.2
PCMCIA Voltage Control
The Linear Technology (LTC 1472*) switching matrix routes power to both the +5V (VCC) and
+12V (VPP) power supply pins on the individual PC Card sockets. The VCC output of the LTC
1472 is switched between three operating states: OFF, 3.3 V and 5 V. The VPP output is switched
between four operating states: 0 V, VCC, 12 V and Hi-Z. The VCC output of the LTC 1472 can
supply up to 1 A of current and the VPP output up to 120 mA. Both switches have built-in current
limiting and thermal shutdown to protect the card, socket, and power supply against accidental
short-circuit conditions.
3.4
Serial and Parallel Communications
COM1 and COM2 are generated and supported by the National Semiconductor 87307 Super I/O
device. COM3 and COM4 are generated and controlled by the Exar ST16C452 Dual
Asynchronous Receiver/Transmitter with Parallel Printer Port device.
COM3 occupies 03E8 - 03EF and COM4 occupies 02E8 - 02EF in the address range. An additional
logic decoding circuit decodes COM3 and COM4 on ST15C452. This is performed by the CSA#
and CSB# signals on the UART.
The Exar ST16C452 chip is a dual universal asynchronous receiver and transmitter (UART) with a
bidirectional Centronics* compatible parallel printer port. A programmable baud rate generator is
provided to select transmit and receive clock rates from 50 Hz to 1.5 MHz.
The ST16C452 on-board status registers indicate the error conditions, type and status of the
transfer operation being performed. Additional features include:
• Complete MODEM control capability
• A processor interrupt system that may be software tailored to the user’s requirements
• Internal loop-back capability for on-board diagnostic testing
Connection to the LPT1 parallel port is made using a 25-pin female D-sub connector. This is a
multi-mode IBM PC/XT*, PC/AT* and PS/2-compatible bidirectional parallel port. Since the
ST16C452 does not supply another parallel port in this design, INTP and INTSEL can be “no
connect.”
The GD75232 driver/receiver from Texas Instruments is used as an interface between the UART
and the communication ports. The GD75232 combines three drivers and five receivers in a single
chip, which decreases the device count and reduces the board space required. One GD75232
supports one communication port, which makes the design modular.
Clamped diodes are added for port protection. This is an optional item but it ensures that excessive
voltage does not cause damage to the GD75232.
Application Note
11
Point of Sale Terminal Design Guide
3.5
Application Flash
The Intel 28F320S5 flash device from the Word-Wide FlashFile™ memory family operates with
5 V on both VCC and VPP.
The BYTE# pin allows either x8 or x16 read/program to the 28F320S5 flash device. When low,
BYTE# selects 8-bit mode, and address A0 selects between the low byte and the high byte. When
high, BYTE# enables 16-bit operation, address A1 becomes the lowest order address, and address
A0 is not used (don’t care).
The 28F320S5 also incorporates a dual chip-enable function with two input pins, CE0# and CE1#.
These pins have exactly the same function as the regular chip enable pin, CE#. Both CE0# and
CE1# must be active low to enable the device. If either signal becomes inactive, the chip is
disabled. Device selection occurs with the falling edge of CE0# or CE1#. The first rising edge of
CE0# of CE1# disables the device. For minimum chip designs, CE1# may be tied to ground and
system logic may use CE0# as the chip enable input.
Memory holes must be used to address the flash. It can either be at 512 Kbyte – 640 Kbyte
(080000H-0A0000H) or between 15 Mbyte and 16 Mbyte (F00000H-FFFFFFH). In this design, a
512-Kbyte window below 16 Mbyte (F80000H-FFFFFFH) is used. General purpose I/O from the
National Semiconductor 87307 Super I/O are used to select one of eight pages in the 28F320S5
memory device.
If the application flash is required to act as a disk, suitable drivers should be used.
3.6
Video Controller
The CL-GD7555 Video and Graphics Controller can control a CRT, TFT, DSTN, or TV display.
The controller supports mixed voltage operation. Active power management provides power-down
control of selected unused internal functional blocks during display. The CL-GD7555 also
connects directly to the 32-bit PCI (v2.1) host bus with a 33 MHz clock rate.
The CL-GD7555’s V-port allows cost-effective implementation of many multimedia features such
as MPEG video playback, TV tuning, video capture and teleconferencing. The chip also supports
TFT flat panel displays (up to 1024 x 768 resolution) and color dual-scan STN flat panel displays
(up to 800 x 600 resolution).
In this design, the CL-GD7555 is implemented with a 2-Mbyte frame buffer using four 256K x 16
DRAMs. The TFT/DSTN display is not implemented in this design. The CRT controller generates
horizontal and vertical signals (HSYNC and VSYNC) for a CRT monitor. It supports up to 1280 x
1024 resolution with 256 colors.
The IDSEL signal is routed to AD13. The INTR signal is connected to PIRQ1.
3.7
Power
Power is supplied to the board through an ATX power connector. ATX power supplies provide
5 V, 3.3 V, +12 V, -5 V and -12 V outputs. All these values are used in the design. When using this
power supply there is no need for additional voltage regulators.
12
Application Note
Point of Sale Terminal Design Guide
4.0
Design Considerations
There should be decoupling capacitors for every schematic page and one bulk capacitor for the
entire design. This provides a short between power and ground for high frequency signals and to
reduce inductance.
If a part is to be removed from the design, the outputs can be left unconnected but the inputs should
be pulled either high or low. Since the TFT/DSTN display is not implemented for this design,
connect the video controller power pins to VCC.
5.0
Summary
This design was created to shorten the development cycle for POS terminal designs. It is intended
to be implemented on a single board for reduced cost. Peripherals are designed in a modular
fashion and can be easily removed for specific applications.
Caution:
6.0
The design has not been implemented in hardware. This document is for reference only. Customers
are responsible for validating designs created using the information included in this document.
Related Documents
Copies of Intel documents that have an order number referenced in this document (see Table 1)
may be downloaded from the Intel web site at http://www.intel.com. To order printed copies, call
1-800-548-4725.
Table 2 lists documents available from other vendors.
Table 1. Intel Documents
Document Name
Order Number
Intel Embedded Processor Module datasheet
273105
Intel Embedded Processor Module Design Guide
273120
Intel Embedded Processor Module (EMBMOD133) Thermal Design Guide
273143
Pentium® Processor datasheet
241997
Pentium®
241428
Processor Family Developer’s Manual
Intel Architecture Software Developer’s Manual (Vols. 1, 2 and 3)
243190, 243191 and
243192
Intel 430HX PCIset 82439HX System Controller (TXC) datasheet
290551
Intel 430HX PCIset 82439HX System Controller (TXC) Timing Specification
272945
Intel 430HX PCIset Design Guide
297467
82371FB (PIIX) and 82371SB (PIIX3) PCI-TO-ISA/IDE Xcelerator datasheet
290550
82371SB PCI-TO-ISA/IDE Xcelerator (PIIX3) Timing Specification
272963
The Advantages of Using the 82371SB PCI-TO-ISA/IDE Xcelerator (PIIX3) with
the Intel 430HX PCIset in Embedded Designs
273009
Intel Word-Wide FlashFile™ Memory 28F320S5 datasheet
290609
Application Note
13
Point of Sale Terminal Design Guide
Table 2.
Third Party Vendor Documents
Document Name
National Semiconductor PC87307VUL Super I/O datasheet
Cirrus Logic CL-GD7555 Advance Hardware Reference Manual
Cirrus Logic CL-PD 6720 datasheet
Exar ST16C452 Dual UART with Parallel Printer Port datasheet
Specifications Lattice ispGAL22V10 In-System Programmable E2CMOS PLD Generic Array Logic datasheet
Linear Technology LTC 1472 Protected PCMCIA Vcc and Vpp Switching Matrix datasheet
Texas Instruments GD75232 Multiple RS-232 Drivers and Receivers datasheet
7.0
14
Contact Information
Intel Corporation
2200 Mission College Blvd.
Santa Clara, CA 95052-8119
Web site: http://www.intel.com
EXAR Corporation
48720 Kato Road
Fremont, CA 94538
Web site: http://www.exar.com
National Semiconductor Corporation
2900 Semiconductor Drive
P.O. Box 58090
Santa Clara, CA 95052-9959
Web site: http://www.national.com
Siemens Microelectronics, Inc.
10950 North Tantau Avenue
Cupertino, CA 95014
Web site: http://www.siemens.com
Cirrus Logic
31000 West Warren Avenue
Fremont, CA 94538
Web site: http://www.cirrus.com
Texas Instruments Incorporated
P.O. Box 809066
Dallas, TX 75244-9066
Web site: http://www.ti.com
Application Note
Point of Sale Terminal Design Guide
Appendix A Bill of Materials
Note:
Intel does not guarantee device availability. Designers should check for device availability before
designing-in any of the components included in the document.
Table 3. POS Design Guide Bill of Materials (Sheet 1 of 4)
POS Design Guide: Embedded Processor Module Connectors Revised: Wednesday, March 11, 1998
Revision: 1.00
The estimated bill of material cost for this design is US$400, as of 3/20/98.
Bill Of Materials
Item
Application Note
Quantity
March 20,1998
8:19:09
Page1
Reference
Part
1
1
BT1
HU 2032-1 SOCKET
2
10
C1, C2, C3, C36, C38, C39, C44, C45, C46, C47
0.001uF
3
37
C4, C24, C32, C33, C34, C35, C37, C48, C65, C73, C74,
C85, C86, C112, C113, C124, C125, C149, C150, C151,
C213, C214, C215, C216, C230, C231, C232, C233,
C237, C242, C267, C268, C288, C289, C290, C291, C292
0.01uF
4
124
C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16,
C17, C18, C21, C22, C23, C25, C26, C27, C28, C29, C30,
C31, C49, C50, C51, C52, C53, C54, C55, C56, C57, C58,
C59, C60, C61, C64, C66, C67, C68, C70, C71, C72, C76,
C77, C79, C80, C82, C83, C84, C88, C89, C91, C92, C93,
C94, C95, C96, C100, C101, C103, C104, C106, C107,
C109, C110, C111, C115, C116, C118, C119, C121,
C122, C123, C128, C143, C144, C145, C146, C147,
C148, C161, C162, C163, C164, C165, C166, C167,
C168, C169, C207, C208, C209, C210, C211, C212,
C225, C226, C227, C228, C229, C235, C236, C240,
C241, C244, C247, C253, C260, C261, C262, C266,
C269, C270, C272, C274, C277, C280, C282, C283,
C285, C293, C294
0.1uF
5
12
C19, C20, C245, C246, C248, C249, C254, C255, C275,
C276, C278, C279
100uF
6
27
C40, C41, C42, C43, C69, C75, C78, C81, C87, C90, C99,
C102, C105, C108, C114, C117, C120, C141, C142,
C202, C203, C221, C222, C256, C263, C264, C271
10uF
7
17
RP1, R1, RP2, R2, RP3, RP4, R6, R8, R16, R23, R30,
R31, C62, C63, C97, C126, C127
0
8
1
C98
100pF
9
14
C129, C130, C131, C132, C133, C134, C135, C136,
C137, C138, C139, C140, C158, C159
10pF
10
25
C152, C153, C154, C155, C156, C157, C172, C173,
C174, C175, C177, C178, C179, C180, C184, C185,
C186, C187, C188, C189, C190, C191, C250, C251, C252
470pF
11
2
C160, C259
22uF
12
16
C170, C171, C176, C181, C182, C183, C192, C193,
C194, C195, C196, C197, C198, C199, C200, C201
220pF
13
12
C204, C205, C206, C217, C223, C224, C234, C239,
C258, C265, C284, C287
1uF
14
6
C218, C219, C220, C238, C281, C296
CAP
15
1
C243
.1uF
15
Point of Sale Terminal Design Guide
Table 3.
16
POS Design Guide Bill of Materials (Sheet 2 of 4)
16
1
C257
4.7nF
17
1
C273
1000pF
18
1
C286
220uF
19
1
C295
0.0022uF
20
4
D1, D53, D54, D55
LGS260-DO
21
1
D2
FMMD914
22
40
D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14,
D15, D16, D17, D18, D19, D20, D21, D22, D33, D34, D35,
D36, D37, D38, D39, D40, D41, D42, D43, D44, D45, D46,
D47, D48, D49, D50, D51, D52
D1N916A
23
10
D23, D24, D25, D26, D27, D28, D29, D30, D31, D32
D1N916
24
1
D56
BZX84C2V7
25
1
D57
BZX84C2V4
26
1
D58
1N5817
27
6
FB1, FB2, FB3, FB4, FB5, FB6
BLM41A800S
28
2
FB8, FB7
CB70
29
2
F1, F2
SMD125-002
30
1
JP1
FLOPPY HEADER 17X2
31
1
JP2
1x4
32
1
J1
EPM DRAM Conn 140-Pin
33
1
J2
EPM PCI Conn 120-Pin
34
1
J3
Embedded Processor
Module DRAM Conn 140-Pin
35
1
J4
Embedded Processor
Module PCI Conn 120-Pin
36
2
J6, J5
Molex 71736-00011
IDE Conn
37
1
J7
38
2
J9, J8
PCI Conn
39
1
J10
ISA Conn A
40
1
J11
ISA Conn B
41
1
J12
PS2 STACK
42
4
J13, J14, J17, J23
1x2
43
3
J15, J24, J25
1x3
44
1
J16
1x1
45
1
J18
SERIAL STACK
46
1
J19
DB25
47
1
J20
CONNECTOR DB15HD
48
1
J21
JUMP3
49
1
J22
ATX POW CONN
50
1
J26
PCMCIA Connector
51
2
L1, L2
INDUCTOR
52
2
P2, P1
DB9
53
2
Q1, Q2
NDS9953A
54
8
R4, RP5, RP6, R7, RP45, RP49, R53, R59
22
Application Note
Point of Sale Terminal Design Guide
Table 3. POS Design Guide Bill of Materials (Sheet 3 of 4)
Application Note
55
25
R5, RP7, R14, RP17, RP18, RP20, RP21, RP25, RP30,
RP32, RP34, RP36, RP38, RP39, RP40, RP41, R46, R47,
R48, R49, R50, R51, R55, R77, R78
10K
56
14
RP8, RP9, RP10, RP11, RP12, RP13, R13, RP14, RP15,
RP16, RP46, RP47, R68, R69
33
57
20
R10, R11, RP19, RP28, R33, R34, R36, R38, R39, R41,
RP42, R42, RP43, R43, RP44, R44, R45, R58, R70, R76
4.7K
58
4
RP22, RP26, R37, R40
330
59
11
RP23, RP24, R25, R26, RP27, R27, R28, RP29, RP31,
RP33, R35
2.7K
60
2
RP35, RP37
5.6K
61
8
R3, R18, R19, R29, R32, RP48, R60, R79
1K
62
5
R9, R21, R22, R67, R72
220
63
3
R12, R15, R17
47
64
2
R20, R73
215
65
1
R24
10
66
1
R52
22M
67
1
R54
120K
68
1
R56
8.2K
69
1
R57
20K
70
3
R61, R62, R63
150
71
1
R64
180
72
2
R66, R65
R
73
1
R71
51K
74
1
R74
130
75
1
R75
110
76
1
S1
RESET SWITCH
77
2
TP2, TP1
12MHZ
78
1
TP3
MWE#
79
1
TP4
MRAS2#
80
1
TP5
MRAS0#
81
1
TP6
MCAS0#
82
1
TP7
MCAS1#
83
1
TP8
MCAS2#
84
1
TP9
MCAS3#
85
1
TP10
MCAS4#
86
1
TP11
MCAS5#
87
1
TP12
MCAS6#
88
1
TP13
MCAS7#
89
1
TP14
14MHZ
90
1
TP15
PCLK_PIIX3
91
1
TP16
24MHZ
BIOSCS#
92
1
TP17
93
1
TP18
PDIAG#
94
1
TP19
SYSCLK
17
Point of Sale Terminal Design Guide
Table 3.
18
POS Design Guide Bill of Materials (Sheet 4 of 4)
95
1
TP20
14MHZ_ISA
96
1
TP21
P12
97
1
TP22
P16
98
1
TP23
P17
99
1
TP24
P20
100
1
TP25
P21
101
1
TP26
X1
102
1
TP27
G10
103
1
TP28
G11
104
1
TP29
G12
105
1
TP30
G13
106
1
TP31
G14
107
1
TP32
G15
108
1
TP33
G16
109
1
TP34
G17
110
1
TP35
G20
111
1
TP36
G21
112
1
TP37
G22
113
1
U1
82371SB (PIIX3)
114
1
U2
74ACT04
115
3
U3, U5, U6
74ALS245
116
1
U4
74HCT14
117
1
U7
74ALS08
118
1
U8
74ALS00
119
1
U9
74ACT05
120
1
U10
PC87307IBU-VUL
121
1
U11
28F001BX-T150
122
4
U12, U13, U27, U29
GD75232SOP
123
1
U14
CL-GD7555
124
4
U15, U16, U17, U18
HYB514171BJ-60
125
1
U19
27C512
126
1
U20
74LS30
127
1
U21
74LS04
128
1
U22
ispGAL22V10
129
1
U23
28F320S5
130
1
U24
74LS08
131
1
U25
74LS260
132
1
U28
ST16C452
133
1
U30
TLC393C
134
1
U31
7404
135
1
U32
CL-PD6720
136
1
U33
LTC1472
137
1
Y1
32.768KHZ
Application Note
Point of Sale Terminal Design Guide
Appendix B BIOS Checklist
This section is a checklist to specify the hardware configuration for a BIOS vendor to customize
the BIOS.
Table 4. Hardware Design Specification
Intel 430HX chipset
Manufacturer
Intel Corporation
Bus
Host
Embedded Processor Module
Manufacturer
Intel Corporation
Speed
133 MHz
Memory - System
Configuration
EDO, FPM
Speeds Supported
60, 70
Memory - Cache (External)
Configuration
256 Kbyte
ROM
Manufacturer
Intel Corporation
Part #
28F001BX-T150
Size
128 Kbyte
Super I/O
Manufacture / Part #
National Semiconductor 87307
Table 5. Items connected to Super I/O
IDE
Floppy
Serial
Parallel
Keyboard Controller
Real Time Clock
Application Note
19
Point of Sale Terminal Design Guide
Table 6.
Onboard Peripherals
Onboard
Peripherals
Manufacturer
and Part
Number
Resident
Bus
Video
Cirrus Logic
CL-GD7555
PCI
PC Card
Controller
Cirrus Logic
CL-PD6720
If PCI,
specify
Vendor/
Device ID
ISA
If PCI,
specify
Dev.# or
IDSEL
Option
ROM
Embedded in
BIOS?
AD13
-
-
-
-
Supported
IRQs
Address Range
I/O address:
0000-FFFFH
(Programmable)
3, 4, 5, 7, 9,
12, 14
(Programmable)
Memory address:
010000-FFFFFFH
(Programmable)
I/O address:
UART
(Com3,
Com4)
Exar ST16C462
COM3:
03E8-03EFH
COM3: IRQ4
ISA
COM4: IRQ3
COM4:
02E8-02EFH
OTHER
Table 7.
Table 8.
PCI Routing Information
INT or PIRQ pins from the chip set are connected to these
INT pins coming from each slot
Physical
Slot #
or
Onboard
Device
IDSEL #
or
DEV. #
PCI BUS #
Slot 0
AD28
0
Slot 1
AD29
0
PIRQ 0 or
INT A
PIRQ 1
or INT B
x
PIRQ 2 or
INT C
PIRQ 3
or INT D
x
x
x
Connectors
Serial
Parallel
PS/2 Mouse
PS/2 Keyboard
Video
Other
Table 9.
Software Design Specification – Feature List
USB
Enhanced IDE
PCI v2.1 Spec
PNP Spec
Other
20
Application Note
Point of Sale Terminal Design Guide
Appendix C Schematics
C.1
POS Terminal Reference Design Schematics
Schematics are provided for the following items:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Application Note
Embedded Processor Module Connectors
DRAM DIMM socket
82371SB PCI to ISA Bridge
ISA interface
PCI slots 0 and 1
ISA sockets
ISA pullup/pulldown
Super I/O
Flash BIOS
I/O connectors
Video controller
Video DRAM and VGA BIOS ROM
PCMCIA connector
Application flash
Serial and parallel communications
Power
21
NOTE
NOTE
NOTE
NOTE
NOTE
4 MD[63:0]
0:
1:
3:
4:
5:
MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
4 MPD[7:0]
4 MA[11:2]
MPD[7:0]
MA[11:2]
MPD0
MPD1
MPD2
MPD3
MPD4
MPD5
MPD6
MPD7
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
4 -MRAS2
4 -MRAS0
4 -MCAS4
4 -MCAS2
4 -MCAS5
4 -MCAS7
MWE#
MAB1
V5_0
MA6
MA5
MA3
V5_0
MA11
MA7
MA9
V5_0
MD48
MD16
MD17
GND
MD02
MD34
MD18
V5_0
MD19
MD36
MD51
V5_0
MD05
MD52
RAS6#
V3_3
MD21
MD37
CAS3#
GND
MD06
CAS1#
MD07
V3_3
CAS0#
MPD2
MD23
GND
MPD4
MPD0
CAS6#
V3_3
MPD1
MPD5
RAS1#
GND
MPD3
RAS3#
MD41
V3_3
MD30
MD44
MD57
GND
MD11
MD10
MD12
V3_3
MD60
MD27
MD28
GND
MD45
MD13
MD63
V3_3
MD31
MD15
GND
EPM DRAM Conn 140-Pin
GND
MAA1
MAA0
MAB0
V5_0
MA4
MA2
MA8
GND
MA10
MD0
MD32
V5_0
MD33
MD01
MD49
V5_0
MD35
MD50
MD03
GND
MD04
RAS7#
RAS5#
V5_0
MD20
RAS4#
MD53
GND
CAS7#
MD22
MD38
V3_3
MD39
MD54
CAS5#
GND
MD55
CAS4#
CAS2#
V3_3
MPD6
RAS0#
MPD7
GND
RAS2#
MD08
MD40
V3_3
MD25
MD24
MD56
GND
MD26
MD09
MD46
V3_3
MD42
MD59
MD58
GND
MD43
MD61
MD29
V3_3
MD62
MD14
MD47
GND
N/C
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
MD31
MD15
MD45
MD13
MD63
MD60
MD27
MD28
MD11
MD10
MD12
MD30
MD44
MD57
MD41
MPD3
MPD1
MPD5
MPD4
MPD0
MPD2
MD23
MD7
MD6
MD21
MD37
MD5
MD52
MD19
MD36
MD51
MD2
MD34
MD18
MD48
MD16
MD17
MA11
MA7
MA9
MA6
MA5
MA3
J1 GND:
A01, A09, A21, A29, A37, A45, A53, A61, A69
B15, B31, B39, B47, B55, B63, B70
J1 V3_3:
A33, A41, A49, A57, A65
B27, B35, B43, B51,
B59, B67
J1 V5_0:
A05, A13, A17, A25
B03, B07, B11,
B19, B23
MD62
MD14
MD47
MD43
MD61
MD29
MD42
MD59
MD58
MD26
MD9
MD46
MD25
MD24
MD56
MD8
MD40
MPD7
MPD6
MD55
MD39
MD54
MD22
MD38
MD53
MD20
MD4
MD35
MD50
MD3
MD33
MD1
MD49
MA10
MD0
MD32
MA4
MA2
MA8
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
-MRAS1 4
-MCAS6 4
-MCAS0 4
-MCAS1 4
-MCAS3 4
-MWE 4
MAB1 4
9 INIT
CPURST
5,7,9,13
5,7,9,13
5,7,9,13
7 -PREQ3
7 -PGNT2
-STOP
7 -PREQ1
-TRDY
7 -PREQ0
-FRAME
5 -PHLDA
5 -PHLD
18 DBRESET
7 PCLK_SLO T0
5 PCLK_PII X3
TP1 12MHZ TP
5 24MHZ
12 -A20M
5,9 INTR
5,9 -IGNNE
5,9
EPM PCI Conn 120-Pin
INIT
V3_3
CPURST STPCLK#
V3_ 3
SMI#
A20M#
GND
INTR
NMI
IGNNE#
FERR#
GND
N/C
24MHZ
V3_3
N/C 2.9V_SENSE
12MHZ
N/C
V3_ 3 14.318MHZ
N/C
GND
PCICLK_1
N/C
N/C
PCICLK_2
GND
N/C
PCICLK_3
V3_3
N/C
PCICLK_4
PCICLK_5
N/C
V3_ 3 PCICLK_0
DBRST
GND
N/C
PCICLK_IN
N/C
N/C
GND
PCIRST#
N/C
V3_3
AD30
AD31
AD28
AD29
V3_ 3
AD27
AD26
GND
PHLD#
AD25
AD23
CBE3#
GND
AD22
PHLDA#
V3_3
AD21
LOCK#
AD19
AD20
V3_ 3
AD24
FRAME#
GND
AD17
AD18
REQ0#
AD16
GND
IRDY#
CBE2#
V3_3
AD15
CBE1#
TRDY#
GNT0#
V3_ 3
AD14
AD13
GND
REQ1#
AD12
AD11
DEVSEL#
GND
AD10
AD9
V3_3
AD8
GNT#
AD7
CBE0#
V3_ 3
REQ2#
STOP #
GND
AD5
AD6
GNT2#
AD4
GND
PAR
AD3
V3_3
REQ3#
AD2
AD1
SERR#
V3_ 3
GNT3#
AD0
GND
J2
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
PCICLK_IN
AD2
AD6
AD4
-C/BE0
AD10
AD12
AD14
-C/BE1
AD18
AD16
AD20
AD24
AD25
-C/BE3
AD22
AD31
AD29
AD27
J2 GND:
A07, A15, A23, A31, A39, A47
B12, B20, B28, B36, B44,
B52, B60
13
5,7,9,12
7
-SERR 5,7,9
-PGNT3 7,13
PAR 5,7,9,13
-PREQ2
-PGNT1 7
-DEVSEL 5,7,9,13
-PGNT0 7
-IRDY
-PLOCK 7,9
-PCIRST 5,7,13
SYSCLK 8.25MHZ (PIIX3) ->
ISA Slots
14MHZ (3v): PIIX3(OSC), ISA
Slots (OSC)
24MHZ (3v): PIIX3(USBCLK),
X1(Super I/O)
-C/BE[3:0]
AD[31:0]
Date:
Size
A4
(B19) De-Skew Loopback
(A13) PIIX3
(B14) Video (Virge GX)
(A16) PCI Expansion Slot 0
(B17) PCI Expansion Slot 1
(A18) PCI Expansion Slots 2/3
5,7,13
5,7,13
Wednesday, May 13, 1998
Document Number
{Doc}
Sheet
3
POS Design Guide : Embedded Processor Module Connectors
PCICLK_0
PCICLK_1/PCLK_PIIX3
PCICLK_2/PCLK_VIDEO
PCICLK_3/PCLK_SLOT0
PCICLK_4/PCLK_SLOT1
PCICLK_5/PCLK_SLOT23
Title
-C/BE[3:0]
AD[31:0]
PCI Clock Distribution (33MHZ)
-C/BE3
-C/BE2
-C/BE1
-C/BE0
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Clock De-Skew Loop Back
(see Note 3)
PCLK_SLO T1 7
PCLK_VIDEO
14MHZ 5,8,13
V2_ 9 18
NMI 5,9
-FERR 5,9
-STPCL K 5,9
-SMI 5,9
24MHZ/14MHZ/SYSCLK
J2 V3_3:
A03, A11, A19, A27, A35, A43, A51, A55, A59
B01, B08, B16, B24, B32, B40, B48, B56
AD0
AD1
AD3
AD5
AD9
AD8
AD7
AD11
AD13
-C/BE2
AD15
AD17
AD21
AD19
AD23
AD26
AD30
AD28
12MHZ
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
ADDRESS/DATA/CLOCKS
Connectors are female
PCLK_PIIX3, PCLK_VIDEO, PCLK_SLOT0, PCLK_SLOT2, PCLK_SLOT23 must be equal length.
PCLK_0 to PCICLK_IN roundtrip must be same length as signals in NOTE 1.
Split PCLK_SLOT23 to supply both PCI SLOT 2 and PCI SLOT 3 as close to the PCI slots as possible. Stubs must be of equal length.
Separate all clocks from any other trace by 10 mil. (SYSCLK, 25MHZ, 14MHZ, PCLK_PIIX3, PCLK_VIDEO, PCLK_SLOT0, PCLK_SLOT1,
PCLK_SLOT23
MD[63:0]
4 MAA1
4 MAA0
4 MAB0
J1
DRAM
Embedded Processor Module Connectors
of
18
Rev
1.00
C5
0.1uF
1
2
3
4
1
2
3
4
MA6
MA7
MA8
MA9
MA10
MA11
1
2
3
4
1
2
3
4
0
RP4
0
RP3
0
RP2
0
RP1
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
SEE NOTE 2
C4
0.01uF
DO NOT
STUFF
C3
0.001uF
MA2
MA3
MA4
MA5
C2
0.001uF
3 -MCAS2
3 -MCAS3
3 MD[63:0]
3 MPD[7:0]
C8
0.1uF
-MCAS2
-MCAS3
MAA0
-MWE
-MCAS0
-MCAS1
MAB0
MAB1
MAA0
MAA1
MA10
MA11
MA6
MA7
MA8
MA9
MA2
MA3
MA4
MA5
C7
0.1uF
3 -MWE
3 -MCAS0
3 -MCAS1
3 -MRAS0
C6
0.1uF
C9
0.1uF
MA[11:2]
MD[63:0]
MPD[7:0]
C10
0.1uF
J3/J4 DU: A42, A62
B111, B115, B125, B126, B128, B132, B134, B135, B146
J3/J4 NC:
A24, A25, A39, A50, A51, A61, A63, A79, A80, A81
B108, B109, B114, B123, B129, B135, B145, B147, B163, B164
J3/J4 GND:
A01, A12, A23, A32, A43, A54, A64, A68, A78 | A31, A44, A82, A83
B85, B96, B107, B116, B127, B138, B148, B152, B162 | B165, B166,
B167
J3/J4 V3_3:
A06, A18, A26, A40, A41, A49, A59, A73, A84
B90, B102, B110, B124, B133, B143, B157, B168
3 MAB0
3 MAB1
3 MAA0
3 MAA1
3 MA[11:2]
C1
0.001uF
MPD2
MPD3
MPD0
MPD1
MA2
MA4
MA6
MA8
MA10
C12
0.1uF
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
C14
0.1uF
DU
DU
GND
DU
NC
CAS6
CAS7
DU
V3_3
NC
NC
CB6
CB7
GND
DQ48
DQ49
DQ50
DQ51
V3_3
DQ52
NC
DU
NC
GND
DQ53
DQ54
DQ55
GND
DQ56
DQ57
DQ58
DQ59
V3_3
DQ60
DQ61
DQ62
DQ63
GND
NC
NC
SA0
SA1
SA2
V3_3
DQ40
GND
DQ41
DQ42
DQ43
DQ44
DQ45
V3_3
DQ46
DQ47
CB4
CB5
GND
NC
NC
V3_3
DU
CAS4
CAS5
NC
DU
GND
A1
A3
A5
A7
A9
A11
NC
V3_3
B125
B126
B127
B128
B129
B130
B131
B132
B133
B134
B135
B136
B137
B138
B139
B140
B141
B142
B143
B144
B145
B146
B147
B148
B149
B150
B151
B152
B153
B154
B155
B156
B157
B158
B159
B160
B161
B162
B163
B164
B165
B166
B167
B168
B95
B96
B97
B98
B99
B100
B101
B102
B103
B104
B105
B106
B107
B108
B109
B110
B111
B112
B113
B114
B115
B116
B117
B118
B119
B120
B121
B122
B123
B124
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
C15
0.1uF
GND
DQ32
DQ33
DQ34
DQ35
V3_3
DQ36
DQ37
DQ38
DQ39
Molex 71736-0001 1
V3_3
DU
GND
OE2
RAS2
CAS2
CAS3
WE2
V3_3
NC
NC
CB2
CB3
GND
DQ16
DQ17
DQ18
DQ19
V3_3
DQ20
NC
DU
NC
GND
DQ21
DQ22
DQ23
GND
DQ24
DQ25
DQ26
DQ27
V3_3
DQ28
DQ29
DQ30
DQ31
GND
NC
NC
NC
SDA
SCL
V3_3
DQ8
GND
DQ9
DQ10
DQ11
DQ12
DQ13
V3_3
DQ14
DQ15
CB0
CB1
GND
NC
NC
V3_3
WE0
CAS0
CAS1
RAS0
OE0
GND
A0
A2
A4
A6
A8
A10
NC
V3_3
GND
DQ0
DQ1
DQ2
DQ3
V3_3
DQ4
DQ5
DQ6
DQ7
J5
C13
0.1uF
C16
0.1uF
MA3
MA5
MA7
MA9
MA11
C17
0.1uF
-MWE
-MCAS0
-MCAS1
C24
0.01uF
MPD0
MPD1
C25
0.1uF
MD4
MD5
MD6
MD7
MD0
MD1
MD2
MD3
C26
0.1uF
MPD2
MPD3
MD21
MD22
MD23
MD20
MD16
MD17
MD18
MD19
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
C29
0.1uF
DU
DU
GND
DU
NC
CAS6
CAS7
DU
V3_3
NC
NC
CB6
CB7
GND
DQ48
DQ49
DQ50
DQ51
V3_3
DQ52
NC
DU
NC
GND
DQ53
DQ54
DQ55
GND
DQ56
DQ57
DQ58
DQ59
V3_3
DQ60
DQ61
DQ62
DQ63
GND
NC
NC
SA0
SA1
SA2
V3_3
DQ40
GND
DQ41
DQ42
DQ43
DQ44
DQ45
V3_3
DQ46
DQ47
CB4
CB5
GND
NC
NC
V3_3
DU
CAS4
CAS5
NC
DU
GND
A1
A3
A5
A7
A9
A11
NC
V3_3
GND
DQ32
DQ33
DQ34
DQ35
V3_3
DQ36
DQ37
DQ38
DQ39
C30
0.1uF
Molex 71736-0001 1
V3_ 3
DU
GND
OE2
RAS2
CAS2
CAS3
WE2
V3_ 3
NC
NC
CB2
CB3
GND
DQ16
DQ17
DQ18
DQ19
V3_ 3
DQ20
NC
DU
NC
GND
DQ21
DQ22
DQ23
GND
DQ24
DQ25
DQ26
DQ27
V3_ 3
DQ28
DQ29
DQ30
DQ31
GND
NC
NC
NC
SDA
SCL
V3_ 3
DQ8
GND
DQ9
DQ10
DQ11
DQ12
DQ13
V3_ 3
DQ14
DQ15
CB0
CB1
GND
NC
NC
V3_ 3
WE0
CAS0
CAS1
RAS0
OE0
GND
A0
A2
A4
A6
A8
A10
NC
V3_ 3
GND
DQ0
DQ1
DQ2
DQ3
V3_ 3
DQ4
DQ5
DQ6
DQ7
J6
C28
0.1uF
B12 5
B12 6
B127
B12 8
B12 9
B13 0
B13 1
B13 2
B133
B13 4
B13 5
B13 6
B13 7
B138
B13 9
B14 0
B14 1
B14 2
B143
B14 4
B14 5
B14 6
B14 7
B148
B14 9
B15 0
B15 1
B152
B15 3
B15 4
B15 5
B15 6
B157
B15 8
B15 9
B16 0
B16 1
B162
B16 3
B16 4
B16 5
B16 6
B16 7
B168
B95
B96
B97
B98
B99
B10 0
B10 1
B102
B10 3
B10 4
B10 5
B10 6
B107
B10 8
B10 9
B110
B11 1
B11 2
B11 3
B11 4
B11 5
B116
B11 7
B11 8
B11 9
B12 0
B12 1
B12 2
B12 3
B124
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
C31
0.1uF
-MCAS6
-MCAS7
MA3
MA5
MA7
MA9
MA11
-MCAS4
-MCAS5
C32
0.01uF
Route on surface (cuttable)
MD60
MD61
MD62
MD63
MD56
MD57
MD58
MD59
MD53
MD54
MD55
MD52
MD48
MD49
MD50
MD51
MD46
MD47
MD41
MD42
MD43
MD44
MD45
MD40
MD36
MD37
MD38
MD39
MD32
MD33
MD34
MD35
C33
0.01uF
Date:
Size
A4
Title
Note: Termination resistors already on Mohave for MRAS#/MCAS#
MD28
MD29
MD30
MD31
-MWE
RAS
C27
0.1uF
V3_ 3
MA2
MA4
MA6
MA8
MA10
-MCAS2
-MCAS3
MD60
MD61
MD62
MD63
DO NOT
STUFF
0
R2
MAB0
MD24
MD25
MD26
MD27
MPD6
MPD7
-MCAS6 3
-MCAS7 3
3 -MRAS1
0
MD56
MD57
MD58
MD59
MD53
MD54
MD55
MD52
MD48
MD49
MD50
MD51
-MCAS6
-MCAS7
MAA1
MD14
MD15
R1
C23
0.1uF
MD46
MD47
C22
0.1uF
MD9
MD10
MD11
MD12
MD13
-MCAS4 3
-MCAS5 3
3 -MRAS2
C21
0.1uF
MD8
-MCAS4
-MCAS5
C20
100uF
MD40
MPD4
MPD5
C19
100uF
MD41
MD42
MD43
MD44
MD45
MD36
MD37
MD38
MD39
MD32
MD33
MD34
MD35
C18
0.1uF
NOTE 1: Place Test Points close to J3/J4 DIMM Connectors
NOTE 2: Use R-PACK pad geometry. Shunt pads with trace.
Note: Termination resistors already on Mohave for MRAS#/MCAS#
MD28
MD29
MD30
MD31
MD24
MD25
MD26
MD27
MD21
MD22
MD23
MD20
MD16
MD17
MD18
MD19
MD14
MD15
MD9
MD10
MD11
MD12
MD13
MD8
MD4
MD5
MD6
MD7
MD0
MD1
MD2
MD3
C11
0.1uF
V3_ 3
DRAM (DIMM) SOCKETS
C35
0.01uF
TP1 3MCAS7#TP
TP1 2MCAS6#TP
TP1 1MCAS5#TP
TP1 0MCAS4#TP
TP9 MCAS3#TP
TP8 MCAS2#TP
TP7 MCAS1#TP
TP6 MCAS0#TP
TP5 MRAS0#TP
TP4 MRAS2#TP
TP3 MWE# TP
MAB1
C36
0.001uF
C37
0.01uF
-MCAS7
-MCAS6
-MCAS5
-MCAS4
-MCAS3
-MCAS2
-MCAS1
-MCAS0
-MRAS0
-MRAS2
-MWE
C38
0.001uF
C39
0.001uF
Wednesday, May 13, 1998
Document Number
{Doc}
Sheet
POS Design Guide : DRAM DIMM Sockets
MPD6
MPD7
MPD4
MPD5
C34
0.01uF
4
of
18
Rev
1.00
7,9,13
PCLK_PII X3
TP
TP1 5
TP14
14MHZ
3,7,13
R3
1K
C42
10uF
-PIRQ[3:0]
-PIRQ[3:0]
DO NOT
STUFF
-FERR
3,7,9,13
6 DD[15:0]
3,8
-PIRQ0
-PIRQ1
-PIRQ2
-PIRQ3
AD[31:0]
-DEVSEL
-FRAME
-TRDY
-IRDY
-STO P
-C/BE[3:0]
DD[15:0]
C44
0.001uF
PCLK_PII X3
C45
0.001uF
8,9,10
8,9,10
8,9,10
8,9,10
8,9
8,9
8,9
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
-IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ14
IRQ15
V5_0
DD0
DD1
DD2
DD3
DD4
DD5
DD6
DD7
DD8
DD9
DD10
DD11
DD12
DD13
DD14
DD15
4.7K
R10
R9
C49
0.1uF
-C/BE0
-C/BE1
-C/BE2
-C/BE3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C48
0.01uF
220
OSC
DD0/SA8
DD1/SA9
DD2/SA10
DD3/SA11
DD4/SA12
DD5/SA13
DD6/SA14
DD7/SA15
DD8/SA16
DD9/SA17
DD10/SA18
DD11/SA19
DD12/SBHE
DD13
DD14/APICCS
DD15/PCS
DDRQ0
DDRQ1
IOCS16
IOCHK
ZEROWS
DREQ0
DREQ1
DREQ2
DREQ3
DREQ5
DREQ6
DREQ7
FERR
EXT SMI
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12/M
IRQ14
IRQ15
IDSEL
DEVSEL
PIRQA
PIRQB
PIRQC
PIRQD
SERR
PHLDA
PHOLD
FRAME
TRDY
IRDY
STO P
C/BE0
C/BE1
C/BE2
C/BE3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
PWROK
PCICLK
OSC
U1
C51
0.1uF
82371SB (PIIX 3)
55
50
49
48
47
46
45
44
43
41
40
39
38
37
36
35
108
111
71
6
15
87
30
12
25
91
95
99
120
125
4
58
56
34
33
32
5
10
73
75
77
83
81
154
184
149
150
151
152
3
110
109
179
181
180
185
198
187
178
167
206
205
204
203
202
201
200
199
197
194
193
192
191
190
189
188
177
176
175
174
173
172
171
168
166
165
164
163
162
161
160
159
126
132
136
C50
0.1uF
C52
0.1uF
C53
0.1uF
IORDY
DIOR
DIOW
DDAK0
DDAK1
INIT
SDIR
XDIR
XOE
RTCALE
BIOSCS
RTCCS
KBCS
RSTDRV
TC
REFRESH
SPKR
DACK0
DACK1
DACK2
DACK3
DACK5
DACK6
DACK7
INTR
SMI
STPCLK
NMI
IGNNE
VCC/VCC3
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
IOCHRDY
IOR
IOW
MEMR
SMEMR
MEMCS16
MEMW
SMEMW
MIRQ0/IRQ0
USBCLK
USBP1USBP1+
USBP0USBP0+
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
LA17/DA0
LA18/DA1
LA19/DA2
LA20/CS3P
LA21/CS1P
LA22/CS3S
LA23/CS1S
SYSCLK
BALE
AEN
PAR
C55
0.1uF
CPURST
PCIRST/APICACK
TESTIN/APICREQ
SOE
C54
0.1uF
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
69
68
67
66
63
61
59
57
130
4.7K
127
128
134 -TESTIN
R11
119
114
113
112
115
116
129
118
141
140
148
137
138
139
28
62
31
117
85
29
60
21
89
93
97
122
123
124
135
121
TC_R
C58
0.1uF
V5_ 0
PIIX3_INI T 9
SDIR 6
8,9
C61
0.1uF
SA[19:0]
22
R4
0.01uF
1
SD[15:0]
24MHZ 3
2
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
Date:
Size
A4
Title
19
1
2
3
4
5
6
7
8
9
8
18
17
16
15
14
13
12
11
1
2
3
4
1
2
3
4
R8
0
22
22
R7
RP6
22
RP5
24MHZ
TP
TP1 6
8
7
6
5
8
7
6
5
-IOW 8,9,10
-SMEMW 8,9
-MEMR 8,9,11
-SMEMR 8,9
-IOR 8,9,10
TC 8,10
BALE 8,9
AEN 8,10,11
-MEMW 8,9,11
XD[7:0] 11
XBUS
XD[7:0]
Wednesday, May 13, 1998
Document Number
{Doc}
Sheet
POS Design Guide : 82371SB PCI to ISA Bridge
RSTDRV 8,10
6
C66
0.1uF
XD7
XD6
XD5
XD4
XD3
XD2
XD1
XD0
Place close to
PIN 146 on
PIIX3
DO NOT
STUFF
C63
0
-RSTDRV
V5_ 0
B1
B2
B3
B4
B5
B6
B7
B8
74ALS2 45
G
DIR
A1
A2
A3
A4
A5
A6
A7
A8
U3
24MHZ
-IOW_R
-SMEMW_R
-MEMR_R
-SMEMR_R
-IOR_R
TC_R
BALE_R
AEN_R
-MEMW_R
Standard
Stuff
Option
SYSCLK
74HCT14 SCHMITT
U4A
SYSCLK=0 on PWROK ->PCICLK/4
33MHz/4=8.25MHz
0.1uF
C65
C64
-BIOSCS 11
CPURST 3,9
-PCIRST 3,7,13
TP17
BIOSCS#
8,10
8,10
8,10
8,10
8
8
8
INTR 3,9
-SMI 3,9
-STPCLK 3,9
NMI 3,9
-IGNNE 3,9
V3_ 3
8,9,10
8,9,10,11
SD[15:0]
R5
10K
IOCHRDY
-DACK0
-DACK1
-DACK2
-DACK3
-DACK5
-DACK6
-DACK7
SD[15:0]
6,8,9,10,11
6,8,9
PAR 3,7,9,13
C60
0.1uF
LA[23:17]
-MEMCS16 8,9
SA[19:0]
IORDY 6
-DIOR 6
-DIOW 6
-DDACK0 6
-SOE 6
C59
0.1uF
LA[23:17]
-REFRESH
SPKR 18
-IOR_R
-IOW_R
18
23
24
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
-MEMR_R
-SMEMR_R
88
19
17
16
14
13
11
9
8
7
92
94
96
98
100
101
102
107
-MEMW_R
-SMEMW_R
SYS_CLK
BALE_R
AEN_R
C57
0.1uF
70
90
22
147
146
143
142
145
144
LA17
LA18
LA19
LA20
LA21
LA22
LA23
86
84
82
80
76
74
72
153
64
20
186
C56
0.1uF
5 mil trace/space gives ~70 Ohm Zo for PCI bus as d-stripline
C47
0.001uF
195
182
170
156
155
133
131
106
105
79
65
52
51
42
26
2
1
NOTE1:
| 130, 134
1,2,26,42,51,52,65,79,105,106,131,133,155,156,170,182,195 | 111, 147
U1 GND:
DRQ0
DRQ1
DRQ2
DRQ3
DRQ5
DRQ6
DRQ7
AD12
C46
0.001uF
U1 V3_3:
6 DDRQ0
6,8,9 -IOCS16
8,9 -IOCHCK
8,9,10 -0WS
9,10
8,9,10
8,9,10
8,9,10
8,9,10
8,9,10
9,10
8,9,10
8,9,10
8,9,10
8,9,10
6,8,9,10
8,9,10
PIIX3: PCI DEVICE 1 (AD12)
-C/BE[3:0]
AD[31:0]
18 PWOK
3 PCLK_PII X3
3,7,9 -SERR
3 -PHLDA
3 -PHLD
3,7,9,13
3,7,9,13
3,7,9,13
3,7,9,13
3,7,13
C43
10uF
DO NOT
STUFF
Place close to PIN 132 on
PIIX3
2
TP
C62
0
R6
0
74ACT 04
Push-Pull
PCLK_PII X3
1
V5_0
C41
10uF
V5_0
V5_0
V5_0
V5_0
V5_0
V5_0
V5_0
V5_0
V5_0
V5_0
V5_0
V5_0
V5_0
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
U1 V5_0: 27, 53, 54,78, 103, 104, 157, 158, 183, 196, 207, 208
3,8,13 14MHZ
U2A
C40
10uF
V5_0
INTEL 82371SB PCI ISA IDE XCELERATOR
208
207
196
183
169
158
157
104
103
78
54
53
27
TP
5
of
18
Rev
1.00
LA[23:17]
LA[23:17]
DD[15:0]
SA[19:0]
R18
1K
V5_ 0
47
R17
47
33
R15
R13
47
R12
B1
B2
B3
B4
B5
B6
B7
B8
B1
B2
B3
B4
B5
B6
B7
B8
10
74ALS 08
U7C
74ALS 08
U7B
74ALS 08
U7A
18
17
16
15
14
13
12
11
18
17
16
15
14
13
12
11
8
6
3
DA2
DA0
DA1
D_SA11
D_SA10
D_SA9
D_SA8
D_SA15
D_SA14
D_SA13
D_SA12
D_SA19
D_SA18
D_SA17
D_SA16
V5_OUT
A_DD15
1
2
3
4
33
RP13
33
RP11
33
RP8
5
4
2
1
33
8
7
6
5
74ALS0 0
U8B
74ALS0 0
U8A
RP15
1
2
3
4
1
2
3
4
1
2
3
4
10K
8
7
6
5
8
7
6
5
8
7
6
5
6
3
-A_CS3
-B_CS1
DD15/PCS# &
DD14/APICCS#
not used so
strap
V5_0
SA11
SA10
SA9
SA8
SA15
SA14
SA13
SA12
SA19
SA18
SA17
SA16
1
2
3
4
33
RP16
8
7
6
5
DD3
DD2
DD1
DD0
1
2
3
4
1
2
3
4
1
2
3
4
DD11
DD10
DD9
DD8
DD7
DD6
DD5
DD4
1
2
3
4
DD15
DD14
DD13
DD12
33
33
RP14
RP12
33
33
RP10
RP9
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
V5_0
PDD[15:0]
D1
LGS260-DO
1
3
5
7
9
11
13
15
17
19
DREQ_0 21
-DIOW_0 23
-DIOR_0 25
IOCHRDY_0 27
-DMACK_0 29
DIRQ_0 31
A_DA1 33
A_DA0 35
-A_CS1 37
-HDACT_0 39
PDD7
PDD6
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0
-RESET
J7
V5_0
IDE Conn
RESET
D7
D6
D5
D4
D3
D2
D1
D0
GND
DREQ
DIOW
DIOR
IOCHRDY
DMACK
DIRQ
DA1
DA0
CS1
HDACT
R20
215
GND
D8
D9
D10
D11
D12
D13
D14
D15
KEY
GND
GND
GND
SPSYNC
GND
IOCS16
PDIAG
DA2
CS3
GND
-SBHE 8,9
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
-PDIAG
A_DA2
-CS3
SPSYNC
HD Active LED
R19
1K
PDD3
PDD2
PDD1
PDD0
PDD7
PDD6
PDD5
PDD4
PDD11
PDD10
PDD9
PDD8
PDD15
PDD14
PDD13
PDD12
3
9
5
4
2
1
74ALS2 45
G
DIR
A1
A2
A3
A4
A5
A6
A7
A8
U6
DIR=1 A to B
74ALS2 45
G
DIR
A1
A2
A3
A4
A5
A6
A7
A8
U5
DIR=1 A to B
8
7
6
5
OUT
LA20
19
1
2
3
4
5
6
7
8
9
19
1
2
3
4
5
6
7
8
9
RP7
NC
LA21
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
DD15
DD12
DD11
DD10
DD9
DD8
1
2
3
4
IN
LA19
LA17
LA18
C68
0.1uF
V5_ 0
C67
0.1uF
V5_ 0
V5_IN
IDE Interface
1
NOTE 1: Cuttable trace RP7 to V5_0
5,8,9
5 -DDACK0
5,8,9,10
IRQ14
5 IORDY
5 -DIOR
5 -DIOW
5 DDRQ0
5 -RSTDRV
5 -SOE
5 SDIR
5 DD[15:0]
5,8,9,10,11 SA[19:0]
2
TP
TP18
PDIAG#
Date:
Size
A4
Title
0
10
7
Wednesday, May 13, 1998
Document Number
{Doc}
POS Design Guide : ISA Interface
GND:
U4, U5
U6, U7
R16
DO NOT STUFF
R14
10K
V5_0 = VCC:
U4, U5 20
U6, U7 20
-IOCS16 5,8,9,
V5_ 0
Sheet
6
of
18
Rev
1.00
J6/J7 +12V:
-12V:
A2
B1
AD[31:0]
R24
10
C96
0.1uF
-C/BE0
-C/BE1
-C/BE2
-C/BE3
V5_0
AD1
AD5
AD3
AD8
AD7
AD12
AD10
AD14
AD17
AD21
AD19
AD23
AD27
AD25
AD31
AD29
C69
10uF
C70
0.1uF
2.7K
R25
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B1
B2
B3
B4
B5
B6
B7
-PIRQ1
B8
-PIRQ3
B9
-PRSNT1
B10
-PRSNT2B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
Place close to PCI Slot 0
DO NOT
STUFF
C98
100pF
PCLK_SL OT0
-PLOCK
-PERR
-SERR
-DEVSEL
3,5,9,13
3,9
9
3,5,9
-IRDY
C93
0.1uF
-PIRQ[3:0]
-C/BE[3:0]
AD[31:0]
3 -PREQ0
PCLK_SLO T0
-PIRQ[3:0]
-C/BE[3:0]
3,5,9,13
3 PCLK_SLO T0
5,9,13
3,5,13
3,5,13
J6/J7 GND:
A12, A13, A18, A24, A30, A35, A37, A42, A48, A56
B3, B12, B13, B15, B17, B28, B34, B38, B46, B49, B57 | B2
J6/J7 NC:
A9, A11, A14, A19
B10, B14
J6/J7 V3_3:
A21, A27, A33, A39 A45, A53
B25, B31, B36, B41, B43, B54
J6/J7 V5_0:
A5, A8, A10, A16, A59, A61, A62 | A1, A3, A4
B5, B6, B19, B22, B59, B61, B62
J8
C72
0.1uF
C/BE0
V3_3
AD[06]
AD[04]
GND
AD[02]
AD[00]
V5_0
REQ64
V5_0
V5_0
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
C73
0.01uF
TRST
+12V
TMS
TDI
V5_0
INTA
INTC
V5_0
NC
V5_0
NC
GND
GND
NC
RST
V5_0
GNT
GND
NC
AD[30]
V3_3
AD[28]
AD[26]
GND
AD[24]
IDSEL
V3_3
AD[22]
AD[20]
GND
AD[18]
AD[16]
V3_3
FRAME
GND
TRDY
GND
STOP
V3_3
SDONE
SBO
GND
PAR
AD[15]
V3_3
AD[13]
AD[11]
GND
AD[09]
PCI SLOT 0
PCI Conn
AD[08]
AD[07]
V3_ 3
AD[05]
AD[03]
GND
AD[01]
V5_ 0
ACK64
V5_ 0
V5_ 0
-12V
TCK
GND
TDO
V5_ 0
V5_ 0
INTB
INTD
PRSNT1
NC
PRSNT2
GND
GND
NC
GND
CLK
GND
REQ
V5_ 0
AD[31]
AD[29]
GND
AD[27]
AD[25]
V3_ 3
C/BE3
AD[23]
GND
AD[21]
AD[19]
V3_ 3
AD[17]
C/BE2
GND
IRDY
V3_ 3
DEVSEL
GND
LOCK
PERR
V3_ 3
SERR
V3_ 3
C/BE1
AD[14]
GND
AD[12]
AD[10]
GND
C71
0.1uF
V5_0
2.7K
R26
-PIRQ0
-PIRQ2
V5_0
C74
0.01uF
V5_ 0
AD2
AD0
AD6
AD4
AD9
AD13
AD11
AD15
AD18
AD16
AD22
AD20
AD24
AD28
AD26
AD30
C75
10uF
C77
0.1uF
SDONE 9
-SBO 9
PAR 3,5,9,13
-STO P 3,5,9,13
-TRDY 3,5,9,13
-FRAME 3,5,9,13
PCIA2
AD28
-PGNT0 3
-PCIRST 3,5,13
C76
0.1uF
V3_3
C79
0.1uF
R21
220
C80
0.1uF
C94
0.1uF
R23
0
C95
0.1uF
-C/BE0
-C/BE1
-C/BE2
-C/BE3
C82
0.1uF
V5_ 0
AD1
AD5
AD3
AD8
AD7
2.7K
R27
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B1
B2
B3
B4
B5
B6
B7
-PIRQ0
B8
-PIRQ2
B9
-PRSNT1
B10
-PRSNT2 B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
AD31
B21
AD29
B22
B23
AD27
B24
AD25
B25
B26
B27
AD23
B28
B29
AD21
B30
AD19
B31
B32
AD17
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
AD14
B46
B47
AD12
B48
AD10
B49
C81
10uF
Place close to PCI Slot 1
DO NOT
STUFF
C97
0
PCLK_SLO T1
-PLOCK
-PERR
-SERR
-DEVSEL
-IRDY
PCLK_SLO T1
3 -PREQ1
3 PCLK_SLO T1
C78
10uF
+12V
PCI SLOTS
J9
C/BE0
V3_3
AD[06]
AD[04]
GND
AD[02]
AD[00]
V5_0
REQ64
V5_0
V5_0
TRST
+12V
TMS
TDI
V5_0
INTA
INTC
V5_0
NC
V5_0
NC
GND
GND
NC
RST
V5_0
GNT
GND
NC
AD[30]
V3_3
AD[28]
AD[26]
GND
AD[24]
IDSEL
V3_3
AD[22]
AD[20]
GND
AD[18]
AD[16]
V3_3
FRAME
GND
TRDY
GND
STOP
V3_3
SDONE
SBO
GND
PAR
AD[15]
V3_3
AD[13]
AD[11]
GND
AD[09]
C84
0.1uF
PCI SLOT 1
PCI Conn
AD[08]
AD[07]
V3_3
AD[05]
AD[03]
GND
AD[01]
V5_0
ACK64
V5_0
V5_0
-12V
TCK
GND
TDO
V5_0
V5_0
INTB
INTD
PRSNT1
NC
PRSNT2
GND
GND
NC
GND
CLK
GND
REQ
V5_0
AD[31]
AD[29]
GND
AD[27]
AD[25]
V3_3
C/BE3
AD[23]
GND
AD[21]
AD[19]
V3_3
AD[17]
C/BE2
GND
IRDY
V3_3
DEVSEL
GND
LOCK
PERR
V3_3
SERR
V3_3
C/BE1
AD[14]
GND
AD[12]
AD[10]
GND
C83
0.1uF
V5_0
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
C85
0.01uF
2.7K
R28
V5_0
AD2
AD0
AD6
AD4
AD9
AD13
AD11
AD15
AD18
AD16
AD22
AD20
AD24
AD28
AD26
AD30
Date:
Size
A4
Title
-PIRQ3
-PIRQ1
V5_ 0
C86
0.01uF
C88
0.1uF
PCIB2
AD29
C89
0.1uF
R22
220
C90
10uF
C91
0.1uF
+12V
C92
0.1uF
Wednesday, May 13, 1998
Document Number
{Doc}
POS Design Guide : PCI Slots 0 & 1
SDONE
-SBO
PAR
-STO P
-TRDY
-FRAME
-PGNT1 3
-PCIRST
C87
10uF
V3_3
Sheet
of
18
Rev
1.00
-0WS
5,9,10
9
5,9
5,6,9
5,9,10
5,9,10
5,9,10
5,9,10
5,6,9,10
5,10
5,9,10
5
5,9
5
5,9
5
5,9
-MASTER
-MEMCS16
-IOCS16
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
-DACK0
DRQ0
-DACK5
DRQ5
-DACK6
DRQ6
-DACK7
DRQ7
3,5,13 14MHZ
-SMEMW
-SMEMR
-IOW
-IOR
-DACK3
DRQ3
-DACK1
DRQ1
-REFRESH
SYSCLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
-DACK2
TC
BALE
DRQ2
5,9,10
5,9
5,9
5,9,10,11
5,9,10
5,10
5,9,10
5,10
5,9,10
5,9
5
5,9,10
5,9,10
5,9,10
5,9,10
5,9,10
5,10
5,10
5,9
IRQ9
5,9,10
C101
0.1uF
SD[15:0]
3
SYSCLK
14MHZ
R31
0
SBHE
LA23
LA22
LA21
LA20
LA19
LA18
LA17
MEMR
MEMW
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
IOCHCK
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
IOCHRDY
AEN
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
C108
10uF
SYSCLK
5,9
C110
0.1uF
-MEMR 5,9,11
-MEMW 5,9,11
-SBHE 6,9
IOCHRDY 5,9,10
AEN 5,10,11
-IOCHCK
C109
0.1uF
V5_ 0
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
C111
0.1uF
LA23
LA22
LA21
LA20
LA19
LA18
LA17
C112
0.01uF
Place close to connectors
DO NOT
STUFF
C127
0
14MHZ_ISA
TP
ISA Conn A
MCS16
IOCS16
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
DACK0
DRQ0
DACK5
DRQ5
DACK6
DRQ6
DACK7
DRQ7
V5_0
MASTER
GND
GND
RSTDRV
V5_0
IRQ9
-5V
DRQ2
-12V
0WS
+12V
GND
SMEMW
SMEMR
IOW
IOR
DACK3
DRQ3
DACK1
DRQ1
REFRESH
CLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
DACK2
TC
BALE
V5_0
OSC
GND
J10
C107
0.1uF
TP2 0
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
C106
0.1uF
TP
Do Not Stuff
-5V
C105
10uF
+12V
TP1 9
1K
R29
4 14MHZ_ISA
V5_0
C104
0.1uF
Note Cap Direction
C103
0.1uF
+12 V -12V
LA[23:17]
SD[15:0]
SA[19:0]
C102
10uF
-12V
Place close to connectors
DO NOT
STUFF
C126
0
R30
0
U2B
74ACT 04
LA[23:17]
5,9,10,11
5,6,9
SA[19:0]
5,6,9,10,11
Note Cap Direction
C100
0.1uF
5,10 RSTDRV
C99
10uF
-5V
C114
10uF
B09
B07
B05
C116
0.1uF
+12V
-MASTER
-MEMCS16
-IOCS16
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
-DACK0
DRQ0
-DACK5
DRQ5
-DACK6
DRQ6
-DACK7
DRQ7
14MHZ_ISA
-SMEMW
-SMEMR
-IOW
-IOR
-DACK3
DRQ3
-DACK1
DRQ1
-REFRESH
SYSCLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
-DACK2
TC
BALE
-0WS
DRQ2
IRQ9
RSTDRV
-12V
-5V
Note Cap Direction
C115
0.1uF
-5V
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
D16
D17
D18
B01
B02
B03
B04
B05
B06
B07
B08
B09
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
C119
0.1uF
SBHE
LA23
LA22
LA21
LA20
LA19
LA18
LA17
MEMR
MEMW
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
IOCHCK
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
IOCHRDY
AEN
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
Note Cap Direction
C118
0.1uF
ISA Conn B
MCS16
IOCS16
IRQ10
IRQ11
IRQ12
IRQ15
IRQ14
DACK0
DRQ0
DACK5
DRQ5
DACK6
DRQ6
DACK7
DRQ7
V5_0
MASTE R
GND
GND
RSTDRV
V5_0
IRQ9
-5V
DRQ2
-12V
0WS
+12V
GND
SMEMW
SMEMR
IOW
IOR
DACK3
DRQ3
DACK1
DRQ1
REFRESH
CLK
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
DACK2
TC
BALE
V5_0
OSC
GND
J11
C117
10uF
-12V
NOTE 1: ISA Conn B is a shared slot with PCI slot 3
(see ATX spec)
J10/11: +12V
-12V
-5V
J10/11 V5_0:
B03, B29,
B31, D16
J10/11 GND:
B01, B10, D18
C113
0.01uF
ISA Slots
C01
C02
C03
C04
C05
C06
C07
C08
C09
C10
C11
C12
C13
C14
C15
C16
C17
C18
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
C120
10uF
-MEMR
-MEMW
-SBHE
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
C123
0.1uF
Date:
Size
A4
Title
C122
0.1uF
IOCHRDY
AEN
-IOCHCK
C121
0.1uF
V5_0
LA2 3
LA2 2
LA2 1
LA2 0
LA1 9
LA1 8
LA1 7
C125
0.01uF
Wednesday, May 13, 1998
Document Number
{Doc}
POS Design Guide : ISA Sockets
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
C124
0.01uF
Sheet
8
of
18
Rev
1.00
5,6,8,10,11
SD[15:0]
5,8,10 IRQ11
5,8,10 IRQ12
5,6,8,10 IRQ14
5,8,10 IRQ15
5,8,10 IRQ6
5,8,10 IRQ7
5,8,10 IRQ9
5,8,10 IRQ10
1
2
3
4
SD4
SD5
SD6
SD7
10K
RP25
10K
RP21
10K
RP20
10K
RP18
1
2
3
4
SA4
SA5
SA6
SA7
10K
RP38
10K
RP36
10K
RP34
10K
RP32
10K
RP30
C136
10pF
C130
10pF
SA1 6 1
SA1 7 2
SA1 8 3
SA1 9 4
SA1 2 1
SA1 3 2
SA1 4 3
SA1 5 4
SA8 1
SA9 2
SA1 0 3
SA1 1 4
1
2
3
4
SA0
SA1
SA2
SA3
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
C131
10pF
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
C137
10pF
SA[19:0]
SD12 1
SD13 2
SD14 3
SD15 4
SD8 1
SD9 2
SD10 3
SD11 4
1
2
3
4
SD0
SD1
SD2
SD3
SD[15:0]
C129
10pF
C135
10pF
SD[15:0]
SA[19:0]
5,10 IRQ1
5,8,10 IRQ3
5,8,10 IRQ4
5,8,10 IRQ5
SA[19:0]
5,8,10,11
5,6,8 LA[23:17]
5,8 DRQ5
5,8 DRQ6
5,8 DRQ7
5,8,10 DRQ0
5,8,10 DRQ1
5,8,10 DRQ2
5,8,10 DRQ3
LA[23:17]
5,8 -IOCHCK
5,8,10 IOCHRDY
5,10 -IRQ8
8 -MASTER
5,8,10 -0WS
5,8 -REFRESH
5,8 -MEMCS16
5,6,8 -IOCS16
5,8,10 -IOR
5,8,10,11 -IOW
5,8,11 -MEMW
5,8,11 -MEMR
5,8 BALE
6,8 -SBHE
5,8 -SMEMR
5,8 -SMEMW
C138
10pF
C132
10pF
C139
10pF
C133
10pF
C140
10pF
C134
10pF
4.7K
R33
1K
R32
330
RP26
330
RP22
4.7K
RP19
10K
RP17
1
2
3
4
1
2
3
4
2.7K
RP33
2.7K
RP31
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
1
2
3
4
1
2
3
4
1
2
3
4
5.6K
RP37
5.6K
RP35
10K
RP41
10K
RP40
10K
RP39
1
2
3
4
1
2
3
4
DRQ[0:3,5:7]
LA2 1
LA2 2
LA2 3
LA1 7
LA1 8
LA1 9
LA2 0
LA[23:17]
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
CONTROL
+ -IRQ8
IRQ1,3:12,14,15
V5_0
V5_0
ISA Pullup/Pulldown
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
V5_0
V5_0
V5_0
V5_0
-PIRQ0
-PIRQ1
-PIRQ2
-PIRQ3
1
2
3
4
1
2
3
4
330
R37
4.7K
R36
4.7K
R34
4.7K
RP28
2.7K
8
7
6
5
8
7
6
5
V3_ 3
V5_ 0
7
-SBO
-PERR
SDONE
-PLOCK
5 PIIX3_INI T
10 -KBDRST
R38
4.7K
V5_0
R39
4.7K
V5_0
5
Note: Pullups on Mohave -PREQ/PGNT[3:0]
74ACT 04
U2C
6
13
12
74ALS 08
U7D
C128
0.1uF
V5_ 0
1
2.7K
R35
2.7K
RP29
2.7K
RP27
2.7K
8
7
6
5
8
7
6
5
8
7
6
5
74ACT0 5
U9A
Date:
Size
A4
Title
11
1
2
3
4
1
2
3
4
1
2
3
4
RP24
V5_0
R40
330
V3_3
INIT 3
-PGNT0
-PGNT1
-PGNT2
-PGNT3
-PREQ0
-PREQ1
-PREQ2
-PREQ3
1
2
3
4
1
2
3
4
REQ/GNT Pull-ups
2.7K
RP51
2.7K
RP50
Wednesday, May 13, 1998
Document Number
{Doc}
POS Design Guide : ISA Pullup/Pulldown
2
-TRDY/-IRDY/ETC
PAR
-SERR
-STO P
3,5,7,13
3,5,7
3,5,7,13
3,5,7,13
-DEVSEL
3,5,7,13
-TRDY
3,5,7,13
-IRDY
3,5,7,13
-FRAME
7
7
3,7
Note: 64-BIT PCI Strap Off At PCI Connectors
3,5 CPURST
3,5 -STPCL K
3,5 -IGNNE
3,5 INTR
3,5 -FERR
3,5 NMI
3,5 -SMI
5,7
5,7,13
5,7
5,7
RP23
PIRQ
PCI Pullup/Pulldown
8
7
6
5
8
7
6
5
Sheet
V3_ 3
V5_ 0
9
of
18
Rev
1.00
3
BT1
HU 2032-1 SOCKET
C160
22uF
VBA T
22
VBA T
APPFLSH_SA19
APPFLSH_SA20
APPFLSH_SA21
APPFLSH_WP#
R83 4.7k
R53
NOTE 1:
NOTE 2:
NOTE 3:
R47
10K
R48
10K
R49
10K
R50
10K
J13
1x2
R51
10K
1x2
J14
-CLRCMOS
10K
R55
V5_ 0
CTS1 12
DCD1 12
DSR1 12
DTR1 12
RI1 12
RTS1 12
RXD1 12
TXD1 12
CTS0 12
DCD0 12
DSR0 12
DTR0 12
RI0 12
RTS0 12
RXD0 12
TXD0 12
MDAT
MCLK
-KBDRST 9
-A20M 3
TP27 TP2 8 TP29 TP3 0 TP3 1 TP32 TP3 3 TP34 TP3 5 TP3 6 TP37
G10
G11
G12
G13
G14
G15
G16
G17
G20
G21
G22
R46
10K
DO NOT STUFF
V5_0
-A20M
R43
4.7K
R41
4.7K
2
TP
TP
TP
TP
TP
TP
TP
TP
TP
Place oscillator circuit close to X1C/X2C. Paracitic <=8pF
Crystal is parallel, resonant, (N cut) or XY bar, Q>=35, Cl=9-13pF
Test points are a hole/via such that a 25-mil square pin can be inserted.
V5_0: 1, 24, 61, 100, 121, 140 | 65, 66
GND: 2, 11, 25, 40, 60, 101, 120, 130, 139 | 79, 80
PC87307IBU-VUL
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO20
GPIO21
GPIO22
P20
V3_ 3
KBDAT
KBCLK
TP
1
V5_ 0
P17
C151
0.01uF
1
D2
FMMD914
R52
22M
12
12
12
12
12
12
12
12
P16
PARALLEL
(SPP/EPP)
P12
TP2 1 TP2 2 TP23 TP2 4 TP25
P12
P16
P17
P20
P21
C150
0.01uF
TP
TP
2
R54 120K
PPDR0
PPDR1
PPDR2
PPDR3
PPDR4
PPDR5
PPDR6
PPDR7
-WAIT 12
-WRITE 12
-ACK 12
SLCT 12
PE 12
-ERR 12
-INIT 12
-ASTRB 12
-DSTRB 12
KEYBOARD
C149
0.01uF
FLOPPY
C148
0.1uF
2
2
COM1
1
1
2
2
C156
470pF
C153
470pF
M_CLK
C155
470pF
V5_0
C152
470pF
SMD125-002
C154
470pF
C157
470pF
FB4
BLM41A80 0S
F2
B1
B2
B3
B4
B5
B6
J12
PS2 STACK
MDATA
NC
GND
M_VCC
M_CLK
NC
KBDAT A
NC
GND
KB_VCC
KB_CLK
NC
*0
1
= X-BUS DISABLED
= X-BUS ENABLED
Date:
Size
A4
Title
13
14
15
16
17
Wednesday, May 13, 1998
Document Number
{Doc}
POS DESIGN GUIDE: Super I/O
RTS1/BADDR1 (Pin 136), DTR1/BADDR0 (Pin 134)
00 = Full PNP ISA
01 = Wake in Wait for Key (index pnp isa)
10 = PNP Motherbd (wake in config state index 0x15C)
*11 = PNP Motherbd (wake in config state index 0x2E)
SOUT1/CFG3 (Pin 148) , RSTB/CFG2 (Pin 146)
00 = Clock Source 24MHZ AT PIN X1
01 = RESERVED
10 = Clock Source 48MHZ AT PIN X1
*11 = Clock Source 32KHZ INTERNAL
MULT
-DTRB/CFG1 (Pin 144)
GND
GND
GND
GND
GND
TOP
BOTTOM
SOUT1/CFG0 (Pin 138) 0 = FDC,KBC,RTC WAKEUP INACTIVE
*1 = FDC, KBC,RTC WAKEUP ACTIVE
M_VCC
MDATA
KB_VCC
KB_CLK
KBDAT A T1
T2
T3
T4
T5
T6
PS/2 Keyboard/Mouse
BLM41A800S: [email protected]/500mA
FB1
BLM41A80 0S
F1
CONFIGURATION STRAPPING
(30K unternal pulldown default)
BLM41A80 0S
BLM41A80 0S
FB6
2
1
2
1
FB5
R45
4.7K
BLM41A8 00S
BLM41A8 00S
FB3
2
1
2
1
FB2
COM0
R44
4.7K
1
1
R42
4.7K
2
VBAT_GND
C159
10pF
TP
Y1
32.768KHZ
KBCLK
KBDA T
MCLK
MDAT
MSEN0 12
MSEN1 12
DRATE0 12
-MOTE A 12
-MOTE B 12
-DRVSA 12
-DRVSB 12
-WDATA 12
-DIR 12
-STE P 12
-SIDE1 12
-WGAT E 12
FDDEN 12
-RDATA 12
-TRK0 12
-INDEX 12
-WPT 12
-DSKCHG 12
C147
0.1uF
TP
10pF
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
C146
0.1uF
2
C158
RSTDRV
DRQ0
DRQ1
DRQ2
DRQ3
-DACK0
-DACK1
-DACK2
-DACK3
5,8
5,8,9
5,8,9
5,8,9
5,8,9
5,8
5,8
5,8
5,8
MSEN0
MSEN1
DRATE0
MTR0
MTR1
DR0
DR1
WDATA
DIR
STEP
HDSEL
WGATE
DENSEL
RDATA
TRK0
INDEX
WP
DSKCHG
V5_0
GND
KBCLK
KBDAT
MCLK
MDAT
P12
P16
P17
P20
P21
C145
0.1uF
TP
BUSY/WAIT
WRITE/STB
ACK
SLCT
PE
ERR
INIT
ASTRB/SLIN
AFD/DSTRB
GND
V5_0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
GND
CTS1
DCD1
DSR1
DTR1/BADDR0
RI1
BADDR1/RTS1
SIN1
CFG0/SOUT1
GND
V5_0
CTS2
DCD2
DSR2
CFG1/DTR2/
RI2
CFG2/RTS2
SIN2
CFG3/SOUT2
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO20
GPIO21
GPIO22
GPIO23
Super I/O
V5_0
GND
D0
D1
D2
D3
D4
D5
D6
D7
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
V5_0
GND
A12
A13
A14
A15
AEN
ZWS
IOCHRDY
RD
WR
TC
IRQ1
IRQ3
IRQ4
IRQ5
GND
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ14
IRQ15
X1
MR
DRQ0
DRQ1
DRQ2
DRQ3
DACK0
DACK1
DACK2
DACK3
GND
V5_0
X1C
X2C
VBAT
VCCH
SWITCH
ONCTL
CS0
XDCS
XRD
XD0
XD1
GPIO24
GPIO25
GPIO26
GPIO27
XD6
XD7
IRRX2/IRSL0/ID0
IRRX1
IRTX
C144
0.1uF
TP
2
32kHZ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
X1
51
52
53
54
55
56
57
58
59
60
61
62
X2C 63
64
65
66
-SWITCH
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
C143
0.1uF
TP
2
IRQ6
IRQ7
-IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ14
IRQ15
SA12
SA13
SA14
SA15
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
U10
C142
10uF
1
1
5,8,9
5,8,9
5,9
5,8,9
5,8,9
5,8,9
5,8,9
5,6,8,9
5,8,9
5,8,11 AEN
5,8,9 -0WS
5,8,9 IOCHRDY
5,8,9 -IOR
5,8,9,11
-IOW
5,8 TC
5,9 IRQ1
5,8,9 IRQ3
5,8,9 IRQ4
5,8,9 IRQ5
SA[19:0]
C141
10uF
1
13
SA[19:0]
5,6,8,9,10
SD[15:0]
V5_0
2
TP2 6
X1
SD[15:0]
5,8,9,10
V5_ 0
SUPER I/O
1
SMD125-002
1
Sheet
10
of
18
Rev
1.00
10
12
7,8
16
7
20
24
1,14
32
14
SA[19:0]
XD[7:0]
SA16
9
1-2
2-3
Recover
Normal
8
Pos
74ALS0 0
U8C
J15
1x3
2
Mode
10
3
GND:
U12
U9
U10/U11
U13
U7
VCC:
U12
U9
U10/U11
U13
U7
SA[19:0]
5 XD[7:0]
-MEMR
5,6,8,9,10
-MEMW
5,8,9
5 -BIOSCS
5,8,9
1
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
ADDR16
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
28F001BX -T150
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
U11
BOOT BLOCK FLASH
VPP
OE
WE
CE
RP
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
1
24
31
22
30
13
14
15
17
18
19
20
21
R57
20K
BIOS_VP P
-BIOS_RP
XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7
C163
0.1uF
V5_0
1x1
1
J16
R56
8.2K
V5_0
C162
0.1uF
+12 V
J17
1x2
Mode
Program
Normal
Pos
IN
OUT
Pull To VPP For Boot Block Unlocking
C161
0.1uF
1
2
Date:
Size
A4
Title
POS Design Guide : Flash Bios
Wednesday, May 13, 1998
Document Number
{Doc}
Sheet
11
of
18
Rev
1.00
DCD0
DSR0
RXD0
RTS0
TXD0
CTS0
DTR0
10 RI0
DCD1
DSR1
RXD1
RTS1
TXD1
CTS1
DTR1
10 RI1
10
10
10
10
10
10
10
10
10
10
10
10
10
10
20
19
18
17
16
15
14
13
12
11
GD75232S OP
V5_0 +12V
RY1
RA1
RY2
RA2
RY3
RA3
DA1
DY1
DA2
DY2
RY4
RA4
DA3
DY3
RY5
RA5
GND -12V
U13
GD75232S OP
SP_DCD1
SP_DSR1
SP_RXD 1
SP_RTS 1
SP_T XD1
SP_CTS 1
SP_DTR1
SP_RI1
+12 V
-12V
SP_DCD0
SP_DSR0
SP_RXD 0
SP_RTS 0
SP_T XD0
SP_CT S0
SP_DTR0
SP_RI0
+12 V
-12V
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
C172
470pF
C188
470pF
C184
470pF
C177
470pF
C173
470pF
-DSKCHG
-SIDE1
-RDATA
-WPT
-TRK0
-WGATE
-WDATA
-STE P
-DIR
-MOTE B
-DRVSA
-DRVSB
-MOTE A
-INDEX
DRATE0
10 FDDEN
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
C174
470pF
C190
470pF
C186
470pF
C179
470pF
C175
470pF
C191
470pF
C187
470pF
C180
470pF
R60
1K
D3
V5_0
D18
D1N916A
D1N916A
D13
D8
D1N916A
D1N916A
D15
D1N916A
D20
D1N916A
D14
D1N916A
D19
D1N916A
8
7
6
5
D6
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
JP1
+12V
D7
-12V
D22
D1N916A
D1N916A
D17
+12V
+12V
D12
D1N916A
D1N916A
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
C168
0.1uF
Pin 5 is the Key
FLOPPY
D21
D1N916A
D1N916A
D16
D11
D1N916A
D1N916A
FLOPPY HEADER 17X2
D10
D1N916A
D9
D1N916A
RP48
1K
D5
D1N916A
D4
D1N916A
1
2
3
4
10 MSEN0
10 MSEN1
C189
470pF
C185
470pF
C178
470pF
C167
0.1uF
+12V
14
18
13
17
12
16
11
15
10
5
9
4
8
3
7
2
6
1
SERIAL STACK
14
18
13
17
12
16
11
15
10
5
9
4
8
3
7
2
6
1
J18
C169
0.1uF
V5_0
COM1
COM0
10 -ACK
10 -WAIT
10 PE
10 SLCT
10 PPDR4
10 PPDR5
10 PPDR6
10 PPDR7
10 PPDR0
10 PPDR1
10 PPDR2
10 PPDR3
10 -INIT
10 -ERR
10 -DSTRB
10 -WRITE
10 -ASTRB
1
2
3
4
1
2
3
4
PDR4
PDR5
PDR6
PDR7
-ACK
-WAIT
PE
SLCT
1
2
3
4
1
2
3
4
PDR0
PDR1
PDR2
PDR3
-INIT
-ERR
-DSTRB
-WRITE
22
R59
22
RP49
33
RP47
33
RP46
22
RP45
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
R58
4.7K
5
6
7
8
V5_0 +12V
RY1
RA1
RY2
RA2
RY3
RA3
DA1
DY1
DA2
DY2
RY4
RA4
DA3
DY3
RY5
RA5
GND -12V
C166
0.1uF
-12V
RP42
4.7K
V5_0
5
6
7
8
U12
C165
0.1uF
V5_0
Clamped diodes acting as input port protection
C164
0.1uF
+12V
RP43
4.7K
5
6
7
8
20
19
18
17
16
15
14
13
12
11
COM0/COM1
-12V
I/O CONNECTORS
4
3
2
1
4
3
2
1
4
3
2
1
Date:
Size
A4
Title
RP44
4.7K
PPSLC T
PPE
-PPWAI T
-PPACK
PPDR7
PPDR6
PPDR5
PPDR4
PPDR3
PPDR2
PPDR1
PPDR0
-PPWRITE
-PPDSTRB
-PPERR
-PPINIT
-PPASTR B
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
J19
DB25
Wednesday, May 13, 1998
Document Number
{Doc}
POS Design Guide : I/O Connectors
C201
220pF
C200
220pF
C199
220pF
C198
220pF
C197
220pF
C196
220pF
C195
220pF
C194
220pF
C193
220pF
C192
220pF
C183
220pF
C182
220pF
C181
220pF
C176
220pF
C171
220pF
C170
220pF
PARALLEL
27
26
Sheet
12
of
18
Rev
1.00
-PIRQ[3:0]
-PIRQ[3:0]
-PIRQ1
-WE
-OE
-IRDY
PAR
-PCIRST
-STO P
-TRDY
14MHZ
-C/BE0
-C/BE1
-C/BE2
-C/BE3
PCLK_VIDEO
-DEVSEL
-FRAME
IDSEL
R67
220
AD13
AD[31:0]
VMD[63:48]
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE0#
C/BE1#
C/BE2#
C/BE3#
CLK
DEVSEL#
FRAME#
IDSEL
INTR#
IRDY#
PAR
RST #
STO P#
TRDY#
OSC/XVCLK
MCLK/SW0/XMCLK
VCLK0/DDCC
CAS#/WE#
OE#
C208
0.1uF
C209
0.1uF
C210
0.1uF
C211
0.1uF
C212
0.1uF
C213
0.01uF
MAVSS
VAVSS
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
DACVDD
CRTVDD
RED
GREEN
BLUE
VREF
IREF
DACVDD
DACVSS2
DACVSS1
VSYNC
HSYNC
LFS
FPVDCLK
LLCLK
FPDE
FPDECTL
VACTI
HREFI
VS1
VPCLK1
DDCD
EROM#
PROG0
PROG1/TWR#
PROG2
ACTI
CLK32K/SUSPST#
FPVCC
FPVEE
SUSPI
U14
CL-GD7555
C214
0.01uF
R68 R69
33 33
HREFI
VSYNC
HSYNC
1uF
C217
MAVDD
V5_0
CAP
C220
32kHZ
-EROM
V5_0
RED
GREEN
BLUE
VREF
IREF
DAC_VDD
CAP
252
107
25
49
64
85
99
128
154
171
177
192
220
233
256
109
117
122
121
120
115
116
134
142
113
114
112
156
155
153
152
124
108
106
110
111
104
253
127
119
129
63
57
125
123
56
R61 R62 R63
150 150 150
R R66
R R65
R64
180
MVDD
C216
0.01uF
DACVDD
C215
0.01uF
CAP
36
77
188
189
207
208
243
244
15
16
194
228
C219
BVDD2
BVDD1
CAS7#
CAS6#
CAS5#
CAS4#
CAS3#
CAS#2
CAS1#
CAS0#
RAS1
RAS0
C218
150
149
148
147
146
145
144
143
141
140
139
138
137
136
135
133
132
131
176
175
174
173
172
170
169
168
167
166
164
163
162
161
160
159
158
157
193
221
222
223
224
225
229
230
231
232
V5_0
FP35
FP34
FP33
FP32
FP31
FP30
FP29
FP28
FP27
FP26
FP25
FP24
FP23
FP22
FP21
FP20
FP19
FP18
FP17
FP16
FP15
FP14
FP13
FP12
FP11
FP10
FP9
FP8
FP7
FP6
FP5
FP4
FP3
FP2
FP1
FP0
MA9
MA8
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
V5_0
C207
0.1uF
254
191
190
130
126
118
66
65
62
2
1
MA[8:0]
C206
1uF
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
-CAS0
-CAS1
-CAS2
-CAS3
-CAS4
-CAS5
-CAS6
-CAS7
-RAS0
AD0 84
AD1 83
AD2 81
AD3 80
AD4 79
AD5 78
AD6 76
AD7 75
AD8 74
AD9 73
AD10 72
AD11 71
AD12 70
AD13 69
AD14 68
AD15 67
AD16 42
AD17 41
AD18 40
AD19 39
AD20 38
AD21 37
AD22 35
AD23 34
AD24 33
AD25 32
AD26 31
AD27 30
AD28 29
AD29 28
AD30 27
AD31 26
61
60
59
58
50
47
52
53
43
51
46
55
45
48
54
251
98
226
255
C205
1uF
200
227
8
151
165
239
82
44
105
250
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
VMD[47:32]
C204
1uF
MD0/ROMD0
MD1/ROMD1
MD2/ROMD2
MD3/ROMD3
MD4/ROMD4
MD5/ROMD5
MD6/ROMD6
MD7/ROMD7
MD8/ROMA0
MD9/ROMA1
MD10/ROMA2
MD11/ROMA3
MD12/ROMA4
MD13/ROMA5
MD14/ROMA6
MD15/ROMA7
MD16/ROMA8
MD17/ROMA9
MD18/ROMA10
MD19/ROMA11
MD20ROMA12
MD21/ROMA13
MD22/ROMA14
MD23/ROMA15
MD24/SW1PU
MD25/SW2PU
MD26
MD27/SCANPU
MD28/INTPU
MD29/XCLKPU
MD30/ROM32KPU
MD31/BIOSPU
MD32
MD33/TMPU
MD34/MMIOPU
MD35
MD36
MD37
MD38
MD39
MD40/RIOPU
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
MVDD3
MVDD2
MVDD1
FPVDD2
FPVDD1
CVDD3
CVDD2
CVDD1
VAVDD
MAVDD
MA_VDD
VMD[31:16]
C203
10uF
VMD63
VMD62
VMD61
VMD60
VMD59
VMD58
VMD57
VMD56
VMD55
VMD54
VMD53
VMD52
VMD51
VMD50
VMD49
VMD48
VMD47
VMD46
VMD45
VMD44
VMD43
VMD42
VMD41
VMD40
VMD39
VMD38
VMD37
VMD36
VMD35
VMD34
VMD33
VMD32
VMD31
VMD30
VMD29
VMD28
VMD27
VMD26
VMD25
VMD24
VMD23
VMD22
VMD21
VMD20
VMD19
VMD18
VMD17
VMD16
VMD15
VMD14
VMD13
VMD12
VMD11
VMD10
VMD9
VMD8
VMD7
VMD6
VMD5
VMD4
VMD3
VMD2
VMD1
VMD0
24
23
22
21
20
19
18
17
14
13
12
11
10
9
7
6
5
4
3
249
248
247
246
245
242
241
240
238
237
236
235
234
219
218
217
216
215
214
213
212
211
210
209
206
205
204
203
202
201
199
198
197
196
195
187
186
185
184
183
182
181
180
179
178
VPY7
VPY6
VPY5
VPY4
VPY3
VPY2
VPY1
VPY0
VPC7
VPC6
VPC5
VPC4
VPC3
VPC2
VPC1
VPC0
VA_VDD
VMD[15:0]
C202
10uF
V5_0
VIDEO CONTROLLER
103
102
101
100
97
96
95
94
93
92
91
90
89
88
87
86
D1N916
D28
D1N916
D23
D1N916
D29
D1N916
D24
D1N916
D30
D1N916
D25
+12V
D1N916
D31
D1N916
D26
Date:
Size
A4
Title
D1N916
D32
D1N916
D27
Clamped diodes acting as input port
protection
Optional :
J20
15
14
13
11
6
12
Friday, May 15, 1998
Document Number
{Doc}
POS Design Guide : Video Controller
CONNECTOR DB15HD
1
7
2
8
3
9
4
10
5
Sheet
13
of
18
Rev
1.00
VMD[31:16]
VMD[15:0]
MA[8:0]
VMD16
VMD17
VMD18
VMD19
VMD20
VMD21
VMD22
VMD23
-RAS0
-CAS1
-CAS0
-WE
-OE
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
14
28
29
13
27
16
17
18
19
22
23
24
25
26
1
6
20
21
35
40
VMD8
VMD9
VMD10
VMD11
VMD12
VMD13
VMD14
VMD15
V5_ 0
11
12
15
30
2
3
4
5
7
8
9
10
31
32
33
34
36
37
38
39
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
1
VMD0
VMD1
VMD2
VMD3
VMD4
VMD5
VMD6
VMD7
VMD8
VMD9
VMD10
VMD11
VMD12
VMD13
VMD14
VMD15
27C51 2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
U19
MA[8:0]
VMD[15:0]
Vss
OE#/VPP
CE#
D0
D1
D2
D3
D4
D5
D6
D7
Vcc
14
22
20
11
12
13
15
16
17
18
19
28
-RAS0
-CAS3
-CAS2
-WE
-OE
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
14
28
29
13
27
16
17
18
19
22
23
24
25
26
11
12
15
30
VMD[15:0]
NC
NC
NC
NC
2
3
4
5
7
8
9
10
31
32
33
34
36
37
38
39
C224
1uF
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
HYB514171BJ-60
RAS#
UCAS#
LCAS#
WE#
OE#
A0
A1
A2
A3
A4
A5
A6
A7
A8
VCC
VCC
VCC
VSS
VSS
VSS
U16
C223
1uF
-EROM
1
6
20
21
35
40
VMD0
VMD1
VMD2
VMD3
VMD4
VMD5
VMD6
VMD7
V5_0
V5_0
C222
10uF
VGA BIOS ROM
NC
NC
NC
NC
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
HYB514171BJ-60
RAS#
UCAS#
LCAS#
WE#
OE#
A0
A1
A2
A3
A4
A5
A6
A7
A8
VCC
VCC
VCC
VSS
VSS
VSS
U15
C221
10uF
VMD16
VMD17
VMD18
VMD19
VMD20
VMD21
VMD22
VMD23
VMD24
VMD25
VMD26
VMD27
VMD28
VMD29
VMD30
VMD31
C226
0.1uF
-RAS0
-CAS5
-CAS4
-WE
-OE
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
VMD[31:16]
MA[8:0]
C225
0.1uF
V5_0
14
28
29
13
27
16
17
18
19
22
23
24
25
26
1
6
20
21
35
40
C227
0.1uF
V5_ 0
NC
NC
NC
NC
11
12
15
30
2
3
4
5
7
8
9
10
31
32
33
34
36
37
38
39
C229
0.1uF
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
HYB514171BJ-60
RAS#
UCAS#
LCAS#
WE#
OE#
A0
A1
A2
A3
A4
A5
A6
A7
A8
VCC
VCC
VCC
VSS
VSS
VSS
U17
C228
0.1uF
VIDEO DRAM
VMD32
VMD33
VMD34
VMD35
VMD36
VMD37
VMD38
VMD39
VMD40
VMD41
VMD42
VMD43
VMD44
VMD45
VMD46
VMD47
C230
0.01uF
MA[8:0]
VMD[47:32]
C231
0.01uF
-RAS0
-CAS7
-CAS6
-WE
-OE
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
C232
0.01uF
V5_ 0
C233
0.01uF
14
28
29
13
27
16
17
18
19
22
23
24
25
26
1
6
20
21
35
40
NC
NC
NC
NC
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
HYB514171BJ-60
RAS#
UCAS#
LCAS#
WE#
OE#
A0
A1
A2
A3
A4
A5
A6
A7
A8
VCC
VCC
VCC
VSS
VSS
VSS
U18
11
12
15
30
2
3
4
5
7
8
9
10
31
32
33
34
36
37
38
39
VMD[63:48]
Date:
Size
A4
Title
VMD48
VMD49
VMD50
VMD51
VMD52
VMD53
VMD54
VMD55
VMD56
VMD57
VMD58
VMD59
VMD60
VMD61
VMD62
VMD63
Friday, May 15, 1998
Sheet
14
POS Design Guide : Video DRAM and VGA BIOS ROM
Document Number
{Doc}
of
18
Rev
1.00
C289
0.01uF
2
V5_0
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
LA17
LA18
LA19
LA20
LA21
LA22
LA23
C290
0.01uF
PWRGOOD
208
195
138
133
27
202
203
170
172
174
177
198
156
154
152
148
150
189
190
193
194
196
197
199
200
143
142
141
139
137
136
135
134
161
162
164
165
167
168
169
171
173
175
176
178
179
181
182
183
184
146
147
149
151
153
155
157
166
187
180
159
158
160
188
191
201
163
145
144
185
186
C291
0.01uF 31
70
79
140
111
192
3
C288
0.01uF
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
7404
U31A
C287
1uF
IRQ12
IRQ14
IRQ3
IRQ4
IRQ5
IRQ7
IRQ9
LA[23:17]
BALE
AEN
-REFRESH
-SBHE
-IOCS16
-MEMCS16
IOCHRDY
-0WS
SA[19:0]
14MHZ
-MEMR
-MEMW
-IOR
-IOW
1
GND
GND
GND
GND
GND
GND
VPP VALID*
+5V
ISA_VCC
ISA_VCC
CORE_VDD
CORE_VDD
SPKR OUT*/C_SEL
INTR*
IRQ3
IRQ4
IRQ5
IRQ7
IRQ9
IRQ10
IRQ11
IRQ12/LED_OUT*
IRQ14
IRQ15/RI_OUT*
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
LA17
LA18
LA19
LA20
LA21
LA22
LA23
ALE
AEN
REFRESH*
SBHE*
IOCS16*
MEMCS16*
IOCHRDY
ZWS*
PWRGOOD
CLK
MEMR*
MEMW*
IOR*
IOW*
B WP/IOIS16*
B INPACK*
B WAIT*
B REG*
B RDY/IREQ*
BD15
BD14
BD13
BD12
BD11
BD10
BD9
BD8
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
B CD1*
B CD2*
B GPSTB
B VCC 3*
B VCC 5*
B RESET
B VPP PGM
B VPP VCC
B SOCKET VCC
B SOCKET VCC
B BVD1/STSCHG*/RI*
B BVD2/ SPKR*/LED*
B OE*
B WE*
B IORD*
B IOWR*
B CE1*
B CE2*
A WP/IOIS16*
A INPACK*
A WAIT*
A REG*
A RDY/IREQ*
A BVD1/STSCHG*/RI*
A BVD2/SPKR*/LED*
A OE*
A WE*
A IORD*
A IOWR*
A CE1*
A CE2*
A CD1*
A CD2*
A GPSTB
A VCC 3*
A VCC 5*
A RESET
A VPP PGM
A VPP VCC
A SOCKET VCC
A SOCKET VCC
131
119
116
71
101
84
82
80
77
75
130
128
126
81
78
76
74
72
129
127
125
V3_3
A WP/-IOIS16
-A INPACK
-A WAIT
-A REG
A RDY/-IREQ
68
56
54
8
39
73
132
7 B GPSTB
206
207
114
204
V5_0
205
88
+12V
117
124
122
87
0.1uF
99
90
C282
92
83
86
A SOCKET VCC
A BVD1/-STSCHG/-RI
A BVD2/-SPKR/-LED
-A OE
-A WE
-A IORD
-A IOWR
-A CE1
-A CE2
61
59
23
37
26
29
19
22
-ACD1
-ACD2
A GPSTB
-A VCC 3
-A VCC 5
A RESET
A VPP PGM
A VPP VCC
10
69
6
4
5
51
1
2
24
52
PCM_D0
PCM_D1
PCM_D2
PCM_D3
PCM_D4
PCM_D5
PCM_D6
PCM_D7
PCM_D8
PCM_D9
PCM_D10
PCM_D11
PCM_D12
PCM_D13
PCM_D14
PCM_D15
62
64
66
9
11
13
15
17
63
65
67
12
14
16
18
20
U32
CL-PD6720
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AA25
AA24
AA23
AA22
AA21
AA20
AA19
AA18
AA17
AA16
AA15
AA14
AA13
AA12
AA11
AA10
AA9
AA8
AA7
AA6
AA5
AA4
AA3
AA2
AA1
AA0
SD[15:0]
RSTDRV
AA0
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
48
46
44
42
40
38
36
34
32
41
43
35
33
45
25
21
28
30
47
49
50
53
55
57
58
60
BA25
BA24
BA23
BA22
BA21
BA20
BA19
BA18
BA17
BA16
BA15
BA14
BA13
BA12
BA11
BA10
BA9
BA8
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
110
108
106
104
102
100
98
96
94
103
105
97
95
107
89
85
91
93
109
112
113
115
118
120
121
123
C283
0.1uF
V5_0
5
2
15
14
9
7
8
4
3
6
VPPIN
5VIN
3VIN
3VIN
VDD
VPPEN0
VPPEN1
VCCEN0
VCCEN1
SHDN
C284
LTC1472
1uF
A VPP VCC
A VPP PGM
-A VCC 3
-A VCC 5
PCM_D[15:0]
AA[25:0]
U33
GND
GND
VPP_OUT
VCCIN
VCC_OUT
VCC_OUT
10
13
11
12
1
16
C280
0.1uF
C281
CAP
VPP_OUT
Date:
Size
A4
Title
43
57
9
15
44
45
33
60
16
59
36
67
7
42
58
63
62
61
30
31
32
2
3
4
5
6
64
65
66
37
38
39
40
41
29
28
27
26
25
24
23
22
12
11
8
10
21
13
14
20
19
46
47
48
49
50
53
54
55
56
PCMCIA Connector
VCC
VCC
VPP2
VPP1
GND
GND
GND
GND
VS1*
VS2*
OE*
WE*/PGM*
IORD*
IOWR*
WP/IOCS16
INPACK*
RDY/BSY*
WAIT*
CD1*
CD2*
CE1*
CE2*
RESET
BVD1/STSCHD*
BVD2/SPKR
REG*
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
J26
Friday, May 15, 1998
Document Number
{Doc}
POS Design Guide : PCMCIA Connector
A SOCKET VCC 17
51
52
VPP_OUT
18
68
1
34
35
A GPSTB
B GTSTB
-A OE
-A WE
-A IORD
-A IOWR
A WP/-IOIS16
-A INPACK
A RDY/-IREQ
-A WAIT
-ACD1
-ACD2
-A CE1
-A CE2
A RESET
A BVD1/-SCSCHG/-RI
A BVD2/-SPKR/-LED
-A REG
PCM_D0
PCM_D1
PCM_D2
PCM_D3
PCM_D4
PCM_D5
PCM_D6
PCM_D7
PCM_D8
PCM_D9
PCM_D10
PCM_D11
PCM_D12
PCM_D13
PCM_D14
PCM_D15
AA0
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
Sheet
15
of
18
Rev
1.00
SD[15:0]
R80
4.7K
IP_GND
PORTCLK1
2
8
14
LA23
LA22
LA21
LA20
LA19
3
4
5
6
7
9
10
11
12
13
16
OP
OP
OP
OP
OP
OP
OP
OP
OP
OP
VCC
SDI
SDO
To Parallel Port
U36
Socket2
PORTMODE
ispGAL22V10
SCLK
I/CLK
MODE
GND
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
IP
U22
SDO
28
15
22
17
18
19
20
21
23
24
25
26
27
SDI
V5_0
-FLSH_CE
RP#
-MEMCS16#
8
7
6
5
4
3
2
1
IOCHRDY
-MEMW
SYSCLK
RSTDRV
BALE
SUPERIO_GPIO24
SUPERIO_GPIO25
SUPERIO_GPIO26
SUPERIO_GPIO27
6
LA[23:17]
-SBHE
SA0
-MEMCS16
SA[19:0]
APPFLSH_SA19
APPFLSH_SA20
APPFLSH_SA21
APPFLSH_WP#
U9C
74ACT05
-MEMR
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
C234
1uF
V5_0
R84
4.7k
-FLSH_WP
C235
0.1uF
V5_0
36
55
20
21
37
51
50
49
48
47
46
45
43
52
53
54
2
3
4
5
13
12
11
10
9
8
23
1
7
22
5
8
7
6
5
4
3
2
1
28F320S5
BYTE#
RP#
STS
WE#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
WP#
CE0#
CE1#
OE#
U23
C236
0.1uF
C237
0.01uF
15
29
44
14
28
42
56
6
34
35
38
40
33
31
27
25
16
18
39
41
32
30
26
24
17
19
Date:
C238
CAP
2
J27
JUMP3
Thursday, May 14, 1998
Document Number
{Doc}
Sheet
16
of
POS DESIGN GUIDE: Application Flash
V5_0
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
1
Size
A4
Title
GND
GND
GND
VCC
VCC
VCC
VPP
NC
NC
NC
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
APPLICATION FLASH
3
18
Rev
1.00
SA8
SA4
13
12
12
13
7400
U45D
7421
9 U46B
10
11
8
10
9
LGC2
4
5
8
6
LGC7
LGC3
3
5
4
2
1
7404
U31B
7400
U45B
7400
U45A
4
V5_0
6
3
LGC6
4.7k
R70
C4CS
-IOW
-IOR
9
61
43
4
39
SYSCLK
1
44
32
3
38
36
37
35
34
33
14
15
16
17
18
19
20
21
45
60
59
SA0
SA1
SA2
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
IRQ4
IRQ3
PULL-UP
LGC5
C3CS
LGC4
SA[19:0]
SD[15:0]
NC
NC
INTSEL*
CLK
RESET*
INTA
INTB
INTP*
BIDEN
RDOUT
CSA*
CSB*
CSP*
IOW*
IOR*
A0
A1
A2
D0
D1
D2
D3
D4
D5
D6
D7
V5_0
SLCT
PE
BUSY
ACK*
ERROR*
TXB
RXB
DTRB*
RTSB*
CTSB*
DSRB*
CDB*
RIB*
TXA
RXA
DTRA*
RTSA*
CTSA*
DSRA*
CDA*
RIA*
.1uF
C243
TX3
RX3
DTR3
RTS3
CTS3
DSR3
CD3
RI3
10
62
11
12
13
5
8
6
46
47
48
49
50
51
52
53
58
57
56
55
65
67
66
68
63
TX2
RX2
DTR2
RTS2
CTS2
DSR2
CD2
RI2
26
41
25
24
28
31
29
30
C240
0.1uF
C241
0.1uF
C242
0.01uF
20
19
18
17
16
15
14
13
12
11
20
19
18
17
16
15
14
13
12
11
GD75232SOP
V5_0 +12V
RY1
RA1
RY2
RA2
RY3
RA3
DA1
DY1
DA2
DY2
RY4
RA4
DA3
DY3
RY5
RA5
GND -12V
U29
GD75232SOP
V5_0 +12V
RY1
RA1
RY2
RA2
RY3
RA3
DA1
DY1
DA2
DY2
RY4
RA4
DA3
DY3
RY5
RA5
GND -12V
U27
GND
GND
GND
GND
-12V
+12V
-12V
54
27
7
2
Date:
Size
A4
Title
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
+12V
D33
D34
D44
1N914
D49
1N914
D35
1N914
D50
1N914
D45
1N914
D40
1N914
D36
1N914
D51
1N914
D46
1N914
D41
1N914
D37
1N914
D52
1N914
D47
1N914
D42
1N914
Friday, May 15, 1998
Document Number
{Doc}
Sheet
17
POS Design Guide : Serial communication s
-12V
1N914
D48
1N914
D43
+12V
-12V
D39
1N914
D38
1N914
1N914
1N914
+12V
of
ACD3
ADSR3
ARX3
ARTS3
ATX3
ACTS3
ADTR3
ARI3
ACD2
ADSR2
ARX2
ARTS2
ATX2
ACTS2
ADTR2
ARI2
18
1
6
2
7
3
8
4
9
5
1
6
2
7
3
8
4
9
5
P1
DB9
1.00
Rev
P2
DB9
11
10
U28
ST16C452
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
SLCTIN*
INIT
AUTOFDXT*
STROBE*
VCC
VCC
VCC
RSTDRV
7400
U45C
7421
1 U46A
2
LGC1
64
40
23
SA9
SA6
SA7
SA3
SA5
C239
1uF
V5_0
ADDITIONAL COMMUNICATION PORTS
11
10
V5_0
1
2
2
2
C271
10uF
C268
0.01uF
C275
100uF
C276
100uF
Supply for
display memory
MVDD
C277
0.1uF
V5_0
C278
100uF
C279
100uF
Vr=2.7v
13
D56
BZX84C2V7
J24
1
1x3
3
V-
R79
1K
V5_0
TLC393C
1
U30A
1uF
C258
1x4
1
2
3
4
JP2
Date:
Size
A4
Title
C252
470pF
Optional
RESET SWITCH
S1
R75
110
VIN_C
C264
10uF
V2_9OK
PS_OK
13
12
C273
1000pF
Wednesday, May 13, 1998
Document Number
{Doc}
POS Design Guide : Power
V5_0
74ALS00
U8D
11
74HCT14
U4B
4
Sheet
18
of
18
Rev
1.00
PWOK 5
FAN HEADER
1x3
1
2
3
J25
SCHMITT
3
PS_OK = OR of PW_OK,-DBRESET,RESET SWITCH
PWOK = V2_9OK AND PS_OK
PS_OK comes up before V2_9 off Mohave so AND
these to generate system power ok to PIIX3
(PWOK)
-
+
4
SPEAKER HEADER
5 SPKR
1-2 Mohave 2.9V
Vr=2.4v
D57
BZX84C2V4
2
3
Note :
.
For EMDMOD133, use D10 which is 2.7V.
For EMBMOD166, use D11 which is 2.3V.
MVDD
DACVDD
3 V2_9
MAVDD 13
2
C274
0.1uF
V3_3
C270
0.1uF
C267
0.01uF
Supply for
RAMDAC
Supply for
memory and
video clock
Place at ATX Connector
C269
0.1uF
PLACE CLOSE TO PIN 8/227/200 OF CL-GD7555
Place at ATX Connector
C272
0.1uF
CB70
1
C266
0.1uF
C265
1uF
C261
0.1uF
V5_0
10K
R78
4
PLACE CLOSE TO PIN 109 OF CL-GD7555
C263
10uF
C260
0.1uF
C259
22uF
74ACT05
U9B
Open Collector
8
1
FB8
2
V5_0
R76
4.7K
3
3
CB70
2
C257
4.7nF
3 DBRESET
NC
1
FB7
C256
10uF
C251
470pF
D55
LGS260-DO
V2_9
IN
C262
0.1uF
1
PLACE CLOSE TO PIN 250 OF CL-GD7555
Note Cap Direction
3
Place single point
connection at ATX
Connector
R77
10K
OUT
C255
100uF
NC
C254
100uF
IN
C253
0.1uF
V5_0
3
Place at ATX Connector
-5V
NC
Note: Add screen marking for V5_0 LED, V3_3 LED, V2_9 LED
C250
470pF
IN
ATX POW CONN
PW_OK
C249
100uF
OUT
J23
1x2
C248
100uF
D54
LGS260-DO
VIN_B
R74
130
OUT
PS_ON
C247
0.1uF
D53
LGS260-DO
1
1
2
3
4
5
6
7
8
9
10
+12V
2
V3_3
V3_3
GND
V5_0
GND
V5_0
GND
PW_OK
5VSB
+12V
Place at ATX Connector
VIN_A
1
V3_3
-12V
GND
PS_ON
GND
GND
GND
-5V
V5_0
V5_0
J22
C246
100uF
R73
215
V3_3
2
Note Cap Direction
C245
100uF
-12V
Power Indicators
1
11
12
13
14
15
16
17
18
19
20
C244
0.1uF
Place at ATX Connector
V5_0
2
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