User's Guide conga-CA6
COM Express™ conga-CA6
Intel® Atom™ processor E6x0/E6x0T series with an Intel® Platform Controller Hub EG20T
User’s Guide
Revision 1.0
Revision History
Revision
Date (yyyy.mm.dd)
Author
Changes
0.1
0.2
2012.05.22
2013.07.17
GDA
AEM
•
•
•
•
0.3
2013.09.26
AEM
•
•
•
•
•
Preliminary release
Added section 1 “Introduction”. Moved COM Express™ Concept and Options Information to section 1 “Introduction”.
Updated section 2.5 “Power Consumption”.
Deleted RTC alarm option and the option to use USB Mouse/Keyboard Event as Wake event in section 7.3 “ACPI Suspend Modes and
Resume Events” because these are not supported in the BIOS.
Updated section 10 “BIOS Description Setup”.
Deleted conga-CA6 variants that are no longer available in sections 1 “Introduction” and 2.5 “Power Consumption”.
Updated section 2.5 “Power Consumption”. Added CMOS battery current in section 2.6.1 “CMOS Battery Power Consumption”. Updated
the block diagram in section 3 “Block diagram”.
Deleted section 6.4 “Security Features” because the conga-CA6 does not support TPM.
Official release.
Copyright © 2012 congatec AG CTOPm10 2/85
Preface
This user’s guide provides information about the components, features, connectors and BIOS Setup menus available on the conga-CA6. It is
one of three documents that should be referred to when designing a COM Express™ application. The other reference documents that should
be used include the following:
COM Express™ Design Guide
COM Express™ Specification
The links to these documents can be found on the congatec AG website at www.congatec.com
Disclaimer
The information contained within this user’s guide, including but not limited to any product specification, is subject to change without notice.
congatec AG provides no warranty with regard to this user’s guide or any other information contained herein and hereby expressly disclaims
any implied warranties of merchantability or fitness for any particular purpose with regard to any of the foregoing. congatec AG assumes
no liability for any damages incurred directly or indirectly from any technical or typographical errors or omissions contained herein or for
discrepancies between the product and the user’s guide. In no event shall congatec AG be liable for any incidental, consequential, special, or
exemplary damages, whether based on tort, contract or otherwise, arising out of or in connection with this user’s guide or any other information
contained herein or the use thereof.
Intended Audience
This user’s guide is intended for technically qualified personnel. It is not intended for general audiences.
Lead-Free Designs (RoHS)
All congatec AG designs are created from lead‑free components and are completely RoHS compliant.
Electrostatic Sensitive Device
All congatec AG products are electrostatic sensitive devices and are packaged accordingly. Do not open or handle a congatec AG product
except at an electrostatic‑free workstation. Additionally, do not ship or store congatec AG products near strong electrostatic, electromagnetic,
magnetic, or radioactive fields unless the device is contained within its original manufacturer’s packaging. Be aware that failure to comply with
these guidelines will void the congatec AG Limited Warranty.
Copyright © 2012 congatec AG CTOPm10 3/85
Symbols
The following symbols are used in this user’s guide:
Warning
Warnings indicate conditions that, if not observed, can cause personal injury.
Caution
Cautions warn the user about how to prevent damage to hardware or loss of data.
Note
Notes call attention to important information that should be observed.
Trademarks
Product names, logos, brands, and other trademarks featured or referred to within this user’s guide, or the congatec website, are the property
of their respective trademark holders. These trademark holders are not affiliated with congatec AG, our products, or our website.
Copyright Notice
Copyright © 2012, congatec AG. All rights reserved. All text, pictures and graphics are protected by copyrights. No copying is permitted without
written permission from congatec AG.
congatec AG has made every attempt to ensure that the information in this document is accurate yet the information contained within is
supplied “as-is”.
Copyright © 2012 congatec AG CTOPm10 4/85
Warranty
congatec AG makes no representation, warranty or guaranty, express or implied regarding the products except its standard form of limited
warranty (“Limited Warranty”). congatec AG may in its sole discretion modify its Limited Warranty at any time and from time to time.
Beginning on the date of shipment to its direct customer and continuing for the published warranty period, congatec AG represents that the
products are new and warrants that each product failing to function properly under normal use, due to a defect in materials or workmanship or
due to non conformance to the agreed upon specifications, will be repaired or exchanged, at congatec AG’s option and expense.
Customer will obtain a Return Material Authorization (“RMA”) number from congatec AG prior to returning the non conforming product freight
prepaid. congatec AG will pay for transporting the repaired or exchanged product to the customer.
Repaired, replaced or exchanged product will be warranted for the repair warranty period in effect as of the date the repaired, exchanged or
replaced product is shipped by congatec AG, or the remainder of the original warranty, whichever is longer. This Limited Warranty extends to
congatec AG’s direct customer only and is not assignable or transferable.
Except as set forth in writing in the Limited Warranty, congatec AG makes no performance representations, warranties, or guarantees, either
express or implied, oral or written, with respect to the products, including without limitation any implied warranty (a) of merchantability, (b) of
fitness for a particular purpose, or (c) arising from course of performance, course of dealing, or usage of trade.
congatec AG shall in no event be liable to the end user for collateral or consequential damages of any kind. congatec AG shall not otherwise
be liable for loss, damage or expense directly or indirectly arising from the use of the product or from any other cause. The sole and exclusive
remedy against congatec AG, whether a claim sound in contract, warranty, tort or any other legal theory, shall be repair or replacement of the
product only
Certification
congatec AG is certified to DIN EN ISO 9001 standard.
ISO 9001
C
ER
T I F I C AT I O
N
TM
Technical Support
congatec AG technicians and engineers are committed to providing the best possible technical support for our customers so that our products
can be easily used and implemented. We request that you first visit our website at www.congatec.com for the latest documentation, utilities and
drivers, which have been made available to assist you. If you still require assistance after visiting our website then contact our technical support
department by email at [email protected]
Copyright © 2012 congatec AG CTOPm10 5/85
Terminology
Term
Description
GB
GHz
kB
MB
Mbit
kHz
MHz
TDP
PCIe
SATA
PEG
PCH
PATA
HDA
APU
FCH
DDI
DP
I/F
N.C.
N.A.
TBD
Gigabyte (1,073,741,824 bytes)
Gigahertz (one billion hertz)
Kilobyte (1024 bytes)
Megabyte (1,048,576 bytes)
Megabit (1,048,576 bits)
Kilohertz (one thousand hertz)
Megahertz (one million hertz)
Thermal Design Power
PCI Express
Serial ATA
PCI Express Graphics
Platform Controller Hub
Parallel ATA
High Definition Audio
Accelerated Processor Unit
Fusion Controller Hub
Digital Display Interface
DisplayPort
Interface
Not connected
Not available
To be determined
Copyright © 2012 congatec AG CTOPm10 6/85
Contents
1Introduction............................................................................... 10
2
Specifications............................................................................ 12
2.1
Feature List............................................................................... 12
2.2
Supported Operating Systems.................................................. 13
2.3
Mechanical Dimensions............................................................ 13
2.4
Supply Voltage Standard Power............................................... 14
2.4.1
Electrical Characteristics........................................................... 14
2.4.2
Rise Time.................................................................................. 14
2.5
Power Consumption.................................................................. 15
2.5.1Intel® Atom™ E680 1.6 GHz 512kB L2 cache ......................... 16
2.5.2Intel® Atom™ E680T 1.6 GHz 512kB L2 cache ....................... 16
2.5.3Intel® Atom™ E640 1.0 GHz 512kB L2 cache.......................... 16
2.5.4Intel® Atom™ E640T 1.0 GHz 512kB L2 cache........................ 17
2.6
Supply Voltage Battery Power.................................................. 17
2.6.1
CMOS Battery Power Consumption......................................... 17
2.7
Environmental Specifications.................................................... 18
3
Block Diagram........................................................................... 19
4Heatspreader............................................................................ 20
4.1
Heatspreader Dimensions........................................................ 21
5
Connector Subsystems Rows A, B, C, D.................................. 22
5.1
Primary Connector Rows A and B............................................. 23
5.1.1
Serial ATA™ (SATA).................................................................. 23
5.1.2
USB 2.0..................................................................................... 23
5.1.3
High Definition Audio (HDA) Interface....................................... 23
5.1.4
Gigabit Ethernet ....................................................................... 23
5.1.5
LPC Bus.................................................................................... 24
5.1.6
I²C Bus...................................................................................... 24
5.1.7
PCI Express™.......................................................................... 24
5.1.8ExpressCard™.......................................................................... 24
5.1.9
Graphics Output (VGA/CRT).................................................... 25
5.1.10LCD........................................................................................... 25
5.1.11TV-Out....................................................................................... 25
5.1.12
Power Control........................................................................... 25
5.1.13
Power Management.................................................................. 26
5.2
Secondary Connector Rows C and D....................................... 27
5.2.1
PCI Express Graphics (PEG).................................................... 27
5.2.2SDVO........................................................................................ 27
5.2.3HDMI......................................................................................... 28
5.2.4
DisplayPort (DP)....................................................................... 28
5.2.5
PCI Bus..................................................................................... 28
5.2.6
IDE (PATA)................................................................................ 28
6
Additional Features................................................................... 29
6.1Watchdog.................................................................................. 29
6.2
Onboard Microcontroller........................................................... 29
6.3
Embedded BIOS....................................................................... 29
6.4
Suspend to Ram....................................................................... 30
6.5
congatec Battery Management Interface.................................. 30
7
conga Tech Notes..................................................................... 31
7.1Intel® Processor Features......................................................... 31
7.1.1
Thermal Monitor and Catastrophic Thermal Protection............ 31
7.1.2
Processor Performance Control................................................ 32
7.1.3Intel® Virtualization Technology................................................. 32
7.2
Thermal Management............................................................... 33
7.3
ACPI Suspend Modes and Resume Events............................. 34
7.4
USB Port Connections.............................................................. 35
7.4.1
USB Client Controller................................................................ 36
8
Signal Descriptions and Pinout Tables...................................... 37
8.1
8.2
8.3
8.4
8.5
A-B Connector Signal Descriptions........................................... 38
A-B Connector Pinout............................................................... 47
C-D Connector Signal Descriptions.......................................... 49
C-D Connector Pinout............................................................... 59
Bootstrap Signals...................................................................... 61
9
System Resources.................................................................... 62
9.1
9.2
I/O Address Assignment............................................................ 62
Interrupt Request (IRQ) Lines................................................... 62
Copyright © 2012 congatec AG CTOPm10 7/85
9.3
9.4
9.5
9.6
PCI Configuration Space Map.................................................. 64
PCI Interrupt Routing Map........................................................ 65
I²C Bus...................................................................................... 66
SM Bus..................................................................................... 66
10
BIOS Setup Description............................................................ 67
10.1
10.1.1
10.2
10.3
10.4
10.5
10.5.1
10.5.2
10.5.3
10.5.4
10.5.5
10.5.6
10.5.7
10.5.8
10.5.9
10.5.9.1
10.5.10
10.5.11
10.5.12
10.5.13
10.5.13.1
10.5.14
10.5.14.1
10.6
10.6.1
10.7
10.7.1
10.8
10.8.1
Entering the BIOS Setup Program............................................ 67
Boot Selection Popup............................................................... 67
Setup Menu and Navigation...................................................... 67
Main Setup Screen................................................................... 68
Platform Information submenu.................................................. 69
Advanced Setup........................................................................ 69
Graphics Configuration Submenu............................................. 70
Watchdog Configuration Submenu........................................... 71
PCI Subsystem Settings Submenu........................................... 72
PCI Express Ports 1-4 Configuration Submenu........................ 73
PIRQ Routing Submenu........................................................... 73
PCI to PCI Bridge Submenu..................................................... 74
ACPI Configuration Submenu................................................... 74
CPU Configuration Submenu.................................................... 76
Chipset Configuration Submenu............................................... 77
Network Settings Submenu...................................................... 77
AHCI SATA Configuration......................................................... 78
SDIO Configuration Submenu.................................................. 78
USB Configuration Submenu.................................................... 78
Super I/O Winbond Configuration Submenu............................. 79
Serial Port 0/1 Configuration Submenu.................................... 79
Serial Port Console Redirection................................................ 80
Console Redirection Settings.................................................... 80
Boot Setup................................................................................ 81
Boot Settings Configuration Submenu...................................... 81
Security Setup........................................................................... 82
Security Settings....................................................................... 82
Save & Exit............................................................................... 83
Save & Exit Menu..................................................................... 83
11
Additional BIOS Features......................................................... 84
11.1
11.2
Updating the BIOS.................................................................... 84
BIOS Security Features............................................................ 84
12
Industry Specifications.............................................................. 85
Copyright © 2012 congatec AG CTOPm10 8/85
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Feature Summary..................................................................... 12
Display Resolutions.................................................................. 27
Signal Tables Terminology Descriptions................................... 37
Intel® High Definition Audio Link Signals Descriptions.............. 38
Gigabit Ethernet Signal Descriptions........................................ 39
Serial ATA Signal Descriptions.................................................. 40
PCI Express Signal Descriptions (general purpose)................. 41
ExpressCard Support Pins Descriptions................................... 41
LPC Signal Descriptions........................................................... 42
USB Signal Descriptions........................................................... 42
CRT Signal Descriptions........................................................... 43
LVDS Signal Descriptions......................................................... 43
SPI BIOS Flash Interface Signal Descriptions.......................... 44
Miscellaneous Signal Descriptions........................................... 44
General Purpose I/O Signal Descriptions................................. 44
Power and System Management Signal Descriptions.............. 45
Power and GND Signal Descriptions........................................ 46
Connector A-B Pinout............................................................... 47
PCI Signal Descriptions............................................................ 49
IDE Signal Descriptions............................................................ 51
PCI Express Signal Descriptions (x16 Graphics)...................... 52
SDVO Signal Descriptions........................................................ 54
HDMI Signal Descriptions......................................................... 55
DisplayPort (DP) Signal Descriptions....................................... 56
Module Type Definition Signal Description............................... 57
Power and GND Signal Descriptions........................................ 57
Miscellaneous Signal Descriptions........................................... 58
Connector C-D Pinout............................................................... 59
Bootstrap Signal Descriptions................................................... 61
IRQ Lines in PIC mode............................................................. 62
IRQ Lines in APIC mode........................................................... 63
PCI Configuration Space Map.................................................. 64
PCI Interrupt Routing Map........................................................ 65
PCI Interrupt Routing Map (continued)..................................... 65
Copyright © 2012 congatec AG CTOPm10 9/85
1
Introduction
COM Express™ Concept
COM Express™ is an open industry standard defined specifically for COMs (computer on modules). Its creation provides the ability to make a
smooth transition from legacy parallel interfaces to the newest technologies based on serial buses available today. COM Express™ modules
are available in the following form factors:
• Compact
• Basic
• Extended
95mm x 95mm
125mm x 95mm
155mm x 110mm
The COM Express™ specification 2.0 defines five different pinout types.
Types
Connector Rows
PCI Express Lanes
Type 1
A-B
Up to 6
PCI
IDE Channels
LAN ports
Type 2
Type 3
A-B C-D
A-B C-D
Up to 22
Up to 22
Type 4
A-B C-D
Up to 32
Type 5
A-B C-D
Up to 32
3
Type 6
A-B C-D
Up to 24
1
Type 10
A-B
Up to 4
1
1
32 bit
32 bit
1
1
3
1
1
The conga-CA6 modules use the COM Express™ Type 2, Rev 2.0 pinout definition. They are equipped with two high performance connectors
that ensure stable data throughput.
The COM (computer on module) integrates all the core components and is mounted onto an application specific carrier board. COM modules
are a legacy-free design (no Super I/O, PS/2 keyboard and mouse) and provide most of the functional requirements for any application. These
functions include, but are not limited to, a rich complement of contemporary high bandwidth serial interfaces such as PCI Express, Serial ATA,
USB 2.0, and Gigabit Ethernet. The Type 2 pinout provides the ability to offer 32-bit PCI, Parallel ATA, and LPC options thereby expanding
the range of potential peripherals. The robust thermal and mechanical concept, combined with extended power-management capabilities, is
perfectly suited for all applications.
Carrier board designers can utilize as little or as many of the I/O interfaces as deemed necessary. The carrier board can therefore provide all
the interface connectors required to attach the system to the application specific peripherals. This versatility allows the designer to create a
dense and optimized package, which results in a more reliable product while simplifying system integration. Most importantly, COM Express™
modules are scalable, which means once an application has been created there is the ability to diversify the product range through the use
of different performance class or form factor size modules. Simply unplug one module and replace it with another- no redesign is necessary.
Copyright © 2012 congatec AG CTOPm10 10/85
conga-CA6 Options Information
The conga-CA6 currently offers four variants. This user’s guide describes all of the available features these variants offer. Below you will find
an order table showing the base configuration modules that are currently offered by congatec AG. For more information about the conga-CA6
variants offered by congatec, contact your local congatec sales representative or visit the congatec website at www.congatec.com.
conga-CA6
Part-No.
061203
061201
061213
061211
Processor
Intel® Atom™
E680 1.6 GHz
512kB
1GB DDR2 (800 MT/s)
2
Yes
No
3.9 W
Intel® Atom™
E640 1.0 GHz
512kB
1GB DDR2 (667 MT/s)
2
Yes
No
3.6 W
Intel® Atom™
E680T 1.6 GHz
512kB
1GB DDR2 (800 MT/s)
2
Yes
No
3.9 W
Intel® Atom™
E640T 1.0 GHz
512kB
1GB DDR2 (667 MT/s)
2
Yes
No
3.6 W
L2 Cache
Onboard Memory up to 2GB
External PCI Express Lane(s)
Gigabit Ethernet
Onboard Solid-State Drive (SSD)
CPU TDP
Copyright © 2012 congatec AG CTOPm10 11/85
2
Specifications
2.1
Feature List
Table 1
Feature Summary
Based on COM Express™ standard pinout Type 2 Rev. 2.0 (compact size 95 x 95mm)
Intel® Atom™ E680 1.6 GHz with 512kB L2 cache
Intel® Atom™ E640 1.0 GHz with 512kB L2 cache
Intel® Atom™ E680T 1.6 GHz with 512kB L2 cache (industrial grade processor)
Intel® Atom™ E640T 1.0 GHz with 512kB L2 cache (industrial grade processor)
Onboard DDR 2 up to 2GB
Memory
Intel® Platform Controller Hub (PCH) EG20T
Chipset
HDA (High Definition Audio)/digital audio interface with support for multiple codecs
Audio
Gigabit Ethernet, Micrel KSZ9021RN (commercial temp.) or KSZ9021RNI (industrial temp.) and Phy
Ethernet
Integrated 3D graphics engine. Dual independent display support.
Graphics Options
• Flat panel Interface (integrated) 80 MHz LVDS Transmitter
• Video Decode Acceleration:
Supports 1x18 and 1x24 bit TFT configurations.
MPEG2
Automatic Panel Detection via EPI (Embedded Panel Interface based on VESA
MPEG4
EDID™ 1.3) Resolutions 640x480 up to 1280x768.
H.264
• AUX Output 1 x Intel compliant SDVO port (serial DVO). Resolutions up to
WMV9/VC1
1280x1024 @ 85 Hz. Supports external DVI, TV and LVDS transmitters
• 4x Serial ATA®
• PCI Bus Rev. 2.3
Peripheral
• 2x x1 PCI Express Lanes (revision 1.1 (2.5Gbps) compliant)
• 1x EIDE (UDMA-66/100) optional
Interfaces
• 6x USB 2.0 (EHCI)
• I²C Bus, Fast Mode (400 kHz) multimaster
• LPC Bus
• SM Bus
Optionally equipped with a Solid State Drive (SSD) up to 32 GByte in capacity
Onboard Storage
AMI Aptio® UEFI 2.x firmware, 4MByte serial SPI with congatec Embedded BIOS features
BIOS
Power Management ACPI 3.0 compliant with battery support. Also supports Suspend to RAM (S3).
Form Factor
Processor
Note
Some of the features mentioned in the above Feature Summary are optional. Check the article number of your module and compare it to the
option information list on page 11 of this user’s guide to determine what options are available on your particular module.
Copyright © 2012 congatec AG CTOPm10 12/85
2.2
Supported Operating Systems
The conga-CA6 supports the following operating systems.
• Microsoft® Windows® 7
• Microsoft® Windows® Embedded Standard 7
• Microsoft® Windows® XP
• Microsoft® Windows® XP Embedded
• Microsoft® Windows® Embedded Compact 7
• Microsoft® Windows® CE 6.0
• Linux
• QNX
Note
DOS is not officially supported by the Intel® Queensbay platform (E6x0 series processors and EG20T Platform Controller Hub (PCH)). As a
result, some legacy DOS based applications may not function properly when used in conjunction with the conga-CA6. This limitation is because
the EG20T PCH architecture is not designed for legacy applications.
2.3
Mechanical Dimensions
• 95.0 mm x 95.0 mm @ (3.75” x 3.75”)
• Height approximately 18 or 21mm (including heatspreader) depending on the carrier board connector that is used. If the 5mm (height) carrier
board connector is used then approximate overall height is 18mm. If the 8mm (height) carrier board connector is used then approximate
overall height is 21mm.
Copyright © 2012 congatec AG CTOPm10 13/85
2.4
Supply Voltage Standard Power
• 12V DC ± 5%
The dynamic range shall not exceed the static range.
12.60V
Absolute Maximum
Dynamic Range
12.10V
12V
Nominal
Static Range
11.90V
11.40V
2.4.1
Absolute Minimum
Electrical Characteristics
Power supply pins on the module’s connectors limit the amount of input power. The following table provides an overview of the limitations for
pinout Type 2 (dual connector, 440 pins).
Power Rail
2.4.2
Module Pin Current Nominal Input Input Range Derated Input Max. Input Ripple Max. Module Input Power Assumed
Max. Load
Capability (Amps) (Volts)
(Volts)
(Volts)
(10Hz to 20MHz) (w. derated input)
Conversion Power
(mV)
(Watts)
Efficiency (Watts)
VCC_12V
16.5
VCC_5V-SBY 2
12
5
11.4-12.6
4.75-5.25
VCC_RTC
3
2.0-3.3
0.5
11.4
4.75
+/- 100
+/- 50
137
9
85%
116
+/- 20
Rise Time
The input voltages shall rise from 10% of nominal to 90% of nominal at a minimum slope of 250V/s. The smooth turn-on requires that, during
the 10% to 90% portion of the rise time, the slope of the turn-on waveform must be positive.
Copyright © 2012 congatec AG CTOPm10 14/85
2.5
Power Consumption
The power consumption values listed in this document were measured under a controlled environment. The hardware used includes a
conga‑CA6 module, conga-CEVAL and conga-Cdebug carrier boards, CRT monitor, SATA drive, and USB keyboard. The conga-Cdebug is
modified so that the 12V input is only routed to the module and all other circuity on the carrier itself is powered by the 5V input. The SATA drive
was powered externally by an ATX power supply so that it does not influence the power consumption value that is measured for the module.
The USB keyboard was detached once the module was configured within the OS. All recorded values were averaged over a 30 second time
period. Cooling of the module was done by the module specific heatspreader and a fan cooled heatsink to measure the power consumption
under normal thermal conditions.
The conga-Cdebug originally does not provide 5V standby power. Therefore, an extra 5V_SB connection without any external loads was made.
Using this setup, the power consumption of the module in S3 (Standby) mode was measured directly.
Each module was measured while running 32 bit Windows 7 Professional and Power Plan set to “Power Saver”. This setting ensures that
Core™ processors run in LFM (lowest frequency mode) with minimal core voltage during desktop idle.
To measure the worst case power consumption the cooling solution was removed and the CPU core temperature was allowed to run up to
between 95° and 100°C while running 100% workload with the Power Plan set to “Balanced”. The peak current value was then recorded. This
value should be taken into consideration when designing the system’s power supply to ensure that the power supply is sufficient during worst
case scenarios.
Power consumption values were recorded during the following stages:
Windows 7 (32 bit)
• Desktop Idle (power plan = Power Saver)
• 100% CPU workload (see note below, power plan = Power Saver)
• 100% CPU workload at approximately 100°C peak power consumption (power plan = Balanced)
• Suspend to RAM. Supply power for S3 mode is 5V.
Note
A software tool was used to stress the CPU to Max Frequency.
Copyright © 2012 congatec AG CTOPm10 15/85
2.5.1
Intel® Atom™ E680 1.6 GHz 512kB L2 cache
With 1GB onboard memory
Intel® Atom™ E680/E680T 1.6 GHz 512kB L2 cache
45nm
Layout Rev. QTOPLA1 /BIOS Rev. QTOPR002
conga-CA6/E680-1G Art. No. 061203
Memory Size
Operating System
Power State
Power consumption (measured in Amperes/Watts)
2.5.2
1GB onboard
Windows 7 (32 bit)
Desktop Idle
100% workload
Suspend to Ram (S3) 5V Input Power
0.67 A/8.0 W
0.83 A/10.0 W
0.20 A/1.0 W
Intel® Atom™ E680T 1.6 GHz 512kB L2 cache
With 1GB onboard memory
Intel® Atom™ E680/E680T 1.6 GHz 512kB L2 cache
45nm
Layout Rev. QTOPLA1 /BIOS Rev. QTOPR002
conga-CA6/E680T-1G Art. No. 061213
Memory Size
Operating System
Power State
Power consumption (measured in Amperes/Watts)
2.5.3
1GB onboard
Windows 7 (32 bit)
Desktop Idle
100% workload
Suspend to Ram (S3) 5V Input Power
0.67 A/8.0 W
0.83 A/10.0 W
0.20 A/1.0 W
Intel® Atom™ E640 1.0 GHz 512kB L2 cache
With 1GB onboard memory
Intel® Atom™ E640/E640T 1.0 GHz 512kB L2 cache
45nm
Layout Rev. QTOPLA2 /BIOS Rev. QTOPR002
conga-CA6/E640-1G Art. No. 061201
Memory Size
Operating System
Power State
Power consumption (measured in Amperes/Watts)
1GB onboard
Windows 7 (32 bit)
Desktop Idle
100% workload
Suspend to Ram (S3) 5V Input Power
0.63 A/7.5 W
0.74 A/8.9 W
0.22 A/1.1 W
Copyright © 2012 congatec AG CTOPm10 16/85
2.5.4
Intel® Atom™ E640T 1.0 GHz 512kB L2 cache
With 1GB onboard memory
Intel® Atom™ E640/E640T 1.0 GHz 512kB L2 cache
45nm
Layout Rev. QTOPLA2 /BIOS Rev. QTOPR002
conga-CA6/E640T-1G Art. No. 061211
Memory Size
Operating System
Power State
Power consumption (measured in Amperes/Watts)
1GB onboard
Windows 7 (32 bit)
Desktop Idle
100% workload
Suspend to Ram (S3) 5V Input Power
0.63 A/7.5 W
0.74 A/8.9 W
0.22 A/1.1 W
Note
All recorded power consumption values are approximate and only valid for the controlled environment described earlier. 100% workload refers
to the CPU workload and not the maximum workload of the complete module. Power consumption results will vary depending on the workload
of other components such as graphics engine, memory, etc.
2.6
Supply Voltage Battery Power
• 2.5V-3.6V DC
• Typical 3V DC
2.6.1
CMOS Battery Power Consumption
RTC @ 20ºC
Voltage
Current
Integrated in the Intel® Platform Controller Hub EG20T
3V DC
1.71 µA
The CMOS battery power consumption value listed above should not be used to calculate CMOS battery lifetime. You should measure the
CMOS battery power consumption in your customer specific application in worst case conditions, for example during high temperature and
high battery voltage. The self-discharge of the battery must also be considered when determining CMOS battery lifetime. For more information
about calculating CMOS battery lifetime refer to application note AN9_RTC_Battery_Lifetime.pdf, which can be found on the congatec AG
website at www.congatec.com.
Note
There is a limitation with the Intel® Platform Controller Hub EG20T. The RTC leakage current is extremely high. This means the RTC battery of
Copyright © 2012 congatec AG CTOPm10 17/85
a system featuring this chipset depletes after as little as 8 months.
congatec solves this RTC current leakage problem by using the onboard board controller found on the conga-CA6. When the conga-CA6 is
powered off, the EG20T RTC is disconnected and the onboard board controller’s RTC is used. When the conga-CA6 is restarted, the BIOS
overwrites the EG20T system clock with the correct one provided by the congatec board controller.
2.7
Environmental Specifications
Temperature
Operation: 0° to 60°C
Storage: -20° to +80°C
Humidity
Operation: 10% to 90%
Storage: 5% to 95%
Caution
The above operating temperatures must be strictly adhered to at all times. The congatec heatspreader is only suitable for use within commercial
temperature ranges (0° to 60°C). It is not designed to be used within industrial temperature ranges (-40° to 85°C). When using a heatspreader
with conga-CA6 commercial grade variants, the maximum operating temperature refers to any measurable spot on the heatspreader’s surface.
congatec AG strongly recommends that you use the appropriate congatec module heatspreader as a thermal interface between the module
and your application specific cooling solution when used in a commercial temperature range.
If it is not possible to use the appropriate congatec module heatspreader for conga-CA6 commercial grade variants or an industrial grade variant
of conga-CA6 is being used within industrial temperature ranges, then it is the responsibility of the operator to ensure that all components found
on the module operate within the component manufacturer’s specified temperature range.
Copyright © 2012 congatec AG CTOPm10 18/85
3
Block Diagram
Onboard DDR2
Maximum 2GB
1x PCIe
Intel® Platform
Controller Hub
EG20T
PCI Bus
GPIOs
I2C
Memory Bus
(533/800MHz)
PCIe Port 0
PCI to SATA/PATA
Bridge
2x SATA
Micrel®
Gbit Ethernet
Phy KSZ9021RN(I)
Gbe MAC
Intel® Atom™
processor
E6xx/E6xxT Series
6x USB
Gbit Ethernet
LVDS
LPC
HDA
SPI
2x PCIe
SM Bus
2x SATA
A-B
Watchdog
Board Controller
Atmel
ATmega165P
I²C Bus
Hardware
Monitor
PCIe to PCI Bridge
TI XIO2000A
Monitoring
Fan
Control
SDVO
PCI Bus
PATA
Circuitry
C-D
Copyright © 2012 congatec AG CTOPm10 19/85
4
Heatspreader
An important factor for each system integration is the thermal design. The heatspreader acts as a thermal coupling device to the module and
its aluminum plate is 3mm thick.
The heatspreader is thermally coupled to the CPU via a thermal gap filler and on some modules it may also be thermally coupled to other heat
generating components with the use of additional thermal gap fillers.
Although the heatspreader is the thermal interface where most of the heat generated by the module is dissipated, it is not to be considered
as a heatsink. It has been designed to be used as a thermal interface between the module and the application specific thermal solution. The
application specific thermal solution may use heatsinks with fans, and/or heat pipes, which can be attached to the heatspreader. Some thermal
solutions may also require that the heatspreader is attached directly to the systems chassis therefore using the whole chassis as a heat
dissipater.
Caution
congatec COM Express™ heaspreaders have been specifically designed for use within commercial temperature ranges (0° to 60°C) only.
congatec AG does not recommend using the conga-CA6 heatspreaders in industrial temperature ranges (-40° to 85°C). The user does so at
their own risk.
It is the responsibility of the end user to design an optimized thermal solution that meets the needs of their application within the industrial
environmental conditions it is required to operate in. Attention must be given to the mounting solution used to mount the heatspreader and
module into the system chassis.
Do not use a threaded heatspreader together with threaded carrier board standoffs. The combination of the two threads may be staggered,
which could lead to stripping or cross-threading of the threads in either the standoffs of the heatspreader or carrier board.
Only heatspreaders that feature micro pins that secure the thermal stacks should be used for applications that require the heatspreader to be
mounted vertically. It cannot be guaranteed that the thermal stacks will not move if a heatspreader that does not have the micro pin feature is
used in vertically mounted applications.
Additionally, the gap pad material used on all heatspreaders contains silicon oil that can seep out over time depending on the environmental
conditions it is subjected to. For more information about this subject, contact your local congatec sales representative and request the gap pad
material manufacturer’s specification
Copyright © 2012 congatec AG CTOPm10 20/85
4.1
Heatspreader Dimensions
Note
All measurements are in millimeters. Torque specification for heatspreader screws is 0.5 Nm.
Copyright © 2012 congatec AG CTOPm10 21/85
5
Connector Subsystems Rows A, B, C, D
The conga-CA6 is connected to the carrier board via two 220-pin connectors (COM Express Type 2 pinout) for a total of 440 pins connectivity.
These connectors are broken down into four rows. The primary connector consists of rows A and B while the secondary connector consists of
rows C and D.
A-B
2x PCI Express Lanes
4x Serial ATA
(commercial temperature
variants only otherwise 2x
Serial ATA)
6x USB 2.0
High Definition Audio I/F
C-D
1x SDVO
PCI Bus
1x IDE
Fan Control
Gigabit Ethernet
LPC Bus
I²C Bus
LVDS
Power Control
C-D
A-B
top view
In this view the connectors are seen “through” the module.
Copyright © 2012 congatec AG CTOPm10 22/85
5.1
Primary Connector Rows A and B
The following subsystems can be found on the primary connector rows A and B.
5.1.1
Serial ATA™ (SATA)
Two Serial ATA connections (Ports 0, 1) are provided via the Intel EG20T Platform Controller Hub (PCH) . Additional two Serial ATA connections
(Ports 2, 3) are provided by VIA VT6421 PCI SATA to PATA bridge. These ports are however only available on the commercial temperature
range variants of the conga-CA6.
The SATA connections (Ports 0, 1, 2, 3) support SATA 1.5-Gbps Gerneration 1 and 3-Gbps Generation 2 speeds. Compliant with Serial ATA
specification 2.6 and Advanced Host Controller Interface (AHCI) specification revision 1.1.
Note
The conga-QA6 SATA interface supports AHCI operating mode only on Ports 0, 1 and Legacy operating mode only on Ports 2, 3. SATA Port 1
is not available if the conga‑CA6 is equipped with the optional onboard SSD feature.
5.1.2
USB 2.0
The conga-CA6 offers 6 USB host ports provided by the Intel EG20T PCH. These ports comply with USB standard 1.1 and 2.0 and are routed
to connector rows A and B. Each port is capable of supporting USB 1.1 and 2.0 compliant devices.
5.1.3
High Definition Audio (HDA) Interface
The conga-CA6 provides an interface that supports the connection of HDA audio codecs.
5.1.4
Gigabit Ethernet
The conga-CA6 is equipped with a Gigabit Ethernet Media Access Controller (GbE MAC) provided by the Intel EG20T PCH that is connected
to a Micrel KSZ9021RN(I) Phy via the Reduced Gigabit Media Independent Interface (RGMII). This controller is implemented through the use
of a x1 PCI Express link.
The Ethernet interface consists of 4 pairs of low voltage differential pair signals designated from GBE0_MD0± to GBE0_MD3± plus control
signals for link activity indicators. These signals can be used to connect to a 10/100/1000 BaseT RJ45 connector with integrated or external
isolation magnetics on the carrier board.
Copyright © 2012 congatec AG CTOPm10 23/85
Note
It is recommended that the center-taps of the Magnetics are not connected to each other and not connected to the CTREF pin.
5.1.5
LPC Bus
conga-CA6 offers the LPC (Low Pin Count) bus through the use of the Intel E6x0/E6x0T CPU. There are many devices available for this
bus. The LPC bus corresponds approximately to a serialized ISA bus yet with a significantly reduced number of signals. Due to the software
compatibility to the ISA bus, I/O extensions such as additional serial ports can be easily implemented on an application specific baseboard
using this bus.
5.1.6
I²C Bus
The I²C bus is implemented through the use of STMicroelectronics STM32F100R8 microcontroller. It provides a multi-master I²C Bus that has
maximum I²C bandwidth.
5.1.7
PCI Express™
The conga-CA6 offers 2x PCI Express™ Gen 2 lanes. These lanes (0, 1) are provided by the Intel E6x0/E6x0T and can be configured to
support PCI Express edge cards or ExpressCards. The PCI Express™ interface offers support for full 5 Gb/s bandwidth in each direction per
lane.
Note
Some PCI Express devices may have a problem if IRQ 6 or IRQ 12 is assigned to the device. In this case it is necessary to manually assign an
IRQ for the device via the PIRQ Routing Submenu found in the BIOS setup program. For more information about this setup node see section
10.5.5 “PIRQ Routing Submenu”.
5.1.8
ExpressCard™
The conga-CA6 supports the implementation of ExpressCards, which requires the dedication of one USB 2.0 port and one x1 PCI Express
link for each ExpressCard used.
Copyright © 2012 congatec AG CTOPm10 24/85
5.1.9
Graphics Output (VGA/CRT)
The conga-CA6 does not provide a VGA/CRT output.
5.1.10
LCD
The conga-CA6 offers a single channel 80 MHz LVDS interface. This interface is provided by Intel E6x0/E6x0T. It supports the connection of
1x18 or 1x24 bit data mapping up to a resolution of [email protected]
5.1.11
TV-Out
Integrated TV-Out support is not supported on the conga-CA6
5.1.12
Power Control
PWR_OK
Power OK from main power supply. A high value indicates that the power is good. Using this input is optional. Through the use of an internal
monitor on the +12V ± 5% input voltage, and/or the internal power supplies, the conga‑CA6 module is capable of generating its own power‑good
signal. According to the COM Express™ Specification PWR_OK is a 3.3V signal and should be driven by open-collector/drain type output.
The conga-CA6 provides support for controlling ATX-style power supplies. When not using an ATX power supply then the conga-CA6’s pins
SUS_S3#/PS_ON#, 5V_SB#, and PWRBTN# should be left unconnected.
SUS_S3#/PS_ON#
The SUS_S3#/PS_ON# (pin A15 on the A-B connector) signal is an active-low output that can be used to turn on the main outputs of an
ATX‑style power supply. To accomplish this the signal must be inverted with an inverter/transistor that is supplied by standby voltage and is
located on the carrier board.
PWRBTN#
When using ATX-style power supplies PWRBTN# (pin B12 on the A-B connector) is used to connect to a momentary‑contact, active-low
debounced push-button input while the other terminal on the push-button must be connected to ground. This signal is internally pulled up to
3V_SB using a 10k resistor. When PWRBTN# is asserted it indicates that an operator wants to turn the power on or off. The response to this
signal from the system may vary as a result of modifications made in BIOS settings or by system software.
Copyright © 2012 congatec AG CTOPm10 25/85
Power Supply Implementation Guidelines
12 volt input power is the sole operational power source for the conga-CA6. The remaining necessary voltages are internally generated on the
module using onboard voltage regulators. A carrier board designer should be aware of the following important information when designing a
power supply for a conga-CA6 application:
• It has also been noticed that on some occasions problems occur when using a 12V power supply that produces non monotonic voltage
when powered up. The problem is that some internal circuits on the module (e.g. clock-generator chips) will generate their own reset signals
when the supply voltage exceeds a certain voltage threshold. A voltage dip after passing this threshold may lead to these circuits becoming
confused resulting in a malfunction. It must be mentioned that this problem is quite rare but has been observed in some mobile power supply
applications. The best way to ensure that this problem is not encountered is to observe the power supply rise waveform through the use
of an oscilloscope to determine if the rise is indeed monotonic and does not have any voltage dips. This should be done during the power
supply qualification phase therefore ensuring that the above mentioned problem doesn’t arise in the application. For more information about
this issue visit www.formfactors.org and view page 25 figure 7 of the document “ATX12V Power Supply Design Guide V2.2”.
5.1.13
Power Management
ACPI 3.0 compliant with battery support. Also supports Suspend to RAM (S3).
Copyright © 2012 congatec AG CTOPm10 26/85
5.2
Secondary Connector Rows C and D
The following subsystems can be found on the secondary connector rows C and D.
5.2.1
PCI Express Graphics (PEG)
The PCI Express graphics interface is not supported by the conga-CA6.
5.2.2
SDVO
The conga-CA6 provides one SDVO port via Display Pipe B of the Intel Atom processor E6x0/E6x0T series. The SDVO port can support a
variety of display types (VGA, LVDS, DVI, TV-Out, etc.) by using an external SDVO device. This single channel 160MHz SDVO interface
supports resolutions up to [email protected] and [email protected] For more information see the table below.
Table 2
Display Resolutions
Resolution
Refresh
Pixel Clock Freq
SDVO Support
LVDS Support
640x480
640x480
848x480
848x480RB
640x480
800x600
848x480
640x480
800x600RB
800x600
848x480
848x480
800x600
1024x768
1024x768RB
800x600
1024x768
1280x768
1280x768RB
1280x768
1400x1050
1280x960
50 Hz
60 Hz
50 Hz
60 Hz
75 Hz
50 Hz
60 Hz
85 Hz
60 Hz
60 Hz
75 Hz
85 Hz
75 Hz
50 Hz
60 Hz
85 Hz
60 Hz
50 Hz
60 Hz
60 Hz
60 Hz
75 Hz
19.75 MHz
23.75 MHz
26 MHz
29.75 MHz
30.75 MHz
30.75 MHz
31.5 MHz
35 MHz
35.5 MHz
38.25 MHz
41 MHz
46.75 MHz
49 MHz
52 MHz
56 MHz
56.75 MHz
63.5 MHz
65.25 MHz
68.25 MHz
79.5 MHz
121.75 MHz
130 MHz
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Max LVDS interface support
Copyright © 2012 congatec AG CTOPm10 27/85
5.2.3
Resolution
Refresh
Pixel Clock Freq
SDVO Support
1600x1200RB
1600x1200
1920x1080RB
1280x1024
1920x1080
1280x960
1400x1050
1280x1024
60 Hz
50 Hz
60 Hz
75 Hz
50 Hz
85 Hz
75 Hz
85 Hz
130.25 MHz
131.5 MHz
138.5 MHz
138.75 MHz
141.5 MHz
148.25 MHz
156 MHz
159.5 MHz
Y
Y
Y
Y
Y
Y
Y
Y
LVDS Support
Max SDVO interface support
HDMI
The conga-CA6 does not support native HDMI.
5.2.4
DisplayPort (DP)
The conga-CA6 does not support native DisplayPort.
5.2.5
PCI Bus
The PCI bus is implemented using the Intel certified Pericom PI7C9X113SL PCIe to PCI bridge and is connected via one of the PCI Express
lanes offered by the Intel Atom processor E6x0/E6x0T series. The PCI bus complies with PCI specification Rev. 2.3 and provides a 32bit
parallel PCI bus that is capable of operating at 33MHz.
Note
The PCI interface is specified to be +5V tolerant, with +3.3V signaling.
5.2.6
IDE (PATA)
The conga-CA6 supports an IDE channel that is capable of UDMA-33/66/100 operation. This channel is implemented by converting PCI Bus
into an IDE channel using VIA VT6421L single chip solution for PCI to parallel ATA translation. The IDE interface supports the connection of
only one device at any given moment and this device operates in Master mode only.
Note
The IDE interface is only available on commercial temperatures variants of conga-CA6.
Copyright © 2012 congatec AG CTOPm10 28/85
6
Additional Features
6.1
Watchdog
The conga-CA6 is equipped with a multi stage watchdog solution that is triggered by software. The COM Express™ Specification does not
provide support for external hardware triggering of the Watchdog. This means the conga-CA6 does not support external hardware triggering.
For more information about the Watchdog feature see the BIOS setup description section 10.5.2 of this document and application note
AN3_Watchdog.pdf on the congatec AG website at www.congatec.com.
6.2
Onboard Microcontroller
The conga-CA6 is equipped with an STMicroelectronics STM32F100R8 microcontroller. This onboard microcontroller plays an important role
for most of the congatec BIOS features. It fully isolates some of the embedded features such as system monitoring or the I²C bus from the x86
core architecture, which results in higher embedded feature performance and more reliability, even when the x86 processor is in a low power
mode.
6.3
Embedded BIOS
The conga-CA6 is equipped with congatec Embedded BIOS and has the following features:
• ACPI Power Management
• Manufacturing Data and Board Information
• ACPI Battery Support
• OEM Splash Screen
• Supports Customer Specific CMOS Defaults
• Flat Panel Auto Detection and Backlight Control
• Multistage Watchdog
• BIOS Setup Data Backup
• User Data Storage
• Fast Mode I²C Bus
Copyright © 2012 congatec AG CTOPm10 29/85
6.4
Suspend to Ram
The Suspend to RAM feature is supported on the conga-CA6.
6.5
congatec Battery Management Interface
To facilitate the development of battery powered mobile systems based on embedded modules, congatec AG has defined an interface for the
exchange of data between a CPU module (using an ACPI operating system) and a Smart Battery system. A system developed according to the
congatec Battery Management Interface Specification can provide the battery management functions supported by an ACPI capable operating
system (e.g. charge state of the battery, information about the battery, alarms/events for certain battery states, ...) without the need for any
additional modifications to the system BIOS.
The conga-CA6 BIOS fully supports this interface. For more information about this subject visit the congatec website and view the following
documents:
• congatec Battery Management Interface Specification
• Battery System Design Guide
• conga-SBM3C User’s Guide
Copyright © 2012 congatec AG CTOPm10 30/85
7
conga Tech Notes
The conga-CA6 has some technological features that require additional explanation. The following section will give the reader a better
understanding of some of these features. This information will also help to gain a better understanding of the information found in the System
Resources section of this user’s guide as well as some of the setup nodes found in the BIOS Setup Program description section.
7.1
Intel® Processor Features
7.1.1
Thermal Monitor and Catastrophic Thermal Protection
Intel® Atom™ processor E6x0/E6x0T series have a thermal monitor feature that helps to control the processor temperature. The integrated
TCC (Thermal Control Circuit) activates if the processor silicon reaches its maximum operating temperature. The activation temperature, that
the Intel® Thermal Monitor uses to activate the TCC, cannot be configured by the user nor is it software visible.
The Thermal Monitor can control the processor temperature through the use of two different methods defined as TM1 and TM2. TM1 method
consists of the modulation (starting and stopping) of the processor clocks at a 50% duty cycle. The TM2 method initiates an Enhanced Intel®
Speedstep transition to the lowest performance state once the processor silicon reaches the maximum operating temperature.
Note
The maximum operating temperature for Intel® Atom™ processor E6x0/E6x0T series is 100°C.
Two modes are supported by the Thermal Monitor to activate the TCC. They are called Automatic and On-Demand. No additional hardware,
software, or handling routines are necessary when using Automatic Mode.
Note
To ensure that the TCC is active for only short periods of time thus reducing the impact on processor performance to a minimum, it is
necessary to have a properly designed thermal solution. The Intel® Atom™ processor E6x0/E6x0T series respective datasheet can provide
more information about this subject.
Copyright © 2012 congatec AG CTOPm10 31/85
7.1.2
Processor Performance Control
Intel® Atom™ processor E6x0/E6x0T series run at different voltage/frequency states (performance states), which is referred to as Enhanced
Intel® SpeedStep® technology (EIST). Operating systems that support performance control take advantage of microprocessors that use several
different performance states to efficiently operate the processor when it is not fully utilized. The operating system will determine the necessary
performance state that the processor should run at so that the optimal balance between performance and power consumption can be achieved
during runtime.
The Windows family of operating systems links its processor performance control policy to the power scheme setting. You must ensure that
your power scheme setting you choose has the ability to support Enhanced Intel® SpeedStep® technology.
7.1.3
Intel® Virtualization Technology
Virtualization solutions enhanced by Intel® VT will allow Atom™ processor E6x0/E6x0T series to run multiple operating systems and applications
in independent partitions. When using virtualization capabilities, one computer system can function as multiple “virtual” systems. With processor
and I/O enhancements to Intel®’s various platforms, Intel® Virtualization Technology can improve the performance and robustness of today’s
software-only virtual machine solutions.
Intel® VT is a multi-generational series of extensions to Intel® processor and platform architecture that provides a new hardware foundation for
virtualization, establishing a common infrastructure for all classes of Intel® based systems. The broad availability of Intel® VT makes it possible
to create entirely new applications for virtualization in servers, clients as well as embedded systems thus providing new ways to improve
system reliability, manageability, security, and real-time quality of service.
The success of any new hardware architecture is highly dependent on the system software that puts its new features to use. In the case of
virtualization technology, that support comes from the virtual machine monitor (VMM), a layer of software that controls the underlying physical
platform resources sharing them between multiple “guest” operating systems. Intel® VT is already incorporated into most commercial and opensource VMMs including those from VMware, Microsoft, XenSource, Parallels, Virtual Iron, Jaluna and TenAsys.
You can find more information about Intel Virtualization Technology at: http://developer.intel.com/technology/virtualization/index.htm
Note
congatec does not offer virtual machine monitor (VMM) software. All VMM software support questions should be directed to the VMM software
vendor and not congatec technical support.
Copyright © 2012 congatec AG CTOPm10 32/85
7.2
Thermal Management
ACPI is responsible for allowing the operating system to play an important part in the system’s thermal management. This results in the
operating system having the ability to take control of the operating environment by implementing cooling decisions according to the demands
put on the CPU by the application.
The conga-CA6 ACPI thermal solution offers three different cooling policies.
• Passive Cooling
When the temperature in the thermal zone must be reduced, the operating system can decrease the power consumption of the processor by
throttling the processor clock. One of the advantages of this cooling policy is that passive cooling devices (in this case the processor) do not
produce any noise. Use the “passive cooling trip point” setup node in the BIOS setup program to determine the temperature threshold that the
operating system will use to start or stop the passive cooling procedure.
• Active Cooling
During this cooling policy the operating system is turning the fan on/off. Although active cooling devices consume power and produce noise,
they also have the ability to cool the thermal zone without having to reduce the overall system performance. Use the “active cooling trip point”
setup node in the BIOS setup program to determine the temperature threshold that the operating system will use to start the active cooling
device. It is stopped again when the temperature goes below the threshold (5°C hysteresis).
• Critical Trip Point
If the temperature in the thermal zone reaches a critical point then the operating system will perform a system shut down in an orderly fashion
to ensure that there is no damage done to the system as result of high temperatures. Use the “critical trip point” setup node in the BIOS setup
program to determine the temperature threshold that the operating system will use to shut down the system.
Note
The end user must determine the cooling preferences for the system by using the setup nodes in the BIOS setup program to establish the
appropriate trip points.
If passive cooling is activated and the processor temperature is above the trip point the processor clock is throttled according to the formula
below.
∆P[%] = TC1(Tn-Tn-1) + TC2(Tn-Tt)
• ∆P is the performance delta
• Tt is the target temperature = critical trip point
Copyright © 2012 congatec AG CTOPm10 33/85
• The two coefficients TC1 and TC2 and the sampling period TSP are hardware dependent constants. These constants are set to fixed values
for the conga-CA6:
• TC1= 1
• TC2= 5
• TSP= 5 seconds
See section 12 of the ACPI Specification 2.0 C for more information about passive cooling.
7.3
ACPI Suspend Modes and Resume Events
conga-CA6 supports the S3 (STR= Suspend to RAM) power state. For more information about S3 wake events see section 10.5.7 “ACPI
Configuration Submenu”. S4 (Suspend to Disk) is not supported by the BIOS (S4_BIOS) but it is supported by some operating systems
(S4_OS= Hibernate). Check with the operating system vendor to determine if S4 (Suspend to Disk) is supported.
This table lists the “Wake Events” that resume the system from S3 unless otherwise stated in the “Conditions/Remarks” column:
Wake Event
Conditions/Remarks
Power Button
Onboard LAN Event
PCI Express WAKE#
Watchdog Power Button Event
Wakes unconditionally from S3 and S5.
Device driver must be configured for Wake On LAN support. Feature must be enabled in BIOS setup.
Wakes unconditionally from S3.
Wakes unconditionally from S3 and S5.
Note
The above list has been verified with a Windows XP SP3 enabled with ACPI
Copyright © 2012 congatec AG CTOPm10 34/85
7.4
USB Port Connections
The 6 USB ports are shared between 2 EHCI host controllers. Ports 0-5 are capable of supporting USB 1.1 and 2.0 compliant devices. Port 1
can be configured as either a USB Device (Client) port or Host port.
Routing Diagram
usbhost4
usbhost2
usbhost0
OHCI
D8:F0
OHCI
D8:F1
OHCI
D8:F2
EHCI
D8:F3
USB Host Controller #0
usbhost5
usbhost3
usbhost1
OHCI
D2:F0
OHCI
D2:F1
OHCI
D2:F2
EHCI
D2:F3
USB Host Controller #1
Copyright © 2012 congatec AG CTOPm10 35/85
7.4.1
USB Client Controller
The Intel EG20T Platform Controller Hub located on the conga-CA6 features a Universal Serial Bus 2.0 device/client controller. This USB
device/client controller allows the conga-CA6 to connect to other computer systems that utilize a USB Host interface. Once connected, the
conga-CA6 can perform tasks supported by common USB devices. This includes, but not limited to, such functionality as data transfer and
network access.
This USB device/client implementation is designed to achieve maximum flexibility while maintaining hardware simplicity. Most of the behavior
above the DMA and USB protocol layer is the responsibility of software. This includes Transaction level formatting, handling USB Descriptors
and the implementation of defined Device Classes.
Detailed information about the USB Client Controller is beyond the scope of this document. For more information refer to the Intel® Platform
Controller Hub EG20T datasheet.
Note
The EG20T Platform Controller Hub USB device/client port is routed to USB Port 1 on the conga-CA6.
Copyright © 2012 congatec AG CTOPm10 36/85
8
Signal Descriptions and Pinout Tables
The following section describes the signals found on COM Express™ Type II connectors used for congatec AG modules. The pinout of the
modules complies with COM Express Type 2.0 Rev. 2.0.
Table 2 describes the terminology used in this section for the signal description tables. The PU/PD column indicates if a COM Express™
module pull-up or pull-down resistor has been used, if the field entry area in this column for the signal is empty, then no pull-up or pull-down
resistor has been implemented by congatec.
The “#” symbol at the end of the signal name indicates that the active or asserted state occurs when the signal is at a low voltage level. When
“#” is not present, the signal is asserted when at a high voltage level.
Note
The signal description tables do not list internal pull-ups or pull-downs implemented by the chip vendors, only pull-ups or pull-downs implemented
by congatec are listed. For information about the internal pull-ups or pull-downs implemented by the chip vendors, refer to the respective chip’s
datasheet.
Table 3
Signal Tables Terminology Descriptions
Term
Description
PU
PD
I/O 3.3V
I/O 5V
I 3.3V
I 5V
I/O 3.3VSB
O 3.3V
O 5V
OD
P
DDC
PCIE
PEG
SATA
REF
PDS
congatec implemented pull-up resistor
congatec implemented pull-down resistor
Bi-directional signal 3.3V tolerant
Bi-directional signal 5V tolerant
Input 3.3V tolerant
Input 5V tolerant
Input 3.3V tolerant active in standby state
Output 3.3V signal level
Output 5V signal level
Open drain output
Power Input/Output
Display Data Channel
In compliance with PCI Express Base Specification, Revision 2.0
PCI Express Graphics
In compliance with Serial ATA specification, Revision 3.0.
Reference voltage output. May be sourced from a module power plane.
Pull-down strap. A module output pin that is either tied to GND or is not connected. Used to signal
module capabilities (pinout type) to the Carrier Board.
Copyright © 2012 congatec AG CTOPm10 37/85
8.1
A-B Connector Signal Descriptions
Table 4
Intel® High Definition Audio Link Signals Descriptions
Signal
Pin #
Description
Intel® High Definition Audio Reset: This signal is the master hardware
reset to external codec(s).
AC/HDA_SYNC
A29
Intel® High Definition Audio Sync: This signal is a 48 kHz fixed rate
sample sync to the codec(s). It is also used to encode the stream number.
AC/HDA_BITCLK
A32
Intel® High Definition Audio Bit Clock Output: This signal is a
24.000MHz serial data clock generated by the Intel® High Definition Audio
controller.
AC/HDA_SDOUT
A33
Intel® High Definition Audio Serial Data Out: This signal is the serial
TDM data output to the codec(s). This serial output is double-pumped for
a bit rate of 48 Mb/s for Intel® High Definition Audio.
AC/HDA_SDIN[2:0] B28-B30 Intel® High Definition Audio Serial Data In [0]: These signals are serial
TDM data inputs from the three codecs. The serial input is single-pumped
for a bit rate of 24 Mb/s for Intel® High Definition Audio.
AC/HDA_RST#
A30
I/O
PU/PD Comment
O 3.3VSB
AC’97 codecs are not supported.
O 3.3VSB
AC’97 codecs are not supported.
O 3.3VSB
AC’97 codecs are not supported.
O 3.3VSB
AC’97 codecs are not supported.
AC/HDA_SDOUT is a bootstrap signal (see
note below)
AC’97 codecs are not supported.
I 3.3VSB
Copyright © 2012 congatec AG CTOPm10 38/85
Table 5
Gigabit Ethernet Signal Descriptions
Gigabit Ethernet Pin # Description
I/O
GBE0_MDI0+
GBE0_MDI0GBE0_MDI1+
GBE0_MDI1GBE0_MDI2+
GBE0_MDI2GBE0_MDI3+
GBE0_MDI3-
A13
A12
A10
A9
A7
A6
A3
A2
I/O Analog
GBE0_ACT#
B2
MDI[0]+/B1_DA+/TX+/MDI[1]+/B1_DB+/RX+/MDI[2]+/B1_DC+/MDI[3]+/B1_DD+/Gigabit Ethernet Controller 0 activity indicator, active low.
GBE0_LINK#
A8
Gigabit Ethernet Controller 0 link indicator, active low.
GBE0_LINK100#
A4
Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low.
GBE0_LINK1000#
A5
Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low.
GBE0_CTREF
A14
Reference voltage for Carrier Board Ethernet channel 0 magnetics center tap. The reference voltage is
determined by the requirements of the module PHY and may be as low as 0V and as high as 3.3V. The
reference voltage output shall be current limited on the module. In the case in which the reference is shorted
to ground, the current shall be limited to 250mA or less.
Gigabit Ethernet Controller 0: Media Dependent Interface Differential Pairs 0, 1, 2, 3. The MDI can operate
in 1000, 100, and 10Mbit/sec modes. Some pairs are unused in some modes according to the following:
1000
100
10
PU/PD
Comment
Twisted pair
signals for
external
transformer.
TX+/RX+/-
O 2.5VSB PU 4k99 GBE0_ACT
2,5VSB is a bootstrap
signal (see
note below)
O 3.3VSB PD 1k
GBE0_LINK#
is a bootstrap
signal (see
note below)
O 2.5VSB PU 4k99 GBE0_
2,5VSB LINK100# is
a bootstrap
signal (see
note below)
O 3.3VSB PD 1k
GBE0_
LINK1000#
is a bootstrap
signal (see
note below)
Not connected
Note
Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module.
For more information refer to section 8.5 of this user’s guide.
Copyright © 2012 congatec AG CTOPm10 39/85
Table 6
Serial ATA Signal Descriptions
Signal
Pin # Description
I/O
SATA0_RX+
SATA0_RXSATA0_TX+
SATA0_TXSATA1_RX+
SATA1_RXSATA1_TX+
SATA1_TXSATA2_RX+
SATA2_RXSATA2_TX+
SATA2_TXSATA3_RX+
SATA3_RXSATA3_TX+
SATA3_TXATA_ACT#
A19
A20
A16
A17
B19
B20
B16
B17
A25
A26
A22
A23
B25
B26
B22
B23
A28
Serial ATA channel 0, Receive Input differential pair.
I SATA
Supports Serial ATA specification, Revision 2.6
Serial ATA channel 0, Transmit Output differential pair.
O SATA
Supports Serial ATA specification, Revision 2.6
Serial ATA channel 1, Receive Input differential pair.
I SATA
Supports Serial ATA specification, Revision 2.6
Serial ATA channel 1, Transmit Output differential pair.
O SATA
Supports Serial ATA specification, Revision 2.6
Serial ATA channel 2, Receive Input differential pair.
I SATA
Supports Serial ATA specification, Revision 1.0
Serial ATA channel 2, Transmit Output differential pair.
O SATA
Supports Serial ATA specification, Revision 1.0
Serial ATA channel 3, Receive Input differential pair.
I SATA
Supports Serial ATA specification, Revision 1.0
Serial ATA channel 3, Transmit Output differential pair.
O SATA
Supports Serial ATA specification, Revision 1.0
ATA (parallel and serial) or SAS activity indicator, active low. O 3.3V
PU/PD
Comment
PU 10k 3.3V
Copyright © 2012 congatec AG CTOPm10 40/85
Table 7
PCI Express Signal Descriptions (general purpose)
Signal
Pin # Description
I/O
PCIE_RX0+
PCIE_RX0PCIE_TX0+
PCIE_TX0PCIE_RX1+
PCIE_RX1PCIE_TX1+
PCIE_TX1PCIE_RX2+
PCIE_RX2PCIE_TX2+
PCIE_TX2PCIE_RX3+
PCIE_RX3PCIE_TX3+
PCIE_TX3PCIE_RX4+
PCIE_RX4PCIE_TX4+
PCIE_TX4PCIE_RX5+
PCIE_RX5PCIE_TX5+
PCIE_TX5PCIE_CLK_REF+
PCIE_CLK_REF-
B68
B69
A68
A69
B64
B65
A64
A65
B61
B62
A61
A62
B58
B59
A58
A59
B55
B56
A55
A56
B52
B53
A52
A53
A88
A89
PCI Express channel 0, Receive Input differential pair.
I PCIE
Supports PCI Express Base Specification, Revision 2.0
PCI Express channel 0, Transmit Output differential pair.
O PCIE
Supports PCI Express Base Specification, Revision 2.0
PCI Express channel 1, Receive Input differential pair.
I PCIE
Supports PCI Express Base Specification, Revision 2.0
PCI Express channel 1, Transmit Output differential pair.
O PCIE
Supports PCI Express Base Specification, Revision 2.0
PCI Express channel 2, Receive Input differential pair.
I PCIE
Not supported
PCI Express channel 2, Transmit Output differential pair.
O PCIE
Not supported
PCI Express channel 3, Receive Input differential pair.
I PCIE
Not supported
PCI Express channel 3, Transmit Output differential pair.
O PCIE
Not supported
PCI Express channel 4, Receive Input differential pair.
I PCIE
Not supported
PCI Express channel 4, Transmit Output differential pair.
O PCIE
Not supported
PCI Express channel 5, Receive Input differential pair.
I PCIE
Not supported
PCI Express channel 5, Transmit Output differential pair.
O PCIE
Not supported
PCI Express Reference Clock output for all PCI Express
and PCI Express Graphics Lanes.
O PCIE
A PCI Express Gen2 compliant clock buffer chip must be used
on the carrier board if more than one PCI Express device is
designed in.
Table 8
PU/PD
Comment
ExpressCard Support Pins Descriptions
Signal
Pin # Description
I/O
PU/PD
EXCD0_CPPE#
EXCD1_CPPE#
EXCD0_PERST#
EXCD1_PERST#
A49
B48
A48
B47
ExpressCard capable card request.
I 3.3V
PU 10k 3.3V
ExpressCard Reset
O 3.3V
PU 10k 3.3V
Comment
Connect to CB_RESET#
Copyright © 2012 congatec AG CTOPm10 41/85
Table 9
LPC Signal Descriptions
Signal
Pin #
Description
I/O
LPC_AD[0:3]
LPC_FRAME#
LPC_DRQ[0:1]#
LPC_SERIRQ
LPC_CLK
B4-B7
B3
B8-B9
A50
B10
LPC multiplexed address, command and data bus
LPC frame indicates the start of an LPC cycle
LPC serial DMA request
LPC serial interrupt
LPC clock output - 33MHz nominal
I/O 3.3V
O 3.3V
I 3.3V
Not supported
I/O OD 3.3V PU 10k 3.3V
O 3.3V
PU/PD
Comment
Table 10 USB Signal Descriptions
Signal
Pin # Description
I/O
USB0+
USB0USB1+
USB1USB2+
USB2USB3+
USB3USB4+
USB4USB5+
USB5USB6+
USB6USB7+
USB7USB_0_1_OC#
A46
A45
B46
B45
A43
A42
B43
B42
A40
A39
B40
B39
A37
A36
B37
B36
B44
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
PU 10k
3.3VSB 3.3VSB
USB_2_3_OC#
A44
USB_4_5_OC#
B38
USB_6_7_OC#
A38
USB Port 0, data + or D+
USB Port 0, data - or DUSB Port 1, data + or D+
USB Port 1, data - or DUSB Port 2, data + or D+
USB Port 2, data - or DUSB Port 3, data + or D+
USB Port 3, data - or DUSB Port 4, data + or D+
USB Port 4, data - or DUSB Port 5, data + or D+
USB Port 5, data - or DUSB Port 6, data + or D+
USB Port 6, data - or DUSB Port 7, data + or D+
USB Port 7, data - or DUSB over-current sense, USB ports 0 and 1. A pull-up for this line shall
be present on the module. An open drain driver from a USB current
monitor on the carrier board may drive this line low.
USB over-current sense, USB ports 2 and 3. A pull-up for this line shall
be present on the module. An open drain driver from a USB current
monitor on the carrier board may drive this line low. .
USB over-current sense, USB ports 4 and 5. A pull-up for this line shall
be present on the module. An open drain driver from a USB current
monitor on the carrier board may drive this line low.
USB over-current sense, USB ports 6 and 7. A pull-up for this line shall
be present on the module. An open drain driver from a USB current
monitor on the carrier board may drive this line low.
PU/PD Comment
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
USB 2.0 compliant. Backwards compatible to USB 1.1
Not supported
Not supported
Not supported
Not supported
Do not pull this line high on the carrier board.
I
PU 10k Do not pull this line high on the carrier board.
3.3VSB 3.3VSB
I
PU 10k Do not pull this line high on the carrier board.
3.3VSB 3.3VSB
I
3.3VSB
Not supported
Copyright © 2012 congatec AG CTOPm10 42/85
Table 11 CRT Signal Descriptions
Signal
Pin # Description
I/O
VGA_RED
VGA_GRN
VGA_BLU
VGA_HSYNC
VGA_VSYNC
VGA_I2C_CK
VGA_I2C_DAT
B89
B91
B92
B93
B94
B95
B96
O Analog
O Analog
O Analog
O 3.3V
O 3.3V
I/O OD 5V
I/O OD 5V
Red for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.
Green for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.
Blue for monitor. Analog DAC output, designed to drive a 37.5-Ohm equivalent load.
Horizontal sync output to VGA monitor
Vertical sync output to VGA monitor
DDC clock line (I²C port dedicated to identify VGA monitor capabilities)
DDC data line.
PU/PD
Comment
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Not supported
Table 12 LVDS Signal Descriptions
Signal
Pin #
Description
I/O
LVDS_A0+
LVDS_A0LVDS_A1+
LVDS_A1LVDS_A2+
LVDS_A2LVDS_A3+
LVDS_A3LVDS_A_CK+
LVDS_A_CKLVDS_B0+
LVDS_B0LVDS_B1+
LVDS_B1LVDS_B2+
LVDS_B2LVDS_B3+
LVDS_B3LVDS_B_CK+
LVDS_B_CKLVDS_VDD_EN
LVDS_BKLT_EN
LVDS_BKLT_CTRL
LVDS_I2C_CK
LVDS_I2C_DAT
A71
A72
A73
A74
A75
A76
A78
A79
A81
A82
B71
B72
B73
B74
B75
B76
B77
B78
B81
B82
A77
B79
B83
A83
A84
LVDS Channel A differential pairs
O LVDS
PU/PD
Comment
LVDS Channel A differential clock
O LVDS
LVDS Channel B differential pairs
O LVDS
Not supported
LVDS Channel B differential clock
O LVDS
Not supported
LVDS panel power enable
LVDS panel backlight enable
LVDS panel backlight brightness control
DDC lines used for flat panel detection and control.
DDC lines used for flat panel detection and control.
O 3.3V
O 3.3V
O 3.3V
O 3.3V
I/O 3.3V
PD 10k
PD 10k
PU 2k2 3.3V
PU 2k2 3.3V
Copyright © 2012 congatec AG CTOPm10 43/85
Table 13 SPI BIOS Flash Interface Signal Descriptions
Signal
Pin # Description
I/O
PU/PD
SPI_CS#
B97
Chip select for Carrier Board SPI BIOS Flash.
O 3.3V
PU 10k 3.3V Carrier shall pull to SPI_POWER when
external SPI provided but not used.
SPI_MISO
SPI_MOSI
SPI_CLK
SPI_POWER
A92
A95
A94
A91
Data in to module from carrier board SPI BIOS flash.
Data out from module to carrier board SPI BIOS flash.
Clock from module to carrier board SPI BIOS flash.
Power source for carrier board SPI BIOS flash. SPI_POWER shall be used to
power SPI BIOS flash on the carrier only.
Selection strap to determine the BIOS boot device.
Selection strap to determine the BIOS boot device.
I 3.3V
O 3.3V
O 3.3V
+ 3.3V
BIOS_DIS0# A34
BIOS_DIS1# B88
Comment
PU 1k 3.3V
I 3.3V
I 3.3V
Not connected
PU 10K 3.3V Carrier shall pull to GND or leave no-connect
Table 14 Miscellaneous Signal Descriptions
Signal
Pin # Description
I/O
PU/PD
I2C_CK
I2C_DAT
SPKR
WDT
KBD_RST#
B33
B34
B32
B27
A86
I/O 3.3V
I/O 3.3V
O 3.3V
O 3.3V
I
PU 2K2 3.3VSB
PU 2K2 3.3VSB
KBD_A20GATE
A87
I
PU 10K 3.3VSB
General purpose I²C port clock output/input
General purpose I²C port data I/O line
Output for audio enunciator, the “speaker” in PC-AT systems
Output indicating that a watchdog time-out event has occurred.
Input to module from (optional) external keyboard controller that can force a reset.
Pulled high on the module. This is a legacy artifact of the PC-AT.
Input to module from (optional) external keyboard controller that can be used to
control the CPU A20 gate line. The A20GATE restricts the memory access to the
bottom megabyte and is a legacy artifact of the PC-AT. Pulled high on the module.
Comment
PU 10K 3.3V
Table 15 General Purpose I/O Signal Descriptions
Signal
Pin # Description
I/O
PU/PD
GPO[0]
GPO[1]
GPO[2]
GPO[3]
GPI[0]
GPI[1]
GPI[2]
GPI[3]
A93
B54
B57
B63
A54
A63
A67
A85
O 3.3V
O 3.3V
O 3.3V
O 3.3V
I 3.3V
I 3.3V
I 3.3V
I 3.3V
PU 4k75 3.3V
PU 4k75 3.3V
PU 4k75 3.3V
PU 4k75 3.3V
General purpose output pins.
General purpose output pins.
General purpose output pins.
General purpose output pins.
General purpose input pins. Pulled high internally on the module.
General purpose input pins. Pulled high internally on the module.
General purpose input pins. Pulled high internally on the module.
General purpose input pins. Pulled high internally on the module.
Comment
Copyright © 2012 congatec AG CTOPm10 44/85
Table 16 Power and System Management Signal Descriptions
Signal
Pin # Description
I/O
PU/PD
PWRBTN#
SYS_RESET#
B12
B49
I 3.3VSB
I 3.3V
PU 10k 3.3VSB
PU 10k 3.3V
CB_RESET#
B50
O 3.3V
PD 20k
PWR_OK
B24
SUS_STAT#
SUS_S3#
B18
A15
SUS_S4#
SUS_S5#
WAKE0#
WAKE1#
A18
A24
B66
B67
BATLOW#
A27
THRM#
THERMTRIP#
SMB_CK
B35
A35
B13
SMB_DAT#
B14
SMB_ALERT#
B15
Power button to bring system out of S5 (soft off), active on rising edge.
Reset button input. Active low input. Edge triggered.
System will not be held in hardware reset while this input is kept low.
Reset output from module to Carrier Board. Active low. Issued by module chipset and may result
from a low SYS_RESET# input, a low PWR_OK input, a VCC_12V power input that falls below
the minimum specification, a watchdog timeout, or may be initiated by the module software.
Power OK from main power supply. A high value indicates that the power is good.
Indicates imminent suspend operation; used to notify LPC devices.
Indicates system is in Suspend to RAM state. Active-low output. An inverted copy of SUS_S3#
on the carrier board (also known as “PS_ON”) may be used to enable the non-standby power on
a typical ATX power supply.
Indicates system is in Suspend to Disk state. Active low output.
Indicates system is in Soft Off state.
PCI Express wake up signal.
General purpose wake up signal. May be used to implement wake-up on PS/2 keyboard or
mouse activity.
Battery low input. This signal may be driven low by external circuitry to signal that the system
battery is low, or may be used to signal some other external power-management event.
Input from off-module temp sensor indicating an over-temp situation.
Active low output indicating that the CPU has entered thermal shutdown.
System Management Bus bidirectional clock line. Power sourced through 5V standby rail and
main power rails.
System Management Bus bidirectional data line. Power sourced through 5V standby rail and
main power rails.
System Management Bus Alert – active low input can be used to generate an SMI# (System
Management Interrupt) or to wake the system. Power sourced through 5V standby rail and main
power rails.
I 3.3V
Comment
Set by resistor divider
to accept 3.3V.
O 3.3VSB
O 3.3VSB
O 3.3VSB
O 3.3VSB
I 3.3VSB
I 3.3VSB
PU 100k 5VSB
PU 10k 3.3VSB
PU 10k 3.3VSB
Not supported
I 3.3VSB
PU 10k 3.3VSB
I 3.3V
PU 10k 3.3V
O 3.3V
PU 10k 3.3V
I/O 3.3VSB PU 10k 3.3VSB
I/O OD
3.3VSB
I 3.3VSB
PU 10k 3.3VSB
PU 10k 3.3VSB
Copyright © 2012 congatec AG CTOPm10 45/85
Table 17 Power and GND Signal Descriptions
Signal
Pin #
Description
I/O
VCC_12V
A104-A109
B104-B109
B84-B87
Primary power input: +12V nominal. All available VCC_12V pins on the connector(s)
shall be used.
Standby power input: +5.0V nominal. If VCC5_SBY is used, all available VCC_5V_SBY
pins on the connector(s) shall be used. Only used for standby and suspend functions.
May be left unconnected if these functions are not used in the system design.
Real-time clock circuit-power input. Nominally +3.0V.
Ground - DC power and signal and AC signal return path.
All available GND connector pins shall be used and tied to Carrier Board GND plane.
P
VCC_5V_SBY
VCC_RTC
GND
A47
A1, A11, A21, A31, A41,
A51, A57, A66, A80,
A90, A96, A100, A110,
B1, B11, B21 ,B31, B41,
B51, B60, B70, B80,
B90, B100, B110
PU/PD
Comment
P
P
P
Copyright © 2012 congatec AG CTOPm10 46/85
8.2
A-B Connector Pinout
Table 18 Connector A-B Pinout
Pin
Row A
Pin
Row B
Pin
Row A
Pin
Row B
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
GND (FIXED)
GBE0_MDI3GBE0_MDI3+
GBE0_LINK100#
GBE0_LINK1000#
GBE0_MDI2GBE0_MDI2+
GBE0_LINK#
GBE0_MDI1GBE0_MDI1+
GND (FIXED)
GBE0_MDI0GBE0_MDI0+
GBE0_CTREF (*)
SUS_S3#
SATA0_TX+
SATA0_TXSUS_S4# (*)
SATA0_RX+
SATA0_RXGND (FIXED)
SATA2_TX+ (**)
SATA2_TX- (**)
SUS_S5#
SATA2_RX+ (**)
SATA2_RX- (**)
BATLOW#
(S)ATA_ACT#
AC/HDA_SYNC
AC/HDA_RST#
GND (FIXED)
AC/HDA_BITCLK
AC/HDA_SDOUT
BIOS_DIS0# (*)
THRMTRIP#
USB6- (*)
USB6+ (*)
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
GND (FIXED)
GBE0_ACT#
LPC_FRAME#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ0#
LPC_DRQ1#
LPC_CLK
GND (FIXED)
PWRBTN#
SMB_CK
SMB_DAT
SMB_ALERT#
SATA1_TX+
SATA1_TXSUS_STAT#
SATA1_RX+
SATA1_RXGND (FIXED)
SATA3_TX+ (**)
SATA3_TX- (**)
PWR_OK
SATA3_RX+ (**)
SATA3_RX- (**)
WDT
AC/HDA_SDIN2 (*)
AC/HDA_SDIN1
AC/HDA_SDIN0
GND (FIXED)
SPKR
I2C_CK
I2C_DAT
THRM#
USB7- (*)
USB7+ (*)
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
PCIE_TX4- (*)
GND
PCIE_TX3+ (*)
PCIE_TX3- (*)
GND (FIXED)
PCIE_TX2+ (*)
PCIE_TX2- (*)
GPI1
PCIE_TX1+
PCIE_TX1GND
GPI2
PCIE_TX0+
PCIE_TX0GND (FIXED)
LVDS_A0+
LVDS_A0LVDS_A1+
LVDS_A1LVDS_A2+
LVDS_A2LVDS_VDD_EN
LVDS_A3+
LVDS_A3GND (FIXED)
LVDS_A_CK+
LVDS_A_CKLVDS_I2C_CK
LVDS_I2C_DAT
GPI3
KBD_RST#
KBD_A20GATE (*)
PCIE0_CK_REF+
PCIE0_CK_REFGND (FIXED)
SPI_POWER
SPI_MISO
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
PCIE_RX4- (*)
GPO2
PCIE_RX3+ (*)
PCIE_RX3- (*)
GND (FIXED)
PCIE_RX2+ (*)
PCIE_RX2- (*)
GPO3
PCIE_RX1+
PCIE_RX1WAKE0#
WAKE1#
PCIE_RX0+
PCIE_RX0GND (FIXED)
LVDS_B0+ (*)
LVDS_B0- (*)
LVDS_B1+ (*)
LVDS_B1- (*)
LVDS_B2+ (*)
LVDS_B2- (*)
LVDS_B3+ (*)
LVDS_B3- (*)
LVDS_BKLT_EN
GND (FIXED)
LVDS_B_CK+ (*)
LVDS_B_CK- (*)
LVDS_BKLT_CTRL
VCC_5V_SBY
VCC_5V_SBY
VCC_5V_SBY
VCC_5V_SBY
BIOS_DIS1#
VGA_RED (*)
GND (FIXED)
VGA_GRN (*)
VGA_BLU (*)
Copyright © 2012 congatec AG CTOPm10 47/85
Pin
Row A
Pin
Row B
Pin
Row A
Pin
Row B
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
USB_6_7_OC# (*)
USB4USB4+
GND (FIXED)
USB2USB2+
USB_2_3_OC#
USB0USB0+
VCC_RTC
EXCD0_PERST#
EXCD0_CPPE#
LPC_SERIRQ
GND (FIXED)
PCIE_TX5+ (*)
PCIE_TX5- (*)
GPI0
PCIE_TX4+ (*)
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
USB_4_5_OC#
USB5USB5+
GND (FIXED)
USB3USB3+
USB_0_1_OC#
USB1USB1+
EXCD1_PERST# (*)
EXCD1_CPPE# (*)
SYS_RESET#
CB_RESET#
GND (FIXED)
PCIE_RX5+ (*)
PCIE_RX5- (*)
GPO1
PCIE_RX4+ (*)
A93
A94
A95
A96
A97
A98
A99
A100
A101
A102
A103
A104
A105
A106
A107
A108
A109
A110
GPO0
SPI_CLK
SPI_MOSI
GND
TYPE10#
RSVD
RSVD
GND (FIXED)
RSVD
RSVD
RSVD
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND (FIXED)
B93
B94
B95
B96
B97
B98
B99
B100
B101
B102
B103
B104
B105
B106
B107
B108
B109
B110
VGA_HSYNC (*)
VGA_VSYNC (*)
VGA_I2C_CK (*)
VGA_I2C_DAT (*)
SPI_CS#
RSVD
RSVD
GND (FIXED)
RSVD
RSVD
RSVD
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND (FIXED)
Note
The signals marked with an asterisk symbol (*) are not supported on the conga-CA6.
The signals marked with an asterisk symbol (**) are not supported on conga-CA6 industrial temperature range variants.
Copyright © 2012 congatec AG CTOPm10 48/85
8.3
C-D Connector Signal Descriptions
Table 19 PCI Signal Descriptions
Signal
Pin #
Description
I/O
PCI_AD[0, 2, 4,
6, 8, 10, 12]
PCI_AD[1, 3,
5, 7]
PCI_AD[9, 11,
13, 15]
PCI_AD14
PCI_AD[16, 18,
20, 22]
PCI_AD[17, 19]
PCI_AD[21, 23]
PCI_AD[24, 26,
28, 30]
PCI_AD[25, 27,
29, 31]
PCI_C/BE0#
PCI_C/BE1#
PCI_C/BE2#
PCI_C/BE3#
PCI_DEVSEL#
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_STOP#
PCI_PAR
PCI_PERR#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#
PCI_RESET#
PCI_LOCK#
PCI_SERR#
PCI_PME#
C24C30
D22D25
D27D30
C32
D37D40
C39-C40
C42-C43
D42D45
C45C48
D26
C33
C38
C44
C36
D36
C37
D35
D34
D32
C34
C22
C19
C17
D20
C20
C18
C16
D19
C23
C35
D33
C15
PCI bus multiplexed address and data lines
I/O 3.3V
PU/PD
PCI bus byte enable lines, active low
I/O 3.3V
PCI bus Device Select, active low.
PCI bus Frame control line, active low.
PCI bus Initiator Ready control line, active low.
PCI bus Target Ready control line, active low.
PCI bus STOP control line, active low, driven by cycle initiator.
PCI bus parity
Parity Error: An external PCI device drives PERR# when it receives data that has a parity error.
PCI bus master request input lines, active low.
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I/O 3.3V
I 3.3V
PU 4K75 3.3V
PU 4K75 3.3V
PU 4K75 3.3V
PU 4K75 3.3V
PU 4K75 3.3V
PCI bus master grant output lines, active low.
O 3.3V
PU 4k75 3.3V
PCI Reset output, active low.
PCI Lock control line, active low.
System Error: SERR# may be pulsed active by any PCI device that detects a system error condition.
PCI Power Management Event: PCI peripherals drive PME# to wake system from low-power states
S1–S5.
O 3.3V
I/O 3.3V
I/O 3.3V
I/O OD
3.3VSB
PU 4K75 3.3V
PU 4K75 3.3V
PU 10k
3.3VSB
Comment
PU 4K75 3.3V
PU 4K75 3.3V
Copyright © 2012 congatec AG CTOPm10 49/85
Signal
Pin #
Description
I/O
PCI_CLKRUN#
PCI_IRQA#
PCI_IRQB#
PCI_IRQC#
PCI_IRQD#
PCI_CLK
PCI_M66EN
D48
C49
C50
D46
D47
D50
D49
Bidirectional pin used to support PCI clock run protocol for mobile systems.
PCI interrupt request lines.
I/O 3.3V PU 10k 3.3V
I 3.3V
PU 4K75 3.3V
PU/PD
PCI 33MHz clock output.
Module input signal indicates whether an off‑module PCI device is capable of 66MHz operation.
Pulled to GND by Carrier Board device or by Slot Card if the devices are NOT capable of 66MHz
operation.
If the module is not capable of supporting 66MHz PCI operation, this input may be a no-connect on
the module.
If the module is capable of supporting 66MHz PCI operation, and if this input is held low by the
Carrier Board, the module PCI interface shall operate at 33MHz.
O 3.3V
I 3.3V
Comment
Not connected
Note
The PCI interface is specified to be +5V tolerant, with +3.3V signaling.
Copyright © 2012 congatec AG CTOPm10 50/85
Table 20 IDE Signal Descriptions
Signal
Pin #
Description
I/O
IDE_D0
IDE_D1
IDE_D2
IDE_D3
IDE_D4
IDE_D5
IDE_D6
IDE_D7
IDE_D8
IDE_D9
IDE_D10
IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15
IDE_A[0.2]
IDE_IOW#
IDE_IOR#
IDE_REQ
IDE_ACK#
IDE_CS1#
IDE_CS3#
IDE_IORDY
IDE_RESET#
IDE_IRQ
IDE_CBLID#
D7
C10
C8
C4
D6
D2
C3
C2
C6
C7
D3
D4
D5
C9
C12
C5
D13-D15
D9
C14
D8
D10
D16
D17
C13
D18
D12
D77
Bidirectional data to / from IDE device.
I/O 3.3V
Address lines to IDE device.
I/O write line to IDE device. Data latched on trailing (rising) edge.
I/O read line to IDE device.
IDE Device DMA Request. It is asserted by the IDE device to request a data transfer.
IDE Device DMA Acknowledge.
IDE Device Chip Select for 1F0h to 1FFh range.
IDE Device Chip Select for 3F0h to 3FFh range.
IDE device I/O ready input. Pulled low by the IDE device to extend the cycle.
Reset output to IDE device, active low.
Interrupt request from IDE device.
Input from off-module hardware indicating the type of IDE cable being used. High indicates a
40-pin cable used for legacy IDE modes. Low indicates that an 80-pin cable with interleaved
grounds is used. Such a cable is required for Ultra-DMA 66, 100 and 133 modes.
O 3.3V
O 3.3V
O 3.3V
I 3.3V
O 3.3V
O 3.3V
O 3.3V
I 3.3V
O 3.3V
I 3.3V
I 3.3V
PU/PD
Comment
Note
The IDE interface is specified to be +5V tolerant, with +3.3V signaling.
Copyright © 2012 congatec AG CTOPm10 51/85
Table 21 PCI Express Signal Descriptions (x16 Graphics)
Signal
Pin # Description
PEG_RX0+
PEG_RX0PEG_RX1+
PEG_RX1PEG_RX2+
PEG_RX2PEG_RX3+
PEG_RX3PEG_RX4+
PEG_RX4PEG_RX5+
PEG_RX5PEG_RX6+
PEG_RX6PEG_RX7+
PEG_RX7PEG_RX8+
PEG_RX8PEG_RX9+
PEG_RX9PEG_RX10+
PEG_RX10PEG_RX11+
PEG_RX11PEG_RX12+
PEG_RX12PEG_RX13+
PEG_RX13PEG_RX14+
PEG_RX14PEG_RX15+
PEG_RX15-
C52
C53
C55
C56
C58
C59
C61
C62
C65
C66
C68
C69
C71
C72
C74
C75
C78
C79
C81
C82
C85
C86
C88
C89
C91
C92
C94
C95
C98
C99
C101
C102
I/O
I PCIE
PCI Express Graphics Receive Input differential pairs. Some of these lines are multiplexed
with SDVO lines.
Note: Can also be used as PCI Express Receive Input differential pairs 16 through 31 known
as PCIE_RX[16-31] + and -.
PU/PD
Comment
PCI Express Graphics (PEG) is
not supported on the
conga-CA6 (see note below).
Copyright © 2012 congatec AG CTOPm10 52/85
Signal
Pin # Description
PEG_TX0+
PEG_TX0PEG_TX1+
PEG_TX1PEG_TX2+
PEG_TX2PEG_TX3+
PEG_TX3PEG_TX4+
PEG_TX4PEG_TX5+
PEG_TX5PEG_TX6+
PEG_TX6PEG_TX7+
PEG_TX7PEG_TX8+
PEG_TX8PEG_TX9+
PEG_TX9PEG_TX10+
PEG_TX10PEG_TX11+
PEG_TX11PEG_TX12+
PEG_TX12PEG_TX13+
PEG_TX13PEG_TX14+
PEG_TX14PEG_TX15+
PEG_TX15PEG_LANE_RV#
D52
D53
D55
D56
D58
D59
D61
D62
D65
D66
D68
D69
D71
D72
D74
D75
D78
D79
D81
D82
D85
D86
D88
D89
D91
D92
D94
D95
D98
D99
D101
D102
D54
PEG_ENABLE#
D97
I/O
PU/PD
Comment
PCI Express Graphics Transmit Output differential pairs. Some of these lines are multiplexed O PCIE
with SDVO lines.
Note: Can also be used as PCI Express Transmit Output differential pairs 16 through 31
known as PCIE_TX[16-31] + and -.
Not supported
PCI Express Graphics lane reversal input strap. Pull low on the carrier board to reverse lane I 1.05V
order.
Strap to enable PCI Express x16 external graphics interface.
I 3.3V
Not supported
Not supported
Note
The PCI Express Graphics (PEG) signals are multiplexed with HDMI, DisplayPort (DP) and SDVO. The signals for these interfaces are routed
to the PEG interface of the COM Express connector. Refer to the SDVO, HDMI and DiplayPort signal description tables in this section for
information about the signals routed to the PEG interface of the COM Express connector.
Copyright © 2012 congatec AG CTOPm10 53/85
Table 22 SDVO Signal Descriptions
Signal
Pin # Description
I/O
SDVOB_RED+
SDVOB_REDSDVOB_GRN+
SDVOB_GRNSDVOB_BLU+
SDVOB_BLUSDVOB_CK+
SDVOB_CKSDVOB_INT+
SDVOB_INTSDVOC_RED+
SDVOC_REDSDVOC_GRN+
SDVOC_GRNSDVOC_BLU+
SDVOC_BLUSDVOC_CK+
SDVOC_CKSDVOC_INT+
SDVOC_INTSDVO_TVCLKIN+
SDVO_TVCLKINSDVO_FLDSTALL+
SDVO_FLDSTALLSDVO_I2C_CK
(SDVO_CLK)
SDVO_I2C_DAT
(SDVO_DATA)
D52
D53
D55
D56
D58
D59
D61
D62
C55
C56
D65
D66
D68
D69
D71
D72
D74
D75
C68
C69
C52
C53
C58
C59
D73
Serial Digital Video B red output differential pair.
Multiplexed with PEG_TX[0]+ and PEG_TX[0]- pair.
Serial Digital Video B green output differential pair.
Multiplexed with PEG_TX[1]+ and PEG_TX[1]-.
Serial Digital Video B blue output differential pair.
Multiplexed with PEG_TX[2]+ and PEG_TX[2]-.
Serial Digital Video B clock output differential pair.
Multiplexed with PEG_TX[3]+ and PEG_TX[3]-.
Serial Digital Video B interrupt input differential pair.
Multiplexed with PEG_RX[1]+ and PEG_RX[1]-.
Serial Digital Video C red output differential pair.
Multiplexed with PEG_TX[4]+ and PEG_TX[4]-.
Serial Digital Video C green output differential pair.
Multiplexed with PEG_TX[5]+ and PEG_TX[5]-.
Serial Digital Video C blue output differential pair.
Multiplexed with PEG_TX[6]+ and PEG_TX[6]-.
Serial Digital Video C clock output differential pair.
Multiplexed with PEG_TX[7]+ and PEG_TX[7]-.
Serial Digital Video C interrupt input differential pair.
Multiplexed with PEG_RX[5]+ and PEG_RX[5]-.
Serial Digital Video TVOUT synchronization clock input differential pair.
Multiplexed with PEG_RX[0]+ and PEG_RX[0]-.
Serial Digital Video Field Stall input differential pair.
Multiplexed with PEG_RX[2]+ and PEG_RX[2]-.
SDVO I²C clock line to set up SDVO peripherals.
O PCIE
C73
SDVO I²C data line to set up SDVO peripherals.
I/O
OD 2.5V
PU/PD Comment
O PCIE
O PCIE
O PCIE
I PCIE
O PCIE
Not supported
O PCIE
Not supported
O PCIE
Not supported
O PCIE
Not supported
I PCIE
Not supported
I PCIE
I PCIE
O 3.3V
SDVO_I2C_DAT is a bootstrap signal (see note
below)
Note
Some signals have special functionality during the reset process. They may bootstrap some basic important functions of the module. For more
information refer to section 8.5 of this user’s guide.
Copyright © 2012 congatec AG CTOPm10 54/85
Table 23 HDMI Signal Descriptions
Signal
Pin # Description
I/O
TMDS_B_CLK +
TMDS_B_CLK TMDS_B_DATA0+
TMDS_B_DATA0TMDS_B_DATA1+
TMDS_B_DATA1TMDS_B_DATA2+
TMDS_B_DATA2TMDS_B_HPD
D61
D62
D58
D59
D55
D56
D52
D53
C61
O PCIE
Not supported
O PCIE
Not supported
O PCIE
Not supported
O PCIE
Not supported
I PCIE
Not supported
DDPB_CTRLCLK
D73
HDMI Port B Clock output differential pair.
Multiplexed with PEG_TX[3]+ and PEG_TX[3]- pair.
HDMI Port B Data0 output differential pair.
Multiplexed with PEG_TX[2]+ and PEG_TX[2]-.
HDMI Port B Data1 output differential pair.
Multiplexed with PEG_TX[1]+ and PEG_TX[1]-.
HDMI Port B Data2 output differential pair.
Multiplexed with PEG_TX[0]+ and PEG_TX[0]-.
HDMI Port B Hot-plug detect.
Multiplexed with PEG_RX[3]+.
HDMI port B Control Clock
PU/PD
Comment
I/O 3.3V
Not supported
DDPB_CTRLDATA
C73
HDMI port B Control Data
I/O 3.3V
Not supported
TMDS_C_CLK +
TMDS_C_CLK TMDS_C_DATA0+
TMDS_C_DATA0TMDS_C_DATA1+
TMDS_C_DATA1TMDS_C_DATA2+
TMDS_C_DATA2TMDS_C_HPD
D74
D75
D71
D72
D68
D69
D65
D66
C74
O PCIE
Not supported
O PCIE
Not supported
O PCIE
Not supported
O PCIE
Not supported
I PCIE
Not supported
DDPC_CTRLCLK
DDPC_CTRLDATA
TMDS_D_CLK +
TMDS_D_CLK TMDS_D_DATA0+
TMDS_D_DATA0TMDS_D_DATA1+
TMDS_D_DATA1TMDS_D_DATA2+
TMDS_D_DATA2TMDS_D_HPD
D63
D64
D88
D89
D85
D86
D81
D82
D78
D79
C88
I/O 3.3V
I/O 3.3V
O PCIE
Not supported
Not supported
Not supported
O PCIE
Not supported
O PCIE
Not supported
O PCIE
Not supported
I PCIE
Not supported
DDPD_CTRLCLK
DDPD_CTRLDATA
C97
D83
HDMI Port C Clock output differential pair.
Multiplexed with PEG_TX[7]+ and PEG_TX[7]- pair.
HDMI Port C Data0 output differential pair.
Multiplexed with PEG_TX[6]+ and PEG_TX[6]-.
HDMI Port C Data1 output differential pair.
Multiplexed with PEG_TX[5]+ and PEG_TX[5]-.
HDMI Port C Data2 output differential pair.
Multiplexed with PEG_TX[4]+ and PEG_TX[4]-.
HDMI Port C Hot-plug detect.
Multiplexed with PEG_RX[7]+.
HDMI port C Control Clock
HDMI port C Control Data
HDMI Port D Clock output differential pair.
Multiplexed with PEG_TX[11]+ and PEG_TX[11]- pair.
HDMI Port D Data0 output differential pair.
Multiplexed with PEG_TX[10]+ and PEG_TX[10]-.
HDMI Port D Data1 output differential pair.
Multiplexed with PEG_TX[9]+ and PEG_TX[9]-.
HDMI Port D Data2 output differential pair.
Multiplexed with PEG_TX[8]+ and PEG_TX[8]-.
HDMI Port C Hot-plug detect.
Multiplexed with PEG_RX[11]+.
HDMI port D Control Clock
HDMI port D Control Data
I/O 3.3V
I/O 3.3V
Not supported
Not supported
Copyright © 2012 congatec AG CTOPm10 55/85
Table 24 DisplayPort (DP) Signal Descriptions
Signal
Pin # Description
I/O
DPB_LANE3+
DPB_LANE3DPB_LANE2+
DPB_LANE2DPB_LANE1+
DPB_LANE1DPB_LANE0+
DPB_LANE0DPB_HPD
D61
D62
D58
D59
D55
D56
D52
D53
C61
O PCIE
Not supported
O PCIE
Not supported
O PCIE
Not supported
O PCIE
Not supported
I PCIE
Not supported
DPB_AUX+
DPB_AUXDDPB_CTRLDATA
DPC_LANE3+
DPC_LANE3DPC_LANE2+
DPC_LANE2DPC_LANE1+
DPC_LANE1DPC_LANE0+
DPC_LANE0DPC_HPD
C58
C59
C73
D74
D75
D71
D72
D68
D69
D65
D66
C74
I PCIE
Not supported
I/O 3.3V
O PCIE
Not supported
Not supported
O PCIE
Not supported
O PCIE
Not supported
O PCIE
Not supported
I PCIE
Not supported
DPC_AUX+
DPC_AUXDDPC_CTRLDATA
DPD_LANE3+
DPD_LANE3DPD_LANE2+
DPD_LANE2DPD_LANE1+
DPD_LANE1DPD_LANE0+
DPD_LANE0DPD_HPD
C71
C72
D64
D88
D89
D85
D86
D81
D82
D78
D79
C88
I PCIE
Not supported
I/O 3.3V
O PCIE
Not supported
Not supported
O PCIE
Not supported
O PCIE
Not supported
O PCIE
Not supported
I PCIE
Not supported
I PCIE
Not supported
I/O 3.3V
Not supported
DPD_AUX+
C85
DPD_AUXC86
DDPD_CTRLDATA D83
DisplayPort B Lane3 output differential pair.
Multiplexed with PEG_TX[3]+ and PEG_TX[3]- pair.
DisplayPort B Lane2 output differential pair.
Multiplexed with PEG_TX[2]+ and PEG_TX[2]- pair.
DisplayPort B Lane1 output differential pair.
Multiplexed with PEG_TX[1]+ and PEG_TX[1]- pair.
DisplayPort B Lane0 output differential pair.
Multiplexed with PEG_TX[0]+ and PEG_TX[0]- pair.
DisplayPort B Hot-plug detect.
Multiplexed with PEG_RX[3]+.
DisplayPort B Aux input differential pair.
Multiplexed with PEG_RX[2]+ and PEG_RX[2]- pair.
Digital Display port B Control Data
DisplayPort C Lane3 output differential pair.
Multiplexed with PEG_TX[7]+ and PEG_TX[7]- pair.
DisplayPort C Lane2 output differential pair.
Multiplexed with PEG_TX[6]+ and PEG_TX[6]- pair.
DisplayPort C Lane1 output differential pair.
Multiplexed with PEG_TX[5]+ and PEG_TX[5]- pair.
DisplayPort C Lane0 output differential pair.
Multiplexed with PEG_TX[4]+ and PEG_TX[4]- pair.
DisplayPort C Hot-plug detect.
Multiplexed with PEG_RX[7]+.
DisplayPort C Aux input differential pair.
Multiplexed with PEG_RX[6]+ and PEG_RX[6]- pair.
Digital Display port C Control Data
DisplayPort D Lane3 output differential pair.
Multiplexed with PEG_TX[11]+ and PEG_TX[11]- pair.
DisplayPort D Lane2 output differential pair.
Multiplexed with PEG_TX[10]+ and PEG_TX[10]- pair.
DisplayPort D Lane1 output differential pair.
Multiplexed with PEG_TX[9]+ and PEG_TX[9]- pair.
DisplayPort D Lane0 output differential pair.
Multiplexed with PEG_TX[8]+ and PEG_TX[8]- pair.
DisplayPort D Hot-plug detect.
Multiplexed with PEG_RX[11]+.
DisplayPort D Aux input differential pair.
Multiplexed with PEG_RX[10]+ and PEG_RX[10]- pair.
Digital Display port C Control Data
PU/PD Comment
Copyright © 2012 congatec AG CTOPm10 56/85
Table 25 Module Type Definition Signal Description
Signal
Pin #
Description
I/O
Comment
TYPE0#
TYPE1#
TYPE2#
C54
C57
D57
The TYPE pins indicate to the Carrier Board the Pin-out Type that is implemented on the module. The pins are tied on
the module to either ground (GND) or are no-connects (NC). For Pinout Type 1, these pins are don’t care (X).
TYPE2#
TYPE1#
TYPE0#
PDS
TYPE[0:2]# signals are
available on all modules
following the Type 2-6
Pinout standard.
The conga-BM67/BS67
is based on the COM
Express Type 2 pinout
therefore these pins are
not connected.
X
NC
NC
NC
NC
GND
X
NC
NC
GND
GND
NC
X
NC
GND
NC
GND
NC
Pinout Type 1
Pinout Type 2
Pinout Type 3 (no IDE)
Pinout Type 4 (no PCI)
Pinout Type 5 (no IDE, no PCI)
Pinout Type 6 (no IDE, no PCI)
The Carrier Board should implement combinatorial logic that monitors the module TYPE pins and keeps power off
(e.g deactivates the ATX_ON signal for an ATX power supply) if an incompatible module pin-out type is detected. The
Carrier Board logic may also implement a fault indicator such as an LED.
TYPE10# A97
Dual use pin. Indicates to the carrier board that a Type 10 module is installed. Indicates to the carrier that a Rev. 1.0/2.0 PDS
module is installed.
Not supported
TYPE10#
NC
PD
12V
Pinout R2.0
Pinout Type 10 pull down to ground with 4.7k resistor
Pinout R1.0
This pin is reclaimed from VCC_12V pool. In R1.0 modules this pin will connect to other VCC_12V pins. In R2.0 this pin
is defined as a no-connect for Types 1-6. A carrier can detect a R1.0 module by the presence of 12V on this pin. R2.0
module Types 1-6 will no-connect this pin. Type 10 modules shall pull this pin to ground through a 4.7k resistor.
Table 26 Power and GND Signal Descriptions
Signal
Pin #
VCC_12V
C104-C109
Primary power input: +12V nominal. All available VCC_12V pins on the connector(s) shall be used. P
D104-D109
Ground - DC power and signal and AC signal return path.
P
C1, C11, C21, C31,
C41, C51, C60, C70, All available GND connector pins shall be used and tied to carrier board GND plane.
C76, C80, C84, C87,
C90, C93, C96, C100,
C103, C110, D1, D11,
D21, D31, D41, D51,
D60, D67, D70, D76,
D80, D84, D87, D90,
D93, D96, D100,
D103, D110
GND
Description
I/O
Copyright © 2012 congatec AG CTOPm10 PU/PD Comment
57/85
Table 27 Miscellaneous Signal Descriptions
Signal
Pin # Description
FAN_PWMOUT C67
FAN_TACHOIN
C77
PP_TPM
C83
I/O
Fan speed control. Uses the Pulse Width Modulation (PWM) technique to control the O OD
fan’s RPM.
3.3V
Fan tachometer input.
I OD
Physical Presence pin of Trusted Platform Module (TPM). Active high. TPM chip has I 3.3V
an internal pull‑down. This signal is used to indicate Physical Presence to the TPM.
PU/PD Comment
PU 10k
3.3V
PU 10k Requires a fan with a two pulse output.
3.3V
The conga-CA6 does not support Trusted
Platform Module (TPM).
Copyright © 2012 congatec AG CTOPm10 58/85
8.4
C-D Connector Pinout
Table 28 Connector C-D Pinout
Pin
Row C
Pin
Row D
Pin
Row C
Pin
Row D
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C27
C28
C29
C30
C31
C32
C33
C34
C35
C36
C37
GND (FIXED)
IDE_D7 (**)
IDE_D6 (**)
IDE_D3 (**)
IDE_D15 (**)
IDE_D8 (**)
IDE_D9 (**)
IDE_D2 (**)
IDE_D13 (**)
IDE_D1 (**)
GND (FIXED)
IDE_D14 (**)
IDE_IORDY (**)
IDE_IOR# (**)
PCI_PME#
PCI_GNT2#
PCI_REQ2#
PCI_GNT1#
PCI_REQ1#
PCI_GNT0#
GND (FIXED)
PCI_REQ0#
PCI_RESET#
PCI_AD0
PCI_AD2
PCI_AD4
PCI_AD6
PCI_AD8
PCI_AD10
PCI_AD12
GND (FIXED)
PCI_AD14
PCI_C/BE1#
PCI_PERR#
PCI_LOCK#
PCI_DEVSEL#
PCI_IRDY#
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
GND (FIXED)
IDE_D5 (**)
IDE_D10 (**)
IDE_D11 (**)
IDE_D12 (**)
IDE_D4 (**)
IDE_D0 (**)
IDE_REQ (**)
IDE_IOW# (**)
IDE_ACK# (**)
GND (FIXED)
IDE_IRQ (**)
IDE_A0 (**)
IDE_A1 (**)
IDE_A2 (**)
IDE_CS1# (**)
IDE_CS3# (**)
IDE_RESET# (**)
PCI_GNT3# (*)
PCI_REQ3# (*)
GND (FIXED)
PCI_AD1
PCI_AD3
PCI_AD5
PCI_AD7
PCI_C/BE0#
PCI_AD9
PCI_AD11
PCI_AD13
PCI_AD15
GND (FIXED)
PCI_PAR
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PCI_AD16
C56
C57
C58
C59
C60
C61
C62
C63
C64
C65
C66
C67
C68
C69
C70
C71
C72
C73
C74
C75
C76
C77
C78
C79
C80
C81
C82
C83
C84
C85
C86
C87
C88
C89
C90
C91
C92
PEG_RX1TYPE1#
PEG_RX2+
PEG_RX2GND (FIXED)
PEG_RX3+ (*)
PEG_RX3- (*)
RSVD
RSVD
PEG_RX4+ (*)
PEG_RX4- (*)
FAN_PWMOUT
PEG_RX5+ (*)
PEG_RX5- (*)
GND (FIXED)
PEG_RX6+ (*)
PEG_RX6- (*)
SDVO_DATA
PEG_RX7+ (*)
PEG_RX7- (*)
GND
FAN_TACHOIN
PEG_RX8+ (*)
PEG_RX8- (*)
GND (FIXED)
PEG_RX9+ (*)
PEG_RX9- (*)
PP_TPM
GND
PEG_RX10+ (*)
PEG_RX10- (*)
GND
PEG_RX11+ (*)
PEG_RX11-(*)
GND (FIXED)
PEG_RX12+ (*)
PEG_RX12- (*)
D56
D57
D58
D59
D60
D61
D62
D63
D64
D65
D66
D67
D68
D69
D70
D71
D72
D73
D74
D75
D76
D77
D78
D79
D80
D81
D82
D83
D84
D85
D86
D87
D88
D89
D90
D91
D92
PEG_TX1TYPE2#
PEG_TX2+
PEG_TX2GND (FIXED)
PEG_TX3+
PEG_TX3DDPC_CTRLCLK (*)
DDPC_CTRLDATA (*)
PEG_TX4+ (*)
PEG_TX4- (*)
GND
PEG_TX5+ (*)
PEG_TX5- (*)
GND (FIXED)
PEG_TX6+ (*)
PEG_TX6- (*)
SVDO_CLK
PEG_TX7+ (*)
PEG_TX7- (*)
GND
IDE_CBLID# (**)
PEG_TX8+ (*)
PEG_TX8- (*)
GND (FIXED)
PEG_TX9+ (*)
PEG_TX9- (*)
RSVD
GND
PEG_TX10+ (*)
PEG_TX10- (*)
GND
PEG_TX11+ (*)
PEG_TX11- (*)
GND (FIXED)
PEG_TX12+ (*)
PEG_TX12- (*)
Copyright © 2012 congatec AG CTOPm10 59/85
Pin
Row C
Pin
Row D
Pin
Row C
Pin
Row D
C38
C39
C40
C41
C42
C43
C44
C45
C46
C47
C48
C49
C50
C51
C52
C53
C54
C55
PCI_C/BE2#
PCI_AD17
PCI_AD19
GND (FIXED)
PCI_AD21
PCI_AD23
PCI_C/BE3#
PCI_AD25
PCI_AD27
PCI_AD29
PCI_AD31
PCI_IRQA#
PCI_IRQB#
GND (FIXED)
PEG_RX0+
PEG_RX0TYPE0#
PEG_RX1+
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
PCI_AD18
PCI_AD20
PCI_AD22
GND (FIXED)
PCI_AD24
PCI_AD26
PCI_AD28
PCI_AD30
PCI_IRQC#
PCI_IRQD#
PCI_CLKRUN#
PCI_M66EN (*)
PCI_CLK
GND (FIXED)
PEG_TX0+
PEG_TX0PEG_LANE_RV# (*)
PEG_TX1+
C93
C94
C95
C96
C97
C98
C99
C100
C101
C102
C103
C104
C105
C106
C107
C108
C109
C110
GND
PEG_RX13+ (*)
PEG_RX13- (*)
GND
RVSD
PEG_RX14+ (*)
PEG_RX14- (*)
GND (FIXED)
PEG_RX15+ (*)
PEG_RX15- (*)
GND
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND (FIXED)
D93
D94
D95
D96
D97
D98
D99
D100
D101
D102
D103
D104
D105
D106
D107
D108
D109
D110
GND
PEG_TX13+ (*)
PEG_TX13- (*)
GND
PEG_ENABLE#
PEG_TX14+ (*)
PEG_TX14- (*)
GND (FIXED)
PEG_TX15+ (*)
PEG_TX15- (*)
GND
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
VCC_12V
GND (FIXED)
Note
The signals marked with an asterisk symbol (*) are not supported on the conga-CA6.
The signals marked with an asterisk symbol (**) are not supported on conga-CA6 industrial temperature range variants.
Copyright © 2012 congatec AG CTOPm10 60/85
8.5
Bootstrap Signals
Table 29 Bootstrap Signal Descriptions
Signal
Pin # Description of Bootstrap Signal
I/O
PU/PD Comment
GBE0_ACT#
B2
Gigabit Ethernet Controller 0 activity indicator, active low.
I/O
2.5VSB
GBE0_LINK#
A8
Gigabit Ethernet Controller 0 link indicator, active low.
O
3.3VSB
PU
GBE0_ACT# is a bootstrap signal (see
4k99
caution statement below)
2.5VSB
PD 1k
GBE0_LINK# is a bootstrap signal (see
caution statement below)
GBE0_LINK100#
A4
Gigabit Ethernet Controller 0 100Mbit/sec link indicator, active low.
I/O
2.5VSB
GBE0_LINK1000#
A5
Gigabit Ethernet Controller 0 1000Mbit/sec link indicator, active low.
LVDS_I2C_DAT
A84
DDC lines used for flat panel detection and control.
SPKR
B32
Output for audio enunciator, the “speaker” in PC-AT systems
SDVO_I2C_DAT
(SDVO_DATA)
C73
SDVO I²C data line to set up SDVO peripherals.
PU
GBE0_LINK100# is a bootstrap signal
4k99
(see caution statement below)
2.5VSB
O
PD 1k
GBE0_LINK1000# is a bootstrap signal
3.3VSB
(see caution statement below)
I/O 3.3V PU 2k2 LVDS_I2C_DAT is a bootstrap signal
3.3V
(see caution statement below).
O 3.3V
SPKR is a bootstrap signal (see caution
statement below)
I/O 3.3V
SDVO_I2C_DAT is a bootstrap signal
(see caution statement below)
Caution
The signals listed in the table above are used as chipset configuration straps during system reset. In this condition (during reset), they are
inputs that are pulled to the correct state by either COM Express™ internally implemented resistors or chipset internally implemented resistors
that are located on the module. No external DC loads or external pull-up or pull-down resistors should change the configuration of the signals
listed in the above table. External resistors may override the internal strap states and cause the COM Express™ module to malfunction and/or
cause irreparable damage to the module.
Copyright © 2012 congatec AG CTOPm10 61/85
9
System Resources
9.1
I/O Address Assignment
The I/O address assignment of the conga-CA6 module is functionally identical with a standard PC/AT. The most important addresses and the
ones that differ from the standard PC/AT configuration are listed in the table below.
Note
The BIOS assigns PCI and PCI Express I/O resources from FFF0h downwards. Non PnP/PCI/PCI Express compliant devices must not
consume I/O resources in that area.
9.2
Interrupt Request (IRQ) Lines
Table 30 IRQ Lines in PIC mode
IRQ#
Available
Typical Interrupt Source
Connected to Pin
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
No
No
No
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
No
Note
Note
Counter 0
Keyboard
Cascade Interrupt from Slave PIC
Not applicable
Not applicable
Not applicable
IRQ3 via SERIRQ or PCI BUS INTx
IRQ4 via SERIRQ or PCI BUS INTx
IRQ5 via SERIRQ
IRQ6 via SERIRQ or PCI BUS INTx
IRQ7 via SERIRQ or PCI BUS INTx
Not applicable
Not applicable
IRQ10 via SERIRQ or PCI BUS INTx
IRQ11 via SERIRQ or PCI BUS INTx
IRQ12 via SERIRQ or PCI BUS INTx
Not applicable
IRQ14 via SERIRQ or PCI BUS INTx
IRQ15 via SERIRQ or PCI BUS INTx
Real-time Clock
SCI
Math processor
IDE Controller 0 (IDE0) / Generic
IDE Controller 1 (IDE1) / Generic
In PIC mode, the PCIe bus interrupt lines can be routed to any free IRQ.
Note
If the SATA and PATA interface mode configuration in BIOS setup is NOT set to legacy IDE mode, IRQ14 and 15 are free for PCI/LPC bus. In
Copyright © 2012 congatec AG CTOPm10 62/85
ACPI mode, IRQ9 is used for the SCI (System Control Interrupt). The SCI can be shared with a PCIe interrupt line.
Table 31 IRQ Lines in APIC mode
IRQ#
Available
Typical Interrupt Source
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
No
No
No
Yes
Yes
Yes
Yes
Yes
No
Note
Yes
Yes
No
No
Yes
Yes
No
17
18
19
20
21
22
23
No
No
No
Yes
Yes
Yes
Yes
Counter 0
Not applicable
Keyboard
Not applicable
Cascade Interrupt from Slave PIC Not applicable
LPC bus via SERIRQ
LPC bus via SERIRQ
LPC bus via SERIRQ
LPC bus via SERIRQ
LPC bus via SERIRQ
Real-time Clock
Not applicable
Generic
LPC bus via SERIRQ , option for SCI
LPC bus via SERIRQ
LPC bus via SERIRQ
LPC bus via SERIRQ exclusively
Math processor
Not applicable
LPC bus via SERIRQ
LPC bus via SERIRQ
PIRQA, Integrated Graphics Device, HDA Controller, PCIe Bridge #0, PCIe Port #1slot, PCIe Port #2slot, PCIe Port
#3slot, PCIe Root Port #0, PCIe Root Port #1, PCIe Root Port #2, PCIe Root Port #3, OHCI Host#1
PIRQB, PCIe Bridge #0, PCIe Port #1slot, PCIe Port #2slot, PCIe Port #3slot, AHCI Controller
PIRQC,PCIe Bridge #0, PCIe Port #1slot, PCIe Port #2slot, PCIe Port #3slot, SDIO Host#0, SDIO Host#1
PIRQD, PCIe Bridge #0, PCIe Port #1slot, PCIe Port #2slot, PCIe Port #3slot, OHCI Host#0, USB Device
PIRQE
PIRQF
PIRQG
PIRQH
Connected to Pin / Function
In APIC mode, the PCI bus interrupt lines are connected with IRQ 20, 21, 22 and 23.
Note
In ACPI and APIC mode, IRQ9 or IRQ20 is used for the SCI (System Control Interrupt).
Copyright © 2012 congatec AG CTOPm10 63/85
9.3
PCI Configuration Space Map
Table 32 PCI Configuration Space Map
Bus Number (hex) Device Number (hex) Function Number (hex) PCI Interrupt Routing Description
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
01h
02h
02h
02h
02h
02h
02h
02h
02h
02h
02h
02h
02h
02h
02h
02h
02h
02h
02h
02h
02h
02h
02h
02h
02h
03h
00h
01h
02h
03h
17h
18h
19h
1Ah
1Bh
1Fh
00h
00h
00h
00h
02h
02h
02h
02h
02h
04h
04h
06h
08h
08h
08h
08h
0Ah
0Ah
0Ah
0Ah
0Ah
0Ch
0Ch
0Ch
0Ch
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
01h
02h
00h
01h
02h
03h
04h
00h
01h
00h
00h
01h
02h
03h
00h
01h
02h
03h
04h
00h
01h
02h
03h
00h
N.A.
N.A.
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Host Bridge
Device ID 4114h
IGD (integrated graphics device)
SDVO Unit Display
PCIe Port 0
PCIe Port 1
PCIe Port 2
PCIe Port 3
Intel High Definition Audio
LPC Interface
PCI Express Bridge
Packet Hub Control
Gigabit Ethernet MAC
GPIO
USB 2.0 OHCI Host #1
USB 2.0 OHCI Host #1
USB 2.0 OHCI Host #1
USB 2.0 OHCI Host #1
USB Device
SDIO #0
SDIO #1
SATA
USB 2.0 OHCI Host #2
USB 2.0 OHCI Host #2
USB 2.0 OHCI Host #2
USB 2.0 OHCI Host #2
Shared DMA
UART #0
UART #1
UART #2
UART #3
Shared DMA
SPI
I2C
CAN
PCI to PCI Bridge
Copyright © 2012 congatec AG CTOPm10 64/85
04h
03h
00h
Internal
RAID Controller
Note
The given bus numbers only apply to a conga-CA6 supporting onboard Gbe LAN with both PCI Express Ports being enabled in the BIOS setup.
When using carrier boards with a PCIe packet switch at PCIe slot 1 the bus number of the Onboard LAN controller is increased by the number
of PCI bridges within the switch.
9.4
PCI Interrupt Routing Map
Table 33 PCI Interrupt Routing Map
PIRQ
A
B
C
D
E
F
G
H
PCI BUS INT
Line ¹
APIC Mode IGD
IRQ
SDVO HDA PCIe Root PCIe Root PCIe Root PCIe Root OHCI
Port 0
Port 1
Port 2
Port 3
Host #0
x
INTA
INTB
INTC
INTD
16
17
18
19
20
21
22
23
x
x
x
x
x
EHCI
Host #0
USB
Device
x
OHCI
Host #1
x
x
x
x
Table 34 PCI Interrupt Routing Map (continued)
PIRQ EHCI
Host #1
A
B
C
D
E
F
G
H
DMA
SPI
I2C
CAN
UART
SATA
x
x
x
x
x
x
x
LAN
GPIO
PCIe Slot
Bridge 0
PCIe Slot PCIe Slot PCIe Slot
Port 1
Port 2
Port 3
x
x
x2
x3
x4
x5
x3
x4
x5
x2
x4
x5
x²
x³
x5
x²
x³
x4
Note
1
These interrupts are available for external devices/slots via the C-D connector rows.
2
Interrupt used by single function PCI Express devices (INTA).
Copyright © 2012 congatec AG CTOPm10 65/85
9.5
3
Interrupt used by multifunction PCI Express devices (INTB).
4
Interrupt used by multifunction PCI Express devices (INTC).
5
Interrupt used by multifunction PCI Express devices (INTD).
I²C Bus
There are no onboard resources connected to the I²C bus. Address 16h is reserved for congatec Battery Management solutions.
9.6
SM Bus
System Management (SM) bus signals are connected to the Intel® EG20T Chipset Hub and the SM bus is not intended to be used by off-board
non-system management devices. For more information about this subject please contact congatec technical support.
Copyright © 2012 congatec AG CTOPm10 66/85
10
BIOS Setup Description
The following section describes the BIOS setup program. The BIOS setup program can be used to view and change the BIOS settings for the
module. Only experienced users should change the default BIOS settings.
10.1
Entering the BIOS Setup Program.
The BIOS setup program can be accessed by pressing the <DEL> key during POST.
10.1.1
Boot Selection Popup
The BIOS offers the possibility to access a Boot Selection Popup menu by pressing the <F11> key during POST. If this option is used a
message will be displayed during POST stating that the “Boot Selection Popup menu has been selected” and the menu itself will be displayed
immediately after POST thereby allowing the operator to choose the boot device to be used.
10.2
Setup Menu and Navigation
The congatec BIOS setup screen is composed of the menu bar and two main frames. The menu bar is shown below:
Note
Entries in the option column that are displayed in bold print indicate BIOS default values.
Main
Advanced
Boot
Security
Save & Exit
The left frame displays all the options that can be configured in the selected menu. Grayed-out options cannot be configured. Only the blue
options can be configured. When an option is selected, it is highlighted in white.
The right frame displays the key legend. Above the key legend is an area reserved for text messages. These text messages explain the options
and the possible impacts when changing the selected option in the left frame.
The setup program uses a key-based navigation system. Most of the keys can be used at any time while in setup. The table below explains
the supported keys:
Copyright © 2012 congatec AG CTOPm10 67/85
10.3
Key
Description
← → Left/Right
↑ ↓ Up/Down
+ - Plus/Minus
Tab
F1
F2
F9
F10
ESC
ENTER
Select a setup menu (e.g. Main, Boot, Exit).
Select a setup item or sub menu.
Change the field value of a particular setup item.
Select setup fields (e.g. in date and time).
Display General Help screen.
Load previous values.
Load optimal default settings.
Save changes and exit setup.
Discard changes and exit setup.
Display options of a particular setup item or enter submenu.
Main Setup Screen
When you first enter the BIOS setup, you will enter the Main setup screen. You can always return to the Main setup screen by selecting the
Main tab. The Main screen reports BIOS, processor, memory and board information and is for configuring the system date and time.
Feature
Options
Description
BIOS ID
OEM BIOS Version
Build Date
Product Revision
Serial Number
BC Firmware Rev.
Boot Counter
MAC Address
Running Time
MRC Version
System Memory
►Platform Information
System Time
System Date
no option
no option
no option
no option
no option
no option
no option
no option
no option
no option
no option
submenu
Hour:Minute:Second
Day of week, month/day/year
Displays the BIOS ID.
Displays the OEM BIOS ID.
Displays the date when the BIOS was built.
Displays the hardware revision of the board.
Displays the serial number of the board.
Displays the revision of the congatec board controller.
Displays the number of boot-ups. (max. 16777215).
Displays the MAC address of the board.
Displays the time the board is running [in hours max. 65535].
Displays the MRC version number.
Displays the total amount of system memory.
Opens the platform information submenu.
Specifies the current system time. Note: The time is in 24-hour format.
Specifies the current system date. Note: The date is in month-day-year format.
Copyright © 2012 congatec AG CTOPm10 68/85
10.4
10.5
Platform Information submenu
Feature
Options
Description
Processor Version
IGD VBIOS
PUNIT Build Date
PUNIT Build Time
no option
no option
no option
no option
Displays the silicon revision of the processor.
Displays the Video BIOS version ID.
Displays the PUNIT build date.
Displays the PUNIT build time
Advanced Setup
Select the Advanced tab from the setup menu to enter the Advanced BIOS Setup screen. The menu is used for setting advanced features:
Main
Advanced
Boot
Security
Power
Exit
Graphic Configuration
Watchdog Configuration
PCI Subsystem Settings
ACPI Configuration
CPU Configuration
Chipset Configuration
AHCI SATA Configuration
SDIO Configuration
USB Configuration
Super IO Configuration
Serial Port Console Redirection
Copyright © 2012 congatec AG CTOPm10 69/85
10.5.1
Graphics Configuration Submenu
Feature
Primary Display
Options
Auto
IGD
PEG
Internal VGA Mode Select Enabled, 4MB
Enabled, 8MB
Enabled, 16MB
Enabled, 32MB
Enabled, 64MB
MSAC Mode Select
Enabled 128MB
Enabled 256MB
Enabled 512MB
IGD – Boot Type
No option
Boot Display Device
Integrated SDVO
Integrated LVDS
Flat Panel Scaling
Auto
Forced
Disabled
Flat Panel Type
Auto
VGA 640x480 1x18 (002h)
VGA 640x480 1x18 (013h)
WVGA 640x480 1x24 (01Bh)
SVGA 800x600 1x18 (01Ah)
XGA 1024x768 1x18 (006h)
XGA 1024x768 1x18 (008h)
Customized EDID 1
Customized EDID 2
Customized EDID 3
DPST Control
VBIOS-Default
DPST Disabled
DPST Enabled L1
DPST Enabled L2
DPST Enabled L3
DPST Enabled L4
DPST Enabled L5
Backlight Inverter Type
None
PWM
I2C
PWM Inverter Frequency 200 - 40000
Backlight Setting
0%, 10%, 25%, 40%, 50%, 60%, 75%,
90%, 100%
Description
This option allows you to select the primary video device among Internal Graphic Driver, External Card
or Auto configuration.
This option allows you to disable the internal VGA controller or enable it with 1MB, 4MB, 8MB, 16MB,
32MB or 64MB initial frame buffer size.
Determines the size of the graphics memory aperture.
VBIOS Default configuration
Select the display device used for booting up.
Defines the Flat Panel Scaling mode.
Select a predefined LFP type or choose Auto to let the BIOS automatically detect and configure the
attached LVDS panel.
Auto detection is performed by reading an EDID data set via the video I²C bus.
The number in brackets specifies the congatec internal number of the respective panel data set.
Note: Customized EDID™ utilizes an OEM defined EDID™ data set stored in the BIOS flash device.
Determines whether the VBIOS default controls the Display Power Save Technology or the setup
configures the desired level.
Select the type of backlight inverter used. PWM = Use IGD PWM signal.
Select PWM inverter frequency. Default 20300.
Actual backlight value in percent of the maximum setting.
Copyright © 2012 congatec AG CTOPm10 70/85
Feature
Options
Description
Inhibit Backlight
No
Permanent
Until End Of POST
No
Yes
Decide whether the backlight on signal should be activated when the panel is activated or whether it
should remain inhibited until the end of BIOS POST or permanently. Hidden if Backlight inverter Type is
None.
Allow to invert backlight control values if required for the actual backlight hardware controller. Hidden if
Backlight inverter Type is None.
Invert Backlight Setting
10.5.2
Watchdog Configuration Submenu
Feature
Options
Description
POST Watchdog
Disabled
30sec
1min
2min
5min
10min
30min
No
Yes
Disabled
One time trigger
Single Event
Repeated Event
Select the timeout value for the POST watchdog.
Stop Watchdog For
User Interaction
Runtime Watchdog
Delay
Event 1
Event 2
Event 3
The watchdog is only active during the power-on-self-test of the system and provides a facility to prevent errors during boot up by
performing a reset..
Select whether the POST watchdog should be stopped during the popup boot selection menu or while waiting for setup password
insertion.
Selects the operating mode of the runtime watchdog.
This watchdog will be initialized just before the operating system starts booting.
If set to ‘One time trigger’ the watchdog will be disabled after the first trigger.
If set to ‘Single event’, every stage will be executed only once, then the watchdog will be disabled.
If set to ‘Repeated event’ the last stage will be executed repeatedly until a reset occurs.
see Post Watchdog Select the delay time before the runtime watchdog becomes active. This ensures that an operating system has enough time to load.
NMI
Selects the type of event that will be generated when timeout 1 is reached. For more information about ACPI Event see note below.
ACPI Event
Reset
Power Button
Selects the type of event that will be generated when timeout 2 is reached.
Disabled
NMI
ACPI Event
Reset
Power Button
Disabled
Selects the type of event that will be generated when timeout 3 is reached.
NMI
ACPI Event
Reset
Power Button
Copyright © 2012 congatec AG CTOPm10 71/85
Feature
Options
Description
Timeout 1
0.5sec
1sec
2sec
5sec
10sec
30sec
1min
2min
see above
see above
Shutdown
Restart
Selects the timeout value for the first stage watchdog event.
Timeout 2
Timeout 3
Watchdog ACPI
Event
10.5.3
Selects the timeout value for the second stage watchdog event.
Selects the timeout value for the third stage watchdog event.
Select the operating system event that is initiated by the watchdog ACPI event. These options perform a critical but orderly operating
system shutdown or restart.
PCI Subsystem Settings Submenu
Feature
Options
Description
PCI BUS Driver Version
PCI ROM Priority
no option
[EFI Compatible ROM]
Legacy ROM
Disabled
Enabled
Disabled
Enabled
submenu
32, 64, 96, ... 248
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
None
IRQ3
IRQ4
IRQ6
IRQ7
IRQ10
IRQ11
IRQ14
IRQ15
Displays the PCI Bus driver version ID number
In case of multiple Option ROMS, specifies what Option ROM is to be launched.
Launch PXE OpROM
Launch Storage OpROM
PCI Express Ports Configuration
PCI Latency Timer
VGA Palette Snoop
PERR# Generation
SERR# Generation
Relaxed Ordering
Reserved Interrupt 1
Allows the launching of PXE Option ROMS
Allows the launching of Storage Option ROMS
Opens the platform information submenu.
Specifies the PCI latency using bus clock units.
Enables or Disables VGA palette registers snooping.
Enables or Disables PCI device to generate PERR#.
Enables or Disables PCI device to generate SERR#.
Enables or Disables PCI Express device Relaxed Ordering.
Reserves additional IRQ for custom purposes.
Copyright © 2012 congatec AG CTOPm10 72/85
Feature
Options
Description
Reserved Interrupt 2
None
IRQ3
IRQ4
IRQ6
IRQ7
IRQ10
IRQ11
IRQ14
IRQ15
submenu
Disabled
Enabled
Disabled
Enabled
Auto, 128, 256, 512,
1024, 2048, 4096
Auto, 128, 256, 512,
1024, 2048, 4096
Disabled
Enabled
Disabled
Enabled
Reserves additional IRQ for custom purposes.
PIRQ Routing
Extended Tag
No Snoop
Maximum Payload
Maximum Read Request
Automatic ASPM
Extended Synch
10.5.4
10.5.5
Allows device to use 8-bit tag field as a requester.
Enables or Disables PCI Express Device no snoop option.
Sets the maximum payload value on bytes or allows the system BIOS to select the value.
Sets the maximum read request value on bytes or allows the system BIOS to select the value.
Enables or disables ASPM on reported capabilities and known issues.
Enables or disables the generation of extended synchronization patterns.
PCI Express Ports 1-4 Configuration Submenu
Feature
Options
Description
PCI Express Root Port 0..3
Disabled
Enabled
Controls the PCI Express Root port.
PIRQ Routing Submenu
Feature
Options
Description
PIRQA...H
Auto
IRQ3
IRQ4
IRQ6
IRQ7
IRQ10
IRQ11
IRQ14
IRQ15
Sets Interrupt for selected PIRQ. Refer to the board’s Resource List for a detailed description of devices
connected to the respective PIRQ.
This setup node is only effective while operating in PIC (non IOAPIC) interrupt mode.
Copyright © 2012 congatec AG CTOPm10 73/85
10.5.6
10.5.7
PCI to PCI Bridge Submenu
Feature
Options
Description
Extra Bus Reserved
0-7
Extra BUS reserved for bridges behind the PCI root Bridge. Range 0 to 7
ACPI Configuration Submenu
Feature
Options
Description
Enable ACPI Auto
Configuration
Enable Hibernation
Disabled
Enabled
Disabled
Enabled
Suspend Disabled
S3 (Suspend to RAM)
70, 80, 90, 95, 100,
105, 110, 115, 120,
125°C, Disabled
Disabled, 30, 40, 50,
60, 70, 80, 90, 95,
100°C
Disabled, 30, 40, 50,
60, 70, 80, 90, 95,
100°C
Enables or disables BIOS ACPI Auto Configuration
ACPI Sleep State
Critical Trip Point
Active Trip Point
Passive Trip Point
Enables or disables System ability to hibernate (OS/S4 Sleep State).
Select the state used for ACPI system sleep/suspend
Specifies the temperature threshold at which the ACPI aware OS performs a critical shutdown.
Specifies the temperature threshold at which the ACPI aware OS turns the fan on/off.
Specifies the temperature threshold at which the ACPI aware OS starts/stops CPU clock throttling.
Note
In ACPI mode it is not possible for a “Watchdog ACPI Event” handler to directly restart or shutdown the OS. For this reason the congatec BIOS
will do one of the following:
For Shutdown: An over temperature notification is executed. This causes the OS to shut down in an orderly fashion.
For Restart: An ACPI fatal error is reported to the OS.
It depends on your particular OS as to how this reported fatal error will be handled when the Restart function is selected. If you are using
Windows XP there is a setting that can be enabled to ensure that the OS will perform a restart when a fatal error is detected. After a very brief
blue-screen the system will restart.
You can enable this setting buy going to the “System Properties” dialog box and choosing the “Advanced” tab. Once there choose the “Settings”
button for the “Startup and Recovery” section. This will open the “Startup and Recovery” dialog box. In this dialog box under “System failure”
there are three check boxes that define what Windows will do when a fatal error has been detected. To ensure that the system restarts after
a ‘Watchdog ACPI Event” is set to ‘Restart’, you must make sure that the check box for the selection “Automatically restart” is checked. If this
Copyright © 2012 congatec AG CTOPm10 74/85
option is not selected then Windows will remain at a blue-screen after a ‘Watchdog ACPI Event” that has been configured for ‘Restart’ has been
generated. Below is a Windows screen-shot showing the proper configuration.
Win XP Watchdog ACPI Event restart configuration
l
Copyright © 2012 congatec AG CTOPm10 75/85
10.5.8
CPU Configuration Submenu
Feature
Options
Description
CPU Information
Intel(R) SpeedStep(tm)
no option
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Describes the CPU/Processor main parameters.
Disabled: CPU speed is set to maximum and cannot be altered by the operating system.
Enabled: CPU speed is controlled by the operating system.
Enables or disables Intel Hyperthreading Technology for being used by the OS.
Hyperthreading
Execute Disable Bit
Limit CPUID Maximum
Disabled
Enabled
Intel Virtualization Technology
Disabled
Enabled
Disabled
Enabled
Enabled
Disabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
C-States
C-State POPUP
Enhanced C-1
Enhanced C-2
Enhanced C-3
Enhanced C-4
Enable or disable the Execute Disable Bit (XD) of the processor.
With the XD bit set to enabled, certain classes of malicious buffer overflow attacks can be prevented when combined with a
supporting OS.
When enabled, the processor will limit the maximum CPUID input value to 03h when queried, even if the processor
supports a higher CPUID input value. When disabled, the processor will return the actual maximum CPUID input value
of the processor when queried. Limiting the CPUID input value may be required for older operating systems that cannot
handle the extra CPUID information returned when using the full CPUID input value.
When enabled, a VMM can utilize the additional hardware capabilities provided by the Vanderpool Technology.
Enable support for supported standard CPU idle states.
Enables or disables C-State POPUP.
Enables or disables the Enhanced C1 State.
Enables or disables the Enhanced C2 State.
Enables or disables the Enhanced C3 State.
Enables or disables the Enhanced C4 State.
Copyright © 2012 congatec AG CTOPm10 76/85
10.5.9
Chipset Configuration Submenu
Feature
Options
Description
Audio Controller
Auto
Enabled
Disabled
Azalia PME Enable
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
submenu
Enabled
Disabled during S5
Disabled during S3/S5
Disabled Always
Disabled
Enabled
Controls activation of the HDA controller device.
Disabled = HDA controller will be unconditionally disabled
Enabled = HDA controller will be unconditionally enabled
Auto = HDA Controller will be enabled if HDA codec present, disabled otherwise.
Enables or disables the Azalia PME (Power Management Events)
Azalia Vci Enable
SMBUS Controller
Network Settings
EG20T Ethernet PHY
High Precision Timer
Enables or disables the Azalia Vci
Enables disables the SMBUS Controller
EG20T MAC Device configuration.
Configures the Chip Power State of Ethernet PHY. Disable S5 and Disable S3/S5 set the PHY on Power off
mode saving energy during the system ACPI Power States S3 or S5. Enable/Disabled always configures Power
On/Power off for all the ACPI states.
Enable or disable the high precision event timer (HPET). This timer can be used for precise multimedia or real
time application timing. Special software support is required.
Note
The BIOS does not initialize the HDA codec. The codecs remains in default mode and must be initialized by its respective device driver.
10.5.9.1
Network Settings Submenu
Feature
Options
Description
Network Stack
Disabled
Enabled
Disabled
Enabled
Wake Up Frame
Magic packet
10 Mbps
100Mbps
1000Mbps
Enable/Disable the Network Stack for PXE and UEFI.
Wake on LAN
WOL Mode
WOL Speed
Enables/Disables WOL.
Selects WOL Mode.
Hidden if Wake on LAN is disabled.
Selects WOL Speed.
Hidden if Wake on LAN is disabled.
Copyright © 2012 congatec AG CTOPm10 77/85
10.5.10 AHCI SATA Configuration
Feature
Options
Description
PORT 0
Disabled
Enabled
Disabled
Enabled
This node enables or disables the Set Transfer mode programming for SATA port 0
PORT 1
This node enables or disables the Set Transfer mode programming for SATA port 1
10.5.11 SDIO Configuration Submenu
Feature
Options
Description
SDIO Access Mode
Auto
DMA
PIO
Configures the access to the SD devices. With Auto, the controller determines the SD access method.
10.5.12 USB Configuration Submenu
Feature
Options
Description
USB Device List
Legacy USB Support
no option
Enabled
Disabled
Auto
Disabled
Enabled
10 sec
20 sec
30 sec
40 sec
1 sec
5 sec
10 sec
20 sec
Auto
Floppy
Forced FDD
Hard Disk
CD-ROM
List of the USB devices connected to the system updated dynamically.
Enables legacy USB support. Auto option disables legacy support if no USB devices are connected. Disable option will keep
USB devices available only for EFI applications and setup.
EHCI Hand-off
Device Reset Timeout
Controller Timeout
USB Mass Storage Device
Name
(Auto detected USB mass
storage devices are listed here
dynamically)
This is a workaround for OSes without EHCI hand-off support. The EHCI ownership change should be claimed by the EHCI OS
driver.
USB legacy mass storage device Start Unit command timeout.
Timeout value for legacy USB control, bulk and interrupt transfers.
Every USB mass storage device that is enumerated by the BIOS will have an emulation type setup option. This option specifies
the type of emulation the BIOS has to provide for the device.
Note: The device’s formatted type and the emulation type provided by the BIOS must match for the device to boot properly.
Select AUTO to let the BIOS auto detect the current formatted media.
If Floppy is selected then the device will be emulated as a floppy drive. Forced FDD allows a hard disk image to be connected
as a floppy image. Works only for drives formatted with FAT12, FAT16 or FAT32.
Hard Disk allows the device to be emulated as hard disk. CDROM assumes the CD-ROM is formatted as bootable media,
specified by the ‘El Torito’ Format Specification.
Copyright © 2012 congatec AG CTOPm10 78/85
10.5.13 Super I/O Winbond Configuration Submenu
Feature
Options
Description
Super IO Chip
Serial Port 0 Configuration
Serial Port 1 Configuration
Wake on Ring
no option
submenu
submenu
Disabled
Enabled
Displays Winbond SIO ID.
Opens the Serial Port 0 Configuration submenu.
Opens the Serial Port 1 Configuration submenu.
Enables or disables SIO wake.
Note
This setup menu is only available if an external Winbond W83627 Super I/O has been implemented on the carrier board.
10.5.13.1 Serial Port 0/1 Configuration Submenu
Feature
Options
Description
Serial Port 0
Disabled
Enabled
IO=3F8h; IRQ=4;
[Auto]
[IO=3F8; IRQ=4]
[IO=3F8 IRQ=3,4,5,6,7,
8, 9,10,11,12]
[IO=2F8 IRQ=3,4,5,6,7,
8, 9,10,11,12]
[IO=3E8 IRQ=3,4,5,6,7,
8, 9,10,11,12]
[IO=2E8 IRQ=3,4,5,6,7,
8, 9,10,11,12]
Normal
High Speed
Enable or disable serial port 0.
Device Settings
Change Settings
Device Mode
Fixed configuration of serial port 0 if enabled.
Selects the IO port address and Interrupt for the SIO Port
Changes the serial port mode
Copyright © 2012 congatec AG CTOPm10 79/85
10.5.14 Serial Port Console Redirection
Feature
Options
COM0/COM1
Console Redirection
no option
Disabled
Enabled
submenu
Console Redirection
Settings
Serial Port for Out-ofBand Management/
Windows EMS
Console Redirection
Out-of-Band Mgmt Port
Terminal Type
no option
Disabled
Enabled
COM0
COM1
COM4
VT100
VT100+
VT-UTF8
ANSI
Description
Allows the Console Redirection Settings note selection
Opens the Serial Port 1/Port2 Console Redirection submenu.
Only selectable when console redirection is enabled
Serial Port for Out-of-Band Management/ Windows Emergency
Management Services (EMS)
Allows the Serial redirection for Windows EMS
Defines the Serial Pot used for the Windows EMS
This note defines the Terminal Type used for the connection.
10.5.14.1 Console Redirection Settings
Feature
Options
Console Redirection
Setting
Terminal Type
no option
Bits per second
Data Bits
Parity
Stop Bits
VT100
VT100+
VT-UTF8
ANSI
9600
19200
57600
115200
8
7
None
Even
Odd
Mark
Space
1
2
Description
Emulation: ANSI: Extended ASCII char set. VT100: ASCII char set. VT100+: Extends VT100 to
support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode chars onto 1 or
more bytes.
Selects serial port transmission speed. The speed must be matched on the other side. Long or
noisy lines may require lower speeds.
Data Bits
A parity bit can be sent with the data bits to detect some transmission errors.
Even: parity bit is 0 if the num of 1’s in the data bits is even.
Odd: parity bit is 0 if num of 1’s in the data bits is odd.
Mark: parity bit is always 1.
Space: Parity bit is always 0.
Mark and Space Parity do not allow for error detection. They can be used as an additional data bit.
Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning). The standard
setting is 1 stop bit. Communication with slow devices may require more than 1 stop bit.
Copyright © 2012 congatec AG CTOPm10 80/85
Feature
Options
Description
Flow Control
None
Hardware RTS/CTS
Recorder Mode
Disabled
Enabled
Disabled
Enabled
80x24
80x25
Flow control can prevent data loss from buffer overflow. When sending data, if the receiving
buffers are full, a ‘stop’ signal can be sent to stop the data flow. Once the buffers are empty, a
‘start’ signal can be sent to re-start the flow. Hardware flow control uses two wires to send start/
stop signals. Software flow control uses start/stop ASCII chars, which slows down the data flow
and can be problematic if binary data is being sent.
On this mode enabled only text will be send. This is to capture Terminal data.
Resolution 100x31
Legacy OS Redirection
Resolution
10.6
Enables or disables extended terminal resolution.
Legacy OS Redirection Resolution.
Boot Setup
Select the Boot tab from the setup menu to enter the Boot setup screen.
10.6.1
Boot Settings Configuration Submenu
Feature
Options
Description
Quiet Boot
Disabled
Enabled
Disabled displays normal POST diagnostic messages.
Enabled displays OEM logo instead of POST messages.
Note: The default OEM logo is a dark screen.
Enables or disables UEFI fast boot with initialization of a minimal set of devices required to launch the active boot option.
Fast Boot
Disabled
Enabled
Setup Prompt Timeout 1
0 - 65535
Bootup NumLock State On
Off
Power Loss Control
Remain Off
Turn On
Last State
Enable Popup Boot
Menu
Boot Priority Selection
No
Yes
Device Based
Type Based
Number of seconds to wait for setup activation key.
0 means no wait for fastest boot, 65535 means infinite wait.
Select the keyboard numlock state.
Specifies the mode of operation if an AC power loss occurs.
Remain Off keeps the power off until the power button is pressed.
Turn On restores power to the computer.
Last State restores the previous power state before power loss occurred.
Note: Only works with an ATX type power supply.
Select whether the popup boot menu can be started.
Select between device and type based boot priority lists. The “Device Based” boot priority list allows you to select from a list
of currently detected devices only. The “Type Based” boot priority list allows you to select device types, even if a respective
device is not yet present. Moreover, the “Device Based” boot priority list might change dynamically in cases when devices are
physically removed or added to the system. The “Type Based” boot menu is static and can only be changed by the user.
Copyright © 2012 congatec AG CTOPm10 81/85
Feature
Options
Description
1st, 2nd, 3rd, ...
Boot Device
(Up to 11 boot devices
can be prioritized if
device based priority
list control is selected.
If “Type Based” priority
list control is enabled
only 8 boot devices
can be prioritized.)
Disabled
SATA 0 Drive
SATA 1 Drive
Primary Master
Secondary Master
Addon Via Controller
USB Floppy
USB Harddisk
USB CDROM
Onboard LAN
External LAN
Other BEV Device
G3/Mech Off
S5/Soft Off
no option
This view is only available when in the default “Type Based” mode.
When in “Device Based” mode you will only see the devices that are currently connected to the system.
System Off Mode
CSM16 Module
Version
GateA20 Active
Option ROM
Messages
Interrupt 19 Capture
10.7
Upon Request
Always
Force BIOS
Keep Current
Disabled
Enabled
Define system state after shutdown when a battery system is present.
Displays the CSM16 Version ID
Gate A20 control.
Upon Request = Gate A20 can be disabled using BIOS services.
Always = Do not allow disabling Gate A20.
Set display mode for option ROMs.
Defines whether option ROMs may trap the INT19h legacy boot vector.
Security Setup
Select the Security tab from the setup menu to enter the Security setup screen.
10.7.1
Security Settings
Feature
Options
Setup Administrator Password Enter password
Description
Specifies the setup administrator password.
Copyright © 2012 congatec AG CTOPm10 82/85
10.8
Save & Exit
Select the Save & Exit tab from the setup menu to enter the Save & Exit setup screen. You can display the Save & Exit screen option by
highlighting it using the ← Arrow → Keys.
10.8.1
Save & Exit Menu
Feature
Description
Save Changes and Exit
Discard Changes and Exit
Save Changes and Reset
Discard Changes and
Reset
Save Changes
Discard Changes
Restore Defaults
Exit setup menu after saving the changes. The system is only reset if settings have been changed.
Exit setup menu without saving any changes.
Save changes and reset the system.
Reset the system without saving any changes.
Save changes made so far to any of the setup options. Stay in setup menu.
Discard changes made so far to any of the setup options. Stay in setup menu.
Restore default values for all the setup options.
Copyright © 2012 congatec AG CTOPm10 83/85
11
Additional BIOS Features
The conga-CA6 uses a congatec/AMI AptioEFI that is stored in an onboard SPI Flash chip and can be updated using the congatec System
Utility, which is available in a DOS based command line, Win32 command line, Win32 GUI, and Linux version.
The BIOS displays a message during POST and on the main setup screen identifying the BIOS project name and a revision code. The initial
production BIOS is identified as CTOPR1xx, where CTOP is the congatec internal BIOS project name for conga-CA6, R is the identifier for a
BIOS ROM file, 1 is the so called feature number and xx is the major and minor revision number.
11.1
Updating the BIOS
BIOS updates are often used by OEMs to correct platform issues discovered after the board has been shipped or when new features are added
to the BIOS.
For more information about “Updating the BIOS” refer to the user’s guide for the congatec System Utility, which is called CGUTLm1x.pdf and
can be found on the congatec AG website at www.congatec.com.
11.2
BIOS Security Features
The BIOS provides a setup administrator password that limits access to the BIOS setup menu.
Copyright © 2012 congatec AG CTOPm10 84/85
12
Industry Specifications
The list below provides links to industry specifications that apply to congatec AG modules.
Specification
Low Pin Count Interface Specification, Revision 1.0 (LPC)
Universal Serial Bus (USB) Specification, Revision 2.0
PCI Specification, Revision 2.3
Serial ATA Specification, Revision 1.0a
PICMG® COM Express Module™ Base Specification
PCI Express Base Specification, Revision 2.0
Link
http://developer.intel.com/design/chipsets/industry/lpc.htm
http://www.usb.org/home
http://www.pcisig.com/specifications
http://www.serialata.org
http://www.picmg.org/
http://www.pcisig.com/specifications
Copyright © 2012 congatec AG CTOPm10 85/85
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