EFM32LG900 Rev. E Errata

EFM32LG900 Rev. E Errata
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EFM32LG900 Errata, Chip Rev. E
F256
This document describes errata for the latest revision of EFM32LG900 devices.
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1 Errata
This document contains information on the errata of the latest revision of this device. For errata on older revisions, please refer to the errata history for the
device. The device data sheet explains how to identify chip revisions, either from package markings or electronically.
In addition to the errata noted below, the errata for the ARM Cortex-M3 r2p1 (www.arm.com) also applies to this device.
1.1 Chip revision E
Table 1.1. Erratas
ID
Title/Problem
Effect
Fix/Workaround
BU_E105
LFXO missing cycles during IOVDD
ramping
When IOVDD is ramped, the dc-level of the XTAL signal
changes, resulting in missed LFXO cycles and possible
glitches on the LFXO clock.
Set PRESC in BURTC_CTRL to greater then 0 when ramping IOVDD in combination with Backup mode to avoid glitches on the LFXO clock.
LFXO missing cycles during IOVDD
ramping when used in combination
with Backup mode.
CMU_E114
Device not waking up from EM2
when using prescaled non-HFRCO
oscillator as HFCLK
If the device is running from any prescaled oscillator other
than HFRCO as HFCLK and HFRCO is disabled, the device
will not wake up from EM2.
Before entering EM2, clear CMU_CTRL_HFCLKDIV.
Alternatively, enable HFRCO by setting
CMU_OSCENCMD_HFRCOEN and wait until
CMU_STATUS_HFRCORDY is set.
DAC_E109
DAC output drift over lifetime
When the device is powered and the DAC is disabled, stress
on an internal circuit node can cause the output voltage of
the DAC to drift over time, and in some cases may violate the
VDACOFFSET specification. If the DAC is always enabled while
the device is powered, this condition cannot occur.
Both in the startup initialization code and prior to disabling
the DAC in application code, set the OPAnSHORT bit in
DACn_OPACTRL to a '1' for the corresponding DAC(s) used
by the application. This will prevent the output voltage drift
over time effect.
During EM2 entry, the high frequency clocks that are disabled during EM2 will run for some clock cycles after WFI is
issued to allow safe shutdown of the peripherals. If an enabled interrupt is requested from one of these non-EM2 peripherals during this shutdown period, the attempt to enter
EM2 will fail, and the device will enter EM1 instead. As a result the pending interrupt will immediately wake the device to
EM0.
Before entering EM2, disable all high frequency peripheral interrupts in the core.
The PCNT Pulse Width Filter does not work as intended.
Do not use the pulse width filter, i.e. ensure FILT = 0 in
PCNTn_CTRL.
The voltage output of the DAC might
drift over time.
EMU_E107
Interrupts during EM2 entry
An interrupt from a peripheral running from the high frequency clock
that is received during EM2 entry will
cause the EMU to ignore the SLEEPDEEP-flag.
PCNT_E102
PCNT Pulse Width Filtering does
not work
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ID
Title/Problem
Effect
Fix/Workaround
TIMER_E103
Capture/compare output is unreliable with RSSCOIST enabled
When RSSCOIST is set and PRESC > 0 in TIMERn_CTRL,
the capture/compare output value is not reliable.
Do not use a prescaled clock, i.e. ensure PRESC = 0 in
TIMERn_CTRL when RSSCOIST is enabled.
The TIMER capture/compare output is
unreliable when RSSCOIST is enabled
and the clock is prescaled.
USB_E103
HNP Sequence fails if A-Device con- The B-Device core only waits for up to 3.4ms before signects after 3.4ms
nalling HNP fail and reverting back to Peripheral mode.
Therefore, the HNP sequence fails if the A-Device connects
after 3.4ms.
No known workaround.
USB_E104
USB A-Device delays the HNP
switch back process
The A-Device core delays the HNP switch back process. As
per the USB-OTG 2.0 specification, the B-Device on the other side of the USB pipe either should wait for disconnect from
the A-Device or should switch to Peripheral mode and wait
for the A-Device to issue a USB reset. Hence, there is no significant impact on actual operation.
No known workaround.
If the B-Device as Host on the other side of the USB pipe
drives K-J pairs for more than 200 ms during USB reset, the
A-Device core exits peripheral state, causing the HNP process to fail. There is no significant impact since normally the
host drives USB reset for a shorter time than 200 ms.
No known workaround.
When USB_PCGCCTL.STOPPCLK is set and the device is
acting as a B-peripheral, a Host-initated Suspend, followed
by a Host Disconnect and Host Connect will not result in a
SessReq interrupt.
If this is an expected use-case, USB_PCGCCTL.STOPPCLK
should not be set. USB_PCGCCTL.GATEHCLK can still be
used to save power.
In some cases, an unexpected USB_HCx_INT.CHHLTD
interrupt might be received from another endpoint
that does not have the USB_HCx_CHAR.CHDIS,
USB_HCx_INT.XACTERR, USB_HCx_INT.BBLERR,
USB_HCx_INT.DATATGLERR or
USB_HCx_INT.XFERCOMPL interrupts enabled.
If such an interrupt is received, the application must reenable the channel for which it received the unexpected
USB_HCx_INT.CHHLTD interrupt.
The list of affected devices can be found in the Knowledge
Base (KB) article listed under Fix/Workaround.
Additional information including a software workaround is
available from the following KB article URL:
The D+ line disconnects after 200 ms,
delaying the HNP switch back process.
USB_E105
B-Device as Host driving K-J pairs
during reset
The A-Device misinterprets the K-J
pairs as Suspend after switching to
High Speed mode.
USB_E109
Missing
USB_GINTSTS.SESSREQINT
Interrupt with
USB_PCGCCTL.STOPPCLK = 1
A Host-initiated Suspend, followed by
a Host Disconnect and Host Connect
will not result in a SessReq interrupt.
USB_E110
Unexpected USB_HCx_INT.CHHLTD
interrupt
In some cases the
USB_HCx_INT.CHHLTD interrupt
might be incorrectly set.
RMU_E101
POR calibration initialization issue
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ID
Title/Problem
Effect
Fix/Workaround
Upon initial power-on, some devices
may not be able to access flash memory above the 4 kB boundary, or some
calibration registers on some devices
may not be set to their factory calibration values.
Some devices are sensitive to the power supply ramp during initial power-on. Specific ramp profiles on these devices
can cause an intermittent issue resulting in one of two failure
modes (A) or (B):
http://community.silabs.com/t5/32-bit-MCU-Knowledge-Base/
POR-calibration-initialization-issue/ta-p/154716
A. Flash memory above the 4 kB boundary is inaccessible.
Reads of the flash will return zeros. Write attempts will return
an “invalid address” error code in the MSC_STATUS register.
Code execution will behave as though the memory above 4
kB was filled with zeros until the device resets itself.
B. Some parts of the calibration initialization process do
not complete successfully. On USB devices, the USB voltage regulator does not get calibrated. Specific peripheral registers that may not be calibrated are as follows (not
all registers apply to all devices): ADC0_CAL, IDAC_CAL,
DAC0_CAL, DAC0_BIASPROG, DAC0_OPACTRL, and
DAC0_OPAOFFSET.
A SYSRESETREQ reset will clear either failure mode, and
the device will behave normally until the next power-on
event.
1.2 Older Revisions
Erratas for older revisions can be found at the Silicon Laboratories homepage:
www.silabs.com/32bit-errata
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2 Revision History
2.1 Revision 1.10
October 5th, 2015
Added TIMER_E103.
Added PCNT_E102.
Added RMU_E101.
Added DAC_E109.
2.2 Revision 1.00
October 15th, 2014
Initial release.
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A Disclaimer and Trademarks
A.1 Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system
and software implementers using or intending to use the Silicon Laboratories products. Characterization data, available modules and peripherals, memory
sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples
described herein are for illustrative purposes only. Silicon Laboratories reserves the right to make changes without further notice and limitation to product
information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon
Laboratories shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright
licenses granted hereunder to design or fabricate any integrated circuits. The products must not be used within any Life Support System without the specific
written consent of Silicon Laboratories. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails,
can be reasonably expected to result in significant personal injury or death. Silicon Laboratories products are generally not intended for military applications.
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A.2 Trademark Information
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B Contact Information
Silicon Laboratories Inc.
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Austin, TX 78701
Please visit the Silicon Labs Technical Support web page:
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and register to submit a technical support request.
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Table of Contents
1. Errata .......................................................................................................................................................................................................................................
1.1. Chip revision E .................................................................................................................................................................................................................
1.2. Older Revisions ................................................................................................................................................................................................................
2. Revision History ..........................................................................................................................................................................................................................
2.1. Revision 1.10 ...................................................................................................................................................................................................................
2.2. Revision 1.00 ...................................................................................................................................................................................................................
A. Disclaimer and Trademarks ..........................................................................................................................................................................................................
A.1. Disclaimer .......................................................................................................................................................................................................................
A.2. Trademark Information .......................................................................................................................................................................................................
B. Contact Information .....................................................................................................................................................................................................................
B.1. .....................................................................................................................................................................................................................................
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List of Tables
1.1. Erratas .................................................................................................................................................................................................................................... 2
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