MOSFET Small Signal Modelling ELEC 3908, Physical Electronics, Lecture 26

MOSFET Small Signal Modelling ELEC 3908, Physical Electronics, Lecture 26
ELEC 3908, Physical Electronics, Lecture 26
MOSFET Small Signal
Modelling
Lecture Outline
• MOSFET small signal behavior will be considered in the
same way as for the diode and BJT
• Capacitances will be considered in more detail for the
MOSFET structure, and depletion, extrinsic and intrinsic
components will be identified
• More attention will be paid to incorporating features of the
process into quantities which can be scaled to absolute
values for a particular device based on its geometry – for
the diode and BJT, only the active 1D area was used for
scaling
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-2
Low Frequency Parameters
•
The transconductance is defined
as the rate of change of ID with
respect to VGS with VDS fixed in
saturation
gm ≡
•
dI D
dVGS
VDS
W
= μ n C$ ox (VGS − VT )(1 + λVDS )
L
The output conductance is
defined as the rate of change of
ID with respect to VDS with VGS
fixed in saturation
dI D
go ≡
dV DS
W (VGS − VT )
= μ n C$ ox
λ
L
2
2
VGS
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-3
Low Frequency Small Signal Equivalent Circuit
•
•
Using the definitions of gm and
go, the small signal equivalent
circuit can be constructed as
shown
Note there is no equivalent of
gπ in the MOSFET small signal
equivalent circuit, since
(ideally) no gate current flows
due to the electrical isolation of
the gate oxide
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-4
MOSFET Capacitance
• There are three origins of capacitance in the MOSFET
structure
– Depletion capacitance associated with the source-substrate and
drain-substrate depletion regions, modelled as sidewall and bottom
components
– Extrinsic capacitance due to physical overlaps in the structure
– Intrinsic capacitance due to the fundamental charge-voltage
relationships in the device
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-5
Physical Origin of Sidewall Depletion Capacitance
•
•
•
•
The depletion capacitance associated
with the external sides of the source
and drain depletion regions is termed
sidewall capacitance
The same voltage dependence model is
used as for the pn-junction
A per unit peripheral length term is
used instead of a per unit area term
because the junction depth is not a
parameter which can be varied
The total capacitance is the per unit
periphery term multiplied by the source
perimeter PS or the drain perimeter PD
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-6
Sidewall Depletion Capacitance Model
•
The sidewall components of the sourcebulk and drain-bulk depletion
capacitance are modelled as
CSB sidewall =
CDB sidewall =
CdepSw
′ PS
(1 + VSB VbiSB )
CdepSw
′ PD
(1 + V
DB
•
•
z SB
VbiDB )
z DB
The primed quantity C’ denotes a per
unit length term
Note that PS and PD are the outside
perimeters, not counting the part facing
the channel
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-7
Physical Origin of Bottom Depletion Capacitance
•
•
•
•
The depletion capacitance associated
with the bottom source and drain
depletion regions is termed bottom
capacitance
Again, the same voltage dependence
model is used as for the pn-junction
A per unit area term is used because the
source and drain areas are quantities
which can be varied in layout
The total capacitance is the per unit
area term multiplied by the source area
AS or the drain area AD
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-8
Bottom Depletion Capacitance Model
•
•
•
The bottom components of the source-bulk
and drain-bulk depletion capacitance are
modelled as
C$ depBot AS
CSB bottom =
z SB
(1 + VSB VbiSB )
C$ depBot AD
CDB bottom =
z DB
(1 + VDB VbiDB )
AS and AD are the junction areas as defined
by the active region mask
NOTE: really should have written VBS and
VBD to be consistent with pn-junction
expressions, however these are always
reverse biases in normal operation
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-9
Final Depletion Capacitance Model
• The final models for the absolute source-bulk and drainbulk depletion capacitances are the sum of the sidewall and
bottom components
CSB =
CdepSw
′ PS
(1 + VSB2V44
biSB )
144
3
z SB
+
sidewall
CDB =
CdepSw
′ PD
(1 + VDB2V44
biDB )
144
3
z DB
sidewall
C$ depBot AS
(1 + VSB2V44
biSB )
144
3
z SB
bottom
+
C$ depBot AD
(1 + VDB2V44
biDB )
144
3
z DB
bottom
• The model parameters are usually determined from
measurements
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-10
Example 26.1: Depletion Capacitance Calculation
• For the MOSFET structure shown below, what are CSB and
CDB? The substrate has NA=2x1016 /cm3. Use 1019 /cm3 as
the source/drain doping, and assume grading coefficients of
0.4 for both junctions.
= 3 × 10 −11 F cm
CdepSw
′
C$ depBot = 4 × 10 −8 F cm 2
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-11
Example 26.1: Solution
•
The source and drain perimeters, not
counting the channel side, are
PS = PD = 4 + 8 + 4 = 16 μm
•
The source and drain areas are
AS = AD = 4 ⋅ 8 = 32 μm 2
•
The source-bulk and drain bulk built in
potentials are given by
VbiSB = VbiDB
⎛ 1019 ⋅ 2 × 1016 ⎞
⎟ = 0.89 V
= 0.02586 ⋅ ln ⎜⎜
10 2 ⎟
. × 10 ) ⎠
⎝ (145
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-12
Example 26.1: Solution (con’t)
•
The source bulk junction potential is 1V of
reverse bias, so the capacitance is
CSB =
3 × 10 −11 ⋅ 16 × 10 −4
(1 − ( − 1) 0.89)
0.4
+
4 × 10 −8 ⋅ 32 × 10−8
(1 − ( − 1) 0.89)
0 .4
= 4.5 × 10 −14 F
•
The drain bulk junction potential is 4V of
reverse bias, so the capacitance is
CDB =
3 × 10 −11 ⋅ 16 × 10 −4
(1 − ( − 4) 0.89)
0.4
+
4 × 10 −8 ⋅ 32 × 10 −8
(1 − ( − 4) 0.89)
0 .4
= 31
. × 10 −14 F
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-13
Extrinsic MOSFET Capacitance
•
Extrinsic MOSFET capacitance arises from overlaps in
the fabricated structure
• These are usually due to processing limitations or rules
imposed by processing limitations, so in principle extrinsic
capacitance can be minimised by better processing
techniques
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-14
Gate/Source and Gate/Drain Overlap Capacitance
•
•
•
When the source and drain are
implanted, lateral diffusion of
dopants causes the source and
drain regions to extend under
the gate (leading to the effective
channel length)
This creates a region of overlap
between the gate and source at
one end, and the gate and drain
at the other end
The capacitance is defined by
the channel width W, the extent
of the overlap xovl and the oxide
thickness tox
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-15
G/S and G/D Overlap Capacitance Model
• The capacitances are modeled as parallel plate structures,
with separation tox and area xovlW
• For symmetrical lateral diffusion, the overlap capacitances
can be written as
CGS ,ovl = CGD ,ovl =
ε ox
xovlW
tox
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-16
G/S and G/D Overlap Capacitance Model (con’t)
• The only factor in the model equations which is variable
by a circuit designer is W, so the remaining terms are
lumped into a per unit width overlap capacitance
ε ox
′ ,ovl = C GD
′ ,ovl ≡
C GS
xovl ( F cm )
tox
• The total capacitance is then the per unit width factor ⋅ W
C GS , ovl = C GS
′ ,ovl ⋅ W
C GD ,ovl = C G′ D ,ovl ⋅ W
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-17
Gate-Substrate Overlap Capacitance
•
•
To ensure that the source and
drain are separated (recall the
self-aligned process), the gate is
usually required to overlap the
active region
This leads to a capacitance
between the gate extension over
the field oxide and the substrate
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-18
Gate-Substrate Overlap Capacitance Model
• Because of the ill-controlled spatially varying nature of the
dielectric thickness, the gate-bulk (substrate) capacitance is
very difficult to predict analytically
• Measurements are usually done to extract a per unit length
capacitance C’GB,ovl , which is then multiplied by the drawn
gate length
• The total capacitance is then
CGB ,ovl = CGB
′ ,ovl ⋅ L
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-19
Example 26.2: Extrinsic Capacitance Calculation
• Calculate the extrinsic capacitances for the structure
below. Measurements give C’GB,ovl = 1.1x10-12 F/cm. tox is
20nm, and the lateral diffusion is 0.1 μm.
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-20
Example 26.2: Solution
• The gate-source and gate-drain overlaps are the amount of
lateral diffusion, 0.1 μm. The per unit width capacitances
are therefore
CGS
′ ,ovl = CGD
′ ,ovl
3.9 ⋅ 8.854 × 10 −14
−4
−12
⋅
×
=
×
F cm
=
01
10
1
73
10
.
.
−7
20 × 10
• From the layout, the channel width is 8 μm, so the total
overlap capacitances are
CGS ,ovl = CGD ,ovl
= 1.73 × 10 −12 ⋅ 8 × 10 − 4
= 138
. × 10 −15 F
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-21
Example 26.2: Solution (con’t)
• The drawn gate length is 2 μm, so the given per unit length
gate-bulk overlap capacitance can be used to find the total
gate-bulk overlap capacitance as
CGB ,ovl = CGB
′ ,ovl ⋅ L
= 11
. × 10 −12 ⋅ 2 × 10 − 4 = 2.2 × 10 −16 F
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-22
Intrinsic MOSFET Capacitance
•
•
•
Intrinsic MOSFET capacitance arises
from the inherent charge voltage
relationship in the device itself
More sophisticated processing can
reduce the source drain depletion and
extrinsic capacitances, but the intrinsic
capacitances will always be present
Although there are in principle 9
independent intrinsic capacitance
components in the MOSFET, the most
important are the gate source and gate
drain capacitances, since they load a
previous stage
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-23
Intrinsic MOSFET Capacitance Model
•
The detailed analysis of intrinsic capacitance involves expressing the channel
charge in terms of the terminal potentials and performing the appropriate
derivatives
CGS
dQG
≡
dVGS
CGD ≡
•
dQG
dVGD
Although QG will balance both depletion and inversion charge, inversion
charge is assumed to dominate, so that the derivatives are those of the
inversion charge with respect to the appropriate voltage
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-24
MOSFET Intrinsic Capacitance (con’t)
• Below threshold, no mobile charge exists, so the inversion
layer charge dependent capacitances are zero
• In triode, the capacitances can be shown to be (note: Cox is
the per unit area term multiplied by WL)
CGS
⎡ ⎛ (V − V ) − V
2
T
DS
= Cox ⎢1 − ⎜⎜ GS
3
⎢⎣ ⎝ 2(VGS − VT ) − VDS
⎞
⎟⎟
⎠
2
⎡ ⎛
⎤
(VGS − VT )
2
⎥, CGD = Cox ⎢1 − ⎜⎜
3
⎥⎦
⎢⎣ ⎝ 2(VGS − VT ) − VDS
⎞
⎟⎟
⎠
2
⎤
⎥
⎥⎦
• For heavy triode operation (VDS << VGS – VT) CGS ≈ CGD ≈
Cox/2
• At pinchoff (VDS = VGS - VT) , CGS = 2/3Cox and CGD = 0
• In saturation, the capacitances are assumed to stay at their
pinchoff values
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-25
MOSFET Intrinsic Capacitance (con’t)
The intrinsic capacitances are plotted below
In the left hand plot, triode is x < 1, saturation x > 1
In the right hand plot, cutoff is x < 0, saturation 0 < x < 1, triode x > 1
The values in saturation are those at the pinchoff point
0.7
0.7
0.6
0.6
0.5
0.5
0.4
0.4
C/Cox
C/Cox
•
•
•
•
0.3
0.2
0.1
0
0
0.3
0.2
0.1
CGS
CGD
0.25
0.5
0.75
1
VDS/(VGS-VT)
1.25
1.5
0
-1
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
CGS
CGD
0
1
2
(VGS-VT)/VDS
3
4
Page 26-26
Example 26.3: Intrinsic Capacitance Calculation
Calculate the intrinsic gate source and gate drain capacitances
for the same device as the previous examples assuming
saturation operation
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-27
Example 26.3: Solution
• For saturation (VDS >> VGS – VT)
2
⋅ 8 × 10 − 4 ⋅1.8 × 10 − 4 ⋅1.73 × 10 −7 = 1.66 × 10 −14 F
3
=0
CGS =
CGD
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-28
Summary of Example Capacitances
•
•
The table below shows all capacitances calculated for the example
structure
For this example, the largest capacitances are associated with the
source and drain sidewalls (but note these are not connected to the
gate)
CAPACITANCE COMPONENT
Depletion (Sidewall)
SB
DB
Depletion (Bottom)
SB
DB
Extrinsic (Overlap)
GS
GD
GB
Intrinsic (saturation)
GS
GD
VALUE (fF)
35.5
24.3
9.5
6.5
1.38
1.38
0.22
16.6
0
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-29
High Frequency Small Signal Equivalent Circuit
•
If all the capacitance components are added to the low frequency small
signal equivalent circuit, the resulting high frequency small signal
equivalent circuit shown below is obtained
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-30
Lecture Summary
• The low frequency MOSFET small signal behavior is
determined by a transconductance and output conductance
• A large number of capacitive components have been
identified, but they fall into only a few categories based on
their physical origin
– Depletion capacitances associated with the bottom and sidewall of
the source and drain regions (same functional model as diode/BJT)
– Overlap capacitances, which are simple parallel plate structures
– Intrinsic capacitances, based on charge/voltage relationships in the
structure (similar idea to the diffusion capacitance Cπ in the BJT)
• Per unit area and per unit periphery quantities were
introduced to allow absolute values to be determined for a
particular device based on its geometry
ELEC 3908, Physical Electronics:
MOSFET Small Signal Modeling
Page 26-31
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