usb97cfdc
USB97CFDC
USB Floppy Disk Controller
FEATURES
- Supports Vertical Recording Format and High
Capacity Drives in User Written Firmware
Applications
- Detects All Overrun and Underrun Conditions
- Sophisticated Power Control Circuitry (PCC)
Including Multiple Powerdown Modes for
Reduced Power Consumption
3.3 Volt, Low Power Operation
Complete USB Specification 1.1 Compatibility
- Includes USB Transceiver
- Based on an Enhanced Version of SMSC’s
Industry Proven USB97C100 USB Controller
Complete System Solution Including USB Mass
Storage Class Compliant Win98/2000 Driver and
Firmware
- Supports 640K, 720K, 1.44M, 1.2M Windows 98
J, and 1.2M NEC DOS 6.x Formats
- Supports Both the UFI and SFF8070i Command
Sets
- Supports USB Mass Storage Compliant
Bootable Floppy BIOS
- 4ms Seek Times
- USB 1.1 Compliance, Including Low Power
Device Class SUSPEND Mode Operation and
Power Control of Disk Drive
- Disk Drive Feedback of Readiness Upon Power
Re-Application Option
- Option for Ultra High Performance Using
Additional Caching SRAM
- Support for Floppy Drive Power Control
- 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data
Rates
- Programmable Precompensation Modes
Intelligent Auto Power Management
- <300µA SUSPEND Current
- <75mA Operating Current
External Program Memory Interface
- 32K Byte Code Space (Supplied Firmware
Requires 16KB Memory)
- Flash, SRAM, or EPROM Memory
4KB Internal Buffer SRAM for High Performance
Operation
Optional External Cache Memory
- Up to 16K x 8 External SRAM may be Used for
Custom Tape/ Drive Applications
Contains SMSC’s Industry Proven Floppy Disk
Controller
- Licensed CMOS 765B Floppy Disk Controller
- Supports Single Normal or Three Mode Floppy
Drives
Enhanced Digital Data Separator
Integrated 14.318 MHz Crystal Driver Circuit
100 pin TQFP package (12.0 x 12.0 mm footprint)
- 25% smaller body size than other 100 pin TQFP
packages
ORDERING INFORMATION
Order Number: USB97CFDC-MN
100 Pin TQFP Package
SMSC DS – USB97CFDC
Rev. 12/15/2000
© STANDARD MICROSYSTEMS CORPORATION (SMSC) 2000
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC is a trademark of Standard Microsystems
Corporation. Product names and company names are the trademarks of their respective holders. Circuit diagrams utilizing SMSC products are included
as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. Although
the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make
changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the semiconductor devices described any
licenses under the patent rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most
recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product
may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly
sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application
where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an
Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well
as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT, AND ANY AND ALL WARRANTIES
ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES,
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR NOT
ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE
POSSIBILITY OF SUCH DAMAGES.
SMSC DS – USB97CFDC
Page 2
Rev. 12/15/2000
GENERAL DESCRIPTION
The USB97CFDC is an integration of the USB97C102 Enhanced Multi-Endpoint USB Peripheral Controller, without
its integrated hub functions, and the SMSC Floppy Disk Controller used in many of its Super IO products, such as
the FDC37C869. Special care in the interconnection of the two devices has been taken to assure the lowest possible
system current draw (<300µA) during SUSPEND mode operation.
Provisions for external Flash Memory up to 32K bytes for program storage is provided.
Although not required for standard floppy operation, provisions for 16K bytes of external buffer SRAM, in addition to
that included in the USB97C102 core, is also provided for extended applications, such as tape drives and for other
special applications.
Several pins are provided for controlling external power control elements and sensing specialized drive functions.
Note:
SMSC has developed and supplies firmware and drivers for this device to implement a standard three mode
or dual mode Floppy Disk Drive system with drive power control. If the customer desires to develop his own
firmware and/or drivers for this system, he may contact SMSC to obtain a complete engineering
specification which details all the internal block functions and register maps of the USB97CFDC to allow
custom programs to be written for this device.
SMSC DS – USB97CFDC
Page 3
Rev. 12/15/2000
TABLE OF CONTENTS
GENERAL DESCRIPTION............................................................................................................................3
DESCRIPTION OF PIN FUNCTIONS ...........................................................................................................5
PIN CONFIGURATION .................................................................................................................................6
BLOCK DIAGRAM ........................................................................................................................................7
PIN DESCRIPTIONS.....................................................................................................................................7
BUFFER TYPE DESCRIPTIONS............................................................................................................10
BOARD TEST MODE OPERATION ...........................................................................................................10
DC PARAMETERS .....................................................................................................................................11
AC PARAMETERS......................................................................................................................................12
USB PARAMETERS ...................................................................................................................................15
USB DC PARAMETERS .........................................................................................................................15
USB AC PARAMETERS .........................................................................................................................16
MECHANICAL OUTLINE............................................................................................................................18
APPENDIX A:..............................................................................................................................................19
USB97CFDC TYPICAL APPLICATION ..................................................................................................19
SMSC PROVIDED SOFTWARE FOR USB97CFDC .............................................................................20
USB97CFDC REVISIONS...........................................................................................................................20
SMSC DS – USB97CFDC
Page 4
Rev. 12/15/2000
DESCRIPTION OF PIN FUNCTIONS
nTRK0
nRDATA
nWDATA
nDSO
USB+
FD0
FD4
FA0
FA4
FA8
FA12
nFRD
SD0
SD4
SA0
SA4
SA8
SA12
nMEMEN
XTAL1/CLKIN
TST_OUT
SMSC DS – USB97CFDC
FLOPPY DISK INTERFACE (14 Pins)
nINDEX
nWRTPRT
DRVDEN0
DRVDEN1
nWGATE
nHDSEL
nMTR0
USB INTERFACE (4 Pins)
USBAVDD
FLASH ROM INTERFACE (26 Pins)
FD1
FD2
FD5
FD6
FA1
FA2
FA5
FA6
FA9
FA10
FA13
FA14
nFCE
SRAM/IO INTERFACE (24 Pins)
SD1
SD2
SD5
SD6
SA1
SA2
SA5
SA6
SA9
SA10
SA13
nMEMR
MISC (10 Pins)
OPTEN
nDRVRDY
XTAL2
nRESET
nTESTEN
POWER, GROUNDS, and NO CONNECTS (22 Pins)
Page 5
nDSKCHG
nSTEP
nDIR
AGND
FD3
FD7
FA3
FA7
FA11
FA15
SD3
SD7
SA3
SA7
SA11
nMEMW
nFDPWR
nTEST
Rev. 12/15/2000
nRDATA
nWRTPRT
nTRK0
nINDEX
nHDSEL
nWGATE
nWDATA
nSTEP
nDIR
GND
nDS0
nMTR0
DRVDEN0
AGND
USB+
VDD
USBAVDD
FA11
FA9
FA8
FA13
FA14
GND
N.C.
PIN CONFIGURATION
75
FA15
FA12
FA7
FA6
FA5
FA4
FA3
GND
FA2
FA1
FA0
VDD
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
nFCE
FA10
nFRD
GND
nFDPWR
USB97CFDC
1
25
SA10
SA9
SA8
SA7
SA6
SA5
SA4
GND
SA3
SA2
SA1
SA0
SA13
VDD
nTEST
nTESTEN
XTAL1/CLKIN
XTAL2
GND
N.C.
nRESET
TSTOUT
nMEMEN
OPTEN
nDRVRDY
nDSKCHG
DRVDEN1
N.C.
GND
N.C.
GND
VDD
N.C.
SD7
SD6
SD5
SD4
GND
SD3
SD2
SD1
SD0
VDD
N.C.
N.C.
N.C.
nMEMR
nMEMW
SA12
SA11
51
SMSC DS – USB97CFDC
Page 6
Rev. 12/15/2000
BLOCK DIAGRAM
To USB Bus
High Speed
USB
XCVR
End Point
Control
Serial Interface Engine
Memory
Management
Unit
Map RAM
CLOCK
CONTROL
SIE DMA
RX/
TX
Queue
Arbiter
FD[7:0]
Flash/
SRAM
Interface
FA[15:0]
4k Data Buffer RAM
nFRD
8051 CPU
nFCE
nMEMEN
Option
Select/
Drive
Control
8237
nOPTEN
nDRVRDY
GPIO
nFDPWR
IRQ0
DRIVE
INTERFACE
SA[13:0]
DRQ2
TC
nTRK0, nINDEX,
nWRTPRT, nDSKCHG
nRDATA, DRVDEN0,
DRVDEN1, nWDATA,
nWGATE, nHDSEL,
nDIR, nMTR0, nDS0,
nSTEP
nDAK2
nIOW
nMEMW
nMEMR
nIOR
FLOPPY DISK
CONTROLLER
SRAM
Interface
SD[7:0]
nCE
ADDRESS
DECODE
AEN
Pin Descriptions
PIN NO.
NAME
75
Read Disk
Data
69
Write
Data
71
Head
Select
67
Direction
Control
68
Step Pulse
76
Disk Change
SMSC DS – USB97CFDC
BUFFER
TYPE
SYMBOL
DESCRIPTION
FLOPPY DISK INTERFACE
nRDATA
IS
Raw serial bit stream from the disk drive, low
active.
Each falling edge represents a flux
transition of the encoded data.
nWDATA
OD12 This active low high current driver provides the
encoded data to the disk drive. Each falling edge
causes a flux transition on the media.
nHDSEL
OD12 This high current output selects the floppy disk
side for reading or writing. A logic "1" on this pin
means side 0 will be accessed, while a logic "0"
means side 1 will be accessed.
nDIR
OD12 This high current low active output determines the
direction of the head movement. A logic "1" on
this pin means outward motion, while a logic "0"
means inward motion.
nSTEP
OD12 This active low high current driver issues a low
pulse for each track-to-track movement of the
head.
nDSKCHG
IS
This input senses that the drive door is open or
that the diskette has possibly been changed since
the last drive selection.
Page 7
Rev. 12/15/2000
PIN NO.
63
NAME
DRVDEN 0
SYMBOL
DRVDEN 0
77
70
DRVDEN 1
Write Gate
DRVDEN1
nWGATE
73
Track 0
nTRK0
72
Index
nINDEX
74
Write Protect nWRTPRT
64
Motor On 0
65
Drive Select 0 nDS0
59
61
USB Bus
Data
USBUSB+
58
USB
Transceiver
Supply
USB
Transceiver
Ground
AVDD
62
nMTR0
Flash Memory FD[7:0]
Data Bus
50, 53, 54,
49, 57, 29,
56, 55, 4844, 42-40,
28
Flash Memory FA[15:0]
Address Bus
1-7,
9-13,
99,100
84-87,
89-92
97
98
Flash Memory nFRD
Read Strobe
Flash Memory nFCE
Chip Select
SRAM
Memory Bus
DESCRIPTION
An active low on this pin indicates a disk drive
spindle speed change from 300 RPM to 360 RPM
or 1.2M format disks in three mode drives. This
pin should be tied to the disk drives spindle speed
control input pin.
OD12 Reserved for future use.
OD12 This active low high current driver allows current to
flow through the write head. It becomes active just
prior to writing to the diskette.
IS
This active low Schmitt Trigger input senses from
the disk drive that the head is positioned over the
outermost track.
IS
This active low Schmitt Trigger input senses from
the disk drive that the head is positioned over the
beginning of a track, as marked by an index hole.
IS
This active low Schmitt Trigger input senses from
the disk drive that a disk is write protected. Any
write command is ignored.
OD12 This active low open drain output selects motor
drive 0.
OD12 This active low open drain output selects drive 0.
USB INTERFACE
IO-U
These pins connect to the USB data signals
through 33 ohm series resistors. The USB+ line
should be pulled up with a 5%, 1.5K ohm resistor
to indicate that this is a high speed USB device.
This is the 3.3V supply to the internal USB
transceiver.
OD12
AGND
31-38
30
BUFFER
TYPE
SA[13:0]
This is the supply ground for the internal USB
transceiver.
FLASH INTERFACE
IO8
These signals are used to transfer data between
the internal 8051 and the external FLASH program
memory.
O8
These signals address memory locations within
the FLASH memory.
O8
Flash ROM Read; active low
O8
Flash ROM Chip Select; active low
SRAM/IO INTERFACE
O8
These signals provide the memory address to an
external SRAM buffer.
SD[7:0]
SRAM
Memory Data
Bus
nMEMR
SRAM
Memory Read
Strobe
I/O8
These signals are used to transfer data to/from the
SRAM Memory.
O8
nMEMW
SRAM
Memory Write
Strobe
O8
Memory read; active low
This active low signal indicates that data is to be
driven onto the data bus by the SRAM. Data will
be latched internal to the chip on the rising edge of
this signal
Memory write; active low
This active low signal indicates to the SRAM to
load data from the data bus on its rising edge.
SMSC DS – USB97CFDC
Page 8
Rev. 12/15/2000
PIN NO.
NAME
17
Crystal
Input/External
Clock Input
18
Crystal
Output
23
SRAM Enable
24
Option Enable
25
Drive Ready
26
Drive Power
21
RESET input
22
Test output
15
Test input
16
Test Enable
14, 39, 60,
82, 93
8, 19, 27, 43,
52, 66, 79,
81, 88
20, 51, 78,
80, 83, 94-96
SMSC DS – USB97CFDC
SYMBOL
BUFFER
TYPE
DESCRIPTION
MISCELLANEOUS
XTAL1/
ICLKx 14.318Mhz Crystal or clock input.
CLKIN
This pin can be connected to one terminal of the
crystal or can be connected to an external
14.318Mhz clock when a crystal is not used.
XTAL2
OCLKx 14.318Mhz Crystal
This is the other terminal of the crystal, or left
open when an external clock source is used to
drive XTAL1/CLKIN. It may not be used to drive
any external circuitry other than the crystal circuit.
nMEMEN
O24
An active low signal is output on this pin to enable
the optional external SRAM for extended FDC
write and read caching for ultra high performance
applications.
OPTEN
I
Current firmware utilizes this input pin for
detecting the media density switch of the drive.
Various firmware options are available for different
polarities of this signal. Contact factory for
available firmware options. If this pin is not driven
by the drive, it should be tied low.
nDRVRDY
I
An active low signal on this pin from the floppy
disk drive, after DS0 goes active, indicates that
the system may activate MTR0. If the drive does
not supply this signal, this pin should be tied low.
nFDPWR
OD24 This active low signal is intended to activate an
external power switch, either in the drive or on the
system board, to supply power to the floppy disk
drive. It is active whenever the USB97CFDC is not
in SUSPEND mode.
nRESET
IS
This active low signal is used by the system to
reset the chip. The active low pulse should be at
least 100ns wide.
TSTOUT
O8
This signal is used for testing the chip via an
internal XNOR chain. User should normally leave
it unconnected.
nTEST
I
This signal is a manufacturing test pin. It should
be tied to VDD for normal operation.
nTESTEN
I
This active low signal places the device into board
test mode using the XNOR chain. For normal
operation this pin should be tied high. See Board
Test Mode Operation on page 10
POWER, GROUND, AND NO CONNECTS
VDD
+3.3V power
GND
Ground Reference
NC
No Connect. These pins should not be connected
externally.
Page 9
Rev. 12/15/2000
BUFFER TYPE DESCRIPTIONS
Table 1 - USB97CFDC Buffer Type Descriptions
BUFFER
DESCRIPTION
I
Input
IS
Input with Schmitt trigger
O8
Output with 8mA drive
I/O8
Input/output with 8mA drive
OD12
Open drain….12mA sink
O24
Output with 24mA drive
OD24
Open drain….24mA sink
ICLKx
XTAL clock input
OCLKx
XTAL clock output
I/O-U
See Table 6.
BOARD TEST MODE OPERATION
By driving the nTESTEN pin low, the device will be placed into a special test mode to allow verification of attachment
of the device to the circuit board. Every pin except the TSTOUT, XTAL2, and the power and ground pins become an
input to an XNOR chain, as shown below, to allow continuity to be tested on the board. This test should individually
toggle the state of the trace connected to the pin being examined for continuity, and the TSTOUT pin monitored for
toggle of state. If no toggle occurs, either the pin under test is discontinuous, or the TSTOUT pin is not connected on
the board
Pin1
Pin2
Pin3
Pin100
TSTOUT
SMSC DS – USB97CFDC
Page 10
Rev. 12/15/2000
DC PARAMETERS
MAXIMUM GUARANTEED RATINGS
o
o
Operating Temperature Range ...........................................................................................................................0 C to +70 C
o
o
Storage Temperature Range ........................................................................................................................... -55 to +150 C
o
Lead Temperature Range (soldering, 10 seconds).....................................................................................................+325 C
Positive Voltage on any pin, with respect to Ground (Note 1)...................................................................................Vcc+0.3V
Negative Voltage on any pin, with respect to Ground .................................................................................................... -0.3V
Maximum Vcc .................................................................................................................................................................. +3.6V
Note 1: Maximum voltage on all I type Inputs and the IS inputs, OD12 and OD24 outputs for floppy disk drive interface is
5.25V
*Stresses above the specified parameters could cause permanent damage to the device. This is a stress rating only
and functional operation of the device at any other condition above those indicated in the operation sections of this
specification is not implied.
Note 2: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum
Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when
the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output.
When this possibility exists, it is suggested that a clamp circuit be used.
DC ELECTRICAL CHARACTERISTICS (TA = 0°C - 70°C, Vcc = +3.3 V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
I Type Input Buffer
Low Input Level
VILI
High Input Level
ICLK Input Buffer
VIHI
0.8
2.0
V
TTL Levels
V
0.4
V
Low Input Level
VILCK
High Input Level
Input Leakage
(All I and IS buffers)
VIHCK
2.2
Low Input Leakage
IIL
-10
+10
uA
VIN = 0
High Input Leakage
O8 Type Buffer
IIH
-10
+10
uA
VIN = VCC
0.4
V
IOL = 8 mA
V
IOH = -4 mA
Low Output Level
VOL
High Output Level
VOH
2.4
Output Leakage
I/O8 Type Buffer
IOL
-10
Low Output Level
VOL
High Output Level
VOH
2.4
Output Leakage
OD12 Type Buffer
IOL
-10
Low Output Level
VOL
Output Leakage
IOL
SMSC DS – USB97CFDC
V
-10
Page 11
VIN = 0 to VCC (Note 1)
+10
UA
0.4
V
IOL = 8mA
V
IOH = -4mA
+10
µA
VIN = 0 to Vcc (Note 1)
0.4
V
IOL = 12mA
+10
µA
VIN = 0 to Vcc (Note 1)
Rev. 12/15/2000
PARAMETER
O24 Type Buffer
SYMBOL
MIN
Low Output Level
VOL
High Output Level
VOH
2.4
Output Leakage
OD24 Type Buffer
IOL
-10
Low Output Level
VOL
Output Leakage
IO-U
Note 2
Supply Current Active
Supply Current
Standby
IOL
TYP
-10
MAX
UNITS
0.4
V
IOL = 24mA
V
IOH = -12mA
+10
µA
VIN = 0 to Vcc (Note 1)
0.4
V
IOL = 24mA
+10
µA
VIN = 0 to Vcc (Note 1)
All outputs open.
ICC
30
75
MA
ICSBU
120
300
µA
COMMENTS
Note 1: Output leakage is measured with the current pins in high impedance.
Note 2: See Appendix A for USB DC electrical characteristics.
CAPACITANCE TA = 25°C; fc = 1MHz; VCC = 3.3V
LIMITS
PARAMETER
SYMBOL MIN TYP MAX UNIT
TEST CONDITION
All pins except USB pins
Clock Input Capacitance
CIN
20
pF
(and pins under test tied
Input Capacitance
CIN
10
pF
to AC ground)
Output Capacitance
COUT
20
pF
AC PARAMETERS
t1
t2
t2
CLOCKI
FIGURE 1 - INPUT CLOCK TIMING
NAME
t1
t2
tr , tf
Table 2 – Input Clock Timing Parameters
DESCRIPTION
MIN
TYP
Clock Cycle Time for 14.318MHz
69.84
Clock High Time/Low Time for 24MHz
41.9/
27.9
Clock Rise Time/Fall Time (not shown)
SMSC DS – USB97CFDC
Page 12
MAX
27.9/
41.9
5
UNITS
ns
ns
ns
Rev. 12/15/2000
t5
t1
FA[0:19
]
t3
t4
FD [7:0
nFR D
t2
nFW R
FIGURE 2 – FLASH READ TIMING
NAME
t1
t2
t3
t4
t5
Table 3 – Flash Read Timing
PARAMETER
MIN
FA[14:0] Address setup time to nFRD asserted
40
nFRD pulse width
110
FD[7:0] Data setup time to nFRD de-asserted
30
FD[7:0] Data hold time from nFRD de-asserted
0
FA[14:0] Address hold time from nFRD de-asserted
35
t1
TYP
MAX
UNITS
ns
ns
ns
ns
ns
t5
S A [1 3:0
t3
t4
S D [7:0
nM E M W
t2
FIGURE 3 – SRAM MEMORY WRITE TIMING
NAME
t1
t2
t3
t4
t5
Table 4 – SRAM Memory Write Timing
PARAMETER
MIN
SA[19:0] valid before nMEMWR asserted
10
nMEMWR pulse width
100
SD[7:0] Data setup time to nMEMWR de-asserted
50
SD[7:0] Data hold time from nMEMWR de-asserted
10
nMEMWR de-asserted to SA[13:0] invalid
10
SMSC DS – USB97CFDC
Page 13
TYP
MAX
UNITS
ns
ns
ns
ns
ns
Rev. 12/15/2000
t1
t5
S A [1 3 :0
t3
t4
S D [7 :0 ]
nM E M R
t2
FIGURE 4 - SRAM MEMORY READ TIMING
NAME
t1
t2
t3
t4
t5
Table 5 – SRAM Memory Read Timing
PARAMETER
MIN
SA[19:0] valid before nMEMRD asserted
10
nMEMRD pulse width
100
SD[7:0] Data setup time to nMEMRD de-asserted
50
SD[7:0] Data hold time from nMEMRD de-asserted
20
nMEMRD de-asserted to SA [13:0] invalid
10
TYP
MAX
UNITS
ns
ns
ns
ns
ns
t3
nDIR
t4
t1
t2
nSTEP
t5
nDS0
nINDEX
t6
t7
nRDATA
t8
nWDATA
NAME
PARAMETER
MIN
t1
t2
t3
t4
t5
t6
t7
t8
nDIR Set Up to nSTEP Low
nSTEP Active Time Low
nDIR Hold Time After nSTEP
nSTEP Cycle Time
nDS0-1 Hold Time from nSTEP Low
nINDEX Pulse Width
nRDATA Active Time Low
nWDATA Write Data Width Low
TYP
4
24
96
132
20
2
40
.5
MAX
UNITS
X*
X*
X*
X*
X*
X*
ns
Y*
*X specifies one MCLK period and Y specifies one WCLK period.
MCLK = 16x Data Rate (at 500 Kbp/s MCLK = 8 MHz)
WCLK = 2x Data Rate (at 500 Kbp/s WCLK = 1 MHz)
FIGURE 5 - DISK DRIVE TIMING
SMSC DS – USB97CFDC
Page 14
Rev. 12/15/2000
USB PARAMETERS
The following tables and diagrams were obtained from the USB specification
Minimum Differential Sensitivity (volts)
USB DC PARAMETERS
1.0
0.8
0.6
0.4
0.2
0.0
0.0 0.2 0.4
0.6
0.8 1.0
1.2
1.4
1.6 1.8
2.0
2.2 2.4
2.6
2.8 3.0
3.2
Common Mode Input Voltage (volts)
FIGURE 6 - DIFFERENTIAL INPUT SENSITIVITY OVER ENTIRE COMMON MODE RANGE
PARAMETER
Supply Voltage
Powered (Host or Hub) Port
Supply Current
Function
Un-configured Function (in)
Suspend Device
Leakage Current
Hi-Z State Data Line
Leakage
Input Levels
Differential Input Sensitivity
Table 6 - DC Electrical Characteristics
CONDITIONS
SYMBOL
(NOTE 1, 2)
MIN
VBUS
ICC
ICCINIT
ICCS
Note 4
Note 5
ILO
0 V < VIN < 3.3
V
-10
VDI
|(D+) - (D-)|,
and FIGURE 6
Includes VDI
range
0.2
Differential Common Mode
Range
Single Ended Receiver
Threshold
Output Levels
Static Output Low
VCM
Static Output High
VOH
Capacitance
Transceiver Capacitance
Terminals
Bus Pull-up Resistor on
Root Port
Bus Pull-down Resistor on
Downstream Port
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
4.4
VSE
VOL
RL of 1.5 KΩ to
3.6 V
RL of 15 KΩ to
GND
TYP
MAX
UNIT
5.25
V
100
100
100
mA
uA
uA
10
uA
V
0.8
2.5
V
0.8
2.0
V
0.3 (3)
V
3.6 (3)
V
20
pF
2.8
CIN
Pin to GND
RPU
(1.5 KΩ +/- 5%)
1.425
1.575
kΩ
RPD
(15 KΩ +/- 5%)
14.25
15.75
kΩ
All voltages are measured from the local ground potential, unless otherwise specified.
All timing use a capacitive load (CL) to ground of 50pF, unless otherwise specified.
This is relative to VUSBIN.
This is dependent on block configuration set by software.
When the internal ring oscillator and waiting for first setup packet.
SMSC DS – USB97CFDC
Page 15
Rev. 12/15/2000
USB AC PARAMETERS
Rise Time
CL
Fall Time
90%
Differential
Data Lines
90%
10%
CL
10%
tR
tF
Full Speed: 4 to 20ns at CL = 50pF
FIGURE 7 - DATA SIGNAL RISE AND FALL TIME
TPERIOD
Differential
Data Lines
Crossover
Points
Consecutive
Transitions
N * TPERIOD + TxJR1
Paired
Transitions
N * TPERIOD + TxJR2
FIGURE 8 - DIFFERENTIAL DATA JITTER
TPERIOD
Differential
Data Lines
Crossover
Point Extended
Crossover
Point
Diff. Data to
SE0 Skew
N * TPERIOD + TDEOP
Source EOP Width: TEOPT
Receiver EOP Width: TEOPR1, TEOPR2
FIGURE 9 - DIFFERENTIAL TO EOP TRANSITION SKEW AND EOP WIDTH
TPERIOD
Differential
Data Lines
TJR
TJR1
TJR2
Consecutive
Transitions
N * TPERIOD + TJR1
Paired
Transitions
N * TPERIOD + TJR2
FIGURE 10 - RECEIVER JITTER TOLERANCE
SMSC DS – USB97CFDC
Page 16
Rev. 12/15/2000
Table 2 - Full Speed (12Mbps) Source Electrical Characteristics
CONDITIONS
PARAMETER
SYM
(NOTE 1, 2, 3)
MIN
TYP
MAX
Driver Characteristics
Transition Time:
Note 4,5 and
FIGURE 7
Rise Time
TR
CL = 50 pF
4
20
Fall Time
Rise/Fall Time Matching
Output Signal
Crossover Voltage
Drive Output
Resistance
Data Source Timing
Full Speed Data Rate
Frame Interval
TFRAME
Differential to EOP
transition Skew
Receiver Data Jitter
Tolerance
To next Transition
For Paired Transitions
EOP Width at receiver
CL = 50 pF
(TR/TF)
4
90
1.3
20
110
2.0
ns
%
V
ZDRV
Steady State Drive
28
43
Ω
TDRATE
Ave. Bit Rate
(12 Mb/s +/0.25%) Note 8
1.0 ms +/- 0.05%
11.95
12.03
Mbs
0.999
5
1.0005
ms
-3.5
-4.0
3.5
4.0
ns
ns
160
175
ns
-2
5
ns
-18.5
-9
18.5
9.0
ns
ns
Note 6, 7 and
FIGURE 8
TDJ1
TDJ2
TEOPT
TDEOP
Note 7 and
FIGURE 9
Note 7 and
FIGURE 9
Note 7 and
FIGURE 10
TJR1
TJR2
Note 7 and
FIGURE 9
Must reject as EOP
Must Accept
TEOPR1
TEOPR2
Cable Impedance and Timing
Cable Impedance (Full
ZO
Speed)
Cable Delay (One Way)
TCBL
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
ns
TF
TRFM
VCRS
Source Differential
Driver Jitter
To next Transition
For Paired Transitions
Source EOP Width
UNIT
40
82
(45 Ω +/- 15%)
38.75
ns
ns
51.75
Ω
30
ns
All voltages are measured from the local ground potential, unless otherwise specified.
All timing use a capacitive load (CL) to ground of 50pF, unless otherwise specified.
Full speed timings have a 1.5KΩ pull-up to 2.8 V on the D+ data line.
Measured from 10% to 90% of the data signals.
The rising and falling edges should be smoothly transiting (monotonic).
Timing differences between the differential data signals.
Measured at crossover point of differential data signals.
These are relative to the 14.318 MHz crystal.
SMSC DS – USB97CFDC
Page 17
Rev. 12/15/2000
MECHANICAL OUTLINE
FIGURE 11 - 100 PIN TQFP PACKAGE
A
A1
A2
D
D/2
D1
E
E/2
E1
H
L
L1
e
MIN
~
0.05
1.35
13.80
6.90
11.80
13.80
6.90
11.80
0.09
0.45
~
o
W
R1
R2
ccc
0
0.13
0.08
0.08
~
NOMINAL
~
~
1.40
14.00
7.00
12.00
14.00
7.00
12.00
~
0.60
1.00
0.40 Basic
o
3.5
0.16
~
~
~
MAX
1.60
0.15
1.45
14.20
7.10
12.20
14.20
7.10
12.20
0.20
0.75
~
o
7
0.23
~
0.20
0.08
REMARK
Overall Package Height
Standoff
Body Thickness
X Span
1
/2 X Span Measure from Centerline
X body Size
Y Span
1
/2 Y Span Measure from Centerline
Y body Size
Lead Frame Thickness
Lead Foot Length from Centerline
Lead Length
Lead Pitch
Lead Foot Angle
Lead Width
Lead Shoulder Radius
Lead Foot Radius
Coplanarity
Note 1: Controlling Unit: millimeter
Note 2: Minimum space between protrusion and an adjacent lead is .007 mm.
Note 3: Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm
Note 5: Details of pin 1 identifier are optional but must be located within the zone indicated.
SMSC DS – USB97CFDC
Page 18
Rev. 12/15/2000
APPENDIX A:
FVDD
FLOPPY
JP1
VCC
P1
R1 10ohm
1
2
3
4
C2
.1uF
C3
.1uF
RN1
C4
.1uF
#1.2M
#HHDOUT
#DSKSTAT
#INDEX
#MTR0
#DS1
#DS0
#MTR1
#DIR
#STEP
#WDATA
#WGATE
#TRK0
#WP
#RDATA
#HDSEL
#DSKCHG
C1
.1uF
FVDD
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
VCC
FVDD
USB97CFDC TYPICAL APPLICATION
HDO
R2 10ohm
R3
10K
5%
1/10W
R4
1.5K
VCC
DD+
GND
USB TYPE B
nDRVRDY
1K x 5
VDD
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
U1
TP2
RN2
VDD
USB97CFDC
FA15
FA12
FA7
FA6
FA5
FA4
FA3
GND
FA2
FA1
FA0
VDD
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
nFCE
FA10
nFRD
GND
nFDPWR
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
13
14
15
17
18
19
20
21
nFDPWR
2
3
30
D0
D1
D2
D3
D4
D5
D6
D7
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
10K x 8
nDSKCHG
DRVDEN1
N.C.
GND
N.C.
GND
VDD
N.C.
SD7
SD6
SD5
SD4
GND
SD3
SD2
SD1
SD0
VDD
N.C.
N.C.
N.C.
nMEMR
nMEMW
SA12
SA11
nRDATA
nWRTPRT
nTRK0
nINDEX
nHDSEL
nWGATE
nWDATA
nSTEP
nDIR
GND
nDS0
nMTR0
DRVDEN0
AGND
USB+
VDD
USBAVDD
FA11
FA9
FA8
FA13
FA14
GND
N.C.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
TP1
SA10
SA9
SA8
SA7
SA6
SA5
SA4
GND
SA3
SA2
SA1
SA0
SA13
VDD
nTEST
VDD
XTAL1/CLKIN
XTAL2
GND
N.C.
nRESET
TSTOUT
nMEMEN
OPTEN
nDRVRDY
Note: If SD
pins not used,
tie to ground to
prevent pins
from floating
during
suspend
mode.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
nDRVRDY
TP3
3.3V Regulator
VCC
VR1
VIN
GND
3
C6
10uF
VOUT
VDD
2
+
C5
10uF
39pf
C7
VCC
1
+
15K
R5
R7
VDD
nFDPWR
C11
.1uF
C12
.1uF
C13
.1uF
CE
OE
WE
VPP
U2
22
24
31
1
28F256
HDO
Y1
14.318Mhz
1µf
C8
15pf
C9
C14
.1uF
Title
USB97CFDC Typical Application
Size
B
Date:
SMSC DS – USB97CFDC
VDD
Q1
MOSFET P
FVDD
C10
.1uF
180K
R6
Note: IF DRIVE
DOES NOT
SUPPLY
nDRVRDY OR
HDO SIGNAL,
THEY
SHOULD BE
TIED LOW AT
U1
Page 19
Document Number
Rev
G
Wednesday, December 13, 2000
Sheet
1
Rev. 12/15/2000
of
1
SMSC PROVIDED SOFTWARE FOR USB97CFDC
SMSC provides the following for the USB97CFDC:
I.
Program firmware with the following features:
(a) Supports 640K, 720K, 1.44M, 1.2M Windows J, 1.2M NEC DOS 6.x formats.
(b) Supports USB Mass Storage Class compliant drivers from Apple and Microsoft as well as SMSC’s
Windows 98 driver.
(c) Supports USB Mass Storage compliant bootable floppy BIOS.
(d) 4ms Seek times.
(e) USB 1.1 compliance, including low power device class SUSPEND mode operation and power control of
disk drive.
(f)
Disk drive feedback of readiness upon power re-application (optional).
(g) Option for using drive media density sense output (HDO#) pin to prevent attempts to format 2DD disks as
2HD.
II.
USB Mass Storage Class compliant driver for Windows 98.
USB97CFDC REVISIONS
PAGE(S)
SECTION/FIGURE/ENTRY
CORRECTION
DATE REVISED
19
USB97CFDC TYPICAL
APPLICATION
Updated schematic
12/15/00
19
USB97CFDC TYPICAL
APPLICATION
Updated schematic
11/01/00
SMSC DS – USB97CFDC
Page 20
Rev. 12/15/2000
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