Lecture 43 slides
ECEN4827/5827 Lecture 43
HW Buck Voltage Regulator
ECEN4827/5827 Analog IC Design
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Start-up and step-load transient
ECEN4827/5827 Analog IC Design
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Pulse-Width Modulator
Saw-tooth
waveform
p (t )
Q
vsaw (t )
+
_
R
S
vc(t)
vc
control
input
vsaw(t)
VM
0
t
p(t)
clock
OSC
0
dTs
Ts
2Ts
clock
Improvement: PWM with feed-forward compensation:
VM proportional to the input voltage vg
ECEN4827/5827 Analog IC Design
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PWM model
VC  vˆc
VM
1
VM
D  dˆ
1
VM
D
Vc
VM
is the amplitude of the saw-tooth waveform
is the gain of the Pulse-Width Modulator
dˆ
1

vˆc VM
With feed-forward compensation: VM = k Vg
D
1 Vc
k Vg
1
DVg  Vc
k
=> improved line regulation
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Pulse-Width Modulator Realization
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PWM operation
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Introduction to voltage comparators
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Open-loop op-amp as voltage comparator
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Propagation delay test circuit
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Open-loop op-amp as a comparator: propagation delays
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No negative feedback: no need for compensation
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Propagation delays without Cc
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Reduce component aspect ratios: reduce parasitic caps
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Reduced (W/L)’s: propagation delays
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Increase bias current
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Ibias = parameter: 1u, 2u, 5u, 10u
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Ibias = parameter: 1u, 2u, 5u, 10u
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Ibias = parameter: 1u, 2u, 5u, 10u
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Application: PWM
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PWM operation
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PWM operation details
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HW circuit example
Gm  100μA/V
Gm
 1.6 kHz
2Cc
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Converter transfer functions*
(small-signal averaged model)
vˆ  Gvc ( s )vˆc  Gvg ( s )vˆg  Z out ( s )iˆo
Gvc (s )
Control-to-output transfer function, relevant for closing
the feedback loop around the converter
Gvg (s )
Line-to-output transfer function, relevant for finding
output voltage variations due to battery-voltage variations
Z out (s )
Output impedance, relevant for finding output voltage
variations due to load current variations
Vg d
L
iL
+
vg
+
–
D iL
+
–
D vg
C
Io d
R
v
io
–
*Material covered in detail in ECEN4797/5797
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Example:
voltage-mode control-to-output response
Derive open-loop voltage-mode model of the buck converter that
includes conduction losses due to the switch on-resistances
Ron,p=Ron,n=Ron, the inductor winding resistance RL and the
capacitor ESR Resr
Given:
• Ron,p=Ron,n=Ron = 0.4
• L = 10 H, RL = 0.1
• C = 22 F, Resr = 10 m
• Vg=3.6V, Vo=1.5 V, Io=300 mA, VM=1V
sketch the magnitude and phase responses of the control-to-output
transfer function
ECEN4827/5827 Analog IC Design
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Small-signal dynamic (AC) model
Vg d
Ron + RL
L
iL
+
vg
+
–
D iL
+
–
Resr
R
D vg
v
io
C
Io d
–
Standard circuit analysis yields converter open-loop transfer
functions
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Solution: converter control-to-output response
Gvc ( s ) 
Vg
VM
s
1
wz
wo 
1 s  s
1
 
Qr wo  wo 
2
1
LC
Q
R
L/C
C
1
1
 
( Ron  RL  Resr )
Qr Q
L
Notes:
• The center frequency of the pair of poles is essentially
the same as without losses
• The quality factor Qr can be significantly reduced
because of the losses
• The transfer function includes a high-frequency zero
due to the capacitor ESR
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Solution: numerical results
Low-frequency gain:
Gvc (0) 
Pole center frequency:
1
fo 
2
Q-factor without losses:
Q-factor with losses:
Q
Qr 
Vg
VM
 3.6  11 dB
1
 11 KHz
LC
R
 7.4  17 dB
L/C
1
1
C

( Ron  RL  Resr )
Q
L
ECEN4827/5827 Analog IC Design
 1.1
27
Solution: control-to-output
magnitude and phase responses
100.
30
500.
1000.
5000.
10000.
50000.
No losses
20
Magnitude response
20 log Gvc ( jw) [dB]
With
losses
10
0
-10
-20
100.
Phase response
500.
500.
1000.
1000.
5000.
5000.
10000.
10000.
50000.
50000.
100000.
500.
1000.
5000.
10000.
50000.
100000.
0
-100
-200
-300
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HW circuit example
Gm  100μA/V
Gm
 1.6 kHz
2Cc
Gvc (0) 
Vg
VM
1
fo 
2
 3.3  10.4 dB
1
 36 KHz
LC
R
Q
 17.9  25 dB
L/C
1
 1.6  4 dB
Qr 
1
C

( Ron )
Q
L
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 G 
f c   m Gvc (0)  5.3 kHz
 2Cc 
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Start-up and load transient
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Dynamic response improvements
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Example: 5827_PWM1.asc
Buck switched-mode DC-DC converter
g
L1
sw
Vg
SW
3.3
cinv
I1
PWL(0A 0 800u 0A 801u 1A)
100µ
ECEN4827/5827 PWM controller behavioral model
A1
c
R1
1
C1
S2
Bpwm
V=if(v(ctrl,t)+0.5,1,0)
out
1µ
ctrl
t
Control
voltage vc
R3
C2
R4
C3
30k
0.1n
1k
0.5n
R2
U1
100k
.lib opamp.sub
Vsaw
ref
S1
SW
.model SW SW(Ron=.05 Roff=1Meg Vt=0.5 Vh=0)
Vref
PWL(0 0 500u 1)
PULSE({Vlow} {Vhigh} 0 {Tr} {Ts-Tr} 0 {Ts})
.param Fs=1meg Tr={0.9/Fs} Ts={1/Fs} Vlow=1 Vhigh=2
.tran 0 1000u 0 2n
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Start-up and load transient
2.7A
2.4A
2.1A
1.8A
1.5A
1.2A
0.9A
0.6A
0.3A
0.0A
-0.3A
I(L1)
Inductor current
V(out)
1.5V
1.3V
V(ctrl)
Control voltage
1.1V
0.9V
0.7V
0.5V
0.3V
Output voltage
0.1V
-0.1V
0µs
100µs
200µs
300µs
400µs
500µs
600µs
ECEN4827/5827 Analog IC Design
700µs
800µs
900µs
1000µs
34
Voltage regulation during step-load transient
Inductor current
2.8A
2.6A
2.4A
2.2A
2.0A
1.8A
1.6A
1.4A
1.2A
1.0A
0.8A
0.6A
0.4A
1.020V
1.014V
1.008V
1.002V
0.996V
0.990V
0.984V
0.978V
0.972V
0.966V
0.960V
0.954V
798µs
I(L1)
V(out)
V(ctrl)
Output voltage
801µs
804µs
807µs
810µs
813µs
816µs
819µs
822µs
ECEN4827/5827 Analog IC Design
825µs
828µs
831µs
834µs
35
ECEN4827/5827 course topics
Buck switched-mode DC-DC converter
S1
SW
.model SW SW(Ron=.05 Roff=1Meg Vt=0.5 Vh=0)
g
L1
sw
Vg
SW
3.3
1µ
cinv
I1
PWL(0A 0 800u 0A 801u 1A)
100µ
A1
ECEN4827/5827 PWM controller behavioral model
R3
C2
R4
C3
30k
0.1n
1k
0.5n
MOSFETs and
driver circuits
R2
U1
V=if(v(ctrl,t)+0.5,1,0)
ctrl
t
Op-amp design
.lib opamp.sub
Vsaw
PULSE({Vlow} {Vhigh} 0 {Tr} {Ts-Tr} 0 {Ts})
100k
ref
Bpwm
PWM oscillators,
waveform
generators, and
voltage comparators
R1
1
C1
S2
c
out
Vref
PWL(0 0 500u 1)
Feedback
Bandgap reference design,
DC biasing
.param Fs=1meg Tr={0.9/Fs} Ts={1/Fs} Vlow=1 Vhigh=2
.tran 0 1000u 0 2n
Transistor-level integrated circuit design techniques
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