AK4636EN

AK4636EN
[AKD4636EN-A]
AKD4636EN-A
Evaluation board Rev.0 forAK4636EN
GENERAL DESCRIPTION
AKD4636EN-A is an evaluation board for the AK4636EN, 16bit mono CODEC with MIC/SPK/VIDEO
amplifier. The AKD4636EN-A can evaluate A/D converter and D/A converter separately in addition to
loop-back mode (A/D → D/A). AKD4636EN-A also has the digital audio interface and can achieve the
interface with digital audio systems via opt-connector.
„ Ordering guide
AKD4636EN-A ---
Evaluation board for AK4636EN
(Cable for connecting with printer port of IBM-AT compatible PC and control software
are packed with this. This control software does not operate on Windows NT.)
FUNCTION
• DIT/DIR with optical input/output
• BNC connector for an external clock input
• 10pin Header for serial control mode
AVDD DVDD VVDD SVDD GND
5V
3.3V
Regulator
Control Data
MIC-Jack
MIC/
MICP/
DMDAT
10pin Header
Digital
MicroPhone
DSP
AK4636
10pin Header
LIN/
MICN/
DMCLK
AOUT
AK4114
SPK-Jack
Opt In
Opt Out
Clock
Gen
VIN VOUT
Figure 1. AKD4636EN Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
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Board Outline Chart
„ Outline Chart
TORX
141
PORT1
1
10
5
6
DGND
VCC
VOUT
VIN
J7
J6
VVDD
DVDD
SW1 SW2
AVDD
AVSS
REG
T1
U1
U8
J1
AK4636
PORT4
MICJACK
74LVC245
AK4114
U6
U9
PORT3
1
MIC
J3
10
74HC541
5
6
PORT2
TOTX
141
DGND
AREA
SPK1
AOUT
AGND
AREA
J9
J8
J2
FCK
EXT/
BICK
SPKJACK
J5
SVDD
SVSS
J4
BEEP/
LIN/
MICN
Figure 2. AKD4636EN-A Outline Chart
„ Comment
(1) J1, J2 (MINI-JACK)
J1 (MIC-JACK): It is analog signal input Jack. The signal is input to MIC pin.
J2 (SPK-JACK): It is analog signal output Jack. The signal is output from SPP/SPN pins.
(2) J3, J4, J5, J6, J7 (RCA-JACK)
J3 (white): An analog signal input Jack. The signal is input to MIC pin.
J4 (white): An analog signal input Jack. The signal is input to BEEP pin.
J5 (white): An analog signal output Jack. The signal is output from AOUT pin.
J6 (yellow): A video signal input Jack. The signal is input to VIN pin.
J7 (yellow): A video signal output Jack. The signal is output from VOUT pin.
(3) REG, AVDD, VVDD, DVDD, VCC, SVDD, AVSS, SVSS, DGND
These are the power supply connectors. Connect power supply with these pins.
As for the detail comments, refer to the setup of power supply in P4.
(4) SPK1 (dynamic speaker)
The analog signal from SPP and SPN pins can be output to SPK1.
(5) PORT4 (10 pin header)
Control port. Connect the bundled cable into this port.
(6) PORT3 (10 pin header)
The clock and data can be input and output with this connector.
(7) PORT1, PORT2 (Optical Connecter)
PORT1 (Input): Optical digital signal (SPDIF, Fs: 32~48kHz) is input to the AK4114.
PORT2 (Output): Optical digital signal (SPDIF, Fs: 32~48kHz) is output from the AK4114.
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„ Operation sequence
1) Set up the power supply lines.
1-1) When AVDD, VVDD, DVDD, SVDD and VCC are supplied from the regulator. <Default>
Set up the jumper pins.
JP3
AVDD_SEL
REG
JP4
SVDD_SEL
AVDD SVDD
JP9
DVDD_SEL
JP10
LVC_SEL
REG DVDD AVDD VCC
JP11
VCC_SEL
DVDD VCC
LVC
Set up the power supply lines.
Name
Color
Voltage
Comments
REG
Red
5V
Input to regulator.
AVDD
Orange
Open
3.3V is supplied to AVDD of AK4636EN from regulator.
VVDD
Blue
Open
3.3V is supplied to VVDD of AK4636EN from regulator.
DVDD
Orange
Open
3.3V is supplied to DVDD of AK4636EN from regulator.
SVDD
Blue
Open
3.3V is supplied to SVDD of AK4636EN from regulator.
VCC
Orange
Open
3.3V is supplied to logic block from regulator.
AVSS
Black
0V
For analog ground.
SVSS
Black
0V
For analog ground.
DGND
Black
0V
For logic ground.
Table 1 Set up of power supply lines
1-2) When AVDD, VVDD, DVDD, SVDD and VCC are supplied from the power supply connectors.
Set up the jumper pins.
JP3
AVDD_SEL
REG
JP4
SVDD_SEL
AVDD SVDD
JP9
DVDD_SEL
JP10
LVC_SEL
REG DVDD AVDD VCC
JP11
VCC_SEL
DVDD VCC
LVC
Set up the power supply lines.
Name
Color
Voltage
Comments
REG
Red
Open
Regulator is not used.
AVDD
Orange
2.6~3.6V (typ3.3V)
Power supply for AVDD of AK4636EN.
VVDD
Blue
2.8~3.6V (typ3.3V)
Power supply for VVDD of AK4636EN.
DVDD
Orange
1.6~3.6V (typ3.3V)
Power supply for DVDD of AK4636EN.
SVDD
Blue
2.6~4.0V (typ3.3V)
Power supply for SVDD of AK4636EN.
VCC
Orange
2.7~3.6V (typ3.3V)
Power supply for logic block.
AVSS
Black
0V
For analog ground.
SVSS
Black
0V
For analog ground.
DGND
Black
0V
For logic ground.
Table 2 Set up of power supply lines
* Each supply line should be distributed from the power supply unit.
DVDD and VCC must be same voltage level.
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
3) Power on.
The AK4636EN and AK4114 should be reset once bringing SW1, 2 “L” upon power-up.
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„ Evaluation mode
In case of AK4636EN evaluation using AK4114, it is necessary to correspond to audio interface format for
AK4636EN and AK4114. About AK4636EN’s audio interface format, refer to datasheet of AK4636EN.
About AK4114’s audio interface format, refer to Table 3 in this manual.
Applicable Evaluation Mode
(1) Evaluation of loop-back mode (A/D → D/A) : PLL, Master Mode (Default)
(2) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode
(PLL Reference CLOCK: MCKI pin)
(3) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode
(PLL Reference CLOCK: BICK or FCK pin)
(4) Evaluation of loop-back mode (A/D → D/A) : EXT, Master Mode
(5) Evaluation of using DIR/DIT of AK4114 (opt-connector) : EXT, Slave Mode
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(1) Evaluation of loop-back mode (A/D → D/A) : PLL, Master Mode (Default)
a) Set up jumper pins of MCKI clock
Set “No.8 of SW3” to “H”. X’tal of 11.2896MHz, 12MHz, 13.5MHz, 24MHz or 27MHz can be set in X1. X’tal
of 12MHz (Default) is set on the AKD4636EN-A.
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz) through a RCA
connector (J8: EXT/BICK) is supplied, select EXT on JP21 (MCLK_SEL) and short JP17 (XTE). JP23 (EXT1)
and R26 should be properly selected in order to much the output impedance of the clock generator.
JP17
XTE
JP18
MKFS
JP21
MCLK_SEL
256fs 512fs 1024fs MCKO
XTL DIR
EXT
b) Set up jumper pins of BICK clock
Output frequency (16fs/32fs/64fs) of BICK should be set by “BCKO1-0 bit” in the AK4636EN.
There is no necessity for set up JP19.
JP20
BICK
JP19
BICK_SEL
16fs EXT
64fs 32fs INV
JP27
BICK
DIR ADC
THR
JP29
BICK_INV
INV
THR
c) Set up jumper pins of FCK clock
JP28
FCK
JP22
FCK_SEL
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4636EN is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the
JP30
JP26
4632_SDTI
DAC/LOOP ADC
SDTI
DIR
ADC
following.
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(2) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode (PLL Reference CLOCK: MCKI pin)
a) Set up jumper pins of MCKI clock
X’tal of 11.2896MHz, 12MHz, 13.5MHz, 24MHz or 27MHz can be set in X1. X’tal of 12 MHz (Default) is set
on the AKD4636EN-A. In this case, the AK4636EN corresponds to PLL reference clock of 12MHz. In this
evaluation mode, the output clock from MCKO-pin of the AK4636EN is supplied to a divider (U3:
74VHC4040), BICK and FCK clocks are generated by the divider. Then “MCKO bit” in the AK4636EN is set to
“1”. When an external clock through a RCA connector (J8: EXT/BICK) is supplied, select EXT on JP21
(MCLK_SEL) and short JP17 (XTE). JP23 (EXT1) and R26 should be properly selected in order to much the
output impedance of the clock generator.
JP17
XTE
JP18
MKFS
JP21
MCLK_SEL
256fs 512fs 1024fs MCKO
XTL DIR
EXT
b) Set up jumper pins of BICK clock
Input frequency of BICK should be set 64fs/32fs/16fs by JP19.
JP20
BICK
JP19
BICK_SEL
16fs EXT
64fs 32fs INV
THR
JP29
BICK_INV
JP27
BICK
DIR ADC
INV
THR
c) Set up jumper pins of FCK clock
JP22
FCK_SEL
JP28
FCK
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4636EN is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the
JP30
JP26
4632_SDTI
SDTI
DAC/LOOP ADC
DIR
ADC
following.
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(3) Evaluation of loop-back mode (A/D → D/A) : PLL, Slave Mode
(PLL Reference CLOCK: BICK or FCK pin)
a) Set up jumper pins of MCKI clock
An external clock through a RCA connector (J8: EXT/BICK), BICK and FCK clocks are generated by the
divider. JP23 (EXT1) and R26 should be properly selected in order to much the output impedance of the clock
generator.
JP17
XTE
JP18
MKFS
JP21
MCLK_SEL
256fs 512fs 1024fs MCKO
XTL DIR
EXT
*When BICK and FCK clocks through a RCA connector (J8, J9) is supplied, select XTL on JP21.
*When X’tal is used, X’tal of 256fs, 512fs or 1024fs can be set in X1. Set OPEN on JP17, and select XTL on
JP21.
b) Set up jumper pins of BICK clock
Input frequency of BICK should be set 64fs/32fs/16fs by JP19.
JP20
BICK
JP19
BICK_SEL
16fs EXT
64fs 32fs INV
JP27
BICK
DIR ADC
THR
JP29
BICK_INV
INV
THR
*When BICK and FCK clocks through a RCA connector (J8, J9) is supplied, select EXT on JP19. JP23 (EXT1)
and R26 should be properly selected in order to much the output impedance of the clock generator.
c) Set up jumper pins of FCK clock
JP22
FCK_SEL
JP28
FCK
DIR
ADC
2fs 1fs EXT
*When BICK and FCK clocks through a RCA connector (J8, J9) is supplied, select EXT on JP22. JP24 (EXT1)
and R27 should be properly selected in order to much the output impedance of the clock generator.
d) Set up jumper pins of DATA
When the AK4636EN is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the
following.
JP30
JP26
4632_SDTI
SDTI
DAC/LOOP ADC
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DIR
ADC
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(4) Evaluation of loop-back mode (A/D → D/A) : EXT, Master Mode
a) Set up jumper pins of MCKI clock
Set “No.8 of SW3” to “H”. An external clock (256fs, 512fs or 1024fs) through a RCA connector (J8:
EXT/BICK) is supplied. JP23 (EXT1) and R26 should be properly selected in order to much the output
impedance of the clock generator.
b) Set up jumper pins of BICK clock
Output frequency (32fs or 64fs) of BICK should be set by “BCKO1-0 bit” in the AK4636EN.
There is no necessity for set up JP19.
JP20
BICK
JP19
BICK_SEL
16fs EXT
64fs 32fs INV
JP27
BICK
DIR ADC
THR
JP29
BICK_INV
INV
THR
c) Set up jumper pins of FCK clock
JP28
FCK
JP22
FCK_SEL
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When the AK4636EN is evaluated by loop-back mode (A/D → D/A), the jumper pins should be set to the
JP30
JP26
4632_SDTI
DAC/LOOP ADC
SDTI
DIR
ADC
following.
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(5) Evaluation of using DIR/DIT of AK4114 (opt-connector) : EXT, Slave Mode
a) Set up jumper pins of MCKI clock
JP17
XTE
JP18
MKFS
JP21
MCLK_SEL
256fs 512fs 1024fs MCKO
XTL DIR
EXT
b) Set up jumper pins of BICK clock
JP20
BICK
JP19
BICK_SEL
64fs 32fs 16fs EXT
INV
JP29
BICK_INV
JP27
BICK
THR
DIR ADC
INV
THR
c) Set up jumper pins of FCK clock
JP22
FCK_SEL
JP28
FCK
DIR
ADC
2fs 1fs EXT
d) Set up jumper pins of DATA
When D/A converter of the AK4636EN is evaluated by using DIR of AK4114, the jumper pins should be set to
the following.
JP30
JP26
4632_SDTI
SDTI
DAC/LOOP ADC
ADC
DIR
When A/D converter of the AK4636EN is evaluated by using DIT of AK4114, the jumper pins should be set to
the following.
JP30
JP26
4632_SDTI
SDTI
DAC/LOOP ADC
DIR
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„ DIP Switch set up
[SW3] (MODE) : Mode Setting of AK4636EN and AK4114
ON is “H”, OFF is “L”.
No.
1
2
3
4
5
6
7
8
Defaul
t
DIF0
AK4114 Audio Format Setting
Off
DIF1
See Table 4
Off
DIF2
On
CM0
Clock Operation Mode select
Off
CM1
See Table 5
On
OCKS0
Master Clock Frequency Select
Off
OCKS1
See Table 6
Off
M/S
Slave mode
Master mode
On
Note. When the AK4636EN is evaluated Master mode, “M/S” is set to “H”.
Table 3. Mode Setting for AK4636EN and AK4114
Name
OFF (“L”)
Register setting
for AK4636EN
ON (“H”)
Setting for AK4114 Audio Interface Format
DIF1 bit
DIF0 bit
DIF0
DIF1
DIF2
DAUX
SDTO
0
1
L
L
L
24bit, Left justified
16bit, Right justified
1
0
L
L
H
24bit, Left justified
24bit, Left justified
Default
1
1
H
L
H
24bit, I2S
24bit, I2S
Note. When the AK4636EN is evaluated by using DIR/DIT of AK4114, “No.8 of SW3” is set to “L”.
Table 4. Setting for AK4114 Audio Interface Format
Mode
0
1
CM0
L
H
2
L
3
H
CM1
L
L
UNLOCK
PLL
X'tal
Clock source
ON
OFF
PLL
OFF
ON
X'tal
0
ON
ON
PLL
H
1
ON
ON
X'tal
H
ON
ON
X'tal
ON: Oscillation (Power-up), OFF: STOP (Power-down)
SDTO
RX
DAUX
RX
DAUX
DAUX
Default
Table 5. Clock Operation Mode select
No.
0
2
OCKS0
L
L
OCKS1
L
H
MCKO1
256fs
512fs
MCKO2
256fs
256fs
X’tal
256fs
512fs
Default
Table 6. Master Clock Frequency Select
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„ Other jumper pins set up
1. JP1 (GND)
OPEN
SHORT
: Analog ground and Digital ground
: Separated.
: Common. (The connector “DGND” can be open.) <Default>
2. JP3 (AVDD_SEL) : AVDD of the AK4636EN
REG
: AVDD is supplied from the regulator (“AVDD” jack should be open). < Default >
AVDD
: AVDD is supplied from “AVDD ” jack.
3. JP4 (SVDD_SEL) : SVDD of the AK4636EN
REG
: SVDD is supplied from the regulator (“SVDD” jack should be open). < Default >
SVDD
: SVDD is supplied from “SVDD ” jack.
4. JP8 (VVDD_SEL) : VVDD of the AK4636EN
AVDD
: VVDD is supplied from “AVDD”. < Default >
VVDD
: VVDD is supplied from “VVDD ” jack.
5. JP9 (DVDD_SEL) : DVDD of the AK4636EN
AVDD
: DVDD is supplied from “AVDD”. < Default >
DVDD
: DVDD is supplied from “DVDD ” jack.
6. JP10 (LVC_SEL) : Logic block of LVC is selected supply line.
DVDD
: Logic block of LVC is supplied from “DVDD”. < Default >
VCC
: Logic block of LVC is supplied from “VCC ” jack.
7. JP11 (VCC_SEL) : Logic block is selected supply line.
LVC
: Logic is supplied from supply line of LVC. < Default >
VCC
: Logic block of LVC is supplied from “VCC ” jack.
8. JP25 (MCKO_SEL) : Master Clock Frequency is selected clock from MCKO1 or MCKO2 of the AK4114.
MCKO1
: The check from MCKO1 of AK4114 is provided to MCKI of the AK4636EN. < Default >
MCKO2
: The check from MCKO2 of AK4114 is provided to MCKI of the AK4636EN.
9. JP102 (I2C)
OPEN
SHORT
: Control Interface is selected mode.
: 3-wire Serial Control Mode. < Default >
: I2C-bus Control Mode. (Not used in this board.)
10. JP103 (MCKO)
OPEN
SHORT
: Master Clock Frequency is selected from AK4636EN.
: Not supply.
: Supplied from AK4636EN. < Default >
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„ The function of the toggle SW
[SW1] (DIR)
: Power control of AK4114. Keep “H” during normal operation.
Keep “L” when AK4114 is not used.
[SW2] (PDN)
: Power control of AK4636EN. Keep “H” during normal operation.
„ Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114.
„ Serial Control
The AK4636EN can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT4
(CTRL) with PC by 10 wire flat cable packed with the AKD4636EN-A
Connect
PC
10 wire
flat cable
10pin
Connector
CSN
CCLK
CDTI
AKD4636
10pin Header
Figure 3. Connect of 10 wire flat cable
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„ Analog Input/Output Circuits
(1) Input Circuits
a) MIC/MICP/DMDAT Input Circuit
J1
MIC-JAC
6
4
3
AVSS
DMP
MPI
JACK
JP12
MIC_SEL
J3
MIC
DMP
R112
2.2k
DMDAT
JP103
MPI-SEL
MPI
DMDAT
MIC
JP105
MIC-SEL
MIC/MICP/DMDAT
C108 1u
RCA
2
3
1
MR-552LS
AVSS
Figure 4. MIC/MICP Input Circuit
(a-1) Analog signal is input to MIC pin via J1 connector.
JP12
MIC_SEL
RCA JACK
JP103
MPI-SEL
DMP MPI
JP105
MIC-SEL
DMDAT MIC
(a-2) Analog signal is input to MIC/MICP pin via J3 connector.
JP12
MIC_SEL
RCA JACK
JP103
MPI-SEL
DMP MPI
JP105
MIC-SEL
DMDAT MIC
(a-3) Digital Microphone Data signal is input to DMDAT pin.
JP12
MIC_SEL
RCA JACK
JP103
MPI-SEL
DMP MPI
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JP105
MIC-SEL
DMDAT MIC
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b) LIN/MICN Input Circuit
J4
JP104
LIN/MICN
BEEP/LIN/MICN
MR-552LS
DMCLK
DMCLK
JP16
MIN
BEEP
2
3
1
C112 1u
R113
R18
47k
LIN/MICN
LIN-SEL
BEEP/MIN/MOUT
C113 1u
2+
1
R114
2.2k
33k
BEEP
JP108 BEEP-RI
JP102
MICN
AVSS
Figure 5. LIN/MICN Input Circuit
(b-1) LIN is input from J4.
JP102
MICN
JP16
BEEP/MIN
JP104
LIN-SEL
LIN/MICN DMCLK
MIN BEEP
(b-2) MICN is input from J4.
JP102
MICN
JP16
BEEP/MIN
JP104
LIN-SEL
LIN/MICN DMCLK
MIN BEEP
(b-3) BEEP is input from J4.
(b-3-1) In case of using external resistor (R114).
JP16
BEEP/MIN
JP108
BEEP-RI
MIN BEEP
(b-3-1) In case of using internal resistor of the AK4636EN.
JP16
BEEP/MIN
JP108
BEEP-RI
MIN BEEP
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c) VIN Input Circuit
J6
VIN
C29
2
3
1
VIN
0.1u
R23
75
MR-552LS
AVSS
AVSS
Figure 6. VIN Input Circuit
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(2) Output Circuits
a) AOUT Output Circuit
AOUT
+
C28
1
R20
220
2
1u
2
3
1
R21
20k
J5 AOUT
MR-552LS
AVSS
AVSS
Figure 7. AOUT Output Circuit
b) VOUT Output Circuit
R22
J7
2
3
1
75
VOUT
VOUT
R41
100k
MR-552LS
AVSS
AVSS
Figure 8. VOUT Output Circuit
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C) SPK Output Circuit
Note. When mini-jack is inserted or pulled out J2 (SPK-JACK) connector, JP13 (SPP_SEL) and JP14
(SPN_SEL) should be open, or “PMSPK bit” in the AK4636EN should be set to “0”.
JP31
Dynamic
R15
10
3
4
SVSS
SPP
J2
SPK-JACK
6
JP13
D1
A
SVSS
K
JP14
D2
SVSS
SPK1
SPP_SEL
DIODE ZENER
A
Dynamic(EXT)
Piezo(EXT)
Dynamic
K
CN5
Dynamic(EXT)
Piezo(EXT)
Dynamic
2
SPN_SEL
DIODE ZENER
020S16
R
1
L
R17
10
SPN
Figure 9. SPK Output Circuit
(C-1) “Dynamic Speaker” of external is evaluated by using J2 (SPK-JACK) connector.
JP13
SPP_SEL
Dynamic
Dynamic(EXT)
Piezo(EXT)
JP14
SPN_SEL
JP31
Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
(C-2) “Piezo (Ceramic) Speaker” of external is evaluated by using J2 (SPK-JACK) connector.
JP13
SPP_SEL
Dynamic
Dynamic(EXT)
Piezo(EXT)
JP14
SPN_SEL
JP31
Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
(C-3) Analog signal of SPP/SPN pins are output “Dynamic Speaker” on the evaluation (SPK1).
JP13
SPP_SEL
Dynamic
Dynamic(EXT)
Piezo(EXT)
JP14
SPN_SEL
JP31
Dynamic
Dynamic
Dynamic(EXT)
Piezo(EXT)
∗ AKEMD assumes no responsibility for the trouble when using the above circuit examples.
[KM095400]
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[AKD4636EN-A]
Control Software Manual
„ Set-up of evaluation board and control software
1. Set up the AKD4636EN-A according to previous term.
2. Connect IBM-AT compatible PC with AKD4636EN-A by 10-line type flat cable (packed with AKD4636EN-A).
Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is
used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control
software”. In case of Windows95/98/ME, this installation is not needed. This control software does not operate on
Windows NT.)
3. Insert the CD-ROM labeled “AKD4636EN Evaluation Kit” into the CD-ROM drive.
4. Access the CD-ROM drive and double-click the icon of “AKD4636EN.exe” to set up the control program.
5. Then please evaluate according to the follows.
„ Operation flow
Keep the following flow.
1. Set up the control program according to explanation above.
2. Click “Port Reset” button.
3. Click “Write default” button
„ Explanation of each buttons
1. [Port Reset] :
2. [Write default] :
3. [All Write] :
4. [Function1] :
5. [Function2] :
6. [Function3] :
7. [Function4] :
8. [Function5] :
9. [SAVE] :
10. [OPEN] :
11. [Write] :
12. [Filter] :
Set up the USB interface board (AKDUSBIF-A) when using the board.
Initialize the register of the AK4636EN.
Write all registers that is currently displayed.
Dialog to write data by keyboard operation.
Dialog to write data by keyboard operation.
The sequence of register setting can be set and executed.
The sequence that is created on [Function3] can be assigned to buttons and executed.
The register setting that is created by [SAVE] function on main window can be assigned to
buttons and executed.
Save the current register setting.
Write the saved values to all register.
Dialog to write data by mouse operation.
Set Programmable Filter (HPF, LPF, EQ1~5) of AK4636EN easily.
„ Indication of data
Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the
part that is not defined in the datasheet.
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[AKD4636EN-A]
„ Explanation of each dialog
1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register.
Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data
becomes “H” or “1”. If not, “L” or “0”.
If you want to write the input data to the AK4636EN, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box:
Data Box:
Input registers address in 2 figures of hexadecimal.
Input registers data in 2 figures of hexadecimal.
If you want to write the input data to the AK4636EN, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate IVOL, OVOL.
There are dialogs corresponding to register of 09h and 0Ah.
Address Box:
Input registers address in 2 figures of hexadecimal.
Start Data Box:
Input starts data in 2 figures of hexadecimal.
End Data Box:
Input end data in 2 figures of hexadecimal.
Interval Box:
Data is written to the AK4636EN by this interval.
Step Box:
Data changes by this step.
Mode Select Box:
If you check this check box, data reaches end data, and returns to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00
If you do not check this check box, data reaches end data, but does not return to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09
If you want to write the input data to the AK4636EN, click [OK] button. If not, click [Cancel] button.
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[AKD4636EN-A]
4. [SAVE] and [OPEN]
4-1. [SAVE]
All of current register setting values displayed on the main window are saved to the file. The extension of file name is
“akr”.
<Operation flow>
(1) Click [SAVE] Button.
(2) Set the file name and click [SAVE] Button. The extension of file name is “akr”.
4-2. [OPEN]
The register setting values saved by [SAVE] are written to the AK4636EN. The file type is the same as [SAVE].
<Operation flow>
(1) Click [OPEN] Button.
(2) Select the file (*.akr) and Click [OPEN] Button.
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[AKD4636EN-A]
5. [Function3 Dialog]
The sequence of register setting can be set and executed.
(1) Click [F3] Button.
(2) Set the control sequence.
Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused.
(3) Click [START] button. Then this sequence is executed.
The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused
step.
This sequence can be saved and opened by [Save] and [OPEN] button on the Figure 10 window. The extension of file
name is “aks”.
Figure 10. [F3] Window
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[AKD4636EN-A]
6. [Function4 Dialog]
The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed.
When [F4] button is clicked, the window as shown in Figure 11 opens.
Figure 11. [F4] window
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[AKD4636EN-A]
6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3].
The sequence file name is displayed as shown in Figure 12.
Figure 12. [F4] window (2)
(2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name
is “*.ak4”.
[OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded.
6-3. Note
(1) This function doesn't support the pause function of sequence function.
(2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the
change.
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[AKD4636EN-A]
7. [Function5 Dialog]
The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to
buttons and then executed. When [F5] button is clicked, the window as shown in Figure 13 opens.
Figure 13. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
The register setting file name is displayed as shown in Figure 14.
(2) Click [WRITE] button, then the register setting is executed.
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[AKD4636EN-A]
Figure 14. [F5] window (2)
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file
name is “*.ak5”.
[OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded.
7-3. Note
(1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be
loaded again in order to reflect the change.
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[AKD4636EN-A]
8. [Filter Dialog]
A calculation of a coefficient of Digital Programmable Filter such as HPF,EQ filter ,a write to a register and check
frequency response such as HPF,EQ filter.
Window to show to Figure 15 opens when push a [Filter] button .
Figure 15. [Filter] Window
8-1. Setting of a parameter
(1) Please set a parameter of each Filter.
Item
Contents
Setting range
Sampling Rate
Sampling frequency (fs)
7350Hz ≤ fs ≤ 48000Hz
HPF
Cut Off Frequency
High pass filter cut off frequency
fc/fs ≥ 0.0001 (fc min = 1.6Hz at 16kHz)
LPF
Cut Off Frequency
Low pass filter cut off frequency
fc/fs ≥ 0.05 (fc min = 2205Hz at 44.1kHz)
5 Band Equalizer
EQ1-5 Center Frequency
EQ1-5 Center Frequency
fon / fs < 0.497
EQ1-5 Band Width
EQ1-5 Band Width
(Note 1)
EQ1-5 Gain
EQ1-5 Gain
(Note 2)
-1≤ Kn < 3
Note 1. A gain difference is a bandwidth of 3dB from center frequency.
Note 2. When a gain is smaller than 0 , EQ becomes a notch filter.
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[AKD4636EN-A]
(2) “LPF”, “HPF”, “HPFAD”, “EQ1”, “EQ2”, “EQ3”, “EQ4”, “EQ5” Please set ON/OFF of Filter with a check button.
When checked it, Filter becomes ON. When checked “Notch Filter Auto Correction”, perform automatic revision of
center frequency of a notch filter. (“Cf. 8-4. automatic revision of center frequency of a notch filter”)
Figure 16. Filter ON/OFF setting button
8-2. A calculation of a register
A register set value is displayed when push a [Register Setting] button. When a value out of a setting range is set, error
message is displayed, and, a calculation of register setting is not carried out.
Figure 17. A register setting calculation result
When it is as follows that a register set value is updated.
(1) When [Register Setting] button was pushed.
(2) When [Frequency Response] button was pushed.
(3) When [UpDate] button was pushed on a frequency characteristic indication window.
(4) When set ON/OFF of a check button “Notch Filter Auto Correction”
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[AKD4636EN-A]
8-3.Indication of a frequency characteristic
A frequency characteristic is displayed when push a [Frequency Response] button. In addition, a register set point is
updated then, too.
Change "Frequency Range", and indication of a frequency characteristic is updated when push a [UpDate] button.
Figure 18. A frequency characteristic indication result
When it is as follows that a register set point is updated.
(1) When [Register Setting] button was pushed.
(2) When [Frequency Response] button was pushed.
(3) When [UpDate] button was pushed on a frequency characteristic indication window.
(4) When set ON/OFF of a check button “Notch Filter Auto Correction”
8-4. Automatic revision of center frequency of a notch filter
When set a gain of 5 band Equalizer to -1, Equalizer becomes a notch filter. When center frequency of plural notch filters
is adjacent, produce a gap to central frequency (Figure 19). When check "a Notch Filter Auto Correction" button, perform
automatic revision of central frequency of a notch filter, display register setting after automatic revision and a frequency
characteristic (Figure 20). This automatic revision is availability for Equalizer Band which set a gain to "-1".
(Note) When distance among center frequency is smaller than band width, there is a possibility that automatic revision is
not performed definitely. Please confirm a revision result by indication of a frequency characteristic.
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[AKD4636EN-A]
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Band Width : 200Hz(3 band common)
Figure 19. When there is no revision of center frequency
Setting of center frequency: 4400Hz, 5000Hz, 5400Hz / Band Width : 200Hz(3 band common)
Figure 20. When there is revision of center frequency
[KM095400]
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[AKD4636EN-A]
Measurement Result
1.AK4636EN Mode: PLL SLAVE mode
[Measurement condition]
• Measurement unit: PW18-1.8AQ, UPD05
• Bit: 16bit
• Sampling Frequency: 8kHz & 44.1kHz
• Measurement Frequency: 20 ∼ 3.4kHz (fs=8kHz), 20 ∼ 20kHz (fs=44.1kHz)
• Power Supply: AVDD=DVDD=SVDD=VVDD=3.3V
• Temperature: Room
• Input Frequency: 1kHz
• MIC Gain: +20dB
[Measurement Results]
1-1. PLL Reference clock : BICK or FCK pin
Loop-back (MIC (+20dB) → ADC Æ DAC Æ AOUT)
Result
PLL Reference clock
Sampling Frequency
S/(N+D) (-1dBFS)
D-Range (-60dBFS)
S/N
1fs (FCK pin)
8kHz
44.1kHz
79.1dB
79.1dB
85.3dB
83.9dB
85.3dB
83.9dB
64fs (BICK pin)
8kHz
44.1kHz
83.5dB
79.6dB
85.3dB
83.9dB
85.3dB
83.9dB
1-2. PLL Reference clock : MCKI pin
Loop-back (MIC (+20dB)→ ADC Æ DAC Æ AOUT)
Result
PLL Reference clock
12MHz
Sampling Frequency
8kHz
44.1kHz
S/(N+D) (-1dBFS)
83.5dB
79.4dB
D-Range (-60dBFS)
85.3dB
83.9dB
S/N
85.3dB
83.9dB
2.AK4636EN Mode: PLL MASTER mode
[Measurement condition]
• Measurement unit: PW18-1.8AQ, UPD05
• MCKI: 12MHz
• BICK: 64fs
• Bit: 16bit
• Sampling Frequency: 8kHz & 44.1kHz
• Measurement Frequency: 20 ∼ 3.4kHz (fs=8kHz), 20 ∼ 20kHz (fs=44.1kHz)
• Power Supply: AVDD=DVDD=SVDD=VVDD=3.3V
• Temperature: Room
• Input Frequency: 1kHz
[Measurement Results]
Loop-back (MIC (+20dB) → ADC Æ DAC Æ AOUT)
Result
8kHz
44.1kHz
S/(N+D) (-1dBFS)
83.5dB
79.4dB
D-Range (-60dBFS)
85.3dB
83.9dB
S/N
85.3dB
83.9dB
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[AKD4636EN-A]
3.PLOT DATA (PLL Slave mode)
3-1.ADC (MIC Æ ADC) PLOT DATA
Figure 1. THD+N vs. Input Level
Figure 2. THD+N vs. Input Frequency (Input Level = -1dBFS)
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[AKD4636EN-A]
Figure 3. Linearity
Figure 4. Frequency Response (AIN Æ ADC)
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[AKD4636EN-A]
Figure 5. FFT Plot ( Input level=-1.0dBFS)
Figure 6. FFT Plot ( Input level=-60.0dBFS )
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[AKD4636EN-A]
Figure 7. FFT Plot ( “0” data input )
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[AKD4636EN-A]
3-2. DAC (DAC Æ AOUT) PLOT DATA
Figure 8. THD+N vs. Input Level
Figure 9. THD+N vs. Input Frequency (Input Level = 0dBFS)
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[AKD4636EN-A]
Figure 10. Linearity
Figure 11. Frequency Response
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[AKD4636EN-A]
Figure 12. FFT Plot ( Input level=0dBFS )
Figure 13. FFT Plot ( Input level=-60.0dBFS )
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[AKD4636EN-A]
Figure 14. FFT Plot ( “0” data input )
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[AKD4636EN-A]
3-3. VIDEO PLOT DATA
[Measurement condition]
• Measurement unit: Tektronix VM700T Video Measurement set
• Power Supply: AVDD=DVDD=SVDD=3.3V,VVDD=3.3V
• Temperature: Room
• Input Frequency: 1kHz
3-3-1. S/N
• Measurement Frequency: 100kH ∼ 6MHz
Figure 1. Noise Spectrum
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[AKD4636EN-A]
4-3-2. DC
Figure 2. Field Time Distortion
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[AKD4636EN-A]
3-3-3. Vector
• Input signal: 75% color
Figure 3. 75% Color Vector
[KM095400]
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[AKD4636EN-A]
Revision History
Date
(yy/mm/dd)
08/06/02
Manual
Board
Revision Revision
KM095400
0
Reason
Page
Contents
First edition
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
[KM095400]
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A
B
REG_IN T1
E
GND
REG
47u
AVSS
SVSS
MOUT
0.1u
BEEP
0.1u
C3
+
INT
C2
AOUT
1
OUT
C1
2
E
DGND
T45_BK
T45_BK
1
24
AOUT
CN3
REG
AVSS
SVDD
22
C14
(NMT)
C15
(NMT)
R3
4
VVDD
SAGC11
8
JP7
(NMT)
2
C18
7
1
(NMT)
JP4
SVDD_SEL
SPN
20
MCKO
19
SVDD
REG
L2
1
SVDD
R5
R4
(NMT)
(NMT)
21
SPP
20
SPN
2
(short)
C16
+
C
47u
4632_MCKO
18
4632_MCKI
SVSS
MCKI
18
DVSS
17
JP6
(NMT)
AVSS
PDN
13
12
SDTI
CDTI
11
10
CSN
9
SDTO
R6 (NMT)
AVSS
19
17
8
VVDD
VSAG
CCLK
1
1
(NMT)
32pin_1
(Short)
VOUT
(NMT)
SAGC00
2
47u
+
2
2
C17
+
PDN
L3
1
C19
SAGC11
7
JP8
6
SVSS
22
SAGC00
AVDD VVDD_SEL
VVDD
VIN
23
21
DVDD
6
5
C20
(NMT)
16
VOUT
JP5
(NMT)
BICK
5
SVSS
+
AVDD
VIN
15
AVSS
FCK
C
SPP
(NMT)
4
C12
(NMT)
1
C11
(NMT)
2
3
MIN
24
1
AVSS
AVSS
SVSS
2
3
AVDD
23
14
AVDD
2
2
+
2
AVDD
C10
(NMT)
1
1
+
(short)
2
47u
C9
(NMT)
2
2
+
C13
1
1
L1
1
SVSS
MOUT
MIN
AVSS
JP3
AVDD_SEL
SVDD
25
26
27
BEEP
28
29
AIN
1
MIC
VCOC
+
REG
VCC_IN
D
CN2
AVDD_IN
AVSS
C7
(NMT)
30
31
MPI
VCOM
32
U1
R2 (NMT)
C8
(NMT)
C6
MICOUT
1
R1
(NMT) (NMT)
AVSS
REG
VVDD
2
2
+
D
REG_IN AVDD_IN DVDD_IN
JP2
(NMT)
+
C4
(NMT)
C5
(NMT)
1
SVSS
T45_BU
1
SVDD
T45_O
1
VCC
T45_BK
1
AVSS
T45_BU
1
VVDD
T45_O
1
DVDD
T45_O
1
AVDD
T45_R
1
REG
1
25
26
27
28
29
32
CN1
32pin_4
30
AVSS
AVSS
31
E
D
JP1
GND
TA48033F
IN
C
32pin_3
NO MOUNT
B
AVDD
R7
(NMT)
R8
(NMT)
R9
(NMT)
R10
(NMT)
R11
(NMT)
R12
(NMT)
R13
(NMT)
R14
13
14
15
4632_SDTO
4632_FCK
4632_BICK
16
12
4632_SDTI
11
CDTI
CN4
LVC
10
DVDD
CCLK
DVDD
JP10
LVC_SEL
9
(short)
R40
(short)
CSN
1
+
DVDD
2
2
47u
AVSS
10
L4
1
C22
2
C21
(NMT)
JP9
AVDD DVDD_SEL
DVDD_IN
1
+
B
32pin_2
VCC
VCC_IN
LVC
L5
1
47u
+
D3.3V
2
(short)
VCC
A
Title
2
C23
1
A
JP11
VCC_SEL
DVDD
AVSS
- 43 -
Size
A3
Date:
A
B
C
D
AKD4636-A
Document Number
Rev
AK4636
Thursday, November 08, 2007
Sheet
E
0
1
of
5
A
B
C
D
E
J1
MIC-JACK
6
JP31
Dynamic
4
3
J2
E
AVSS
JACK
JP12
MIC_SEL
R15
10
INT
J3
MIC
SPK-JACK
SVSS
SPP
RCA
6
2
3
1
JP13
D1
A
Dynamic(EXT)
Piezo(EXT)
Dynamic
K
MR-552LS
AVSS
JP15
MIN/MOUT
BEEP/MIN/MOUT
2
3
1
2
R16
(NMT)
OUT
IN
C24
(NMT)
1
CN5
A
SVSS
R
Dynamic(EXT)
Piezo(EXT)
Dynamic
K
C25
(NMT)
020S16
JP14
D2
MOUT
SPK1
SPP_SEL
DIODE ZENER
SVSS
+
J4
2
SPN_SEL
DIODE ZENER
1
AVSS
L
MR-552LS
R17
AVSS
D
E
3
4
10
C26
(short)
2
1
+
MOUT
MIN
BEEP
MIN
R19
BEEP/MIN/MOUT
R18
47k
D
SPN
JP16
BEEP
(short)
AVSS
+
C28
1
AOUT
R20
J5
220
AOUT
2
2
3
1
1u
R21
20k
MR-552LS
AVSS
AVSS
C
C
J7
J6
R22
C29
VIN
2
3
1
75
VIN
VOUT
2
3
1
VOUT
0.1u
R23
75
MR-552LS
R41
100k
MR-552LS
AVSS
AVSS
AVSS
AVSS
B
B
A
A
Title
- 44 -
Size
A3
Date:
A
B
C
D
AKD4636-A
Document Number
Rev
Input/Output
Thursday, November 08, 2007
Sheet
E
A
2
of
5
A
B
C
D
E
for
74HCU04,74AC74,74VHC4040,74HC14,74HC14,74HC541,74HCT04
C30
C31
C32
C33
C34
C35
C36
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
0.1u
E
+ C37
2
X1
12MHz
1
2
E
1
D3.3V
47u
R24
1M
U2C
5
U2B
6
3
74HCU04
C38
5p
JP17
XTE
4
74HCU04
C39
5p
D
D
EXT_MCLK
Q
10
6
12
D
11
CLK
U4B
74AC74
PR
Q
5
1
MCLK_SEL
C
CLK
CL
XTL
DIR
EXT
DIR_MCLK
D
3
U4A
74AC74
Q
CL
R25
short
D3.3V
Q
9
JP18
MKFS
JP19
BICK_SEL
U3
256fs
512fs
1024fs
MCKO
10
11
8
13
JP21
2
PR
4
D3.3V
CLK
RST
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
9
7
6
5
3
2
4
13
12
14
15
1
74VHC4040
64fs
32fs
16fs
EXT
THR
1
JP20
BICK
EXT_BICK
2
U5A
74HC14
INV
C
JP22
2fs
1fs
EXT
EXT_FCK
FCK_SEL
MCKO
J8
EXT/BICK
2
3
1
B
B
R26
51
MR-552LS
AVSS
JP23
EXT1
J9
FCK
2
3
1
R27
51
MR-552LS
AVSS
A
JP24
EXT2
A
Title
- 45 -
Size
A3
Date:
A
B
C
D
AKD4636-A
Document Number
Rev
CLOCK
Thursday, November 08, 2007
Sheet
E
0
3
of
5
A
B
C40
C
D
E
C41
0.1u 0.1u
D3.3V
1
D3.3V
(short)
R28
10k
C42
U5B
0.1u
C43
10u
R29
470
2
4
1
3
74HC14
D3.3V
6
E
5
74HC14
L
+
TORX141
H
C44
SW1
0.1u
DIR
2
C45
0.1u
1
3
2
1
VCC
GND
OUT
D3
HSU119
U5C
3
PORT1
A
2
E
K
L6
1
38
37
INT1
R
AVDD
40
39
R30
18k
VCOM
AVSS
41
42
RX0
43
NC
44
RX1
46
45
TEST1
NC
RX2
16
15
14
13
12
11
10
9
47
U6
SW3
1
2
3
4
5
6
7
8
RX3
DIF0
DIF1
DIF2
CM0
CM1
OCKS0
OCKS1
M/S
D
48
C46
0.47u
D
R31
1k
U7D
IPS0
INT0
36
9
LED1
ERF
8
K
A
D3.3V
74HC04
2
NC
OCKS0
35
OCKS0
3
DIF0
OCKS1
34
OCKS1
4
TEST2
CM1
33
CM1
5
DIF1
CM0
32
CM0
6
NC
PDN
31
RP1
9
8
7
6
5
4
3
2
1
CM0
CM1
OCKS0
OCKS1
M/S
47k
AK4114
7
DIF2
C
C47
5p
XTI
30
1
C
X2
11.2896MHz
C48
5p
IPS1
XTO
29
9
P/SN
DAUX
28
10
XTL0
MCKO2
27
11
XTL1
BICK
26
DIR_BICK
12
VIN
SDTO
25
DIR_SDTI
2
8
DAUX
C49
0.1u
C50
0.1u
LRCK
24
MCKO1
23
22
DVSS
DVDD
21
20
VOUT
UOUT
19
COUT
18
BOUT
17
TX1
16
15
DVSS
14
13
TX0
B
TVDD
B
JP25
MCKO_SEL
DIR_FCK
2
1
C51
10u
+
1
+
MCKO2
MCKO1
DIR_MCLK
2
C52
10u
D3.3V
D3.3V
PORT2
A
IN
VCC
GND
3
2
1
A
D3.3V
C53
TOTX141
0.1u
Title
- 46 -
Size
A3
Date:
A
B
C
D
AKD4636-A
Document Number
Rev
DIR/DIT
Wednesday, October 31, 2007
Sheet
E
A
4
of
5
A
B
C
D
E
U8
LVC
U9
1
E
MCKO
11
Y8
A8
9
M/S
12
Y7
A7
8
4632_MCKO
DIR
20
VCC
E
C54
0.1u
GND
10
A1
B1
18
3
A2
B2
17
4
A3
B3
16
5
A4
B4
15
6
A5
B5
14
7
A6
B6
13
8
A7
B7
12
B8
11
19
G
2
RP2
4632_MCKI
DAUX
13
A6
7
Y6
EXT_MCLK
14
Y5
A5
6
4632_SDTO
15
Y4
A4
5
16
Y3
A3
4
17
Y2
A2
3
18
Y1
A1
2
G2
19
JP26
47k
4632_SDTI DAC/LOOP
4632_SDTI
RP3
7
6
5
4
3
2
1
ADC
7
6
5
4
3
2
1
47k
D
D
10
GND
BICK
4632_BICK
VCC
ADC
DIR
C55
0.1u
20
JP27
4632_FCK
1
G1
9
A8
EXT_BICK
DIR_BICK
JP28
FCK
ADC
74LVC245
74HC541
DIR
EXT_FCK
DIR_FCK
C
C
1
LVC
13
47u
2
JP29
U10F
+ C56
INV
12
THR
74HC14
BICK_INV
U11
R32
R34
R36
D3.3V
1
2
3
4
5
B
PORT4
10
9
8
7
6
10k
10k
10k
R33
R35
R37
470
470
470
CSN
CCLK
CDTI
2
3
4
5
6
7
8
9
A1
A2
A3
A4
A5
A6
A7
A8
1
19
G1
G2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
18
17
16
15
14
13
12
11
CSN
CCLK
CDTI
PDN
4632_MCKI
MCLK
BICK
FCK
SDTI
VCC
1
2
3
4
5
PORT3
10
9
8
7
6
ROM
B
R38
74HC541
CTRL
D3.3V
10k
ADC
D3.3V
DAUX
K
JP30
SDTI
R39
A
D4
HSU119
10k
U5D
9
11
10
U2A
74HC14
74HC14
1
U7A
U2F
2
13
12
1
H
74HCU04
1
3
L
C57
PDN
0.1u
9
8
3
4
11
10
74HCU04
5
10
5
13
12
74HC04
- 47 -
U10C
6
11
74HC14
U7F
6
74HC04
U10B
4
74HC14
74HC04
U7C
U2E
11
3
U7E
74HC04
74HCU04
2
74HC04
74HCU04
U7B
U2D
2
A
SW2
9
U10D
8
74HC14
U10E
10
A
74HC14
1
U10A
2
Title
74HC14
Size
A3
Date:
A
DIR_SDTI
DIR
U5E
8
B
C
D
AKD4636-A
Document Number
Rev
LOGIC
Wednesday, October 31, 2007
A
Sheet
E
5
of
5
A
B
C
D
E
TP102
VIN
TP101
AVSS
1
TP100
1
2
3
4
5
6
8
8P
7
CN102
AVDD
1
1AVDD
DMP
E
TP103
VOUT
1
R100
51
E
CN106
C111
4700p
1
1
1pin
C109
0.1u
1
+
2
+
C103
0.1u
C100
0.1u
1
R111
10k
C101
10u
2
C102
10u
1
2
CN105
C110
TP125
2.2u
1
1
TP130
DMP
1
1
PDN
TP104
+
R101
100k
TP126
VVDD
JP107
DMVDD-SEL
VCOC
2
1
JP100
2pin
TP124
VCOM
TP128
DMDAT
I2C
CN107
1
TP129
DMCLK
1
1
1
1
30
1
2
3
VCOC
AVDD
VSS1
4
5
6
VVDD
VCOM
33k
28
BEEP
C113
1u
1
2
TP127
BEEP
+
BICK
VSS3
27
TP121
AOUT
NC
16
SDTO
NC
25
26
2
8P
24
1
C105
10u
TP115
MCKO
CN101
C106
0.1u
+
1
B
+
C104
0.1u
25
C112
1u
SPN
SVDD
23
SPP
22
NC
VSS2
21
17
8P
20
CN104
18
PDN
MCKO
1
16
2
B
C107
10u
JP101
R113
1
2.2k
MCKO
R110
(open)
TP117
SPP
R109
1 51
1
1
1
A
TP120
LIN
22
TP118
SVDD
20
19
18
TP116
SPN
17
TP119
SVSS
1
A
CN103
1
24
1
21
TP113
AVSS
JP102
MICN
23
TP114
MCKI
Title
8P
Size
A3
Date:
A
C
27
1
SDTI
26
1
TP112
DVDD
15
28
JP108 BEEP-RI
TP111
BICK
15
31
TP122
MIC
LIN/MICN
1
14
14
1
DMCLK
29
R114
MCKI
2.2k
C108 1u
29
AOUT
AK4636
DVDD
1
1
13
13
R108 51
FCK
R112
R115 51
30
LIN
1
12
R107 51
CCLK
TP109
SDTO
TP110
FCK
MIC
LIN-SEL
12
C
31
MIC
32
MPI
DMDAT
JP104
11
R106 51
CDTIO
MIC-SEL
11
R105 51
7
1
10
JP105
TP107
CDTI
TP108
SDTI
DMP
JP103
32
MPI
MPI-SEL
10
R104 51
CSN
19
R103 51
TP106
CCLK
D
TP123
AVSS
1
9
9
VOUT
TP105
CSN
R102 51
VIN
I2C
U100
8
1pin
D
B
C
D
AKD4636-A
Document Number
Rev
AK4636_SUB_32QFN
Tuesday, November 27, 2007
Sheet
E
1
of
0
1
AKD4636-A L1
- 57 -
AKD4636-A L2
- 58 -
AKD4636-A L1_SILK
- 59 -
AKD4636-A L2_SILK
- 60 -
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