EK-RX01-MM-002_maint_Dec76
RXS/RX11
flo,ppy disk system
maintenance manual
EK-RXOI-MM-002
digital equipmen:t corporation · maynard. massachusetts
1st Edition, May 1975
2nd Printing (Rev), September 1975
3rd Printing, July 1976
4th Printing (Rev), December 1976
Copyright © 1975, 1976 by Digital Equipment Corporation
The material in this manual is for informational
purposes and is subject to change without notice.
Digital Equipment Corporation assumes no respon·
sibility for any errors which may appear in this
manual.
Printed in U.S.A.
The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
DECCOMM
DECsystem·l0
DECSYSTEM·20
DECtape
DECUS
DIGITAL
MASSBUS
PDP
RSTS
TYPESET-8
TYPESET·l1
UNIBUS
CONTENTS
Page
CHAPTER 1
GENERAL INFORMATION
1.1
1.2
1.2.1
1.2.2
1.2.3
1.2.4
1.2.5
1.3
1.3.1
1.3.2
1.3.3
1.3.3.1
1.3.3.2
1.3.3.3
1.3.3.4
1.4
1.5
1.6
INTRODUCTION . . . . .
PHYSICAL DESCRIPTION
RX8E/RXl1 Interfaces
Microprogrammed Controller
Read/Write Electronics . . .
Electro-Mechanical Drive ..
Power Supply . . . . . . . . . .
SYSTEMS COMPATIBILITY . . . . .
Media
Recording Scheme . . . . . . . . . .
Logical Format . . . . . . . . .
Header Description . . . . . . .
Data Field Description . . . . .
Track Usage . . . . . . . . . . . . . . . .
CRC Capability
....... .
APPLICABLE INSTRUCTION MANUALS . . . . . .
CONFIGURATION
SPECIFICATIONS . . . . . . . ; ..
CHAPTER 2
INSTALLATION AND OPERATION
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.4
2.4.1
2.4.2
2.4.3
2.4.3.1
2.4.3.2
2.4.4
2.5
2.5.1
2.5.2
2.5.3
2.5.3.1
2.5.3.2
2.5.4
PURPOSE AND ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . .
SITE PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Space . . . . . . . . . . . . . . .
Cabling . . . . . . . . . . . . . .
AC Power
........... .
Fire and Safety Precautions
. . . ..
ENVIRONMENTAL CONSIDERATIONS . . . .
General . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . ..
Temperature, Relative Humidity . . . . . . . . . . . .
. . . ..
Heat Dissipation . . . . . . . . . . . . . . . . . . . .
Radiated Emissions
. . . . . .
Cleanliness . . . . . . . . . . . . . . . . . . . .
INSTALLATION
....... ......... .
General . . . . . . . . . . .
Tools . . . . . . . . . . . .
Unpacking and Inspection .
Cabinet-Mounted . . . . .
Separate Container
. . . . . . .
. . . . . . . . . . . .
Installation . . .
OPERATION
................. .
Operator Control . . . . . . . . . . . . . .
Diskette Handling Practices and Precautions
.
rnskette~om~
................ .
. .......
Short Term (Available for Immediate Use) .
...........
. ... .
Long Term . . . . . .
. ..........
Shipping Diskettes . . . . . . . . . . . . . . . .
iii
1-1
1-1
1-2
1-2
1-2
1-2
1-3
1-3
1-3
1-10
1-10
1-10
1-11
1-11
1-12
1-12
1-12
1-13
2-1
2-1
2-1
2-1
2-1
2-2
2-2
2-2
2-3
2-4
2-4
2-4
2-4
2-4
2-4
2-4
2-4
2-6
2-6
2-8
2-8
2-8
2-12
2-12
2-12
2-12
CONTENTS (Cont)
Page
CHAPTER 3
RXll INTERFACE PROGRAMMING INFORMATION
3.1
3.2
3.2.1
3.2.2
3.2.2.1
3.2.2.2
3.2.2.3
3.2.2.4
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
3.4
3.4.1
3.4.2
3.4.3
3.5
3.6
REGISTER AND VECTOR ADDRESSES . . . . . . . . . . . . . . . . . . . . . . . . .. 3-1
REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
RXCS - Command and Status (177170)
. . . . . . . . . . . . . . . . . . . . . . . 3-2
RXDB - Data Buffer Register (177172) . . . . . . . . . . . . . . . . . . . . . . .. 3-3
RXT A - RX Track Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
RXSA - RX Sector Address . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
RXDB - RX Data Buffer
RXES - RX Error and Status . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
FUNCTION CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Fill Buffer (000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Empty Buffer (001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Write Sector (010) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Read Sector (011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Read Status (101) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Write Sector with Deleted Data (110) . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Read Error Register Function (111) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Power Fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
PROGRAMMING EXAMPLES
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Read Data/Write Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Empty Buffer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Fill Buffer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
RESTRICTIONS AND PROGRAMMING PITFALLS . . . . . . . . . . . . . . . . . . . . 3-11
ERROR RECOVERY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
CHAPTER 4
RX8E INTERFACE PROGRAMMING INFORMATION
4.1
4.2
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
DEVICE CODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Load Command (LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Transfer Data Register (XDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
STR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
INTR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
INIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Error Code Register
. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
RXT A - RX Track Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "
RXSA - RX Sector Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
...............................
RXDB - RX Data Buffer
RX Error and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
FUNCTION CODE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fill Buffer (000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Empty Buffer (001) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Write Sector (010) . . . . . . . . . " . . . . . . . . . . . . . . . . . . . . . . . . .
Read Sector (011) . . . . . . . . . " . . . . . . . . . . . . . . . . . . . . . . . . .
Read Status (101) . . . . . . . . . " . . . . " . . . . . . . . . . . . . . . . . . . .
1V
4-1
4-2
4·2
4-2
4-3
4-3
4-3
4-3
4-3
4-3
4-3
4-4
4-5
4-5
4-6
4-6
4-7
4-7
4-8
4-8
4-9
4-9
CONTENTS (Cont)
Page
4.4.6
4.4.7
4.4.8
4.5
4.5.1
4.5.2
4.5.3
4.6
4.7
Write Deleted Data Sector (110) ..
Read Error Register Function (111)
Power Fail . . . . . . . . . . . . .
PROGRAMMING EXAMPLES
..... .
Write/Write Deleted Data/Read Functions
Empty Buffer Function . . . . . . . . . .
Fill Buffer Function . . . . . . . . . . .
RESTRICTIONS AND PROGRAMMING PITFALLS
ERROR RECOVERY
............ .
CHAPTERS
THEORY OF OPERATION
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.2
5.2.1
5.2.1.1
5.2.1.2
5.2.1.3
5.2.1.4
5.2.1.5
5.2.2
5.2.2.1
5.2.2.2
5.2.2.3
5.2.2.4
5.2.2.5
5.2.2.6
5.2.3
5.2.3.1
5.2.3.2
5.2.3.3
5.2.3.4
5.2.3.5
5.2.3.6
5.2.3.7
5.2.3.8
5.2.3.9
5.2.3.10
5.2.3.11
5.2.3.12
5.2.4
5.2.4.1
. 5.2.4.2
5.2.4.3
OVERALL SYSTEM BLOCK DIAGRAM
Omnibus to RX8E Interface Signals
Unibus to RX 11 Interface Signals
Interface to MCPU Controller Signals
MCPU Controller to Read/Write Electronics Signals
Read/Write Electronics to Drive Signals . . . . .
DET AILED BLOCK DIAGRAM AND LOGIC DISCUSSION
RX8E Interface
Device Select and lOT Decoder
Interrupt Control and Skip Logic
C Line Select Logic
..... .
Interface Register
....... .
Sequence and Function Control Logic
RX 11 Interface
Address Decoder .
Data Path Selection
Interface Register
Sequence and Function Control Logic
Interrupt Control Logic . . . . . . .
Vector Address Generator . . . . . .
Microprogrammed Controller (MCPU) Hardware
Control ROM and Memory Buffer ..
Program Counter and Field Counter
Instruction Decode Logic . . . . . .
....... .
Do Pulse Generator
Branch Condition Selector and Control
Scratch Pad Address Register and Scratch Pad
Counter Input Selector, Counter, and Shift Register
MCPU Timing Generator . . . . .
Sector Buffer and Address Register
CRC Generator and Checker . . .
Data Synchronizer and Separator
Output Circuit . . . . . . . . .
Microprogram Instruction Repertoire
DO Instruction . . .
Conditional Branch
Wait Branch
v
· .
·
·
· .
·
· .
4-9
4-9
4-9
4-10
4-10
4-10
4-10
4-15
4-16
·
·
·
· .
· .
·
· .
· .
...
·
· .
·
·
...
· .
· .
·
·
·
·
· .
· .
·
·
·
· .
5-1
5-2
5-3
5-4
5-6
5-7
5-8
5-8
5-8
5-8
5-8
5-10
5-10
5-11
5-11
5-13
5-13
5-13
5-14
5-14
5-14
5-14
5-16
5-16
5-17
5-17
5-17
5-17
5-18
5-18
5-18
5-19
5-20
5-21
5-21
5-22
5-22
CONTENTS (Cont)
Page
5.2.4.4
5.2.4.5
5.2.5
5.2.6
5.2.6.1
5.2.6.2
5.2.6.3
5.2.6.4
5.2.7
5.2.7.1
5.2.7.2
5.2.7.3
5.2.7.4
Open Scratch Pad . . . . . . .
Jump . . . . . . . . . . . . . .
Microprogram Flowchart Description
Read/Write Electronics . . . . .
Diskette Position . . . . . . . . .
Head Read/Write Circuitry . . .
Head Load Control and Solenoid Drivers
Stepper Motor Control and Motor Drivers
Mechanical Drive . . . .
Drive Mechanism . . . .
Spindle Mechanism ..
Positioning Mechanism
Head Load Mechanism
CHAPTER 6
MAINTENANCE
6.1
RECOMMENDED TOOLS AND TEST EQUIPMENT
CUSTOMER CARE . . . . . . . . .
REMOVAL AND REPLACEMENT
Module Replacement . . . .
Drive Placement . . . . .
CORRECTIVE MAINTENANCE
Initialize Errors
Interface Diagnostic in Memory
Diagnostics Not in Memory
KMll Usage . . . . . . . . . . . . .
6.2
6.3
6.3.1
6.3.2
6.4
6.4.1
6.4.1.1
6.4.1.2
6.4.2
· . 5·22
· . 5·23
· 5·23
· 5·36
· 5·36
. . . . . . . . . . . 5·36
· 5·36
. . . 5·36
· . 5·38
. . . . . . . . 5·39
· 5·39
· . 5·39
· . 541
6·1
6·1
6·2
6·2
64
64
6·4
64
6·9
6·9
ILLUSTRA TIONS
Figure No.
1·1
1·2
1·3
1·4
1·5
1·6
1·7
1·8
1·9
1·10
1·11
2·1
2·2
2·3
24
2·5
2·6
Title
Floppy Disk System Configuration
Front View of the Floppy Disk System
M8357 Module (RX8E Interface)
M7846 Module (RXll Interface)
Top View of the RXO 1 .
Underside View of Drive
Top View of Drive ..
Diskette Media . . . . .
Flux Reversal Patterns .
Track Format (Each Track)
Sector Format (Each Sector)
RXOI
.......... .
Cabinet Layout Dimensions
RXOI Shipping Restraints .
RX8/RX 11 Unpacking . . .
RXOI Cabinet Mounting Information
Cable Routing, BC05L·15 . . . . . . .
vi
Page
1·2
1·3
14
1·5
1·6
1·7
1·8
1·9
1·10
1·10
1·11
2·2
2·3
2·5
2·7
2-8
2·9
ILLUSTRATIONS (Cont)
Figure No.
2-7
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
6-1
6-2
6-3
Title
Flexible Diskette Insertion
RXCS Format (RXll)
RXTA Format (RXll)
RXSA Format (RXll)
RXDB Format (RX11)
RXES Format (RXll)
...... .
RXll Write/Write Deleted Data/Read Example
RXl1 Empty Buffer Example
RXll Fill Buffer Example . . . . .
LCD Word Format (RX8E)
Command Register Format (RX8E)
Error Code Register Format
RXTA Format (RX8E)
RXSA Format (RX8E)
RXDB Format (RX8E)
RXES Format (RX8E)
RX8E Write/Write Deleted Data/Read Example
RX8E Empty Buffer Example ..
Fill Buffer Example . . . . . . . .
.......... .
Bus Structure
Omnibus to RX8E Interface Signals
Unibus to RXl1 Interface Signals
Interface to pCPU Controller Signals
pCPU Controller to Read/Write Electronics Signals
Read/Write Electronics to Drive Signals
RX8E Interface Block Diagram
RXll Interface Block Diagram
pCPU Controller Block Diagram
Data and Clock Separation . . . .
ID Address Mark Data Separation
Initialize and Function Decode Flowchart .
Empty and Fill Buffer Functions Flowchart
Read Sector and Read Status Functions Flowchart
........ .
Write Sector Function Flowchart
FINDTR Subroutine Flowchart . . . . . . . . .
FINDHD and GETDAM Subroutines Flowchart .
HDRCOM, BDSRT, BADHDR Routines Flowchart
DELAY, FINDSE, WRTOS, GETWRD Subroutines Flowchart
STEPHD, WAlTRN, MAGCOM Subroutines Flowchart
DIF and CHKRDY Subroutine Flowchart
Read/Write Electronics Block Diagram .
Disk Drive Mechanical System
Drive Mechanism . . . . . . .
Centering Cone and Drive Hub
Positioning Mechanism
RXO 1, Rear View
Troubleshooting Flow
BC05L-15 Cable
vii
Page
· . 2-11
3-2
3-3
3-3
3-4
3-4
3-9
· . 3-10
· . 3-13
4-2
4-3
4-4
4-5
4-5
4-6
4-6
· . 4-11
· . 4-13
· . 4-14
5-1
5-2
5-3
5-4
5-6
5-7
· ..
· .
......
......
· ..
· .
· .
·
· ..
·
·
.....
· .
· .
. . . . ..
5-9
5-12
5-15
5-19
5-20
5-24
5-25
5-26
5-28
5-29
5-30
5-32
5-33
5-34
5-35
. 5-37
·
· .
·
· .
5-38
5-39
5-40
5-40
6-2
6-5
6-7
ILLUSTRATIONS (Cont)
Figure No.
6-4
6-5
6-6
6-7
Page
Title
RX8 Status Routine
..... .
RX 11 Status Routine
KM 11 Maintenance Module Inserted
KM 11 Light and Switch Definitions for RXOI
. ..
·
·
..
6-10
6-10
6-11
6-12
TABLES
Table No.
2-1
4-1
5-1
6-1
6-2
Title
Page
Interface Code/Jumper Configuration
Device Code Switch Selection
C Line Transfer Control Signals
Recommended Tools and Test Equipment
M7727 Connectors . . . . . . . . . . . .
· 2-10
· 4·1
. . . 5-10
6-1
.. 6-3
viii
CHAPTER 1
GENERAL INFORMATION
This manual presents information on the installation, operation, programming, theory of operation, and
maintenance of the RX8 or RXII Floppy Disk System. Chapter 2 (Installation and Operation) should be consulted
for unpacking and installation information. Chapter 2 also provides information on the proper care of the media and
should be read carefully.
1.1 INTRODUCTION
The RX8 and RXII Floppy Disk Systems consist of an RXOI sUbsystem and either an RX8E interface for a PDP-8
system or an RXII interface for a PDP-II system.
The RXOI is a low cost, random access, mass memory device that stores data in fixed length blocks on a
preformatted, IBM-compatible, flexible diskette. Each drive can store and retrieve up to 256K 8-bit bytes of data
(PDP-ll or PDP-8) or I28K I2-bit words (PDP-8). The RXOI consists of one or two flexible disk drives, a single
read/write electronics module, a microprogrammed controller module, and a power supply, enclosed in a
rack-mountable, 10-1/2 inch, self-cooled chassis. A cable is included for connection to either a PDP-8 interface
module for use on the PDP-8 Omnibus or a PDP-II interface for use on the PDP-II Unibus.
The RXOI performs implied seeks. Given an absolute sector address, the RXOI locates the desired sector and
performs the indicated function, including automatic head position verification and hardware calculation and
verification of the Cyclic Redundancy Check (CRC) character. The CRC character that is read and generated is
compatible with IBM 3740 equipment.
The RXOI connects to the M8357 Omnibus interface module, which converts the RXOI I/O bus to a PDP-8 family
Omnibus structure. It controls interrupts to the CPU initiated by the RXOI, controls data interchange between the
RXOI and the host CPU, and handles I/O transfers used to test status conditions.
The RXOI connects to the M7846 Unibus interface module, which converts the RXOI I/O bus to a PDP-II Unibus
structure. It controls interrupts to the CPU initiated by the RXOI, decodes Unibus addresses for register selection,
and handles data interchange between the RXOI and the host CPU.
The interface modules are dc powered by their host processor.
1.2 PHYSICAL DESCRIPTION
A complete system consists of the following components:
M7726 controller module
M7727 read/write electronics module
H77IA or B power supply
RXOI-CA floppy disk drive (60 Hz, max of 2)
RXOI-CC floppy disk drive (50 Hz, max of 2)
M8357 (RX8E) or M7846 (RXII) interfaces
1-1
All components except the interface are housed in a 10-1/2 in. rack-mountable box. The power supply, M7726
module, and M7727 module are mounted above the drives. Interconnection from the RXOI to the interface is with a
40-conductor BC05L-15 cable of standard length (15 ft). Figure 1-1 is a configuration drawing of the system, and
Figure 1-2 is a front view of a dual drive system.
CP-1505
Figure 1-1 Floppy Disk System Configuration
1.2.1 RX8E/RXll Interfaces
Interface modules M8357 (RX8E) and M7846 (RXll) are both quad modules. The M8357 plugs into an Omnibus
slot and allows the RXOI to be used on the PDP-8 processors. The M7846 plugs into an SPC (small peripheral
controller) slot with any PDP-II processor. Figure 1-3 shows the M8357 module and its major sections. Figure 14
shows the M7846 module and its major sections.
1.2.2 Microprogrammed Controller
The M7726 microprogrammed controller module is located in the RXOI cabinet as shown in Figure 1-5. The M7726
is hinged on the left side and lifts up for access to the M7727 read/write electronics module.
1.2.3 Read/Write Electronics
The M7727 read/write electronics module is located in the RXOI cabinet as shown in Figure 1-5.
1.2.4 Electro-Mechanical Drive
A maximum of two drives can be attached to the read/write electronics. The electro-mechanical drives are mounted
side by side under the read/write electronics board (M7727). Figure 1-6, which is an underside view of the drive,
shows the drive motor connected to the spindle by a belt. (This belt and the small pulley are different on the 50 Hz
and 60 Hz units; see Paragraph 2.2.3.2 for complete input power modification requirements.) Figure 1-7 is the top
view showing the electro-mechanical components of the drive.
1-2
7408-1
Figure 1-2 Front View of the Floppy Disk System
1.2.5 Power Supply
The H771 power supply is mounted at the rear of the RX01 cabinet as shown in Figure 1-5. The H771A is rated at
60 Hz ± 1/2 Hz over a voltage range of 90-132 Vac. The H771C and D are rated at 50 Hz ± 1/2 Hz over four voltage
ranges:
90-120 Vac }
100-132 Vac
3.5 A circuit breaker; H771C
1BO-240 Vac }
200-264 Vac
1.75 A circuit breaker; H771D
Two power harnesses are provided to adapt the H771C or D to each voltage range. This is not applicable to the
H771A. See Paragraph 2.2.3.2 for complete input power modification requirements.
1.3 SYSTEMS COMPATIBILITY
This section describes the physical, electrical, and logical aspects of IBM compatibility as defined for data
interchange with IBM system 3740 devices.
1.3.1 Media
The media used on the RXB or RX11 Floppy Disk System is compatible with the IBM 3740 family of equipment
and is shown in Figure I-B.
The "diskette" media was designed by applying tape technology to disk architecture. This resulted in a flexible
oxide-on-mylar surface encased in a plastic envelope with a hole for the read/write head, a hole for the drive spindle
hub, and a hole for the hard index mark. The envelope is lined with a fiber material that cleans the diskette surface.
The media is supplied to the customer preformatted and pretested.
1-3
BC05L-15
INTERFACE
CABLE
CONNECTOR
DEVICE
CODE
SWITCHES
7408-3
Figure 1-3 M8357 Module (RX8E Interface)
1-4
CONNECTOR
FOR THE
BC05L-15
INTERFACE
CABLE
PRIORITY
PLUG
RX11
INTERFACE
REGISTER
Figure 1-4 M7846 Module (RXll Interface)
1-5
7408-4
M7726,uCPU
CONTROLLER
MODULE
BC05L·15
INTERFACE
CABLE
M7727
READIWRITE
ELECTRONICS
MODULE
H771
POWER
SUPPLY
7408-8
Figure 1-5 Top View of the RXOI
1-6
DRIVE MOTOR
BELT
DRIVE SPINDLE
PULLEY
AC
POWER
CONNECTOR
DC
STEPPER
MOTOR
7408-5
Figure 1-6 Underside View of Drive
1-7
READ/WRITE
HEAD
HEAD LOAD
ARM
HELIX
DRIVE
Figure 1-7 Top View of Drive
1-8
INDEX HOLE
REGISTRATION
HOLE
READ/WRITE
HEAD
APERTURE
7408-2
Figure 1-8 Diskette Media
1-9
1.3.2 Recording Scheme
The recording scheme used is "double frequency." In this method, data is recorded between bits of a constant clock
stream. The clock stream consists of a continuous pattern of 1 flux reversal every 4 ps (Figure 1-9). A data "one" is
indicated by an additional reversal between clocks (Le., doubling the bit stream frequency; hence the name). A data
"zero" is indicated by no flux reversal between clocks.
A continuous stream of ones, shown in the bottom waveform in Figure 1-9, would appear as a "2F" bit stream, and
a continuous stream of zeros, shown in the top waveform in Figure 1-9, would appear as a "IF" or fundamental
frequency bit stream.
ALL ZEROS
PATTERN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHANGING
PATTERN
0
0
0
ALL ONES
PATTERN
I
I
I
-: 41'sec
I
I
I
L.-
CP -1506
I
Figure 1-9 Flux Reversal Patterns
1.3.3 Logical Format
The logical format of the RX8 and RXII Floppy Disk Systems is the same as that used in the IBM 3740.
Data is recorded on only one side of the diskette. This surface is divided into 77 concentric circles or "tracks"
numbered 0-76. Each track is divided into 26 sectors numbered 1-26 (Figure 1-10). Each sector contains two
major fields: the header field and the data field (Figure 1-11).
r--_-.LL---,L.E.D. TRANSDUCER OUTPUT
,
HARD
II
..I L
I
~f~~ ~--------------------------~"
~
PRE-INDEX
tSECTOR
GAP
#26 Rl320BYTES
SECTOR
#1
SECTOR
#2
SECTOR
#3
I
T
SECTOR
#4
~
CP-1507
SOFT INDEX MARK
1 BYTE
_
ROTATION
Figure 1-10 Track Format (Each Track)
1.3.3.1 Header Description - The header field is broken into seven bytes (eight bits/byte) of information and is
preceded by a field of zeros for synchronization.
1.
Byte No.1: ID Address Mark - This is a unique stream of flux reversals (not a string of data bits) that is
decoded by the controller to identify the beginning of the header field.
2.
Byte No.2: Track Address - This is the absolute (0-1148) binary track address. Each sector contains
track address information to identify its location on 1 of the 77 tracks.
1-10
HEADER FIELD
DATA FIELD
~O
-H
aJ'
l>l>
-<!='
ADDRESS
MARK
SYNC
FIELD
ALL "O'S"
33 BYTES
-tl>
"'0
o
RI
en
en
~
l>
::0
;ot
-I J.-,
,.
L
-en
--t
aJ::O
-<l>
-to
"';ot
l>
~~
aJ
•
.
-<~
-ten
",
o
o
::0
",
en
en
aJ'"
aJ
•
-t
en-
-<0
-<0
-t-t
",0
::0
",
l>
HEADER
CRC
2 BYTES
o
o
DATA MARK
SYNC FIELD
ALL "O'S"
17 BYTES
-0
aJ::o
-<
-to
",~
128 10 BYTES
OF DATA
",
-t
DATA
CRC
2 BYTES
",
o
o
::0
",
en
en
~
I
BYTE
"BYTES--tol·.....---..;
..
~
l
WRITE GATE TURN OFF
FOR WRITE OF PRECEEDING
DATA FIELD
-
1---6 BYTES
WRITE GATE TURN ON
FOR WRITE OF NEXT
DATA FIELD
CP-H50S
ROTATION
Figure 1·11 Sector Format (Each Sector)
3.
Byte No.3 - Zeros (one byte)
4.
Byte No.4: Sector Address - This is the absolute binary sector address (1-328). Each sector contains
sector address information to identify its circumferential position on a track.
5.
Byte No.5 - Zeros (one byte)
6.
Bytes No.6 and 7: CRC - This is the Cyclic Redundancy Check character that is calculated for each
sector from the first five header bytes using a polynomial division algorithm designed to detect the types
of failures most likely to occur with "double frequency" recorded data and the floppy media. The CRC
is compatible with IBM 3740 series equipment.
1.3.3.2 Data Field Description - The data field is broken into 131 bytes of information and is preceded by a field
of zeros for synchronization and the header field (Figure 1·11).
1.
Byte No. I: Data or Deleted Data Address Mark - This is a unique string of flux reversals (not a string
of data bits) that is decoded by the controller to identify the beginning of the data field. The deleted
data mark is not used during normal operation but the RX01 can identify and write deleted data marks
under program cQntrol, as required. The deleted data mark is only included in the RX8/RXII system to
be IBM compatible. One or the other data address marks precedes each data field.
2.
Bytes No. 2-129 - These bytes comprise the data field used to store 128 8-bit bytes of information.
NOTE
Partial data fields are not recorded.
3.
Bytes No. 130 and 131 - These bytes comprise the CRC character that is calculated for each sector
from the first 129 data field bytes using the industry standard polynomial division algorithm designed to
detect the types of failures most likely to occur in double frequency recording on the floppy media.
1.3.3.3 Track Usage - In the IBM 3740 system, some tracks are commonly designated for special purposes such as
error information, directories, spares, or unused tracks. The RXOI is capable of recreating any system structure
through the use of special systems programs, but normal operation will make use of all the available tracks as data
tracks. Any special file structures must be accomplished through user software.
1·11
1.3.3.4 CRC Capability - Each sector has a two-byte header CRC character and a two-byte data CRC character to
ensure data integrity. The CRC characters are generated by the hardware during a write operation and checked to
ensure all bits were read correctly during a read operation. The CRC character is the same as that used in the IBM
3740 series of equipment. A complete description of CRC generation and checking is presented in Paragraph 5.2.3.
1.4 APPLICABLE INSTRUCTION MANUALS
This manual is designed to be used in conjunction with the RXS/RXII Engineering Drawings. Other documents
useful in operating and understanding the RXS/RXll system are:
PDP-}} * Processor Handbook
PDP-}} Peripherals and Inter/acing Handbook
PDP-8 Small Computer Handbook
PDP-8A User Manual
1.5 CONFIGURATION
Option number designations are as follows:
PDP-8 Systems
RXS-AA
RXS-AD
RXS-BA
RXS-BD
Single drive system, 115 V, 60 Hz
Single drive system, 50 Hz
Dual drive system, 115 V /60 Hz
Dual drive system, 50 Hz
PDP-II Systems
RX11-AA
RX11-AC
RX11-BA
RXI1-BD
Single drive system, 115 V/60 Hz
Single drive system, 50 Hz
Dual drive system, 115 V/60 Hz
Dual drive system, 50 Hz
NOTE
50 Hz versions are available in voltages of 105, 115,220,240
Vac by field pluggable conversion. See Paragraph 2.2.3.2 for
complete input power modification requirements.
'" Appropriate handbook for the particular processor used with the system.
1-12
1.6 SPECIFICATIONS
System Reliability
Minimum number of revolutions per track
1 million/media (head loaded)
Seek error rate
1 in 10 6 seeks
Soft read error rate
1 in 10 9 bits read
Hard read error rate
1 in 10 12 bits read
. NOTE
The above error rates only apply to media that is properly
cared for. Seek error and soft read errors are usually
attributable to random effects in the head/media interface,
such as electrical noise, dirt, or dust. Both are called "soft"
errors if the error is recoverable in ten additional tries or less.
"Hard" errors cannot be recovered. Seek error retries should
be preceded by an Initialize.
Drive Performance
Capacity
Per diskette
Per track
Per sector
Data transfer rate
Diskette to controller buffer
Buffer to CPU interface
CPU interface to I/O bus
8-bit bytes
12-bit words
256,256 bytes
3,328 bytes
128 bytes
128,128 words
1,664 words
64 words
4 Ms/data bit (250K bps)
2 Ms/bit (500K bps)
18 Ms/8-bit byte (> 50K bytes/sec)
NOTE
PDP-8 interface can operate in 8- or 12-bit modes under
software control. The transfer rate is 23 MS per 12-bit word
(>40K bytes/sec).
Track-to-track move
Head settle time
Rotational speed
Recording surfaces per disk
Tracks per disk
Sectors per track
Recording technique
Bit density
Track density
Average access
10 ms/track maximum
25 ms maximum
360 rpm ± 2.5%; 166 ms/rev nominal
1
77 (0-76) or (0-1148)
26 (1-26) or (1-328)
Double frequency
3200 bpi at inner track
48 tracks/in.
488 ms, computed as follows:
Seek
Settle
Rotate
(77 tks/2) X 10 ms + 25 ms + (166 ms/2) = 493 ms
I
1-13
Environmental Characteristics
Temperature
RXOI, operating
RXOI, nonoperating
0
15° to 32° C (59° to 90 F) ambient; maximum
temperature gradient =20° F/hr (11.1 ° C/hr)
0
_35 to +600 C (_30 0 to +1400 F)
Media, operating
Media, nonoperating
0
-35 0 to +52 C (-30° to +125° F)
NOTE
Media temperature must be within operating temperature
range before use.
Relative humidity
RX01, operating
0
0
25 C (77 F) maximum wet bulb
0
2 C (36° F) minimum dew point
20% to 80% relative humidity
RX01, nonoperating
5% to 98% relative humidity (no condensation)
Media, nonoperating
10% to 80% relative humidity
Magnetic field
Media exposed to a magnetic field strength of 50 oersteds
or greater may lose data.
Interface modules
Operating temperature
Relative humidity
Maximum wet bulb
Minimum dew point
0
0
5° to 50° C (41 to 122 F)
10% to 90%
0
32° C (90 F)
0
0
2 C (36 F)
Electrical
Power consumption
RXOI
PDP-II interface (M7846)
PDP-8 interface (M8357)
AC power input
3 A at 24 V (dual), 75W; 5 A at 5 V, 25 W
Not more than 1.5 A at 5 Vdc
Not more than 1.5 A at 5 Vde
4 A at 115 Vae
2 A at 230Vae
1-14
CHAPTER 2
INSTALLATION AND OPERATION
2.1 PURPOSE AND ORGANIZATION
This chapter provides information on installing and operating the RX8/RXll Floppy Disk System. This information
is organized into four sections as outlined below.
1.
Site Preparation - The planning required to make the installation site suitable for operation of the
floppy disk system, including space, cabling, and power requirements, and fire and safety precautions.
2.
Environmental Considerations - The specific environmental characteristics of the floppy disk systems,
i.e., temperature, relative humidity, air conditioning and/or heat dissipation, and cleanliness.
3.
Installation - The actual step-by-step process of installing the floppy disk system from unpacking
through the preliminary installation checks, power conversion techniques, and acceptance testing.
4.
Operation Practices - The recommended practices for using the floppy disk system, handling the media,
and shipping and storing the diskettes.
2.2 SITE PREPARATION
2.2.1 Space
The RXOI is a cabinet-mountable unit that may be installed in a standard Digital Equipment Corporation cabinet.
This rack-mountable version is approximately 10-1/2 in. (28 cm) high, 19 in. (48 cm) wide, and 16-1/2 in. (42 cm)
deep (Figure 2-1).
Provision should be made for service clearances of approximately 22 in. (56 cm) at the front and rear of the cabinet
(Figure 2-2).
2.2.2 Cabling
The standard interface cable provided with an RX8/RXll (BC05L-15) is 15 ft (4.6 m) in length, and the positioning
of the RXOI in relation to the central processor should be planned to take this into consideration. The RXOI should
be placed near the control console or keyboard so that the operator will have easy access to load or unload disks.
The position immediately above the CPU is preferred. The ac power cord will be about 9 ft (2.7 m) long.
2.2.3 AC Power
2.2.3.1 Power Requirements - The RXOI is designed to use either a 60 Hz or a 50 Hz power source. The 60 Hz
version (RXOI-A) will operate from 90 to 132 Vac, without modifications, and will use less than 4 A operating. The
50 Hz version (RXOI-D) will operate within four voltage ratings and will require field verification/modification to
ensure that the correct voltage option is selected. The voltage ranges of90 to 120 Vac and 180 to 240 Vac will use
less than 4 A operating. The voltage ranges of 100-132 Vac and 200-264 Vac will use less than 2 A. Both versions
of the RXOI will be required to receive the input power from an ac source (e.g., 861 power control) that is
controlled by the system's power switch.
2-1
1
10.5"
Ilillllmllllll~IIIIIIIIIIIII~I~~llllllllllllmlllllllll~~
I·
19"
(48.3 em)
],m)
·1
(FRON T VIEW)
17.0"
'I
(43.2 em)
\',.--
~
---
~
-~
~
I
(FRONT)
0
----
.....------,
-
~
<Z>
1:-
.....----,
~
~
VSEE NOTE
IINSIOE TRACK
r:a:==:::J
26.5"
(66.3 em)
SIDE VIEW)
NOTE
Dust cover allaehed to cabinet
not RXO 1.
CP-1611
Figure 2-1
RXO 1
2.2.3.2 Input Power Modification Requirements - The 60 Hz version of the RXOI uses the H771A power supply
and will operate on 90 to 132 Vac, without modification. To convert to operate on a 50 Hz power source in the
field, the H771A supply must be replaced with an H771C or D (Figure 1-5) and the drive motor belt and drive
motor pulley must be replaced (Figure 1-6). The 50 Hz version of the RX01 uses either the H77lC or D power
supply. The H771C operates on a 90-120 Vac or 100-132 Vac power source. The H771D operates on a
180-240 Vac or 200-264 Vac power source. To convert the H771C to the higher voltage ranges or the H771D to
the lower voltage ranges, the power harness and circuit breaker must be changed. See Figure 2-3 for appropriate
power harness and circuit breaker.
2.2.4 Fire and Safety Precautions
The RX8/RXII Floppy Disk System presents no additional fire or safety hazards to an existing computer system.
Wiring should be carefully checked, however, to ensure that the capacity is adequate for the added load and for any
contemplated expansion.
2.3 ENVIRONMENTAL CONSIDERATIONS
2.3.1 General
The RX8/RXII is capable of efficient operation in computer environments; however, the parameters of the
operating environment must be determined by the most restrictive facets of the system, which in this case are the
diskettes.
2-2
SWINGING
MOUNTING
~, \F::M~~::O: _R_.H_O_R_L_.H_._ _ _ _ _ _~-~
-~ _\~
-..;~~
/'/
;;- ~
'""
""""
""\\
//
////
II
~
18 Y3~
(46.35em)
\\
If
\\
'l
\\
~
\\
\
I
\
/I
\
nj/'~~~~~~~~~~~'\ ---------------~
+
+
REMOVABLE
END PANEL
48 7/ 32"
( 122.47em)
FAN
PORTS
30"
(76.2em)
LEVELER
4 PLACES
+
CASTER SWIVEL
RADIUS 2 '3/32"
(6.12 em)
(4) CASTERS
+
I
1.1
21'~'6
I -
:
(54.87 em)
'.1
I
I
I
1
I
RXOI EXTENDED
FROM CABINET
I
I
II
19
(48.26 em)
I
L________ J~
CABIN ET 717/,~ (182 .28em) high
(floor line to cabinet top)
CP-1612
Figure 2·2 Cabinet Layout Dimensions
2.3.2 Temperature, Relative Humidity
The operating ambient temperature range of the diskette is 59° to 90° F (I5° to 32° C) with a maximum
temperature gradient of 20° F/hr (-6.7° C/hr).
The media nonoperating temperature range (storage) is increased to -30° to 125° F (-34.4° to 51.6° C), but care
must be taken to ensure that the media has stabilized within the operating temperature range before use. This range
will ensure that the media will not be operated above its absolute temperature limit of 125° F.
2·3
Humidity control is important in any system because static electricity can cause errors in any CPU with memory.
The RX01 is designed to operate efficiently within a relative humidity range of 20 to 80 percent, with a maximum
wet bulb temperature of 77° F (25° C) and a maximum dew point of 36° F (2° C).
2.3.3 Heat Dissipation
The heat dissipation factor for the RX01 Floppy Disk System is less than 225 Btu/hr. By adding this figure to the
total heat dissipation for the other system components and then adjusting the result to compensate for such factors
as the number of personnel, the heat radiation from adjoining areas, and sun exposure through windows, the
approximate cooling requirements for the system can be determined. It is advisable to allow a safety margin of at
least 25 percent above the maximum estimated requirements.
2.3.4 Radiated Emissions
Sources of radiation, such as FM, vehicle ignitions, and radar transmitters located close to the computer system, may
affect the performance of the RX8/RX11 Floppy Disk System because of the possible adverse effects magnetic
fields can have on diskettes. A magnetic field with an intensity of 50 oersteds or greater might destroy all or some of
the information recorded on the diskette.
2.3.5 Cleanliness
Although cleanliness is important in all facets of a computer system, it is particularly important in the case of
moving magnetic media, such as the RXOl. Diskettes are not sealed units and are vulnerable to dirt. Such minute
obstructions as dust specks or fingerprint smudges may cause data errors. Therefore, the RX01 should not be
subjected to unusually contaminated atmospheres, especially one with abrasive airborne' particles. (Refer to
Paragraph 2.5.2.)
NOTE
Removable media involve use, handling, and maintenance
which are beyond DEC's direct control. DEC disclaims
responsibility for performance of the equipment when operated with media not meeting DEC specifications or with media
not maintained in accordance with procedures approved by
DEC. DEC shall not be liable for damages to the equipment or
to media resulting from such operation.
2.4 INSTALLATION
2.4.1 General
The RX8/RX11 Floppy Disk System can be shipped in a cabinet as an integral part of a system or in a separate
container. If the RX01 is shipped in a cabinet, the cabinet should be positioned in the final installation location
before proceeding with the installation.
2.4.2 Tools
Installation of an RX8/RX11 Floppy Disk System requires no special tools or equipment. Normal hand tools are all
that are necessary. However, a forklift truck or pallet handling equipment may be needed for receiving and installing
a cabinet-mounted system.
2.4.3 Unpacking and Inspection
2.4.3.1 Cabinet-Mounted
1.
Remove the protective covering over the cabinet.
2.
Remove the restraint on the rear door latch and open the door.
24
3.
Remove the two bolts on the cabinet's lower side rails that attach the cabinet to the pallet.
4.
Raise the four levelers at the corners of the cabinet, allowing the cabinet to roll on the casters.
5.
Carefully roll the cabinet off the pallet; if a forklift is available, it should be used to lift and move the
cabinet.
6.
Remove the shipping restraint from the RXOI and save it for possible reuse (Figure 2-3).
7.
Slide the RXOI out on the chassis slides and visually inspect for any damage, loose screws, loose wiring,
etc.
NOTE
If any shipping damage is found, the customer should be
notified at this time so he can contact the carrier, and record
the information on the acceptance form.
JUMPER P1
FILTER
POWER PLUGS
FILTER
7436-12
VOLTAGE (Vac)
POWER HARNESS
CIRCUIT BREAKER
90-120
100-132
180-240
200-264
70-10696-02
70-10696-01
70-10696-04
70-10696-03
3.5 A, 12-12301-01
3.5 A, 12-12301-01
1.75 A, 12-12301-00
1.75 A, 12-12301-00
Figure 2-3 RXOI Shipping Restraints
2-5
2.4.3.2 Separate Container
1.
Open the carton (Figure 2-4) and remove the corrugated packing pieces.
2.
Lift the RXOI out of the carton and remove the plastic shipping bag.
3.
Remove the shipping fixtures from both sides of the RXOI and inspect for shipping damage.
4.
Attach the inside tracks of the chassis slides provided in the carton to the RXOI (Figure 2-1).
5.
Locating the proper holes in the cabinet rails (Figure 2-5), attach the outside tracks to the cabinet.
6.
Place the tracks attached to the RXOI inside the extended cabinet tracks and slide the unit in until the
tracks lock in the extended position.
7.
Locate the RXOI cover in the cabinet above the unit and secure it to the cabinet rails (Figure 2-3).
2.4.4 Installation
1.
Loosen the screws securing the upper module (M7726) and swing it up on the hinge.
2.
Inspect the wiring and connectors for proper routing and ensure that they are seated correctly.
3.
This step is for 50 Hz versions only. Check the power configuration to ensure that the proper power
harness and the correct circuit breaker are installed (Figure 2-3).
4.
Connect the BC05l.r15 cable to the M7726 module and route it through the back of the RXOI (Figure
2-6) to the CPU, then connect it to the interface module (RX8E, M8357; RXll, M7846).
5.
Refer to Table 2-1 for correct device code or addressing jumpers.
6.
Ensure that power for the system is off.
7.
Insert the interface module into the Omnibus (RX8E) or available SPC slot (RX11). (Refer toPDP-ll
Processor Handbook, Specifications, Chapter 9.)
8.
Connect the RXOI ac power cord into a switched power source.
9.
Turn the power on, watching for head movement on the drive(s) during the power up, initialize phase.
The head(s) should move ten tracks toward the center and back to track O.
10.
Perform the diagnostic in the sequence listed below for the number of passes (time) indicated. If any
errors occur, refer to Chapter 6 for corrective action.
RX8 or RX11 Diagnostic - 2 passes
Data Reliability /Exerciser - 3 passes
DECX-8 or DECX-11 - 10 minutes
2-6
SLIDES
ONE PIECE
FOLDER
9905711
PLYWOOD HOLDING
FIXTURE RT. SI DE
9905712-01
PLYWOOD HOLDING
FIXTURE LT. SIDE
9905712-00
FLAT WASHER (8)
/
90- 09024-00
~,......--LOCK WASHER (8)
' , - 90-07906-00
~SCREW(8)
90- 06076-01
SLOTTED
SHIPPING
CARTON
CP-1596
Figure 2-4 RX8/RXll Unpacking
2-7
COVER
SCREWS,
CHASSIS SLIDES
o
o
CP-1594
Figure 2-5 RXO 1 Cabinet Mounting Information
2.5 OPERATION
2.5.1 Operator Control
The simplicity of the RXOI precludes the necessity of operator controls and indicators. A convenient method of
opening the unit for diskette insertion and removal is provided. On each drive is a simple pushbutton, which is
compressed to allow the spring-loaded front cover to open. The diskette may be inserted or removed, as shown in
Figure 2-7, with the label up. The front cover will automatically lock when the bar is pushed down.
CAUTION
The drive(s) should not be opened while they are being
accessed because data may be incorrectly recorded, resulting in
a CRC error when the sector is read.
2.5.2 Diskette Handling Practices and Precautions
To prolong the diskette life and prevent errors when recording or reading, reasonable care should be taken when
handling the media. The following handling recommendations should be followed to prevent unnecessary loss of
data or interruptions of system operation.
1.
Do not write on the envelope containing the diskette. Write any information on a label prior to affixing
it to the diskette.
2.
Paper clips should not be used on the diskette.
3.
Do not use writing instruments that leave flakes, such as lead or grease pencils, on the jacket of the
media.
2-8
M7727
7436-18
Figure 2-6 Cable Routing, BC05L-15
2-9
Table 2·1
Interface Code/J umper Configuration
RXll (M7846)
BR Priority
BR7 BR6 *BR5 BR4 -
54-08782
54-08780
54-08778
57-08776
RX8E (M8357)
Device Codes
*670X
67lX
672X
673X
674X
675X
676X
677X
SWI
SW2
SW3
SW4
SW5
SW6
ON
ON
ON
ON
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
*Unibus Address 17717X
A12/W18 - Removed
All/W17 - Removed
AlO/W16 - Removed
A9/W15 - Removed
A8/W14 - Installed
A7 /W13 - Installed
A6/W12 - Removed
AS/WI 1 - Removed
A4/WlO - Removed
A3/W9 - Removed
* Vector Address (264 8 )
V2/Wl V3/W2 V4/W3 V5/W4 V6/W5 V7/W6 V8/W7 -
*Standard
2-10
Installed
Removed
Installed
Installed
Removed
Installed
Removed
7408-6
Figure 2-7 Flexible Diskette Insertion
4.
Do not touch the disk surface exposed in the diskette slot or index hole.
5.
Do not clean the disk in any manner.
6.
Keep the diskette away from magnets or tools that may have become magnetized. Any disk exposed to a
magnetic field may lose information.
7.
Do not expose the diskette to a heat source or sunlight.
8.
Always return the diskette to the envelope supplied with it to protect the disk from dust and dirt.
Diskettes not being used should be stored in the fIle box if possible.
9.
When the diskette is in use, protect the empty envelope from liquids, dust, and metallic materials.
10.
Do not place heavy items on the diskette.
11.
Do not store diskettes on top of computer cabinets or in places where dirt can be blown by fans into the
diskette interior.
12.
If a diskette has been exposed to temperatures outside of the operating range, allow 5 minutes for
thermal stabilization before use. The diskette should be removed from its packaging during this time.
2-11
2.5.3 Diskette Storage
2.5.3.1 Short Term (Available for Immediate Use)
1.
Store diskettes in their envelopes.
2.
Store hOrizontally, in piles of ten or less. If vertical storage is necessary, the diskettes should be
supported so that they do not lean or sag, but should not be subjected to compressive forces. Permanent
deformation may result from improper storage.
3.
Store in an environment similar to that of the operating system; at a minimum, store within the
operating environment range.
2.5.3.2 Long Term - When diskettes do not need to be available for immediate use, they should be stored in their
original shipping containers within the nonoperating range of the media.
2.5.4 Shipping Diskettes
Data recorded on disks may be degraded by exposure to any sort of small magnet brought into close contact with
the disk surface. If diskettes are to be shipped in the cargo hold of an aircraft, take precautions against possible
exposure to magnetic sources. Because physical separation from the magnetic source is the best protection against
accidental erasure of a diskette, diskettes should be packed at least 3 in. within the outer box. This separation should
be adequate to protect against any magnetic sources likely to be encountered during transportation, making it
generally unnecessary to ship diskettes in specially shielded boxes.
When shipping, be sure to label the package:
DO NOT EXPOSE TO PROLONGED HEAT OR SUNLIGHT.
When received, the carton should be examined for damage. Deformation of the carton should alert the receiver to
possible damage of the diskette. The carton should be retained, if it is intact, for storage of the diskette or for future
shipping.
2·12
CHAPTER 3
RXll INTERFACE
PROGRAMMING INFORMATION
This chapter describes device registers, register and vector address assignments, programming specifications, and
programming examples for the RXll interface.
All software control of the RXll is performed by means of two device registers: the RXll Command and Status
register (RXCS) and a multipurpose RXll Data Buffer register (RXDB). These registers have been assigned bus
addresses and can be read or loaded, with certain exceptions, using any instruction referring to their addresses.
The RX01, which includes the mechanical drive (s), read/write electronics, and pCPU controller, contains all the
control circuitry required for implied seeks, automatic head position verification, and calculation and verification of
the CRC; it has a buffer large enough to hold one full sector of diskette data (128 8-bit bytes). Information is
serially passed between the interface and the RXOI.
A typical diskette write sequence, which is initiated by a user program, would occur in two steps:
1.
Fill Buffer - A command to fill the buffer is moved into the RXCS. The Go bit (paragraph 3.2.1) must
be set. The program tests for Transfer Request (TR). When TR is detected, the program moves the first
of 128 bytes of data to the RXDB. TR goes false while the byte is moved into the RX01. The program
retests TR and moves another byte of data when TR is true. When the RXOI sector buffer is full, the
Done bit will set, and an interrupt will occur if the program has enabled interrupts.
2.
Write Sector - A command to write the contents of the buffer onto the disk is issued to the RXCS.
Again the Go bit must be set. The program tests TR, and when TR is true, the program moves the
desired sector address to the RXDB. TR goes false while the RXO 1 handles the sector address. The
program again waits for TR and moves the desired track address to the RXDB, and again TR is negated.
The RXOI locates the desired track and sector, verifies its location, and writes the contents of the sector
buffer onto the diskette. When this is done, an interrupt will occur if the program has enabled interrupts.
A typical diskette read occurs in just the reverse way: first locating and reading a sector into the buffer (Read
Sector) and then unloading the buffer into core (Empty Buffer). In either case, the content of the buffer is not valid
if Power Fail or Initialize follows a Fill Buffer or Read Sector function.
3.1 REGISTER AND VECTOR ADDRESSES
The RXCS register is normally assigned Unibus address 177170, and the RXDB register is assigned Unibus address
177172. The normal BR priority level is 5, but it can be changed by insertion of a different priority plug located on
the interface module. The vector address is 264.
3-1
3.2 REGISTER DESCRIPTION
3.2.1 RXCS - Command and Status (177170)
Loading this register while the RXOI is not busy and with bit 0 = 1 will initiate a function as described below and
indicated in Figure 3-1. Bits 0-4 write-only bits.
15
14
t2
11
10
09
07
08
!
I
ERROR
13
I
NOT USED
I
06
04
03
\
I
TR
RX
INIT
05
02
I
FUNCTION
DONE
01
00
I
GO
UNIT
SEL
INT
ENS
CP -1509
Figure 3-1 RXCS Format (RXll)
Description
Bit No.
o
Go - Initiates a command to RXOI. This is a write-only bit.
1-3
Function Select - These bits code one of the eight possible functions described in Paragraph
3.3 and listed below. These are write-only bits.
Function
Code
Fill Buffer
Empty Buffer
Write Sector
Read Sector
Not used
Read Status
Write Deleted Data Sector
Read Error Register
000
001
010
011
100
101
110
111
4
Unit select - This bit selects one of the two possible disks for execution of the desired
function. This is a write-only bit. Unit 0 is physically the left-hand unit in the rack.
5
Done - This bit indicates the completion of a function. Done will generate an interrupt
when asserted if Interrupt Enable (RXCS bit 6) is set. This is a read-only bit.
6
Interrupt Enable - This bit is set by the program to enable an interrupt when the RXOI has
completed an operation (Done). The condition of this bit is normally determined at the time
a function is initiated. This bit is cleared by Initialize and is a read/write bit.
7
Transfer Request - This bit signifies that the RXll needs data or has data available. This is a
read-only bit.
8-13
Unused
3-2
Bit No.
Descrip tion
14
RXll Initialize - This bit is set by the program to initialize the RXl1 without initializing all
of the devices on the Unibus. This is a write-only bit.
CAUTION
Loading the lower byte of the RXCS will also load the upper
byte of the RXCS.
Upon setting this bit in the RXCS, the RXll will negate Done and move the head position
mechanism of drive 1 (if two are available) to track O. Upon completion of a successful
Initialize, the RXOI will zero the Error and Status register, set Initialize Done, and set RXES
bit 7 (DRV RDY) if unit 0 is ready. It will also read sector 1 of track 1 on drive O.
15
Error - This bit is set by the RXOI to indicate that an error has occurred during an attempt
to execute a command. This read-only bit is cleared by the initiation of a new command or
an Initialize (paragraph 3.6).
3.2.2 RXDB - Data Buffer Register (177172)
This register serves as a general purpose data path between the RXOI and the interface. It may represent one of four
RXOI registers according to the protocol of the function in progress (paragraph 3.3).
This register is read/write if the RXOI is not in the process of executing a command; that is, it may be manipulated
without affecting the RXOI subsystem. If the RXOI is actively executing a command, this register will only accept
data if RXCS bit 7 (TR) is set. In addition, valid data can only be read when TR is set.
CAUTION
Violation of protocol in manipulation of this register may
cause permanent data loss.
3.2.2.1 RXTA - RX Track Address (Figure 3-2) - This register is loaded to indicate on which of the 115 8 tracks a
given function is to operate. It can be addressed only under the protocol of the function in progress (paragraph 3.3).
Bits 8 through 15 are unused and are ignored by the control.
15
14
13
12
11
10
09
07
08
I
06
05
04
03
02
01
00
0
J
~--------------_v~--------------~
NOT USED
0- 114 8
CP-l:110
Figure 3-2 RXTA Format (RXll)
3.2.2.2 RXSA - RX Sector Address (Figure 3-3) - This register is loaded to indicate on which of the 328 sectors a
given function is to operate. It can be addressed only under the protocol of the function in progress (paragraph 3.3).
Bits 8 through 15 are unused and are ignored by the control.
15
14
13
12
11
10
09
07
08
I
J
0
06
I
0
05
I
04
03
02
01
00
0
....
1-32 8
NOT USED
CP-l:1n
Figure 3-3 RXSA Format (RXl1)
3-3
3.2.2.3 RXDB - RX Data Buffer (Figure 3-4) - All information transferred to and from the floppy media passes
through this register and is addressable only under the protocol of the function in progress (paragraph 3.3).
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
00
NOT USED
CP-1512
Figure 34 RXDB Format (RXll)
3.2.2.4 RXES - RX Error and Status (Figure 3-5) - This register contains the current error and status conditions
of the drive selected by bit 4 (Unit Select) of the RXCS. This read-only register can be addressed only under the
protocol of the function in progress (paragraph 3.3). The RXES is located in the RXDB upon completion of a
function.
15
14
13
12
11
10
09
08
I
07
06
DRV
DO
ROY
04
05
\
I
NOT USED
03
02
01
10
PAR
00
I I
eRe
NOT USED
CP -1513
Figure 3-5 RXES Format (RXll)
RXES bit assignments are:
Description
Bit No.
o
CRC Error - A cyclic redundancy check error was detected as information was retrieved
from a data field of the diskette. The RXES is moved to the RXDB, and Error and Done are
asserted.
Parity Error - A parity error was detected on command or address information being
transferred to the RXOI from the Unibus interface. A parity error indication means that
there is a problem in the interface cable between the RXOI and the interface. Upon
detection of a parity error, the current function is terminated; the RXES is moved to the
RXDB, and Error and Done are asserted.
2
Initialize Done - This bit is asserted in the RXES to indicate completion of the Initialize
routine which can be caused by RXOI power failure, system power failure, or programmable
or Unibus Initialize.
3-5
Unused
6
Deleted Data Detected - During data recovery, the identification mark preceding the data
field was decoded as a deleted data mark (paragraph 1.3.3).
34
Bit No.
7
Description
Drive Ready - This bit is asserted if the unit currently selected exists, is properly supplied
with power, has a diskette installed correctly, has its door closed, and has a diskette up to
speed.
NOTE I
The Drive Ready bit is only valid when retrieved via a Read
Status function or at completion of Initialize when it indicates
status of drive O.
NOTE 2
If the Error bit was set in the RXCS but Error bits are not set
in the RXES, then specific error conditions can be accessed via
a Read Error Register function (Paragraph 3.3.7).
3.3 FUNCTION CODES
Following the strict protocol of the individual function, data storage and recovery on the RX11 occur with careful
manipulation of the RXCS and RXDB registers. The penalty for violation of protocol can be permanent data loss.
A summary of the function codes is presented below:
000
001
010
011
100
101
110
111
Fill Buffer
Empty Buffer
Write Sector
Read Sector
Not used
Read Status
Write Deleted Data Sector
Read Error Register
The following paragraphs describe in detail the programming protocol associated with each function encoded and
written into RXCS bits 1-3 if Done is set.
3.3.1 Fill Buffer (000)
This function is used to fill the RXOI buffer with 128 8-bit bytes of data from the host processor. Fill Buffer is a
complete function in itself; the function ends when the buffer has been fIlled. The contents of the buffer can be
written onto the diskette by means of a subsequent Write Sector function, or the contents can be returned to the
host processor by an Empty Buffer function.
RXCS bit 4 (Unit Select) does not affect this function, since no diskette drive is involved. When the command has
been loaded, RXCS bit 5 (Done) is negated. When the TR bit is asserted, the first byte of the data may be loaded
into the data buffer. The same TR cycle will occur as each byte of data is loaded. The RXOI counts the bytes
transferred; it will not accept less than 128 bytes and will ignore those in excess. Any read of the RXDB during the
cycle of 128 transfers is ignored by the RXl1.
3.3.2 Empty Buffer (001)
This function is used to empty the internal buffer of the 128 data bytes loaded from a previous Read Sector or Fill
Buffer command. This function will ignore RXCS bit 4 (Unit Select) and negate Done.
3-5
When TR sets, the program may unload the first of 128 data bytes from the RXDB. Then the RXll again negates
TR. When TR resets, the second byte of data may be unloaded from the RXDB, which again negates TR. Alternate
checks on TR and data transfers from the RXDB continue until 128 bytes of data have been moved from the RXDB.
Done sets, ending the operation and initiating an interrupt if RXCS bit 6 (Interrupt Enable) is set.
NOTE
The Empty Buffer function does not destroy the contents of
the sector buffer.
3.3.3 Write Sector (010)
This function is used to locate a desired track and sector and write the sector with the contents of the internal sector
buffer. The initiation of this function clears bits 0, I, and 6 of RXES (CRC Error, Parity Error, and Deleted Data
Detected) and negates Done.
When TR is asserted, the program must move the desired sector address into the RXDB, which will negate TR. When
TR is again asserted, the program must load the desired track address into the RXDB, which will negate TR. If the
desired track is not found, the RXll will abort the operation, move the contents of the RXES to the RXDB, set
RXCS bit 15 (Error), assert Done, and initiate an interrupt i"f RXCS bit 6 (Interrupt Enable) is set.
TR will remain negated while the RXOI attempts to locate the desired sector. If the RXOI is unable to locate the
desired sector within two diskette revolutions, the RXll will abort the operation, move the contents of the RXES
to the RXDB, set RXCS bit 15 (Error), assert Done, and initiate an interrupt if RXCS bit 6 (Interrupt Enable) is set.
If the desired sector is successfully located, the RXll will write the 128 bytes stored in the internal buffer followed
by a 16-bit CRC character that is automatically calculated by the RXOI. The RXll ends the function by asserting
Done and initiating an interrupt if RXCS bit 6 (Interrupt Enable) is set.
NOTE I
The contents of the sector buffer are not valid data after a
power loss has been detected by the RXOI. The Write Sector
function, however, will be accepted as a valid function, and
the random contents of the buffer will be written, followed by
a valid CRC.
NOTE 2
The Write Sector function does not destroy the contents of
the sector buffer.
3.3.4 Read Sector (OIl)
This function is used to locate a desired track and sector and transfer the contents of the data field to the J,lCPU
controller sector buffer. The initiation of this function clears bits 0, 1, and 6 of RXES (CRC Error, Parity Error,
Deleted Data Detected) and negates Done.
When TR is asserted, the program must load the desired sector address into the RXDB, which will negate TR. When
TR is again asserted, the program must load the desired track address into the RXDB, which will negate TR.
If the desired track is not found, the RXl1 will abort the operation, move the contents of the RXES to the RXDB,
set RXCS bit 15 (Error), assert Done, and initiate an interrupt if RXCS bit 6 (Interrupt Enable) is set.
3-6
TR and Done will remain negated while the RX01 attempts to locate the desired track and sector. If the RX01 is
unable to locate the desired sector within two diskette revolutions after locating the presumably correct track, the
RX11 will abort the operation, move the contents of the RXES to the RXDB, set RXCS bit 15 (Error), assert Done,
and initiate an interrupt if RXCS bit 6 (Interrupt Enable) is set.
If the desired sector is successfully located, the control will attempt to locate a standard data address mark or a
deleted data address mark. If either mark is properly located, the control will read data from the sector into the
sector buffer.
If the deleted data address mark was detected, the control will assert RXES bit 6 (DD). As data enters the sector
buffer, a CRC is computed, based on the data field and CRC bytes previously recorded. A non-zero residue indicates
that a read error has occurred. The control sets RXES bit 0 (CRC Error) and RXCS bit 15 (Error). The RX11 ends
the operation by moving the contents of the RXES to the RXDB, sets Done, and initiates an interrupt if RXCS bit 6
(Interrupt Enable) is set.
3.3.5 Read Status (l 01)
The RX11 will negate RXCS bit 5 (Done) and begin to assemble the current contents of the RXES into the RXDB.
RXES bit 7 (Drive Ready) will reflect the status of the drive selected by RXCS bit 4 (Unit Select) at the time the
function was given. All other RXES bits will reflect the conditions created by the last command. RXES may be
sampled when RXCS bit 5 (Done) is again asserted. An interrupt will occur if RXCS bit 6 (Interrupt Enable) is set.
RXES bits are defined in Paragraph 3.2.2.
NOTE
The average time for this function is 250 ms. Excessive use of
this function will result in substantially reduced throughput.
3.3.6 Write Sector with Deleted Data (110)
This operation is identical to function 010 (Write Sector) with the exception that a deleted data address mark
precedes the data field instead of a standard data address mark (paragraph 1.3.3.2).
3.3.7 Read Error Register Function (111)
The Read Error Register function can be used to retrieve explicit error information provided by the pCPU controller
upon detection of the general error bit. The function is initiated, and bits 0-6 of the RXES are cleared. Out is
asserted and Done is negated. The controller then generates the appropriate number of shift pulses to transfer the
specific error code to the Interface register and completes the function by asserting Done. The Interface register can
now be read and the error code interrogated to determine the type of failure that occurred (paragraph 3.6).
NOTE
Care should be exercised in use of this function since, under
certain conditions, erroneous error information may result
(Paragraph 3.5).
3.3.8 Power Fail
There is no actual function code associated with Power Fail. When the RX01 senses a loss of power, it will unload
the head and abort all controller action. All status signals are invalid while power is low.
When the RX01 senses the return of power, it will remove Done and begin a sequence to:
1.
Move drive 1 head position mechanism to track O.
2.
Clear any active error bits.
3-7
3.
Read sector 1 of track 1 of drive 0 into the sector buffer.
4.
Set RXES bit 02 (Initialize Done) (paragraph 3.2.2.4) after which Done is again asserted.
5.
Set Drive Ready of the RXES according to the status of drive O.
There is no guarantee that information being written at the time of a power failure will be retrievable. However, all
other information on the diskette will remain unaltered.
A method of aborting a function is through the use of RXCS bit 14 (RXll Initialize). Another method is through
the use of the system Initialize signal that is generated by the PDP-II RESET instruction, the console START key,
or system power failure.
3.4 PROGRAMMING EXAMPLES
3.4.1 Read Data/Write Data
Figure 3-6 presents a program for implementing a Write, Write Deleted Data, or a Read function, depending on the
function code that is used. The first instructions set up the error retry counters, PTRY, CTRY, and STRY. The
instruction RETRY moves the command word for a Write, Write Deleted Data, or Read into the RXCS.
The set of three instructions beginning at the label 1$ moves the sector address to the RX 11 after Transfer Request
(TR) , which is bit 7, has been set. The three instructions beginning at the label 2$ move the track address to the
RXll after TR has been set. The group of instructions beginning at the label 3$ looks for the Done flag to set and
checks for errors.
An error condition, indicated by bit 15 setting, is checked beginning at ERFLAG. If bit 0 is set, a CRC error has
occurred, and a branch is made to CRCER. If bit 1 is set, a parity error has occurred, and a branch is made to
PARER. If neither of the above bits is set, a seek error is assumed to have occurred and a branch is made to
SEEKER, where the system is initialized. In the case of a Write function, the sector buffer is refilled by a JMP to
FILLBUF. In the case of a Read function, a JMP is made to EMPBUFF.
In each of the PAR, CRC, and SEEK routines, the command sequence is retried ten times by decrementing the
respective retry counter. If an error persists after ten tries, it is a hard error. The retry counters can be set up to retry
as many times as desired.
NOTE
A Fill Buffer function is performed before a Write function,
and an Empty Buffer function is performed after a Read
function.
3.4.2 Empty Buffer Function
Figure 3-7 shows a program for implementing an Empty Buffer function. The first instruction sets the number of
error retries to ten. The address of the memory buffer is placed in register RO, and the Empty Buffer command is
placed in the RXCS. Existence of a parity error is checked starting at instruction 3$. If a parity error is detected, the
Empty Buffer command is loaded again. If an error persists for ten retries, the error is considered hard.
3-8
1
2
3
,
,THE f'OI.I.OWING IS THE 'U(l1 SUNDARD DEVICE ADORUS AND VECTDII ADOIIUS
4
5
6
7
8
9
111
11
12
13
14
15
16
17
18
19
2111
21
22
23
24
25
26
27
28
29
3111
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
5111
51
52
54
55
I
17717111
177172
177172
177172
177172
,
~~E W~~~~~W ~~1 T~ D~I.~~igR~:; i ~C O~X~~:6E ~f' .~~~0~1I2~2C~~H:E~~~~~~TS
:
S
A
Of' 'IIOGIIAH
Il.0CATION lECTOR) Of' TIIACI< "T" (THE CONTENTS or ,1II0CIIIAH I.OCATION TIIACK)
I
IIIU,III.
0011181116
111111111814
11112767
11112767
11112767
17777111
17777111
117773
11100321
111'111314
11181318
STARTI
MOV
MOV
MOV
I
''--111.
111.
'-111.
pTRY
CTRY
STillY
;
~~~l :h:~T~~u~9~~TEII
I
lUI< IItrlllY COUNTI:III
'WRITE. WRITE DEI.ETED DATA. oR IIIUD
I
I BITS 4 THRU 1 of' PROGRAM 1.0CATIoN CoMMAND OoNUIN THI: 'UNCTlON
I
I BIT 4 • 1 MEANS UNIT 1 ( • • MUNI UNIT ')
I
I BITS 3 THRU 1 IS THE COMMAND ( 4 • WIllITE. ,4 • W"ITE DEI.ETED DATA, 6 • "UD)
I
"IIIU22
1316167
Jlllnlll6
17714,
RETRY I
MOV COMMAND. MXCS
I UNIT. (WRITE, WIIITE DEI.ETlD DATA,
all
IIUD)
I
I WA IT F'OR THE
I
illll1II83111
~11101113"
1110111836
1fIl,767
111111177'
116767
lSI
177134
0J0214
177126
TRANsrEH MEQUEST '1.4(:1 THEN TIIANSF'ER THE 'ECTOR ADDIIESS
TSTB RXCS
BEQ lS
MOVB SECTOR, MXU
I
I WA I T F'OR THE TRANSF'EH REQUEST F'I.AO THEN TRANSF'ER THE TIIACI< ADDRU'
I
01110144
111111011151
,,,,'111852
ln767
11"177'
116767
032767
U1II8611
0111111166
"U,7111
""111874
I11III111,,76
1111115767
02111111111
01111111111"
111111"11116
11311111111
11"1116
"01"14
21 :
17712'"
"1!I0262
['",111111411
177112
1711112
301774
1771114
III~IIII1IIII"
'6
6'
il3276?
1332761
11101404
"'~"""3
01HH'"2
17711164
17'1"'"
Tsn RICCS
BEQ 21
MOVB TRACK. RX14
I
I THE SECTOR AND TMACI< ADDRESSES HAVE IEEN TR'NsF'ERIIED TO TIoIE RII81
I
I WSA IT f'OR THE DoNE F'I.AIi AND CIoIECI< roR ANY EIllRoRS
I
IIF' THE "UNeT I ON HAS COMPl.tTED suCCtss'UI.I. Y (No ERROR HAG) THEN HAI.T
I
31 I
BIT 'DONEB IT. AXCS
SET'
BEQ 3'
TUT F'OR TWE ERROR F'I.AG
TST RXCS
BNE ERf'LAG
aNE I" AN ERROR HAS aCCUIIEO
OK • COMPI.UEO
HAl. T
I THE ERROR f'LAG IS SET
I
I THE CONTENTS oF' THE HICES IS THE: ERROR STATUI
I
THEN SOMt TYPE OF' stEI< EIIROR oCCURtD
IIF' THE RXES BITS 1 AND 111 •
CIIC ERIIOR HAl OCCUREO
II" THE RXES BIT • • 1 THEN
, All I Ty ERROR HAS OCCURED
IIF' THE RXES BIT 1 • 1 THEN
~~gT U~~~I. T~~E D8~~E f'~~~G
ERF'I.AGI BIT
BEQ
BIT
BEQ
13, RXES
SEEK
'2, R)(ES
CRC
TEST rOR CRC AND 'AR I TV ERROIIS
NOT A 'MIITY OR CRC CMUSTJ II!: A SEEK
TEST F'DR P'RPY ERRD"
NOT A 'ARlTY ERROR tMUIT~ IE A CRC
I
I A PAR ITY ERROR HAS oCCURED
I
IINCREMENT AND TEST THE PARITY ERROR RETillY CoUNTER PROGRAM I.OCATION " "TIIY ..
I
lAND RETIIY THE" COMMAND" UNTIl. TIoI£ PARITY ERROR IIIEeOYERS
I
,
'OR UNT II. THE pTRY COUNTER OVEII'I.OWS To
0011112111
00111124
00111126
ilU261
001336
IIIUIIIIlI'I
INC pTRY
INE RETRY
HAl. T
ilCJ02(!2
RETRY THE COMMAND
HAIID P.R I TIl ERROR
I
,
I A CRC ERROR HAS oCCUHED
II NCREMENT AND TEST THE CRC ERIIOR IIETRV CDUNTER PROGRAM LoCATION " CTRV "
I
I AND RETRY THE COMMAND UNT I L. THE CAC UROR RECOVER'
I
'DR UNT I I. THE CTRY COUNTER OVEAf'1.0W, To
111""'13111
"111111134
1""136
IIIU1H!
"""267
","1332
,,""'1110111
il12767
IIIU146
00111152
"""1'4
""'267
001323
III UIII III
°
CRC I
INC CTAY
BNE RETRY
HAL. T
I THE ERROR F'LAG IS SET
"""174
""""""
1I1J6
107
108
UJ9
COMMANO IT &lUS REG IITU
DATA IUrf'EII REG liTER
IEC'OIll ADD"ESS RCCISTU
TRACIC ADDRESS IllEaUTER
[111110111 ITA TUS REG UTEIII
RXCS'l7717111
RXD"177172
RXS"177172
RXT A'177172
RXEhl77172
57
58
59
61
62
63
64
65
66
67
68
69
70
71
12
13
14
75
76
77
18
19
80
81
82
83
84
85
86
81
88
89
91
92
93
94
95
96
97
98
99
UIII
111)1
U2
1"3
11114
U5
,ABS
,PROGRAMM I NG EXAMPLES 'OR THE IIXU/RXll 'I.EX 18LE IIISKE;TTE
",11111116111
17111122
RETRY THE ODMMAND
CIIC EIIROR
IiA!D.
: THE ERROR IS CNon A "AR ITY ERROR A~D II eNoT] A CRC ERROR
I
SEEI< EIIROR
I THEREF'ORE IT MUST BE
I
AND 1 AilE III)
I (STATE 0" RXCS lilTS
I
SEEK:
INITIAL.IIE
MOV UNIT, R)(lll!
; INCREMENT AND TEST THE SEtK ERRoR RETRY COUNTER ""oCRAM I.OCA TI ON " ITIIY "
I
I AND RETIIY THE COMMAND UNTIl. THE SEEIC ERIIOR "ECoVEIII
I
lOR UNT II. THE CTRY COUNTER oVE"f'L.OWS To III
I
INC STRY
aNE RETRy
"tfRY THE COMMAND
HAL T
!oIARD lEEK ERROII
Figure 3-6 RXll Write/Write Deleted Data/Read Example
3-9
160
161
162
163
164
165
166
167
168
169
170
171
172
,THE
""'111~4~
0011125111
00111~54
;/l12767
2112700
id16767
1777713
001!llil56
~''''054
17671116
(Wn4~
I
FOR A TRANSFER REQUEST
,
IPIHOR TO TESTIN G THE ERROR
0U262
0U266
0"""270
00111276
1"'767
001014
2132767
001771
r~AG BEro~E
TRANsrERRING OATA TO THE PROGRAMS
eoM~LETIoN
or THE EH,TY BUrrER COMMAND
r~AG
TSTB RXCS
EI.OO~I
~MI
TtST rOR TRANSFER REQUEIT 'I.AO
INE Ir TRANsrER REOUEST '~AG IS SET
TEIT rOR DONE rl.4G
lEO UNTI~ THE CONE rl.AG lET'
EMPTY
BIT 'CONEBIT, RXCS
aEQ EI.OOP
176672
I
;THE DONE 'LAG IS SET
,
iTEST FOR ANY ERRoRS (oNLY ERROR poSSlal.E IS A PARITY ERRoR)
0U30G1
001113':14
UIII306
il0,767
001001
00"00111
176664
1$T Rxes
BNE 11
HALT
NO ERRORI • OK •
COM'~ETE
IINcrEMENT AND TEST THE PARITY ERROR RETRY PAOGRAM
~oCATIoN
i
I
lAND RCTRY THE CoMMANO
UNTI~
" ,TRY "
THE ERROR RECOVERS
I
00111 31GI
IilU314
,,"'111316
""'267
0013"
00""00
('100012
,lOR
UNTIL THE
CUNTER oVERrl.oWS TO "
INC PTRY
aNE ESETUP
HALT
1$:
,
,iTHE
~TRY
RETRY TO EM~TY THE StCTOR BurrER
PARITY ERROR
~ARO
TRANsrER REQUEST
'~AG
Is sET
ITRANSFER DATA TO THE PROGRAM
,
206
207
208
209
210
21'1
212
213
01il0326
210"331B
210111332
000000
215
216
000334
176646
,THE rOLLOWING 3 PROGHAM
~2100~0
~a0000
~OCATIO~S
,IPROGRAM
LOCATION" COMMAND "
(4),
COMMAND I
CONTAl~S T~E
i
I
,~ROGRAM
218
LOCATION "
,
,'PROGRAM LOCATION"
00111336
00000111
SECTORI m
0011134111
1il01il"1il1il
TRACK I
00011140
2J40000
1il1il0342
DONEBITI4111
INIT.41111U1II
BUFF'ER',
,IBurrER+ZIIlIil
,END
,
,
S~CTOR
1il1il054~
(6),
OR EMPTY BurreR (2)
" CoNTAINS THE SECTOR AODREIS (1 TO 32
OCTA~)
; 1 TO 32 OCTAL
THACK " CONTAINS
I
"
T~E
TRACK ADDRESS (' TO 114 oCTAl.)
III TO 114 OCTAL
I
00011101
COMMAND TO BE ISSUED VIA THE LCO lOT
4, 14. 6, OR 2 • (GO Bn 1 • 1)
IPROGRAM EQUIVALENTS
226
EAROR RETRY COUNTERS
WRITE DELETED DATA (14), Oill READ
I
217
T~E
i
I
01il0000
ARE
'ARITY ERROR RETRY COUNTtR
; CRC ER~OR RETRy COUNTER
i SEEK ERROR RETRY COUNTER
F'TRy:
CTRy:
STRY:
IWRITE
DATA surrER rRoM THE RXll SECTOR BurrER
~RV~L~~~B. '(HIIl)+
EM~TYI
I
214
228
229
231il
231
232
REQUIRED TO
I
0""321B
00111324
227
~~OTOCO~
8 TRYS TO EMPTY THE lECTOR BurrER
'ROHCRAHI OATA BurrER
ISSUE THE COMMAND
'WAIT FOA A DONE rLAG TO INDICATE THE
116730
1il00756
219
220
221
222
223
224
225
or
EXAM'~!
,
191
192
193
194
195
196
197
198
199
200
201
202
203
204
IS A ~HOGRAMMING
SECTOR BurrER or 12a a-SIT BYTES
IDATA BurrER rRoN THE RXllll SECTOA BurrER
181
182
183
164
165
186
187
188
189
190
,
T~E
EENTRYI MOV '-1111. ~TRY
CSETUPI MOV 'BurrER, Hili
MOV COMMAND, RXCS
,IWAIT
173
174
175
176
177
178
179
180
rO~~OWING
,
IEMpTY
Figure 3-7 RX11 Empty Buffer Example
3-10
If no error is indicated, the program looks for the Transfer Request (TR) flag to set. The Error flag is retested if TR
is not set. Once TR sets, a byte is moved from the RXII sector buffer to the core locations of BUFFER. The
process continues until the sector buffer is empty and the Done bit is set.
3.4.3 Fill Buffer Function
Figure 3-8 presents a program to implement a Fill Buffer function. It is very similar to the Empty Buffer example.
3.5 RESTRICTIONS AND PROGRAMMING PITFALLS
A set of restrictions and programming pitfalls for the RXII is presented below.
I.
Depending on how much data handling is done by the program between sectors, the minimum interleave
of two sectors may be used, but to be safe a three-sector" interleave is recommended.
2.
If an error occurs and the program executes a Read Error Register function (111), a parity error may
occur for that command. The error status would not be for the error in which the Read Error Register
function was originally required.
3.
The DRV SEL RDY bit is present only at the time of a Read Status function (101) for both drives, and
after an Initialize, depending on the status of drive O.
4.
It is not required to load the Drive Select bit into the RXCS when the command is Fill Buffer (000) or
Empty Buffer (010).
5.
Sector Addressing: 1-26 (No sector 0)
Track Addressing: 0-76
6.
A power failure causing the recalibration of the drives will result in a Done condition, the same as
fmishing reading a sector. However, during a power failure, RXES bit 2 (Initialize Done) will set.
Checking this bit will indicate a power fail condition.
7.
Excessive usage of the Read Status function (101) will result in drastically decreased throughput,
because a Read Status function requires between one and two diskette revolutions or about 250 ms to
complete.
3.6 ERROR RECOVERY
There are two error indications given by the RXII system. The Read Status function (paragraph 3.3.5) will assemble
the current contents of the RXES (paragraph 3.2.2), which can be sampled to determine errors. The Read Error
Register function (paragraph 3.3.7) can also be used to retrieve explicit error information. The RX11 Interface
register can be interrogated to determine the type of failure that occurred.
A list of error codes is presented on the following page.
NOTE
A Read Status function is not necessary if the DRV RDY bit is
not going to be interrogated, because the RXES is in the
Interface register at the completion of every function.
3-11
Octal
Code
0010
0020
0030
0040
0050
0060
0070
0110
0120
0130
0140
0150
0160
0170
0200
0210
Error Code Meaning
Drive 0 failed to see home on Initialize.
Drive 1 failed to see home on Initialize.
Found home when stepping out 10 tracks for INIT.
Tried to access a track greater than 77.
Home was found before desired track was reached.
Self-diagnostic error.
Desired sector could not be found after looking at 52 headers (2 revolutions).
More than 40 J,JS and no SEP clock seen.
A preamble could not be found.
Preamble found but no I/O mark found within allowable time span.
eRe error on what we thought was a header.
The header track address of a good header does not compare with the desired track.
Too many tries for an IDAM (identifies header).
Data AM not found in allotted time.
eRe error on reading the sector from the disk. No code appears in the ERREG.
All parity errors.
3-12
111
112
113
11"
115
116
117
118
119
120
121
122
123
12.
125
126
127
128
129
130
131
132
133
13.
135
136
137
138
139
1.0
141
142
143
aTHE
IS A ~HOGRA~MING
EXA~'~E
or
T~E PROTOCO~ ~EQUIRED
TO
THE SECTOR BUfrER WITH 128 a-S!T B¥TES
IrI~L
a
a NOTEI THE DATA To rlL~ THE SECTO~ BU,rER CAN BE AISEMB~ED IN CORE IN THE
I
EVEN ADDRESSES SYTES or 128 WORDS OR IN BOTH BYTES or •• WORDS
0.8156
001164
0el178
012767
012700
016767
177773
000342
~001.0
0.01.2
176772
I
8 TR¥S TO
'I~L THE SECTO~ BurfER
DATA Bu,rER
ISIUE THE COMMAND
fENTRYI MOV '-10, PTRY
SETUPI MOV 'BurrER, RI
MOV COMMAND, Rxes
,aHAIT
'ROG~AMS
rOR A TRANSfER HEQUEST
f~AG
IErORE TRANsrERRING DATA fROM THE PROGRAMS
a
10ATA BUrfER TO THE RXll SECTOR Bu,rER
I
,lHAIT fOR
a~RIoR
l
e00176
000202
000204
000212
10,767
'01414
032767
001771
LOO~I
176766
A DONE rLAT TO INDICATE THE
TO TESTING THE ERROR
0~00'"
0' THE
rlL~
BurrER COMMAND
TEST rOR T_ANSrER REQUEST '~AG
ItO Ir TRANsrER REQUEST r~AG SET
TEIT rOR TWE DONE r~AG
lEO UNTI~ THE DONE r~AG StTS
TSTB RKCS
BIT 'DONEBIT, RXes
BEQ LOOP
176756
COMP~ETloN
r~AG
l:IMl fll"L
a
ITHE DONE rLAG IS SET
,'TEST
rOR ANY ERRORS (ONLY ERROR
I
000214
000228
'00222
,"767
001001
0000'0
176750
I
145
146
l
lOR
I
0'022.
000238
000232
00'267
0013"
000000
000076
lSI
,ITHE
UNTI~
113067
00075'
176732
UNTI~
THE pTRY COUNTER
THE ERROR RECOVERS
OVE~rLOwS
INC PTRY
aNE SETU~
HALT
To •
RtTR¥ TO rl~L THE
~ARD ~'RITY ERRO~
SECTOR
8UrrE~
TRANsrER REQUEST rLAG IS SET
I
'0'23.
001241
Is A PARITY ERROR)
ANO TEST THE PARITY ERROR RETRY PROGRAM LOCATION" ,TRY "
lAND RETRY THE COMMANU
147
~OSSI!~E
TST RXCS
BNE 1$
HALT
,IINCREMENT
144
1.8
1.9
150
151
152
153
15"
155
156
157
158
rO~~OHING
a
,
fROM THE PROGRAMS CAT. SUrfER TO THE RXll
BurrER
,ITRANsrERMOveDATA'(RI)+,
fILL:
HXOS
;
DATA Bu,rER IS 6.. WoRDS IN
SECTO~
PROG~AMS
BR LOOP
Figure 3-8 RXII Fill Buffer Example
3-13
~ENGTH
CHAPTER 4
RX8E INTERFACE
PROGRAMMING INFORMATION
The RX8E interface allows two modes of data transfer: 8-bit word length and 12-bit word length. In the 12-bit
mode, 64 words are written in a diskette sector, thus requiring two sectors to store one page of information. The
diskette capacity in this mode is 128,128 12-bit words (l,001 pages). In the 8-bit transfer mode, 128 8-bit words
are written in each sector. Disk capacity is 256,256 8-bit words, which is a 33 percent increase in disk capacity over
the 12-bit mode. Eight-bit mode must be used for generating IBM-compatible diskettes, since 12-bit mode does not
fully pack the sectors with data. The hardware puts in the extra Os. Data transfer requests occur 23 ps after the
previous request was serviced for 12-bit mode (18 ps for 8-bit mode). There is no maximum time between the
transfer request from the RXOI and servicing of that request by the host processor. This allows the data transfer to
and from the RXOI to be interrupted without loss of data.
4.1 DEVICE CODES
The eight possible device codes that can be assigned to the interface are 70-77. These device codes define address
locations of a specific device and allow up to eight RX8E interfaces to be used on a single PDP-8. These multiple
device codes are also shared with other devices. Depending on what other devices are on the system, the RX8E
device code can be selected to avoid conflicts. (Refer to the PDP-8 Small Computer Handbook for specific device
codes.)
The device codes are selected by switches according to Table 4-1. These switches control AC bits 6-8, while AC bits
3-5 are fixed at 1s. The device code is initially selected to be 70. Switches 7 and 8 are not connected and will not
affect the device selection code. The switches are all located on a single DIP switch package that is located on the
M8357 RX8E interface board.
Table 4-1
Device Code Switch Selection
o (OFF)
Device
Code
SI
S2
S3
S4
S5
S6
S7
S8
77
76
75
74
73
72
71
70
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
4-1
1 (ON)
c:J
c::::J
c:::::J
83
[:=J
84
81
82
c:::J
85
[=:J
86
c::::J
87
[:=J
88
4.2 INSTRUCTION SET
The RX8E instruction set is listed below and described in the following paragraphs.
lOT
Mnemonic
67xO
67xI
67x2
67x3
67x4
67x5
67x6
67x7
LCD
XDR
STR
SER
SDN
INTR
INIT
Description
No Operation
Load Command, Clear AC
Transfer Data Register
Skip on Transfer Request Flag, Clear Flag
Skip on Error Flag, Clear Flag
Skip on Done Flag, Clear Flag
Enable or Disable Disk Interrupts
Initialize Controller and Interface
4.2.1 Load Command (LCD) - 67xl
This command transfers the contents of the AC to the Interface register and clears the AC. The RXOI begins to
execute the function specified in AC 8, 9, and 10 on the drive specified by AC 7. A new function cannot be initiated
unless the RXOI has completed the previous function. The command word is defined as shown in Figure 4-1.
00
01
02
03
04
05
06
07
08
09
FUNCTION
10
11
NOT
USED
8/12
DRV
SEL
CP-1514
Figure 4-1 LCD Word Format (RX8E)
The command word is described in greater detail in Paragraph 4.3 .1.
4.2.2 Transfer Data Register (XDR) - 67x2
With the Maintenance flip-flop cleared, this instruction operates as follows. A word is transferred between the AC
and the Interface register. The direction of the transfer is governed by the RXOI, and the length of the word
transferred is governed by the mode selected (8-bit or I2-bit). When Done is negated, executing this instruction
indicates to the RXOI:
l.
That the last data word suppUed by the RXOI has been accepted by the PDP-8, and the RXOI can
proceed, or
2.
That the data or address word requested by the RXOI has been provided by the PDP-8, and the RXOI
can proceed.
A data transfer (XDR) from the AC always leaves the AC unchanged. If operation is in 8-bit mode, AC 0-3 are
transferred to the Interface register but are ignored by the RXOI. Transfers into the AC are I2-bit jam transfers
when in I2-bit mode. When in 8-bit mode, the 8-bit word is ORed into AC 4-11, and AC 0-3 remain unchanged.
When the RXOI is done, this instruction can be used to transfer the RXES status word from the Interface register to
the AC. The selected mode controls this transfer as indicated above.
4·2
4.2.3 STR - 67x3
This instruction causes the next instruction to be skipped if the Transfer Request (TR) flag has been set by RXO 1
and clears the flag. The TR flag should be tested prior to transferring data or address words with the XDR
instruction to ensure the data or address has been received or transferred, or after an LCD instruction to ensure the
command is in the Interface register. In cases where an XDR follows an LCD, the TR flag needs to be tested only
once between the two instructions. (See programming example in Paragraph 4.5.1.)
4.2.4 SER - 67x4
This instruction causes the next instruction to be skipped if the Error flag has been set by an error condition in the
RXOI and clears the flag. An error also causes the Done flag to be set (paragraph 4.3.6).
4.2.5 SDN - 67x5
This instruction causes the next instruction to be skipped if the Done flag has been set by the RXOI indicating the
completion of a function or detection of an error condition. If the Done flag is set, it is cleared by the SDN
instruction. This flag will interrupt if interrupts are enabled.
4.2.6 INTR - 67x6
This instruction enables interrupts by the Done flag if AC 11
= 1. It disables interrupts if AC
11
= O.
4.2.7 INIT - 67x7
The instruction initializes the RXOI by moving the head position mechanism of drive 1 (if drive 1 is available) to
track O. It reads track 1, sector 1 of drive o. It zeros the Error and Status register and sets Done upon successful
completion of Initialize. Up to 1.8 seconds may elapse before the RXOI returns to the Done state. Initialize can be
generated programmably or by the Omnibus Initialize.
4.3 REGISTER DESCRIPTION
Only one physical register (the Interface register) exists in the RX8E, but it may represent one of the six RXOI
registers described in the following paragraphs, according to the protocol of the function in progress.
4.3.1 Command Register (Figure 4-2)
The command is loaded into the Interface register by the LCD instruction (paragraph 4.2.1).
00
01
02
03
04
05
06
07
08
09
FUNCTION
10
11
NOT
USED
8/12
DRV
SEL
Figure 4-2 Command Register Format (RX8E)
4-3
CP-1514
The function codes (bits 8,9, 10) are summarized below and described in Paragraph 4.4.
Code
Function
000
001
010
011
100
101
110
111
Fill Buffer
Empty Buffer
Write Sector
Read Sector
Not used
Read Status
Write Deleted Data Sector
Read Error Register
The DRV SEL bit (bit 7) selects one of the two drives upon which the function will be performed:
AC7=0
AC 7 = I
Select drive 0
Select drive 1
The 8/12 bit (bit 5) selects the length of the data word.
AC 5=0
AC 5 = 1
Twelve-bit mode selected
Eight-bit mode selected
The RX8E will initialize into 12-bit mode.
4.3.2 Error Code Register (Figure 4-3)
Specific error codes can be accessed by use of the Rear Error Register function (111) (paragraph 4.4.7). The specific
octal error codes are given in Paragraph 4.7.
00
~
01
____
02
~~
03
____
04
~J\~
05
06
07
08
09
10
11
_ _ _ _ _ _ _ _ _ _ _ __ _
NOT USED
ERROR
CODE
CP-1010
Figure 4-3 Error Code Register Format
The Maintenance bit (M bit) can be used to diagnose the RX8E interface under off-line and on-line conditions. The
off-line condition exists when the BC05L-15 cable is disconnected from the RXO 1; the on-line condition exists when
the cable is connected to the RXOl.
If an LCD lOT (I/O Transfer) is issued with AC 4 = 1, the Maintenance flip-flop is set. When the Maintenance
flip-flop is set, the assertion of RUN on fol/owing XDR instructions is inhibited, and all data register transfers (XDR)
are forced into the AC. The Maintenance bit allows the Interface register to be written and read for maintenance
checks. The Maintenance flip-flop is cleared by Initialize or by an LCD lOT with AC 4 = o.
The following paragraphs describe more explicitly how to use the Maintenance bit in an off-line mode.
The contents of the interface buffer cannot be guaranteed immediately following the first LCD lOT, which sets the
Maintenance flip-flop. However, successive LCD lOTs will guarantee the contents of the Interface register. The
contents of the Interface register can then be verified by using the XDR lOT to transfer those contents into the AC.
4·4
In addition, the Maintenance flip-flop directly sets the Skip flags, which will remain set as long as the Maintenance
flip-flop is set. Skipping in these flags as long as the Maintenance flip-flop is set will not clear the flags. Setting and
then clearing the Maintenance flip-flop will leave the Skip flags in a set condition. The skip lOTs can then be issued
to determine whether or not a large portion of the interface skip logic is working correctly.
The Maintenance flip-flop can also be used to determine if the interface is capable of generating an interrupt on the
Omnibus. The Maintenance flip-flop is set, thus causing the Done flag to set. The Interrupt Enable flip-flop can be
set by issuing an INTR lOT with AC bit 11 = 1. The combination of Done and Interrupt Enable should generate an
interrupt.
The Maintenance flip-flop can also be used to test the INIT lOT. The Maintenance flip-flop is set and cleared to
generate the flags, and INIT lOT is then executed. If execution of INIT lOT is internally successful, all of the flags
and the Interrupt Enable flip-flop should be cleared if they were previously set.
In the on-line mode, use of the Maintenance bit should be restricted to writing and reading the Interface register.
The same procedure described to write and read the Interface register in the off-line mode should be implemented in
the on-line mode. Additional testing of the RX8E in the on-line mode should reference the appropriate circuit
schematics. Exiting from the on-line Maintenance bit mode should be finalized by an initialize to the RXOI.
4.3.3 RXT A - RX Track Address (Figure 44)
This register is loaded to indicate on which of the 77 tracks a given function is to operate. It can be addressed only
under the protocol of the function in progress (paragraph 4.4). Bits 0 through 3 are unused and are ignored by the
control.
00
~
01
02
I I
______
~
03
____
04
I
05
06
07
08
09
10
11
I I
0
~J
NOT USED
0- 114 8
CP-l~16
Figure 44 RXTA Format (RX8E)
4.3.4 RXSA - RX Sector Address (Figure 4-5)
This register is loaded to indicate on which of the 26 sectors a given function is to operate. It can be addressed only
under the protocol of the function in progress (paragraph 4.4). Bits 0 through 3 are unused and are ignored by the
control.
00
01
02
03
04
05
06
07
08
09
10
11
1- 32 8
NOT USED
CP-l~17
Figure 4-5 RXSA Format (RX8E)
4-5
4.3.5 RXDB - RX Data Buffer (Figure 4-6)
All information transferred to and from the floppy media passes through this register and is addressable only under
the protocol of the function in progress. The length of data transfer is either 8 or 12 bits, depending on the state of
bit 5 of the Command register when the LCD lOT is issued (paragraph 4.3.1).
00
01
02
03
04
05
06
07
08
12 BIT
8 or 12 BIT
MODE ONLY
MODE
09
10
11
CP-HI18
Figure 4-6 RXDB Format (RX8E)
4.3.6 RX Error and Status (Figure 4-7)
The RXES contains the current error and status conditions of the selected drive. This read-only register can be
accessed by the Read Status function (101). The RXES is also available in the Interface register upon completion of
any function. The RXES is accessed by the XDR instruction. The meaning of the error bits is given below.
00
01
02
03
I
v
04
05
DRV
ROY
DO
06
I
07
08
.....
NOT USED
I
I
09
10
ID
PAR
11
I I
CRC
NOT USED
CP-l~19
Figure 4-7 RXES Format (RX8E)
Bit No.
Description
11
CRC Error - The cyclic redundancy check at the end of the header or data field has
indicated an error. The header or data must be considered invalid; it is suggested that the
data transfer be retried up to ten times, as most data errors are recoverable (soft). (See
Chapter 6).
10
Parity Error - When status bit 10 = 1, a parity error has been detected on command and
address information being transferred to the RXOI pCPU controller from the RX8E
interface. Upon detection of a parity error, the current function is terminated, the RXES
status word is moved to the Interface register, and the Error and Done flags are set. The
function can be retried to determine if the parity error is a soft or hard error. A parity error
indication means that there is a problem in the interface cable between the RXOI and the
interface.
9
Initialize Done - This bit indicates completion of the Initialize routine. It can be asserted
due to RXOI power failure, system power failure, or programmable or bus Initialize. This bit
is not available within the RXES from a Read Status function.
4-6
Bit No.
Description
5
Deleted Data (DD) - In the course of reading data, a deleted data mark was detected in the
identification field. The data following will be collected and transferred normally, as the
deleted data mark has no further significance within the RXOI. Any alteration of fIles or
actual deletion of data due to this mark must be accomplished by user software. This bit will
be set if a successful or unsuccessful Write Deleted Data function is performed.
4
Drive Ready - This bit is asserted if the unit currently selected exists, is properly supplied
with power, has a diskette installed properly, has its door closed, and has a diskette up to
speed.
NOTE 1
This bit is only valid for either drive when retrieved via a Read
Status function or for drive 0 upon completion of an Initialize.
NOTE 2
If the Error bit was set in the RXCS but Error bits are not set
in the RXES, then specific error conditions can be accessed via
a Read Error Register function.
4.4 FUNCTION CODE DESCRIPTION
RX8E functions are initiated by means of the Load Command lOT (LCD). The Done flag should be tested and
cleared with the SDN instruction in order to verify that the RX8E is in the Done state prior to issuing the LCD
instruction. Upon receiving an LCD instruction while in the Done state, the RX8E enters the Not Done state while
the command is decoded. Each of the eight functions summarized below requires that a strict protocol be followed
for the successful transfer of data, status, and address information. The protocol for each function is described in the
following sections, and a summary table is presented below.
AC
Octal
8
9
10
Function
0
2
4
6
10
12
14
16
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
Fill Buffer
Empty Buffer
Write Sector
Read Sector
Not Used
Read Status
Write Deleted Data Sector
Read Error Register
NOTE
AC bit 11 is assumed to be 0 in the above octal codes, since
AC bit 11 can be 0 or 1.
4.4.1 Fill Buffer (000)
This function is used to load the RXOI sector buffer from the host processor with 64 12-bit words if in 12-bit mode
or 128 8-bit words if in 8-bit mode. This instruction only loads the sector buffer. In order to complete the transfer
to the diskette, another function, Write Sector, must be performed. The buffer may also be read back by means of
the Empty Buffer function in order to verify the data.
4-7
Upon decoding the Fill Buffer function, the RXOI will set the Transfer Request (TR) flag, signaling a request for the
first data word. The TR flag must be tested and cleared by the host processor with the STR instructions prior to
each successive XDR lOT (paragraph 4.2.3). The data word can then be transferred to the Interface register by
means of the XDR lOT. The RXOI next moves the data word from the Interface register to the sector buffer and
sets the TR flag as a request for the next data word. The sequence above is repeated until the sector buffer has been
loaded (64 data transfers for I2-bit mode or 128 data transfers for 8-bit mode). After the 64th (or I28th) word has
been loaded into the sector buffer, the RXES is moved to the Interface register, and the RXOI sets the Done flag to
indicate the completion of the function. It is, therefore, unnecessary for the host processor to keep a count of the
data transfers. Any XDR commands after Done is set will result in the RXES status word being loaded in the AC.
The sector buffer must be completely loaded before the RX8E will set Done and recognize a new command. An
interrupt would now occur if Interrupt Enable were set.
4.4.2 Empty Buffer (001)
This function moves the contents of the sector buffer to the host processor. Upon decoding this function, RXES bits
10 and 11 (parity Error and CRC Error) are cleared, and the TR flag is set with the first data word in the Interface
register. This TR flag signifies the request for a data transfer from the RX8E to the host processor. The flag must be
tested and cleared, then the word can be moved to the AC by an XDR command. The direction of the transfer for
an XDR command is controlled by the RXOl. The TR flag is set again with the next word in the Interface register.
The above sequence is repeated until 64 words (128 bytes if 8-bit mode) have been transferred, thus emptying the
sector buffer. The Done flag is then set after the RXES is moved in the Interface register to indicate the end of the
function. An interrupt would now occur if Interrupt Enable were set.
NOTE
The Empty Buffer function does not destroy the contents of
the sector buffer.
4.4.3 Write Sector (010)
This function transfers the contents of the sector buffer to a specific track and sector on the diskette. Upon
decoding this function, the RX8E clears bits 10 and 11 (parity Error and CRC Error) of the RXES and sets the TR
flag, signifying a request for the sector address. The TR flag must be tested and cleared before the binary sector
address can be loaded into the Interface register by means of the XDR command. The sector address must be within
the limits 1-328.
The TR flag is set, signifying a request for the track address. The TR flag must be tested and cleared, then the binary
track address may be loaded into the Interface register by means of the XDR command. The track address must be
within the limits 0-1148.
The RXOI tests the supplied track address to determine if it is within the allowable limits. If it is not, the RXES is
moved to the Interface register, the Error and Done flags are set, and the function is terminated.
If the track address is legal, the RXOI moves the head of the selected drive to the selected track, locates the
requested sector, transfers the contents of the sector buffer and a CRC character to that sector, and sets Done. Any
errors encountered in the seek operation will cause the function to cease, the RXES to be loaded into the Interface
register, and the Error and Done flags to be set. If no errors are encountered, the RXES is loaded into the Interface
register and only the Done flag is set.
NOTE
The Write Sector function does not destroy the contents of
the sector buffer.
4-8
4.4.4 Read Sector (011)
This function moves a sector of data from a specified track and sector to the sector buffer. Upon decoding this
function, the RX8E clears RXES bits 5, 10, 11 (Deleted Data, Parity Error, eRe Error) and sets the TR flag,
signifying the request for the sector address. The flag must be tested and cleared. The sector address is then loaded
into the Interface register by means of the XDR command. The TR flag is set, signifying a request for the track
address. The flag is tested and cleared by the host processor, and the track address is then loaded into the Interface
register by an XDR command. The legality of the track address is checked by the RXOI. If illegal, the Error and
Done flags are set with the RXES moved to the Interface register, and the function is terminated. Otherwise, the
RXOI moves the head to the specified track, locates the specified sector, transfers the data to the sector buffer,
computes and checks CRC for the data. If no errors occur, the Done flag is set with the RXES in the Interface
register. If an error occurs anytime during the execution of the function, the function is terminated by setting the
Error and Done flags with RXES in the Interface register. A detection of CRe error results in RXES bit 11 being set.
If a deleted data mark was encountered at the beginning of the desired data field, RXES bit 5 is set.
4.4.5 Read Status (l 01)
Upon decoding this function, the RXOI moves the RXES to the RX8E Interface register and sets the Done flag. The
RXES can then be read by the Transfer Data Register command (XDR). The bits are defined in Paragraph 4.3.6.
NOTE
The average time for this function is 250 ms. Excessive use of
this function will result in substantially reduced throughput.
4.4.6 Write Deleted Data Sector (110)
This function is identical to the Write Data function except that a deleted data mark is written prior to the data field
rather than the normal data mark (Paragraph 1.3.3.2). RXES bit 5 (Deleted Data) will be set in the RX8E Interface
register upon completion of the function.
4.4.7 Read Error Register Function (Ill)
The Read Error Register function can be used to retrieve explicit error information upon detection of the Error flag.
Upon receiving this function, the RXOI moves an error code to the Interface register and sets Done. The Interface
register can then be read via an XDR command and the code interrogated to determine which type of failure
occurred (paragraph 4.7).
NOTE
Care should be exercised in use of this function because, under
certain conditions, erroneous error information may result
(Paragraph 4.6).
4.4.8 Power Fail
There is no actual function code associated with Power Fail. When the RXOI senses a loss of power, it will unload
the head and abort all controller action. All status signals are invalid while power is low.
When the RXOI senses the return of power, it will remove Done and begin a sequence to:
1.
Move drive 1 head position mechanism to track O.
2.
Clear any active error bits.
3.
Read sector 1 of track 1 of drive O.
4.
Set Initialize Done bit of the RXES, after which Done is again asserted.
4-9
There is no guarantee that information being written at the time of a power failure will be retrievable. However, all
other information on the diskette will remain unaltered.
A method of aborting an incomplete function is with the INIT lOT (paragraph 4.2.7).
4.5 PROGRAMMING EXAMPLES
4.5.1 Write/Write Deleted Data/Read Functions
Figure 4-8 presents a program for implementing a Write, Write Deleted Data, or a Read function with interrupts
turned off (lOF). The first three steps preset the PTRY, CTRY, and STRY retry counters, which are set at ten
retries but can be changed to any number. Starting at RETRY, the program tests for 8- or 12-bit mode, type of
function, and drive. Once the command is loaded, the program waits in a loop for the controller to respond with
Transfer Request (TR). When TR is set, the sector address is loaded and the AC is cleared. The program loops while
waiting for the controller to respond with another TR. When TR is reset, the track address is loaded, and the AC is
cleared again. The program loops to wait for the Done condition.
When the Done flag is set, the program checks for an error condition, indicated by the Error flag being set. If the
AC = 0000, then the error is a seek error; if bit 10 of the AC is set, the error is a parity error; and if bit 11 of the AC
is set, the error is a CRC error. Error status from the RXES is saved and tested to determine the error (paragraph
4.3.6). The RXES will not include the Select Drive Ready bit. If a parity error is detected, the program increments
and tests the PTRY retry counter. If a parity error persists after ten tries, it is considered a hard error. If ten retries
have not occurred, a branch is made to RETRY and the sequence repeated.
If the Parity Error bit of the RXES is not set, then the program tests to see if the CRC Error bit is set. If a CRC error
is detected, the program increments and tests the CTRY retry counter. If a CRC error persists after ten retries, it is
considered a hard error. If ten retries have not occurred, a branch is made to RETRY and the sequence repeated.
A seek error is assumed if neither a eRC nor a parity error is detected. An Initialize (lNIT) instruction is performed
(paragraph 4.2.7). During a Write or Write Deleted Data function, the sector buffer must be refilled, because INIT
will cause sector 1 of track 1 of drive 0 to be read, which will destroy the previous contents of the sector buffer. The
instruction sequence for a Fill Buffer function is not included in Figure 4-8, but is presented in Figure 4-10. After
the system has been initialized, the program increments and tests the STRY retry counter. If a seek error persists
after ten tries, it is considered a hard error. If ten retries have not occurred, a branch is made to RETRY and the
sequence repeated.
4.5.2 Empty Buffer Function
Figure 4-9 shows a program for implementing an Empty Buffer function with interrupts turned off (lOF). The first
instruction sets the number of retries at ten. A 2 is set in the AC to indicate an Empty Buffer command, and the
command is loaded. When TR is set, the program jumps to EMPTY to transfer a word to the BUFFER location. A
jump is made back to loop to wait for another TR. This process continues until either 64 words or 128 bytes have
been emptied from the sector buffer. When Done is set, the program tests to see if the Error bit is set. If the Error
bit is set, the program retries ten times. If the error persists, a hard parity error is assumed, indicating a problem in
the interface cable.
4.5.3 Fill Buffer Function
Figure 4-10 presents a program to implement a Fill Buffer function. It is very similar to the Empty Buffer example.
4-10
IPROGRAMMING EXAMPLES F'OR THE RX8/RXIII1
1
2
3
4
I
ITHE
F'O~~OWING
ITHE STANDARD lOT DEVICE CODE IS 6'''-
6
7
I
67"1
671112
671113
6704
67(115
671116
671117
8
9
10
11
.. 2
13
14
18
lIN
71
?7
78
79
80
81
82
83
84
85
86
87
88
89
90
1112~4
"205
12'4
32"
1254
3256
12'4
3257
START.
OR 12 BIT MODE
TAO
DCA
TAO
OCA
TAO
DCA
KM1I1l
PTRy
KM1i1J
CTRY
KM1I1l
STRY
I
-1'"
IPARITY
~ETRV
COUNTER
ICRC RETRY COUNTER
ISEEK RETRY COUNTER
I
IWRITE. WRITE DELETED DATA. OR READ
I
"207
1261/1
1261
1/12U
1262
671111
"2~6
"211
RETRY,
TAO MODE
TAO COMMAND
II1l IF" 12-SlT. 1"11l IF" a-BIT
4 I' WRITE. 14 I' WRITE OE~ETED
ICATA, OR 6 IF' READ
I I!! I' UNIT Il, 2m IF' UNIT 1
IIOT 67X1 TO LOAD THE COMMAND
I
TAO UNIT
L.CO
I
IWAIT F'OR THE TRANSF'ER REQUEST F'I.AG THEN TRANSfER THE StOTOR ADDRtSS
I
"212
0213
111214
11l21'
0216
/I or 67)(3 TO
IHAIT ro~ TRANSF'ER REQUEST F'~AG
1 TO J2(OCTAL)
IIOT TO L.OAD SECTOR
ICI.A 8ECAuse; lOT XOR DOESN'T
ST~
671113
5212
1263
6702
721:1111
JMP .-1
TAO SECTOR
XOR
I
C~A
I
IWAIT F'OR THE TRANsrER REQUEST FLAG THEN TRANsre;R THE TRACK ADDRESS
I
111217
1:1221:1
111221
111222
111223
671:13
5217
1264
6702
7200
STR
JMP •• 1
TAO TRACK
XOR
/I OT 67X3 TO
IWA I T ro~ TR ANSF'ER REQUEST
0 TO 114(OCTAL)
/lOT TO L.OAD TRACK
ICI.~ BECAUSE lOT XOR DOESN'T
C~A
/THE: SECTOR AND TRACK ADDRESSES HAVE ilEEN TRANSF'[RR~D TO THE RXU VIA THE XOR lOT
I
I
IWAIT F'OR THE DONE F'I.AG AND CHECK F'OR ANY ERRORS
I
IIF' THE rUNCTION HAS
I
111224
111225
111226
111227
COM"~ETEO SUCCES!iF'UL~V
SON
JMP .-1
SER
6705
'224
6704
7402
(NO [RROII!
"~'G'
THEN HALT
/I OT 6'X' TO
IWAIT '011 DONE F'L.AG
IIOT 67X4 SAMPLES ERROR
I OK - COM"L.I!TED
H~ T
r~AG
I
ITHE ERROR
F'~A~
IS SET
I
/THE CONTENTS OF' THE
TRA~SF'ER
REGISTEH IS THE ERROR STATUS
I
IIF" TRANSF'ER REGISTER BITS 111l. ANC 11
IIF' TRANSF'ER REGISTER BIT 11 • 1 THEN
IIF' TRANSF'!':R REG I STER BIT 11/1 • 1 THEN
I
111230
0231
(11232
111233
111234
"235
XOR
DCA
CL.1.
AND
SNA
JM"
6702
3265
7305
121265
769111
5241
~ THEN SOME TV"E oF' SEEK tRRoR HAS OCCUREO,
CRC ERROR HAS OCOUREO.
PARITY ERROR HAS OCCURED
IGE:i CONTENTS OF' TR (tRROR STATUS)
IANO SAVE
ASTATUS
CLA lAC RAI.
ASTATUS
CLA
TCRC
I
2
ITUT rOR "ARITY ERROR
ISKIP lr PARITV ERROR
INOT • PARITY ERROR - MAVBE CRC
I
IA PARITV ERROR HAS OCCUREO
I
IINCREMENT AND TEST THE PARITY ERROR HETRY COUNTER PlI!oGRAH L.OCHION .. "TRY"
I
lAND RETRY THE" COMMAND" UNTIL THE PAHITY ERROR RECOVERS
I
lOR
UNTI~
I
"236
111237
111240
2255
'206
741212
THE "TRV COUNTER OVERF'L.OWS TO 121
lSi! PTRY
JMP RETRY
IRETRV THE COMMANC
IHARD "ARITY ERROR
H~T
I
/THE ERROR F'L.AG IS SET BUT THE ERHOR IS NOT A "ARITV ERROR
91
92
93
94
95
96
97
98
8
I
"2(11111
1112:111
1112(112
1112(113
55
72
73
74
75
76
I RED
I
I
22
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
~EQU
II.OCAT I ON SECTOR, OF' TRACK "T" (THE CONTENTS OF' PROGRAM LOCAT I ON TRACK)
20
21
51
I NG I S A PROGRAMM I NG EXAMPLE OF' THE "ROTOCOL
ITO WRITE. WRITE DELETED DATA, OR READ AT SECTOR "S" ITHE: CONTENTS OF' "ROGRAM
19
52
53
54
F'O~LOW
I
17
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
SER~6704
SDN-67(11'
I NTR.6'1116
INIT.6'I1J'
/THE
16
/lOT TO LOAD HIE COMMANC. (AC) IS THE COMMAND
IIOT TO LOAD OR REAC THE TRANSF'ER REGISTER
IIOT TO SKIP ON A TRANSF'ER R~QUEST F'~AG
IIOT TO SKIP ON AN ERROR F'I.AG
IIOT TO SKIP ON THE DONE F'LAG
I lAC) " (II INi[RRUPT ENAB~E OF'F'I (AC) - 1 MEANS ON
IIOT TO INITIi!LIAE THE RX8/RXI/I1 SUBSYSTEM
I.CD-6701
XDR.67(112
STRII670J
I
15
33
DISKETTE
I
5
23
24
25
26
27
28
29
3(11
31
32
~'LE)(IBL[
ARE RXllll lOT COOE DEF'INITIONS
I
/TEST rOR A CRC ERROR
111241
111242
(11243
111244
7301
<1265
76'"
52'"
I
TCRC,
CL~ CLA lAC
AND ASTATUS
SNA CL.l
JM" SEEK
I 1
ITEn '011 A ORC ERROR
ISKIP IF' A CIIC ERROR
INOT A CIIC - MUST aE A SEEK
Figure 4-8 RX8E Write/Write Deleted Data/Read Example (Sheet 1 of 2)
4-11
99
1fiHIi
101
102
103
104
105
106
107
108
109
I
A CRC E:RROR HAS OCCUREO
I
IINCREME:NT AND TEST THE CRC ERROR RETHY COUNTE.R
lAND RETRY THE COMMAND UNTIL THE CRC t;RROR RECOVERS
I
lOR UNTIl. THE: CTRY COUNT!:R OVERFLOWS TO 0
I
0245
"246
"247
IS! CTRy
JM" RETRY
HL,T
2256
5206
7402
l10
IRETRY T~t COMMAND
IHARO CRC tR"OR
I
111
/THE ERROR FI.AG IS SET
112
I
ITHE ERROR IS eNOT] A PARITY ERROR AND IS CNOTl A CNC ERROR
113
114
115
I
116
117
118
I
I
I
119
120
121
122
123
124
125
126
127
128
129
ITHEREFORt IS MUST BE A StEI< ERROR
025"
671'"
(CONTENTS OF THE TRANSF'tR REGISTER elTS lrll, AND 11 • rill
SEtK,
IIOT 67X7 TO INITI'I.IAE
INIT
I
IINCREMtNT AND TEST THE StEI< ERROR RETRY COUNTER PROGRAM 1.0C'TION " STRY "
I
lAND RETRY THE COMMAND UNTIL, THt SEEt< tRROR RtCOVERS
I
lOR UNTIl. THE CrRY COUNTER OVERFt.OWS TO 0
I
0251
0252
"253
lSi! STRY
JM" RETRY
HLT
2257
5206
74"2
IRET"Y T~E COMMAND
IIiARO SEEK t"ROR
130
/THt f"01.1.0W I NG PROGRAM 1.0C ATIONS ARE Rl:F'ERENCtO WITH I N
131
I
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
16"
161
162
163
164
165
166
167
168
169
17'"
171
172
173
1.0CATION " CTRY "
~ROGRAM
I
"254
777"
T~ IS
EXAMfll.C
t<M1f/l,
I
ITHt FOl.1.0WING 3 PROGRAM 1.0CATIONS ARE THt ERROR RETRY COUNTl:RS
I
"255
0256
0257
0:11""
0000
l2I:1IrIIS
PTRY,
CTRy,
STRY,
IPARITV tRRO" RETRY COUNTER
ICRC ERROR RrTRY COUNTER
ISEEK ERROR IIIETRY COUNTER
I
IPROGRAM 1.0CATION " MODE" CONTAINS A " IF 12-81T
ICONTAINS A 1,,0 IF e-BIT MOOt
I
0260
0000
~10DE,
I
OR
~OO£,
0 OR 1110
I
IPROGRAM 1.0CATION
I
IWRITE
(4),
n
COMMAND" CONTAINS THt COMMAND TO BE ISSUED VIA THE LCD lOT
WRITE OtLtTED DATA (14), OR READ (6), OR [MPTY BUFFER
I
121261
0000
COMMAND,
I
",
(a)
14, OR ., OR
I
IPROGRAM 1.0CATION " UNIT" CONTAINS THE UNIT DESIGNATION
I
I!,INIT 0 (0', OR UNIT 1 (2'"
I
0262
0000
UNI T,
I
I
IPROGRAM 1.0CATION " SECTOR" CONTAINS THE SECTOR
I
0263
0:1100
SECTOR,
0, OR 2rIJ
AOO~ESS
(1 TO 32 OCTAl.)
liTO 32 OCTAL
III
I
IPROGRAM 1.0CATION " TRACK " CONTAINS
T~E:
TRACt< ADDRESS (I! TO 114 aCTAl.'
I
0264
011100
TFIACK,
I
II TO :1.14 OOTAI.
I
IPROGRAM 1.0CA TI ON " ASH TUS " CO NT AI NS THE
CONTE~T!I
I
IAT
TH~
DETtCTION OF AN ERROR (ERROR FL,AG •
1) WHIC~
or
T~E
TRANSFER REG I STER
CORRESPONDS TO THt
I
IF.:RROR STATUS
I
I
•
0 Ir stEt< ERROR, 1 Ir CRC F.:RROR,
~
IF PARITY ERROR
I
ASTATUS,
ISTATUS AT
E~ROR
Figure 4-8 RX8E Write/Write Deleted Data/Read Example (Sheet 2 of 2)
4-12
ITHE
228
229
rO~~OW1NG
I
23~
I~MPTY
231
I
232
233
234
235
236
237
238
239
24~
I
121312
121313
121314
~31'
"316
12131'
12132~
1254
3255
1377
311lU
1260
1261
EENTRY, TAD
DCA
ESETUP, TAO
DCA
TAO
TAD
~CO
67~1
241
I
IWAIT rOR A DONE
284
285
EM~TY
BurrER COMMAND
P~IOR
ITE5T rOR TR r~AG
ITR NOT SET, TEST rOR DONE
ITR r~AG SET
ITE5T rOR OO~E r~AQ
INOT TA, OR OONE YET
r~AG
r~AG
IS SET
ITEST roR ANY [RRORS (ONLY ERROR POSSIBLE IS A PARITY ERROR)
121326
1lI32'
I
SER
67~4
'4"2
ITEST rOA THE ERROR
INO [RRD"S - OK
H~T
r~AG
I
IINCREMENT AND TEST THE PARITY ERROR RETRY PROGRAM LOCATION" PTRY "
I
lAND RETRY THE COMMAND UNTIL THE ERROR RECOVERS
I
lOR
UNTI~
I
1lI331l1
1lI3a
1lI332
THE PTRY COUNTER OVERFLOWS TO
lSI PTRy
22"
H~T
74~2
I
ITHE TRANsrER REQUEST
~
IRETRY TO EM_TY THE SECTOR BUFrER
IHARc 'ANITY ERROR
JMII' ESETUP
5314
r~AG
15 SET
I
ITRANsrER DATA TO THE PROGRAMS DATA BurrER rROM THE RX81 SECTOR BurrER
275
283
Or THE
I
274
281
282
COMP~ETION
JMP ELOOP
I
273
278
TO INDICATE THE
STR
ITHE OONE
267
279
28(11
r~AG
JMp EMPTY
SON
263
264
265
266
276
277
BErORE TRANsr£RRING DATA TO THE PROGRAMS
SKI'
256
272
r~AG
ITESTING THE ERROR rLAG
E~OOP,
271
8 TRYS TO EMPTY THE SECTOR BurrER
IPARITY tRRO~ RETRY COUNTER
IPROCRAMS DATA BurrER
IAUTO INOEX REGISTrR 1111
I 121 I' 12-B1T, 10"" lr 8 BIT
I 2 MEANS EM.TY BurrER
IIOr TO tssur THE COMMAND
I
I
27~
O~
10ATA BurFER FROM THE RXi2ll SECTOR BurfER
25~
268
269
REQUIRED TO
I
251
252
253
254
255
262
PROTOCO~
I
I
249
26~
Or
KM1"
PTRy
<BUFFER-l)
A10
MODE
COMMAND
IWAIT rOR A TRANsrER REQUEST
243
244
245
246
247
248
261
~XAM~~E
IEMPTY THE SECTOR BUrrER or 128 a-BIT BYTES (8 BIT MOOE)
242
257
258
259
15 A PROGRAMMING
THE SECTOR BurrER or 64 12-BIT WORD. (12 BIT MODE),
I
"333
21334
67""2
34U
1lI335
'321
"377
11l3?7
2J411l""
EMPTY,
XOR
DCA! AU
JMII' [LOOP
IrROM THe RX~l SECTOR BurrER
ITO THE 'ROGNAMS DATA BurrER
THE DONE F~AG SETS
I~OOP UNTI~
~AGE
ITHE
rOL~OWING
PROGRAM LOCATIONS ARE RfSERVEO rOR THE PROGRAMS DATA BurrER
I
BUrFER,
rIJ
*sur'ER+20rIJ
!Ii
Figure 4-9 RX8E Empty Buffer Example
4-13
TO
174
175
176
177
178
179
18111
181
182
183
184
185
186
187
188
189
19111
191
192
193
194
195
196
197
198
199
20111
21111
202
203
204
21115
206
207
21118
209
21111
211
212
213
214
215
216
217
218
ITHE
IS A PROGRAMMING
EXAMP~E
Or
REQUIRED TO
PROTOCO~
THE SECTOR BUrrER WITH 64 12-BIT WORDS (12 BIT MODE), OR
I
I~I~~
THE SECTOR BUrrER WITH 128 a-BIT BYTES (8 BIT MODE)
I
0111U
AlI1l1111iJ
12,4
3255
1377
31111r11
126Q)
61"1
rENTRY, TAO
DCA
SETUP, TAO
DCA
TAO
I
111266
r/J261
3273
r/J271
111272
3273
~CD
KM13
PTRy
(BUFrER-l)
A10
MoDE
e
TRVS TO rl~~ THE SECTOR
I~ARtTY £RRO~ RETRV COUNTER
I~ROGRAM' DATA BurrER
I
BurrER
IAUTO INOEX REGISTER 1"
" I' 12-BIT, lf11r/J IF e BIT
IIOT TO ISSUE THE COMMAND
I
I
IWAIT rOR A TRANSrER REQUEST
r~AG
BE~aRE
TRANsrERRING OATA FROM THE PROGRAMS
I
IDATA BurFER TO THE RXf1Il SECTOR BurFEH
I
IWAIT rOR A DONE
P~AG
TO
THE
I~DICATE
COMP~ETION
I
or
THE
rl~~
BUrFER COMMAND PRIOR TO
ITESTING THE ERROR rLAG
I
"274
0275
0276
3277
"30tl!
611113
,4U
LOOP,
6""
'2'"
STR
IT£5T rOR TR rLAG
ITR NOT lET, TEST rOR DONt
ITR n.AG SET
ITEST rOR DONE F~AG
INOT TR, OA OONE YET
SKI"
JM"
SON
JMP
'3"6
I
ITHE DONE
rn.~
~OOP
'~AG
r~AG
IS SET
I
ITEST rOR ANY ERRORS
(ON~Y
ERROR
POSSIB~E
IS A PARITV ERRoR)
I
r/J301
r/J302
6104
7""2
IT EST rOR THE ERROR
INO ERRORS • OK
r~AG
I
IINCREMENT AND TEST THE PARITY ERROR RETRY PROGRAM
~OCATloN
" PTRV "
I
lAND RETRy THE COMMAND UNTIL THE ERROR RECOVERS
I
lOR
UNTJ~
THE PTRY COUNTER OVERFLOWS TO 0
I
031113
0304
rlJ31ll5
lSI! PTRy
JM" SETUP
HL.T
2255
52'"
7402
219
22111
221
222
223
224
225
226
227
rO~~OWING
I
Irl~~
IRETRY TO rl~~ THE SECTOR surrER
IHARO PA~ITY ERROR
I
ITHE TRANS'ER REQUEST rL.AG IS SET
I
ITRANSrER DATA rROM THE PROGRAMS OATA BUFrER To THE RX01 SECTOR BU,rER
I
r/J306
031117
03H'J
3311
1410
67r/J2
72U
5274
rIL~,
TAO I AU
IVIA AUTO INDEX REGISTER 1Z
ITO THE ~Xf1Il SECTOR BU'FER
leLA BECAUSE lOT XOR DOESN'T
I~OOfl' UNTIL. THE CONE rL.AG SETS
XOR
C~A
JMfI' L.OOP
Figure 4-10 Fill Buffer Example
4-14
4.6 RESTRICTIONS AND PROGRAMMING PITFALLS
A set of 11 restrictions and programming pitfalls for the RX8E is presented below.
1.
When performing the following sequence of instructions, interrupts must be off.
[ E:-----SDN
JMP
(done)
(fill or empty buffer)
If interrupts are not off, the following sequence of events will occur. Assume interrupts are enabled and
the RX8E issues an interrupt request just before the SDN instruction. The SDN instruction will be
execu ted as the last legal instruction before the processor takes over. However, since the Done flag is
cleared by the SDN instruction, the processor will not find the device that issued the interrupt.
2.
The program must issue an SER instruction to test for errors following an SDN instruction.
3.
For maximum data throughput for consecutive writes or reads in 8-bit mode, interleave every three
sectors; in l2-bit mode, interleave every two sectors. (This of course depends on program overhead.)
4.
When issuing the lOT XDR at the end of a function to test the status, the instruction AND 377 must be
given, because the most significant bits (0-3) contain part of the previous command word.
5.
If an error occurs and the program executes a Read Error Register function (lll) (paragraph 4.4.7), a
parity error may occur for that command. The error code coming back would not be for the original
error in which the Read Error Register function was issued, but for the parity error resulting from the
Read Error Register function. Therefore, check for parity error with the Read Status function (l01)
before checking for errors with the Read Error Register function (lll).
6.
The SEL DRV RDY bit is present only at the time of the Read Status function (l01) for either drive, or
at completion of an Initialize for drive O.
7.
It is not necessary to load the Drive Select bit into the command word when the command is Fill Buffer
(000) or Empty Buffer (001).
8.
Sector Addressing: 1-26 or 1-328 (No sector 0)
Track Addressing: 0-76 or 1-1148
9.
If a Read Error Register function (l1 1) is desired, the program must perform this function before a
Read Status function (l01), because the content of the Error register is always mO,dified by a Read
Status function.
10.
The instructions STR, SDN, SER also clear the respective flags after testing, so that the software must
store these flags if future reference to them is needed after performing one of these instructions.
11.
Excessive use of the Read Status function (l01) will result in drastically decreased throughput, because a
Read Status function requires between one and two diskette revolutions or about 250 ms to complete.
4-15
4.7 ERROR RECOVERY
There are two error indications given by the RX8E system. The Read Status function (Paragraph 4.4.5) will assemble
the current contents of the RXES (paragraph 4.3.6), which can be sampled to determine errors. The Read Error
Register function (paragraph 4.4.7) can also be used to retrieve explicit error information.
The results of the Read Status function or the Read Error Register function are in the Interface register when Done
sets, indicating the completion of the function. The XDR lOT must be issued to transfer the contents of the
Interface register to the PDP-8's AC.
NOTE
A Read Status function is not necessary if the DRV RDY bit is
not going to be interrogated, because the RXES is in the
Interface register at the completion of every function.
The error codes for the Read Error Register function are presented below.
Octal
Code
0010
0020
0030
0040
0050
0060
0070
0110
0120
0130
0140
0150
0160
0170
0200
0210
Error Code Meaning
Drive 0 failed to see home on Initialize.
Drive 1 failed to see home on Initialize.
Found home when stepping out 10 tracks for INIT.
Tried to access a track greater than 77.
Home was found before desired track was reached.
Self-diagnostic error.
Desired sector could not be found after looking at 52 headers (2 revolutions).
More than 40 ps and no SEP clock seen.
A preamble could not be found.
Preamble found but no I/O mark found within allowable time span.
CRC error on what we thought was a header.
The header track address of a good header does not compare with the desired track.
Too many tries for an IDAM (identifies header).
Data AM not found in allotted time.
CRC error on reading the sector from the disk. No code appears in the ERREG.
All parity errors.
4-16
CHAPTER 5
THEORY OF OPERATION
This chapter presents a discussion of the hardware and pCPU firmware of the RX11 and RX8 Floppy Disk Systems.
This information, combined with the programming information and functional descriptions contained in Chapters 3
and 4, should give the reader a complete knowledge of the theory of operation of the RX11 and RX8 Floppy Disk
Systems.
The first section of this chapter describes the overall system block diagram and the signals that interconnect each of
the blocks. The second section presents a detailed block diagram and logic discussion of each of the system blocks.
The pCPU microprogram is discussed in Paragraphs 5.2.4 and 5.2.5.
5.1 OVERALL SYSTEM BLOCK DIAGRAM
The floppy disk system consists of four elements (Figure 5-1):
1.
Drive mechanics, which includes actuators and transducers (up to two per controller)
2.
Read/write electronics, which translates power levels between drive mechanics and control logic
3.
Microprogrammed controller, which includes all control logic.
4.
Bus interface, which translates between host processor bus protocol (Unibus or Omnibus) and RX01
data bus
o
RXOI
DATA BUS
M
N
I
B
U
DISK DRIVE
INTERFACE
READ/WRITE
ELECTRON ICS
S
f'CPU
CONTROLLER
OR
U
N
I
B
U
S
CP-HI20
Figure 5-1 Bus Structure
5-1
There are three levels of data transmission in the floppy disk system (Figure 5-1):
1.
Unibus for PDP-ll or Omnibus for PDP-8 for data transmission between bus interface and host
processor
2.
RXOI data bus for data transmission between the RXOI pCPU controller and the bus interface
3.
The disk drive interface for data and control information transmission between the read/write
electronics and the RXOI pCPU controller.
Signals between the read/write electronics and mechanical drive are analog signals used to control head motion and
sense diskette motion and position. The sections which follow describe the signals used in the three levels of data
transmission and the analog signals between the read/write electronics and mechanical drive.
5.1.1 Omnibus to RX8E Interface Signals
The RX8E interface communicates with the PDP-8 Omnibus via the signals shown in Figure 5-2 and described
below. These signals are further explained in the PDP-8 Small Computer Handbook.
.t.
A
K
DATA BUS (12)
~
~
'\
./
A_
V
:\..~
RXBE
INTERFACE
MEMORY DATA BUS (9)
TP3 H
0
M
N
I
B
U
S
TP4 H
INTERNAL 1/0 L
SKIP L
INT ROST L
CO,C!
INIT H
I/O PAUSE
...
?
CP-1521
Figure 5-2 Omnibus to RX8E Interface Signals
DATA BUS - Twelve parallel bits of data are transferred along a bidirectional bus for both input and output data
between the AC register in the processor and the Interface register in the RX8E interface.
MEMORY DATA BUS - This signal provides I/O transfer (lOT) instructions from memory to the RX8E interface.
TP3 H, TP4 H - These signals are used to clear the flag and clock the Interface register of the RX8E interface in
transferring data along the data bus.
INTERNAL I/O L - This signal is grounded by the RX8E interface selector decoder to inhibit decoding any internal
Omnibus I/O transfer (lOT) instructions. Failure to ground this line will result in long lOT timing.
SKIP L - An lOT checks the flag for a ONE state. If the flag is set, SKIP L is asserted and the address of the
program counter (PC) plus one is loaded into the Central Processor Memory Address (CPMA) register to implement a
skip.
5-2
INT RQST L - This signal is part of the interrupt structure of the Omnibus. It is the method by which the RX8E
interface signals the processor that it has data to be serviced.
CO, C1 - Signals CO and Cl determine the type of transfer between the RX8E interface and the processor. These
signals control the data path within the processor and determine if data is to be placed on the data bus or received
from the data bus. They are also used to develop the necessary load control signals required to load either the
accumulator (AC) or the program counter (PC) in the processor.
INIT H - INIT H is a signal used to clear all flags in the RX8E interface and initialize the RXO 1.
I/O PAUSE L - This signal is used to gate the RX8E select and operation codes into the programmed I/O interface
of the PDP-8 decoders.
5.1.2 Unibus to RXll Interface Signals
The RXII interface communicates with the PDP-II Unibus via the signals shown in Figure 5-3 and described below.
These signals are further explained in the PDP-11 Peripherals Handbook.
~
/
A
~
ADDRESS SIGNAL (18)
"\/
v
,...
A
~
~
DATA SIGNAL (16)
y
)
MSYN L
SSYN L
RXII
INTERFACE
U
N
I
B
U
S
NPR L
CI L
INIT
INTR L
SACK L
BBSY L
BR (7:4)
BG(7:4)
'III;
"
CP-1522
Figure 5-3 Unibus to RXll Interface Signals
ADDRESS (A Lines) - The 18 address lines are used by the CPU to select the device register addresses of the RXl1,
which are 177170 (RXCS) and 177172 (RXDB).
DATA (D Lines) - The 16 parallel data lines are used to transfer information in and out of the RXll interface.
MSYN L - This signal is the master synchronization control signal that is initiated by the RXl1 when it has control
of the Unibus for data transmission.
SSYN L - This signal is the slave synchronization control signal that is initiated by the RXll in response to an
MSYN L signal from the processor or another device that has control of the Unibus and is about to send data to the
RXl1.
5-3
NPR L - This signal from the processor will inhibit the RXll interface from issuing a bus grant.
NOTE
The RX 11 is not an NPR device.
Cl L - This bus signal is coded by the master device to control the slave in Data In mode (passing data to the
Unibus) if it is negated and Data Out mode (passing data from the Unibus) if it is asserted.
INIT L - This is the signal asserted by the processor when the START key on the console is depressed, when a
RESET instruction is executed, or when the power fail sequence occurs. This signal will initialize the RXll system.
INTR L - This signal is asserted by the RXl1 when it has bus control during an interrupt sequence. It directs the
processor to go to interrupt service routine.
SACK L - This signal is sent by the RXll to the processor in acknowledgment of Unibus control being transferred
to it. This signal inhibits further bus grants by the processor.
BBSY L - This is the signal sent by the RXll when asserting master control of the Unibus. This signal follows the
SACK L signal.
BR (7:4) - These four priority bus request lines are used by the RXII to request bus mastership. Each device of the
same priority level passes a grant signal to the next device on the line, unless it has requested bus control; in this
case, the requesting device blocks the signal from the following devices and assumes bus control.
BG (7:4) - These are four priority bus grant lines corresponding to the four request lines. The processor uses them
to respond to a specific bus request.
5.1.3 Interface to pCPU Controller Signals
The pCPU controller and RX8E or RXll interface communicate via the signals shown in Figure 5-4 and described
below.
DATAL
DONE L
TRANSFER REQUEST L
SHIFT L
JLCPU
CONTROLLER
OUT L
ERROR L
RX8E
OR
RXII
INTERFACE
RUN L
INIT L
12 BIT L
-(RX8E ONLY)
CP -1523
Figure 5-4 Interface to pCPU Controller Signals
INIT L - The RXOl will negate DONE L and move the head position mechanism of drive 1 (if it exists) to track o.
The RXOI will also read sector 1 of track 1 of drive 0 and then assert DONE L without error upon successful
completion of the function.
DONE L - Asserted low, DONE L indicates that there is no RXOI function in progress. Initiating any function will
cause DONE L to go false for the duration of that function. Attempting to initiate any function other than Initialize
while DONE L is false is illegal and may result in an error.
5-4
RUN L - RUN L initiates communication between interface and controller. RUN L, asserted while DONE L is true,
passes a command from interface to controller serially. DONE L will go false until the command has been executed
(or until Initialize is asserted). RUN L, asserted while DONE L is false, signals transfer of data to or from the
controller. All control lines to the controller must be stable 75 ns before RUN L is asserted.
OUT L - OUT L signals the direction in which the RXOI is prepared to transfer data. When OUT L is asserted, the
direction of transfer is from controller to interface. When OUT L is negated, the direction is from interface to
controller. OUT L is never asserted while DONE L is true, and OUT L is negated by Initialize.
TRANSFER REQUEST L (TR L) - The TR L line, with RUN L and OUT L, forms a bidirectional handshake set.
On transfers from controller to interface (OUT L asserted), TR L going true indicates that the next data element has
been transferred to the Interface register. The transfer of the following data element will be initiated by asserting
RUN L. This will negate TR L until the new data element has been assembled in the interface.
On transfers from interface to controller (OUT L negated), TR asserted indicates that the controller is prepared to
accept the next element of data. The arrival of the new data element will be signaled by assertion of RUN L.
Assertion of RUN L while TR L is negated is an error.
DATA L - DATA L is a bidirectional line for transfer of data to and from the controller. A parity bit is appended to
the serial data stream by the interface when the direction of the data transfer is into the controller. The controller
will interrogate the parity bit for validity.
SHIFT L - The SHIFT L pulse strobes information to or from the controller bit-by-bit.
1.
Interface to Controller Transfer - The transfer of either commands or data words begins with assertion
of RUN L. Following the assertion of RUN L, DONE L or TR L will be negated and a number of SHIFT
L pulses will occur. The number depends on the length of the data element to be passed. The first bit of
data (or command) must be stable when RUN L is asserted. The SHIFT L pulse width is 200 ns nominal.
SHIFT L pulses will not occur more often than every 400 ns. Subsequent bits of data may be brought up
on the trailing edge of SHIFT L. DONE L or TR L will be reasserted following the last SHIFT L pulse.
2.
Controller to Interface Transfer - The assertion of TR L indicates the controllers readiness to transfer
data. Assertion of RUN L will negate TR L and initiate a train of SHIFT L pUlses. The data is to be
sampled on the leading edge of SHIFT L and is valid only while SHIFT L is asserted. TR L will be
reasserted at the end of each element of data. DONE L will be asserted following transfer of the last
elemen t of data in a block.
12 BIT L - This signal is asserted by the interface to controller and determines the number of shift pulses generated
by the controller for each byte transferred.
Signal 12 BIT L asserted will produce 12 SHIFT L pulses for data transfer between the interface and controller upon
the assertion of RUN L. Signal 12 BIT L negated will produce eight SHIFT L pulses for data transfer between the
interface and controller upon the assertion of RUN L. This line must remain asserted throughout the entire data
transfer. When data is transferred, the most significant bit is transferred first.
NOTE
Signal 12 BIT L is only asserted by the RX8E interface for
PDP-8 12-bit words. It is never asserted by the RX 11 interface.
ERROR L - This is an error summary bit generated by the controller that sets when any error is detected
(Paragraphs 3.2.1 and 4.3.6). The detection of ERROR L stops all controller action and asserts DONE L and the
Error flag. This line is cleared by INIT L or the initiation of a new function.
5-5
S.l.4 J-lCPU Controller to Read/Write Electronics Signals
The J-lCPU controller and read/write electronics communicate via the signals shown in Figure 5-5 and described
below.
WRITE GATE H
ERASE GATE H
LOW CUR H
LD HD H
WRITE DATA H
R/W
ELECTRON ICS
HD STEP H
HDDIROUTH
p.CPU
CONTROLLER
SEL TRK 0 H
SELINDEXH
RAW DATA L
SEL 1 H
DC LO L
CP-1524
Figure 5-5 J-lCPU Controller to Read/Write Electronics Signals
LOW CUR H - This signal is asserted by the controller to select the lower of two write current levels when operating
on a track above 43. As the head moves closer to the center of the disk, the bit density increases as linear velocity
decreases, necessitating a reduction in write current.
WRITE DATA H - This signal conveys the complete data stream to the read/write electronics at TTL logic levels.
Each transition on this line results in a flux reversal on the disk.
In general, the pattern will be one clock transition every 4 J-lS with an intervening transition between two successive
clocks to represent a data one and no intervening transition to represent a data zero. It should be noted that the data
content of this stream cannot be inferred from its instantaneous logic level, but only from the pattern of its
transitions (paragraph 1.3.2).
RA W DATA L - This signal conveys the complete data stream recovered from the diskette at TTL logic levels. It
includes a regular pattern of clock transitions which the controller will separate from the data transitions. As above,
the data content is in the pattern of transitions rather than the absolute level at any instant of time (paragraph
1.3.2).
SEL 1 H - This signal uniquely selects one of the two possible diskette drives. The assertion of this line will select
logical drive 1 for use. Unit 0 is physically the left-hand unit in the rack.
WRITE GA TE H - This signal is asserted by the controller to enable the selected write drivers. This level must be
asserted prior to the beginning of the data field to be written and is negated after the last bit of the data field. This
timing is completely under microprogram control.
ERASE GA TE H - This signal is used in conjunction with WRITE GATE H to enable the tunnel erase drivers. It is
asserted and negated after the assertion of WRITE GATE H, with timing determined by the microprogrammed
controller.
LD HD H - This signal is asserted by the controller to hold the media against the selected head.
5-6
HD STEP L - This signal is asserted twice by the controller to change head position by one track in a direction
determined by signal HD DIR OUT H. The maximum step rate is 10 ms per step. Minimum pulse width is 200 ns.
HD DIR OUT H - This signal determines the direction in which the head will move in response to an HD STEP L
signal. If HD DIR OUT H is unasserted, the heads will travel toward the center of the disk (IN), increasing the track
address. If HD STEP L is asserted when HD DIR OUT H is asserted, the heads will travel toward the outside edge of
the disk (OUT), decreasing the track address.
SEL TRK 0 H - This signal is asserted by the selected drive to indicate that its head is positioned over track O.
SEL INDEX H - This signal is asserted by the selected drive to indicate that the hard index hole has been detected.
This occurs once per revolution and is used by the control to time operations and detect "up to speed." This pulse is
400}.ls minimum width.
DC LO L - This signal is asserted by an Initialize signal from the controller to the drives.
5.1.5 Read/Write Electronics to Drive Signals
The read/write electronics and drive(s) communicate through five sets of signals per drive as shown in Figure 5-6 and
described below. The plug designations for the cabling are also shown in Figure 5-6.
DRIVE
0
HEAD
P3
INDEX
P6_
TRACK 00
P7 ~
HEA D STEP PER
P4
HE AD LOAD SOLENO I D
P5
READ/WRITE
ELECTRON ICS
P3 ~
HEAD
DRIVE
1
INDEX
P6
TRACK 00
P7 _
HEAD STEPPER
P4
HEAD LOAD SOLENO I D
P5
CP-HI25
Figure 5-6 Read/Write Electronics to Drive Signals
HEAD - This is an analog signal to and from the drive head.
INDEX - This is a set of signals connected to a LED-phototransistor pair which locates the index hole for
determination of diskette rotational position and speed.
TRACK 00 - This is a set of signals connected to a LED-phototransistor pair, which indicates positioning at track O.
HEAD STEPPER - This signal is output from the read/write electronics, which moves the head from track to track.
HEAD LOAD SOLENOID - These signals activate a solenoid to load the head onto the diskette during a read/write
operation. The head is unloaded from the diskette to reduce diskette wear when not performing a read/write
operation.
5-7
5.2 DETAILED BLOCK DIAGRAM AND LOGIC DISCUSSION
This section presents a detailed block diagram and logic discussion of each of the system blocks of Paragraph 5.1 and
a discussion of the J..lCPU instruction set and microprogram. The logic discussion makes references to the engineering
drawings included in the RXII and RX8 Print Sets, which are separate documents.
5.2.1 RX8E Interface
Figure 5-7 presents a block diagram of the RX8E interface. The page references in the following discussion are from
the RX8 Print Set, which is a separate document.
5.2.1.1 Device Select and lOT Decoder - The Device Select and lOT Decoder Logic, shown on page D2, decodes
RX8E instructions from the memory data bus and generates signals to the Interrupt Control and Skip Logic, the C
Line Control Logic, and the Sequence and Function Control Logic. Device selection codes are determined by the
switch configuration with relation to the state of MD6, MD7, and MD8. When the correct code for the RX8E is
input to the Device Select Logic on MD03 L to MD08 L and I/O PAUSE L is asserted, MD09 L to MDll L are
decoded by the 7442 decoder, and signal INTERNAL I/O L is asserted on the Omnibus. I/O PAUSE L is present
anytime an lOT instruction is being executed by the program. INTERNAL I/O L prevents the processor from
executing other I/O transfers (lOTs) while this instruction is being executed.
The 7442 is a BCD to decimal decoder. All Os applied to inputs A, B, and C (C is MSB) will cause pin 1, which is
unused, to be asserted low. An input of 001 (C is MSB) will cause signal LCD lOT L to be asserted. An input of 010
(decimal 2) will cause XFER lOT L to be asserted. Therefore, for each function code input on MD09 L to MDl1 L,
only one of the output lines of the 7442 will be asserted. The function codes are further explained in Paragraph 4.4.
5.2.1.2 Interrupt Control and Skip Logic - The Interrupt Control Logic, shown on page D2, asserts the BUS INT
RQST L signal on the Omnibus. Bit 11 of the data bus must be set and an INTERRUPT lOT L must be decoded by
the RX8E to set the Interrupt Enable flip-flop. The combination of the Interrupt Enable and Buffered Done
flip-flops will assert BUS INT RQST L. Setting the Buffered Done flip-flop indicates that no RXOI function is
currently in progress.
The Skip Logic implements the three lOT commands Skip on Transfer Request Flag (STR), Skip on Error Flag
(SER), and Skip on Done Flag (SDN) as described in Paragraph 4.2.
NOTE
When using these instructions, the respective flags are cleared
after they are tested (Paragraph 4.6).
Signal SKIP L will be asserted if any of the above instructions are decoded by the lOT decoder and the respective
flag has been asserted by the RXO 1.
The RX8E asserts the RX8E flags by causing a positive transition on the clock inputs of flip-flops XFER REQ, ERR,
and DONE. The signal MAINT (1) L will directly set the Skip flags to allow the Skip lOTs to assert the BUS SKIP L
signal when decoded by the lOT decoder.
5.2.1.3 C Line Select Logic - The C Line Select Logic (page D3) controls the direction of data flow between the
processor AC and the data bus and determines whether or not the AC is cleared upon completion of the transfer.
CO L will be asserted during an LCD (Load Command) instruction when signal LCD lOT L is asserted. Assertion of
Cl L requires XFER lOT H to be asserted and either MAINT (1) L or B DONE L to be asserted or WRT H to be
negated. Data transfers occur under the control of the C bits according to Table 5-1.
5-8
"'~
~
INT RQST L
SKIP L
SKP STR IOT L
MD03-MDll
I/O PULSE L
INT I/O L
0
M
N
I
B
U
S
I
RX8
SEL L
I
I
INTERRUPT CONTROL
AND
SKIP LOGIC
SKP ERR lOT L
DEVICE SELECT
AND
lOT DECODER
SKP DONE lOT L
INTERRUPT lOT L
XFER lOT H
CLINE
SELECT
LOGIC
~
LOC lOT L
.....-I
I
CO
Cl
INIT lOT L
I
...J
::t:
-o -
1,
N
Q)
MSB 12 (1) H
Vl
~
DATA 00 L
DATA It L
INTERFACE
REGISTER
...J
I.LI
Z
Z
0
~
III
~
Ci
0
::t:
~
II::
3=
BTP 3 L
MSB 8 (1) H
BTP 4H
DATA
INIT H
INIT L
XFER REQ H
B DATA 5 (1) H
B DONE H
B DATA 4( 1) H
.....
B DATA 11( 1) H
r
::
MAINT (1)L
SEQUENCE
AND
FUNCTION
CONTROL
LOGIC
B ERROR H
RX DATA L
CLK BUFF L
RXSHIFTL
ENB BUFF LOAD L
RX TRANSFER REQUEST L
TP3 H
RX OUT L
TP4 H
RX DONE L
INIT H
TO "CPU
CONTROLLER
RX ERROR L
~
7
n
I
I
RX 12 BIT L
RX INIT L
RX RUN L
~
CP-1526
Figure 5-7 RX8E Interface Block Diagram
Table 5-1
C Line Transfer Control Signals
Type of Transfer
CO
Cl
Action Required by RX8E Interface
Action by Processor
Output AC to
data bus; AC
unchanged.
H
H
Load data bus into buffer.
Transfers AC to data
bus. AC remains
unchanged.
Output AC to
data bus; AC
cleared.
L
H
Load data bus into buffer. Ground
CO.
Transfers AC to data
bus and clears AC.
Input AC ORed
with peripheral data
H
L
Gate peripheral data to data bus.
Ground CI.
AC ORed with
peripheral data.
Jam input data
bus to AC.
L
L
Gate peripheral data to data bus.
Ground CO and C 1.
Transfers data bus
to AC register.
5.2.1.4 Interface Register - The Interface register shown on page D3 is made up of three 8271 4-bit shift registers.
This register temporarily stores data during transfers from the Omnibus to the RXOI pCPU controller or during
transfers from the RXOI pCPU controller to the Omnibus.
During a data transfer from the Omnibus (Fill Buffer), the 12 parallel data lines to the register are enabled by signal
RX8 SEL L from the Device Select Logic. Data is parallel loaded into the register when signals ENB BUFF LOAD L
and CLK BUFF L are asserted. In shifting data out of the register serially for transmission to the pCPU controller,
ENB BUFF LOAD L must be negated. Signal CLK BUFF L from the Sequence and Function Control Logic clocks
data out of the buffer (paragraph 5.2.1.5).
During data transfer to the Omnibus (Empty Buffer), serial data from the pCPU controller is shifted into the buffer.
ENB BUFF LOAD L must be negated while CLK BUFF L supplies the clock pulses. The parallel data is enabled
from the outputs of the register when MAINT (1) H, RD H, or B DONE H is asserted, and when XFER lOT L is
asserted as decoded by the lOT decoder. Only eight bits of data will be output if signal 8/12 (0) H is low; otherwise,
12 bits will be transmitted.
5.2.1.5 Sequence and Function Control Logic - The Sequence and Function Control Logic shown on pages D2 and
D3 performs six distinct functions:
1.
Controls loading and shifting of the Interface register to and from the pCPU controller.
2.
Senses 8- or 12-bit mode and outputs RX 12 BIT L.
3.
Senses maintenance conditions.
4.
Generates INIT L signal to the pCPU controller.
5.
Generates RUN L signal to the pCPU controller.
6.
Generates a parity bit for the serial bit stream to the RXOI.
Interface register operation is controlled by signals ENB BUFF LOAD Land CLK BUFF L generated by the
Sequence and Function Control Logic. To assert ENB BUFF LOAD L, signal RX OUT L cannot be asserted and
either RX TRANSFER REQUEST L or RX DONE L must be asserted.
5-10
In parallel data entry to the buffer, CLK BUFF L will be asserted if any of the following conditions hold:
1.
ENB BUFF LOAD L is asserted.
2.
Either LCD or XDR instructions are being performed.
3.
Signal BUS TP3 H is asserted.
In serial data entry to the buffer, the CLK BUFF L pulses are derived from the RX SHIFT L pulses from the J.lCPU
controller.
The 8/12 flip-flop will set and signal 8/12 (1) H will be asserted if BUS DATA 5 L is asserted during a Load
Command (LCD) operation. Signal 8/12 (1) H is used to control whether 8 or 12 bits of data are transferred to or
from the Omnibus and whether 8 or 12 bits of data are transferred between the RX8E and the J.lCPU controller.
The MAINT flip-flop will set, and signal MAINT (1) H will be asserted if BUS DATA 4 L is asserted during a LCD
operation. Signal MAINT (1) H is used to allow parallel writing and reading of the Interface register from the
Omnibus. It is also used to assert signal RUN Land C Line Control signals.
An Initialize signal to the J.lCPU controller (RX INIT L) is generated either by a BUS INIT H signal from the
Omnibus or an IN IT lOT L decoded from the lOT decoder.
The RUN L signal, which is used to initiate communication between the interface and J.lCPU controller, is asserted
by setting the Run flip-flop. This flip-flop is clocked either in Command Transfer mode when LCD lOT H is asserted
or Data Transfer mode to or from the J.lCPU controller when XFER lOT H is asserted. (RUN L cannot be asserted if
DONE L is asserted.) RX BUSY Land INIT L must both be high for a RUN L signal to be asserted. Assertion of
either RX BUSY Lor INIT L will clear the Run flip-flop.
5.2.2 RXll Interface
A block diagram of the RXll interface is shown in Figure 5-8. In the following discussion, it is assumed that the
reader is familiar with Unibus operations as described in the PDP-]] Peripherals and Interfacing Handbook. Page
references are to the RXll Print Set, which is a separate document.
5.2.2.1 Address Decoder - The address decoder determines whether its associated RXll is being addressed and
whether control information or data is being transferred.
The hardware on page D2 is a combinational logic network that decodes two discrete addresses assigned to the
RXl1. Address bits (17: 13) must always be asserted to satisfy the decoder. The state of address bits A (12:03) is
determined by the placement of jumpers A12 through A3 on the board. For each of these bits, one 8242
exclusive-NOR gate is used. Insertion of a jumper for a particular bit position stores a 0 on one leg of the 8242, so
that a 1 appearing on the other leg causes the output to go low. This is a mismatch condition which is met when the
associated address bit is a 1. When both legs match (1s or Os on both), the output is high. The output of these 12
gates are wire-ORed and applied to pin 9 of the 7400 NAND gate. Pin 10 of this gate receives the NANDed signal of
A (17: 13) and BUS MSYN. Pin 8, the output of this gate, is signal REG SELECT L and is asserted when the proper
Unibus addresses are decoded.
The states of address bits A02 and AO 1 and REG SELECT L are used to produce signals D2 SELECT 00 H or D2
SELECT 02 H. The state of AO! determines which of the mutually exclusive signals, D2 SELECT 00 H or D2
SELECT 02 H, is generated. If BUS AOI L is asserted, D2 SELECT 02 H is asserted. If BUS AOI L is negated, D2
SELECT 00 H is asserted. These signals, in turn, allow access to the RXCS register as in the case of D2 SELECT 00
H asserted, or to the RXDB register as in the case of D2 SELECT 02 H asserted. (Refer to Paragraph 3.2 for register
descriptions. )
5-11
..
~
~
~17) A
MSYN
~
SSYN
.....
--
ADDR
DECODE
SELECT
02H
SELECT
00 H
....
DATA 0
....
Cl
U
N
I
B
U
S
......
DATA (8)
I-
DATA
PATH
SELECTION
1
-
J
~
READ/WRITE
DATA
BUFFER
......
....
..
~
J"
.
'
TRANS FER REQUEST L
I
DATA H
CMD H
Y'
:J:
:J:
N
0
0
0
l-
N
VECTOR
ADDRESS
GENERATOR
_0(8:2)
I-
C,.)
C,.)
UJ
...J
UJ
IJJ
IJJ
...J
fJ)
fJ)
:J:
<X
I-
:J:
...J
I-
-Zm
t:
:J:
:J:
<X
-
c
fJ)
0
m
...J
:J:
~ ~
TO P- CPU
CONl ROLLER
~
a: ::>
m ~
x <X
m a: c
IJJ
fJ)
,
DATA L
L.
L...
i.&
L...
BBSY L
BR( 7:4)
~
.....
INTR L
BG (7:4)
SSYN L
......
......
IN TERRUPT
CONTROL
LOGIC
SACK L
NPR L
i.&
L...ERROR
.....
~
L...
DONE H
t-.DONE L
t-. OUT L
•
I
I
l
SHIFT L
7
J 1- BB
Jl-J
RUN L
J1-D
TRANSFER RE(Q L Jl-T
SEQU ENCE
AND FUNCTION
CONTROL
LOGIC
I NT ENB H
......
......
--
INIT L
J I-X
JI-RR
JI-N
Jl- LL
CP-1527
Figure 5-8 RX 11 Interface Block Diagram
5.2.2.2 Data Path Selection - Data Path Selection Logic is shown on pages D2 and D3. Signal BUS C 1 L from the
Unibus controls whether Data Out or Data In operation is to be executed. Assertion of BUS C 1 L indicates Data Out
(from Unibus), and negation of BUS C 1 L indicates Data In (to Unibus). Signals D2 OUT H and its complement D2
IN H from page D2 are derived from BUS C 1 L and are input to the rest of the Data Path Selection Logic on page
D3. With BUS Cl L negated and D2 SELECT 02 H asserted, all eight bits from the data buffer are enabled through
the 8838 bus transceivers. With BUS Cl L negated and D2 SELECT 00 H asserted, only lines BUS D04 through BUS
D07, providing control and status information (RXCS), are enabled. With BUS Cl L asserted, none of the 8838s are
enabled, and data is being input from the Unibus on lines BUS DOO through BUS D07.
The 74157 multiplexer controls passage of status and control information (RXCS) in the form of signals D3 DONE
H, D3 INT ENB (1) H, and D3 TRANSFER REQUEST H from the Sequence and Function Control Logic or passage
of data from the Read/Write Data Buffer register (RXDB). If D2 SELECT 02 H is asserted, then data is output from
the 74157. If D2 SELECT 02 H is negated, then control information (RXCS) is output from the 74157.
5.2.2.3 Interface Register - The Interface register is a 74199 eight-bit, parallel load, shift register shown on page
D3. Data transfer through the register can take place from the Unibus to the pCPU controller or from the pCPU
controller to the Unibus.
In data transfer to the RXll from the Unibus, parallel data is loaded into the register when D3 RX BUSY H is
negated and D3 LOAD H is asserted. Data is serially shifted in the register from QA to QH by the D3 B SHIFT H
signal derived from the pCPU controller when D3 RX BUSY H is asserted. Serial data is shifted to the Sequence and
Function Control Logic, which transmits data to the pCPU controller (paragraph 5.2.2.4).
Data is assembled in a serial fashion for parallel transfer on the Unibus. Serial data is input at D3 B SER DATA H
and shifted by D3 B SHIFT H when D3 RX BUSY H is asserted and D3 LOAD H is negated. The eight bits of
parallel data appearing at the output of the buffer are input to the Data Path Selection Logic for transmission to the
Unibus.
5.2.2.4 Sequence and Function Control Logic - The Sequence and Function Control Logic schematics are shown
on page D3 and in the lower left-hand corner of page D2. This portion of the RXll interface provides key signals to
control the Interface register and the Interrupt Control Logic as shown in Figure 5-8. Operation of this circuitry is
controlled by signals from the pCPU controller and D2 SELECT 00 Hand D2 SELECT 02 H from the address
decoder.
Signals RX TRANSFER REQUEST L, RX OUT L, RX DONE L, and RX RUN L control data transfer between the
interface and the pCPU controller. The RX RUN L signal from the RX11 interface initiates communication between
the RXl1 interface and the pCPU controller. The Run flip-flop is set in passing either a command from interface to
controller or data between interface and controller. Run asserted while Done is true passes a command from
interface to controller. Run asserted while Done is false signals transfer of data to or from the controller.
Once a particular function has been decoded by the pCPU controller, it requests a data transfer by assertion of RX
TRANSFER REQUEST L. The access of the RXDB in the RXll interface sets the Run flip-flop and thereby asserts
RX RUN L. The Run flip-flop is cleared either by assertion of D2 B INIT H or RX BUSY H. RX BUSY H is asserted
when both RX TRANSFER REQUEST Land RX DONE L are negated. Assertion of RX BUSY H also allows the
Interface register to shift serially in communicating between pCPU controller and interface.
RX OUT L from the pCPU controller determines in which direction the data transfer is about to take place. When
RX OUT L is asserted, the direction of data transfer is from controller to interface. When RX OUT L is negated, the
direction of data transfer is from interface to controller.
On transfers from controller to interface, assertion of RX TRANSFER REQUEST L indicates that the next data
element has been assembled in the RXDB. Transfer of the next data element is initiated by RX RUN L. On transfers
from interface to controller, assertion of RX TRANSFER REQUEST L indicates that the controller is prepared to
accept the next element of data. Arrival of the next data element will be signaled by assertion of RX RUN L.
5-13
The three signals D3 DONE H, D3 INT ENB (1) H, and D3 TRANSFER REQUEST H from the Sequence and
Function Control Logic to the Data Path Selection Logic represent the three bits that may be read in the Control
and Status (RXCS) register. A functional programming description of this register is given in Paragraph 3.3.
During serial data transfer from the RXDB, a 8281 binary counter and a 74HI06 JK flip-flop are used to count eight
bits of data and to append the parity bit to the data element.
An error indication from the pCPU controller results in assertion of RX ERROR 1. This indication is passed to the
Unibus when a read from the RXCS to the Unibus is performed. When this occurs, signal BUS D 15 L is asserted.
5.2.2.5 Interrupt Control Logic - The Interrupt Control Logic, shown on page D2, is a combinational logic
network that receives and generates the control signals required for the RXII to become bus master. With signals D3
DONE Hand D3 INT ENB H both asserted, D2 BUS REQUEST L will be generated if the SACK and BBSY
flip-flops are not set. The D2 BUS REQUEST L signal is routed to the appropriate bus request line (normally BR5)
through the priority plug shown on page D3. Etch on the plug selects both request and grant lines. When the bus
grant signal is generated by the processor, it is routed via the priority plug and becomes ~ignal D3 BG IN H. This
signal clocks the GRANT flip-flop and the SACK flip-flop. The SACK flip-flop is set because the RXII had
requested bus mastership. The SACK flip-flop is cleared and the BBSY flip-flop set when BUS BBSY L, BUS SSYN
L, and D3 BG IN H are negated on the Unibus. Thus the BUS BBSY L signal will be asserted again by the RXll,
which is now bus master. The BBSY signal is inverted and applied to the vector address generator, generating the
BUS INTR L signal and the vector address of 264.
5.2.2.6 Vector Address Generator - The vector address generator, shown on page D2, consists of eight bus drivers
that are used to generate a vector address and the BUS INTR L signals. When BUS BBSY L is asserted by the RXll,
the inputs to the bus drivers are active. Seven drivers are connected to the Unibus data lines D (08:02) via jumpers.
The placement of these jumpers determines the vector address.
5.2.3 Microprogrammed Controller (pCPU) Hardware - A block diagram of the J'CPU controller is shown in Figure
5-9. The controller is a hardware microprocessor controlled by a ROM with 1536 tight-bit words; the ROM contains
the microprogram. This section discusses the various parts of the hardware while Paragraph 5.2.5 discusses the
microprogram.
5.2.3.1 Control ROM and Memory Buffer - The heart of the controller is the ROM, which contains the
microprogram shown on page D6. All control and processing activities executed by the RXOI are controlled by the
microcode sequences stored within the ROM. The ROM is divided into six fields, each with a storage capacity of 256
eight-bit words. Sequencing through the ROM microcode is accomplished by updating the contents of the program
counter (PC) every 200 ns. The eight bits from the PC indicate the address of the next instruction to be executed.
The eight-bit instruction addressed by the PC is loaded into the memory buffer on assertion of LD MB + CLK PC 1.
Each instruction consists of three fields that are sampled by the pCPU logic circuits to allow processing action
appropriate to the instruction to be taken. The three fields can be defined as follows:
07
06
05
04
I'",ST I'"o"T I s~. I S~L I
INSTRUCTION
CODE
FIELD
03
SEL
I
SELECT
FIELD
02
I S~L I
01
00
Cl
co
CONTROL
FIELD
CP-1531
5-14
RX RUN
RX 12 BIT
RX DATA
(8640)
RX INIT
DRV INIT
DC lOW
OR INIT
CKT (08)
+1 OV
CO NT I NIT
I---
SEP DATA
SYNC:~~IZER
I---
SEP CLK
~_ _ _ _....;(.;;.D_4)
r-- MI S
MEMORY BUFFER
CONTROL FLO-FUNCTION
DEPENDS ON INSTRUCTION
SELECT FLO - SELECTS
ONE OF 16
1. SCRATCH PAD REG
2. BRANCH CONDITIONS
3· DO PULSES
4. MEM FLO
INSTRUCTION FLO
WBR
(08)
(3
DRV
CONNECTOR
1 : 0
LD SP ADDR REG
(06)
CLK
I
1------ CBR
INSTRUCTION
DECODER
FLO CNTR
JUMP-
I
~1•
5 : 4 : 3 : 2
WBR CLK CNTR
r.SElECT FLO
DATA SEPERATOR
I
l
I--DATA
'«(INES)
DRIVE
RAW
DATA
7 : 6
f----12 BIT MODE
(02)
INTERFACE
CONNECTOR
I
f---- RUN
INTRF
BUS
RCVR
JUMP
00
DO PULS E
DO
01
CONDITIONAL BRI
OPEN
Cl' 0
LINES)
INSTR
FLO
(74154)
FLO DECODE
10
01-- ClK lOB 0
(2
JUMP TO FLO X NE
WORD IS ADDRESS
11-- ClK lOB 1
LINES)
21-- ClK lOB 2
(06)
WAIT BRANCH STA
CONDITION IS AS 0
OR COUNTER OVEI
11
31-- ClK lOB 3
RF~~
ENAB
(6
PC lOADl
(74161)( TWO)
(23-XXX42l(12)
B BIT
PROGRAM CNTR
~_(;.;S;..L;.I_N..;E..;S;;.)_~ CONTROL ROM
(06)
(S
LINES)
t
1(7475HTWOl
MEMORY
I-';;";''';'';..;...j~--~I BUFFER
B:{~~RDS
~_ _ _ _(;.;;D;..;6~)
B
41-- CLK lOB 4
CNT
INPUT
SEL
LINES)
SCRATCHPIl
I
IOF16
SELECT
FLO
(4 LINES)
1!00-4........------~
51-- ClK
lOB 5
61-- ClK
lOB 6
DO PULSE 7~ClK UNIT SEL
GENERATOR
BI--ClK LO HD
(03)1
91--ClK BUF ADD REG
CI
CO
o
o
o
1
o
1
1
1
SHIFT
lOAD
SHIFT
SH I FT
ZERO
SR
ONE
SEP DA 1
lOr- ClK SECTOR BUF
SELECT FLO
(4 LINES)
111-- ClK CRC
121-- ClK FLAG
RUN _
0(74150)
OB3 -
I
DATA -
2
131-- ClK SCRATCH PAD
141-- CLK CNTR
(05) 151-- ClK SR
L-._...l.!::;::..!-...J
SYN INDEX -
3
SR MSB -
4
CNTR OVFLW -
5
CRC BIT16 -
6
HOME WRT PROT -
7 Cg~I~~~N
B SELECTOR
SEP ClK 12 BIT MODE SR7e SEP DATA -
11
12
MIS CLK -
13
SEC BUFR OUT -
14
BRANCH
CONTROL
(OS)
f
Cl
10
SR7 e
FLAG -
SELECT
FLO
(4 LINES)
9
SEC BUF OVFLW -
rNO SRATCH PAD
,..------CBR
"BRIFTRUE)
( O:BR IFFALSE
(OS)
PC
LOAD
(74174)
SP
ADDR
REG
(4 LI NES)
(03)
(O'lD)
O'NCR)
C
FROM
CONTROL ROM
(74B9)(TWO)
SCRATCH PAD
16 WORDS
OF S BITS
(03)
I
1
(8 LINES)
(8266)(TWOl
l
[74161HTWOl
(8 LINES)
(SLINES
(S LINES)
CNT INPUT SEL
COUNTER
(03)
(03)
l
CO
(1: SP)
(S LINE)
ClK
CNTR
(0= ROM)
!
CNTR
OFlW
: 4 : 3
: 0
I MEMORY BUFFER
L=
I
•
I--~~~~-
lD SP ADDR REG
INSTRUCTION I---~~~-CBR
DECODER
WBR
I'CONTROl
H LT S W -;-..+~
TIMING
CONTIN SW --r.+-......
GEN
CONT ROl FLO - FUNCTION
DEPENDS ON INSTRUCTION
EAR HlT SW
-+-+-........
!
TP4
(07)
MAINT MODULE
CONNECTO
SCRATCH PAD REG
BRANCH CONDITIONS
DO PULSES
MEM FLO
CO
ClK OB 0
(INCR:' )
(LD =0) Cl
SEC BUFR
OVFlW
01
CONDITIONAL
ClK OB 3
INT ERF DATA
BRANCH
1....-_ _- - - '
OPEN
Cl = 0
INSTR
FLO
(74154)
o
(2
10
ClK lOB 0
ClK lOB 2
SELECT
FLO
(4 LINES)
3
ClK lOB 3
4
ClK lOB 4
5
ClK
lOB 5
6
10F16
DO PULSE 7
GENERATOR
8
C lK
lOB 6
9
10
1\
(D5)
P
Cl
ClK UNIT SEl
PC
lOAD
(03)
o
1
o
ClK BUF ADD REG
ClK SECTOR BUF
ClK SCRATCH PAD
ClK SR
RX SHIFT
INTRF/DRV
OUTPUT
BUFFER
--
(05)
INTERF/DRV
DRV
-
(05)
(6)
DRV WRT GATE
DRV HD STEP
DISK
BUS
GATING
DRV HD DIR
DRV ERASE GATE
DRV lOW CUR
r-
i
CRC
A -t(74174HTHREE)
}--D_A_T_
CRC
GENERATOR
CHECKER
16 BITS
i
CRC
BIT
16
DRV UNIT SEl
DRV HD lD
FLAG
DRV WRr DATA
DRV
WRT GATE
CO
J1
PRESET CRC
SET C RC
(0= lD)
(l=NCR)
FROM
CONTROL ROM
(7489)(TWOl
SCRATCH PAD
16 WORDS
OF 8 BITS
(03)
ClK
SR
CO
INDEX
SYNCRON IZER
DRV INDEX
(07)
(8266HTWOl
(74194)(TWOl
(8 LINES)
(8 liNES
CNT INPUT SEl
(8 LINES)
COUNTER
(03)
(D3)
CNTR
OFlW
SYN
INDEX
(05)
Cl
DRV TRK 00
HOME
(8 LINES)
CO
(1 = SP)
(8 liNE)
ClK
CNTR
Cl
CONNECTOR
(7408)
(7474)
DRV
C LK LD HD_
OUTPUT
BUFFER
eLK FlG _
(05)
SEP DATA
CO
'-'
(6LINES)
1
SHIFT ZERO
lOAD SR
SHIFT ONE
SHIFTSEPDATA
RX DATA
CL K UNIT SEL -
Cl
13
15
ClK OB 6
110
(D4)
ClK CRC
ClK CNTR
SEC
BUFR
OUT
SEP DATA
RX OUT
R X DONE
(7474)
CO
o
o
ClK lO Ho
14
ClK OB 5
--
r----
Cl
ClK FLAG
(4 II NES)
SP
ADoR
REG
I NTERFI DRV
--
(6)
1
RX ERROR
RX TRANS REa
INTERF
BUS
DRIVERS
(05)
12
(74174)
SCRATCHPAD
WAIT BRANCH STAll UNTIL
CONDITION IS AS DESIRED
OR COUNTER OVERFLOW
11
NO SRATCH PAD
SELECT
FLO
(4 LINES)
CLK OB 4
JUMP TO FlD X NEXT
WORD IS ADDRESS Cl=1
ClK lOB 1
liNES)
CLK OB I
CLK OB 2
DO PULSE
00
(De)I----~~-DO
(I =SEn
(O=CLR)
Cl
(1 =4K COUNT)
(O=lK COUNT)
INSTRUCTION FLO
1-_ _ _ _ _ JU MP
INTERFACE
CON NECTOR
(8881)
SELECT Flo- SELECTS
ONE OF 16
I.
2.
3·
4.
1 - - - - - - WBR ClK CNTR
TP3
CO NT INIT
lSB
SHIFT
REGISTER
HD DIR OUT
I - - _ - - S R MSB
DRV INIT
(See note)
(03)
SEP
DATA
SR-rG)SEP DATA
'-'
CP-1528
(O=ROM)
NOTE:
Some os DC LO l
MIS
CLK
in Reod I Write electronics.
SR7e MIS ClK
Figure 5-9 IlCPU Controller Block Diagram
5-15
5.2.3.4 Do Pulse Generator - Detection of a Do instruction by the instruction decoder and assertion of signal TP3
L will enable the Do pulse generator (page D5), which is a 74154 decoder. The function select bits determine which
of the outputs is asserted. All outputs supply clpcking to various flip-flops, counters, and shift registers, depending
on the function select bits. If the select field is 0000, signal CLK lOB 0 is asserted; if the select field is 0001, signal
CLK lOB 1 is asserted; etc.
5.2.3.5 Branch Condition Selector and Control - The 74150 branch condition selector (page D8) is always enabled
during a Branch instruction. The function select field determines which data line is selected for input to the Branch
Control Logic. The output signals from the Branch Control Logic, PC LOAD EN Land LD MB + CLK PC L, are
used to either increment the program counter or load in a new address. LD MB + CLK PC L is also used to load the
memory buffer.
The Cl bit, which the firmware has converted to data, is compared with the output of the branch condition selector.
If the conditions match, the PC LOAD EN Land LD MB + CLK PC L signals are enabled. The WBR CLK CNTR L
signal is asserted when a WBR instruction is decoded by the instruction decoder.
5.2.3.6 Scratch Pad Address Register and Scratch Pad - During execution of an Open Scratch Pad instruction, the
function select field contains an address in the Scratch Pad. The four-bit function select field is input to the Scratch
Pad Address register (page D3), which consists of four D-type flip-flops. The function select field appears at the
output of this register upon assertion of the CLK SP ADDR REG L signal generated by the instruction decoder.
The Scratch Pad (page D3) itself consists of two 7489s (64-bit read/write memory), capable of storing 16 eight-bit
words. Data from the shift register is written into the address indicated by the Scratch Pad Address register when LD
SCRATCH PAD L is asserted. Reading occurs when this signal is negated. Data read out is input to the Counter
Input Selector Logic.
5.2.3.7 Counter Input Selector, Counter, and Shift Register - The counter input selector, counter, and shift
register (page D3) act as buffering circuitry for information flow in and out of the Scratch Pad. Signals CO and C 1
control operation of this logic.
The counter input selector consists of two 8266 multiplexers that select eight parallel bits from either the ROM or
the Scratch Pad, depending on the state of CO(1) H. If CO(1) H is asserted, the Scratch Pad data is selected; if CO(1)
H is negated, the ROM data is selected. The state of CO is determined by the low order bit of the instruction code
from the memory buffer.
The outputs of the counter input selector are presented to both the program counter and the counter. During
execution of a Jump instruction and Branch instruction when the branch conditions are met, a new address is loaded
into the program counter. The control field of the instruction will determine the source of the new address. If the
source is the ROM, the address is in the location following the instruction. If the source is the Scratch Pad, some
previous calculation was performed to determine the new address.
The counter is made up of two 74161 synchronous four-bit counters. The output of the counter input selector is
loaded in the counter if signal Cl(1) H is negated. If Cl(1) H is asserted, the counter increments upon detection of
signal CLK CNTR L. During execution of a DO instruction, the Do pulse generator supplies the clocking signal if the
select field is correct. An overflow condition, indicated by allis in the counter, is detected by assertion of signal
CNTR OVFLW H, which is input to the branch condition selector.
Data output from the Scratch Pad counter is loaded into the shift regsiter if CO(1) L is asserted and Cl(1) H is
negated. Data appears at the outputs after the positive transition of the clock input CLK SR L. When CO(1) Land
C1(1) H are asserted, data from the data separator is serially shifted into the shift register by signal CLK SR L.
Therefore, input to the Scratch Pad is either by way of serial data from the data separator or parallel data from the
counter. The data from the data separator originates from the read/write electronics during access from the diskette.
SRMSB, the MSB of the shift register, is exclusive-ORed with data [SEP DATA (1) L] and a missing clock indication
[MIS CLK (1) L] from the data separator for input to the branch condition selector. SRMSB (1) H alone is also
presented to the branch condition selector.
5-17
Bits can be shifted in to the shift register via CLK SR L, CO, and C 1. Signal SR LOAD H is asserted when CO(1) L is
asserted and Cl(1) H is negated, allowing the shift register to be parallel loaded from the counter. With CO(1) Hand
Cl(1) H both asserted, SEP DATA from the data synchronizer and separator is serially input to the shift register. If
CO(1) L is negated, Is and Os from the Cl(1) H bit stream are loaded into the shift register. In summary, CO
determines shift or load of the shift register; C 1 and SEP DATA are two serial bit streams.
Cl
CO
0
0
0
1
0
Shift Zero
Load Shift Register
Shift One
Shift SEP DATA
5.2.3.8 pCPU Timing Generator - The pCPU timing generator, shown on page D7, produces signals TP3 and TP4,
which are used as timing signals for the rest of the pCPU controller. The 74H74 flip-flops are used as a wraparound
shift register to derive TP3 and TP4 from the 20 MHz oscillator. TP3 and TP4 are 5 MHz signals with a pulse width
of 50 ns. In normal operation, a recirculating 1 bit in this shift register causes TP3 to occur before TP4. Inputs to the
maintenance module connector and signal INIT + PC L control operation of this shift register.
5.2.3.9 Sector Buffer and Address Register - The 2102 sector buffer, which is a 1024-bit MOS RAM, and the
address register, composed of three 74161 synchronous four-bit counters, is shown on page D4. The address register
is used as a loop counter for the microprogram as well as an address register for the sector buffer. The ten LSB
inputs to the register are grounded, and the upper two MSB inputs are connected to signal CO(1) L.
When used as a loop counter or an address register, Cl(1) H is negated and the ten LSB bits of the register are zero.
With Cl(1) H asserted, the count is incremented by signal CLK BAR L, which occurs once per disk data bit. If CO(1)
L is asserted, the two MSB bits are also zero, enabling the counter to count 4096 clocks before the SEC BUF
OVFLW H signal is asserted. If CO(1) L is negated, the two MSB bits are one, enabling the counter to count only
1024 clocks before the SEC BUF OVFLW H signal is asserted.
Reading or writing is controlled by a flip-flop. If CO(1) H is asserted and CLK SEC BUF L is asserted, the write
enable line to the 2102 is asserted by setting the flip-flop. The CLK SEC BUF L signal is asserted twice per bit, once
to set the flip-flop and once again to clear it. It is cleared when CO(1) H is negated and the second CLK SEC BUF L
pulse is asserted. Data to be written in the sector buffer is contained in signal SEP DATA (1) L from the read/write
electronics while reading from the diskette; the data is contained in signal DATA I L from the interface while writing
on the diskette.
In reading data out of the sector buffer, the write enable line is negated, and the serial data stream appears at SEC
BUF OUT (1) H as the Buffer Address register is incremented.
5.2.3.10 CRC Generator and Checker - Each sector has a two-byte CRC character for the header field and another
two-byte CRC character for the data field (Figure 1-11). The CRC generator and checker shown on page D7
produces the CRC character to be written on the diskette and checks the CRC character read from the diskette. A
16·bit shift register with properly placed exclusive-OR gates implements the polynomial divide algorithm. The CLK
CRC L signal clocks the shift register so that the entire header field or data field is divided by a selected CRC divisor
which is 2 15 + 212 + 25 + 1. The mathematical expression for this operation is:
an 2n + ... + a 3 2 3 + a 2 2 2 + a 1 21 + a o 2
where a
n
0
= coefficient of the bit position
= number of bit positions in
the data block
5-18
In writing data on the diskette, each bit is shifted through the CRC generator. This data stream appears on signal
C1(1) L and is produced by the firmware. Signal CO(!) L negated will enable this data stream to the CRC register.
After the data field has been written, the CRC register contains the remainder of the division, which is the two-byte
CRC character that is written after the data field.
During a read operation, the data stream from the data synchronizer and separator, SEP DATA (1) L, is enabled to
the CRC register. This data stream is manipulated in the same way as in the write operation. When the CRC
character on the diskette is encountered, it is shifted into the CRC generator as if it is part of the data stream. If all
the data and CRC bits that were previously written on the diskette are retrieved, the CRC register, which contains
the remainder of the division, should be zero. The contents of this register are input to the condition selector, where
the firmware checks to see that the register contents are all zero.
S.2.3.11 Data Synchronizer and Separator - The data synchronizer and separator (page D4) separates clocking
information from data, identifies missing clocks, and synchronizes the clock to the data. Clocking and data are
mixed in the output data stream (paragraph 1.3.2). In the read/write electronics, one-shots set to produce 200 ns
pulses for each transition convert the flux reversal signals to a series of pulses as shown in Figure 5-10. The clock
pulses can be separated from the 1 data pulses as shown. If no data pulse occurs between two clock pulses, a 0 bit is
indicated. Notice that there is a clock pulse every 4 ps.
FLUX
REVERSAL
STREAM
RAW DATA
IoIIIoIIIIIo IIIoI
C
SEP CLOCK
I
-I
C
1
j.....
4".sec
C
C
1
C
1
C
C
1
C
C
0
I
SEP DATA
MIS ClK
CP'1~:;!9
Figure 5-10 Data and Clock Separation
The data synchronizer and separator produces three outputs: separated clock (SEP CLK), separated data (SEP
DATA), and missing clock (MIS CLK). SEP DATA is one bit position delayed from the flux reversal stream. In the
example shown in Figure 5-10, there are no missing clock indications because the RAW DATA stream does have a
clock pulse every 4 ps. The MIS CLK indication is used in locating the ID address mark of the sector header field and
the data or deleted data mark of the sector data field. (See Figure 1-9.) Each of these data marks is a unique
sequence of data and missing clocks that the microprogram identifies by examining the data synchronizer and
separator circuit.
Figure 5-11 is the ID address mark which contains missing clocks. Since clocks must occur every 4 ps, the missing
clocks can be identified· as C. SEP CLK output will include clock pulses that are separated by 6 ps and will be out of
synchronization with the real clock pulses. SEP DATA will indicate a 1 bit when a data pulse exists between SEP
CLK pulses; it will indicate a 0 where there is no data pulse. As in the first case, SEP DATA is delayed by one clock
period. MIS CLK is also delayed by one clock period and occurs when SEP CLK pulses occur more than 5 ps apart.
5-19
1112131415\6\7\8\
I---
1 D ADDRESS MARK
'\
FLUX REVERSA L
STREAM
I
1111
C OC 1 C 1
I
I
C 1 C1 C
111111
I
1
RAW DATA
1 C 1 C 1 C OC OC
---,--I-",--I--1-'--1...1---,--'--,--I--1-1-1--..1---,--I--,--I SEP CL K
L
SEP DATA
_____---'nL..______1l
MIS CLK
CP-1530
Figure 5-11 ID Address Mark Data Separation
The data synchronizer and separator uses two timing windows to separate data from clocks. If a pulse occurs within
3 J.,ls from a valid clock pulse, it is a data 1 bit. If it occurs between 3 and 5 J.,lS from a valid clock pulse, it is the next
clock pulse. If it occurs after 5 J.,lS, there was a MIS CLK. The logic is shown on page D4. The timing windows are
produced by two pairs of 74193 counters, which are preset to a given count and clocked by the 20 MHz clock after
it has been divided down to 10 MHz. The carry of these counters is used to clear flip-flops to provide timing
indications. The END WIND L signal from the 3 J.,lS timer clears the 74HI03 flip-flop. The two follOWing 74S74s
synchronize the data to the 20 MHz clock. The SEP DATA output delayed by one SEP CLK clock period appears at
the output of the 74HI03. MIS CLK is produced when the 5 J.,lS timer issues a carry to clear the 74HI03. SEP CLK is
produced by the 74HI03 flip-flop, which is cleared by a state of the 3 J.,lS timer. The following flip-flop synchronizes
the SEP CLK signal with BTP3H.
5.2.3.12 Output Circuit - The output circuit shown on page D5 consists of the interface/drive output buffer, drive
output buffer, interface bus drivers, disk bus gating, and index synchronizer. Signals CLK lOBO to CLK IOB6 from
the Do pulse generator are used to clock the flip-flops in the interface/drive output buffer. The interface bus drivers
and the disk bus gating outputs are appropriate combinations of signals from the interface/drive output buffer that
are output to the interface or to the read/write electronics. lOBO selects the output bus to which the rest of the lOB
signals are to be assembled. A further explanation of these signals is given in Paragraphs 5.1.3 and 5.1.4.
The drive output buffer consists of three flip-flops, FLAG, UNIT, and HD LD, which respectively produce signals
DRY WRT DATA, DRY SEL 1 H, and DRY HD LD H to the read/write electronics.
The index synchronizer consists of two flip-flops used to synchronize the SEL INDEX H signal from the read/write
electronics. The flip-flops are cleared and SYN INDEX (1) H is negated by the Do pulse generator. SYN INDEX (1)
H will be asserted by the first TP3 after the SEL INDEX H assertion and input to the branch condition selector.
5-20
5.2.4 Microprogram Instruction Repertoire - The firmware within the RXOI Read-Only Memory (ROM) employs
five different instruction types to implement the various control sequences used to process each function code.
Regardless of type, an instruction is made up of eight bits and contains three fields as shown below:
07
06
05
INSTRUCTION
CODE
FIELD
04
03
02
SELECT
FIELD
01
00
CONTROL
FIELD
CP-l~32
The RXOI pCPU controller distinguishes between the different instruction types by the content of the instruction
code field. The select field is used to define sub functions of a single instruction type. This field is also used for
addressing locations in the pCPU Scratch Pad memory. The control field allows for still further definition of the
instruction purpose and, in one case, serves to distinguish between two instructions having the same instruction field
code. The five basic instructions executable by the pCPU controller are:
1.
DO instruction
2.
Conditional Branch
3.
Wait Branch
4.
Open Scratch Pad
5.
Jump
5.2.4.1 DO Instruction - The most frequently executed pCPU firmware instruction is the DO instruction. Its
format is:
07
I
0
06
I
05
04
03
02
01
00
0
INSTRUCTION
CODE
FIELD
SELECT
FIELD
CONTROL
FIELD
CP-1533
Through use of different function select codes, the DO instruction is used to assert/negate many of the interface
lines going to both the interface and the read/write electronics. The DO instruction is also used in shifting data bits
to/from the interface for the Empty/Fill Buffer function and writing data bits onto the disk for the Write Sector
function. Furthermore, the DO instruction is used for function decoding, parity checking, CRC field
generation/detection, and numerous housekeeping functions inherent in the various pCPU controller sequences. A
complete breakdown of all DO instruction subfunctions is given in the RX8/RXll Print Sets.
5-21
5.2.4.2 Conditional Branch - The Conditional Branch instruction is used to sample status conditions within the
RXOl. On detection of a given condition, a branch to another area of the ROM occurs. The format of the
Conditional Branch instruction is given below:
07
INSTRUCTION CODE
FIELD
05
06
04
03
02
01
00
0- BRANCH ADDRESS
TAKEN FROM ROM
1 - BRANCH ADDRESS
TAKEN FROM OPEN
SCRATCH PAD
~l
0- BRANCH WHEN
DEFINES CONDITION _ _ _ _ _ _ _ _ _---'
BEl NG SAMPLED
CONDITION IS FALSE
1 - BRANCH WHEN
CONDITION IS TRUE
CP-H!34
Many conditions are sampled by the Conditional Branch instruction; examples are 12-bit mode, drive ready,
read/write head located at track zero, and two index pulses have occurred. A complete breakdown of all Conditional
Branch subfunctions is given in the RX8/RXll Print Sets.
5.2.4.3 Wait Branch - The Wait Branch instruction is similar to the Conditional Branch instruction; the difference
is that the Wait Branch instruction is used to stall pCPU controller operations until a given condition becomes true.
The format of the Wait Branch instruction is given below:
07
INSTRUCTION CODE
FIELD
05
06
03
04
02
00
01
0- BRANCH ADDRESS
~\
1-
TAKEN FROM ROM
BRANCH ADDRESS
TAKEN FROM OPEN
SCRATCH PAD
0- BRANCH WHEN
DEFINES CONDITION
BEl NG SAMPLED
CONDITION IS FALSE
1 - BRANCH WH EN
CONDITION IS TRUE
CP-1535
A breakdown of all Wait Branch sub functions is given in the RX8/RXll Print Sets.
5.2.4.4 Open Scratch Pad - The Open Scratch Pad instruction is used to address (select) any of 16 locations in the
pCPU controller prior to executing a read/write operation. The format of the Open Scratch Pad instruction is given
below:
07
06
05
04
03
02
01
00
MUST
BE
ZERO
CP -1536
5-22
- REFERS TO 1'S COMPLEMENT
0<) MEANS CONTENTS OF REG X
FLAG = ZERO
FLAG = ONE
20, .... ERREG
10, .... CNTR
[DRV 0 HOME
COULD NOT
BE FOUND)
[ORV 1 HOME
COULD NOT
BE FOUND)
c
FLAG = ONE
NOT ROY
SR = 252.
SR
ROY
'* 252.
SR7 =ONE
SHI FT SR ONCE
FOR 2NO FUNC
BIT
NOTES:
SR7 =ONE
All numerals are decimal
unless subscripted.
LEGEND
FLAG = ONE
I
I
«
(
)
)
SHIFT SR ONCE
FOR 3RD FUNC
BIT
FLAG = ZERO
INDICATES CALL
TO SUBROUTINE
tSR) .... INTERFACE
[SERIAL
SYNCHRONOUS
TRANSFER)
BEGINNING OF
A SUBROUTINE
BRANCH TO OR
OONE
HOME
BEGINNING OF
A ROUTINE
ACTIONS
Figure 5-12 Initialize and Function Decode Flowchart
5-24
o
SR7 =ONE
~
a
SR7 = ZERO
SR.
FLAG - ZERO
FLAG = ONE
20 ..... ERREG
[DRV 1 HOME
COULD NOT
BE FOUND]
10 ..... CNTR
[DRVOHOME
COULD NOT
BE FOUND]
c
FLAG = ZERO
FLAG =ONE
SHIFT SR 3 TIMES
FOR UNIT BIT IN
SR7
CLR ERR
SAVE UNIT IN
FLAG.
UNIT 0 = FLAG ON
NOT ROY
ROY
SHIFT SR ONCE
FOR FUNCTION
BIT
SR7 =ONE
SR7-ZERO
SHIFT SR ONCE
FOR 2ND FUNC
BIT
SHIFT SR ONCE
FOR 2ND FUNC
BIT
E
:::J
HOME
:=J
~
HOME
6
{SRI .... INTERFACE
[SERIAL
SYNCHRONOUS
TRANSFER]
SR7 =ONE
SR7 =ZERO
~ ~
SR7 =ONE
SR7 = ZERO
~
SR7- ZERO
SHIFT SR ONCE
FOR 3 RD FUNC
BIT
SHIFT SR ONCE
FOR 3RD FUNC
BIT
SHIFT SR ONCE
FOR 3RO FUNC
BIT
::J
. SR7=ONE
SR7'" ZERO
SR7 = ONE
SR7 -ONE
SHIFT SR ONCE
FOR 3RD FUNC
BIT
SR7 = ZERO
~
SR7=ONE
SR7 =ZERO
~
CP·1544
FILL BUFR
(CNTRI + 1 -> TEMPA
[lNCR BYTE CNT]
INCREMENT SEC
BUFR ADDR
(CNTRI + 1->
OPENED SP
[INCREMENT
BYTE COUNT]
SHIFT SR. INSERT 0
TWICE [CLEAR SR]
SBITMODE
( BYTEOur)
CNTR =OVFLW
CNTR
INCREMENT SEC
BUFADDR FOR
NEXT BIT
12 BIT MODE
SBITMODE
CNTR
* OVFL
CNTR = OVFL
CNTR =OVFLW
* OVFLW
12BITMODE
SBITMODE
DATA DIR = OUT
DATA DIR = IN
~
NOTES:
All numerals are decimal
unless subscripted.
CNTR
CNTR =OVFLW
DATA DIR = OUT
* OVFLW
LEGEND
CNTR
DATA DIR = IN
SELECT SECTOR
BUFFER AS
DATA SOURCE
RUN=T
RUN = F
* OVFLW
I
(
(
I
)
)
INDICATES CALL
TO SUBROUTINE
BEGINNING OF
A SUBROUTINE
BRANCH TO OR
BEGINNING OF
A ROUTINE
I
ACTIONS
CP-1545
Figure 5-13 Empty and Fill Buffer Functions Flowchart
5-25
READ
OPEN TEMP 0
[FOR SOFT UNIT
SELECT]
BUFFR ADDRESS
SEP CLK = F
END AROUND
SHIFT OF DRV
ROY BIT
SEP CLK = T
-3"'" TEMP B
[DATA MARK
TRY COUNTER]
SET FLAG
[TO SIGNIFY
LOOKING FOR
DATA MARK]
O..... CNTR
[UNIT 1 ..... SOFT
UNIT SEL BIT]
FLAG = ZERO
FLAG =ONE
SHIFT SR, INSERT 1
[SET DEL DATA
BIT]
SHIFTSR,INSERTO
[CLR DEl DATA
BIT]
FLAG = 1
FLAG = 0
SEC BUF ADDR
*- OVFLW
SEC BUF ADDR = OVFLW
WAIT 96Jl.s
[TO PASS WRITE
TURN ON SPLASH
AREA]
END AROUND
SHIFT OF NEXT
5SR BITS
SHIFT SR, INSERT 1
[SET CRC ERROR
BITOFSTAT]
-16 ..... CNTR
[BIT COUNT FOR
CRC CHECK]
-16 ..... CNTR
[BIT COUNT TO
PICKUPCRC]
200 8 ..... CNTR
[UNIT 0 ..... SOFT
UNIT SEL BIT]
CRC 16= 1
(SRI ..... OPENED SP
[RESTORE STAT]
(CNTRI ..... OPENED SP
[STORE SOFT UNIT
SEL BIT]
CRC 16= 0
NOTES:
All numerals are decimal
SEP CLK = F
unless subscripted.
SEPCLK = T
O..... CRC
[BRING UP NEXT
CRC BIT]
LEGEND
I
C
(
I
)
)
200 8 ..... CNTR
[ERROR CODE FOR
DATA CRC ERROR]
INDICATES CALL
TO SUBROUTINE
(CNTR) + 1 ..... CNTR
[INCREMENT BIT
COUNT]
BEGINNING OF
END AROUND
SHIFT OF 5
BITS IN SR
A SUBROUTINE
BRANCH TO OR
CNTR
*-
OVFLW
CNTR = OVFLW
(SRI ..... OPENED SP
[RESTORE STAT]
BEGINNING OF
A ROUTINE
CNTR
*- OVFLW
END AROUND
SHIFT OF LAST TWO
STAT BITS IN SR
CNTR =OVFLW
SHIFT SR, INSERT 0
[CLR INIT DONE
BIT]
ACTIONS
CP·1547
Figure 5-14 Read Sector and Read Status Functions Flowchart
5-26
The Read Status function (Figure 5· 14) checks to see if the Drive Ready conditions are met by calling the CHKRDY
subroutine. If they are, the Drive Ready bit of the Status register is set, and the system status is checked. If not, the
Drive Ready bit is not set, and the system status is checked by a branch to the DONE condition.
The functions Write Sector and Write Deleted Data Sector (Figure 5· 15) are similar except that the Deleted Data flag
is set in the Write Deleted Data Sector function. The diskette address and sector are found and WRITE GATE and
ERASE GATE signals are sent to the read/write electronics. The sector must be correctly formatted with proper
header, header CRC, 1024 bits of data, and data CRC. After the WRITE GATE and ERASE GATE signals are
negated and the next header is located, a branch is made back to the DONE condition to check status.
The FINDTR subroutine (Figure 5.16) locates the track as specified by the diskette address. Status and Error
Scratch Pad locations are cleared. The Drive Select bit is interrogated to detennine which drive is being used. The
sector address is moved from the interface to the controller shift register by the subroutine GETWRD, and its parity
is checked. Then the eight·bit track address is moved from the interface to the target track register, and parity and
track legality are checked. The current track address of the drive selected is compared with the target track address
by the subroutine MAGCOM to detennine if the head must step in or out to reach the target track. Head stepping is
accomplished by the subroutine STEPHD once the proper track is located and the head is loaded. If the track
address is greater than 44, the low write current level is selected. If the track address is less than 44, the high write
current level is selected. Subroutine FINDSE locates the target sector.
The FINDHD and GETDAM subroutines (Figure 5·17) locate the header field and identify the data address mark.
The data address mark is a unique combination of data, clocks, and missing clocks for which the microcode searches.
Figure 5·18 contains the routines HDRCOM, BDSRT, and BADHDR, which are continuations of the FINDHD
subroutine. The routine HDRCOM is used in comparing a located header with a desired header. A sector address
compare and a track compare are made. The BDSRT and BADHDR routines count the number of retries for "finding
a data mark or an ID address mark. If too many tries are made, the appropriate error codes are set.
Figure 5·19 contains the four subroutines, DELAY, FINDSE, WRTOS, and GE1WRD. The DELAY subroutine
produces a delay period as set by the delay multiplier that resides in the shift register. The DELAY subroutine is
called throughout the microcode to establish waiting times, such as a head load wait of 20 ms. The FINDSE
subroutine uses the sector address to locate the correct sector by calling the subroutine FINDHD to find the correct
header. The subroutine WRTOS writes the specified number of zeros indicated in the shift register. The GETCMD
and GETWRD subroutines differ in that a Transfer Request must be set for a GETWRD. The microcode calls the
subroutine WAITRN to wait for a RUN signal from the interface. Error and Done flags are cleared, and either 12 bits
or 8 bits are transferred. Parity is checked and the appropriate error code results if a parity error is detected.
Figure 5·20 shows the flowchart for the STEPHD, WAITRN, and MAGCOM subroutine. The STEPHD subroutine
moves the head in or out a certain number of tracks as indicated by the counter. When the head is positioned over
the desired track, the head is loaded, and a 20 ms delay occurs before the microcode exits from the subroutine. The
WAITRN subroutine waits for the RUN signal from the interface. If RUN does not come within 45.87 ms, the head
is unloaded, Transfer Request is cleared, and an exit is made out of the subroutine. If RUN does occur within
45.87 ms, Transfer Request is cleared and an exit is made out of the subroutine.
The MAGCOM subroutine compares track addresses and is called by the FINDTR subroutine.
Figure 5·21 shows flowcharts for the DIF and CHKRDY subroutines. The DIF subroutine detennines the difference
between target track and desired track, so that the STEPHD routine can move to the right track. The CHKRDY
subroutine checks for a Drive Ready condition during an Initialize sequence or during a Read Status function.
5·27
CNTR =OVFLW
CNTR oF OVFLW
352, -+ SR
[FLUX TRANSITION
PATTERN FOR 1ST
HALF OF BOTH
DATA MARKS)
WRTENAB
=F
SR7
CNTR '" OVFLW
CNTR
=1
~OVFLW
WRTENAB:T
(CNTR) + 1 ~ CNTR
[INCREMENT
TRANSITION
COUNT]
CNTR -OVFLW
SR7
=0
SR7 = 1
CNTR oF OVFLW
SHIFT SR, INSERT 0
[BRING NEXT
TRANSITION
TOSR7)
SR7 = 0
GO,
-+ CNTR
[ERROR CODE FOR
A SELFTEST ERROR!
SR7
F
SET EGATE
[START ERASE
CURRENT IN
MIDDLE OF
PREAMBLE)
NOTES:
SEC BUF OUT
=1
1
=0
SEC BUF OUT = 1
All num •••• are decimal
CRCI6= 0
C
CRCI6-1
unl . . subscripted.
CNTR '" OVFLW
LEGEND
I
f_---J)
C
__)
I
CNTR =OVFLW
INDICATES CALL
SHIFT SR, INSERTO
[BRING NEXT
TRANSITION TO SR7)
TO SUBROUTINE
o -+
CRC
[JAM 1ST 6 BITS
OF DATA MARK
INTO CRC
GENERATOR!
BEGINNING OF
A SUBROUTINE
{CNTR) + 1 -+CNTR
[INCREMENT
TRANSITION
COUNT)
BRANCH TO OR
BEGINNING OF
A ROUTINE
SR7-0
SR7
~
[SET UP
TRANSITION
COUNT)
SEC BUF ADDR oF OVFLW
SEC BUF ADDR = OVFLW
,.
ACTIONS
337, -+CNTR
[2ND HALF TRANSITION PATTERN
FOR NORMAL
DATA MARK!
325, -+ CNTR
[2ND HALF TRANSITION PATTERN
FOR DELETED
DATA MARK!
TWO I'S-+CRC
[JAM LAST 2 BITS
OF NORMAL
DATA MARK
INTOCRC)
TWO O'S -+ CRC
[JAM LAST 2 BITS
OF DEL
DATA MARK
INTOCRC)
Figure 5-15 Write Sector Function Flowchart
5-28
WRTOS
[WRITE 22 ZEROS
LAST HALF OF
PREAMBLE)
B
CNTR ",OVFLW
c
CNTR
=OVFLW
E
CNTR =OVFLW
CNTR
¢
OVFLW
352, - SR
(FLUX TRANSITION
PATTERN FOR 1ST
HALF OF BOTH
DATA MARKS)
SR7= 1
SR7
CNTR '" OVFLW
=0
CNTR =OVFLW
WRTENAB=T
(CNTR) + 1 - CNTR
(INCREMENT
TRANSITION
COUNT]
CNTR =OVFLW
SR7 = 0
SR7 = 1
CNTR
¢
OVFLW
SHIFT SR, INSERT 0
[BRING NEXT
TRANSITION
TOSR7)
SR7
SR7
F
SET EGATE
[START ERASE
CURRENT IN
MIDDLE OF
PREAMBLE)
(CNTRI + l-CNTR
(INCREMENT
TRANSITION
COUNT)
325, -CNTR
11'S-CRC
1/1 LAST 2 BITS
TWOO'S-CRC
[JAM LAST 2 BITS
OF DEL
DATA MARK
INTOCRC)
"A MARK
OCRC)
CRC16
=0
CRC16 = 1
CNTR =OVFLW
-7-CNTR
[SET UP
TRANSITION
COUNT]
SEC BUF ADDR
¢
OVFLW
SEC BUF ADDR = OVFLW
SR7= 1.
-CNTR
) HALF TRANON PATTERN
NORMAL
'AMARK)
~ORMAL
SEC BUF OUT = 1
(TEMPBI- SR
[GET 2ND HALF
TRANSITION
PATTERN]
[JAM 1ST 6 BITS
OF DATA MARK
INTO CRC
GENERATOR)
SR7=O
=1
1
SEC BUF OUT = 0
CNTR "'OVFLW
=0
[2ND HALF TRANSITION PATTERN
FOR DELETED
DATA MARK)
WRTOS
[WRITE 22 ZEROS
LAST HALF OF
PREAMBLE)
B
CNTR *OVFLW
c
CNTR=OVFLW
E
CP-1546
Nchart
GETWRD
[-SEC ADDR FROM
HOST- SR)
SHIFT SR, INSERT 1
[SET MSBOF
SECTOR ADDR)
MAG COM
[CHECK I FLEGAL
TRACK)
TARTRK> 77
TARTRK
= 77
MAGCOM
[IS TARGET SAME
ACCURRENT)
TARTRK
<
TARGF.T = CURRENT
77
DIF
[NECESSARY
STEPS-SR)
TARGET
<
CURRENT
TARGET> CURRENT
~ARGET > CURRENT
(TEMP Dl-SR
[GET SOFT UNIT
SEL BIT)
TARGET
< CURRENT
~
(TEMPDI-SR
[GET UNIT SEll
(TEMPDI-SR
[GET UNIT SEL)
SR7
FLAG = 0
=0
SR7
FLAG = 1
=1
FLAG = 0
FLAG
=1
GETWRD
[-TRACK ADDR
FROM HOST-SR)
STEP HD
[GO TO TARGET
TRACK)
SR7
SR7
200. -CNTR
[UNIT 0 - SOFT
UNITSEL)
=0
SR7
=0
SR7
=1
=,
O~CNTR
[UNIT 1 - SOFT
UNIT SEll
(CNTRI - OPENED SP
[RESTORE SOFT
UNIT BIT TO
TEMPO)
O-TEMPE
[CLRSOFT HD
LOADED BIT
BECAUSE A NEW
UNIT IS SELECTEDI
HOME
DONE
(SRI -+ TEMP F
[PASS TAR TRACK
TO SUBR MAGCOM)
-77-TEMPG
[PASS #77 TO
SUBR MAGCOM)
50. -CNTR
[ERROR CODE
FOR HOME
BEFORE DONE]
(TEMP Dl-SR
[GET SOFT
UNIT SEL)
(OPENED SPI-TEMPG
[PASS CURRENT
TRACK TO MAGCOM)
ITARTRKI- CNTR
[PASS TO DIF)
(TARTRKI- TEMPF
[PASS TARGET
TOMAGCOM)
SR7
=0
SR7 = 1
MAG COM
[CHECK I FLEGAL
TRACK]
GETWRD
[-SEC ADDR FROM
HOST- SRI
SHIFT SR, INSERT 1
[SET MSB OF
SECTOR ADDR]
TARTRK> 77
TARTRK = 77
MAG COM
[IS TARGET SAME
ACCURRENT)
TARTRK
TARGET = CURRENT
< 77
DIF
[NECESSARY
STEPS-+ SR)
TARGET
<
CURRENT
TARGET> CURRENT
~ARGET > CURRENT
TARGET
< CURRENT
SR7 = 0
SR7 = 1
(TARTRK) -+ TEMPF
[PASS TO MAGCOM]
~
-44 - TEMPG
[PASS #44 TO
MAGCOM]
(TEMP OJ -+ SR
[GET UNIT SEL)
GETWRD
[-TRACK ADDR
FROM HOST -+ SRI
STEP HD
[GO TO TARGET
TRACK]
SR7
(TEMPE) -+ SR
GET HD LOADED
BIT
(CNTRI .... OPENED SP
[TARGET TO APPROPRIATE CURRENT
TRACK REGI
=0
MAGCOM
[COMPARE
TARGET TO 43]
SR7 = 1
SR7 = 1
SR7 = 0
HOME
DONE
NOTES:
All numerals are decimal
(SRI -+ TEMP F
[PASS TAR TRACK
TO SUBR MAGCOM]
-77 -+ TEMP G
[PASS #77 TO
SUBR MAGCOM]
TARGET
50, -+ CNTR
[ERROR CODE
FOR HOME
BEFORE DONE)
<
44
TARGET
= 44
TARGET> 44
unless subscripted.
LEGEND
I
(OPENED SPI -+ TEMPO
[PASS CURRENT
TRACK TO MAGCOM]
FINDSE
[LOCATE THE
TARGET SECTOR I
(TARTRKI- CNTR
[PASS TO DIF]
(TARTRKJ-+ TEMPF
[PASS TARGET
TOMAGCOM]
SR7 = 0
I
)
)
C
(
TO SUBROUTINE
BEGINNING OF
A SUBROUTINE
BRANCH TO OR
BEGINNING OF
A ROUTINE
I
SR7 = 1
INDICATES CALL
ACTIONS
CP-1548
Figure 5·16 FINDTR Subroutine Flowchart
5·29
WAIT 40 p.s FOR
FOURTH CELL
SEP DATA = 0
SEPDATA=1
MISCLK =1
MISCLK =0
SEPCLK
MISCLK = 0
O.... CRC
[JAM 6TH
DAM BIT]
MISCLK = 1
I
SEP DATA = 0
SEP DATA = 1
1 .... CRC
[JAM 7TH
lOAM BIT]
~
MISCLK = F
WAIT 40,...
FOR SIXTH CELL
MISCLK=T
WAIT 40,... FOR
LAST CELL]
A
WAIT40p.s
FOR FIFTH CELL
MISCLK=1
SEPCLK
40P.5
MISCLK =0
SEPCLK
SEPDATA= 1
SEP DATA = 0
I
I
FLAG = 1
SEP DATA = 0
SEP DATA = 1
110, .... CNTR
[ERROR CODE
FOR NOSEP
CLOCKS]
SEP DATA =0
MISCLK=1
SEPDATA= 1
MISCLK = 0
FLAG =0
~
MISCLK = 1
MISCLK = 0
WAIT 40,... FOR
SEVENTH CELL
WAIT 40,... FOR
SEVENTH CELL
40,...
SEPCLK
SEPCLK
40p.s
WAIT 40,... FOR
SIXTH CELL
~
40,...
SEPCLK
cb
A
NOTES:
All numerals are decimal
unless SUbscripted.
LEGEND
I
C
(
I
)
)
INDICATES CALL
TO SUBROUTINE
BEGINNING OF
A SUBROUTINE
SEP DATA = 0
SEP DATA = 1
SEP DATA = 0
I
BRANCH TO OR
BEGINNING OF
A ROUTINE
ACTIONS
SEP DATA = 1
MISCLK = 1
MISCLK =0
CP·1550
Figure 5-17 FINDHD and GETDAM Subroutines Flowchart (Sheet 1 of 2)
5-30
WAIT 40j.l.5
FOR SEP ClK
-O-TEMPA
[INNER COUNT
FOR BAD STARTS]
INIT BUFF ADDR
REG FOR 4096
COUNT
[NOSTART
COUNT)
40j.l.s
SEP ClK
!
OPEN TEMPB
[OUTER COUNTER
FOR BADSTARTS)
SEP DATA = 0
SEP DATA = 1
d:J
WAIT 401'5
FOR SEPCLK
SEP ClK
INCR BUFFR
ADDR REG
[INCR PREAMBLE
FAIL COUNT)
SEP DATA = 1
SEP DATA = 0
BUF ADDR = OVFLW
BUF ADDR
*- OVFLW
MISClK = F
IN IT BUFF ADDR
REG FOR COUNT
OF 4096
[PREAMBLE
FAilURE COUNT]
MISClK =T
120. -CNTR
[ERROR CODE
NON EXISTENT
PREAMBLE]
BUF ADDR
A
*- OVFLW
BUF ADDR = OVFLW
130. -+ CNTR
[ERROR CODE
lOAM START
FAilURE)
-24-CNTR
[0 BIT COUNT)
l-CRCTWICE
[JAM 2 BITS OF
lOAM OR DAM)
NOTES:
B
All numerals are decimal
unlllSS subscripted.
LEGEND
MISCLK = F
CNTR
067, - SR
IClR SR7 FOR
COMPARISONS)
*-
OVFLW
CNTR =OVRlW
I
«
(
c
I
)
)
INDICATES CAll
TO SUBROUTINE
BEGINNING OF
A SUBROUTINE
BRANCH TO OR
BEGINNING OF
A ROUTINE
I
ACTIONS
G
fAIT 401'5
OR SEP ClK
WAIT 401'5
FOR SECOND CEll
INIT BUFF ADDR
REG FOR 4096
COUNT
[NOSTART
COUNT]
I
401'5
l,p
DATA = 1
d:J
WAIT 401'5
FOR SEPClK
I
SEP DATA = 1
SEP ClK
MISClK = F
MISClK = T
SEP DATA = 0
*-
SEP DATA - 0
~
FI BUFFR
IR REG
:R PREAMBLE
L COUNT]
BUF ADDR
401'5
SEPClK
1 ~CRC THREE
TIMES
[JAM 3MORE
AM BITS]
SEP DATA = 1
OVFlW
MISClK = F
WAIT 40,us
FOR THIRD CELL
MISClK '"T
SEP ClK
BUF ADDR
*- OVFlW
40 IlS
BUF ADDR = OVFlW
130. ~CNTR
[ERROR CODE
lOAM START
FAilURE]
1
1 --CRC TWICE
[JAM 2 BITS OF
lOAM OR DAM]
NOTES:
SEP DATA =0
SEP DATA = 1
All numerals ara decimal
unless subscripted.
LEGEND
MISClK = F
I
C
(
I
)
)
MISClK =T
INDICATES CALL
TO SUBROUTINE
BEGINNING OF
A SUBROUTINE
BRANCH TO OR
BEGINNING OF
A ROUTINE
ACTIONS
CP·1549
Figure 5-17 FINDHD and GETDAM Subroutines
Flowchart (Sheet 2 of 2)
5·31
(TARTRK)--+ SR
(GET 1'S COMPLE·
MENT OF TRACK
ADDRESS]
-8--+CNTR
[FOR OBYTE
BIT COUNT]
CNTR
SEPCLK
0--+ FLAG
[PREPARATION
FOR SECTOR
COMPARE]
=F
CNTR =OVFLW
SEP DATA
SEP DATA - SR7
CNTR =OVFLW
SEP CLK = F
SEP CLK = T
SEPCLK = T
*" OVFLW
CNTR
SHIFT SR 7 TIMES
INSERT ZERO
(GET TRACK
COMPARE RESULT
TO SR71
*- OVFLW
*" SR7
-24 ... CNTR
(FOR 0 BYTE AND
2 BYTE CRC BIT
COUNT)
SR7 = 0
(SR)"" ERREG
[SET ERREG BIT 0
TO INDICATE A
TRACK SEEK
ERROR IF THIS
IS LEGAL HDR]
SEP CLK
CNTR
*" OVFLW
=T
SEP CLK = F
CNTR =OVFLW
c
(TAR SEC)", SR
(ONES COMPLE·
MENT OF SECTOR
ADDRESS]
-8-+CNTR
(FOR SECTOR
BIT COUNT]
NOTES:
(CNTR) + 1-+CNTR
(INCREMENT BIT
COUNTER]
*-
OVFLW
All numeral!
unless
SEPCLK = T
CNTR -OVFLW
CNTR
CNTR =OVFLW
CNTR
-16 ... CNTR
[BIT COUNT FOR
CRCCHECK)
SEP CLK = F
LEGEND
c
+- OVFLW
SEP DATA
= SR7
CRC16=0
1--+ FLAG
[TO INDICATE
SECTOR
MISMATCH]
SUbSCl
CRC 16 - 1
140..... ERREG
(ERROR CODE FOR
HEADER CRC
ERROR)
c
c
c
C
"""----:BDSRT
BADHDR
)
I
-8--> CNTR
(FOR BYTE
BIT COUNT)
o
FLAG
FLAG = 1
SEP ClK = F
0
(TEMPBI- CNTR
(GET DAM
BADSTART COUNT)
CNTR =OVFlW
CNTR"* OVFlW
~
(ERREG --+ SR
[GET RESULT OF
TRACK COMPARE)
]
CNTR -OVFlW
]
SHIFT SR 7 TIMES
INSERT ZERO
[GET TRACK
COMPARE RESULT
TO SR7)
CNTR"* OVFlW
-24-CNTR
(FOR 0 BYTE AND
2 BYTE CRC BIT
COUNT)
CNTR =OVFlW
]
SR7= 0
SEP ClK = T
CNTR '" OVFlW_
CNTR = OVFlW
CNTR '" OVFLW
SR7 = 1
170.--+ CNTR
[ERROR CODE
FOR TOO MANY
TRIES FOR A
DATA MARK)
150. -CNTR
(ERROR CODE FOR
POSITIONING
ERROR)
SEPClK = F
(TEMP B) --> CNTR
(GET OUTER
BADSTART
COUNT)
:NTR = OVFlW
TAR SECI--> SR
ONES COMPlE~ENT OF SECTOR
lDDRESS)
-8-CNTR
[FOR SECTOR
BIT COUNT)
NOTES:
CNTR"* OVFlW
CNTR = OVFlW
CRC 16 = 0
CNTR"* OVFlW
CNTR =OVFlW
unless subscripted_
-16--+ CNTR
(BIT COUNT FOR
CRCCHECK)
SEP ClK = F
All numerals are decimal
160.-->CNTR
[ERROR CODE
FOR TOO MANY
TRIES FOR
AN lOAM)
lEGEND
I
CRC 16 = 1
140. --> ERREG
[ERROR CODE FOR
HEADER CRC
ERROR)
C
(
I
)
)
INDICATES CAll
TO SUBROUTINE
BEGINNING OF
A SUBROUTINE
BRANCH TOOR
BEGINNING OF
A ROUTINE
ACTIONS
CP-1601l
Figure 5-18 HDRCOM, BDSRT, BADHDR Routines Flowchart
5-32
DATAIN =0
ICNTRI->SR
[BIT COUNT WILL
RESIDE IN SHIFT
REG]
CNTR.;. OVFLW
FLAG = 0
CNTR =OVFLW
SHIFTSR, INSERT
ONE
[COMPLEMENT OF
DATA TO SR]
WAITRN
[WAIT FOR RE·
SPONSE FROM
INTERFACEI
FLAG = 1
DATAIN = 1
CNTR -OVFLW
CNTR ,*OVFLW
TOG FLAG
[FOR A CLOCK FLUX
TRANSITION IF
WRITE GATE IS SET]
FLAG - 1
FLAG -0
STALL 323.2jl.
[WAIT 10.1 BYTES
FOR WRITE TURN
ON TIME]
CNTR .;.OVFLW
CNTR=OVFLW
END AROUND
SHIFT OF UPPER
5 BITS OF STAT
IN THE SR
12 BIT MODE
NOTES:
8BITMODE
CNTR.;. OVFLW
All num....1s are decimal
unl_ sub_iptlld.
LEGEND
I
C
(
I
)
)
INDICATES CALL
TO SUBROUTINE
70. -CNTR
[ERROR CODE
FOR NONEXIS·
TENT SECTOR
HEADER]
CNTR.;. OVFLW
CNTR =OVFLW
BEGINNING OF
A SUBROUTINE
BRANCH TO OR
BEGINNING OF
A ROUTINE
ACTIONS
CP·1610
Figure 5-19 DELAY, FINDSE, WRTOS,
G ETWRD Subroutines Flowchart
5-33
B
CNTR ",OVFLW
CNTR =OVFLW
HOME=T
RUN=T
RUN=F
RUN=T
HOMEz F
c
RUN=F
(CNTR) +2- CNTR
[INCREMENT
RETURN ADDRESS
BY TWO]
SR7 = 0
SR7
=1
~
45.87 1"S
RUN = T
-200-CNTR
[PASS MULTI·
PLiER TO
DELAY]
SR7=
CNTR= OVFLW
-30-+ CNTR
[PASS MULTI·
PLiER TO
DELAY]
a
SR7 = 1
SR7
=1
SR7=O
DELAY
(20MS FOR HD
LOAD SETTLE
TIME]
SETSTEPHD
CLRSTEPHD
[GIVE SECOND
STEPPULSEI
CNTR *,OVFLW
NOTES:
All numerals are decimal
unlass subscripted.
LEGEND
I
C
(
I
)
)
INDICATES CALL
TO SUBROUTINE
B
BEGINNING OF
A SUBROUTINE
BRANCH TO OR
BEGINNING OF
A ROUTINE
ACTIONS
CNTR '" OVFLW
CNTR zOVFLW
cP·1607
Figure 5·20 STEPHD, WAITRN, MAGCOM Subroutines Flowchart
5·34
A
o
B
INDEX = F
CNTR
z
INDEX =T
CNTR #0 OVFLW
OVFLW
CNTR #0 OVFLW
CNTR =OVFLW
CNTR=OVFLW
I
FLAG
CNTR '" OVFLW
CNTR =OVFLW
CNTR'" OVFLW
1
~
0
CNTR =OVFLW
CNTR #0 OVFLW
CNTR = OVFLW
CNTR ."OVFLW
FLAG = 0
FLAG = 1
NOTES:
All numerals are decimal
unless subscript..t.
LEGEND
I
C
(
I
}
)
INDICATES CALL
TO SUBROUTINE
BEGINNING OF
FLAG = 0
A SUBROUTINE
BRANCH TO OR
BEGINNING OF
A ROUTINE
WRTEN = T
WRTEN = F
ACTIONS
A
B
o
Figure 5·21
o
B
INDEX; F
INDEX = T
CNTR",OVFLW
CNTR",OVFLW
CNTR =OVFLW
CNTR -OVFLW
I
CNTR +OVFLW
1
FLAG = 0
CNTR",OVFLW
:LW
FLAG -1
CNTR =OVFLW
CNTR",OVFLW
CNTR =OVFLW
CNTR ",OVFLW
FLAG
m
0
FLAG
~
1
,SCALL
)UTINE
~G
OF
FLAG = 0
"'TINE
FLAG - 1
TOOR
~G
OF
~E
WRTEN =T
A
B
WRTEN = F
o
CP·16011
Figure 5-21 DIF and CHKRDY Subroutine Flowchart
5-35
5.2.6 Read/Write Electronics
A detailed block diagram of the read/write electronics is shown in Figure 5-22. The read/write electronics can be
separated into four functions:
1.
Diskette position
2.
Head read/write circuitry
3.
Head load control and solenoid drivers
4.
Stepper motor control and motor drivers
5.2.6.1 Diskette Position - Track 0 and index hole detection are accomplished by an LED-phototransistor pair.
There are separate circuits for drive 0 and drive 1 for a total of four sensing circuits. A schematic diagram of the
circuitry appears on page D4 of the RX8/RXll Print Sets.
The six sensor indicator lines are input to a 74157 data selector shown on page D6, which outputs track 0 and index
hole sensing information to the pCPU controller. The 74157 is data-selected by the SEL 1 H signal from the pCPU
controller, indicating which drive is being used.
5.2.6.2 Head Read/Write Circuitry - The head read/write circuitry is shown on page D3 and is composed of a write
section and a read section.
Head writing is controlled by six signals from the pCPU controller as shown in Figure 5-22. Each of these signals is
further explained in Paragraph 5.1.4. During a write operation, D6 WT GATE H initiates a Write command, and D6
ERASE H activates the tunnel erase drivers. The data stream D6 WT DATA H is amplified by the head write current
amplifiers and directed to the proper drive by D6 SEL DKO Hand D6 SEL DK 1 H signals. Head writing is inhibited
by D6 SEL WT PROT L or D6 DC LO L signals. The signal ABOVE TK 43 H controls proper write current to the
heads.
Head reading is accomplished by the circuitry shown on page D3. The diode and resistor circuitry on the R/W BUS +
and R/W BUS - protect the 733 preamplifier during a write operation. The fIlter following the preamplifier
eliminates unwanted head noise. The next 733 amplifier stage drives the peak detection circuitry, composed of a
differentiator and crossover detector {l414}. The output of the 1414 is fed to 74123s (monostables), which are used
as pulse shapers. RAW DATA L, which represents digitized data from the diskette, is sent to the pCPU controller.
5.2.6.3 Head Load Control and Solenoid Drivers - Head load control and solenoid driver circuitry is shown on
page D6. A D6 LOAD HEAD H signal from the pCPU controller causes either head load solenoid to be activated,
depending on whether signal D6 SEL DKI H is high or low. D5 INIT L, an initialize signal from the stepper motor
control, will reset the drive and cause the head to unload.
5.2.6.4 Stepper Motor Control and Motor Drivers - Stepper motor control and motor driver circuitry is shown on
page D5. A separate and identical control section and motor driver section exists for each drive. Signals D6 SEL DK 1
Hand D6 SEL DKO H determine which drivers to activate.
D6 OUT H determines the direction of movement of the head in response to the pulse D6 STEP L from the pCPU
controller. If D6 OUT H is asserted, the head moves outward toward track 0; if it is negated the head moves inward
toward track 77. The two 7473s and the 7450 in the two control sections are connected as up/down counters to
control the four motor driver transistors. In moving OUT, the counter counts up to turn on the driver transistors to
move the head outward. In moving IN, the counter counts down to turn on the driver transistors to move the head
inward. Each track position requires two phases of the counter. Therefore, two step pulses are required for each
track moved.
5-36
TO
TO
~cPU
DRIVES
CONTROL
DKO
lDKo INDX .H
INDEX
SENSOR
SEL TRK 0 H
J
DKO
DK1
INDEX
SENSOR
DK1
DKO
TRACK
SENSOR
DKO
OK!
TRACK
SENSOR
DKI
IDK1 INDX
J
SEL INDX H
H
I DKO TRK 0 H
ABOVE TK 43 H
74157
DATA
SELECTOR
WT GATE H
ERASE H
WT DATA H
I
DC LO L
I DKt TRKO H
SEL OK 0 H
r
SEL OK 0 H
.A
DKO HEAD (
DK1 HEAD (
HEAD WRITE
CURRENT
AMPLIFIERS
~
...
A
HEAD WRITE
CONTROL
;-
..,-
SEL DK 1 H
VI
W
....
......:J
:.
~
DKO
HEAD LOAD
DK1
HEAD LOAD
DKO
STEPPER
-A
..)
A
<"""
,
.A
PEAK
DETECTOR
RAW DATA L
SEL DK! H
~
HEAD
LOAD
CONTROL
INIT L
LOAD HEAD H
....
A
'-
'"
A
DK1
STEPPER
HEAD READ
CURRENT
AMPLI FIERS
<"""
STEPPER
MOTOR
CONTROL
AND
DRIVERS
--
INIT L
--
DC LO L
SELDKIH
SEL DKO H
STEP L
OUT H
CP-1692
Figure 5-22 Read/Write Electronics Block Diagram
5.2.7 Mechanical Drive
The mechanical drive consists of four major pa~ts:
1.
Drive mechanism
2.
Spindle mechanism
3.
Positioning mechanism
4.
Head load mechanism
The complete mechanical structure of the drive is shown in Figure 5-23, and each section is described in the
following paragraphs.
DISK
CENTERING CON E
HEAD LOAD
ACTUATOR
READ/WRITE
HEAD
...
<,
HEAD
CARRIAGE
HELIX
STEPPER
MOTOR
COOLING
FAN
DISK
DRIVE
MOTOR
CP-l138
Figure 5-23 Disk Drive Mechanical System
5-38
5.2.7.1 Drive Mechanism - The drive system provides rotational diskette movement using a single-phase motor
selected to match primary power of the controller system (Figure 5-24). The diskette drive attains ready status
within 2 seconds of primary power application.
A cooling fan is mounted on one end of the drive motor shaft. Rotation of the diskette is provided by a belt and
pulley connected to the other end of the motor shaft. The drive pulley and belt are selected for either 50 or 60 Hz
power to achieve a diskette rotational speed of 360 rpm. See Paragraph 2.2.3.2 for complete input power
modification requirements.
SPINDLE DRIVE
PULLEY
IMPELLER
DRIVE
BELT
DRIVE
MOTOR
DRIVE MOTOR
PULLEY
CP-1595
Figure 5-24 Drive Mechanism
5.2.7.2 Spindle Mechanism - The spindle mechanism consists of a centering cone and a load plate. In the unload
position, the load plate is pivoted upward, creating an aperture through which the floppy diskette is inserted. In this
position, the centering cone disengages the diskette from the drive mechanism.
To load a diskette, the operator inserts the floppy diskette and presses down on the load handle, which latches the
load plate in the operating mode. The centering cone is mechanically linked to the load plate and is activated at the
same time. (Figure 5-25).
The centeringcone is an open splined nylon device that performs two functions:
1.
Engages the diskette media and drive mechanism.
2.
Positions the diskette media in ,the correct track alignment.
As the load plate is pivoted to the load position, the centering cone enters the floppy diskette center. At
approximately 80 mils from the fully down position, a centering cone expander is automatically activated. This
device then expands the centering cone, which grips the inner diameter of the diskette media in the correct track
alignment.
The track o position serves as the diskette drive reference track. This position is sensed by a phototransducer, which
generates track 0 status. This status is sent to the controller for initial track positioning. The controller generates
step pulses to position the carriage from the current track to a new track.
5.2.7.3 Positioning Mechanism - The positioning mechanism comprises a carriage assembly and a bidirectional
stepper motor (Figure 5-26). The stepper motor rotational movements are converted to linear motion by the rotor
helix drive.
The read/write head mount rides in the grooved helix shaft and is held in horizontal alignment by the way. When the
stepper motor is pulsed, the helix drive rotates clockwise or counterclockwise, moving the mount in or out.
5-39
I
EXPANDER SPRING
~ CENTERING CONE
i
CENTERING CONE
........+ - - - EXPANDER
SPINDLE DRIVE
HUB
CP-1575
Figure 5-25 Centering Cone and Drive Hub
TRACK 00
TRANSDUCER
FIXED WAY
READ/WRITE
HEAD
CARRAGE
ASSEMBLY
HEAD LOAD
ARM
I
I
I
\
I
..../-
~STEPPER
MOTOR
HELIX DRIVE
FRONT
BEARING
MOUNT
CP-1576
Figure 5-26 Positioning Mechanism
540
The stepper motor includes four pairs of quadrature windings. In detent, current flows in one winding and maintains
the rotor in electro-magnetic detent. Forpositioning, one or more step pulses are sequentially applied to quadrature
windings, causing an imbalance in the electro-nYagnetic field. Consequently, the stepper motor rotor revolves through
detent positions until the step pulses are halted. The rotor then locks in that position. The sequence in which the
stepper motor quadrature windings are pulsed dictates rotational direction and, subsequently, higher or lower track
addressing from a relative position.
5.2.7.4 Head Load Mechanism - The head load mechanism is basically a relay driver and a solenoid. When
activated by signal LD HD from the controller, the spring-loaded head load pad is released and rests in parallel
alignment with the floppy diskette surface. Part of the casting provides the lower alignment dimensional surface,
while the head load solenoid bar provides the upper alignment surface.
In the load position, the read/write head tang rides between these two alignment surfaces and keeps the read/write
head in contact with the diskette surface. The load pad is located behind the read/write head and holds the floppy
diskette flat against the lower alignment block.
To minimize diskette surface and head wear, the head is automatically disabled by the controller if no new
command has been issued within 48 ms. Head settling time is 20 ms.
S-41
CHAPTER 6
MAINTENANCE
6.1 RECOMMENDED TOOLS AND TEST EQUIPMENT
Table 6-1 lists the recommended tools and test equipment for maintenance of the RX8/RXll Floppy Disk System.
Table 6-1
Recommended Tools and Test Equipment
Equipment
Manufacturer and Model/part No.
Multimeter
Triplett 310 or Simpson 360
Oscilloscope
Tektronix 453
Oscilloscope Probes,
Voltage (XI0, two required)
Tektronix P6010
Field Service Tool Kit
DEC 29-18303
Head Cleaning Kit
(includes TEX pads and wand)
DEC 22-00007
DEC 29-19557
DEC 29-19558
RX8/RX11 Service Kit
DEC-O-LOG
DEC ECO log and computer on-line synopsis
6.2 CUSTOMER CARE
Although there is no scheduled preventive maintenance, there are two tasks that should be performed on an
as-needed basis.
1.
Clean the exterior of the RXOI with a damp cloth, using either a solution of nonabrasive cleaner or mild
soap.
2.
Examine the air filter (Figure 6-1) and clean the element as necessary. Use water and a mild soap, drying
thoroughly before reinstalling.
6-1
JUMPER P1
SHIPPING
RISTRAINT (RID)
FILT!R
POWER PLUGS
FILTER
7436-12
Figure 6-1 RXO I, Rear View
6.3 REMOVAL AND REPLACEMENT
The following steps define the procedures for replacing the subassemblies of the RX8/RXI1 Floppy Disk System.
6.3.1 Module Replacement
Floppy Disk Controller, M7726 (Figure 6-6)
1.
Remove power from the RXOL
2.
Unscrew the two captive screws on the right side of the module and raise the module to the servicing
position.
3.
Remove the plugs in connectors J 1, J2, and J4.
4.
Lower the module and remove the three screws holding the module onto the hinge.
5.
Remove the module and remove the two captive screws.
6.
To install a module, insert the two captive screws removed from the original module and perform the
reverse of the steps 1-5.
6-2
Read/Write Control, M7727 (Figure 6-6)
1.
Remove power from the RXOI.
2.
Raise the floppy disk control module to the servicing position.
3.
Remove the plugs from connectors on the module, ensuring that they do not drop into the drive.
4.
Remove the six screws holding the module to the frame and remove the module.
s.
To install a M7727, replace the screws and plugs removed in steps 3 and 4, ensuring that they are
reinstalled into the correct connector (Table 6-2).
Table 6-2
M7727 Connectors
Description
Connector
11
J2
DKO(P3)
DKO(P4)
DKO(PS)
DKO(P6)
DKO(P7)
DKO(P8)
DK1(P3)
DK1(P4)
DK1(PS)
DK1(P6)
DK1(P7)
DK1(P8)
Disk drive interface cable
Power from H771 power supply
Head cable
Stepper motor
Head load solenoid
Index signal
Track 0 signal
Write protect*
Head cable
Stepper motor
Head load solenoid
Index signal
Track 0 signal
Write protect*
*Not used.
H771 Power Supply Regulator, 70-10718 (Figure 6-6)
1.
With the power off, remove the plug from the regulator.
2.
Unscrew the leads going to the capacitors, checking with the H771 prints to ensure that the wiring
matches the prints.
3.
Remove the plugs from the M7726 and M7727.
4.
Remove the six screws holding the regulator to the power supply chassis.
S.
Replace the regulator by performing the reverse of steps 1-4.
6-3
6.3.2 Drive Placement (Figure 6-6)
1.
With the power removed, remove the power plug in the rear of the drive (Figure 6-1).
2.
Remove the plugs for this drive (Table 6-2).
3.
Loosen the six screws holding the drive to the chassis.
4.
While holding the drive, remove the screws from the four corners.
5.
Carefully remove the two remaining screws without allowing the drive to drop down.
6.
Slowly lower the drive, guiding the wiring as the drive islowered.
7.
To install a drive, place the two center screws in the holes in the chassis.
8.
Raise the drive, guiding the wiring through the hole.
9.
With the drive centered, start the two screws carefully so as not to cross-thread them. Do not tighten
these screws all the way.
10.
Start the remaining screws, being careful not to cross-thread them.
II.
Tigh ten all screws.
12.
Insert the plugs listed in Table 6-2.
13.
Insert the power plug.
6.4 CORRECTIVE MAINTENANCE
Figure 6-2, Sheet I, illustrates the method to be used when correcting a fault in the RX8/RXII system. The proper
use of the KMII module is described in Paragraph 6.4.2.
6.4.1
Errors
6.4.1.1 Interface Diagnostic in Memory - Use Figure 6-2, Sheet 2.
6-4
NO
SWITCH ABOUT
15 TIMES
(LlSTINGI
NO
NO
(Ref. 54·113981
NO
NO
YES
PERFORM
DATA
RELIABILITY
TEST
INSERT KM11
MAINT. MODULE
WIO RUN ENABLE
(FIGURE 6-41
NO
REFER TO
DIAGNOSTIC
DOCUMENT FOR
TROUBLE·
SHOOTING
INFORMATION
NO
NO
USE
OSCILLOSCOPE
TO
TROUBLESHOOT
NO
YES
POWER OFF.
REPLACE
FALTY UNIT
c
3
2
c
NO
SWITCH ABOUT
15TIMES
(L1STINGI
FACE ONLY TESTS
NO
(Ref. 54-113981
NO
NO
NO
YES
PERFORM
DATA
RELIABILITY
TEST
INSERT KM11
MAl NT. MODULE
WIO RUN ENABLE
(FIGURE 6-41
NO
REVERSED
(FIG. 6-31
REFER TO
DIAGNOSTIC
NO
USE
OSCILLOSCOPE
TO
TROUBLESHOOT
NO
EXIT TO
APPROPRIATE
ROUTINE
I
YES
POWER OFF,
REPLACE
FALTY UNIT
USE
OSCILLOSCOPE
TO
TROUBLESHOOT
INTERFACE
CABLE
NO
c
o
c
3
2
3
CP-1542a
Figure 6·2 Troubleshooting Flow (Sheet 1 of 2)
6-5
E
NO
CHECK SEL TRK OH
SIGNAL
(M7726-D51
(M7727-D61
NO
YES
CABLE
USE
OSCILLOSCOPE
TO
TROUBLESHOOT
PERFORM
THE ACCEPTANCE TESTS
(CHAPTER 2.
PARAGRAPH
2.4.41
USE KM11 &
OSCILLOSCOPE
TO
TROUBLESHOOT
CP-1542b
Figure 6-2 Troubleshooting Flow (Sheet 2 of 2)
6-6
7436-1
Figure 6-3 BC05L-15 Cable (Reversed) (Sheet 1 of 2)
6-7
7436-16
Figure 6-3 BC05L-15 Cable (Correctly Inserted) (Sheet 2 of 2)
6-8
6.4.1.2 Diagnostics Not in Memory - Since the RX8/RXll may be the only input device for a system, there may
not be a way to input the diagnostics into the system. In that event, the following routines (Figures 6-4 and 6-5) and
the use of the Initialize Diagnostic Routine residing in the controller's firmware may aid in the repair of the floppy
disk system.
1.
Load the following routines (Figures 6-4 and 6-5) into main memory.
2.
Starting at location 200 (RX8) or 1000 (RXII), initiate the program.
3.
Examine the status locations for failure information.
ESTAT,RI
DSTAT,RO
EREG,R2
DRSTAT
4.
A good pass with a media installed in drive 0 will be:
ESTAT/Os
DSTAT/4 8 or 104 8
EREG/Os
DRSTAT/204 8 or 3048
5.
Neither the read/write controller module nor the drives will cause the program to continuously loop on
the first check of the Done flip-flop.
6.
If the program halts at any location other than the halt at the end of the program, the controller or
interface module could be at fault.
7.
If the program halts at the end of the program with the following status, the controller is most likely at
fault.
ESTAT/4 8
DSTAT/Os
EREG/60 8
DRSTAT/X
8.
All other valid error status will probably be caused by the read/write controller module, the drive, or the
floppy disk controller module. It should be noted that a Read Sector is not performed on drive 1;
therefore, it is possible for a fault to inhibit reading on both drives without reporting that information.
6.4.2 KM 11 Usage
The KMII maintenance module may be used to single-step through a routine in the floppy controller's firmware. It
should be noted that at times the controller will be accessing a signal produced from the media; in this case, the
KM 11 cannot single-step the microprogram. For the correct method of inserting the KM 11, refer to Figure 6-6. The
representation of the lights and use of the switches is shown in Figure 6-7. To start a functional routine, the
command must be issued from the central processor.
6-9
0200
0201
0202
0203
0204
0205
0206
0207
0210
0211
0212
0213
0214
0215
0216
0217
6771
6772
6774
6775
6777
0200
6775
5200
6774
5207
6772
3227
5211
6772
3226
1225
6771
6775
5213
6774
7410
7402
IRX8 STATUS ROUTINE
LCD=6771
XDR=6772
SER=6774
SDN=6775
JNIT=6777
*0200
SDN
JMP .-1
SER
JMP .+4
XDR
DCA F.RSTAT
JMP .+3
XDR
OCA DNSTAT
TAO RDEREG
LCD
SDN
JMP .-1
SER
SKP
HLT
0220
0221
0222
0223
0224
0225
0226
0227
0230
6772
3230
7402
6777
5200
0016
0000
0000
0000
XDR
DCA F.REG
HLT
INIT
JMP 200
RDf.:REG, 0016
DNSTAT, 0
ERSTAT, 0
0
EREG,
ISKIP ON DONE PLAG
IWAIT POR fLAG
ISKIP ON ERROR PLAG
IBRANCH ON NO ~RROR
ITRANSFER DATA - RXOI STATUS TO AC
ISAVE IN LOCATION ERROR STATUS
IARANCH OVER THIS HASH
ITRANSFER DATA - RXOI STATUS TO AC
ISAVE IN LOCATION DONE STATUS
IGET READ ERROR REGISTER COMMAND
ILOAD THE COMMAND REGISTER
ISKJP ON DONE PLAG
IWAIT FOR DONE FLAG
ISKIP ON ERROR
IUNCOND ITIONAL SKIP
IFATAL ERROR - FAILURE TO EXECUTE
IA "READ ERROR REG" COMMAND
ITRANSFr.R DATA - RXOI ERROR REG TO AC
ISAVE IN LOCATION ERROR REG
IREPLACE WITH NOP (7000 ) TO LOOP
IINITIALIZE RX01
ILOOP
$
Figure 6-4 RX8 Status Routine
001000
001006
001010
001014
001016
001022
001030
001036
001040
001044
001046
177170
177172
000000
000001
000002
001000
032767
001774
005767
100424
010067
012767
032767
001774
005767
100001
000000
001050
001054
016702
000000
176116
001056
001064
001066
001072
012767
000745
016701
000753
000001
040001
000040
176162
176154
176150
000017
000040
176140
176132
176124
176100
176104
:RXll STATUS ROUTINE
:RO = STATUS REG IF DONE COMES UP & NO ERROR FLAG
:Rl = STATUS REG IF DONE COMES UP & ERROR FLAG
;R2 = RXOI F:RFlOR REGISTER CONTENTS (SPECInc ERROR CODE)
RXCS=177170
RXDA=177172
RO=%O
Rl=%1
R2=%2
.=1000
:TEST DONE BIT
START: BIT 1I40,RXCS
: WAIT rOR DONE
BEO START
;TEST ERROR BIT (MSB)
TST Rxes
;BRANCH TO INIT~R ON INITIALIZE ERROR
8MI INITER
;PUT DONE STATUS IN RO
MOV RO,RXDB
;ISSUE READ ERROR REG COMMAND & GO BIT
READ:
MOV U7,RXCS
;TE5T DONE BIT
READ1: BIT #40,RXCS
;WAIT rOR DONE
REO READI
; TEST ERROR BIT (MSB)
TST RXCS
BPL READ2
:FlRANCH TO READ2 If NO ERROR
HALT
;FATAL ERROR - ERROR OCCURED
:IN "READ ERROR REG" COMMAND
;PUT SPECIFIC ERROR CODE IN R2
READ2: MOV RXDF-I,R2
;NORMAL HALT - REPLACE WITH NOP (240) TO LOOP
HALT
MOV #40001,RXCS
BR START
INITER: MOV RXDB,Rl
BR READ
;ISSUE RXOI INITIALIZE & GO BIT
;START OVER
;P0T ERROS STATUS IN Rl
;GO READ ERROR REGISTER
• ~~N D
Figure 6-5 RX11 Status Routine
6-10
7436-8
Figure 6-6 KM 11 Maintenance Module Inserted
6-11
I
HALT
RUN
ENAB
C
ERROR
HLT
~
INST1
INSTO
r--
I
I
I
CONTINUE
~
CO
C1
I
PC71
FIELD
I
I
J
I
PCO
PROGRAM COUN TER
UNUSED
C
I
SELECT FIELD
I
I
I
I
I
I
I
I
I
I
I
I
COUN TER
I
I
I
I
CP-l!!43
Switch
RUNENAB
CONTINUE
ERRORHLT
Function
ON:
OFF:
ON:
OFF:
ON:
OFF:
M7726 Clock
Maint. Clock Pulses (Continue)
Advance Controller Firmware Once
Halt Controller When Error Detected
Do Not Halt On Error Condition
Lights
Function
HALT
INST 1 and 0
SELECT FLD
CO and Cl
FIELD
PROGRAM COUNTER (0-7)
COUNTER (0-7)
Firmware Halted
Instruction Bits
Selects 1 of 16 Conditions (Depends on Instruction)
Control Functions (Depends on Instruction)
ROM Field
(Halted) Address +1 of Instruction Displayed
Displays Contents of Counter Register
Figure 6-7 KM 11 Light and Switch Definitions for RXO 1
6-12
Table 6-3
Power Supply Output Voltages
Voltage
+5Vdc
+9.5 Vdc
Tolerance
~
Measured At
~+5.25
+4.75 Vdc
Vdc
Ripple ~ 200 mV (p-p)
Pl-4
P2-4
~+9.0Vdc
P2-7
~
+10.3 Vdc
Ripple ~ 2.0 V (p-p)
+24 Vdc
~
+23.6 Vdc
P1-1
~+28.0Vdc
Ripple
-5Vdc
~
1.2 V (P-p)
~
-4.6 Vdc
-5.6 Vdc
Ripple ~ 200 mV (p-p)
Pl-6
~
+10 Vac
J1-1,3
+24 Vac
J1-2, 4
NOTE
This table should be used in conjunction with the DC Power
Checks perfonned with Figure 6-2, Sheet 1.
6-13
1
1
Reader's Comments
1
1
RX8/RX 11 FLOPPY DISK SYSTEM
MAINTENANCE MANUAL
EK-RXOI-MM-002
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