datasheet for WM8731SEDS/V by Wolfson Micro

w

WM8731 / WM8731L

Portable Internet Audio CODEC with Headphone Driver and Programmable Sample Rates

DESCRIPTION

The WM8731 or WM8731L (WM8731/L) are low power stereo CODECs with an integrated headphone driver. The

WM8731/L is designed specifically for portable MP3 audio and speech players and recorders. The WM8731 is also ideal for MD, CD-RW machines and DAT recorders.

Stereo line and mono microphone level audio inputs are provided, along with a mute function, programmable line level volume control and a bias voltage output suitable for an electret type microphone.

Stereo 24-bit multi-bit sigma delta ADCs and DACs are used with oversampling digital interpolation and decimation filters. Digital audio input word lengths from 16-32 bits and sampling rates from 8kHz to 96kHz are supported.

Stereo audio outputs are buffered for driving headphones from a programmable volume control, line level outputs are also provided along with anti-thump mute and power up/down circuitry.

The device is controlled via a 2 or 3 wire serial interface.

The interface provides access to all features including volume controls, mutes, de-emphasis and extensive power management facilities. The device is available in a small 28lead SSOP package or the smaller 28 lead quad flat leadless package (QFN).

FEATURES

•

Highly Efficient Headphone Driver

- ADC SNR 90dB (‘A’ weighted) at 3.3V, 85dB at 1.8V

- DAC SNR 100dB

(‘A’ weighted) at 3.3V, 95dB at 1.8V

- Playback only 22mW, 8mW (‘L’ Variant)

- Analogue Pass Through 12mW, 3.5mW (‘L’ variant)

- 1.42 – 3.6V Digital Supply Operation

- 2.7 – 3.6V Analogue Supply Operation

- 1.8 – 3.6V Analogue Supply Operation (‘L’ Variant)

•

ADC and DAC Sampling Frequency: 8kHz – 96kHz

•

Selectable ADC High Pass Filter

•

2 or 3-Wire MPU Serial Control Interface

•

Programmable Audio Data Interface Modes

- I

2

S, Left, Right Justified or DSP

- 16/20/24/32 bit Word Lengths

- Master or Slave Clocking Mode

•

Microphone Input and Electret Bias with Side Tone Mixer

•

Available in 28-lead SSOP or 28-lead QFN package

APPLICATIONS

•

Portable MP3 Players and Recorders

•

CD and Minidisc Recorders

•

PDAs / smartphones

BLOCK DIAGRAM

WOLFSON MICROELECTRONICS plc

To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews/

Production Data, April 2009, Rev 4.8

Copyright

©2009 Wolfson Microelectronics plc

WM8731 / WM8731L

Production Data

TABLE OF CONTENTS

DESCRIPTION .......................................................................................................1

FEATURES.............................................................................................................1

APPLICATIONS .....................................................................................................1

BLOCK DIAGRAM .................................................................................................1

PIN CONFIGURATION - 28 PIN SSOP.................................................................3

ORDERING INFORMATION ..................................................................................3

PIN CONFIGURATION – 28 PIN QFN ...................................................................4

ORDERING INFORMATION ..................................................................................4

PIN DESCRIPTION ................................................................................................5

ABSOLUTE MAXIMUM RATINGS.........................................................................6

RECOMMENDED OPERATING CONDITIONS – WM8731 ...................................6

RECOMMENDED OPERATING CONDITIONS – WM8731L.................................6

ELECTRICAL CHARACTERISTICS – WM8731 ....................................................7

TERMINOLOGY ............................................................................................................ 9

POWER CONSUMPTION – WM8731 ..................................................................10

ELECTRICAL CHARACTERISTICS – WM8731L................................................11

TERMINOLOGY .......................................................................................................... 13

POWER CONSUMPTION – WM8731L................................................................14

MASTER CLOCK TIMING....................................................................................15

DIGITAL AUDIO INTERFACE – MASTER MODE ....................................................... 16

DIGITAL AUDIO INTERFACE – SLAVE MODE .......................................................... 17

MPU INTERFACE TIMING .......................................................................................... 18

DEVICE DESCRIPTION .......................................................................................20

INTRODUCTION ......................................................................................................... 20

AUDIO SIGNAL PATH................................................................................................. 21

DEVICE OPERATION ................................................................................................. 34

AUDIO DATA SAMPLING RATES............................................................................... 41

ACTIVATING DSP AND DIGITAL AUDIO INTERFACE .............................................. 45

SOFTWARE CONTROL INTERFACE......................................................................... 45

POWER DOWN MODES ............................................................................................ 47

REGISTER MAP ......................................................................................................... 49

DIGITAL FILTER CHARACTERISTICS ...............................................................54

TERMINOLOGY .......................................................................................................... 55

DAC FILTER RESPONSES .................................................................................56

ADC FILTER RESPONSES .................................................................................57

ADC HIGH PASS FILTER ........................................................................................... 58

DIGITAL DE-EMPHASIS CHARACTERISTICS ...................................................58

DIGITAL DE-EMPHASIS CHARACTERISTICS ...................................................59

APPLICATIONS INFORMATION .........................................................................60

RECOMMENDED EXTERNAL COMPONENTS .......................................................... 60

MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS........................................ 61

PACKAGE DIMENSIONS - SSOP .......................................................................62

PACKAGE DIMENSIONS - QFN..........................................................................63

IMPORTANT NOTICE ..........................................................................................64

ADDRESS: .................................................................................................................. 64 w PD, Rev 4.8, April 2009

2

WM8731 / WM8731L

PIN CONFIGURATION - 28 PIN SSOP

DBVDD

CLKOUT

BCLK

DACDAT

DACLRC

ADCDAT

ADCLRC

HPVDD

LHPOUT

RHPOUT

HPGND

LOUT

ROUT

AVDD

12

13

14

8

9

10

11

3

4

1

2

5

6

7

28

27

26

25

24

23

22

21

20

19

18

17

16

15

DGND

DCVDD

XTO

XTI/MCLK

SCLK

SDIN

CSB

MODE

LLINEIN

RLINEIN

MICIN

MICBIAS

VMID

AGND

Production Data

ORDERING INFORMATION

DEVICE

TEMPERATURE

RANGE

AVDD

RANGE

PACKAGE

WM8731SEDS/V -40 to +85 o

C

WM8731SEDS/RV -40 to +85 o

C

2.7 to 3.6V

28-lead SSOP

(Pb-free)

2.7 to 3.6V

28-lead SSOP

(Pb-free, tape and reel)

Note:

Reel quantity = 2,000

MOISTURE

SENSITIVITY LEVEL

PEAK SOLDERING

TEMPERATURE

MSL3 260°C

MSL3 260°C w

PD, Rev 4.8, April 2009

3

WM8731 / WM8731L

PIN CONFIGURATION – 28 PIN QFN

Production Data

ORDERING INFORMATION

DEVICE

TEMPERATURE

RANGE

WM8731LSEFL -40 to +85 o

C

WM8731LSEFL/R -40 to +85 o

C

WM8731SEFL -40 to +85 o

C

WM8731SEFL/R

Note:

Reel quantity = 3,500

-40 to +85 o

C

AVDD

RANGE

1.8 to 3.6V

1.8 to 3.6V

2.7 to 3.6V

2.7 to 3.6V

PACKAGE

28-lead QFN

(Pb-free)

28-lead QFN


28-lead QFN

(Pb-free)

28-lead QFN


MOISTURE

SENSITIVITY LEVEL

PEAK SOLDERING

TEMPERATURE

MSL1 260°C

MSL1 260°C

MSL1 260°C

MSL1 260°C w PD, Rev 4.8, April 2009

4

WM8731 / WM8731L

Production Data

PIN DESCRIPTION

28 PIN

SSOP

28 PIN

QFN

NAME TYPE

1 5 DBVDD Supply Digital Buffers VDD

DESCRIPTION

8 12 HPVDD Supply Headphone VDD

11 15 HPGND Ground Headphone GND

14 18 AVDD

15 19 AGND

Supply Analogue VDD

Ground Analogue GND

21 25 MODE Digital

22 26 CSB selection, active low, Pull up (see Note 1)

24 28 SCLK Digital

26 2 XTO Digital Crystal Output

27 3 DCVDD

28 4 DGND

Supply Digital Core VDD

Ground Digital GND

Note:

1. Pull Up/Down only present when Control Register Interface ACTIVE=0 to conserve power.

2. It is recommended that the QFN ground paddle is connected to analogue ground on the application PCB. w


5

WM8731 / WM8731L

Production Data

ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical

Characteristics at the test conditions specified.

ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device.

Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are:

MSL1 = unlimited floor life at <30

°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.

MSL2 = out of bag storage for 1 year at <30

°C / 60% Relative Humidity. Supplied in moisture barrier bag.

MSL3 = out of bag storage for 168 hours at <30

°C / 60% Relative Humidity. Supplied in moisture barrier bag.

CONDITION

Digital supply voltage

MIN MAX

-0.3V +3.63V

Analogue supply voltage

Voltage range digital inputs

-0.3V +3.63V

DGND -0.3V DVDD +0.3V

Voltage range analogue inputs AGND -0.3V AVDD +0.3V

Operating temperature range, T

A

-40

°C +85°C

Storage temperature after soldering

-65

°C +150°C

Notes:

1. Analogue and digital grounds must always be within 0.3V of each other.

2. The digital supply core voltage (DCVDD) must always be less than or equal to the analogue supply voltage (AVDD)

RECOMMENDED OPERATING CONDITIONS – WM8731

CONDITIONS

Digital supply range (Core)

Digital supply range (Buffer)

Analogue supply range

Ground

Notes:

AVDD, HPVDD

DGND,AGND,HPGND

1. DCVDD must be lower than or equal to DBVDD.

2. USB Mode should not be used with DCVDD lower than 2V

2.7 3.6 V

0 V

RECOMMENDED OPERATING CONDITIONS – WM8731L

CONDITIONS

Digital supply range (Core)

Digital supply range (Buffer)

Analogue supply range

Ground

Notes:

AVDD, HPVDD

DGND,AGND,HPGND

1.8 3.6 V

0 V

1. If DBVDD is lower than 2.5V, DCVDD must be at least 0.225V lower than DBVDD.

2. If DBVDD is higher than or equal to 2.5V, DCVDD must be lower than or equal to DBVDD.

3. USB Mode should not be used with DCVDD lower than 2V w PD, Rev 4.8, April 2009

6

WM8731 / WM8731L

Production Data

ELECTRICAL CHARACTERISTICS – WM8731

Test Conditions

AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T

A

= +25 o

256fs unless otherwise stated.

C, Slave Mode, fs = 48kHz, XTI/MCLK =

CONDITIONS

Digital Logic Levels (CMOS Levels)

Input LOW level

Input HIGH level

Output LOW

V

IL

V

IH

V

OL

Output HIGH

Power On Reset Threshold (DCVDD)

V

OH

DCVDD Threshold On -> Off V th

Hysteresis V

IH

DCVDD Threshold Off -> On V

OL

Analogue Reference Levels

Reference voltage (VMID)

Potential divider resistance

Line Input to ADC

Input Signal Level (0dB)

V

R

V

VMID

VMID

INLINE

0.3 x DBVDD V

V

DBVDD

V

0.9 V

0.3 V

0.6 V

AVDD/2

50k

V

Signal to Noise Ratio

(Note 1,3)

SNR

AVDD/3.3

85 90 dB

Dynamic Range (Note 3)

Total Harmonic Distortion

Power Supply Rejection Ratio

DR

THD

PSRR

A-weighted, 0dB gain

@ fs = 48kHz


@ fs = 96kHz


@ fs = 48kHz,

AVDD = 2.7V

A-weighted, -60dB full scale input

-1dB input, 0dB gain

90

88

85 90 dB

-84

0.006

-74

0.02 dB

%

50

45 dB

ADC channel separation

Programmable Gain

1kHz, 100mVpp

20Hz to 20kHz,

100mVpp

1kHz input

1kHz input

Rsource < 50

90 dB

-34.5 0 +12 dB

Programmable Gain Step Size

Mute attenuation

Input Resistance

Input Capacitance

R

INLINE

C

INLINE

0dB, 1kHz input

0dB gain

12dB gain

1.5 dB

80 dB

20k

10k

30k

15k

10 pF w


7

WM8731 / WM8731L

Production Data

Test Conditions


A

= +25 o



Microphone Input to ADC @ 0dB Gain, fs = 48kHz (40k Source Impedance. See Figure 12)

Input Signal Level (0dB) V

INMIC

AVDD/3.3


(Note 1,3)

85 dB

Dynamic Range (Note 3) DR 85 dB



THD

PSRR


0dB input, 0dB gain

1kHz 100mVpp

-60

50

-55 dB dB

45 dB

Programmable Gain Boost MICBOOST bit set

20Hz to 20kHz

100mVpp

1kHz input

Rsource < 50

34 dB

Mic Path gain (MICBOOST gain is additional to this nominal gain)

Mute attenuation

Input Resistance

Input Capacitance

Rsource < 50

R

INMIC

C

INMIC

10k

10 pF

Microphone Bias

Bias Voltage V

MICBIAS

V


Mute attenuation

PSSR 1kHz 100mVpp

20Hz to 20kHz

100mVpp

1kHz, 0dB

100mV 100mV

Bias Current Source

Output Noise Voltage

I

MICBIAS

Vn 1K to 20kHz

Line Output for DAC Playback Only (Load = 10k . 50pF)

0dBfs Full scale output voltage At LINE outputs

25 nV/

√Hz

1.0 x

AVDD/3.3

Vrms

95 100 dB Signal to Noise Ratio

(Note 1,3)


SNR

DR

A-weighted,

@ fs = 48kHz

A-weighted

@ fs = 96kHz

A-weighted,

fs = 48kHz,

AVDD = 2.7V


1kHz, 0dBfs

1kHz, -3dBfs

98

98

85 95 dB

Total Harmonic Distortion -80

Power Supply Rejection Ratio PSRR 1kHz 100mVpp

20Hz to 20kHz

100mVpp

50

45

DAC channel separation

1kHz, 0dB 100

Analogue Line Input to Line Output (Load = 10k . 50pF, No Gain on Input ) Bypass Mode

0dB Full scale output voltage

AVDD/3.3 dB dB


(Note 1,3)


THD

THD 1kHz, 0dB

1kHz, -3dB

-88

-92

-86

-92

-80 dB dB dB

50

45

80 dB dB

PD, Rev 4.8, April 2009 w

8

WM8731 / WM8731L

Production Data

Test Conditions


A

= +25 o



Stereo Headphone Output


AVDD/3.3

Max Output Power P

O mW

Signal to Noise Ratio (Note 1, 3)



SNR

THD

PSRR

1kHz, R

L

= 32

P

O

= 10mW rms (-5dB)

1kHz, R

L

= 32

P

O

= 20mW rms (-2dB)

1kHz 100mVpp

20Hz - 20kHz, 100mVpp

Programmable Gain

Programmable Gain Step Size

Mute attenuation 1kHz, 0dB

Microphone Input to Headphone Output Side Tone Mode


-65

80

60

AVDD/3.3

SNR 90 Signal to Noise Ratio

(Note 1,3)

Power Supply Rejection Ratio PSRR

-45

50

45

40

Programmable Attenuation

Programmable Attenuation Step

Size

Mute attenuation

1kHz 100mVpp

20Hz to 20kHz

100mVpp

50

1kHz 6

45 dB

1kHz, 0dB 80

% dB

% dB dB dB dB dB dB

Notes:

1. Ratio of output level with 1kHz full scale input, to the output level with the input short circuited, measured ‘A’ weighted over a 20Hz to 20kHz bandwidth using an Audio analyser.

2. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted over a

20Hz to 20kHz bandwidth.

3. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.

4. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).

TERMINOLOGY

1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).

2. Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal.

Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).

3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.

4. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. w


9

WM8731 / WM8731L

POWER CONSUMPTION – WM8731

MODE

DESCRIPTION

Production Data

CURRENT CONSUMPTION

TYPICAL

AVDD

(3.3V)

HP

VDD

(3.3V)

DC

VDD

(1.5V)

DB

VDD

(3.3V)

UNIT

Record and Playback

Oscillator enabled

External MCLK

Oscillator and

CLKOUT disabled,

No microphone

0 0 0 0 0 0 0 0 13.1 1.7 3.0 1.5 mA

0 0 1 0 0 0 0 0 13.1 1.7 3.2 0.8 mA

0 1 1 0 0 0 1 0 12.2 1.7 3.2 0.07 mA

Playback Only

Oscillator enabled

External MCLK

Record Only

Line Record, oscillator enabled

Line Record, using external MCLK

Mic Record, oscillator enabled

Mic Record, using external MCLK

0 0 0 0 0 1 1 1 3.4 1.7 2.1 1.5 mA

0 1 1 0 0 1 1 1 3.3 1.7 2.3 0.07 mA

0 0 0 1 1 0 1 0 9.2 - 2.6 1.3 mA

0 0 1 1 1 0 1 0 9.2 - 2.6 0.7 mA

0 0 0 1 1 0 0 1 8.6 - 2.7 1.5 mA

0 0 1 1 1 0 0 1 8.6 - 2.6 0.7 mA

Side Tone (Microphone Input to Headphone Output)

External clock still running

0 0 1 0 1 1 0 1 1.6 1.7 0.08 0.7 mA

Clock stopped 0 0 1 0 1 1 0 1 1.5 1.7 - - mA

Analogue Bypass (Line-in to Line-out)

0 0 1 0 1 1 1 0 2.1 1.7 0.08 0.7 mA External clock still running

Clock stopped

0 0 1 0 1 1 1 0 2.2 1.7 - - mA

Standby


Clock stopped

Power Down


Clock stopped

0 1 1 1 1 1 1 1 16 0.3 77 65

0 1 1 1 1 1 1 1 16 0.3 0.3 0.2

1 1 1 1 1 1 1 1 0.2 0.3 77 65

1 1 1 1 1 1 1 1 0.3 0.3 0.3 0.3

µA

µA

µA

µA

Table 1 Powerdown Mode Current Consumption Examples

Notes:

1. T

A

= +25 o

C. fs = 48kHz, XTI/MCLK = 256fs (12.288MHz).

2. The data presented here was measured with the audio interface in master mode whenever the internal clock oscillator was used, and in slave mode whenever an external clock was used (i.e. MS = 1 when OSCPD = 0 and vice versa).

However, it is also possible to use the WM8731 with MS = OSCPD = 0 or MS = OSCPD = 1.

3. All figures are quiescent, with no signal.

4. The power dissipation in the headphone itself not included in the above table. w PD, Rev 4.8, April 2009

10

WM8731 / WM8731L

Production Data

ELECTRICAL CHARACTERISTICS – WM8731L

Test Conditions


A

= +25 o



CONDITIONS

Digital Logic Levels (CMOS Levels)

Input LOW level

Input HIGH level

Output LOW

V

IL

V

IH

V

OL

Output HIGH

Power On Reset Threshold (DCVDD)

V

OH

DCVDD Threshold On -> Off

Hysteresis V

IH

DCVDD Threshold Off -> On

V th

V

OL

Analogue Reference Levels

Reference voltage (VMID)

Potential divider resistance

Line Input to ADC

Input Signal Level (0dB)

V

R

V

VMID

VMID

INLINE

0.7 x DBVDD

0.9 x DBVDD

0.3 x DBVDD

DBVDD

0.9

0.3

0.6

V

V

V

V

V

V

AVDD/2 V

50k


(Note 1,3)

SNR

AVDD/3.3

75 85 dB




DR

THD

PSRR


@ fs = 48kHz


@ fs = 96kHz


-1dB input, 0dB gain

20Hz to 20kHz,

100mVpp

85

80 88 dB

-76 -60 dB

50 dB

45

ADC channel separation

Programmable Gain

-34.5 0 +12 dB 1kHz input

Rsource < 50

Guaranteed Monotonic 1.5 dB Programmable Gain Step Size

Mute attenuation

Input Resistance R

INLINE

Input Capacitance C

INLINE

0dB gain

12dB gain

20k

10k

30k

15k

10 pF w


11

WM8731 / WM8731L

Production Data

Test Conditions


A

= +25 o



Microphone Input to ADC @ 0dB Gain, fs = 48kHz (40k Source Impedance. See Figure 12)

Input Signal Level (0dB) V

INMIC

AVDD/3.3


(Note 1,3)

Dynamic Range (Note 3) DR 70 dB



THD

PSRR


0dB input, 0dB gain -55 dB

Programmable Gain Boost MICBOOST bit set

20Hz to 20kHz

100mVpp

1kHz input

Rsource < 50

45 dB

34 dB

Mic Path gain (MICBOOST gain is additional to this nominal gain)

Rsource < 50

Mute attenuation

Input Resistance

Input Capacitance

Microphone Bias

Bias Voltage V

R

INMIC

C

INMIC

MICBIAS

10k

10 pF

0.75*AVDD –

100mV

0.75*AVDD 0.75*AVDD +

100mV

V

Bias Current Source

Output Noise Voltage

I

MICBIAS

Vn 1K to 20kHz

Line Output for DAC Playback Only (Load = 10k . 50pF)

0dBfs Full scale output voltage

At LINE outputs

25 nV/

√Hz


(Note 1,3)

SNR A-weighted,

@ fs = 48kHz

1.0 x

AVDD/3.3

Vrms

85 95 dB



DR

THD

A-weighted

@ fs = 96kHz


1kHz, 0dBfs

93

85 90 dB

-80 -75 dB


PSRR

20Hz to 20kHz

100mVpp

50 dB

45

DAC channel separation 1kHz, 0dB 100

Analogue Line Input to Line Output (Load = 10k . 50pF, No Gain on Input ) Bypass Mode


AVDD/3.3 dB


(Note 1,3) dB

Total Harmonic Distortion THD 1kHz, 0dB -83 -76 dB

Power Supply Rejection Ratio PSSR

20Hz to 20kHz

100mVpp

50 dB

45

Mute attenuation w PD, Rev 4.8, April 2009

12

WM8731 / WM8731L

Production Data

Test Conditions


A

= +25 o



Stereo Headphone Output


AVDD/3.3

Max Output Power P

O mW

RL = 16 18

SNR A-weighted 86 95 dB Signal to Noise Ratio

(Note 1,3)

Total Harmonic Distortion THD


PSRR

1kHz, -5dB FS signal

R

L

= 32

1kHz, -2dB FS signal

-62 -60

% dB

R

L

= 32

1

-40

100mVpp 50 dB

20Hz - 20kHz, 100mVpp 45

Programmable Gain

Programmable Gain Step Size dB

Mute attenuation

Microphone Input to Headphone Output Side Tone Mode


AVDD/3.3

SNR 85 Signal to Noise Ratio

(Note 1,3)


PSRR dB

1kHz 100mVpp

20Hz to 20kHz

100mVpp

50

1kHz 6

45 dB

Programmable Attenuation

Programmable Attenuation Step

Size

Mute attenuation 1kHz, 0dB 80 dB

Notes:

1. Ratio of output level with 1kHz full scale input, to the output level with the input short circuited, measured ‘A’ weighted over a 20Hz to 20kHz bandwidth using an Audio analyser.

2. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’ weighted over a

20Hz to 20kHz bandwidth.

3. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values.

4. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).

TERMINOLOGY

1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).

2. Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal.

Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).

3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.

4. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other. w


13

WM8731 / WM8731L

Production Data

POWER CONSUMPTION – WM8731L

MODE

DESCRIPTION

CURRENT CONSUMPTION

TYPICAL

Record and Playback

All active, oscillator enabled

0 0 0 0 0 0 0 0 6 0.6 2.7 0.9 mA

Playback Only

Oscillator enabled

Record Only

Line Record, oscillator enabled

AVDD

(1.8V)

HP

VDD

(1.8V)

DC

VDD

(1.5V)

DB

VDD

(1.8V)

UNIT

0 0 0 0 0 1 1 1 1.7 0.6 1.8 0.9 mA

0 0 0 1 1 0 1 0 3.9 - 2.4 0.9 mA

Mic Record, oscillator enabled

0 0 0 1 1 0 0 1 3.6 - 2.4 0.9 mA

Side Tone (Microphone Input to Headphone Output)

Clock stopped 0 0 1 0 1 1 0 1 0.8 0.6 - - mA

Analogue Bypass (Line-in to Line-out)

Clock stopped 0 0 1 0 1 1 1 0 1.1 0.6 - - mA

Standby

Clock stopped

0 1 1 1 1 1 1 1 8 - - -

µA

Power Down

Clock stopped

1 1 1 1 1 1 1 1 0.2 0.2 0.3 0.2

µA

Table 2 Powerdown Mode Current Consumption Examples

Notes:

1. AVDD, HPVDD, DBVDD = 1.8V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T

A

= +25 o

C. Slave Mode, fs = 48kHz,

XTI/MCLK = 256fs (12.288MHz).

2. All figures are quiescent, with no signal.

3. All figures are measured with the audio interface in master mode (MS = 1).

4. The power dissipation in the headphone itself is not included in the above table. w PD, Rev 4.8, April 2009

14

WM8731 / WM8731L

MASTER CLOCK TIMING

Production Data t

XTIL

XTI/MCLK

t

XTIY t

XTIH

Figure 1 System Clock Timing Requirements

Test Conditions


A

= +25 o

C, Slave Mode fs = 48kHz, XTI/MCLK =


System Clock Timing Information

XTI/MCLK System clock pulse width high

XTI/MCLK System clock pulse width low

XTI/MCLK System clock cycle time

XTI/MCLK Duty cycle t

XTIH t

XTIL t

XTIY

18

18

54 ns ns ns

XTI/MCLK

t

COP

CLKOUT

CLKOUT

(DIV X2)

Figure 2 Clock Out Timing Requirements

Test Conditions


A

= +25 o

C, Slave Mode fs = 48kHz, XTI/MCLK =


System Clock Timing Information

CLKOUT propagation delay from

XTI/MCLK falling edge t

COP

0 ns w


15

WM8731 / WM8731L

DIGITAL AUDIO INTERFACE – MASTER MODE

BCLK

ADCLRC

WM8731

CODEC

DACLRC

ADCDAT

DACDAT

Note: ADC and DAC can run at different rates

Figure 3 Master Mode Connection

DSP

ENCODER/

DECODER

Production Data

BCLK

(Output)

ADCLRC

DAC/LRC

(Outputs)

ADCDAT t

DL t

DDA

DACDAT t

DST t

DHT

Figure 4 Digital Audio Data Timing – Master Mode

Test Conditions

AVDD, HPVDD, DBDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T

A

= +25 o



PARAMETER SYMBOL CONDITIONS

Audio Data Input Timing Information

ADCLRC/DACLRC propagation delay from

BCLK falling edge t

DL t

DDA

ADCDAT propagation delay from BCLK falling edge

DACDAT setup time to

BCLCK rising edge

DACDAT hold time from

BCLK rising edge t t

DST

DHT

10

10 ns ns w PD, Rev 4.8, April 2009

16

WM8731 / WM8731L

DIGITAL AUDIO INTERFACE – SLAVE MODE

Production Data

BCLK

ADCLRC

WM8731

CODEC

DACLRC

ADCDAT

DACDAT

DSP

ENCODER/

DECODER

Note: The ADC and DAC can run at different rates

Figure 5 Slave Mode Connection t

BCH t

BCL

BCLK t

BCY

DACLRC/

ADCLRC t

DS t

LRH t

LRSU

DACDAT t

DD t

DH

ADCDAT

Figure 6 Digital Audio Data Timing – Slave Mode

Test Conditions


A

= +25 o



PARAMETER SYMBOL CONDITIONS

Audio Data Input Timing Information

BCLK cycle time t

BCY

BCLK pulse width high

BCLK pulse width low

DACLRC/ADCLRC set-up time to BCLK rising edge t

BCH t

BCL t

LRSU t

LRH

50

20

20

10

10 DACLRC/ADCLRC hold time from BCLK rising edge

DACDAT set-up time to

BCLK rising edge t

DS

10

DACDAT hold time from

BCLK rising edge

ADCDAT propagation delay from BCLK falling edge t t

DH

DD

10 w ns ns ns ns ns ns ns


17

WM8731 / WM8731L

MPU INTERFACE TIMING

Production Data

CSB t

CSL t

CSH t

CSS t

SCH t

SCY t

SCL t

SCS

SCLK

SDIN

LSB

t

DSU t

DHO

Figure 7 Program Register Input Timing - 3-Wire MPU Serial Control Mode

Test Conditions


A

= +25 o



Program Register Input Information

SCLK rising edge to CSB rising edge t

SCS

SCLK pulse cycle time

SCLK pulse width low

SCLK pulse width high

SDIN to SCLK set-up time

SCLK to SDIN hold time

CSB pulse width low

CSB pulse width high

CSB rising to SCLK rising t

SCY t

SCL t

SCH t

DSU t

DHO t

CSL t

CSH t

CSS

60

80

20

20

20

20

20

20

20 ns ns ns ns ns ns ns ns ns w PD, Rev 4.8, April 2009

18

WM8731 / WM8731L

Production Data

t

3 t

5 t

3

SDIN t

4 t

6 t

2 t

8

SCLK t

1 t

7 t

10

Figure 8 Program Register Input Timing – 2-Wire MPU Serial Control Mode

Test Conditions


A

= +25 o



Program Register Input Information

SCLK Frequency

SCLK Low Pulsewidth

SCLK High Pulsewidth

Hold Time (Start Condition)

Setup Time (Start Condition)

Data Setup Time

SDIN, SCLK Rise Time

SDIN, SCLK Fall Time

Setup Time (Stop Condition)

Data Hold Time t

4 t

5 t

6 t

7 t

1 t

2 t

3

0

1.3

600

600

600

100 kHz us ns ns ns ns ns ns t

8

600 ns t

10 ns w


19

WM8731 / WM8731L

Production Data

DEVICE DESCRIPTION

INTRODUCTION

The WM8731/L is a low power audio CODEC designed specifically for portable audio products. It’s features, performance and low power consumption make it ideal for portable MP3 players and portable mini-disc players.

The CODEC includes line and microphone inputs to the on-board ADC, line and headphone outputs from the on-board DAC, a crystal oscillator, configurable digital audio interface and a choice of 2 or 3 wire MPU control interface. It is fully compatible and an ideal partner for a range of industry standard microprocessors, controllers and DSPs.

The CODEC includes three low noise inputs - mono microphone and stereo line. Line inputs have

+12dB to -34dB logarithmic volume level adjustments and mute. The Microphone input has -6dB to

34dB volume level adjustment. An electret microphone bias level is also available. All the required input filtering is contained within the device with no external components required.

The on-board stereo analogue to digital converter (ADC) is of a high quality using a multi-bit highorder oversampling architecture delivering optimum performance with low power consumption. The output from the ADC is available on the digital audio interface. The ADC includes an optional digital high pass filter to remove unwanted dc components from the audio signal.

The on-board digital to analogue converter (DAC) accepts digital audio from the digital audio interface. Digital filter de-emphasis at 32kHz, 44.1kHz and 48kHz can be applied to the digital data under software control. The DAC employs a high quality multi-bit high-order oversampling architecture to again deliver optimum performance with low power consumption.

The DAC outputs, Microphone (SIDETONE) and Line Inputs (BYPASS) are available both at line level and through a headphone amplifier capable of efficiently driving low impedance headphones.

The headphone output volume is adjustable in the analogue domain over a range of +6dB to –73dB and can be muted.

The design of the WM8731/L has given much attention to power consumption without compromising performance. It includes the ability to power off selective parts of the circuitry under software control, thus conserving power. Nine separate power save modes be configured under software control including a standby and power off mode.

Special techniques allow the audio to be muted and the device safely placed into standby, sections of the device powered off and volume levels adjusted without any audible clicks, pops or zipper noises. Therefore standby and power off modes maybe used dynamically under software control, whenever recording or playing is not required.

The device caters for a number of different sampling rates including industry standard 8kHz, 32kHz,

44.1kHz, 48kHz, 88.2kHz and 96kHz. Additionally, the device has an ADC and DAC that can operate at different sample rates.

There are two unique schemes featured within the programmable sample rates of the WM8731/L:

Normal industry standard 256/384fs sampling mode may be used, with the added ability to mix different sampling rates. Also a special USB mode is included, whereby all audio sampling rates can be generated from a 12.00MHZ USB clock. Thus, for example, the ADC can record to the DSP at

44.1kHz and be played back from the CODEC at 8kHz with no external digital signal processing required. The digital filters used at for both record and playback are optimised for each sampling rate used.

The digitised output is available in a number of audio data formats I

2

S, DSP Mode (a burst mode in which frame sync plus 2 data packed words are transmitted), MSB-First, left justified and MSB-First, right justified. The digital audio interface can operate in both master or slave modes.

The software control uses either 2 or 3-wire MPU interface.

A crystal oscillator is included on board the device. The device can generate the system master clock or alternatively it can accept an external master clock from the audio system. w PD, Rev 4.8, April 2009

20

WM8731 / WM8731L

Production Data

AVDD

VMID

AGND

MICBIAS

RLINEIN

MICIN

LLINEIN

VOL

+12 to -34.5dB, 1.5dB Steps,

Reg 02h

0dB/

20dB

MIC BOOST Reg 08h

RLINEIN Mute

Reg 02h

MUTE

INSEL, Reg 08h

MUX

ADC

MUTE

VOL

+12 to -34.5dB, 1.5dB Steps,

Reg 00h

MUTE

MUX

MUTE

LLINEIN Mute

Reg 00h

INSEL, Reg 08h

ADC

OSCPD

Reg 0Ch

OSC

CLKIN

DIVIDER

(Div x1, x2)

CLKIDIV2, Reg 10h

CLKOUTPD, Reg 0Ch

CLKODIV2, Reg 10h

CLKOUT

DIVIDER

(Div x1, x2)

CONTROL INTERFACE

WM8731

DAC

Bypass, Reg 08h

MUTE

ATTEN/

MUTE

SIDEATT,

Reg 08h

MUTE

DACMUTE

Reg 0Ah

Σ

SIDETONE

Reg 08h

+6 to -73dB

1 dB Steps, Reg 06h

VOL/

MUTE

H/P

DRIVER

DIGITAL

FILTERS

DIGTAL AUDIO INTERFACE

DAC

DACMUTE

Reg 0Ah

MUTE

SIDETONE

Reg 08h

Σ

SIDEATT,

Reg 08h

ATTEN/

MUTE

MUTE

Bypass, Reg 08h

VOL/

MUTE

+6 to -73dB

1 dB Steps, Reg 04h

H/P

DRIVER

HPVDD

HPGND

RHPOUT

ROUT

LOUT

LHPOUT

Figure 9 Functional Block Diagram

AUDIO SIGNAL PATH

LINE INPUTS

The WM8731/L provides Left and Right channel line inputs (RLINEIN and LLINEIN). The inputs are high impedance and low capacitance, thus ideally suited to receiving line level signals from external hi-fi or audio equipment.

Both line inputs include independent programmable volume level adjustments and ADC input mute.

The scheme is illustrated in Figure 10. Passive RF and active Anti-Alias filters are also incorporated within the line inputs. These prevent high frequencies aliasing into the audio band or otherwise degrading performance.

LINEIN 12.5k

w

VMID

Figure 10 Line Input Schematic

To

ADC


21

WM8731 / WM8731L

Production Data

The gain between the line inputs and the ADC is logarithmically adjustable from +12dB to –34.5dB in

1.5dB steps under software control. The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with AVDD. The gain is independently adjustable on both Right and Left

Line Inputs. However, by setting the INBOTH bit whilst programming the volume control, both channels are simultaneously updated with the same value. Use of INBOTH reduces the required number of software writes required. The line inputs to the ADC can be muted in the analogue domain under software control. The software control registers are shown Table 3. Note that the Line Input

Mute only mutes the input to the ADC, this will still allow the Line Input signal to pass to the line output in Bypass Mode.

REGISTER

ADDRESS

0000000

Left Line In

BIT LABEL DEFAULT

4:0 LINVOL[4:0] 10111

( 0dB )

DESCRIPTION

0000001

Right Line In

7

8

LINMUTE

LRINBOTH

1

0

4:0 RINVOL[4:0] 10111

7

8

RINMUTE

RLINBOTH

( 0dB )

1

0

Left Channel Line Input Volume

Control

11111 = +12dB . . 1.5dB steps down to 00000 = -34.5dB

Left Channel Line Input Mute to ADC

1 = Enable Mute

0 = Disable Mute

Left to Right Channel Line Input

Volume and Mute Data Load Control

1 = Enable Simultaneous Load of

LINVOL[4:0] and LINMUTE to

RINVOL[4:0] and RINMUTE

0 = Disable Simultaneous Load

Right Channel Line Input Volume

Control

11111 = +12dB . .1.5dB steps down to 00000 = -34.5dB

Right Channel Line Input Mute to

ADC

1 = Enable Mute

0 = Disable Mute

Right to Left Channel Line Input



RINVOL[4:0] and RINMUTE to

LINVOL[4:0] and LINMUTE


Table 3 Line Input Software Control

The line inputs are biased internally through the operational amplifier to VMID. Whenever the line inputs are muted or the device placed into standby mode, the line inputs are kept biased to VMID using special anti-thump circuitry. This reduces any audible clicks that may otherwise be heard when re-activating the inputs.

The external components required to complete the line input application is shown in the Figure 11. w PD, Rev 4.8, April 2009

22

WM8731 / WM8731L

R1

C2

Production Data

LINEIN

R2

C1

AGND

AGND AGND

Figure 11 Line Input Application Drawing

For interfacing to a typical CD system, it is recommended that the input is scaled to ensure that there is no clipping of the signal. R1 = 5.6k, R2 = 5.6k, C1 = 220pF, C2 = 1

µF.

R1 and R2 form a resistive divider to attenuate the 2 Vrms output from a CD player to a 1 Vrms level, so avoiding overloading the inputs. R2 also provides a discharge path for C2, thus preventing the input to C2 charging to an excessive voltage which may otherwise damage any equipment connected that is not suitably protected against high voltages. C1 forms an RF low pass filter for increasing the rejection of RF interference picked up on any cables. C2 forms a DC blocking capacitor to remove the DC path between the WM8731/L and the driving audio equipment. C2 together with the input impedance of the WM8731/L form a high pass filter.

MICROPHONE INPUT

MICIN is a high impedance, low capacitance input suitable for connection to a wide range of monophonic microphones of different dynamics and sensitivities.

The MICIN includes programmable volume adjustments and a mute function. The scheme is shown in Figure 12. Passive RF and active Anti-Alias filters are also incorporated within the microphone inputs. These allow a matched interface to the multi-bit oversampling ADC and preventing high frequencies aliasing into the audio band or otherwise degrading performance.

50k

20dB GAIN BOOST

MICIN 10k

VMID

VMID

To

ADC w

Figure 12 Microphone Input Schematic

There are 2 stages of gain made up of two low noise inverting operational amplifiers.

The 1 st

stage comprises a nominal gain of G1 = 50k/10k = 5. By adding an external resistor (Rmic) in series with MICIN the gain of stage can be adjusted. For example adding Rmic = 40K sets the gain of stage 1 to x1 (0dB). The equation below can be used to calculate the gain versus Rmic.

G1 = 50k/ (Rmic + 10k)


23

WM8731 / WM8731L

Production Data

Or alternatively to calculate the value of Rmic to achieve a given gain, G1.

Rmic = (50k/G1) – 10k

The internal 50k and 10k resistors have a tolerance of 15%. For Rmicext = 90k G = 0.5 (-6dB) and for Rmicext = 0 G = x10 (14dB).

The 2 nd

stage comprises a 0dB gain stage that can be software configured to provide a fixed 20dB of gain for low sensitivity microphones.

The microphone input can therefore be configured with a variable gain of between -6dB and 14dB on the 1 st

stage, and an additional fixed 0dB or 20dB on the 2 nd

stage. This allows for all gains to the input signal in the range –6dB to 34dB to be catered for.

The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with

AVDD. Stage 1 and Stage 2 gains should be configured so that the ADC receives a maximum signal equal to its full scale for maximising the signal to noise.

The software control for the MICIN is shown in Table 4. Note that the Microphone Mute only mutes the input to the ADC, this will still allow the Microphone Input signal to pass to the line output in

Sidetone Mode.

BIT LABEL DEFAULT DESCRIPTION REGISTER

ADDRESS

0000100

Analogue Audio

Path Control

0

1

MICBOOST

MUTEMIC

0

1

Microphone Input Level Boost

1 = Enable Boost

0 = Disable Boost

Line Input Mute to ADC

1 = Enable Mute

0 = Disable Mute

Table 4 Microphone Input Software Control

The microphone input is biased internally through the operational amplifier to VMID. Whenever the line inputs are muted the MICIN input is kept biased to VMID using special anti-thump circuitry. This reduces any audible clicks that may otherwise be heard when re-activating the input.

The application drawing for the microphone is shown in Figure 13.

MICBIAS

R1

Rmic

C2

FROM

MICROPHONE

MICIN

AGND

R2

C1 w

AGND AGND

Figure 13 Microphone Input and Bias Application Drawing

Recommended component values are C1 = 220pF (npo ceramic), C2 = 1

µF, R1 = 680 , R2 = 47k.

Rmic values depends on gain setting (see above).


24

WM8731 / WM8731L

Production Data

R1 and R2 form part of the biasing network (refer to Microphone Bias section below). R1 connected to MICBIAS is necessary only for electret type microphones that require a voltage bias. R2 should always be present to prevent the microphone input from charging to a high voltage which may damage the microphone on connection. R1 and R2 should be large so as not to attenuate the signal from the microphone, which can have source impedance greater than 2k. C1 together with the source impedance of the microphone and the input impedance of MICIN forms an RF filter. C2 is a

DC blocking capacitor to allow the microphone to be biased at a different DC voltage to the MICIN signal.

MICROPHONE BIAS

The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to the Microphone Input section for an application drawing and further description.

The scheme for MICBIAS is shown in Figure 14. Note that there is a maximum source current capability of 3mA available for the MICBIAS. This limits the smallest value of external biasing resistors that can safely be used.

Note that the MICBIAS output is not active in standby mode.

VMID

MICBIAS

AGND

Figure 14 Microphone Bias Schematic

ADC

The WM8731/L uses a multi-bit oversampled sigma-delta ADC. A single channel of the ADC is illustrated in the Figure 15.

FROM MICROPHONE

INPUT

ANALOG

INTEGRATOR

TO ADC DIGITAL FILTERS

FROM LINE INPUT

MULTI

BITS

INSEL

w

Figure 15 Multi-Bit Oversampling Sigma Delta ADC Schematic


25

WM8731 / WM8731L

Production Data

The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise.

The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with

AVDD.

The device employs a pair of ADCs. The input can be selected from either the Line Inputs or the

Microphone input under software control. The two channels cannot be selected independently. The control is shown in Table 5.

REGISTER

ADDRESS

0000100

Analogue

Audio Path

Control

2


INSEL

Table 5 ADC Software Control

0

DESCRIPTION

Microphone/Line Input Select to ADC

1 = Microphone Input Select to ADC

0 = Line Input Select to ADC

The digital data from the ADC is fed for signal processing to the ADC Filters.

ADC FILTERS

The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. Figure 16 illustrates the digital filter path.

FROM ADC

DIGITAL

DECIMATOR

DIGITAL

DECIMATION

FILTER

DIGITAL

HPF

TO DIGITAL

AUDIO

INTERFACE w

HPFEN

Figure 16 ADC Digital Filter

The ADC digital filters contain a digital high pass filter, selectable via software control. The high-pass filter response detailed in Digital Filter Characteristics. When the high-pass filter is enabled the dc offset is continuously calculated and subtracted from the input signal. By setting HPOR the last calculated dc offset value is stored when the high-pass filter is disabled and will continue to be subtracted from the input signal. If the dc offset changes, the stored and subtracted value will not change unless the high-pass filter is enabled. The software control is shown in Table 6.

REGISTER

ADDRESS

0000101

Digital Audio

Path Control

BIT LABEL DEFAULT DESCRIPTION

0 ADCHPD 0 ADC High Pass Filter Enable

(Digital)

1 = Disable High Pass Filter

0 = Enable High Pass Filter

4 HPOR 0 Store dc offset when High Pass

Filter disabled

1 = store offset

0 = clear offset

Table 6 ADC Software Control


26

WM8731 / WM8731L

Production Data

There are several types of ADC filters, frequency and phase responses of these are shown in Digital

Filter Characteristics. The filter types are automatically configured depending on the sample rate chosen. Refer to the sample rate section for more details.

DAC FILTERS

The DAC filters perform true 24 bit signal processing to convert the incoming digital audio data from the digital audio interface at the specified sample rate to multi-bit oversampled data for processing by the analogue DAC. Figure 17 illustrates the DAC digital filter path.

FROM DIGITAL

AUDIO

INTERFACE

DIGITAL

DE_EMPHASIS

MUTE

DIGITAL

INTERPOLATION

FILTER

TO LINE

OUTPUTS

DEEMP DACMU

Figure 17 DAC Filter Schematic

The DAC digital filter can apply digital de-emphasis under software control, as shown in Table 7.The

DAC can also perform a soft mute where the audio data is digitally brought to a mute level. This removes any abrupt step changes in the audio that might otherwise result in audible clicks in the audio outputs.


ADDRESS

0000101

Digital

Audio Path

Control

3 DACMU 1

(Digital)

11 = 48kHz

10 = 44.1kHz

01 = 32kHz

00 = Disable

DAC Soft Mute Control

(Digital)

1 = Enable soft mute

0 = Disable soft mute

Table 7 DAC Software Control

Notes:

1. Not valid when SR[3:0] = 1111 or 0111.

2. To ensure correct DACMU operation at fs = 88.2kHz, set SR[3:0] = 1000.

3. To ensure correct DACMU operation at fs = 96kHz, set SR[3:0] = 0000.

DAC

The WM8731/L employs a multi-bit sigma delta oversampling digital to analogue converter. The scheme for the converter is illustrated in Figure 18. w


27

WM8731 / WM8731L

Production Data

FROM DAC

DIGITAL

FILTERS

TO LINE OUTPUT

Figure 18 Multi-Bit Oversampling Sigma Delta Schematic

The DAC converts the multi-level digital audio data stream from the DAC digital filters into high quality analogue audio.

LINE OUTPUTS

The WM8731/L provides two low impedance line outputs LLINEOUT and RLINEOUT, suitable for driving typical line loads of impedance 10K and capacitance 50pF. The line output is used to selectively sum the outputs from the DAC or/and the Line inputs in bypass mode.

The LLINEOUT and RLINEOUT outputs are only available at a line output level and are not level adjustable in the analogue domain, having a fixed gain of 0dB. The level is fixed such that at the DAC full scale level the output level is 1.0Vrms at AVDD = 3.3 volts. Note that the DAC full scale level tracks directly with AVDD. The scheme is shown in Figure 19. The line output includes a low order audio low pass filter for removing out-of band components from the sigma-delta DAC. Therefore no further external filtering is required in most applications.

SIDETONE

FROM MICROPHONE

INPUT

BYPASS

FROM LINE

INPUTS

DACSEL

FROM DAC

LINEOUT

VMID

TO HEADPHONE AMP

Figure 19 Line Output Schematic

The DAC output, Line Input and microphone are summed into the Line Output. In DAC mode only the output from the DAC is routed to the line outputs. In Bypass mode the Line Input is summed into the

Line Outputs. In Side Tone mode the Microphone Input is summed into the Line Output. These features can be used for either over-dubbing or, if the DAC is muted, as a pure analogue bypass or

Side Tone feature, so avoiding any digital signal processing.

The line output is muted by either muting the DAC (analogue) or Soft Muting (digital) and disabling the BYPASS and SIDETONE paths. Refer to the DAC section for more details. Whenever the DAC is muted or the device placed into standby mode the DC voltage is maintained at the line outputs to prevent any audible clicks from being present. w PD, Rev 4.8, April 2009

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WM8731 / WM8731L

Production Data

The software control for the line outputs is shown in Table 8.

BIT LABEL DEFAULT REGISTER

ADDRESS

0000100

Analogue

Audio Path

Control

3 BYPASS

4 DACSEL

1

0

DESCRIPTION

Bypass Switch

1 = Enable Bypass

0 = Disable Bypass

5 SIDETONE 0

1 = Select DAC

0 = Don’t select DAC

Side Tone Switch

1 = Enable SideTone

0 = Disable Side Tone

Table 8 Output Software Control

The recommended external components are shown in Figure 20.

R2

LINEOUT

C1

R1

AGND

AGND

Figure 20 Line Outputs Application Drawing

Recommended values are C1 = 10

µF, R1 = 47k, R2 = 100 .

C1 forms a DC blocking capacitor to the line outputs. R1 prevents the output voltage from drifting so protecting equipment connected to the line output. R2 forms a de-coupling resistor preventing abnormal loads from disturbing the device. Note that poor choice of dielectric material for C1 can have dramatic effects on the measured signal distortion at the output

HEADPHONE AMPLIFIER

The WM8731/L has a stereo headphone output available on LHPOUT and RHPOUT. The output is designed specifically for driving 16 or 32 headphones with maximum efficiency and low power consumption. The headphone output includes a high quality volume level adjustment and mute function. w


29

WM8731 / WM8731L

The scheme of the circuit is shown in Figure 21.

FROM

DAC VIA

LINEOUT

Production Data

HPOUT

VMID

Figure 21 Headphone Amplifier Schematic

LHPOUT and RHPOUT volumes can be independently adjusted under software control using the

LHPVOL[6:0] and RHPVOL[6:0] bits respectively of the headphone output control registers. The adjustment is logarithmic with an 80dB range in 1dB steps from +6dB to –73dB.

The headphone outputs can be separately muted by writing codes less than 0110000 to

LHPVOL[6:0] or RHPVO[6:0]L bits. Whenever the headphone outputs are muted or the device placed into standby mode, the DC voltage is maintained at the line outputs to prevent any audible clicks from being present.

A zero cross detect circuit is provided at the input to the headphones under the control of the LZCEN and RZCEN bits of the headphone output control register. Using these controls the volume control values are only updated when the input signal to the gain stage is close to the analogue ground level.

This minimises and audible clicks and zipper noise as the gain values are changed or the device muted. Note that this circuit has no time out so if only DC levels are being applied to the gain stage input of more than approximately 20mV, then the gain will not be updated. This zero cross function is enabled when the LZCEN and RZCEN bit is set high during a volume register write. If there is concern that a DC level may have blocked a volume change (one made with LZCEN or RZCEN set high) then a subsequent volume write of the same value, but with the LZCEN or RZCEN bit set low will force a volume update, regardless of the DC level.

LHPOUT and RHPOUT volume and zero-cross setting can be changed independently. Alternatively, the user can lock the two channels together, allowing both to be updated simultaneously, halving the number of serial writes required, provided that the same gain is needed for both channels. This is achieved through writing to the HPBOTH bit of the control register. Setting LRHPBOTH whilst writing to LHPVOL and LZCEN will simultaneously update the Right Headphone controls similarly. The corresponding effect on updating RLHPBOTH is also achieved. w PD, Rev 4.8, April 2009

30

WM8731 / WM8731L

Production Data

The software control is given in Table 9.

BIT LABEL DEFAULT REGISTER

ADDRESS

0000010

Left

Headphone

Out

( 0dB )

0000011

Right

Headphone

Out

7

8

7

8

LZCEN

LRHPBOTH

RZCEN

RLHPBOTH

0

0

( 0dB )

0

0

DESCRIPTION

Left Channel Headphone Output

Volume Control

1111111 = +6dB

. . 1dB steps down to

0110000 = -73dB

0000000 to 0101111 = MUTE

Left Channel Zero Cross detect

Enable

1 = Enable

0 = Disable

Left to Right Channel Headphone

Volume, Mute and Zero Cross Data

Load Control


LHPVOL[6:0] and LZCEN to

RHPVOL[6:0] and RZCEN


Right Channel Headphone Output

Volume Control

1111111 = +6dB


0110000 = -73dB

0000000 to 0101111 = MUTE

Right Channel Zero Cross Detect

Enable

1 = Enable

0 = Disable

Right to Left Channel Headphone


Load Control


RHPVOL[6:0] and RZCEN to

LHPVOL[6:0] and LZCEN


Table 9 Headphone Output Software Control

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The recommended external components required to complete the application are shown in Figure 22.

HPOUT

C1

R1

AGND

LINEIN 12.5K

VMID

AGND

Figure 22 Headphone Output Application Drawing

Recommended values are C1 = 220uF (10V electrolytic), R1 = 47k

C1 forms a DC blocking capacitor to isolate the dc of the HPOUT from the headphones. R1 form a pull down resistor to discharge C1 to prevent the voltage at the connection to the headphones from rising to a level that may damage the headphones.

BYPASS MODE

The WM8731/L includes a bypass mode whereby analogue line inputs are routed directly to the analogue line outputs and headphone outputs. The scheme for this is in Figure 23.

FROM

LINE

INPUTS

FROM

DAC

SIDETONE (OFF)

BYPASS (ON)

DACSEL (OFF)

VMID

LINEOUT

VMID

HPOUT

Figure 23 Signal Routing in Bypass Mode

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The bypass mode is selected under software control using the BYPASS microphone bit as shown in

Table 10. In true bypass mode, the output from the DAC (DACSEL) and (SIDETONE) should be deselected from the line output block. However this can also be used to sum the DAC output, Line

Inputs together and microphone inputs. The analogue line input and headphone output volume controls and mutes are still operational in bypass mode. The 0dB gain setting is recommended for the Line Input volume control to avoid distortion. The maximum signal at any point in the bypass path must be no greater than 1.0V rms at AVDD = 3.3V, to avoid distortion. This amplitude tracks linearly with AVDD. This means that if the DAC is producing a 1Vrms signal, and it is being summed with

1Vrms line BYPASS signal, the resulting LINEOP signal will be clipped.

REGISTER

ADDRESS

0000100

Analogue

Audio Path

Control

BIT LABEL

3 BYPASS 1

Table 10 Bypass Mode Software Control

DEFAULT DESCRIPTION

Bypass Switch (Analogue)

1 = Enable Bypass

0 = Disable Bypass

SIDETONE MODE

The WM8731/L also includes a side tone mode where the microphone input is routed to line and headphone outputs. The scheme for this is shown in Figure 24.

The side tone mode allows the microphone input to be attenuated to the outputs for telephone and headset applications.

50k

10dB GAIN BOOST

MICIN 10k

VMID

SIDETONE (ON)

VMID

BYPASS (OFF)

FROM

LINE

INPUTS

FROM

DAC

DACSEL (OFF)

LINEOUT

VMID

VMID

Figure 24 Side Tone Mode Schematic

REGISTER

ADDRESS

0000100

Analogue

Audio Path

Control

BIT LABEL

5 SIDETONE 0

DEFAULT

7:6 SIDEATT[1:0] 00

DESCRIPTION

Side Tone Switch (Analogue)

1 = Enable Side Tone


11 = -15dB

10 = -12dB

01 = -9dB

00 = -6dB

Table 11 Side Tone Mode Table

HPOUT w


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The side tone mode and attenuation is selected under software control using the SIDETONE bit as shown in Table 11. In true side tone the output from the DAC (DACSEL) and line inputs (BYPASS) should be deselected from the line output block. However, this can also be used to sum the DAC output, line inputs and microphone inputs together. The microphone boost gain control and headphone output volume control and mutes are still operational in side tone mode. The maximum signal at any point in the side tone path must be no greater than 1.0V rms at VDD = 3.3V, to avoid distortion. This amplitude tracks linearly with AVDD.

DEVICE OPERATION

DEVICE RESETTING

The WM8731/L contains a power on reset circuit that resets the internal state of the device to a known condition. The power on reset is applied as DCVDD powers on and released only after the voltage level of DCVDD crosses a minimum turn off threshold. If DCVDD later falls below a minimum turn on threshold voltage then the power on reset is re-applied. The threshold voltages and associated hysteresis are shown in the Electrical Characteristics table.

The user also has the ability to reset the device to a known state under software control as shown in the table below.


ADDRESS

0001111

Reset Register

8:0 RESET

Writing 00000000 to register resets device

Table 12 Software Control of Reset

When using the software reset. In 3-wire mode the reset is applied on the rising edge of CSB and released on the next rising edge of SCLK. In 2-wire mode the reset is applied for the duration of the

ACK signal (approximately 1 SCLK period, refer to Figure 34).

CLOCKING SCHEMES

In a typical digital audio system there is only one central clock source producing a reference clock to which all audio data processing is synchronised. This clock is often referred to as the audio system’s

Master Clock. To allow WM8731/L to be used in a centrally clocked system, the WM8731/L is capable of either generating this system clock itself or receiving it from an external source as will be discussed.

For applications where it is desirable that the WM8731/L is the system clock source, then clock generation is achieved through the use of a suitable crystal connected between the XTI/MCLK input and XTO output pins (see CRYSTAL OSCILLATOR section).

For applications where a component other than the WM8731/L will generate the reference clock, the external system can be applied directly through the XTI/MCLK input pin with no software configuration necessary. Note that in this situation, the oscillator circuit of the WM8731/L can be safely powered down to conserve power (see POWER DOWN section).

CORE CLOCK

The WM8731/L DSP core can be clocked either by MCLK or MCLK divided by 2. This is controlled by software as shown in Table 13 below.

REGISTER

ADDRESS

0001000

Sampling

Control


6 CLKIDIV2 0

Table 13 Software Control of Core Clock

DESCRIPTION

Core Clock divider select

1 = Core Clock is MCLK divided by 2

0 = Core Clock is MCLK

Having a programmable MCLK divider allows the device to be used in applications where higher frequency master Clocks are available. For example the device can support 512fs master clocks whilst fundamentally operating in a 256fs mode. w PD, Rev 4.8, April 2009

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CRYSTAL OSCILLATOR

The WM8731/L includes a crystal oscillator circuit that allows the audio system’s reference clock to be generated on the device. This is available to the rest of the audio system in buffered form on

CLKOUT. The crystal oscillator is a low radiation type, designed for low EMI. A typical application circuit is shown in Figure 25.

XTI/MCLK XTO

Cp Cp

DGND DGND

Figure 25 Crystal Oscillator Application Circuit

The WM8731/L crystal oscillator provides an extremely low jitter clock source. Low jitter clocks are a requirement for high quality audio ADC and DACs, regardless of the converter architecture. The

WM8731/L architecture is less susceptible than most converter techniques but still requires clocks with less than approximately 1ns of jitter to maintain performance. In applications where there is more than one source for the master clock, it is recommended that the clock is generated by the

WM8731/L to minimise such problems.

CLOCKOUT

The Core Clock is internally buffered and made available externally to the audio system on the

CLKOUT output pin. CLKOUT provides a replication of the Core Clock, but buffered as suitable for driving external loads.

There is no phase inversion between XTI/MCLK, the Core Clock and CLOCKOUT but there will inevitably be some delay. The delay will be dependent on the load that CLOCKOUT drives. Refer to

Electrical Characteristics.

CLKOUT can also be divided by 2 under software control, refer to Table 14. Note that if CLKOUT is not required then the CLKOUT buffer on the WM8731/L can be safely powered down to conserve power (see POWER DOWN section). If the system architect has the choice between using F

CLKOUT

=

F

MCLK or F

CLKOUT

= F

MCLK

/2 in the interface, the latter is recommended to conserve power. When the divide by two is selected CLKOUT changes on the rising edge of MCLK. Please refer to Electrical

Characteristics for timing information.


ADDRESS

0001000

Sampling

Control

1 = CLOCKOUT is Core Clock divided by 2

0 = CLOCKOUT is Core Clock

Table 14 Programming CLKOUT

CLKOUT is disabled and set low whenever the device is in reset. w


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DIGITAL AUDIO INTERFACES

WM8731/L may be operated in either one of the 4 offered audio interface modes. These are:

•

I

2

S

All four of these modes are MSB first and operate with data 16 to 32 bits.

Note that 32 bit data is not supported in right justified mode.

The digital audio interface takes the data from the internal ADC digital filter and places it on the

ADCDAT output. ADCDAT is the formatted digital audio data stream output from the ADC digital filters with left and right channels multiplexed together. ADCLRC is an alignment clock that controls whether Left or Right channel data is present on the ADCDAT lines. ADCDAT and ADCLRC are synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low transition. BCLK maybe an input or an output dependent on whether the device is in master or slave mode. Refer to the MASTER/SLAVE OPERATION section

The digital audio interface also receives the digital audio data for the internal DAC digital filters on the

DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters with left and right channels multiplexed together. DACLRC is an alignment clock that controls whether Left or Right channel data is present on DACDAT. DACDAT and DACLRC are synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low transition. DACDAT is always an input. BCLK and DACLRC are either outputs or inputs depending whether the device is in master or slave mode. Refer to the MASTER/SLAVE OPERATION section

There are four digital audio interface formats accommodated by the WM8731/L. These are shown in the figures below. Refer to the Electrical Characteristic section for timing information.

Left Justified mode is where the MSB is available on the first rising edge of BCLK following a ADCLR or DACLRC transition.

1/fs

LEFT CHANNEL RIGHT CHANNEL

DACLRC/

ADCLRC

BCLK

DACDAT/

ADCDAT

1

MSB

2 3 n-2 n-1 n

LSB

1

MSB

2 3 n-2 n-1 n

LSB

Figure 26 Left Justified Mode

I

2

S mode is where the MSB is available on the 2nd rising edge of BCLK following a DACLRC or

ADCLRC transition. w PD, Rev 4.8, April 2009

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1/fs


DACLRC/

ADCLRC

BCLK

DACDAT/

ADCDAT

Figure 27 I

2

S Mode

1 BCLK

1 2 3

MSB n-2 n-1 n

LSB

1 BCLK

1

MSB

2 3 n-2 n-1 n

LSB

Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a DACLRC or ADCLRC transition, yet MSB is still transmitted first.

1/fs


DACLRC/

ADCLRC

BCLK

DACDAT/

ADCDAT

1 2 3 n-2 n-1 n 1 2 3 n-2 n-1 n

MSB LSB MSB LSB

Figure 28 Right Justified Mode

In DSP/PCM mode, the left channel MSB is available on either the 1 st

(mode B) or 2 nd

(mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample.

Figure 29 DSP/PCM Mode Audio Interface (mode A, LRP=1)

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Figure 30 DSP/PCM Mode Audio Interface (mode B, LRP=0)

In all modes DACLRC and ADCLRC must always change on the falling edge of BCLK, refer to Figure

26, Figure 27, Figure 28, Figure 29 and Figure 30.

Operating the digital audio interface in DSP mode allows ease of use for supporting the various sample rates and word lengths. The only requirement is that all data is transferred within the correct number of BCLK cycles to suit the chosen word length.

In order for the digital audio interface to offer similar support in the three other modes (Left Justified,

I

2

S and Right Justified), the DACLRC, ADCLRC and BCLK frequencies, continuity and mark-space ratios need more careful consideration.

In Slave mode, DACLRC and ADCLRC inputs are not required to have a 50:50 mark-space ratio.

BCLK input need not be continuous. It is however required that there are sufficient BCLK cycles for each DACLRC/ADCLRC transition to clock the chosen data word length. The non-50:50 requirement on the LRCs is of use in some situations such as with a USB 12MHZ clock. Here simply dividing down a 12MHz clock within the DSP to generate LRCs and BCLK will not generate the appropriate

DACLRC or ADCLRC since they will no longer change on the falling edge of BCLK. For example, with 12MHz/32k fs mode there are 375 MCLK per LRC. In these situations DACLRC/ADCLRC can be made non 50:50.

In Master mode, DACLRC and ADCLRC will be output with a 50:50 mark-space ratio with BCLK output at 64 x base frequency (i.e. 48 kHz).. The exception again is in USB mode where BCLK is always 12MHz. So for example in 12MHz/32k fs mode there are 375 master clocks per DACLRC period. Therefore DACLRC and ADCLRC outputs will have a mark space ratio of 187:188.

The ADC and DAC digital audio interface modes are software configurable as indicated in Table 14.

Note that dynamically changing the software format may result in erroneous operation of the interfaces and is therefore not recommended.

The length of the digital audio data is programmable at 16/20/24 or 32 bits, in I2S or left justified modes only. Refer to the software control table below. The data is signed 2’s complement. Both ADC and DAC are fixed at the same data length. The ADC and DAC digital filters process data using 24 bits. If the ADC is programmed to output 16 or 20 bit data then it strips the LSBs from the 24 bit data.

If the ADC is programmed to output 32 bits then it packs the LSBs with zeros. If the DAC is programmed to receive 16 or 20 bit data, the WM8731/L packs the LSBs with zeros. If the DAC is programmed to receive 32 bit data, then it strips the LSBs.

The DAC outputs can be swapped under software control using LRP and LRSWAP as shown in

Table 15. Stereo samples are normally generated as a Left/Right sampled pair. LRSWAP reverses the order so that a Left sample goes to the right DAC output and a Right sample goes to the left DAC output. LRP swaps the phasing so that a Right/Left sampled pair is expected and preserves the correct channel phase difference.

To accommodate system timing requirements the interpretation of BCLK maybe inverted, this is controlled vias the software shown in Table 15. This is especially appropriate for DSP mode.

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ADCDAT lines are always outputs. They power up and return from standby low.

DACDAT is always an input. It is expected to be set low by the audio interface controller when the

WM8731/L is powered off or in standby.

ADCLRC, DACLRC and BCLK can be either outputs or inputs depending on whether the device is configured as a master or slave. If the device is a master then the DACLRC and BCLK signals are outputs that default low. If the device is a slave then the DACLRC and BCLK are inputs. It is expected that these are set low by the audio interface controller when the WM8731/L is powered off or in standby.

REGISTER

ADDRESS

0000111

Digital Audio

Interface

Format


1:0

3:2

4

5

6

7

FORMAT[1:0]

IWL[1:0]

LRP

LRSWAP

MS

BCLKINV

10

10

0

0

0

0

DESCRIPTION

Audio Data Format Select

11 = DSP Mode, frame sync + 2 data packed words

10 = I

2

S Format, MSB-First left-1 justified

01 = MSB-First, left justified

00 = MSB-First, right justified

Input Audio Data Bit Length Select

11 = 32 bits

10 = 24 bits

01 = 20 bits

00 = 16 bits

DACLRC phase control (in left, right or I

2

S modes)

1 = Right Channel DAC data when

DACLRC high


DACLRC low

(opposite phasing in I

2

S mode) or

DSP mode A/B select (in DSP mode only)

1 = MSB is available on 2nd BCLK rising edge after DACLRC rising edge

0 = MSB is available on 1st BCLK rising edge after DACLRC rising edge

DAC Left Right Clock Swap

1 = Right Channel DAC Data Left

0 = Right Channel DAC Data Right

Master Slave Mode Control

1 = Enable Master Mode

0 = Enable Slave Mode

Bit Clock Invert

1 = Invert BCLK

0 = Don’t invert BCLK

Table 15 Digital Audio Interface Control

Note: If right justified 32 bit mode is selected then the WM8731/L defaults to 24 bits. w


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MASTER AND SLAVE MODE OPERATION

The WM8731/L can be configured as either a master or slave mode device. As a master mode device the WM8731/L controls sequencing of the data and clocks on the digital audio interface. As a slave device the WM8731/L responds with data to the clocks it receives over the digital audio interface. The mode is set with the MS bit of the control register as shown in Table 16.

REGISTER

ADDRESS

0000111

Digital Audio Interface

Format

6


MS

Table 16 Programming Master/Slave Modes

0

DESCRIPTION




As a master mode device the WM8731/L controls the sequencing of data transfer (ADCDAT,

DACDAT) and output of clocks (BCLK, ADCLRC, DACLRC) over the digital audio interface. It uses the timing generated from either its on-board crystal or the MCLK input as the reference for the clock and data transitions. This is illustrated in Figure 31. ADCDAT is always an output from and DACDAT is always an input to the WM8731/L independent of master or slave mode.

BCLK

ADCLRC

WM8731

CODEC

DACLRC

ADCDAT

DACDAT

DSP

ENCODER/

DECODER

Note: ADC and DAC can run at different rates

Figure 31 Master Mode

As a slave device the WM8731/L sequences the data transfer (ADCDAT, DACDAT) over the digital audio interface in response to the external applied clocks (BCLK, ADCLRC, DACLRC). This is illustrated in Figure 32.

BCLK

ADCLRC

WM8731

CODEC

DACLRC

ADCDAT

DACDAT

DSP

ENCODER/

DECODER

Note: The ADC and DAC can run at different rates

Figure 32 Slave Mode

Note that the WM8731/L relies on controlled phase relationships between audio interface BCLK,

DACLRC and the master MCLK or CLKOUT. To avoid any timing hazards, refer to the timing section for detailed information. w PD, Rev 4.8, April 2009

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AUDIO DATA SAMPLING RATES

The WM8731/L provides for two modes of operation (normal and USB) to generate the required DAC and ADC sampling rates. Normal and USB modes are programmed under software control according to the table below.

In Normal mode, the user controls the sample rate by using an appropriate MCLK or crystal frequency and the sample rate control register setting. The WM8731/L can support sample rates from 8ks/s up to 96ks/s.

In USB mode, the user must use a fixed MLCK or crystal frequency of 12MHz to generate sample rates from 8ks/s to 96ks/s. It is called USB mode since the common USB (Universal Serial Bus) clock is at 12MHz and the WM8731/L can be directly used within such systems. WM8731/L can generate all the normal audio sample rates from this one Master Clock frequency, removing the need for different master clocks or PLL circuits.

Uniquely, the WM8731/L offers the user the ability to sample the ADC and DAC at different rates under software control in both Normal and USB modes. This reduces the burden on any controlling

DSP. However, the signal processing in the ADC and DAC over-sampling filters is tightly coupled together in order to minimise power consumption. To this end, only the combinations of sample rates listed in the following sections are supported. Note that these rates supported are anticipated to be the likely combinations used in typical audio systems.


ADDRESS

0001000

Sampling

Control

0 USB/

NORMAL

1

5:2

BOSR

SR[3:0]

0

0000

1 = USB mode (250/272fs)

0 = Normal mode (256/384fs)

Base Over-Sampling Rate

0 = 250fs

1 = 272fs

Normal Mode

96/88.2kHz

0 = 256fs

0 = 128fs

1 = 384fs

1 = 192fs

ADC and DAC sample rate control;

See USB Mode and Normal Mode

Sample Rate sections for operation

Table 17 Sample Rate Control

NORMAL MODE SAMPLE RATES

In normal mode MCLK/crystal oscillator is set up according to the desired sample rates of the ADC and DAC. For ADC or DAC sampling rates of 8, 32, 48 or 96kHz, MCLK frequencies of either

12.288MHz (256fs) or 18.432MHz (384fs) can be used. For ADC or DAC sampling rates of 8, 44.1 or

88.2kHz from MCLK frequencies of either 11.2896MHz (256fs) or 16.9344MHz (384fs) can be used.

Table 18 should be used to set up the device to work with the various sample rate combinations. For example if the user wishes to use the WM8731/L in normal mode with the ADC and DAC sample rates at 48kHz and 48kHz respectively then the device should be programmed with BOSR = 0, SR3

= 0, SR2 = 0, SR1 = 0 and SR0 = 0 with a 12.288MHz MCLK or with BOSR = 1, SR3 = 0, SR2 = 0,

SR1 = 0 and SR0 = 0 with a 18.432MHz MCLK. The ADC and DAC will then operate with a Digital

Filter of type 1, refer to Digital Filter Characteristics section for an explanation of the different filter types. w


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SAMPLING

RATE

ADC DAC

MCLK

FREQUENCY

SAMPLE

RATE

REGISTER SETTINGS

kHz kHz MHz BOSR

48 48

48 8

8 48

8 8

32 32

96 96

44.1 44.1

0 0 0 0

0 0 0 0

0 0 0 1

0 0 0 1

0 0 1 0

0 0 1 0

0 0 1 1

0 0 1 1

0 1 1 0

0 1 1 0

0 1 1 1

0 1 1 1

1 0 0 0

1 0 0 0

44.1 8

8

(Note 1)

8

(Note 1)

(Note 1)

44.1

8

(Note 1)

88.2 88.2

1 0 0 1

1 0 0 1

1 0 1 0

1 0 1 0

1 0 1 1

1 0 1 1

1 1 1 1

1 1 1 1

Table 18 Normal Mode Sample Rate Look-up Table

DIGITAL

FILTER

TYPE

1

1

1

1

1

2

1

1

1

1

2

Notes:

1. 8k not exact, actual = 8.018kHz

2. All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid

The BOSR bit represents the base over-sampling rate. This is the rate that the WM8731/L digital signal processing is carried out at. In Normal mode, with BOSR = 0, the base over-sampling rate is at

256fs, with BOSR = 1, the base over-sampling rate is at 384fs. This can be used to determine the actual audio data rate produced by the ADC and required by the DAC.

Example scenarios are:

1. with a requirement that the ADC data rate is 8kHz and DAC data rate is 48kHz, then choosing

MCLK = 12.288MHz the device is programmed with BOSR = 0 (256fs), SR3 = 0, SR2 = 0, SR1

= 1, SR0 = 0.The ADC output data rate will then be exactly 8kHz (derived from 12.288MHz/256 x1/6) and the DAC expects data at exactly 48kHz (derived from 12.288MHz/256)

2. with a requirement that ADC data rate is 8kHz and DAC data rate is 44.1kHz, then choosing

MCLK = 16.9344MHz the device is programmed with BOSR = 1 (384fs), SR3 = 1, SR2 = 0, SR1

= 1, SR0 = 0. The ADC will no longer output data at exactly 8.000kHz, instead it will be

8.018kHz (derived from 16.9344MHz/384 x 2/11), the DAC still is at exactly 44.1kHz (derived from 16.9344MHz/384). A slight (sub 0.5%) pitch shift will therefore result in the 8kHz audio data and (importantly) the user must ensure that the data across the digital interface is correctly synchronised at the 8.018kHz rate. w PD, Rev 4.8, April 2009

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The exact sample rates achieved are defined by the relationships in Table 19 below.

TARGET

SAMPLING

RATE

BOSR=0

ACTUAL SAMPLING RATE

BOSR=1

MCLK=12.288 MCLK=11.2896 MCLK=18.432 MCLK=16.9344

8 8 8.018 8 8.018

(12.288MHz/256) x 1/6 (11.2896MHz/256) x 2/11 (18.432MHz/384) x 1/6 (16.9344MHz/384) x 2/11

32

44.1

(12.288MHz/256) x 2/3

not available

11.2896MHz/256

48

88.2

12.288MHz/256

not available

(11.2896MHz/256) x 2

96

(12.288MHz/256) x 2

Table 19 Normal Mode Actual Sample Rates

(18.432MHz/384) x 2/3

18.432MHz/384

(18.432MHz/384) x 2

16.9344MHz /384

(16.9344MHz /384) x 2

128/192fs NORMAL MODE

The Normal Mode sample rates are designed for standard 256fs and 384fs MCLK rates. However the

WM8731/L is also capable of being clocked from a 128 or 192fs MCLK for application over limited sampling rates as shown in the table below.

SAMPLING

RATE

ADC DAC

MCLK

FREQUENCY

SAMPLE

RATE



48 48

44.1 44.1

6.144 0 0 1 1 1

9.216 1 0 1 1 1

5.6448 0 1 1 1 1

8.4672 1 1 1 1 1

DIGITAL

FILTER

TYPE

2

2

Table 20 128fs Normal Mode Sample Rate Look-up Table

512/768fs NORMAL MODE

512 fs and 768 fs MCLK rates can be accommodated by using the CLKIDIV2 bit (Register 8, bit 6).

The core clock to the DSP will be divided by 2 so an external 512/768 fs MCLK will become 256/384 fs internally and the device otherwise operates as in Table 18 but with MCLK at twice the specified rate. See Table 17 for software control. w


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USB MODE SAMPLE RATES

In USB mode the MCLK/crystal oscillator input is 12MHz only.

SAMPLING

RATE

ADC DAC

MCLK

FREQUENCY

SAMPLE

RATE



DIGITAL

FILTER

TYPE

44.1

(Note 2)

44.1

(Note 2)

12.000 1 1 0 0 0 1

48 8 12.000 0 0 0 0 1 0

44.1 8

12.000 1 1 0 0 1 1

(Note 2) (Note 1)

8 48 12.000 0 0 0 1 0 0

8 44.1 12.000 1 1 0 1 0 1

((Note 1) (Note 2)

8 8 12.000 0 0 0 1 1 0

8

(Note 1)

8

(Note 1)

12.000 1 1 0 1 1 1 w

88.2

(Note 3)

88.2

(Note 3)

12.000 1 1 1 1 1 2

Table 21 USB Mode Sample Rate Look-up Table

Notes:

1. 8k not exact, actual = 8.021kHz

2. 44.1k not exact, actual = 44.118kHz

3. 88.2k not exact, actual = 88.235kHz

4. All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid

The table above can be used to set up the device to work with various sample rate combinations. For example if the user wishes to use the WM8731/L in USB mode with the ADC and DAC sample rates at 48kHz and 48kHz respectively then the device should be programmed with BOSR = 0, SR3 = 0,

SR2 = 0, SR1 = 0 and SR0 = 0. The ADC and DAC will then operate with a Digital Filter of type 0, refer to Digital Filter Characteristics section for an explanation of the different filter types.

The BOSR bit represents the base over-sampling rate. This is the rate that the WM8731/L digital signal processing is carried out at and the sampling rate will always be a sub-multiple of this. In USB mode, with BOSR = 0, the base over-sampling rate is defined at 250fs, with BOSR = 1, the base over-sampling rate is defined at 272fs. This can be used to determine the actual audio sampling rate produced by the ADC and required by the DAC.

Example scenarios are, :-

1. with a requirement that the ADC data sampling rate is 8kHz and DAC data sampling rate is

48kHz the device is programmed with BOSR = 0 (250fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 =

0.The ADC will then be exactly 8kHz ( derived from 12MHz/250 x 1/6 ) and the DAC expects data at exactly 48kHz ( derived from 12MHz/250 ).

2. with a requirement that ADC data rate is 8kHz and DAC data rate is 44.1kHz the device is programmed with BOSR = 1 (272fs), SR3 = 1, SR2 = 0, SR1 = 1, SR0 = 0. The ADC will not output data at exactly 8kHz, instead it will be 8.021kHz ( derived from 12MHz/272 x 2/11 ) and the DAC at 44.118kHz ( derived from 12MHz/272 ). A slight (sub 0.5%) pitch shift will therefore results in the 8kHz and 44.1kHz audio data and (more importantly) the user must ensure that the data across the digital interface is correctly synchronised at the 8.021kHz and 44.117kHz rates.


44

WM8731 / WM8731L

Production Data

The exact sample rates supported for all combinations are defined by the relationships in Table 22 below.

TARGET

SAMPLING

RATE

ACTUAL SAMPLING RATE

BOSR=0

( 250fs) kHz kHz

BOSR=1

(272fs) kHz

8 8 8.021

32

12MHz/(250 x 48/8)

32

12MHz/(272 x 11/2)

not available

44.1

12MHz/(250 x 48/32)

not available

48

44.117

12MHz/272

not available

88.2

48

12MHz/250

not available

96 96

12MHz/125

88.235

12MHz/136

not available

Table 22 USB Mode Actual Sample Rates

ACTIVATING DSP AND DIGITAL AUDIO INTERFACE

To prevent any communication problems from arising across the Digital Audio Interface the Audio

Interface is disabled (tristate with weak 100k pulldown). Once the Audio Interface and the Sampling

Control has been programmed it is activated by setting the ACTIVE bit under Software Control.

REGISTER

ADDRESS

0001001

Active Control

BIT LABEL DEFAULT DESCRIPTION

1 = Active

0 = Inactive

Table 23 Activating DSP and Digital Audio Interface

It is recommended that between changing any content of Digital Audio Interface or Sampling Control

Register that the active bit is reset then set.

SOFTWARE CONTROL INTERFACE

The software control interface may be operated using either a 3-wire (SPI-compatible) or 2-wire MPU interface. Selection of interface format is achieved by setting the state of the MODE pin.

In 3-wire mode, SDIN is used for the program data, SCLK is used to clock in the program data and

CSB is used to latch in the program data. In 2-wire mode, SDIN is used for serial data and SCLK is used for the serial clock. In 2-wire mode, the state of CSB pin allows the user to select one of two addresses.

SELECTION OF SERIAL CONTROL MODE

The serial control interface may be selected to operate in either 2 or 3-wire modes. This is achieved by setting the state of the MODE pin.

MODE INTERFACE

FORMAT

Table 24 Control Interface Mode Selection

w


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WM8731 / WM8731L

Production Data

3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE

The WM8731/L can be controlled using a 3-wire serial interface. SDIN is used for the program data,

SCLK is used to clock in the program data and CSB is use to latch in the program data. The 3-wire interface protocol is shown in Figure 33.

CSB

SCLK

SDIN B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

Figure 33 3-Wire Serial Interface

Notes:

1. B[15:9] are Control Address Bits

2. B[8:0] are Control Data Bits

3. CSB is edge sensitive not level sensitive. The data is latched on the rising edge of CSB.

2-WIRE SERIAL CONTROL MODE

The WM8731/L supports a 2-wire MPU serial interface. The device operates as a slave device only.

The WM8731/L has one of two slave addresses that are selected by setting the state of pin 15,

(CSB).

SDIN

R ADDR R/W

ACK DATA B15-8 ACK

DATA B7-0

ACK

SCLK

START STOP

Figure 34 2-Wire Serial Interface

Notes:

1. B[15:9] are Control Address Bits

2. B[8:0] are Control Data Bits

CSB STATE ADDRESS

0 0011010

1 0011011

Table 25 2-Wire MPU Interface Address Selection

To control the WM8731/L on the 2-wire bus the master control device must initiate a data transfer by establishing a start condition, defined by a high to low transition on SDIN while SCLK remains high.

This indicates that an address and data transfer will follow. All peripherals on the 2-wire bus respond to the start condition and shift in the next eight bits (7-bit address + R/W bit). The transfer is MSB first. The 7-bit address consists of a 6-bit base address + a single programmable bit to select one of two available addresses for this device (see Table 24). If the correct address is received and the

R/W bit is ‘0’, indicating a write, then the WM8731/L will respond by pulling SDIN low on the next clock pulse (ACK). The WM8731/L is a write only device and will only respond to the R/W bit indicating a write. If the address is not recognised the device will return to the idle condition and wait for a new start condition and valid address. w PD, Rev 4.8, April 2009

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WM8731 / WM8731L

Production Data

Once the WM8731/L has acknowledged a correct address, the controller will send eight data bits

(bits B15-B8). WM8731/L will then acknowledge the sent data by pulling SDIN low for one clock pulse. The controller will then send the remaining eight data bits (bits B7-B0) and the WM8731/L will then acknowledge again by pulling SDIN low.

A stop condition is defined when there is a low to high transition on SDIN while SCLK is high. If a start or stop condition is detected out of sequence at any point in the data transfer then the device will jump to the idle condition.

After receiving a complete address and data sequence the WM8731/L returns to the idle state and waits for another start condition. Each write to a register requires the complete sequence of start condition, device address and R/W bit followed by the 16 register address and data bits.

POWER DOWN MODES

The WM8731/L contains power conservation modes in which various circuit blocks may be safely powered down in order to conserve power. This is software programmable as shown in the table below.

REGISTER

ADDRESS

0000110

Power Down

Control

0 LINEINPD 1 Line Input Power Down

1 = Enable Power Down

0 = Disable Power Down

Power Down











7 POWEROFF 1



Power Off Device

1 = Device Power Off

0 = Device Power On

Table 26 Power Conservation Modes Software Control

The power down control can be used to either a) permanently disable functions when not required in certain applications or b) to dynamically power up and down functions depending on the operating mode, e.g.: during playback or record. Please follow the special instructions below if dynamic implementations are being used.

LINEINPD: Simultaneously powers down both the Line Inputs. This can be done dynamically without any audible effects either on the ADC or to the Line Outputs in Bypass mode. This is of use when the device enters Playback, Pause or Stop modes or the Microphone input has been selected. w


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WM8731 / WM8731L

Production Data

MICPD: Simultaneously powers down both the Microphone Input and Microphone Bias. If this is done dynamically, audible pops through the ADC will result. This will only be audible if the Microphone

Input is selected to the ADC at the time. If the state of MICPD is changed then the controlling DSP or microprocessor should switch to select the Line Inputs as input to the ADC (INSEL) before changing

MICPD. This is of use when the device enters Playback, Pause or Stop modes or the Microphone

Input is not selected.

ADCPD: Powers down the ADC and ADC Filters. If this is done dynamically then audible pops will result if any signals were present through the ADC. To overcome this whenever the ADC is to be powered down, either mute the Microphone Input (MUTEIN) or MUTELINEIN, then change ADCPD.

This is of use when the device enters Playback, Pause or Stop modes regardless of whether

Microphone or Line Inputs are selected.

DACPD: Powers down the DAC and DAC Digital Filters. If this is done dynamically then audible pops will result unless the following guidelines are followed. In order to prevent pops, the DAC should first be soft-muted (DACMU), the output should then be de-selected from the line and headphone output

(DACSEL), then the DAC powered down (DACPD). This is of use when the device enters Record,

Pause, Stop or Bypass modes.

OUTPD: Powers down the Line and Headphone outputs. If this is done dynamically then audible pops may result unless the DAC is first soft-muted (DACMU). This is of use when the device enters

Record, Pause or Stop modes.

OSCPD: Powers off the on board crystal oscillator. The MCLK input will function independently of the

Oscillator being powered down.

CLKOUTPD: Powers down the CLOCKOUT pin. This conserves power, reduces digital noise and RF emissions if not required. CLKOUT is tied low when powered down.

The device can be put into a standby mode (STANDBY) by powering down all the audio circuitry under software control as shown in Table 27. If the crystal oscillator and/or CLOKOUT pins are being used to derive the system master clock, these should probably never be powered off in standby.

Provision has been made to independently power off these areas according to Table 27.

DESCRIPTION

0 0 0 1 1 1 1 1 STANDBY, but with Crystal

Oscillator OS and CLKOUT available

0 1 0 1 1 1 1 1 STANDBY, but with Crystal

Oscillator OS available,

CLKOUT not-available

0 1 1 1 1 1 1 1 STANDBY, Crystal oscillator and CLKOUT notavailable.

Table 27 Standby Mode

In STANDBY mode the Control Interface, a small portion of the digital and areas of the analogue circuitry remain active. The active analogue includes the analogue VMID reference so that the analogue line inputs, line outputs and headphone outputs remain biased to VMID. This reduces any audible effects caused by DC glitches when entering or leaving STANDBY mode. w PD, Rev 4.8, April 2009

48

WM8731 / WM8731L

Production Data

The device can be powered off by writing to the POWEROFF bit of the Power Down register. In

POWEROFF mode the Control Interface and a small portion of the digital remain active. The analogue VMID reference is disabled. As in STANDBY mode the crystal oscillator and/or CLKOUT pin can be independently controlled. Refer to Table 28.

DESCRIPTION

1 0 0 X X X X X POWEROFF, but with Crystal

Oscillator OS and CLKOUT available

1 1 0 X X X X X POWEROFF, but with Crystal

Oscillator OS available, CLKOUT not-available

1 1 1 X X X X X POWEROFF, Crystal oscillator and CLKOUT not-available.

Table 28 Poweroff Mode

REGISTER MAP

The complete register map is shown in Table 29. The detailed description can be found in Table 30 and in the relevant text of the device description. There are 11 registers with 16 bits per register (7 bit address + 9 bits of data). These can be controlled using either the 2 wire or 3 wire MPU interface.

REGISTER BIT[8] BIT[7] BIT[6] BIT[5] BIT[4] BIT[3] BIT[2] BIT[1] BIT[0] DEFAULT

R0 (00h)

Left Line In

LRINBOTH LINMUTE 0 0 LINVOL[4:0] 0_1001_0111

RLINBOTH RINMUTE 0 0 RINVOL[4:0]

R1 (01h)

Right Line In

R2 (02h)

Left

Headphone Out

LRHPBOTH LZCEN LHPVOL[6:0]

0_1001_0111

0_0111_1001

RLHPBOTH RZCEN RHPVOL[6:0] 0_0111_1001

R1 (01h)

Right

Headphone Out

R4 (04h)

Analogue Audio

Path Control

R5 (05h)

Digital Audio

Path Control

R6 (06h)

Power Down

Control

R7 (07h)

Digital Audio

Interface Format

R8 (08h)

Sampling

Control

R9 (09h)

Active Control

R15 (0Fh)

Reset

0 BCLKINV MS LRSWAP LRP IWL[1:0]

SR[3:0]

FORMAT[1:0] 0_1001_1111

NORMAL

Table 29 Register Map

w


49

WM8731 / WM8731L

REGISTER

ADDRESS

0000000

Left Line In


Production Data

DESCRIPTION

0000001

Right Line In

0000010

Left Headphone

Out

4:0 LINVOL[4:0] 10111

( 0dB )

7

8

LINMUTE

LRINBOTH

4:0 RINVOL[4:0] 10111

( 0dB )

7

8

RINMUTE

RLINBOTH

6:0 LHPVOL

7

8

[6:0]

LZCEN

LRHPBOTH

1

0

1

0

1111001

( 0dB )

0

0

Left Channel Line Input Volume

Control

11111 = +12dB . . 1.5dB steps down to 00000 = -34.5dB

Left Channel Line Input Mute to ADC

1 = Enable Mute

0 = Disable Mute

Left to Right Channel Line Input



LINVOL[4:0] and LINMUTE to

RINVOL[4:0] and RINMUTE


Right Channel Line Input Volume

Control

11111 = +12dB . .1.5dB steps down to 00000 = -34.5dB

Right Channel Line Input Mute to

ADC

1 = Enable Mute

0 = Disable Mute

Right to Left Channel Line Input



RINVOL[4:0] and RINMUTE to

LINVOL[4:0] and LINMUTE


Left Channel Headphone Output

Volume Control

1111111 = +6dB


0110000 = -73dB

0000000 to 0101111 = MUTE

Left Channel Zero Cross detect

Enable

1 = Enable

0 = Disable

Left to Right Channel Headphone


Load Control


LHPVOL[6:0] and LZCEN to

RHPVOL[6:0] and RZCEN

0 = Disable Simultaneous Load w PD, Rev 4.8, April 2009

50

WM8731 / WM8731L

Production Data

REGISTER

ADDRESS

0000011

Right

Headphone Out


6:0 RHPVOL

[6:0]

1111001

( 0dB )

0000100

Analogue Audio

Path Control

7

8

0

1

2

3

RZCEN

RLHPBOTH

MICBOOST

MUTEMIC

INSEL

BYPASS

0

0

0

1

0

1

DESCRIPTION

Right Channel Headphone Output

Volume Control

1111111 = +6dB


0110000 = -73dB

0000000 to 0101111 = MUTE

Right Channel Zero Cross detect

Enable

1 = Enable

0 = Disable

Right to Left Channel Headphone


Load Control


RHPVOL[6:0] and RZCEN to

LHPVOL[6:0] and LZCEN


Microphone Input Level Boost

1 = Enable Boost

0 = Disable Boost

Mic Input Mute to ADC

1 = Enable Mute

0 = Disable Mute

Microphone/Line Input Select to ADC

1 = Microphone Input Select to ADC

0 = Line Input Select to ADC

Bypass Switch

1 = Enable Bypass

0 = Disable Bypass

4 DACSEL 0

5 SIDETONE 0

1 =Select DAC

0 = Don’t select DAC

Side Tone Switch

1 = Enable Side Tone


7:6 SIDEATT[1:0] 00

11 = -15dB

10 = -12dB

01 = -9dB

00 = -6dB w


51

WM8731 / WM8731L

REGISTER

ADDRESS

0000101

Digital Audio

Path Control

0000110

Power Down

Control

Production Data

DESCRIPTION BIT LABEL DEFAULT

0 ADCHPD 0

2:1

3

4

0

1

DEEMP[1:0]

DACMU

HPOR

LINEINPD

MICPD

00

1

0

1

1

ADC High Pass Filter Enable

1 = Disable High Pass Filter

0 = Enable High Pass Filter

De-emphasis Control

11 = 48kHz

10 = 44.1kHz

01 = 32kHz

00 = Disable

DAC Soft Mute Control

1 = Enable soft mute

0 = Disable soft mute

Store dc offset when High Pass Filter disabled

1 = store offset

0 = clear offset

Line Input Power Down



Microphone Input an Bias Power

Down



2 ADCPD 1



3 DACPD 1



4 OUTPD 1

5 OSCPD 0



Oscillator Power Down



6 CLKOUTPD 0

7 POWEROFF 1



POWEROFF mode

1 = Enable POWEROFF

0 = Disable POWEROFF w PD, Rev 4.8, April 2009

52

WM8731 / WM8731L

REGISTER

ADDRESS

0000111

Digital Audio

Interface

Format

0001000

Sampling

Control

Production Data

DESCRIPTION BIT LABEL DEFAULT

1:0 FORMAT[1:0] 10

3:2

4

5

6

7

IWL[1:0]

LRP

LRSWAP

MS

BCLKINV

10

0

0

0

0

Audio Data Format Select

11 = DSP Mode, frame sync + 2 data packed words

10 = I

2

S Format, MSB-First left-1 justified

01 = MSB-First, left justified

00 = MSB-First, right justified

Input Audio Data Bit Length Select

11 = 32 bits

10 = 24 bits

01 = 20 bits

00 = 16 bits

DACLRC phase control (in left, right or I

2

S modes)


DACLRC high


DACLRC low

(opposite phasing in I

2

S mode) or

DSP mode A/B select (in DSP mode only)

1 = MSB is available on 2nd BCLK rising edge after DACLRC rising edge

0 = MSB is available on 1st BCLK rising edge after DACLRC rising edge

DAC Left Right Clock Swap

1 = Right Channel DAC Data Left

0 = Right Channel DAC Data Right




Bit Clock Invert

1 = Invert BCLK

0 = Don’t invert BCLK

0 USB/

NORMAL

1 BOSR

5:2

6

SR[3:0]

CLKIDIV2

0

0000

0

1 = USB mode (250/272fs)

0 = Normal mode (256/384fs)

Base Over-Sampling Rate

USB Mode

0 = 250fs

1 = 272fs

Normal Mode

0 = 256fs

1 = 384fs

ADC and DAC sample rate control;

See USB Mode and Normal Mode

Sample Rate sections for operation

Core Clock divider select

1 = Core Clock is MCLK divided by 2

0 = Core Clock is MCLK

7 CLKODIV2 0

1 = CLOCKOUT is Core Clock divided by 2

0 = CLOCKOUT is Core Clock w


53

WM8731 / WM8731L

REGISTER

ADDRESS

0001001

Active Control


0 ACTIVE 0

Production Data

DESCRIPTION

1 = Active

0 = Inactive

0001111

Reset Register

8:0 RESET

Writing 00000000 to register resets device

Table 30 Register Map Description

DIGITAL FILTER CHARACTERISTICS

The ADC and DAC employ different digital filters. There are 4 types of digital filter, called Type 0, 1, 2 and 3. The performance of Types 0 and 1 is listed in the table below, the responses of all filters is shown in the proceeding pages.

ADC Filter Type 0 (USB Mode, 250fs operation)

Passband +/- 0.05dB 0 0.416fs

Passband Ripple

Stopband

Stopband Attenuation

0.584fs f > 0.584fs

ADC Filter Type 1 (USB mode, 272fs or Normal mode operation)

-60

+/- dB

Passband +/- 0.05dB 0 0.4535fs

Passband Ripple

Stopband


High Pass Filter Corner

Frequency

+/-

0.5465fs f > 0.5465fs -60 dB

-0.5dB

Hz

10.4

-0.1dB

DAC Filter Type 0 (USB mode, 250fs operation)

Passband +/- 0.03dB

21.6

Passband Ripple

Stopband


0.584fs f > 0.584fs

DAC Filter Type 1 (USB mode, 272fs or Normal mode operation)

-50 dB dB

Passband

+/- 0.03dB

0

0

0.416fs

0.4535fs

Passband Ripple

Stopband


Table 31 Digital Filter Characteristics

+/-

0.5465fs f > 0.5465fs -50 dB w PD, Rev 4.8, April 2009

54

WM8731 / WM8731L

DAC FILTERS ADC FILTERS

0 11/FS 0 12/FS

1 18/FS 1 20/FS

2 5/FS 2 3/FS

3 5/FS 3 6/FS

Table 32 ADC/DAC Digital Filters Group Delay

Production Data

TERMINOLOGY

1. Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band)

2. Pass-band Ripple – any variation of the frequency response in the pass-band region w


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WM8731 / WM8731L

Production Data

DAC FILTER RESPONSES

0

-20

-40

-60

0.04

0.03

0.02

0.01

0

-0.01

-80

-0.02

-0.03

-100

0 0.5

1 1.5

Frequency (Fs)

2 2.5

3

Figure 35 DAC Digital Filter Frequency Response –Type 0

-0.04

0 0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Frequency (Fs)

Figure 36 DAC Digital Filter Ripple –Type 0

0

-20

-40

-60

0.01

0

-0.01

0.04

0.03

0.02

-80

-0.02

-0.03

-100

0 0.5

1 1.5

Frequency (Fs)

2 2.5

3


-0.04

0 0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Frequency (Fs)


0

-20

0.02

0.01

0

-0.01

-40

-60

-0.02

-0.03

-0.04

-80

-0.05

-100

0 0.5

1 1.5

Frequency (Fs)

2 2.5

3


-0.06

0 0.05

0.1

0.15

Frequency (Fs)


0.2

0.25


56

WM8731 / WM8731L

0

0.05

-20

0

-0.05

-40

-60

-0.1

-0.15

-80

-0.2

-100

0 0.5

1 1.5

Frequency (Fs)

2 2.5

3


-0.25

0 0.05

0.1

0.15

Frequency (Fs)


0.2

Production Data

0.25

ADC FILTER RESPONSES

0

-20

-40

-60

-80

0.02

0.01

0

-0.01

-0.02

-0.03

-0.04

-0.05

-100

0 0.5

1 1.5

Frequency (Fs)

2 2.5

3

Figure 43 ADC Digital Filter Frequency Response –Type 0

-0.06

0 0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Frequency (Fs)

Figure 44 ADC Digital Filter Ripple –Type 0

0

-20

-40

-60

0.02

0.01

0

-0.01

-0.02

-0.03

-80

-0.04

-0.05

-100

0 0.5

1 1.5

Frequency (Fs)

2 2.5

3


-0.06

0 0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Frequency (Fs)


w


57

WM8731 / WM8731L

Production Data

0

-20

-40

-60

-0.01

-0.02

-0.03

0.02

0.01

0

-80

-0.04

-0.05

-100

0 0.5

1 1.5

Frequency (Fs)

2 2.5

3


-0.06

0 0.05

0.1

0.15

Frequency (Fs)


0.2

0.25

0

-20

0.02

0.01

0

-40

-60

-0.01

-0.02

-0.03

-0.04

-80

-0.05

-100

0 0.5

1 1.5

Frequency (Fs)

2 2.5

3


-0.06

0 0.05

0.1

0.15

Frequency (Fs)


0.2

0.25

ADC HIGH PASS FILTER

The WM8731/L has a selectable digital high pass filter to remove DC offsets. The filter response is characterised by the following polynomial.

H(z) = 1 – z

-1

1 – 0.9995 z

-1 w PD, Rev 4.8, April 2009

58

WM8731 / WM8731L

DIGITAL DE-EMPHASIS CHARACTERISTICS

0 0.4

-2

0.3

0.2

Production Data

-4

-6

0.1

0

-0.1

-0.2

-8

-0.3

-10

0 2000 4000 6000 8000 10000 12000 14000 16000

Frequency (Fs)

Figure 51 De-Emphasis Frequency Response (32kHz)

-0.4

0 2000 4000 6000 8000 10000 12000 14000 16000

Frequency (Fs)

Figure 52 De-Emphasis Error (32kHz)

0

-2

-4

-6

-8

0.4

0.3

0.2

0.1

0

-0.1

-0.2

-0.3

-10

0 5000 10000

Frequency (Fs)

15000 20000

Figure 53 De-Emphasis Frequency Response (44.1kHz)

-0.4

0 5000 10000

Frequency (Fs)

15000

Figure 54 De-Emphasis Error (44.1kHz)

0

-2

-4

-6

-8

-10

0 5000 10000 15000

Frequency (Fs)

20000

Figure 55 De-Emphasis Frequency Response (48kHz)

0.4

0.3

0.2

0.1

0

-0.1

-0.2

-0.3

-0.4

0 5000 10000 15000

Frequency (Fs)

Figure 56 De-Emphasis Error (48kHz)

20000

20000 w


59

WM8731 / WM8731L

APPLICATIONS INFORMATION

RECOMMENDED EXTERNAL COMPONENTS

Production Data

Figure 57 External Components Diagram


60

WM8731 / WM8731L

Production Data

MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS

To minimise any pop or click noise when the system is powered up or down, the following procedures are recommended.

POWER UP SEQUENCE

•

Switch on power supplies. By default the WM8731 is in Standby Mode, the DAC is digitally muted and the Audio Interface and Outputs are all OFF.

•

Set all required bits in the Power Down register (0Ch) to ‘0’; EXCEPT the OUTPD bit, this should be set to ‘1’ (Default).

•

Set required values in all other registers except 12h (Active).

•

Set the ‘Active’ bit in register 12h.

•

The last write of the sequence should be setting OUTPD to ‘0’ (active) in register

0Ch, enabling the DAC signal path, free of any significant power-up noise.

POWER DOWN SEQUENCE

•

Set the OUTPD bit to ‘1’ (power down).

•

Remove the WM8731 supplies. w


61

WM8731 / WM8731L

PACKAGE DIMENSIONS - SSOP

DS: 28 PIN SSOP (10.2 x 5.3 x 1.75 mm) b e

28

15

Production Data

DM007.E

E1 E

GAUGE

PLANE

Θ

1

D

14

A A2

A1

-C-

0.10 C

SEATING PLANE

Symbols

D e

E

A

A

1

A

2 b c

E

1

L

L

1

θ

MIN

-----

0.05

1.65

0.22

0.09

9.90

7.40

5.00

0.55

0 o

Dimensions

(mm)

NOM

-----

-----

1.75

0.30

-----

10.20

0.65 BSC

7.80

5.30

0.75

1.25 REF

4 o

MAX

2.0

0.25

1.85

0.38

0.25

10.50

8.20

5.60

0.95

8 o

REF:

JEDEC.95, MO-150

NOTES:

A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.

B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.

C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.

D. MEETS JEDEC.95 MO-150, VARIATION = AH. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.

c

L

L

1

0.25


62

WM8731 / WM8731L

PACKAGE DIMENSIONS - QFN

FL: 28 PIN QFN PLASTIC PACKAGE 5

X

5

X

0.9 mm BODY, 0.50 mm LEAD PITCH

SEE DETAIL A

CORNER

TIE BAR

5

22

D2

B

D2/2

27 28

INDEX AREA

(D/2 X E/2)

A

21

EXPOSED

GROUND

PADDLE

6

L

1

2

E2/2

A

E2

D

DM023.G

E

(A3)

1

15 7

SEE DETAIL B

14 13 e B

BOTTOM VIEW

8 b ccc

M

C A B

A

ccc C

0.08

C

C

SEATING PLANE

SIDE VIEW

A1

DETAIL B

2 X

2 X aaa C aaa C

TOP VIEW

DETAIL A

bbb

M

C

1

A B

28x b

EXPOSED

GROUND

PADDLE

0.

566 m m

R

CORNER

TIE BAR

5

0.1

5

L1

0.3

8m m

1

0.210mm

Symbols

D

D2

E

E2

A

A1

A3 b e

L

L1

R

K aaa bbb ccc

REF:

MIN

0.85

0

0.18

3.2

3.2

0.35

Dimensions (mm)

NOM MAX

0.90

0.02

1.00

0.05

0.2 REF

0.23

5.00 BSC

3.3

0.30

3.4

5.00 BSC

3.3

0.5 BSC

0.4

3.4

0.45

0.1

NOTE

1

2

2

1 b(min)/2

0.20

Tolerances of Form and Position

0.15

0.10

0.10

JEDEC, MO-220, VARIATION VHHD-1

NOTES:

1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. DIMENSION L1 REPRESENTS TERMINAL PULL BACK FROM

PACKAGE SIDE WALL. MAXIMUM OF 0.1mm IS ACCEPTABLE. WHERE TERMINAL PULL BACK EXISTS, ONLY UPPER HALF OF LEAD IS VISIBLE ON PACKAGE SIDE WALL DUE TO HALF

ETCHING OF LEADFRAME.

2. FALLS WITHIN JEDEC, MO-220 WITH THE EXCEPTION OF D2, E2:

D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION

3. ALL DIMENSIONS ARE IN MILLIMETRES

4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.

5. SHAPE AND SIZE OF CORNER TIE BAR MAY VARY WITH PACKAGE TERMINAL COUNT. CORNER TIE BAR IS CONNECTED TO EXPOSED PAD INTERNALLY

6. REFER TO APPLICATION NOTE WAN_0118 FOR FURTHER INFORMATION REGARDING PCB FOOTPRINTS AND QFN PACKAGE SOLDERING.

Production Data w


63

WM8731 / WM8731L

Production Data

IMPORTANT NOTICE

Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement.

Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice. Customers should therefore obtain the latest version of relevant information from Wolfson to verify that the information is current.

Testing and other quality control techniques are utilised to the extent Wolfson deems necessary to support its warranty.

Specific testing of all parameters of each device is not necessarily performed unless required by law or regulation.

In order to minimise risks associated with customer applications, the customer must use adequate design and operating safeguards to minimise inherent or procedural hazards. Wolfson is not liable for applications assistance or customer product design. The customer is solely responsible for its selection and use of Wolfson products. Wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a Wolfson product.

Wolfson’s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to result in personal injury, death or severe property or environmental damage.

Any use of products by the customer for such purposes is at the customer’s own risk.

Wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of Wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. Any provision or publication of any third party’s products or services does not constitute

Wolfson’s approval, licence, warranty or endorsement thereof. Any third party trade marks contained in this document belong to the respective third party owner.

Reproduction of information from Wolfson datasheets is permissible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other notices (including this notice) and conditions. Wolfson is not liable for any unauthorised alteration of such information or for any reliance placed thereon.

Any representations made, warranties given, and/or liabilities accepted by any person which differ from those contained in this datasheet or in Wolfson’s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person’s own risk. Wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person.

ADDRESS:

Wolfson Microelectronics plc

Westfield House

26 Westfield Road

Edinburgh

EH11 2QB

United Kingdom

Tel :: +44 (0)131 272 7000

Fax :: +44 (0)131 272 7001

Email :: [email protected] w PD, Rev 4.8, April 2009

64

datasheet for WM8731SEDS/V by Wolfson Micro

Portable Internet Audio CODEC with Headphone Driver and Programmable Sample Rates

DIGITAL AUDIO INTERFACE – MASTER MODE

DIGITAL AUDIO INTERFACE – SLAVE MODE

MPU INTERFACE TIMING

INTRODUCTION

AUDIO SIGNAL PATH

R2

LINEOUT

C1

R1

AGND

AGND

HPOUT

C1

R1

AGND

AGND

DEVICE OPERATION

AUDIO DATA SAMPLING RATES

ACTIVATING DSP AND DIGITAL AUDIO INTERFACE

SOFTWARE CONTROL INTERFACE

POWER DOWN MODES

REGISTER MAP

TERMINOLOGY

ADC HIGH PASS FILTER

RECOMMENDED EXTERNAL COMPONENTS

MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS

ADDRESS:

Related manuals

Table of contents

datasheet for WM8731SEDS/V by Wolfson Micro

Portable Internet Audio CODEC with Headphone Driver and Programmable Sample Rates

DIGITAL AUDIO INTERFACE – MASTER MODE

DIGITAL AUDIO INTERFACE – SLAVE MODE

MPU INTERFACE TIMING

INTRODUCTION

AUDIO SIGNAL PATH

R2

LINEOUT

C1

R1

AGND

AGND

HPOUT

C1

R1

AGND

AGND

DEVICE OPERATION

AUDIO DATA SAMPLING RATES

ACTIVATING DSP AND DIGITAL AUDIO INTERFACE

SOFTWARE CONTROL INTERFACE

POWER DOWN MODES

REGISTER MAP

TERMINOLOGY

ADC HIGH PASS FILTER

RECOMMENDED EXTERNAL COMPONENTS

MINIMISING POP NOISE AT THE ANALOGUE OUTPUTS

ADDRESS:

Related manuals

Cirrus Logic

WM8731

Cirrus Logic

WM8988

Table of contents